WO2022222498A1 - 基于忆阻器阵列的数据处理方法、电子装置 - Google Patents

基于忆阻器阵列的数据处理方法、电子装置 Download PDF

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Publication number
WO2022222498A1
WO2022222498A1 PCT/CN2021/137845 CN2021137845W WO2022222498A1 WO 2022222498 A1 WO2022222498 A1 WO 2022222498A1 CN 2021137845 W CN2021137845 W CN 2021137845W WO 2022222498 A1 WO2022222498 A1 WO 2022222498A1
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memristor
array
convolution
row
sub
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PCT/CN2021/137845
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English (en)
French (fr)
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吴华强
刘正午
唐建石
高滨
钱鹤
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清华大学
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
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    • G06N3/09—Supervised learning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present disclosure relate to a data processing method and electronic device based on a memristor array.
  • Convolution processing is a commonly used linear operation, which is widely used in the field of signal processing, image processing, neural network and so on.
  • the convolution result obtained by convolution of two objects indicates how one object is modified by the other. For example, in the field of signal processing, convolution can be used to filter the signal.
  • At least one embodiment of the present disclosure provides a data processing method based on a memristor array, the memristor array comprising a plurality of memristor cells arranged in an array and configured to perform a multiply-sum operation, the method comprising: Acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to the convolution parameter matrix of the convolution processing into the memristor array, wherein the convolution parameter matrix is the first matrix and includes a plurality of parameter elements arranged in an array, the plurality of parameter elements are correspondingly mapped to different plurality of memristor sub-arrays in the memristor array multiple times in the form of the first matrix, respectively, And the plurality of memristor sub-arrays do not overlap in the row direction and the column direction of the memristor array; the plurality of first analog signals are respectively input into the set multi-units of the memristor array.
  • acquiring the plurality of first analog signals includes: acquiring a plurality of initial digital signals; A digital-to-analog conversion process is performed to obtain the plurality of first analog signals respectively.
  • a data processing method based on a memristor array each memristor sub-array corresponds to the first matrix, and different memristor sub-arrays respectively correspond to
  • the plurality of parameter elements are correspondingly mapped to different plurality of memristor sub-arrays in the memristor array for multiple times in the form of the first matrix, including: Among the plurality of column signal input ends, the object column groups that need to be subjected to the convolution processing are sequentially selected, wherein each object column group includes at least one column signal input end; for each selected object column group, the The plurality of parameter elements are correspondingly mapped to the object memristor sub-array in the form of the first matrix, wherein the object memristor sub-array is one of the plurality of memristor sub-arrays corresponding to the The memristor subarray of the selected object column group.
  • each memristor sub-array includes a plurality of target memristor cells, and for each selected object column group, the The plurality of parameter elements are correspondingly mapped to the object memristor sub-array in the form of the first matrix, including: mapping the parameter elements of the same row in the first matrix to the object memristor respectively.
  • the target memristor cells in the same row in the resistor sub-array; the parameter elements in the same column in the first matrix are respectively mapped to the target memristor cells in the same column in the object memristor sub-array.
  • a data processing method based on a memristor array each row of the convolution parameter matrix includes Q parameter elements, and each memristor unit includes at least one memristor , each memristor can be set to an initial state, mapping the parameter elements of the same row of the first matrix to the target memristor cells of the same row in the object memristor subarray, including: for the volume Product each row of parameter elements of the parameter matrix, select Q target memristor cells in a row of memristor cells in the memristor array corresponding to the object memristor sub-array to correspond one-to-one to the Q parameter elements, and then set the memristors in the memristor units in the row of memristor units except the Q target memristor units as the initial state, where Q is a positive value greater than 1 Integer.
  • Q is selected in a row of memristor cells in the memristor array corresponding to the object memristor sub-array.
  • the target memristor units correspond to the Q parameter elements one-to-one, including: according to the value of each parameter element in the Q parameter elements, the selected Q target memristor units included in the The memristor as a whole is set to a conductive state available for calculation and has a conductance value corresponding to the numerical value.
  • a method for data processing based on a memristor array is provided. From the plurality of column signal input terminals, sequentially selecting an object column group to be subjected to the convolution processing includes: According to the translation step size of the convolution processing, from the plurality of column signal input terminals, the target column group to be subjected to the convolution processing is sequentially selected.
  • the convolution parameter matrix is a first matrix arranged in 2*P rows and Q columns, and the convolution parameter matrix It includes a first sub-convolution parameter matrix with P rows and Q columns and a corresponding second sub-convolution parameter matrix with P rows and Q columns.
  • the first sub-convolution parameter matrix corresponds to the second sub-convolution parameter matrix.
  • the parameter elements at the row and column positions collectively represent one parameter element for performing the convolution process, wherein P is a positive integer greater than or equal to 1, and Q is a positive integer greater than 1.
  • the first sub-convolution parameter matrix includes P rows of first parameter elements
  • the second sub-convolution parameter matrix includes The second parameter element of row P
  • the first parameter element of row P is in one-to-one correspondence with the row and column positions of the second parameter element of row P.
  • a plurality of second analog signals after convolution processing including: for each memristor sub-array, determining at least one group of rows to be processed, wherein each group of rows to be processed includes a row of targets corresponding to a row of first parameter elements A memristor unit, and a row of target memristor units corresponding to a row of the second parameter elements of the row of the first parameter elements; for the two rows of target memristor units included in each group of rows to be processed, corresponding to The current signals of the two row signal output terminals are subjected to current preprocessing to obtain the second analog signal corresponding to each group of rows to be processed.
  • At least one embodiment of the present disclosure provides a data processing method based on a memristor array
  • the memristor array includes a first memristor array and a second memristor array
  • the convolution parameter matrix Including a first sub-convolution parameter matrix and a second sub-convolution parameter matrix, the first sub-convolution parameter matrix and the second sub-convolution parameter matrix are in the form of the first matrix, and the first sub-convolution parameter matrix is in the form of the first matrix.
  • the convolution parameter matrix is correspondingly mapped to different multiple memristor sub-arrays in the first memristor array according to the form of the first matrix
  • the second sub-convolution parameter matrix is correspondingly according to The form of the first matrix is mapped multiple times to different multiple memristor sub-arrays in the second memristor array.
  • a data processing method based on a memristor array is provided, a plurality of row signal output ends of the memristor array are respectively obtained after performing the convolution processing.
  • Two analog signals including: performing current preprocessing on the current signal of each row signal output terminal in the first memristor array and the current signal at the corresponding row signal output terminal in the second memristor array to obtain the plurality of second analog signals.
  • the current preprocessing is current subtraction processing or current addition processing.
  • At least one embodiment of the present disclosure provides a data processing method based on a memristor array, further comprising: performing analog-to-digital conversion processing on the plurality of second analog signals, so as to convert the plurality of second analog signals respectively are multiple digital signals for subsequent processing.
  • the first analog signal is an analog voltage signal
  • the second analog signal is an analog current signal
  • At least one embodiment of the present disclosure provides an electronic device, including: a memristor array configured to perform a multiplication and sum operation; a signal acquisition device configured to acquire a plurality of first analog signals; and a control driving circuit, wherein the control The drive circuit is configured to perform the steps of setting the memristor array, and writing data corresponding to a convolution parameter matrix of convolution processing into the memristor array, wherein the convolution parameter matrix is a first matrix and includes a plurality of parameter elements arranged in an array, the plurality of parameter elements are correspondingly mapped to different plurality of memristor sub-arrays in the memristor array multiple times in the form of the first matrix, respectively, And the plurality of memristor sub-arrays do not overlap in the row direction and the column direction of the memristor array; the plurality of first analog signals are respectively input into the set multi-units of the memristor array.
  • an electronic device includes a digital signal acquisition circuit and a digital-to-analog conversion circuit, the digital signal acquisition circuit is configured to acquire a plurality of initial digital signals; the digital signal acquisition circuit is configured to acquire a plurality of initial digital signals; The analog-to-analog conversion circuit is configured to perform digital-to-analog conversion processing on the plurality of initial digital signals to obtain the plurality of first analog signals respectively.
  • an electronic device wherein the control driving circuit includes: a source line driving circuit configured to detect the plurality of second analog signals and perform execution on the memristor array an initialization operation; a word line driver circuit configured to apply a turn-on signal to a plurality of signal control terminals of the memristor array and to perform an initialization operation on the memristor array; and a bit line driver circuit configured to perform an initialization operation on the plurality of memristor arrays
  • Each column signal input terminal applies an input signal and performs an initialization operation on the memristor array, wherein the input signal at least includes the plurality of first analog signals.
  • At least one embodiment of the present disclosure provides an electronic device further comprising a data output circuit, wherein the data output circuit is configured to convert the plurality of second analog signals into digital signals, so as to convert the plurality of second analog signals into digital signals.
  • the analog signals are respectively converted into a plurality of digital signals for subsequent processing.
  • Figure 1 shows a schematic structure of a memristor array
  • 2A is a schematic diagram of a memristor cell with a 1T1R structure
  • 2B is a schematic diagram of a memristor cell with a 2T2R structure
  • FIG. 3 is a schematic flowchart of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure
  • 5A is a schematic diagram of a memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure
  • 5B is a schematic diagram of another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of still another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of still another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure
  • FIG. 8 is a schematic processing flow diagram of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure
  • FIG. 9A is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure.
  • FIG. 9C is a schematic diagram of another electronic device provided by at least one embodiment of the present disclosure.
  • the term “including” and variations thereof are open-ended inclusions, ie, "including but not limited to”.
  • the term “based on” is “based at least in part on.”
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment”; the term “some embodiments” means “at least some embodiments”. Relevant definitions of other terms will be given in the description below.
  • Memristors are a new type of micro-nano electronic device whose conductance state can be adjusted by applying external excitation.
  • the working mechanism of memristors is similar to the synapses and neurons in the human brain, so they have a wide range of application prospects in neuromorphic computing.
  • an array composed of such devices can perform multiply-accumulate calculations in parallel, and both storage and calculation occur in each device of the array. Based on this computing architecture, it is possible to realize the integrated computing of storage and computing that does not require a large amount of data transfer, which reduces the time for data transfer, and results in higher energy efficiency, lower power consumption, and smaller area during computing.
  • analog computations such as convolution processing
  • the full analog calculation based on the memristor array requires the use of analog input voltage and analog conductance in the operation.
  • common convolution processing operations such as signal filtering
  • only the results corresponding to one time point can be obtained each time. Therefore, this method requires a large number of data shifts to complete a complete convolution process, resulting in high calculation delay and high power consumption.
  • At least one embodiment of the present disclosure provides a data processing method and electronic device based on a memristor array.
  • the data processing method based on the memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to the convolution parameter matrix of the convolution process into the memristor array, wherein the convolution
  • the parameter matrix is a first matrix and includes a plurality of parameter elements arranged in an array, and the plurality of parameter elements are correspondingly mapped to different multiple memristor sub-arrays in the memristor array in the form of the first matrix, respectively, And the multiple memristor sub-arrays do not overlap in the row direction and the column direction of the memristor array; the multiple first analog signals are respectively input to the multiple column signal input terminals of the memristor array after setting, to control the memristor array.
  • the resistor array is operated to perform convolution processing on a plurality of analog signals, and a plurality of
  • the memristor array-based data processing method maps the convolution parameter matrix to different multiple memristor sub-arrays in the memristor array multiple times, and performs one calculation (or one calculation cycle) to obtain convolution processing. All result values of the operation, which greatly reduces the time required for data shifting, reduces power consumption, and increases computation speed.
  • At least one embodiment of the present disclosure also provides an electronic device corresponding to the data processing method based on the memristor array.
  • FIG. 1 shows a schematic structure of a memristor array.
  • the memristor array is composed of a plurality of memristor cells, and the plurality of memristor cells form an array of m rows and n columns, where m and n are both is a positive integer.
  • Each memristor cell includes a switching element and one or more memristors.
  • WL ⁇ 1>, WL ⁇ 2>...WL ⁇ m> represent the word lines of the first row, the second row...
  • the control electrode (such as the gate of a transistor) is connected to the corresponding word line of the row; BL ⁇ 1>, BL ⁇ 2>...BL ⁇ n> represent the bit lines of the first column, the second column...the nth column, respectively , the memristors in the memristor cells of each column are connected to the corresponding bit lines of the column; SL ⁇ 1>, SL ⁇ 2>...SL ⁇ m> respectively represent the first row, the second row...the mth row.
  • the source lines of the rows, the sources of the transistors in the memristor cells of each row are connected to the corresponding source lines of the row.
  • the above-mentioned memristor array can complete the multiply-accumulate calculation in parallel .
  • the memristor cells in the memristor array of FIG. 1 may have, for example, a 1T1R structure or a 2T2R structure, wherein a memristor cell with a 1T1R structure includes one transistor and one memristor, and a memristor cell with a 2T2R structure includes two transistor and two memristors. It should be noted that the present disclosure does not limit the structure of the memristor unit, and other structural forms of the memristor unit that can realize the multiply-accumulate operation can also be used.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors (eg, MOS field effect transistors) or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • the two electrodes ie, the source electrode and the drain electrode
  • FIG. 2A is a schematic diagram of a memristor cell of 1T1R structure. As shown in FIG. 2A, the memristor cell of 1T1R structure includes a transistor M1 and a memristor R1.
  • the embodiments of the present disclosure do not limit the type of transistors used.
  • the transistor M1 when the transistor M1 is an N-type transistor, its gate is connected to the word line WL.
  • the transistor M1 when the word line WL inputs a high level, the transistor M1 is turned on;
  • One pole may be the source and configured to be connected to the source line SL, for example, the transistor M1 may receive a reset voltage through the source line SL;
  • the second pole of the transistor M1 may be the drain and configured to be connected to the second pole of the memristor R1 ( For example, the negative pole is connected, and the first pole (for example, the positive pole) of the memristor R1 is connected to the bit line BL.
  • the memristor R1 can receive a set voltage through the bit line BL.
  • the transistor M1 is a P-type transistor, its gate is connected to the word line WL.
  • the transistor M1 is turned on; the first electrode of the transistor M1 can be the drain and is configured to be connected to the source line SL.
  • the transistor M1 may receive a reset voltage through the source line SL; the second electrode of the transistor M1 may be a source electrode and is configured to be connected to the second electrode (eg, the negative electrode) of the memristor R1, and the first electrode (eg, the negative electrode) of the memristor R1
  • the positive pole is connected to the bit line BL, for example, the memristor R1 can receive the set voltage through the bit line BL.
  • the memristor structure may also be implemented as other structures, for example, a structure in which the second pole of the memristor R1 is connected to the source line SL, which is not limited in the embodiments of the present disclosure.
  • the function of the word line terminal WL is to apply a corresponding voltage to the gate of the transistor M1 to control the transistor M1 to be turned on or off.
  • the transistor M1 needs to be turned on first, that is, a turn-on voltage needs to be applied to the gate of the transistor M1 through the word line terminal WL.
  • the resistance state of the memristor R1 can be changed by applying a voltage to the memristor R1 at the source line terminal SL and the bit line terminal BL.
  • a set voltage can be applied through the bit line terminal BL to make the memristor R1 in a low resistance state; for another example, a reset voltage can be applied through the source line terminal SL to make the memristor R1 in a high resistance state.
  • the resistance value of the high resistance state is 100 times or more, eg, 1000 times or more, of the resistance value of the low resistance state.
  • the resistance value of the memristor R1 can be made smaller and smaller by simultaneously applying a voltage to the word line terminal WL and the bit line terminal BL, that is, the memristor R1 changes from a high resistance state
  • the operation of changing the memristor R1 from a high-resistance state to a low-resistance state is called a set operation; by applying a voltage at the word line terminal WL and the source line terminal SL at the same time, the memristor R1 can be made to have a low resistance state.
  • the memristor R1 has a threshold voltage, and when the input voltage amplitude is smaller than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 will not be changed.
  • the resistance value (or conductance value) of the memristor R1 can be used for calculation by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can be changed by inputting a voltage greater than the threshold voltage conductance value).
  • FIG. 2B is a schematic diagram of a memristor cell with a 2T2R structure.
  • the memristor cell of 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2.
  • the following description will be given by taking N-type transistors as both the transistors M1 and M2 as an example.
  • the gate of the transistor M1 is connected to the word line terminal WL1.
  • the transistor M1 when the word line terminal WL1 of M1 inputs a high level, the transistor M1 is turned on, and the gate of the transistor M2 is connected to the word line terminal WL2.
  • the word line terminal WL2 of M2 inputs a high level.
  • the transistor M2 is turned on; the first pole of the transistor M1 can be a source and is configured to be connected to the source line terminal SL, for example, the transistor M1 can receive the reset voltage through the source line terminal SL, and the first pole of the transistor M2 can be the source.
  • the transistor M2 can receive the reset voltage through the source line terminal SL, and the first pole of the transistor M1 is connected to the first pole of the transistor M2 and is connected to the source line terminal SL together.
  • the second pole of the transistor M1 may be the drain and is configured to be connected to the second pole (eg, the negative pole) of the memristor R1, and the first pole (eg, the positive pole) of the memristor R1 is connected to the bit line terminal BL1, eg, the memristor.
  • Resistor R1 may receive a set voltage through bit line terminal BL1; the second pole of transistor M2 may be the drain and be configured to be connected to the second pole (eg, negative pole) of memristor R2, the first pole of memristor R2 A pole (eg, positive pole) is connected to the bit line terminal BL2, eg, the memristor R2 can receive a set voltage through the bit line terminal BL2.
  • the second pole of transistor M2 may be the drain and be configured to be connected to the second pole (eg, negative pole) of memristor R2, the first pole of memristor R2 A pole (eg, positive pole) is connected to the bit line terminal BL2, eg, the memristor R2 can receive a set voltage through the bit line terminal BL2.
  • the transistors M1 and M2 in the memristor unit of the 2T2R structure may also both use P-type transistors, which will not be repeated here.
  • FIG. 3 is a schematic flowchart of a data processing method based on a memristor array according to at least one embodiment of the present disclosure.
  • the data processing method based on a memristor array provided by an embodiment of the present disclosure includes steps S110 to S130 , and the memristor array includes a plurality of memristor cells arranged in an array and is configured as It can perform multiplication and sum operation (that is, multiply and accumulate and accumulate, and accumulate the product results of the multiplication to obtain the sum value after the accumulation of the multiplication and addition results).
  • the structure diagram of the memristor array is shown in Figure 1.
  • Each memristor unit may be a 1T1R structure as shown in FIG. 2A or a 2T2R structure as shown in FIG. 2B .
  • step S110 a plurality of first analog signals are acquired.
  • a memristor array is set up, and data corresponding to the convolution parameter matrix processed by the convolution is written into the memristor array, wherein the convolution parameter matrix is a first matrix and includes a plurality of parameter elements arranged in the array , the multiple parameter elements are correspondingly mapped to different multiple memristor sub-arrays in the memristor array multiple times in the form of the first matrix, and the multiple memristor sub-arrays are in the row direction of the memristor array. and do not overlap in the column direction.
  • step S130 a plurality of first analog signals are respectively input to a plurality of column signal input terminals of the set memristor array, and the operation of the memristor array is controlled to perform convolution processing on the plurality of analog signals.
  • the plurality of line signal output terminals of the device respectively obtain a plurality of second analog signals after performing convolution processing.
  • the plurality of first analog signals are input signals to be subjected to convolution processing
  • the plurality of second analog signals are output signals after performing convolution processing on the input signals.
  • the first analog signal is an analog voltage signal
  • the second analog signal is an analog voltage signal
  • the analog signal is an analog current signal.
  • the number of the second analog signals can be set according to calculation requirements.
  • the number of second analog signals can be (N+Q-1), where N represents the number of first analog signals, Q represents the number of columns of the convolution parameter matrix, and correspondingly, the number of rows of the memristor array It can also be set according to the change of the number of the second analog signals.
  • the number of the second analog signals can also be obtained in other forms, which is not limited in the embodiment of the present disclosure.
  • convolution processing is used to perform signal filtering processing on the input signal, and each row of parameter elements in the convolution parameter matrix represents a filter coefficient vector.
  • the number of rows of the convolution parameter matrix is greater than or equal to 1.
  • the convolution parameter matrix represents a vector of filter coefficients used to perform a specific filtering process.
  • the filter used for the filtering process is a finite impulse response filter, for example, a plurality of finite impulse response filters may form a finite impulse phase response filter bank.
  • the input-output relationship of the finite impulse response filter bank can be expressed by the following formula (1):
  • m represents the serial number in the filter bank
  • M represents the total number of filters in the filter bank
  • K represents the filter order
  • x represents the input signal vector
  • y represents the output signal vector
  • h m (k) represents the filter coefficient vector of the m-th filter
  • n may represent a certain moment, for example.
  • the convolution parameter matrix can represent a filter bank, that is, the convolution parameter matrix is composed of multiple filter coefficient vectors.
  • the number of rows of the convolution parameter matrix has at least one row, and each row of parameter elements represents a filter coefficient vector.
  • the parameter elements of the row represent the filter coefficient vectors of different filters, for example, the parameter element of each row is h m (k) in formula (1).
  • the input signal can be processed in parallel by using the feature of the memristor that can perform multiply-accumulate calculations, and not only can all the result values of the convolution processing be obtained in one calculation cycle , on this basis, the results of convolution processing of different filters can be obtained at the same time, speeding up the processing speed and improving the computational efficiency.
  • the signal to be convoluted is a digital signal
  • the digital signal needs to be converted into an analog signal through a digital-to-analog converter, and then calculated through a memristor array.
  • the full analog calculation based on the memristor array needs to convert the digital signal to be calculated into an analog signal many times as the input of the memristor, so this method also requires a large number of digital-to-analog conversions to complete a complete Convolution processing.
  • step S110 may include: acquiring a plurality of initial digital signals; and performing digital-to-analog conversion processing on the plurality of initial digital signals to obtain a plurality of first analog signals respectively.
  • the plurality of initial digital signals may be pre-stored digital signals; for example, the plurality of initial digital signals may be digital signals acquired in real time. Digital-to-analog conversion processing is performed on the plurality of initial digital signals to obtain a plurality of first analog signals.
  • the analog-to-digital conversion process is performed only once, and the obtained multiple first analog signals are input into the memristor array to obtain all the result values of the convolution process.
  • the conversion time caused by multiple analog-to-digital conversions is greatly reduced, and the calculation speed is further improved.
  • a plurality of first analog signals may be obtained by sampling consecutive analog signals.
  • step S110 may include: acquiring an initial analog voltage signal, where the length of the initial analog voltage signal is a preset duration; adjusting the voltage value of the initial analog voltage signal to be within a preset voltage range to obtain the adjusted analog voltage signal; A sampling frequency is set to sample the adjusted analog voltage signal, so as to obtain a plurality of first analog signals respectively corresponding to different moments within a preset time period.
  • each memristor sub-array corresponds to the first matrix
  • different memristor sub-arrays correspond to different column signal input terminals respectively
  • multiple parameter elements are correspondingly multiplied in the form of the first matrix.
  • each memristor sub-array includes multiple target memristor cells.
  • mapping multiple parameter elements to the object memristor subarray in the form of a first matrix including: mapping the parameter elements in the same row in the first matrix to the object respectively The target memristor cells in the same row in the memristor subarray; the parameter elements in the same column in the first matrix are respectively mapped to the target memristor cells in the same column in the target memristor subarray.
  • each row of the convolution parameter matrix includes Q parameter elements
  • each memristor cell includes at least one memristor
  • each memristor can be set to an initial state, eg, the initial state can be the memristor in High resistance state (low conductance state) after initialization.
  • Mapping the parameter elements of the same row of the first matrix to the target memristor cells of the same row in the object memristor subarray including: for each row of parameter elements of the convolution parameter matrix, in the memristor array corresponding to the object memristor element; Select Q target memristor units in a row of memristor units in the resistor subarray to correspond to Q parameter elements one-to-one, and then assign the memristor units except the Q target memristor units in a row of memristor units The memristor in the cell is set to an initial state, where Q is a positive integer greater than 1.
  • selecting Q target memristor cells in a row of memristor cells in the memristor array corresponding to the target memristor sub-array to correspond one-to-one with the Q parameter elements including: according to each of the Q parameter elements
  • the numerical value of the parameter elements sets the memristors included in the selected Q target memristor cells as a whole to a conductive state available for calculation and having a conductance value corresponding to the numerical value.
  • a set voltage or reset voltage can be applied to the memristor at the column signal input terminal (ie, the bit line terminal BL) and the row signal output terminal (ie, the source line terminal SL).
  • each memristor unit may have a 1T1R structure, as shown in FIG. 2A , that is, each memristor unit includes one memristor, and the conductance value of the memristor represents the corresponding parameter element.
  • each memristor unit may have a 2T2R structure, as shown in FIG. 2B , that is, each memristor unit includes two memristors.
  • the method may further include: Obtain a plurality of inversion analog signals corresponding to the plurality of first analog signals, wherein one of the two memristors is used to receive a selected one of the plurality of first analog signals, and the other The resistor is used for receiving an inverted analog signal corresponding to the selected one of the first analog signals.
  • the conductance values of the two memristors can be used to realize the negative value of the parameter element, so that more abundant and complex convolution processing can be realized by using multiple target memristor units.
  • sequentially selecting object column groups to be convolutional from a plurality of column signal input terminals may include: sequentially selecting from a plurality of column signal input terminals to perform convolution according to the translation step size of the convolution processing The processed object column group.
  • x represents the input vector and is an N-dimensional column vector
  • W represents the convolution parameter matrix whose parameter elements are arranged in P rows and M columns
  • a matrix of rows and N columns, O a (a represents any subscript) represents a zero matrix, the number of rows of the zero matrix is P rows, and the number of columns of each zero matrix can be divided according to the block obtained by the convolution parameter matrix W
  • P, M and N are all positive integers, and both M and N are greater than 1.
  • FIG. 4 is a schematic diagram of a memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure.
  • convolution processing is used for signal filtering processing
  • the first row parameter elements in the convolution parameter matrix [w 11 ,w 12 ,...,w 1M ] represent the filter coefficient vector (1)
  • the second row parameter elements in the convolution parameter matrix [w 21 ,w 22 ] ,...,w 2M ] represents the filter coefficient vector (2), ...
  • the Pth row parameter element [w P1 ,w P2 ,...,w PM ] in the convolution parameter matrix represents the filter coefficient vector ( P).
  • the memristor array may include (N+M-1) rows and N columns, and the column signal input terminals of the memristor array respectively input N first analog signals, namely x 1 , x 2 , x 3 ,. ..,x N , the row signal output terminals of the memristor array respectively output (N+M-1) second analog signals, namely y 1 , y 2 , y 3 , .., y N-M+1 , the black square at the intersection of the row and column lines represents a memristor cell.
  • the number “0" next to a memristor cell indicates that the memristor of that memristor cell is in the initial state
  • the mark " wij " next to the memristor cell indicates the conductance value of the memristor of that memristor cell is the value of the parameter element "wij", where i and j are both positive integers, i is less than or equal to P, and j is less than or equal to M.
  • the convolution parameter matrices are mapped to memristor subarrays (1), ..., memristor subarrays (n), ..., memristor subarrays (N-M+1), etc.
  • the convolutional results y 1 , y 2 , y 3 ,..., y N-M+1 of the N first analog signals are simultaneously obtained, where n is greater than 1 and A positive integer less than (N-M+1).
  • each memristor sub-array corresponds to different object column groups.
  • the object column group corresponding to the memristor sub-array (1) includes M column signal input terminals , and the first analog signals input by the M column signal input terminals are respectively x1 to x M .
  • each memristor sub-array does not overlap in the row and column directions of the memristor array, and when the translation step size of the convolution processing is a, the translation step size a is Select the object column groups that need to be convoluted in sequence.
  • the object column group (1) may be the first analog signals x 1 to x M
  • the object column group (2) may be the first analog signals x a to x a+ M , and so on to obtain the object column group that needs to be processed by convolution, where a is a positive integer.
  • the moving direction of the memristor sub-array also changes accordingly, which is not limited in the embodiment of the present disclosure.
  • a plurality of first analog signals may be respectively applied to a plurality of column signal input terminals of the set memristor array, and a turn-on signal may be applied to a plurality of signal control terminals of the memristor array at the same time to detect and acquiring multiple current signals of multiple row signal output terminals of the memristor array, and obtaining multiple second analog signals based on the multiple current signals.
  • 5A is a schematic diagram of a memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure.
  • the row vector W 2 is a filter coefficient vector corresponding to the second filter, and G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are parameter elements, respectively.
  • the memristor array includes 14 rows and 10 columns, eg, which is part of a larger memristor array.
  • each box represents a memristor cell
  • the text in the box represents the conductance value of the memristor in the memristor cell, for example, "0" represents the memristor of the memristor cell
  • the memristor in the memristor unit can be reset to a high resistance state to make it in the initial state.
  • the resistance value of the initial state of the memristor is much larger than that of the set state. If the initial state is The resistance value of is considered to be infinite, then its reciprocal corresponds to 0.
  • G 1 [0]” to “G 1 [3]” and “G 2 [0]” to “G 2 [3]” represent the memristor of the memristor cell whose conductance value is the value of the parameter element .
  • Each memristor cell can be either a 1T1R structure or a 2T2R structure.
  • V[0] to V[9] in FIG. 5A are 10 first analog signals, respectively input to 10 column signal input terminals
  • I 1 [0] to I 1 [6] and I in FIG. 5A 2 [0] to I 2 [6] are respectively 14 second analog signals output by the 14 line signal output terminals.
  • each memristor unit with 2 rows and 4 columns defined by the thick solid line frame is a memristor sub-array, and a plurality of memristor sub-arrays are arranged in the row direction of the memristor array and There is no overlap in the column direction, and different memristor sub-arrays correspond to different column signal input terminals respectively.
  • the memristor sub-arrays located in the first row and the second row of the memristor array are corresponding to The object memristor subarray of the object column group (1), the parameter elements G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are mapped to the object memory in the first matrix form resistor sub-array.
  • the parameter elements G1 [0] to G1 [3] are mapped to the 4 target memristor cells in the first row (that is, the one starting from the upper left corner in the memristor array Memristor cells in row 1, column 7 to row 1, column 10), 4 target memristor cells one-to-one corresponding to 4 parameter elements G 1 [0] to G 1 [3], the first row
  • the memristors in the 6 memristor cells except these 4 target memristor cells are set to the initial state, that is, the "0" in the 1st row and the 1st column to the 1st row and the 6th column in Fig. 5A ".
  • parameter elements G2[ 0 ] through G2[ 3 ] map to the 4 target memristor cells in the second row (i.e. row 2, column 7 to row 2, 10 in the memristor array).
  • the 4 target memristor cells correspond one-to-one to the 4 parameter elements G2[ 0 ] to G2[ 3 ], except for these 4 target memristor cells in the second row
  • the memristors in the 6 memristor cells are set to the initial state, that is, "0" in the 2nd row, the 1st column to the 2nd row and the 6th column in FIG. 5A .
  • the memristor sub-arrays located in the third row and the fourth row of the memristor array are corresponding to The object memristor subarray of the object column group (2), the parameter elements G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are mapped to the object memory in the first matrix form In the resistor sub-array, the specific mapping process is as described above and will not be repeated here.
  • the memristor sub-arrays located in the fifth row and the sixth row of the memristor array are corresponding to the object an object memristor subarray of column group (3) to which the parameter elements G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are mapped in a first matrix form to the object memristor In the sub-array, the specific mapping process is as described above, and will not be repeated here.
  • the parameter elements G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are respectively mapped to different memristor sub-arrays according to the first matrix form, so as to obtain as follows:
  • 10 first analog signals are respectively input to multiple column signal input terminals of the set memristor array, and the operation of the memristor array is controlled to perform convolution processing on the multiple analog signals.
  • the output current of the memristor array can be obtained according to the following formula (2):
  • V k represents the voltage input by the k-th column signal input terminal among the plurality of column signal input terminals
  • I j represents the current signal output by the j-th row signal output terminal among the plurality of row signal output terminals.
  • G jk represents the overall conductance value of the memristor cell located at the jth row and the kth column. According to Kirchhoff's law, the memristor array can complete the multiply-accumulate calculation in parallel.
  • 14 second analog signals after convolution processing are respectively obtained at the 14 row signal output terminals of the memristor array, that is, I 1 [0] to I 1 [6] and I in FIG. 5A . 2 [0] to I 2 [6], where I 1 [0] to I 1 [6] are 7 convolution processing results corresponding to the first filter, I 2 [0] to I 2 [6] are 7 convolution processing results corresponding to the second filter.
  • Fig. 5B is a schematic diagram of another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure. This embodiment can implement the same convolution calculation as the embodiment shown in Fig. 5A.
  • the definitions of the memristor array, the convolution parameter matrix, the 10 first analog signals, and the object column group shown in FIG. 5B are exactly the same as those shown in FIG. 5A , and will not be repeated here.
  • the memristor cell located in the upper left corner of the memristor array is regarded as the memristor cell located in the first row and the first column
  • the object memristor array corresponding to the object column group (1) is the memristor array located in the memristor array
  • the elements G 1 [0] to G 1 [3] and G 2 [0] to G 2 [3] are arranged separately in two rows that are no longer directly adjacent, they still constitute a subarray.
  • the target memristor arrays corresponding to the target column group (2) are 4 target memristor cells located in the second row, 6th column to the second row, 9th column of the memristor array and the memristor cells located in the memristor array.
  • the 4 target memristor cells in the ninth row and the sixth column to the ninth row and the ninth column, and so on, will not be repeated here.
  • each row of parameter elements includes Q parameter elements, such as the first row of parameter elements G 1 [0] to G 1 [3] or the second row of parameter elements G 2 [0 for each row of parameter elements of the convolution parameter matrix ] to G 2 [3], map each row of parameter elements to multiple memristor rows in the memristor array, each memristor row includes Q target memristor cells one-to-one corresponding to Q parameters elements, e.g., map the first row of parameter elements to the first through seventh rows in the memristor array, and map the second row of parameter elements to the eighth through fourteenth rows in the memristor array, e.g.
  • each memristor row includes 4 target memristor cells, and the 4 target memristor cells correspond to 4 parameter elements G 1 [0] to G 1 [3], for the eighth to fourteenth rows in the memristor array, each memristor row includes 4 target memristor cells, and these 4 The target memristor cells correspond one-to-one to the 4 parameter elements G 2 [0] to G 2 [3].
  • the size of the memristor subarray is the same as the size of the convolution parameter matrix.
  • the convolution parameter matrix is in the form of a first matrix with P rows and Q columns. It includes P rows and Q columns of target memristor cells.
  • one memristor row in the memristor array uniquely corresponds to a row of parameter elements in the convolution parameter matrix, and the present disclosure is for each row of target memristors in the memristor sub-array.
  • the positional relationship between cells and the positional relationship between target memristor cells in each memristor row are not limited.
  • each row of target memristor cells in the memristor sub-array may be a plurality of target memristor cells that are adjacent and consecutive to each other, eg, according to a plurality of first analog signals
  • each row of target memristor cells in the memristor sub-array may also be a plurality of discontinuous target memristor cells, which is not limited in the present disclosure.
  • each row of target memristor cells in the memristor sub-array is not restricted to be adjacent, for example, as shown in Figure 5A, The two rows of target memristor cells in each memristor sub-array are adjacent to each other, or as shown in FIG. 5B, the two rows of target memristor cells in each memristor sub-array are not adjacent to each other, the present disclosure There is no restriction on this.
  • each parameter element can be represented by the conductance value of two memristors, for example, by the difference of the conductance values of the two memristors to represent a Parametric element, alternatively, a parametric element represented by the sum of the conductance values of the two memristors.
  • the convolution parameter matrix is a first matrix arranged in 2*P rows and Q columns, and the convolution parameter matrix includes a first subconvolution parameter matrix with P rows and Q columns and a corresponding second subvolume with P rows and Q columns.
  • Product parameter matrix, the parameter elements corresponding to the row and column positions in the first sub-convolution parameter matrix and the second sub-convolution parameter matrix together represent a parameter element for performing convolution processing, thereby obtaining the substantial P row and Q column after the operation.
  • Convolution parameter matrix where P is a positive integer greater than or equal to 1, and Q is a positive integer greater than 1.
  • corresponding to a row-column position refers to a position in the memristor array that corresponds in the row and column directions.
  • the first sub-convolution parameter matrix includes P rows of first parameter elements
  • the second sub-convolution parameter matrix includes P rows of second parameter elements, P rows of first parameter elements and P rows of second parameters
  • the row and column positions of the elements are in one-to-one correspondence
  • a plurality of second analog signals after performing convolution processing are obtained at the plurality of row signal output ends of the memristor array respectively, including: for each memristor sub-array, determining at least one set of rows to be processed, wherein each group of rows to be processed includes a row of target memristor cells corresponding to a row of first parameter elements, and a row of target memristors corresponding to a row of second parameter elements corresponding to a row of first parameter elements performing current preprocessing on the current signals of the two row signal output terminals corresponding to the two rows of target memristor units included in each group of rows to be processed, to obtain second analog signals corresponding to each group of rows to be processed.
  • the current preprocessing is current subtraction processing or current addition processing.
  • the first matrix is a matrix with parameter elements arranged in 2 rows and 4 columns
  • the row vector W + is the first subconvolution parameter matrix
  • the first subvolume includes a row of first parameter elements (G + [0], G + [1], G + [2])
  • the row vector W - is the second sub-convolution parameter matrix
  • the second sub-convolution parameter matrix includes A row of second parameter elements (G - [0], G - [1], G - [2], G - [3]).
  • the parameter element G + [0] and the parameter element G-[0] collectively represent the parameter element G[0] that performs the convolution process, and the parameter element G + [1] and the parameter element G-[1] collectively represent that the convolution process is performed .
  • the parameter element G[1], the parameter element G + [2] and the parameter element G-[2] collectively represent the parameter element G[2], the parameter element G + [3] and the parameter element G-[2] that perform the convolution process 3] together represent the parameter element G[3] for performing convolution processing, that is, the filter coefficient vector used for performing convolution processing is (G[0], G[1], G[2], G[3 ]), the filter coefficient vector is jointly represented by the first sub-convolution parameter matrix and the corresponding second sub-convolution parameter matrix, so that the parameter elements can be realized by using the first sub-convolution parameter matrix and the corresponding second sub-convolution parameter matrix Negative value of , to perform richer and more complex convolution processing.
  • FIG. 6 is a schematic diagram of still another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure.
  • V[0] to V[9] in Fig. 6 are 10 first analog signals, respectively input to 10 column signal input terminals, I + [0] to I + [6] and I in Fig. 6 - [0] to I - [6] are 14 current signals output by the 14 line signal output terminals, respectively, and 7 second analog signals I[0] to I[6] are obtained based on the 14 current signals.
  • the convolution parameter matrix W' is mapped to different multiple memristor sub-arrays in the memristor array multiple times in the form of the first matrix, and each memristor sub-array is marked with a thick black solid line in Figure 6
  • the convolution parameter matrix W' corresponding to each memristor array is a convolution parameter matrix with 1 row and 4 columns after the operation, and the specific process is as follows As mentioned above, it will not be repeated here.
  • each parameter element for performing the convolution process is represented by the difference between the parameter elements at the corresponding row and column positions in the first subconvolution parameter matrix W + and the second subconvolution parameter matrix W ⁇ .
  • the corresponding set of rows to be processed includes the memristor arrays in the memristor array A row of target memristor cells in the first row, and a row of target memristor cells in the second row of the memristor array.
  • the current signal I + [0] of the row signal output terminal of the first row in the memristor array is subtracted from the current signal I-[0] of the row signal output terminal of the second row to obtain the second analog signal I [0].
  • the corresponding set of rows to be processed includes the memristor sub-arrays (2) in the memristor array One row of target memristor cells in three rows, and one row of target memristor cells in the fourth row of the memristor array.
  • the current signal I + [1] of the row signal output terminal of the third row in the memristor array is subtracted from the current signal I-[1] of the row signal output terminal of the fourth row to obtain the second analog signal I [1].
  • the second analog signal I[2] to the second analog signal [6] are obtained in the above-mentioned manner, so as to obtain seven second analog signals after performing convolution processing.
  • two correspondingly set first memristor arrays and second memristor arrays can also be used, and the current signals at the corresponding row signal output terminals can be preprocessed to obtain the second analog signal, so as to realize the negation of the parameter element. value to perform richer, more complex convolution processing.
  • the memristor array includes a first memristor array and a second memristor array
  • the convolution parameter matrix includes a first subconvolution parameter matrix and a second subconvolution parameter matrix
  • the first subconvolution parameter matrix and The second sub-convolution parameter matrix is in the form of a first matrix
  • the first sub-convolution parameter matrix is correspondingly mapped to different multiple memristor sub-arrays in the first memristor array according to the first matrix form.
  • the second sub-convolution parameter matrix is correspondingly mapped to different multiple memristor sub-arrays in the second memristor array for multiple times in the form of the first matrix.
  • step S130 for example, obtaining a plurality of second analog signals after performing convolution processing at the signal output terminals of a plurality of rows of the memristor array, respectively, may include: for each row in the first memristor array The current signal at the signal output terminal and the current signal at the corresponding row signal output terminal in the second memristor array are subjected to current preprocessing to obtain a plurality of second analog signals.
  • the current preprocessing is current subtraction processing or current addition processing.
  • the first matrix is a matrix with parameter elements arranged in 1 row and 4 columns, that is, a 4-dimensional row vector.
  • the row vector W + is the first sub-convolution parameter matrix
  • the row vector W- is the second sub - convolution parameter matrix
  • the first sub-convolution parameter matrix and the second sub-convolution parameter matrix are both in the form of first matrices.
  • the parameter elements at the corresponding row and column positions in the first sub-convolution parameter matrix and the second sub-convolution parameter matrix together represent one parameter element for performing the convolution process.
  • the parameter element G + [0] and the parameter element G-[0] collectively represent the parameter element G[0] that performs the convolution process
  • the parameter element G + [1] and the parameter element G-[1] collectively represent the execution volume
  • the parameter element G[1] of the product process, the parameter element G + [2] and the parameter element G - [2] collectively represent the parameter element G[2]
  • the parameter element G + [3] and the parameter element G that perform the convolution process - [3] collectively represents the parameter element G[3] for performing convolution processing, that is, the filter coefficient vector for performing convolution processing is (G[0], G[1], G[2], G [3]), the filter coefficient vector is jointly represented by the first sub-convolution parameter matrix and the corresponding second sub-convolution parameter matrix, so that the first sub-convolution parameter
  • FIG. 7 is a schematic diagram of still another memristor array after writing a convolution parameter matrix according to at least one embodiment of the present disclosure. This embodiment can implement the same convolution calculation as the embodiment shown in FIG. 6 .
  • the memristor array shown in FIG. 7 includes a first memristor array and a second memristor array, and each memristor array has an independent control circuit, for example, has an independent column signal input terminal to input 10 signals respectively first analog signals V[0] to V[9], and independent row signal output terminals to output current signals I + [0] to current signals I + [6] and current signals I-[0] to current signals I-[6] .
  • I[0] to I[6] in FIG. 7 represent seven second analog signals after convolution processing.
  • the first sub-convolution parameter matrix W + in the convolution parameter matrix W' is mapped to different multiple memristor sub-arrays in the first memristor array multiple times in the form of the first matrix
  • the convolution The second sub-convolution parameter matrix W in the parameter matrix W' is mapped to different multiple memristor sub - arrays in the second memristor array multiple times in the form of the first matrix to obtain the memristor shown in FIG. 7 .
  • Resistor array the specific process is as described above, and will not be repeated here.
  • each parameter element for performing the convolution process is represented by the difference between the parameter elements at the corresponding row and column positions in the first subconvolution parameter matrix W + and the second subconvolution parameter matrix W ⁇ .
  • the current signal I + [0] of the row signal output terminal of the first row in the first memristor array and the current signal I-[0] of the row signal output terminal of the first row in the second memristor array Subtracted to obtain the second analog signal I[0].
  • the current signal I + [1] of the row signal output terminal of the second row in the first memristor array and the current signal I-[1] of the row signal output terminal of the second row in the second memristor array Subtracted to obtain the second analog signal I[1].
  • the second analog signal I[2] to the second analog signal [6] are obtained in the above manner, so as to obtain seven second analog signals after performing convolution processing.
  • the data processing method based on a memristor array provided by at least one embodiment of the present disclosure may further include: performing analog-to-digital conversion processing on a plurality of second analog signals, so as to convert the plurality of second analog signals into a plurality of digital signals respectively signal for subsequent processing.
  • FIG. 8 is a schematic processing flow diagram of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure.
  • step S120 the data corresponding to the convolution parameter matrix of the convolution process is written into the memristor array, and the specific process is as described in step S120 , which will not be repeated here.
  • the initial digital signal used for convolution processing is converted into a plurality of first analog signals, where the first analog signal is an analog voltage signal, and the specific process is as described in step S110, which will not be repeated here.
  • Step S130 is described and will not be repeated here.
  • the data processing method based on the memristor array can realize that all results of the convolution processing operation can be obtained in one calculation (or one calculation cycle), which greatly reduces the data shift and the number of analog-to-digital conversions in the process of obtaining the first analog signal and the required time, reducing power consumption and increasing computing speed.
  • the data processing method based on the memristor array provided by the present disclosure can be used for the analysis of neural signals, for example, can be used for the design of intracranial systems to process the acquired initial neural signals, such as feature extraction, etc., Further reduce the power consumption of the convolution processing process, improve the operation speed, and meet the strict power consumption and area requirements of the intracranial system design.
  • the initial nerve signal may be a cranial nerve signal, a spinal nerve signal, etc., and the initial nerve signal includes but is not limited to nerve signals of various animals.
  • each filter coefficient vector is used to extract different feature information, so that the memristor array can be used to perform multiple different features on multiple initial neural signals in parallel. Extraction to obtain multiple second analog signals, that is, multiple feature information, has higher computational efficiency and lower power consumption.
  • FIG. 9A is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device 900 includes a memristor array 901 , a signal acquisition device 902 and a control driving circuit 903 .
  • the memristor array 901 is configured to perform multiplication and sum operations to perform convolution processing as described above.
  • the signal acquisition means 902 is configured to acquire a plurality of first analog signals.
  • the control driving circuit 903 is configured to perform steps S120 to S130.
  • the memristor array 901 may adopt the memristor array shown in FIG. 1 , and the memristor array includes a plurality of memristor cells arranged in an array, for example, the memristor array includes m rows and n columns.
  • each memristor cell includes a memristor
  • each memristor includes a first end and a second end
  • the memristor can be set to an initial state, and can also be set (set) to have a certain The set state of the resistance value. When the memristor is in its initial state, its resistance value is much greater than when it is in the set state.
  • each memristor unit further includes a switch element, the switch element includes a control terminal, a first pole and a second pole, and the first terminal of the memristor is electrically connected to the first pole of the switch element.
  • a memristor array also includes m word lines, m source lines, and n bit lines.
  • m word lines correspond to m rows respectively, each word line is electrically connected to the control terminals of each switching element of a row of memristor cells
  • m source lines correspond to m rows respectively
  • m source lines correspond to m rows respectively
  • Each source line is electrically connected to the second pole of each switching element of a row of memristor cells
  • n bit lines correspond to n columns respectively, and each bit line is connected to the second pole of each memristor of a row of memristor cells terminal electrical connection.
  • the signal acquisition device 902 includes a digital signal acquisition circuit and a digital-to-analog conversion circuit.
  • the digital signal acquisition circuit is configured to acquire a plurality of initial digital signals; the digital-to-analog conversion circuit is configured to perform digital-to-analog conversion processing on the plurality of initial digital signals to obtain a plurality of first analog signals respectively.
  • control driver circuit 903 may include a source line driver circuit, a word line driver circuit, and a bit line driver circuit.
  • the source line driver circuit is configured to detect a plurality of second analog signals and perform an initialization operation on the memristor array;
  • the word line driver circuit is configured to apply a turn-on signal to the plurality of signal control terminals of the memristor array and to perform an initialization operation on the memristor array.
  • the array performs an initialization operation;
  • the bit line driver circuit is configured to apply an input signal to a plurality of column signal input terminals and perform an initialization operation to the memristor array, wherein the input signal includes at least a plurality of first analog signals.
  • control driver circuit 903 can apply input signals to multiple column signal input terminals of the memristor array through the bit line driver circuit, and simultaneously apply the turn-on signal to multiple signal control terminals of the memristor array through the word line driver circuit, Finally, the current signals of the plurality of row signal output terminals of the set memristor array are processed by the source line driving circuit to obtain a plurality of second analog signals.
  • the electronic device 900 may further include a data output circuit, wherein the data output circuit is configured to convert the plurality of second analog signals into digital signals, so as to respectively convert the plurality of second analog signals into a plurality of digital signals for use in for subsequent processing.
  • the data output circuit is configured to convert the plurality of second analog signals into digital signals, so as to respectively convert the plurality of second analog signals into a plurality of digital signals for use in for subsequent processing.
  • step S110 shown in FIG. 3 in the above-mentioned embodiment of the data processing method based on the memristor array
  • the circuit 903 is used to implement the steps S120 to S130 shown in FIG. 3 .
  • the control driving circuit 903 please refer to the steps S120 to S130 shown in FIG. 3 in the above-mentioned embodiment of the data processing method based on the memristor array. related description.
  • the electronic device can achieve similar technical effects as the aforementioned data processing method based on the memristor array, which is not repeated here.
  • FIG. 9B is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure.
  • the electronic device includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array, and a data output circuit.
  • the signal acquisition device is configured to convert a digital signal into a plurality of first analog signals through a DAC (Digital to Analog converter), so as to be input to a plurality of column signals of the memristor array during convolution processing input.
  • DAC Digital to Analog converter
  • a memristor array includes M source lines, M word lines, and N bit lines, and a plurality of memristor cells arranged in M rows and N columns of the array.
  • each memristor unit has a 1T1R structure, and the convolution parameter matrix used for convolution processing is mapped to different sub-arrays in the memristor array multiple times. The specific process is as described in step S120, which will not be repeated here. .
  • the process of implementing the convolution processing by the word line driving circuit, the bit line driving circuit and the source line driving circuit is as described above, and will not be repeated here.
  • the word line driver circuit includes a plurality of multiplexers (Multiplexer, Mux for short) for switching the word line input voltage
  • the bit line driver circuit includes a plurality of multiplexers for switching the bit line input voltage
  • the source line The driver circuit also includes a plurality of multiplexers for switching the source line input voltage.
  • a memristor array includes an operating mode and a computing mode.
  • the memristor array is in the operating mode, the memristor cell is in an initialization state, and the values of the parameter elements in the convolution parameter matrix can be written into the memristor array.
  • the source line input voltage, bit line input voltage and word line input voltage of the memristor are switched to corresponding preset voltage ranges through multiplexers.
  • the word line input voltage is switched to the corresponding voltage range through the control signal WL_sw[1:M] of the multiplexer in the word line driving circuit in FIG. 9B .
  • the word line input voltage is set to 2V (volts), for example, when the memristor is reset, the word line input voltage is set to 5V, for example, the word line input voltage It can be obtained by the voltage signals V_WL[1:M] in FIG. 9B.
  • the source line input voltage is switched to the corresponding voltage range through the control signals SL_sw[1:M] of the multiplexer in the source line driving circuit in FIG. 9B.
  • the word line input voltage is set to 0V.
  • the source line input voltage is set to 2V.
  • the source line input voltage can be obtained by Fig.
  • the voltage signals V_SL[1:M] in 9B are obtained.
  • the bit line input voltage is switched to the corresponding voltage range through the control signals BL_sw[1:N] of the multiplexer in the bit line driving circuit in FIG. 9B .
  • the bit line input voltage is set to 2V.
  • the bit line input voltage is set to 0V.
  • the source line input voltage can be obtained by Fig. DAC obtained in 9B.
  • the memristors in the memristor array are in a conductive state that can be used for calculation, and the input voltage of the bit line input at the column signal input terminal will not change the conductance value of the memristor,
  • the convolution process is accomplished by performing a multiply-sum operation through the memristor array. For example, the word line input voltage is switched to the corresponding voltage range by the control signal WL_sw[1:M] of the multiplexer in the word line driving circuit in FIG.
  • the word line input of the corresponding row The voltage is set to 5V, for example, when the turn-on signal is not applied, the input voltage of the word line of the corresponding row is set to 0V, for example, the GND signal is turned on; through the control signal SL_sw[1 of the multiplexer in the source line driver circuit in FIG. 9B :M] Switch the input voltage of the source line to the corresponding voltage range, for example, set the input voltage of the source line to 0V, so that the current signals of the multiple row signal output terminals can flow into the data output circuit, through the bit line driving circuit in FIG.
  • the control signal BL_sw[1:N] of the multiplexer in the bit line switches the input voltage of the bit line to the corresponding voltage range, for example, the input voltage of the bit line is set to 0.1V-0.3V, so that the multiplication can be performed by using the memristor array.
  • the characteristics of the sum operation complete the convolution operation.
  • the data output circuit includes a plurality of ADCs (Analog to Digital converter, analog-to-digital converters), which can convert the current signals of the plurality of row signal output terminals into digital signals for subsequent processing.
  • ADCs Analog to Digital converter, analog-to-digital converters
  • FIG. 9C is a schematic diagram of another electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device shown in FIG. 9C has the same structure as the electronic device shown in FIG. 9B , and also includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array and a data output circuit.
  • a memristor array includes M source lines, 2M word lines, and 2N bit lines, and a plurality of memristor cells arranged in M rows and N columns.
  • each memristor unit has a 2T2R structure, and the convolution parameter matrix used for convolution processing is mapped to different sub-arrays in the memristor array multiple times. The specific process is as described in step S120, which will not be repeated here. .
  • the memristor array may also include M source lines, M word lines and 2N bit lines, and a plurality of memristor cells arranged in M rows and N columns. Since the turn-on signal is simultaneously applied to a plurality of signal control terminals of the memristor array when step S130 is performed, each word line can simultaneously control two memristors in each row of memristor cells.

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Abstract

一种基于忆阻器阵列(901)的数据处理方法、电子装置(900)。该基于忆阻器阵列(901)的数据处理方法包括：获取多个第一模拟信号；设置忆阻器阵列(901)，将对应于卷积处理的卷积参数矩阵的数据写入忆阻器阵列(901)；将多个第一模拟信号分别输入设置后的忆阻器阵列(901)的多个列信号输入端，控制忆阻器阵列(901)操作以对多个模拟信号进行卷积处理，在忆阻器阵列(901)的多个行信号输出端分别得到执行卷积处理后的多个第二模拟信号。该基于忆阻器阵列(901)的数据处理方法通过将卷积参数矩阵多次映射于忆阻器阵列(901)中不同的多个忆阻器子阵列，实现一次计算即可得到卷积处理操作的所有结果，大大减少了移位所需的时间，降低了功耗，提高了计算速度。

Description

基于忆阻器阵列的数据处理方法、电子装置
本申请要求于2021年4月20日递交的中国专利申请第202110426351.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种基于忆阻器阵列的数据处理方法、电子装置。
背景技术
随着科学技术的进步和信息技术的快速发展，人们可以通过物联网传感技术采集得到大量的数据，并且需要对这些大量数据进行低功耗、高能效的分析及处理，以快速提取数据特征和信息。
卷积处理是一种常用的线性运算，广泛应用于信号处理领域、图像处理领域、神经网络领域等。对两个对象进行卷积处理所得到的卷积结果，表示其中一个对象如何被另一个对象修改，例如，在信号处理领域，可以利用卷积处理对信号进行滤波等处理。
发明内容
本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法，所述忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算，所述方法包括：获取多个第一模拟信号；设置所述忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入所述忆阻器阵列，其中，所述卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，且所述多个忆阻器子阵列在所述忆阻器阵列的行方向和列方向上均不重叠；将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个模拟信号进行所述卷积处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，获取所述多个第一模拟信号，包括：获取多个初始数字信号；对所述多个初始数字信号进行数模转换处理，以分别得到所述多个第一模拟信号。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，每个忆阻器子阵列对应于所述第一矩阵，不同的所述忆阻器子阵列分别对应于不同的列信号输入端，所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，包括：从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组，其中，每个对象列组包括至少一个列信号输入端；对于每个被选择的对象列组，将所述多个参数元素对应地按照所述第一矩阵的形式映射到对象忆阻器子阵列中，其中，所述对象忆阻器子阵列为所述多个忆阻器子阵列中对应于所述被选择的对象列组的忆阻器子阵列。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，每个忆阻器子阵列包括多个目标忆阻器单元，对于每个被选择的对象列组，将所述多个参数元素对应地按照所述第一矩阵的形式，映射到所述对象忆阻器子阵列中，包括：将所述第一矩阵中同一行的参数元素分别映射于所述对象忆阻器子阵列中同一行的目标忆阻器单元；将所述第一矩阵中同一列的参数元素分别映射于所述对象忆阻器子阵列中同一列的目标忆阻器单元。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述卷积参数矩阵的每行包括Q个参数元素，每个忆阻器单元包括至少一个忆阻器，每个忆阻器可被设置为初始状态，将所述第一矩阵的同一行参数元素映射于所述对象忆阻器子阵列中同一行的目标忆阻器单元，包括：对于所述卷积参数矩阵的每行参数元素，在所述忆阻器阵列中对应于所述对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于所述Q个参数元素，再将所述一行忆阻器单元中除所述Q个目标忆阻器单元外的忆阻器单元中的忆阻器设置为所述初始状态，其中，Q为大于1的正整数。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，在所述忆阻器阵列中对应于所述对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于所述Q个参数元素，包括：根据所述Q个参数元素中每个参数元素的数值，将所述选择的Q个目标忆阻器单元中包括的忆阻器整体上设定为可用于计算的导电状态且具有对应于所述数值的 电导值。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组，包括：按照所述卷积处理的平移步长，从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述卷积参数矩阵为排布成2*P行Q列的第一矩阵，所述卷积参数矩阵包括P行Q列的第一子卷积参数矩阵和对应的P行Q列的第二子卷积参数矩阵，所述第一子卷积参数矩阵和所述第二子卷积参数矩阵中对应行列位置的参数元素共同表示执行所述卷积处理的一个参数元素，其中P为大于等于1的正整数，Q为大于1的正整数。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述第一子卷积参数矩阵包括P行第一参数元素，所述第二子卷积参数矩阵包括P行第二参数元素，所述P行第一参数元素与所述P行第二参数元素的行列位置一一对应，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号，包括：针对每个忆阻器子阵列，确定至少一组待处理行，其中，每组待处理行包括与一行第一参数元素所对应的一行目标忆阻器单元，以及与对应于所述一行第一参数元素的一行第二参数元素所对应的一行目标忆阻器单元；对每组待处理行包括的两行目标忆阻器单元分别对应的两个行信号输出端的电流信号进行电流预处理，以得到所述每组待处理行对应的第二模拟信号。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，所述卷积参数矩阵包括第一子卷积参数矩阵和第二子卷积参数矩阵，所述第一子卷积参数矩阵和所述第二子卷积参数矩阵均为所述第一矩阵形式，所述第一子卷积参数矩阵对应地按照所述第一矩阵的形式被多次映射于所述第一忆阻器阵列中不同的多个忆阻器子阵列，所述第二子卷积参数矩阵对应地按照所述第一矩阵的形式被多次映射于所述第二忆阻器阵列中不同的多个忆阻器子阵列。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号，包括：对所述第一忆阻器阵列中的每个行信号输出端的电 流信号和所述第二忆阻器阵列中对应的行信号输出端的电流信号进行电流预处理，以得到所述多个第二模拟信号。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述电流预处理为电流相减处理或电流相加处理。
例如，本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法还包括：对所述多个第二模拟信号进行模数转换处理，以将所述多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
例如，在本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法中，所述第一模拟信号为模拟电压信号，所述第二模拟信号为模拟电流信号。
本公开至少一实施例提供一种电子装置，包括：忆阻器阵列，配置为能进行乘和运算；信号获取装置，配置为获取多个第一模拟信号；控制驱动电路，其中，所述控制驱动电路配置为执行以下步骤：设置所述忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入所述忆阻器阵列，其中，所述卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，且所述多个忆阻器子阵列在所述忆阻器阵列的行方向和列方向上均不重叠；将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个模拟信号进行所述卷积处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号。
例如，在本公开至少一实施例提供一种电子装置中，所述信号获取装置包括数字信号获取电路和数模转换电路，所述数字信号获取电路配置为获取多个初始数字信号；所述数模转换电路配置为对所述多个初始数字信号进行数模转换处理，以分别得到所述多个第一模拟信号。
例如，在本公开至少一实施例提供一种电子装置中，所述控制驱动电路包括：源线驱动电路，配置为对所述多个第二模拟信号进行检测和对所述忆阻器阵列执行初始化操作；字线驱动电路，配置为对所述忆阻器阵列的多个信号控制端施加开启信号和对所述忆阻器阵列执行初始化操作；以及位线驱动电路，配置为对所述多个列信号输入端施加输入信号和对所述忆阻器阵列执行初始化操作，其中，所述输入信号至少包括所述多个第一模拟信号。
例如，本公开至少一实施例提供一种电子装置还包括数据输出电路，其 中，所述数据输出电路配置为将所述多个第二模拟信号转换为数字信号，以将所述多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种忆阻器阵列的示意性结构；
图2A为1T1R结构的忆阻器单元的示意图；
图2B为2T2R结构的忆阻器单元的示意图；
图3为本公开至少一实施例提供的一种基于忆阻器阵列的数据处理方法的示意性流程图；
图4为本公开至少一实施例提供的一种写入卷积参数矩阵后的忆阻器阵列的示意图；
图5A为本公开至少一实施例提供的一种写入卷积参数矩阵后的忆阻器阵列的示意图；
图5B为本公开至少一实施例提供的另一种写入卷积参数矩阵后的忆阻器阵列的示意图；
图6为本公开至少一实施例提供的再一种写入卷积参数矩阵后的忆阻器阵列的示意图；
图7为本公开至少一实施例提供的再一种写入卷积参数矩阵后的忆阻器阵列的示意图；
图8为本公开至少一实施例提供的基于忆阻器阵列的数据处理方法的处理流程示意图；
图9A为本公开至少一实施例提供的一种电子装置的示意性框图；
图9B为本公开至少一实施例提供的一种电子装置示意图；以及
图9C为本公开至少一实施例提供的另一种电子装置示意图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且 不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。
需要注意，本公开中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本公开中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
应当理解，本公开的方法实施方式中记载的各个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本公开的范围在此方面不受限制。本公开实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的，而并不是用于对这些消息或信息的范围进行限制。
目前，对大量数据进行处理通常采用传统的技术平台，例如CPU(Central Processing Unit,中央处理器)、GPU(Graphics Processing Unit，图形处理器)等采用冯诺依曼架构的平台，由于摩尔定律逼近极限，通过这些传统的计算平台所得到的算力提升面临终结。
忆阻器(例如阻变存储器、相变存储器、导电桥存储器等)是一种新型的微纳电子器件，可以通过施加外部激励，调节其电导状态。忆阻器的工作机理与人脑中的神经突触、神经元等具有一定的相似性，所以它们在神经形态计算中有广泛的应用前景。根据基尔霍夫电流定律和欧姆定律，由这类器件构成的阵列可以并行的完成乘累加计算，且存储和计算都发生在该阵列的各器件中。基于这种计算架构，可以实现不需要大量数据搬移的存算一体计算，减少了数据搬运的时间，计算时能效较高、功耗较低、面积较小。
例如，可以基于忆阻器阵列，利用物理定律实现模拟计算，例如卷积处理。
目前，基于忆阻器阵列的全模拟计算，需要在运算时采用模拟输入电压和模拟电导，在执行信号的滤波等常用卷积处理操作的时候，每次只能得到对应于一个时间点的结果值，获得不同时间点的结果值需要对模拟输入电压进行移位得到，因此这种方式需要大量次数的数据移位才能完成一次完整的卷积处理，计算延时高、功耗大。
本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法和电子装置。该基于忆阻器阵列的数据处理方法包括：获取多个第一模拟信号；设置忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入忆阻器阵列，其中，卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，多个参数元素对应地按照第一矩阵的形式被多次分别映射于忆阻器阵列中不同的多个忆阻器子阵列，且多个忆阻器子阵列在忆阻器阵列的行方向和列方向上均不重叠；将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个模拟信号进行卷积处理，在忆阻器阵列的多个行信号输出端分别得到执行卷积处理后的多个第二模拟信号。
该基于忆阻器阵列的数据处理方法通过将卷积参数矩阵多次映射于忆阻器阵列中不同的多个忆阻器子阵列，进行一次计算(或一个计算周期)即可得到卷积处理操作的所有结果值，这大大减少了数据移位所需的时间，降低了功耗，提高了计算速度。
本公开的至少一实施例还提供该基于忆阻器阵列的数据处理方法对应的电子装置。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1示出了一种忆阻器阵列的示意性结构，该忆阻器阵列由多个忆阻器单元构成，该多个忆阻器单元构成一个m行n列的阵列，m和n均为正整数。每个忆阻器单元包括开关元件和一个或多个忆阻器。在图1中，WL<1>、WL<2>……WL<m>分别表示第一行、第二行……第m行的字线，每一行的忆阻器单元中的开关元件的控制极(例如晶体管的栅极)和该行对应的字线连接；BL<1>、BL<2>……BL<n>分别表示第一列、第二列……第n列的位线，每一列的忆阻器单元中的忆阻器和该列对应的位线连接；SL<1>、SL<2>……SL<m>分别表示第一行、第二行……第m行的源线，每一行的忆阻器单元中的晶体管的源极和该行对应的源线连接。根据基尔霍夫定律，通过 设置忆阻器单元的状态(例如阻值)并且在字线与位线施加相应的字线信号与位线信号，上述忆阻器阵列可以并行地完成乘累加计算。
图1的忆阻器阵列中的忆阻器单元例如可以具有1T1R结构或者2T2R结构，其中，1T1R结构的忆阻器单元包括一个晶体管和一个忆阻器，2T2R结构的忆阻器单元包括两个晶体管和两个忆阻器。需要说明的是，本公开对忆阻器单元的结构不作限制，也可以采用可以实现乘累加运算的其他结构形式的忆阻器单元。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管(例如MOS场效应晶体管)或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极(即源极和漏极)，直接描述了其中一极为第一极，而另一极为第二极。
图2A为1T1R结构的忆阻器单元的示意图。如图2A所示，1T1R结构的忆阻器单元包括一个晶体管M1和一个忆阻器R1。
本公开的实施例对采用的晶体管的类型不作限定，例如当晶体管M1采用N型晶体管时，其栅极和字线WL连接，例如字线WL输入高电平时晶体管M1导通；晶体管M1的第一极可以是源极并配置为和源线SL连接，例如晶体管M1可以通过源线SL接收复位电压；晶体管M1的第二极可以是漏极并配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线BL连接，例如忆阻器R1可以通过位线BL接收置位电压。例如当晶体管M1采用P型晶体管时，其栅极和字线WL连接，例如字线WL输入低电平时晶体管M1导通；晶体管M1的第一极可以是漏极并配置为和源线SL连接，例如晶体管M1可以通过源线SL接收复位电压；晶体管M1的第二极可以是源极并配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线BL连接，例如忆阻器R1可以通过位线BL接收置位电压。需要说明的是，忆阻器结构还可以实现为其他结构，例如忆阻器R1的第二极与源线SL连接的结构，本公开的实施例对此不作限制。
下面各实施例均以晶体管M1采用N型晶体管为例进行说明。
字线端WL的作用是对晶体管M1的栅极施加相应电压，从而控制晶体管M1导通或关闭。在对忆阻器R1进行操作时，例如进行置位操作或复位操作，均需要先开启晶体管M1，即需要通过字线端WL对晶体管M1的栅极施 加导通电压。在晶体管M1导通后，例如，可以通过在源线端SL和位线端BL向忆阻器R1施加电压，以改变忆阻器R1的阻态。例如，可以通过位线端BL施加置位电压，以使得该忆阻器R1处于低阻态；又例如，可以通过源线端SL施加复位电压，以使得该忆阻器R1处于高阻态。例如，高阻态的电阻值为低阻态的电阻值100倍以上，例如1000倍以上。
需要说明的是，在本公开的实施例中，通过字线端WL和位线端BL同时施加电压，可以使得忆阻器R1的电阻值越来越小，即忆阻器R1从高阻态变为低阻态，将使得忆阻器R1从高阻态变为低阻态的操作称为置位操作；通过字线端WL和源线端SL同时施加电压，可以使得忆阻器R1的电阻值越来越大，即忆阻器R1从低阻态变为高阻态，将使得忆阻器R1从低阻态变为高阻态的操作称为复位操作。例如，忆阻器R1具有阈值电压，在输入电压幅度小于忆阻器R1的阈值电压时，不会改变忆阻R1的电阻值(或电导值)。在这种情况下，可以通过输入小于阈值电压的电压，利用忆阻器R1的电阻值(或电导值)进行计算；可以通过输入大于阈值电压的电压，改变忆阻器R1的电阻值(或电导值)。
图2B为2T2R结构的忆阻器单元的示意图。如图2B所示，2T2R结构的忆阻器单元包括两个晶体管M1和M2以及两个忆阻器R1和R2。下面以晶体管M1和M2均采用N型晶体管为例进行说明。
晶体管M1的栅极和字线端WL1相连，例如M1的字线端WL1输入高电平时晶体管M1导通，晶体管M2的栅极和字线端WL2相连，例如M2的字线端WL2输入高电平时晶体管M2导通；晶体管M1的第一极可以是源极并被配置为和源线端SL连接，例如晶体管M1可以通过源线端SL接收复位电压，晶体管M2的第一极可以是源极并被配置为和源线端SL连接，例如晶体管M2可以通过源线端SL接收复位电压，晶体管M1的第一极与晶体管M2的第一极相连，并一起连接至源线端SL。晶体管M1的第二极可以是漏极并被配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线端BL1连接，例如忆阻器R1可以通过位线端BL1接收置位电压；晶体管M2的第二极可以是漏极并被配置为和忆阻器R2的第二极(例如负极)连接，忆阻器R2的第一极(例如正极)和位线端BL2连接，例如忆阻器R2可以通过位线端BL2接收置位电压。
需要说明的是，2T2R结构的忆阻器单元中的晶体管M1和M2也可以均 采用P型晶体管，这里不再赘述。
图3为本公开至少一实施例提供的一种基于忆阻器阵列的数据处理方法的示意性流程图。
例如，如图3所示，本公开实施例提供的基于忆阻器阵列的数据处理方法包括步骤S110至S130，并且，该忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算(也即乘积累加运算，将乘法的乘积结果进行累加处理，以得到乘加结果累加后的和值)，例如，该忆阻器阵列的结构示意图如图1所示，每个忆阻器单元可以为如图2A所示的1T1R结构或者如图2B所示的2T2R结构。
在步骤S110，获取多个第一模拟信号。
在步骤S120，设置忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入忆阻器阵列，其中，卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，多个参数元素对应地按照第一矩阵的形式被多次分别映射于忆阻器阵列中不同的多个忆阻器子阵列，且多个忆阻器子阵列在忆阻器阵列的行方向和列方向上均不重叠。
在步骤S130，将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个模拟信号进行卷积处理，在忆阻器阵列的多个行信号输出端分别得到执行卷积处理后的多个第二模拟信号。
例如，多个第一模拟信号为待进行卷积处理的输入信号，多个第二模拟信号为对输入信号执行卷积处理后的输出信号，例如，第一模拟信号为模拟电压信号，第二模拟信号为模拟电流信号。
例如，第二模拟信号的个数可以根据计算需要设定。例如，第二模拟信号的个数可以为(N+Q-1)，这里N表示第一模拟信号的个数，Q表示卷积参数矩阵的列数，对应的，忆阻器阵列的行数也可以根据第二模拟信号的个数变化对应设置，例如，第二模拟信号的个数还可以其他形式得到，本公开的实施例对此不作限制。
例如，卷积处理用于对输入信号进行信号滤波处理，卷积参数矩阵中的每行参数元素表示一个滤波系数向量，例如，卷积参数矩阵的行数大于等于1，例如为1时，则卷积参数矩阵表示一个用于执行特定滤波处理的滤波系数向量。
例如，用于滤波处理的滤波器是有限脉冲响应滤波器，例如，多个有限脉 冲响应滤波器可以构成一个有限脉冲相响应滤波器组。有限脉冲响应滤波器组的输入输出关系可以由下面的公式(1)表示：
Figure PCTCN2021137845-appb-000001
在上述公式(1)中，m表示在滤波器组中的序号，M表示滤波器组中的滤波器总个数，K表示滤波器阶数，x表示输入信号向量，y表示输出信号向量，h m(k)表示第m个滤波器的滤波系数向量，n例如可以表示某个时刻。
例如，卷积参数矩阵可以表示滤波器组，也即卷积参数矩阵由多个滤波系数向量组成，例如，卷积参数矩阵的行数有至少一行，每行参数元素表示一个滤波系数向量，不同行的参数元素表示不同滤波器的滤波系数向量，例如每行参数元素为公式(1)中的h m(k)。
例如，当卷积参数矩阵由多个滤波系数向量组成时，利用忆阻器可以进行乘累加计算的特点，可以并行对输入信号进行处理，不仅能够在一个计算周期得到卷积处理的全部结果值，在此基础上还可以同时得到不同滤波器的卷积处理的结果，加快处理速度，提升计算效率。
例如，当待进行卷积处理的信号为数字信号时，需要将数字信号通过数模转换器变为模拟信号，再通过忆阻器阵列进行计算。目前，基于忆阻器阵列的全模拟计算需要多次将待计算的数字信号转换为模拟信号，以作为忆阻器的输入，因此这种方式还需要大量次数的数模转换才能完成一次完整的卷积处理。
例如，在一些示例中，步骤S110可以包括：获取多个初始数字信号；对多个初始数字信号进行数模转换处理，以分别得到多个第一模拟信号。
例如，多个初始数字信号可以为预先存储的数字信号；例如，多个初始数字信号可以为实时获取的数字信号。将多个初始数字信号进行数模转换处理以得到多个第一模拟信号。
在本公开至少一实施例提供的信号处理方法中，模数转换处理仅执行一次，将得到的多个第一模拟信号输入忆阻器阵列中即可得到所有的卷积处理的结果值，从而大大减少了多次模数转换带来的转换时间，进一步提高了计算速度。
例如，在另一些示例中，可以通过对连续的模拟信号进行采样，得到多个第一模拟信号。
例如，步骤S110可以包括：获取初始模拟电压信号，初始模拟电压信号 的长度为预设时长；将初始模拟电压信号的电压值调整至预设电压范围内，以得到调整后模拟电压信号；以预设采样频率对调整后模拟电压信号进行采样，以得到分别对应于预设时长内的不同时刻的多个第一模拟信号。
对于步骤S120，例如，每个忆阻器子阵列对应于第一矩阵，不同的忆阻器子阵列分别对应于不同的列信号输入端，多个参数元素对应地按照第一矩阵的形式被多次分别映射于忆阻器阵列中不同的多个忆阻器子阵列，这可以包括：从多个列信号输入端中，依次选择需要进行卷积处理的对象列组，其中，每个对象列组包括至少一个列信号输入端；对于每个被选择的对象列组，将多个参数元素对应地按照第一矩阵的形式映射到对象忆阻器子阵列中，其中，对象忆阻器子阵列为多个忆阻器子阵列中对应于被选择的对象列组的忆阻器子阵列。
例如，每个忆阻器子阵列包括多个目标忆阻器单元。对于每个被选择的对象列组，将多个参数元素对应地按照第一矩阵的形式，映射到对象忆阻器子阵列中，包括：将第一矩阵中同一行的参数元素分别映射于对象忆阻器子阵列中同一行的目标忆阻器单元；将第一矩阵中同一列的参数元素分别映射于对象忆阻器子阵列中同一列的目标忆阻器单元。
例如，卷积参数矩阵的每行包括Q个参数元素，每个忆阻器单元包括至少一个忆阻器，每个忆阻器可被设置为初始状态，例如，初始状态可以为忆阻器在初始化后的高阻状态(低电导状态)。将第一矩阵的同一行参数元素映射于对象忆阻器子阵列中同一行的目标忆阻器单元，包括：对于卷积参数矩阵的每行参数元素，在忆阻器阵列中对应于对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于Q个参数元素，再将一行忆阻器单元中除Q个目标忆阻器单元外的忆阻器单元中的忆阻器设置为初始状态，其中，Q为大于1的正整数。
例如，在忆阻器阵列中对应于对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于Q个参数元素，包括：根据Q个参数元素中每个参数元素的数值，将选择的Q个目标忆阻器单元中包括的忆阻器整体上设定为可用于计算的导电状态且具有对应于数值的电导值。
根据上文描述的忆阻器的特性，例如，可以通过在列信号输入端(也即位线端BL)和行信号输出端(也即源线端SL)向忆阻器施加置位电压或者重置电压来改变忆阻器的电导值，从而可以使得每个忆阻器具有不同的电导值，也 即通过改变忆阻器的电导值来改变滤波器的滤波系数向量，从而设计出符合滤波要求的滤波器。
例如，每个忆阻器单元可以为1T1R结构，如图2A所示，也即每个忆阻器单元包括1个忆阻器，通过该忆阻器的电导值表示对应的参数元素。
例如，每个忆阻器单元可以为2T2R结构，如图2B所示，也即每个忆阻器单元包括两个忆阻器，在获取多个第一模拟信号之后，该方法还可以包括：获取多个第一模拟信号分别对应的多个反相模拟信号，其中，两个忆阻器中的一个忆阻器用于接收多个第一模拟信号中选择的一个第一模拟信号，另一个忆阻器用于接收该选择的一个第一模拟信号对应的反相模拟信号。
例如，当忆阻器单元为2T2R结构时，可以利用两个忆阻器的电导值实现参数元素的负值，从而可以利用多个目标忆阻器单元实现更加丰富、复杂的卷积处理。
例如，从多个列信号输入端中，依次选择需要进行卷积处理的对象列组，可以包括：按照卷积处理的平移步长，从多个列信号输入端中，依次选择需要进行卷积处理的对象列组。
例如，对于卷积处理y＝x T*W，这里，“*”代表卷积运算，x表示输入向量且为N维列向量，W表示参数元素排布为P行M列的卷积参数矩阵，则卷积处理也可以重新写作y＝x TH,其中，H＝[O 11,W；O 21,W,O 22；…；W,O s1]，这里，H为(N+M-1)行N列的矩阵，O a(a表示任意下标)表示零矩阵，零矩阵的行数为P行，各个零矩阵的列数可以按照由卷积参数矩阵W所划分得到的分块矩阵的要求唯一确定，这里，P、M和N均为正整数，且M和N均大于1。
图4为本公开至少一实施例提供的一种写入卷积参数矩阵后的忆阻器阵列的示意图。
例如，卷积处理用于信号滤波处理，卷积参数矩阵为W＝[w 11,w 12,...,w 1M；w 21,w 22,...,w 2M；...；w P1,w P2,...,w PM]。卷积参数矩阵中的第一行参数元素[w 11,w 12,...,w 1M]表示滤波系数向量(1)，卷积参数矩阵中的第二行参数元素[w 21,w 22,...,w 2M]表示滤波系数向量(2)，...，卷积参数矩阵中的第P行参数元素[w P1,w P2,...,w PM]表示滤波系数向量(P)。
例如，忆阻器阵列可以包括(N+M-1)行、N列，忆阻器阵列的列信号输入端分别输入N个第一模拟信号，也即x 1,x 2,x 3,...,x N，忆阻器阵列的行信号 输出端分别输出(N+M-1)个第二模拟信号，也即y 1,y 2,y 3,..,y N-M+1，行列线交汇处的黑色方块表示一个忆阻器单元。例如，忆阻器单元旁的数字“0”表示该忆阻器单元的忆阻器处于初始状态，忆阻器单元旁的标记“w ij”表示该忆阻器单元的忆阻器的电导值为参数元素“w ij”的数值，这里i和j均为正整数，i小于等于P，j小于等于M。
如图4所示，卷积参数矩阵被映射于忆阻器子阵列(1)、……、忆阻器子阵列(n)、……、忆阻器子阵列(N-M+1)等忆阻器子阵列中，以同时得到对N个第一模拟信号进行卷积处理后的结果y 1,y 2,y 3,……,y N-M+1，这里，n为大于1且小于(N-M+1)的正整数。
例如，结合公式(1)，各个忆阻器子阵列分别对应不同的对象列组，例如，如图4所示，忆阻器子阵列(1)对应的对象列组包括M个列信号输入端，且这M个列信号输入端所输入的第一模拟信号分别为x1至x M。
例如，如图4所示，各个忆阻器子阵列在忆阻器阵列的行方向和列方向上均不重叠，并且，当卷积处理的平移步长为a时，按照平移步长a来依次选择需要进行卷积处理的对象列组，例如，对象列组(1)可以为第一模拟信号x 1至x M，对象列组(2)可以为第一模拟信号x a至x a+M，以此类推得到需要进行卷积处理的对象列组，这里，a为正整数。
例如，当多个第一模拟信号的相对位置关系如图4所示时，忆阻器子阵列从忆阻器阵列的左上角(或右下角)开始，每个忆阻器子阵列依次向左(或向右)移动a列，a＝1。需要说明的是，当多个第一模拟信号的相对位置关系变化时，忆阻器子阵列的移动方向也会随之发生变化，本公开的实施例对此不作限制。
对于步骤S130，例如，可以将多个第一模拟信号分别施加至设置后的忆阻器阵列的多个列信号输入端，同时将开启信号施加至忆阻器阵列的多个信号控制端，检测并获取忆阻器阵列的多个行信号输出端的多个电流信号，并基于多个电流信号得到多个第二模拟信号。
图5A为本公开至少一实施例提供的一种写入卷积参数矩阵后的忆阻器阵列的示意图。
例如，卷积参数矩阵W＝[W 1；W 2]＝[G 1[0],G 1[1],G 1[2],G 1[3]；G 2[0],G 2[1],G 2[2],G 2[3]]，也即第一矩阵为参数元素排布为2行4列的矩阵，行向量W 1为对应于第一滤波器的滤波系数向量，行向量W 2为对应于第二滤波器的滤波系 数向量，G 1[0]至G 1[3]和G 2[0]至G 2[3]分别为参数元素。
例如，如图5A所示，忆阻器阵列包括14行、10列，例如，其是一个更大的忆阻器阵列的一部分。忆阻器阵列的示意图中每个方框表示一个忆阻器单元，方框中的文字表示忆阻器单元中的忆阻器的电导值，例如，“0”表示忆阻器单元的忆阻器处于初始状态，例如可以将忆阻器单元中的忆阻器复位至高阻值的状态使其处于初始状态，忆阻器初始状态的电阻值远大于置位状态的电阻值，如果将初始状态的电阻值视为无穷大，则其倒数对应于0。例如，“G 1[0]”至“G 1[3]”和“G 2[0]”至“G 2[3]”表示忆阻器单元的忆阻器的电导值为参数元素的数值。每个忆阻器单元可以为1T1R结构，也可以为2T2R结构。
例如，图5A中的V[0]至V[9]分别为10个第一模拟信号，分别输入10个列信号输入端，图5A中的I 1[0]至I 1[6]和I 2[0]至I 2[6]分别为14个行信号输出端所输出的14个第二模拟信号。
例如，如图5A所示，每个由粗实线框所限定的2行4列的忆阻器单元为忆阻器子阵列，多个忆阻器子阵列在忆阻器阵列的行方向和列方向上均不重叠，不同的忆阻器子阵列分别对应于不同的列信号输入端。
例如，选择第一模拟信号V[0]至第一模拟信号V[3]为对象列组(1)，位于忆阻器阵列的第一行和第二行的忆阻器子阵列为对应于对象列组(1)的对象忆阻器子阵列，将参数元素G 1[0]至G 1[3]和G 2[0]至G 2[3]按照第一矩阵形式映射至该对象忆阻器子阵列中。
例如，如图5A所示，参数元素G 1[0]至G 1[3]映射至第一行中的4个目标忆阻器单元(也即忆阻器阵列中以左上角为起始的第1行第7列至第1行第10列的忆阻器单元)，4个目标忆阻器单元一一对应于4个参数元素G 1[0]至G 1[3]，第一行中的除这4个目标忆阻器单元外的6个忆阻器单元中的忆阻器设置为初始状态，也即图5A中第1行第1列至第1行第6列的“0”。
例如，参数元素G 2[0]至G 2[3]映射至第二行中的4个目标忆阻器单元(也即忆阻器阵列中的第2行第7列至第2行第10列的忆阻器单元)，4个目标忆阻器单元一一对应于4个参数元素G 2[0]至G 2[3]，第二行中的除这4个目标忆阻器单元外的6个忆阻器单元中的忆阻器设置为初始状态，也即图5A中第2行第1列至第2行第6列的“0”。
例如，选择第一模拟信号V[1]至第一模拟信号V[4]为对象列组(2)，位于忆阻器阵列的第三行和第四行的忆阻器子阵列为对应于对象列组(2)的对 象忆阻器子阵列，将参数元素G 1[0]至G 1[3]和G 2[0]至G 2[3]按照第一矩阵形式映射至该对象忆阻器子阵列中，具体映射过程如前所述，这里不再赘述。
例如，选择第一模拟信号V[2]至第一模拟信号V[5]为对象列组(3)，位于忆阻器阵列的第五行和第六行的忆阻器子阵列为对应于对象列组(3)的对象忆阻器子阵列，将参数元素G 1[0]至G 1[3]和G 2[0]至G 2[3]按照第一矩阵形式映射至该对象忆阻器子阵列中，具体映射过程如前所述，这里不再赘述。
以此类推，将参数元素G 1[0]至G 1[3]和G 2[0]至G 2[3]按照第一矩阵形式分别映射至不同的忆阻器子阵列中，以得到如图5A所示的忆阻器阵列。
例如，将10个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个模拟信号进行卷积处理。根据基尔霍夫定律，忆阻器阵列的输出电流可以根据下述公式(2)得出：
Figure PCTCN2021137845-appb-000002
其中，j＝1,…,M，k＝1,…,N。
在上述公式(2)中，V k表示多个列信号输入端中第k个列信号输入端输入的电压，I j表示多个行信号输出端中第j个行信号输出端输出的电流信号。G jk表示位于第j行第k列的忆阻器单元整体电导值。根据基尔霍夫定律可知，忆阻器阵列可以并行地完成乘累加计算。
例如，对于图5A中第一个行信号输出端输出的第二模拟信号I 1[0]，结合公式(2)可以得到，I 1[0]＝V[3]*G 1[0]+V[2]*G 1[1]+V[1]*G 1[2]+V[0]*G 1[3]，参考公式(1)可以看出，第二模拟信号I 1[0]为对对象列组(1)中的4个第一模拟信号执行卷积处理后的卷积结果。
同样的，对于图5A中第三个行信号输出端输出的第二模拟信号I 1[1]，结合公式(2)可以得到，I 1[1]＝V[4]*G 1[0]+V[3]*G 1[1]+V[2]*G 1[2]+V[1]*G 1[3]，参考公式(1)可以看出，第二模拟信号I 1[1]为对对象列组(2)中的4个第一模拟信号执行卷积处理后的卷积结果。
以此类推，在忆阻器阵列的14个行信号输出端分别得到执行卷积处理后的14个第二模拟信号，也即图5A中的I 1[0]至I 1[6]和I 2[0]至I 2[6]，其中，I 1[0]至I 1[6]为7个对应于第一滤波器的卷积处理结果，I 2[0]至I 2[6]为7个对应于第二滤波器的卷积处理结果。
图5B为本公开至少一实施例提供的另一种写入卷积参数矩阵后的忆阻器阵列的示意图，该实施例可以与图5A所示的实施例实现相同的卷积的计 算。
例如，图5B所示的忆阻器阵列、卷积参数矩阵、10个第一模拟信号以及对象列组的定义与图5A完全相同，这里不再赘述。
例如，将忆阻器阵列中位于左上角的忆阻器单元作为位于第一行第一列的忆阻器单元，对应于对象列组(1)的对象忆阻器阵列为位于忆阻器阵列第一行第7列至第一行第10列的4个目标忆阻器单元以及位于忆阻器阵列第八行第7列至第八行第10列的4个目标忆阻器单元，参数元素G 1[0]至G 1[3]和G 2[0]至G 2[3]尽管分开设置在不再直接相邻的两行中，但是仍然构成一个子阵列。同样的，对应于对象列组(2)的对象忆阻器阵列为位于忆阻器阵列第二行第6列至第二行第9列的4个目标忆阻器单元以及位于忆阻器阵列第九行第6列至第九行第9列的4个目标忆阻器单元，以此类推，这里不再赘述。
例如，每行参数元素包括Q个参数元素，对于卷积参数矩阵的每行参数元素，例如第一行参数元素G 1[0]至G 1[3]或第二行参数元素G 2[0]至G 2[3]，将每行参数元素映射至忆阻器阵列中的多个忆阻器行，每个忆阻器行包括的Q个目标忆阻器单元一一对应于Q个参数元素，例如，将第一行参数元素映射至忆阻器阵列中的第一行至第七行，将第二行参数元素映射至忆阻器阵列中的第八行至第十四行，例如，如图5B所示，对于忆阻器阵列中的第一行至第七行，每个忆阻器行包括4个目标忆阻器单元，且这4个目标忆阻器单元一一对应于4个参数元素G 1[0]至G 1[3]，对于忆阻器阵列中的第八行至第十四行，每个忆阻器行包括4个目标忆阻器单元，且这4个目标忆阻器单元一一对应于4个参数元素G 2[0]至G 2[3]。
例如，如图5A和图5B所示，忆阻器子阵列的大小与卷积参数矩阵的大小相同，例如，卷积参数矩阵为P行Q列的第一矩阵形式，忆阻器子阵列也包括P行Q列个目标忆阻器单元。
需要说明的是，在本公开中，忆阻器阵列中的一个忆阻器行唯一对应于卷积参数矩阵中的一行参数元素，本公开对于忆阻器子阵列中的每行目标忆阻器单元之间的位置关系以及每个忆阻器行中的目标忆阻器单元之间的位置关系不作限制。
例如，如图5A和图5B所示，忆阻器子阵列中的每行目标忆阻器单元可以是彼此相邻且连续的多个目标忆阻器单元，例如，根据多个第一模拟信号之间的相对位置关系的变化，忆阻器子阵列中的每行目标忆阻器单元也可以是 不连续的多个目标忆阻器单元，本公开对此不作限制。
例如，当忆阻器子阵列包括多行目标忆阻器单元时，忆阻器子阵列中的每行目标忆阻器单元之间不限制为相邻的形式，例如，如图5A所示，每个忆阻器子阵列中的两行目标忆阻器单元彼此相邻，或者如图5B所示，每个忆阻器子阵列中的两行目标忆阻器单元彼此不相邻，本公开对此不作限制。
例如，参数元素的数值可能为正数也可能为负数，例如，每个参数元素可以利用两个忆阻器的电导值来表示，例如，利用两个忆阻器的电导值之差来代表一个参数元素，或者，利用两个忆阻器的电导值之和来代表一个参数元素。
例如，卷积参数矩阵为排布成2*P行Q列的第一矩阵，卷积参数矩阵包括P行Q列的第一子卷积参数矩阵和对应的P行Q列的第二子卷积参数矩阵，第一子卷积参数矩阵和第二子卷积参数矩阵中对应行列位置的参数元素共同表示执行卷积处理的一个参数元素，由此得到运算后实质上的P行Q列的卷积参数矩阵，其中P为大于等于1的正整数，Q为大于1的正整数。例如，“对应行列位置”指忆阻器阵列中在行方向和列方向上对应的位置。
此时对于步骤S130，例如，第一子卷积参数矩阵包括P行第一参数元素，第二子卷积参数矩阵包括P行第二参数元素，P行第一参数元素与P行第二参数元素的行列位置一一对应，在忆阻器阵列的多个行信号输出端分别得到执行卷积处理后的多个第二模拟信号，包括：针对每个忆阻器子阵列，确定至少一组待处理行，其中，每组待处理行包括与一行第一参数元素所对应的一行目标忆阻器单元，以及与对应于一行第一参数元素的一行第二参数元素所对应的一行目标忆阻器单元；对每组待处理行包括的两行目标忆阻器单元分别对应的两个行信号输出端的电流信号进行电流预处理，以得到每组待处理行对应的第二模拟信号。
例如，电流预处理为电流相减处理或电流相加处理。
例如，卷积参数矩阵W’＝[W +；W -]＝[G +[0],G +[1],G +[2],G +[3]；G -[0],G -[1],G -[2],G -[3]]，第一矩阵为参数元素排布为2行4列的矩阵，行向量W +为第一子卷积参数矩阵，第一子卷积参数矩阵包括一行第一参数元素(G +[0],G +[1],G +[2])，行向量W -为第二子卷积参数矩阵，第二子卷积参数矩阵包括一行第二参数元素(G -[0],G -[1],G -[2],G -[3])。
参数元素G +[0]和参数元素G -[0]共同表示执行卷积处理的参数元素G[0]，参数元素G +[1]和参数元素G -[1]共同表示执行卷积处理的参数元素G[1]，参 数元素G +[2]和参数元素G -[2]共同表示执行卷积处理的参数元素G[2]，参数元素G +[3]和参数元素G -[3]共同表示执行卷积处理的参数元素G[3]，也即是，用于执行卷积处理的滤波系数向量为(G[0],G[1],G[2],G[3])，滤波系数向量由第一子卷积参数矩阵和对应的第二子卷积参数矩阵共同表示，从而可以利用第一子卷积参数矩阵和对应的第二子卷积参数矩阵实现参数元素的负值，以执行更加丰富、复杂的卷积处理。
图6为本公开至少一实施例提供的再一种写入卷积参数矩阵后的忆阻器阵列的示意图。
例如，图6中的V[0]至V[9]分别为10个第一模拟信号，分别输入10个列信号输入端，图6中的I +[0]至I +[6]和I -[0]至I -[6]分别为14个行信号输出端所输出的14个电流信号，基于14个电流信号得到7个第二模拟信号I[0]至I[6]。
例如，将卷积参数矩阵W’按照第一矩阵的形式多次映射至忆阻器阵列中不同的多个忆阻器子阵列，每个忆阻器子阵列如图6中黑色粗实线标记的区域所示，以得到图6所示的忆阻器阵列，每个忆阻器阵列对应的卷积参数矩阵W’为运算后实质上的1行4列的卷积参数矩阵，具体过程如前所述，这里不再赘述。
例如，每个用于执行卷积处理的参数元素由第一子卷积参数矩阵W +和第二子卷积参数矩阵W -中对应行列位置的参数元素之差表示。
例如，对于位于忆阻器阵列中的第一行和第二行的、由黑色粗实线框标记的忆阻器子阵列(1)，其对应的一组待处理行包括位于忆阻器阵列第一行中的一行目标忆阻器单元，以及位于忆阻器阵列第二行中的一行目标忆阻器单元。例如，将忆阻器阵列中的第一行的行信号输出端的电流信号I +[0]和第二行的行信号输出端的电流信号I -[0]相减，以得到第二模拟信号I[0]。
例如，对于位于忆阻器阵列中的第三行和第四行的、由黑色粗实线标记的忆阻器子阵列(2)，其对应的一组待处理行包括位于忆阻器阵列第三行中的一行目标忆阻器单元，以及位于忆阻器阵列第四行中的一行目标忆阻器单元。例如，将忆阻器阵列中的第三行的行信号输出端的电流信号I +[1]和第四行的行信号输出端的电流信号I -[1]相减，以得到第二模拟信号I[1]。
以此类推，按照上述方式得到第二模拟信号I[2]至第二模拟信号[6]，以得到执行卷积处理后的7个第二模拟信号。
例如，还可以利用两个对应设置的第一忆阻器阵列和第二忆阻器阵列，并将对应的行信号输出端的电流信号进行预处理以得到第二模拟信号，以实现参数元素的负值，执行更加丰富、复杂的卷积处理。
例如，忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，卷积参数矩阵包括第一子卷积参数矩阵和第二子卷积参数矩阵，第一子卷积参数矩阵和第二子卷积参数矩阵均为第一矩阵形式，第一子卷积参数矩阵对应地按照第一矩阵的形式被多次映射于第一忆阻器阵列中不同的多个忆阻器子阵列，第二子卷积参数矩阵对应地按照第一矩阵的形式被多次映射于第二忆阻器阵列中不同的多个忆阻器子阵列。
此时对于步骤S130，例如，在忆阻器阵列的多个行信号输出端分别得到执行卷积处理后的多个第二模拟信号，可以包括：对第一忆阻器阵列中的每个行信号输出端的电流信号和第二忆阻器阵列中对应的行信号输出端的电流信号进行电流预处理，以得到多个第二模拟信号。
例如，电流预处理为电流相减处理或电流相加处理。
例如，卷积参数矩阵W’＝[W +；W -]＝[G +[0],G +[1],G +[2],G +[3]；G -[0],G -[1],G -[2],G -[3]]，第一矩阵为参数元素排布为1行4列的矩阵，也即一个4维行向量。行向量W +为第一子卷积参数矩阵，行向量W -为第二子卷积参数矩阵，第一子卷积参数矩阵和第二子卷积参数矩阵均为第一矩阵形式。
同样的，第一子卷积参数矩阵和第二子卷积参数矩阵中对应行列位置的参数元素共同表示执行所述卷积处理的一个参数元素。例如，参数元素G +[0]和参数元素G -[0]共同表示执行卷积处理的参数元素G[0]，参数元素G +[1]和参数元素G -[1]共同表示执行卷积处理的参数元素G[1]，参数元素G +[2]和参数元素G -[2]共同表示执行卷积处理的参数元素G[2]，参数元素G +[3]和参数元素G -[3]共同表示执行卷积处理的参数元素G[3]，也即是，用于执行卷积处理的滤波系数向量为(G[0],G[1],G[2],G[3])，滤波系数向量由第一子卷积参数矩阵和对应的第二子卷积参数矩阵共同表示，从而可以利用第一子卷积参数矩阵和对应的第二子卷积参数矩阵实现参数元素的负值，以执行更加丰富、复杂的卷积处理。
图7为本公开至少一实施例提供的再一种写入卷积参数矩阵后的忆阻器阵列的示意图，该实施例可以与图6所示的实施例实现相同的卷积的计算。
图7所示的忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，每个忆 阻器阵列具有独立的控制电路，例如具有独立的列信号输入端，以分别输入10个第一模拟信号V[0]至V[9]，以及独立的行信号输出端，以输出电流信号I +[0]至电流信号I +[6]和电流信号I -[0]至电流信号I -[6]。例如，图7中的I[0]至I[6]表示7个经过卷积处理后的第二模拟信号。
例如，将卷积参数矩阵W’中的第一子卷积参数矩阵W +按照第一矩阵的形式多次映射至第一忆阻器阵列中不同的多个忆阻器子阵列，将卷积参数矩阵W’中的第二子卷积参数矩阵W -按照第一矩阵的形式多次映射至第二忆阻器阵列中不同的多个忆阻器子阵列，以得到图7所示的忆阻器阵列，具体过程如前所述，这里不再赘述。
例如，每个用于执行卷积处理的参数元素由第一子卷积参数矩阵W +和第二子卷积参数矩阵W -中对应行列位置的参数元素之差表示。
例如，将第一忆阻器阵列中的第一行的行信号输出端的电流信号I +[0]和第二忆阻器阵列中的第一行的行信号输出端的电流信号I -[0]相减，以得到第二模拟信号I[0]。
例如，将第一忆阻器阵列中的第二行的行信号输出端的电流信号I +[1]和第二忆阻器阵列中的第二行的行信号输出端的电流信号I -[1]相减，以得到第二模拟信号I[1]。
以此类推，如图7所示，按照上述方式得到第二模拟信号I[2]至第二模拟信号[6]，以得到执行卷积处理后的7个第二模拟信号。
例如，本公开至少一实施例提供的基于忆阻器阵列的数据处理方法还可以包括：对多个第二模拟信号进行模数转换处理，以将多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
例如，图8为本公开至少一实施例提供的基于忆阻器阵列的数据处理方法的处理流程示意图。
下面结合图8，具体说明该基于忆阻器阵列的数据处理方法的执行过程。
首先，如图8所示，将对应于卷积处理的卷积参数矩阵的数据写入忆阻器阵列，具体过程如步骤S120所述，这里不再赘述。
接着，将用于进行卷积处理的初始数字信号转换为多个第一模拟信号，这里，第一模拟信号为模拟电压信号，具体过程如步骤S110所述，这里不再赘述。
最后，将多个第一模拟信号施加至对应的列信号输入端，以得到多个第二 模拟信号，并对多个第二模拟信号进行模数转换处理以得到数字化的滤波结果，具体过程如步骤S130所述，这里不再赘述。
该基于忆阻器阵列的数据处理方法可以实现一次计算(或一个计算周期)即可得到卷积处理操作的所有结果，大大减少了数据移位以及获取第一模拟信号过程中的模数转换次数和所需的时间，降低了功耗，提高了计算速度。
例如，本公开所提供的基于忆阻器阵列的数据处理方法可以用于神经信号的分析，例如，可以用于颅内系统设计，以对采集得到的初始神经信号进行处理，例如特征提取等，进一步降低卷积处理过程的功耗，提高运算速度，满足颅内系统设计严格的功耗和面积要求。
例如，初始神经信号可以为脑神经信号、脊神经信号等，初始神经信号包括但不限于各种动物的神经信号。
例如，当卷积参数矩阵包括多个滤波系数向量时，每个滤波系数向量用于提取不同的特征信息，从而可以并行的利用忆阻器阵列对多个初始神经信号进行多种不同的特征的提取，以得到多个第二模拟信号，也即多个特征信息，计算效率更高，功耗更低。
与上述基于忆阻器阵列的数据处理方法相对应，本公开至少一实施例还提供一种电子装置，图9A为本公开至少一实施例提供的一种电子装置的示意性框图。
如图9A所示，电子装置900包括忆阻器阵列901、信号获取装置902以及控制驱动电路903。忆阻器阵列901配置为能进行乘和运算，以上述执行卷积处理。信号获取装置902配置为获取多个第一模拟信号。控制驱动电路903被配置为执行步骤S120至S130。
例如，忆阻器阵列901可以采用图1所示的忆阻器阵列，忆阻器阵列包括阵列排布的多个忆阻器单元，例如，忆阻器阵列包括m行n列。例如，每个忆阻器单元包括忆阻器，每个忆阻器包括第一端和第二端，且该忆阻器能被设置为初始状态，也能被设置(置位)为具有一定电阻值的置位状态。当忆阻器处于初始状态时，其电阻值远大于处于置位状态的电阻。例如，每个忆阻器单元还包括开关元件，开关元件包括控制端、第一极和第二极，忆阻器的第一端与开关元件的第一极电连接。
例如，忆阻器阵列还包括m条字线、m条源线和n条位线。m条字线分别与m行对应，每条字线与一行忆阻器单元的各个开关元件的控制端电连接，m条 源线分别与m行对应；m条源线分别与m行对应，每条源线与一行忆阻器单元的各个开关元件的第二极电连接；n条位线分别于n列对应，且每条位线与一列忆阻器单元的各个忆阻器的第二端电连接。
例如，信号获取装置902包括数字信号获取电路和数模转换电路。例如，数字信号获取电路配置为获取多个初始数字信号；数模转换电路配置为对多个初始数字信号进行数模转换处理，以分别得到多个第一模拟信号。
例如，控制驱动电路903可以包括源线驱动电路、字线驱动电路和位线驱动电路。源线驱动电路配置为对多个第二模拟信号进行检测和对忆阻器阵列执行初始化操作；字线驱动电路配置为对忆阻器阵列的多个信号控制端施加开启信号和对忆阻器阵列执行初始化操作；位线驱动电路配置为对多个列信号输入端施加输入信号和对忆阻器阵列执行初始化操作，其中，输入信号至少包括多个第一模拟信号。
例如，控制驱动电路903可以通过位线驱动电路向忆阻器阵列的多个列信号输入端施加输入信号，通过字线驱动电路同时将开启信号施加至忆阻器阵列的多个信号控制端，最终通过源线驱动电路对设置后的忆阻器阵列的多个行信号输出端的电流信号进行处理，以得到多个第二模拟信号。
例如，电子装置900还可以进一步包括数据输出电路，其中，该数据输出电路配置为将多个第二模拟信号转换为数字信号，以将多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
需要说明的是，关于通过信号获取装置902获取多个第一模拟信号的具体说明可以参考上述基于忆阻器阵列的数据处理方法的实施例中图3所示的步骤S110的相关描述；控制驱动电路903用于实现图3所示的步骤S120至步骤S130，关于控制驱动电路903的具体说明可以参考上述基于忆阻器阵列的数据处理方法的实施例中图3所示的步骤S120至步骤S130的相关描述。此外，电子装置可以实现与前述基于忆阻器阵列的数据处理方法相似的技术效果，在此不再赘述。
图9B为本公开至少一实施例提供的一种电子装置示意图。例如，如图9B所示，电子装置包括信号获取装置、字线驱动电路、位线驱动电路、源线驱动电路、忆阻器阵列以及数据输出电路。
例如，信号获取装置配置为将数字信号通过DAC(Digital to Analog converter，数字模拟转换器)转换为多个第一模拟信号，以在进行卷积处理时 输入至忆阻器阵列的多个列信号输入端。
例如，忆阻器阵列包括M条源线、M条字线和N条位线，以及阵列排布为M行N列的多个忆阻器单元。例如，每个忆阻器单元为1T1R结构，将用于卷积处理的卷积参数矩阵多次映射于忆阻器阵列中不同的多个子阵列，具体过程如步骤S120所述，这里不再赘述。
例如，通过字线驱动电路、位线驱动电路和源线驱动电路实现卷积处理的过程如前所述，这里不再赘述。
例如，字线驱动电路包括多个多路选择器(Multiplexer，简称Mux)，用于切换字线输入电压，位线驱动电路包括多个多路选择器，用于切换位线输入电压，源线驱动电路也包括多个多路选择器，用于切换源线输入电压。
例如，忆阻器阵列包括操作模式和计算模式。当忆阻器阵列处于操作模式时，忆阻器单元处于初始化状态，可以将卷积参数矩阵中的参数元素的数值写入忆阻器阵列中。例如，将忆阻器的源线输入电压、位线输入电压和字线输入电压通过多路选择器切换至对应的预设电压区间。
例如，通过图9B中的字线驱动电路中的多路选择器的控制信号WL_sw[1:M]将字线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将字线输入电压设置为2V(伏特)，例如在对忆阻器进行复位操作时，将字线输入电压设置为5V，例如，字线输入电压可以通过图9B中的电压信号V_WL[1:M]得到。
例如，通过图9B中的源线驱动电路中的多路选择器的控制信号SL_sw[1:M]将源线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将字线输入电压设置为0V，例如在对忆阻器进行复位操作时，将源线输入电压设置为2V，例如，源线输入电压可以通过图9B中的电压信号V_SL[1:M]得到。
例如，通过图9B中的位线驱动电路中的多路选择器的控制信号BL_sw[1:N]将位线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将位线输入电压设置为2V，例如在对忆阻器进行复位操作时，将位线输入电压设置为0V，例如，源线输入电压可以通过图9B中DAC得到。
当忆阻器阵列处于计算模式时，此时，忆阻器阵列中的忆阻器处于可用于计算的导电状态，列信号输入端输入的位线输入电压不会改变忆阻器的电导值，以通过忆阻器阵列执行乘和运算完成卷积处理。例如，通过图9B中的字 线驱动电路中的多路选择器的控制信号WL_sw[1:M]将字线输入电压切换至相应的电压区间，例如施加开启信号时，相应行的字线输入电压设置为5V，例如不施加开启信号时，相应行的字线输入电压设置为0V，例如接通GND信号；通过图9B中的源线驱动电路中的多路选择器的控制信号SL_sw[1:M]将源线输入电压切换至相应的电压区间，例如将源线输入电压设置为0V，从而使得多个行信号输出端的电流信号可以流入数据输出电路，通过图9B中的位线驱动电路中的多路选择器的控制信号BL_sw[1:N]将位线输入电压切换至相应的电压区间，例如将位线输入电压设置为0.1V-0.3V，从而利用忆阻器阵列可进行乘和运算的特性完成卷积操作。
例如，数据输出电路包括多个ADC(Analog to Digital converter，模拟数字转换器)，可以将多个行信号输出端的电流信号转换为数字信号，以用于后续处理。
图9C为本公开至少一实施例提供的另一种电子装置示意图。
图9C所示的电子装置与图9B所示的电子装置的结构相同，也包括信号获取装置、字线驱动电路、位线驱动电路、源线驱动电路、忆阻器阵列以及数据输出电路。
例如，忆阻器阵列包括M条源线、2M条字线和2N条位线，以及阵列排布为M行N列的多个忆阻器单元。例如，每个忆阻器单元为2T2R结构，将用于卷积处理的卷积参数矩阵多次映射于忆阻器阵列中不同的多个子阵列，具体过程如步骤S120所述，这里不再赘述。
需要说明的是，忆阻器阵列也可以包括M条源线、M条字线和2N条位线，以及阵列排布为M行N列的多个忆阻器单元。由于在执行步骤S130时为同时将开启信号施加至忆阻器阵列的多个信号控制端，可以由每条字线同时控制每行忆阻器单元中的两个忆阻器。
关于信号获取装置、控制驱动电路以及数据输出电路的描述如前所述，这里不再赘述。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离上述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而 形成的技术方案。
此外，虽然采用特定次序描绘了各操作，但是这不应当理解为要求这些操作以所示出的特定次序或以顺序次序执行来执行。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实施例中。相反地，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实施例中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种基于忆阻器阵列的数据处理方法，其中，所述忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算，所述方法包括：
    获取多个第一模拟信号；
    设置所述忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入所述忆阻器阵列，其中，所述卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，且所述多个忆阻器子阵列在所述忆阻器阵列的行方向和列方向上均不重叠；
    将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个模拟信号进行所述卷积处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号。
  2. 根据权利要求1所述的数据处理方法，其中，获取所述多个第一模拟信号，包括：
    获取多个初始数字信号；
    对所述多个初始数字信号进行数模转换处理，以分别得到所述多个第一模拟信号。
  3. 根据权利要求1所述的数据处理方法，其中，每个忆阻器子阵列对应于所述第一矩阵，不同的所述忆阻器子阵列分别对应于不同的列信号输入端，
    所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，包括：
    从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组，其中，每个对象列组包括至少一个列信号输入端；
    对于每个被选择的对象列组，将所述多个参数元素对应地按照所述第一矩阵的形式映射到对象忆阻器子阵列中，其中，所述对象忆阻器子阵列为所述多个忆阻器子阵列中对应于所述被选择的对象列组的忆阻器子阵列。
  4. 根据权利要求3所述的数据处理方法，其中，每个忆阻器子阵列包括多个目标忆阻器单元，
    对于每个被选择的对象列组，将所述多个参数元素对应地按照所述第一 矩阵的形式，映射到所述对象忆阻器子阵列中，包括：
    将所述第一矩阵中同一行的参数元素分别映射于所述对象忆阻器子阵列中同一行的目标忆阻器单元；
    将所述第一矩阵中同一列的参数元素分别映射于所述对象忆阻器子阵列中同一列的目标忆阻器单元。
  5. 根据权利要求4所述的数据处理方法，其中，所述卷积参数矩阵的每行包括Q个参数元素，
    每个忆阻器单元包括至少一个忆阻器，每个忆阻器可被设置为初始状态，
    将所述第一矩阵的同一行参数元素映射于所述对象忆阻器子阵列中同一行的目标忆阻器单元，包括：
    对于所述卷积参数矩阵的每行参数元素，在所述忆阻器阵列中对应于所述对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于所述Q个参数元素，再将所述一行忆阻器单元中除所述Q个目标忆阻器单元外的忆阻器单元中的忆阻器设置为所述初始状态，
    其中，Q为大于1的正整数。
  6. 根据权利要求5所述的数据处理方法，其中，在所述忆阻器阵列中对应于所述对象忆阻器子阵列的一行忆阻器单元中选择Q个目标忆阻器单元以一一对应于所述Q个参数元素，包括：
    根据所述Q个参数元素中每个参数元素的数值，将所述选择的Q个目标忆阻器单元中包括的忆阻器整体上设定为可用于计算的导电状态且具有对应于所述数值的电导值。
  7. 根据权利要求3-6中任一项所述的数据处理方法，其中，从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组，包括：
    按照所述卷积处理的平移步长，从所述多个列信号输入端中，依次选择需要进行所述卷积处理的对象列组。
  8. 根据权利要求1-7中任一项所述的数据处理方法，其中，所述卷积参数矩阵为排布成2*P行Q列的第一矩阵，
    所述卷积参数矩阵包括P行Q列的第一子卷积参数矩阵和对应的P行Q列的第二子卷积参数矩阵，
    所述第一子卷积参数矩阵和所述第二子卷积参数矩阵中对应行列位置的参数元素共同表示执行所述卷积处理的一个参数元素，其中P为大于等于1 的正整数，Q为大于1的正整数。
  9. 根据权利要求8所述的数据处理方法，其中，所述第一子卷积参数矩阵包括P行第一参数元素，所述第二子卷积参数矩阵包括P行第二参数元素，所述P行第一参数元素与所述P行第二参数元素的行列位置一一对应，
    在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号，包括：
    针对每个忆阻器子阵列，确定至少一组待处理行，其中，每组待处理行包括与一行第一参数元素所对应的一行目标忆阻器单元，以及与对应于所述一行第一参数元素的一行第二参数元素所对应的一行目标忆阻器单元；
    对每组待处理行包括的两行目标忆阻器单元分别对应的两个行信号输出端的电流信号进行电流预处理，以得到所述每组待处理行对应的第二模拟信号。
  10. 根据权利要求1-9任一项所述的数据处理方法，其中，所述忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，所述卷积参数矩阵包括第一子卷积参数矩阵和第二子卷积参数矩阵，所述第一子卷积参数矩阵和所述第二子卷积参数矩阵均为所述第一矩阵形式，
    所述第一子卷积参数矩阵对应地按照所述第一矩阵的形式被多次映射于所述第一忆阻器阵列中不同的多个忆阻器子阵列，
    所述第二子卷积参数矩阵对应地按照所述第一矩阵的形式被多次映射于所述第二忆阻器阵列中不同的多个忆阻器子阵列。
  11. 根据权利要求10所述的数据处理方法，其中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号，包括：
    对所述第一忆阻器阵列中的每个行信号输出端的电流信号和所述第二忆阻器阵列中对应的行信号输出端的电流信号进行电流预处理，以得到所述多个第二模拟信号。
  12. 根据权利要求9或11所述的数据处理方法，其中，所述电流预处理为电流相减处理或电流相加处理。
  13. 根据权利要求1-12任一项所述的数据处理方法，还包括：
    对所述多个第二模拟信号进行模数转换处理，以将所述多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
  14. 根据权利要求1-13任一项所述的数据处理方法，其中，所述第一模 拟信号为模拟电压信号，所述第二模拟信号为模拟电流信号。
  15. 一种电子装置，包括：
    忆阻器阵列，配置为能进行乘和运算；
    信号获取装置，配置为获取多个第一模拟信号；
    控制驱动电路，其中，所述控制驱动电路配置为执行以下步骤：
    设置所述忆阻器阵列，将对应于卷积处理的卷积参数矩阵的数据写入所述忆阻器阵列，其中，所述卷积参数矩阵为第一矩阵且包括阵列排布的多个参数元素，所述多个参数元素对应地按照所述第一矩阵的形式被多次分别映射于所述忆阻器阵列中不同的多个忆阻器子阵列，且所述多个忆阻器子阵列在所述忆阻器阵列的行方向和列方向上均不重叠；
    将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个模拟信号进行所述卷积处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述卷积处理后的多个第二模拟信号。
  16. 根据权利要求15所述的电子装置，其中，所述信号获取装置包括数字信号获取电路和数模转换电路，
    所述数字信号获取电路配置为获取多个初始数字信号；
    所述数模转换电路配置为对所述多个初始数字信号进行数模转换处理，以分别得到所述多个第一模拟信号。
  17. 根据权利要求15或16所述的电子装置，其中，所述控制驱动电路包括：
    源线驱动电路，配置为对所述多个第二模拟信号进行检测和对所述忆阻器阵列执行初始化操作；
    字线驱动电路，配置为对所述忆阻器阵列的多个信号控制端施加开启信号和对所述忆阻器阵列执行初始化操作；以及
    位线驱动电路，配置为对所述多个列信号输入端施加输入信号和对所述忆阻器阵列执行初始化操作，其中，所述输入信号至少包括所述多个第一模拟信号。
  18. 根据权利要求15-17任一项所述的电子装置，还包括数据输出电路，
    其中，所述数据输出电路配置为将所述多个第二模拟信号转换为数字信号，以将所述多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
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