WO2024108349A1 - 存储系统和存储系统的操作方法 - Google Patents

存储系统和存储系统的操作方法 Download PDF

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Publication number
WO2024108349A1
WO2024108349A1 PCT/CN2022/133312 CN2022133312W WO2024108349A1 WO 2024108349 A1 WO2024108349 A1 WO 2024108349A1 CN 2022133312 W CN2022133312 W CN 2022133312W WO 2024108349 A1 WO2024108349 A1 WO 2024108349A1
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Prior art keywords
data
raid
controller
word line
check
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PCT/CN2022/133312
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English (en)
French (fr)
Inventor
罗贤武
石江伟
何有信
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长江存储科技有限责任公司
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Priority to PCT/CN2022/133312 priority Critical patent/WO2024108349A1/zh
Priority to CN202280004988.1A priority patent/CN118382893A/zh
Priority to US18/148,865 priority patent/US12079085B2/en
Publication of WO2024108349A1 publication Critical patent/WO2024108349A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/1096—Parity calculation or recalculation after configuration or reconfiguration of the system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Definitions

  • the present disclosure relates to the field of storage technology, and in particular to a storage system and an operating method of the storage system.
  • Redundant array of independent disk (RAID) technology is widely used in storage systems.
  • RAID technology can be understood as a technology that combines multiple disk drives into a logical unit for data redundancy processing and performance improvement to provide reliability guarantee for stored data.
  • the controller can generate RAID verification data based on valid data and store the RAID verification data in the disk. If a disk is damaged, the controller can restore the data in the damaged disk based on the current valid data and the corresponding RAID verification data.
  • the RAID verification data calculated by the controller in the storage system will first be stored in the cache space of the controller.
  • a swap operation can be used to share the capacity of the limited cache space in a time-sharing manner. In other words, in the process of calculating the RAID verification data and caching the RAID data, it may be necessary to perform multiple swap operations, and it may even be necessary to wait for the swap operation to end before continuing the calculation, thereby affecting the write performance of the controller.
  • Embodiments of the present disclosure provide a storage system and a method for operating the storage system, aiming to solve the problem of poor write performance of a controller.
  • a storage system which includes a controller and a three-dimensional non-volatile memory, the three-dimensional non-volatile memory includes a three-dimensional storage array, the three-dimensional storage array includes a plurality of coupled word lines and a plurality of pages;
  • the controller is coupled to the three-dimensional non-volatile memory, and the controller is configured to: calculate the page data corresponding to the first word line received in units of page data corresponding to a word line to obtain first independent redundant disk array RAID verification data, and store the first RAID verification data in a verification cache space; calculate the page data corresponding to the i+1th word line received and the i-th RAID verification data to obtain i+1th RAID verification data, and store the i+1th RAID verification data in the verification cache space, the i+1th RAID verification data covering the i-th RAID verification data, where i is a positive integer greater than or equal to 1.
  • the controller when the controller is storing RAID verification data, if the RAID verification data is more than the capacity of the verification cache space, a swap operation is required to share the limited verification cache space in a time-sharing manner. Since the RAID verification data in the embodiment of the present application is calculated from the page data corresponding to a word line, the verification cache space can satisfy the RAID verification data calculated from the page data corresponding to a word line. Therefore, in the embodiment of the present application, the storage process of the RAID verification data can reduce the storage pressure and reduce the number of times the controller performs swap operations, thereby improving the write performance of the controller.
  • the controller is further configured to: when the value of i is w-1, write the w-th RAID check data into the three-dimensional non-volatile memory, where w is the number of word lines corresponding to one set.
  • writing the wth RAID obtained after multiple calculations into the three-dimensional non-volatile memory can reduce the number of write times of the controller and the three-dimensional non-volatile memory, and can reduce the storage space required for the three-dimensional non-volatile memory to store RAID verification data.
  • the controller is further configured to: when the check cache space is insufficient, set the first storage space of the write cache space to cache the RAID check data.
  • the first storage space of the write cache space is also used to cache RAID verification data, which can meet the storage space required for the RAID verification data, and further eliminates the need for a swap operation, thereby achieving continuity of the RAID verification data cache and improving the write performance of the controller.
  • the controller is further configured to: store page data corresponding to the first word line to page data corresponding to the (i+1)th word line in a second storage space of the write cache space.
  • the page data corresponding to the first word line and the i+1th word line can be data stored in the three-dimensional non-volatile memory by the host computer.
  • the page data corresponding to each word line is first stored in the second storage space of the write cache space, which can increase the rate at which the host computer reads or writes data to the three-dimensional non-volatile memory.
  • the configuration priority of the second storage space of the write cache space is higher than the configuration priority of the first storage space.
  • the first storage space is allocated to the check cache space to cache RAID check data, thereby ensuring the storage of page data corresponding to multiple word lines.
  • the check cache space includes a check data cache space and a garbage collection cache space.
  • the check data cache space is used to cache RAID check data
  • the garbage collection cache is used to cache garbage collection data.
  • the garbage collection data includes RAID check data corresponding to the data to be recovered in the page data.
  • garbage collection cache space is also allocated in the check cache space to cache RAID check data corresponding to data to be recovered in page data corresponding to multiple word lines, so that the memory occupied by garbage collection data in the three-dimensional non-volatile memory can be released.
  • the controller is further configured to: perform a swap operation after power-on.
  • the cache space is initialized, and the verification cache space can be cleared to start caching RAID verification data.
  • the controller is further configured to: after completing the calculation of the received page data corresponding to the i-th word line, continuously perform the calculation operation of the page data corresponding to the (i+1)-th word line.
  • the controller continuously executes operations such as waiting for calculation and calculation, and stores the RAID verification data after the calculation is completed in the verification cache space without performing a swap operation, thereby achieving the continuity of the RAID verification data cache and improving the write performance of the controller.
  • the RAID check data is obtained by performing an XOR operation on page data corresponding to a word line.
  • the (i+1)th RAID check data is used to check page data corresponding to the first word line to the (i+1)th word line.
  • the damaged page data can be restored through the (i+1)th RAID check data.
  • the storage system includes a controller and a three-dimensional non-volatile memory.
  • the three-dimensional non-volatile memory includes a three-dimensional storage array.
  • the three-dimensional storage array includes a plurality of coupled word lines and a plurality of pages.
  • the controller is coupled to the three-dimensional non-volatile memory.
  • the method includes: taking the page data corresponding to a word line as a unit, calculating the page data corresponding to the first word line received to obtain the first independent redundant disk array RAID verification data, and storing the first RAID verification data in the verification cache space; calculating the page data corresponding to the i+1th word line received and the i-th RAID verification data to obtain the i+1th RAID verification data, and storing the i+1th RAID verification data in the verification cache space, wherein the i+1th RAID verification data covers the i-th RAID verification data, where i is a positive integer greater than or equal to 1.
  • the method further includes: when the value of i is w-1, the controller writes the w-th RAID check data into the three-dimensional non-volatile memory, where w is the number of word lines corresponding to one set.
  • the method before storing the first RAID check data in the check cache space, the method further includes: when the check cache space is insufficient, the controller sets a first storage space of the write cache space for caching the RAID check data.
  • the method further includes: the controller storing page data corresponding to the first word line to page data corresponding to the (i+1)th word line in a second storage space of the write cache space.
  • the configuration priority of the second storage space of the write cache space is higher than the configuration priority of the first storage space.
  • the check cache space includes a check data cache space and a garbage collection cache space.
  • the check data cache space is used to cache RAID check data
  • the garbage collection cache is used to cache garbage collection data.
  • the garbage collection data includes RAID check data corresponding to the data to be recovered in the page data.
  • the method further includes: performing a swap operation after the controller is powered on.
  • the method further includes: after the controller completes the calculation of the received page data corresponding to the i-th word line, continuously performing the calculation operation of the page data corresponding to the (i+1)-th word line.
  • the RAID check data is obtained by performing an XOR operation on page data corresponding to a word line.
  • the (i+1)th RAID check data is used to check page data corresponding to the first word line to the (i+1)th word line.
  • a controller is provided, the controller is used to couple with a three-dimensional non-volatile memory, the three-dimensional non-volatile memory includes a three-dimensional storage array, the three-dimensional storage array includes a plurality of coupled word lines and a plurality of pages; the controller is configured to: calculate the page data corresponding to a first word line received in units of page data corresponding to a word line to obtain first independent redundant disk array RAID verification data, and store the first RAID verification data in a verification cache space; calculate the page data corresponding to the received i+1th word line and the i-th RAID verification data to obtain i+1th RAID verification data, and store the i+1th RAID verification data in the verification cache space, the i+1th RAID verification data covering the i-th RAID verification data, where i is a positive integer greater than or equal to 1.
  • the controller is further configured to: when the value of i is w-1, write the w-th RAID check data into the three-dimensional non-volatile memory, where w is the number of word lines corresponding to one set.
  • the controller is further configured to: when the check cache space is insufficient, set the first storage space of the write cache space to cache the RAID check data.
  • the controller is further configured to: store page data corresponding to the first word line to page data corresponding to the (i+1)th word line in a second storage space of the write cache space.
  • the configuration priority of the second storage space of the write cache space is higher than the configuration priority of the first storage space.
  • the check cache space includes a check data cache space and a garbage collection cache space.
  • the check data cache space is used to cache RAID check data
  • the garbage collection cache is used to cache garbage collection data.
  • the garbage collection data includes RAID check data corresponding to the data to be recovered in the page data.
  • the controller is further configured to: perform a swap operation after power-on.
  • the controller is further configured to: after completing the calculation of the received page data corresponding to the i-th word line, continuously perform the calculation operation of the page data corresponding to the (i+1)-th word line.
  • the RAID check data is obtained by performing an XOR operation on page data corresponding to a word line.
  • the (i+1)th RAID check data is used to check page data corresponding to the first word line to the (i+1)th word line.
  • an electronic system in yet another aspect, includes a host computer and the above storage system.
  • FIG1 is a schematic diagram of a storage system provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of the structure of a NAND flash memory provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a structure of data using two word lines for data protection according to an embodiment of the present application
  • FIG4 is a schematic diagram of a storage space type provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of another round calculation to obtain RAID check data provided by an embodiment of the present application.
  • FIG6 is a schematic diagram of a process flow of a swap operation provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a controller provided in an embodiment of the present application.
  • FIG8 is a flow chart of a storage system operation method provided by an embodiment of the present application.
  • FIG9 is a schematic diagram of a structure of data using one word line for data protection according to an embodiment of the present application.
  • FIG10 is a flow chart of an operating method of a storage system provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of a storage space provided in an embodiment of the present application.
  • FIG12 is a flow chart of a controller caching data provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact.
  • the term “coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
  • the term "substrate” refers to a material on which subsequent material layers may be added.
  • the substrate itself may be patterned.
  • the material added to the substrate may be patterned or may remain unpatterned.
  • the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.
  • the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.
  • three-dimensional non-volatile memory refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string”, such as a NAND memory cell string) arranged in an array on a main surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or the source layer.
  • memory cell string such as a NAND memory cell string
  • vertical/vertically means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.
  • RAID refers to "Redundant Array of Independent Disks” technology. It should be understood that although “RAID” refers to an array of any independent disks, embodiments of the present application can be implemented at the hardware level using any type of non-volatile storage device, such as a NAND flash memory storage device.
  • FIG1 is a schematic diagram of a storage system provided in an embodiment of the present application.
  • the storage system 10 includes a controller 101 and a three-dimensional non-volatile memory 102.
  • the controller 101 can communicate with a host computer 11 outside the storage system 10.
  • the controller 101 can also be connected to the three-dimensional non-volatile memory 102 via a storage channel.
  • the storage system 10 can include at least one three-dimensional non-volatile memory 102, and each three-dimensional non-volatile memory 102 can be managed by the controller 101.
  • the host computer 11 may send data to be stored in the three-dimensional non-volatile memory 102 to the controller 101, and the host computer 11 may also read data from the three-dimensional non-volatile memory 102 through the controller 101.
  • the controller 101 may process input/output (I/O) requests received from the host computer 11, and ensure the integrity and effective storage of the data to be stored according to the I/O requests. For example, the controller 101 may cache the data received from the host computer 11, and perform RAID calculations based on the received data to obtain RAID verification data and cache the RAID verification data. The RAID verification data is used to recover data damaged during encoding or storage.
  • the controller 101 may also send the data received from the host computer 11 and the calculated RAID verification data to the three-dimensional non-volatile memory 102 for storage.
  • the host computer 11 is a dedicated processor for performing data processing of the three-dimensional non-volatile memory 102.
  • the host computer 11 may include a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor.
  • Data is transmitted between the host computer 11 and the controller 101 through at least one of a plurality of interface protocols.
  • the interface protocol includes at least one of the universal serial bus (USB) protocol, the Microsoft management console (MMC) protocol, the peripheral component interconnect (PCI) protocol, the PCI high-speed (PCI-E) protocol, the advanced technology attachment (ATA) protocol, the serial ATA protocol, the parallel ATA protocol, the small computer system interface (SCSI) protocol, the integrated drive electronic (IDE) protocol or the firewire protocol.
  • USB universal serial bus
  • MMC Microsoft management console
  • PCI peripheral component interconnect
  • PCI-E PCI high-speed
  • ATA advanced technology attachment
  • serial ATA protocol serial ATA protocol
  • parallel ATA protocol serial ATA protocol
  • SCSI small computer system interface
  • IDE integrated drive electronic
  • the controller 101 may be configured to control operations in the three-dimensional non-volatile memory 102, such as read, write, erase, or encode operations.
  • the controller 101 may also be configured to manage various functions of data stored or to be stored in the three-dimensional non-volatile memory 102, including but not limited to bad block management, garbage collection, logical to physical address conversion, or wear leveling.
  • the controller 101 is also configured to process error correction code (ECC) for data read from or written to the three-dimensional non-volatile memory 102.
  • ECC error correction code
  • the controller 101 may also perform any other suitable functions on the three-dimensional non-volatile memory 102, such as formatting the three-dimensional non-volatile memory 102, which is not specifically limited in the embodiments of the present application.
  • the controller 101 may control the operation of the three-dimensional non-volatile memory 102 by generating control signals to control striping, calculation, or storage of data in the three-dimensional non-volatile memory 102.
  • the controller 101 may receive signals for the operation of the three-dimensional non-volatile memory 102 from the host computer 11 to control striping, calculation, or storage of data in the three-dimensional non-volatile memory 102.
  • the controller 101 may have different modules in a single device, such as an integrated circuit chip, for example, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), or a separate device with dedicated functions.
  • the components of the controller 101 may be in an integrated device, or distributed in different locations but communicate with each other through a network.
  • the three-dimensional non-volatile memory 102 in the present disclosure may be a flash memory, for example, a NAND flash memory.
  • NAND flash memory may also be referred to as flash memory or NAND.
  • the three-dimensional non-volatile memory 102 in the present disclosure may also be other memories, which is not limited in the present application, and is only described by taking the three-dimensional non-volatile memory 102 as a NAND flash memory as an example.
  • FIG. 2 is a schematic diagram of the structure of a NAND flash memory provided in an embodiment of the present application.
  • the NAND flash memory 20 generally includes a plurality of die (DIE) 201, such as D0 and D1.
  • DIE 201 has a plurality of planes (PL), such as PL0, PL1, PL2 and PL3.
  • PL planes
  • Each PL may include one or more memory blocks, and each memory block may be further divided into multiple strings (STRs).
  • Each STR includes memory cells for storing an upper page (UP) data portion, a middle page (MP) data portion, and a lower page (LP) data portion.
  • the memory cells are coupled to a plurality of word lines (WL) arranged vertically, and to a plurality of bit lines (BL) arranged horizontally.
  • each STR may include a plurality of gate conductive layers extending laterally.
  • a memory block includes a plurality of gate conductive layers stacked vertically at a plurality of levels, and each gate conductive layer is coupled to memory cells in a plurality of pages in the STRs distributed laterally in the memory block.
  • the storage capacity of the NAND flash memory also increases, and the space between adjacent gate conductive layers becomes smaller, causing the interference between adjacent gate conductive layers to become significant.
  • RAID5 In order to improve the integrity and readability of memory cells, RAID5 has been widely used in NAND flash memory. Generally, RAID5 uses striping in memory blocks to divide the memory data in the memory blocks into multiple data parts, performs an exclusive OR (XOR) operation between the data parts in the stripes to generate corresponding parity data, and stores the parity data in the memory cells.
  • XOR exclusive OR
  • a stripe can be understood as including data parts located in two dimensions, for example, a stripe includes different memory blocks located horizontally across different DIEs and different PLs, and data located vertically at different levels in the same memory block. In other words, in the lateral direction, a stripe can include data parts at the same position in different PLs.
  • a stripe can include data parts at the same position in different levels.
  • the data part includes parity data of the stripe.
  • the damaged data can be recovered by performing an XOR operation using the parity data of the stripe and the remaining data parts in the stripe.
  • 127 data portions are used to store memory data and 1 data portion is used to store parity data for the stripe, so the error correction capability of RAID 5 using this striping configuration can be described as (127+1). That is, one parity data portion protects 127 memory data portions.
  • Table 1 shows part or all of the memory data to be stored in the three-dimensional non-volatile memory 102.
  • the memory data needs to be stored in the three-dimensional non-volatile memory 102 before being stored in the three-dimensional non-volatile memory 102.
  • DIE0 and DIE1 DIEs
  • Each DIE includes 4 PLs: PL0, PL1, PL2, and PL3.
  • Each PL includes 6 STRs: STR0, STR1, STR2, STR3, STR4, and STR5, and each STR includes a memory cell for storing a UP data portion, an MP data portion, and a LP data portion.
  • the memory cell is coupled to a plurality of word lines arranged vertically.
  • word lines are labeled with word line numbers, such as WL0 and WL1, etc.
  • data parts (such as UP data part, MP data part and LP data part) are also numbered.
  • the LP data part stored in the memory cell in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "0"
  • the MP data part stored in the memory cell in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "1”
  • the UP data part stored in the memory cell in the 0th string (STR0) and coupled to the 0th word line (WL0) has a data number "2".
  • the data parts stored in the memory cells of the same word line coupled to the same page in different planes have the same data number.
  • the data parts stored in the memory cells coupled to WL0 in PL0 and PL1 have the same data number "0".
  • the number of word lines may vary from 32, 64, 96, 128 to 256. It should be noted that the RAID operation may be applied to any suitable three-dimensional nonvolatile memory 102, and is not limited to the exact number of dies, planes, strings, and word lines of the three-dimensional nonvolatile memory 102.
  • the word lines of each level may be coupled to 18 data portions (e.g., 0-17 data portions) (e.g., WL0).
  • the controller 101 may adopt RAID5 when receiving data from the host computer 11, and calculate the RAID check data based on the page data of the data pages (data page) corresponding to the two word lines, that is, use the page data corresponding to the two word lines to perform data protection.
  • one word line is coupled to 18 pages, and each page includes one parity page and 127 data pages.
  • the RAID parity data in the parity page is calculated by the 127 data pages in the page. That is, one parity page can be used to protect 127 data pages. Therefore, two word lines correspond to 36 parity pages.
  • 36 parity pages are a round.
  • FIG. 3 shows 576 page lines in DIE0 and DIE1, which are denoted as P0 to P575.
  • Each page line includes multiple PL pages.
  • round 0 (301) includes P0-P35
  • round 2 (302) includes P36-P71
  • ... and round 16 includes P540-P575 (303). That is, 16 rounds are required to store 576 pages, and 16 rounds are a fund.
  • the controller 101 When the controller 101 receives data and calculates RAID verification data, it needs to cache the received data and RAID verification data first and then send them to the NAND flash memory for storage. Therefore, the storage space in the controller 101 is first introduced here.
  • FIG4 is a schematic diagram of storage space types in the controller 101.
  • the storage space may include a read buffer space, a copy buffer space, or a parity buffer (PB) space, etc.
  • PB parity buffer
  • FIG4 is only an exemplary diagram and does not limit the controller 101 to include other buffer spaces.
  • the parity buffer space can be used to store RAID check data and garbage collection (GC) data.
  • the RAID check data and garbage collection data corresponding to the two word lines usually require 1152KB of storage space for cache. Since the storage space of the check cache space is limited, usually only 320KB of storage space is provided for RAID check data and garbage collection data, so the controller 101 needs to share the limited check cache space through swap operations.
  • FIG. 5 is a schematic diagram of a round of RAID verification data calculated in an embodiment of the present application.
  • P0-P35 on the vertical axis represents the index of 36 page lines in a round (page line index).
  • the controller 101 is allocated 12 PBs when caching RAID verification data, and the capacity of each PB is 16KB, which is used to store the RAID verification data of 1 verification page.
  • the horizontal axis represents the usage status of each 12 PB (0-11PB) at different stages, such as from time t1 to time t17.
  • the controller 101 can calculate 3 PBs of RAID verification data at time t1, such as P0-P2.
  • 3 PBs of RAID verification data can also be calculated, such as P3-P5, at which time 6 PBs of RAID verification data have been stored, such as P0-P5.
  • P3-P5 time 6 PBs of RAID verification data have been stored
  • 8 PBs of RAID verification data have been stored at this time, such as P0-P7
  • a swap operation is performed at time t4. That is, when every 8 PBs are full of RAID check data, the controller 101 needs to perform a swap operation, that is, back up the RAID check data of the 8 check pages that have been calculated to the three-dimensional non-volatile memory 102. Then, the three-dimensional non-volatile memory 102 can restore the RAID check data of the 8 check pages that are about to be used.
  • FIG6 shows a schematic diagram of the process of the swap operation.
  • the controller 101 needs to perform 5 swap operations in total, namely, at time t4, time t7, time t10, time t13 and time t16.
  • Each swap operation includes calculation operations on 8 check pages and reading operations on 8 check pages. Even in a swap operation, it is necessary to wait for the previous swap operation to be completed before continuing to send program commands for executing the next swap operation, and the write performance of the controller 101 is low.
  • the embodiment of the present application provides a storage system operation method.
  • the method uses the page data corresponding to a word line as a unit, calculates RAID verification data and caches the RAID verification data to the verification cache space of the cache module.
  • the verification cache space continues to cache the second RAID verification data after caching the first RAID verification data, and the second RAID verification data overwrites the first RAID verification data. Since in the storage system operation method provided by the present disclosure, the RAID verification data is calculated from the page data corresponding to a word line, and the verification cache space can satisfy the cached RAID verification data, the RAID verification storage process of the present application can reduce the storage pressure, reduce the number of times the controller 101 performs swap operations, and thus improve the write performance of the controller.
  • FIG. 7 is a schematic diagram of the structure of a controller provided in an embodiment of the present application.
  • the controller 101 may perform a calculation operation, for example, the controller 101 calculates the received page data corresponding to the first word line in units of page data corresponding to a word line, obtains the first RAID check data, and stores the first RAID check data in the check cache space.
  • the first RAID check data may be calculated from 18 page data corresponding to the first word line, so the first RAID check data may correspond to 18 check page data.
  • the controller 101 is coupled to the three-dimensional non-volatile memory 102 and can perform a data write operation or a data read operation in response to a control signal.
  • the controller 101 can be configured to temporarily store data transmitted between the host computer 11 and the three-dimensional non-volatile memory 102. For example, during the period when the host computer 11 writes data to the three-dimensional non-volatile memory 102 or the host computer 11 reads data from the three-dimensional non-volatile memory 102, the controller 101 can be configured to temporarily store page data corresponding to a word line or RAID check data calculated in units of page data corresponding to a word line.
  • the controller 101 may include a static random access memory (SRAM) or a dynamic random access memory (DRAM), which is not specifically limited in the embodiments of the present application.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • controller 101 may provide data and control communications with the three-dimensional non-volatile memory 102 via a data bus.
  • Controller 101 may include a general or special microprocessor, digital signal processor or microcontroller of any appropriate type. Controller 101 may be configured as an independent processor module dedicated to analyzing signals or controlling scanning schemes. Optionally, controller 101 may also be configured as a shared processor module for performing other functions unrelated to signal analysis/scanning schemes. Controller 101 may include multiple functional units or modules that can be implemented using software, hardware, middleware, firmware or any combination thereof. Multiple functional units can perform operations such as reading, writing, erasing, striping, calculating, decision making or controlling the storage of RAID verification data based on signals from host computer 11 or pre-stored control data.
  • the controller 101 may perform configuration work, such as setting the first storage space of the write cache space to cache RAID check data. In some implementations, the controller 101 may also perform a swap operation.
  • FIG8 is a flow chart of a storage system operation method provided by an embodiment of the present application. The method includes:
  • Step 801 The controller 101 calculates the received page data corresponding to the first word line in units of page data corresponding to a word line to obtain first RAID check data, and stores the first RAID check data into the check cache space.
  • FIG. 9 is a schematic diagram of the structure of data using one word line for data protection provided by an embodiment of the present application.
  • the page data corresponding to one word line can be 18 pages of data.
  • FIG. 9 shows 288 pages of data in DIE0 and DIE1, wherein round 0 (901) includes P0-P17, round 1 (902) includes P18-P31, ..., and round 16 (903) includes P270-P287. That is, 16 rounds are required to store 288 pages, wherein 16 rounds are a set.
  • the RAID check data is obtained by performing an exclusive OR operation on page data corresponding to a word line.
  • the controller 101 may perform an XOR operation on the page data corresponding to a word line to obtain the first RAID check data. In one example, if one page of 18 pages of data corresponding to a word line is d1, d2, d3, d4, and d5, the RAID check data corresponding to this page is d1, d2, d3, d4, and d5, the RAID check data corresponding to this page is d1, d2, d3, d4, and d5, the RAID check data corresponding to this page is
  • the controller 101 may use a parity check algorithm to add a parity check bit to the calculated first RAID check data.
  • Parity check can be understood as checking whether the number of "1"s in a set of binary codes transmitted is an odd number or an even number, wherein the odd number is called odd check, and vice versa, it is called even check.
  • the first RAID parity data is subjected to an XOR operation, and then the result is XORed with "1" to obtain the value of the odd parity bit in the first RAID parity data.
  • odd parity the first RAID parity data is subjected to an XOR operation, and then the result is XORed with "0" to obtain the value of the even parity bit in the first RAID parity data. This ensures the accuracy of the first RAID parity data.
  • the RAID check data may also be other operations except XOR operation performed on the page data corresponding to a word line, which is not limited in the present application.
  • the page data corresponding to a word line may be data pre-written by the host computer 11 to the three-dimensional non-volatile memory 102 .
  • the page data may be binary digital data of symbols, text, numbers, voice, images, videos or a combination thereof.
  • Step 802 the controller 101 calculates the page data corresponding to the received i+1th word line and the i-th RAID verification data to obtain the i+1th RAID verification data, and stores the i+1th RAID verification data in the verification cache space.
  • the i+1th RAID verification data overwrites the i-th RAID verification data, where i is a positive integer greater than or equal to 1.
  • the controller 101 may perform a calculation operation on the received page data corresponding to the second word line and the first RAID check data to obtain the second RAID check data.
  • the first word line corresponds to 18 pages of page data, namely D1, D2, ..., D18
  • an XOR operation is performed on the page data of D1-D18 respectively
  • each page of the page data corresponds to a group of RAID check data
  • the first RAID check data may include 18 groups of RAID check data, namely P1, P2, ..., P18.
  • the second word line also corresponds to 18 pages of page data, namely D19, D20, ..., D36.
  • an XOR operation is performed on the first page data D19 in the page data corresponding to the second word line and the first group of RAID check data P1 in the 18 groups of RAID check data to obtain the first group of RAID check data P19 in the second RAID check data, that is,
  • the remaining groups of RAID verification data in the second RAID verification data can also be obtained by a method similar to the first group of RAID verification data in the second RAID verification data.
  • the controller 101 stores the calculated second RAID verification data over the first RAID verification data in the verification cache space.
  • FIG. 10 is another method for operating a storage system provided in an embodiment of the present application.
  • the method may also include step 803, when the value of i is w-1, the controller 101 writes the w-th RAID check data into the three-dimensional non-volatile memory 102, where w is the number of word lines corresponding to a set.
  • the page data corresponding to the received 16th word line and the 15th RAID check data are performed with an exclusive OR operation, and the 16th RAID check data can be obtained, and the 15th RAID check data is stored in the check cache space with the 16th RAID check data overwritten.
  • the controller 101 has completed the calculation of the RAID check data for the page data corresponding to the word lines of a set, so that the 16th RAID check data can be sent to the three-dimensional non-volatile memory 102. If any page data corresponding to a word line of a set is damaged, it can be restored according to the 16th RAID check data and other page data corresponding to the word line of a set.
  • the valid data in the three-dimensional non-volatile memory 102 may be bit-flipped and converted into erroneous data due to the physical state of the memory unit or programming interference during the storage process. Therefore, it is necessary to restore the erroneous data to valid data. Therefore, the RAID check data is also stored in the three-dimensional non-volatile memory 102, and the valid data can be restored according to the RAID check data corresponding to the valid data, thereby improving the correctness of the valid data stored in the three-dimensional non-volatile memory 102.
  • the method may further include:
  • Step 804 When the verification cache space is insufficient, the controller 101 sets the first storage space of the write cache space to cache the RAID verification data.
  • Figure 11 is a schematic diagram of a storage space provided by an embodiment of the present application.
  • a word line protection method is adopted, a total of 448KB of storage space is required for RAID verification data and garbage collection data.
  • the controller 101 can allocate a first storage space with a capacity of 128KB in the write cache space for caching RAID verification data.
  • the total storage space in the verification cache space for storing RAID verification data and garbage collection data is 512KB, and the controller 101 can allocate 448KB of storage space from the verification cache space for caching RAID verification data and garbage collection data, and the remaining storage space can be used to store other system data.
  • the controller 101 can allocate part of the storage space from the verification cache space for caching RAID verification data and garbage collection data, and the remaining storage space can be used to store other system data.
  • the RAID verification data and garbage collection data require a total of 576KB of storage space, and the controller 101 can allocate 448KB of storage space from the verification cache space for caching RAID verification data and garbage collection data.
  • the partial storage space allocated from the verification cache space for caching RAID verification data and garbage collection data gives priority to the storage of RAID verification data, and the remaining storage space is used to store garbage collection data.
  • the controller 101 allocates 18PB storage space for storing RAID check data, and each PB occupies 16KB.
  • the first RAID check data includes 18 groups of RAID check data
  • the method may further include:
  • Step 805 The controller 101 stores the page data corresponding to the first word line to the page data corresponding to the (i+1)th word line in the second storage space of the write cache space.
  • the second storage space of the write cache space can cache data transferred between the host computer 11 and the three-dimensional non-volatile memory 102, that is, page data corresponding to multiple word lines.
  • the second storage space of the write cache space stores data in units of page data corresponding to one word line. Therefore, when performing a read or write operation between the host computer 11 and the three-dimensional non-volatile memory 102, the page data corresponding to multiple word lines are stored in the second storage space of the write cache space, which can increase the rate at which the host computer 11 reads or writes data to the three-dimensional non-volatile memory 102.
  • the configuration priority of the second storage space of the write cache space is higher than the configuration priority of the first storage space.
  • the controller 101 should reallocate the first storage space to the check cache space for caching RAID check data when the capacity of the second storage space is sufficient to cache data of pages corresponding to multiple word lines.
  • the controller 101 can cache all RAID check data without performing a swap operation, thereby improving the write performance of the controller.
  • the first storage space and the check cache space can be shared in a time-sharing manner by performing a swap operation.
  • the write performance of the controller can still be improved because the number of swap operations is reduced.
  • the check cache space includes a check data cache space and a garbage collection cache space.
  • the check data cache space is used to cache RAID check data
  • the garbage collection cache is used to cache garbage collection data.
  • the garbage collection data includes RAID check data corresponding to the data to be recovered in the page data.
  • 10 PBs may be allocated for storing garbage collection data.
  • a GC operation may be performed in order to reuse the data blocks storing such invalid data.
  • the controller 101 may perform a GC operation to change the data blocks storing valid data into free blocks.
  • a GC mechanism may be set in the controller 101 to be triggered when the number of remaining free blocks is equal to or less than a threshold. When the GC mechanism is triggered, the controller 101 may identify a closed block among the multiple data blocks in the three-dimensional non-volatile memory 102, and use the closed block whose number of valid pages is less than the threshold as a sacrifice block.
  • the controller 101 may copy the valid data in the sacrifice block and store the valid data in a target block as a free block that has not yet been subjected to an encoding operation. After the valid data is copied and stored in the target block, the controller 101 may erase the sacrifice block.
  • the controller 101 may read the data from the closed block of the three-dimensional nonvolatile memory 102, load the read data into the cache space, and then write the data stored in the cache space into the free block. Since the controller 101 performs the read/write operation on the three-dimensional nonvolatile memory 102, when a read command or a write command is transmitted from the host computer 11 while performing the GC operation, the controller 101 may stop the GC operation to perform the operation of the command.
  • the controller 101 will mark valid data and invalid data.
  • the method of marking invalid data is called a garbage marking algorithm, which can be divided into a reference counting algorithm and a root search algorithm.
  • the reference counting algorithm maintains a memory field for each data to count the number of times the data is referenced.
  • the counter is incremented by 1, and decremented by 1 when the reference becomes invalid.
  • the data is marked as invalid data and waits for the next recycling.
  • the root search algorithm starts from a data called "GC Roots" as the root starting point, traverses the object graph through the reference relationship, and the searched path is called a reference chain.
  • GC Roots a data called "GC Roots" as the root starting point
  • the method further includes:
  • Step 806 The controller 101 performs a swap operation after being powered on.
  • the controller 101 may execute a program of a load swap operation to initialize the check cache space and the write cache space.
  • the RAID check data cache process can satisfy the RAID check data calculated based on the page data corresponding to a word line. Therefore, the RAID check data cache process of the present application does not need to perform a swap operation, realizes the continuity of the RAID check data cache, and improves the write performance of the controller.
  • the host computer 11 may also send a reset signal to the controller 101 , and the reset signal is used to clear the data cached in the cache space.
  • the method further includes: after completing the calculation of the received page data corresponding to the i-th word line, continuously performing the calculation operation of the page data corresponding to the (i+1)-th word line.
  • Figure 12 is a flow chart of a controller cache data provided by an embodiment of the present application.
  • the controller 101 executes a program for loading and swapping operations. After the swapping operation is performed, steps such as waiting for calculation, calculation, and calculation completion are performed, and then the above steps are repeated.
  • the controller 101 will continuously perform the following steps: a. Wait for the calculation of the page data corresponding to the i-th word line; b. Calculate the page data corresponding to the i-th word line; c. The calculation of the page data corresponding to the i-th word line is completed; d. Wait for the calculation of the page data corresponding to the i+1-th word line; e. Calculate the page data corresponding to the i+1-th word line; f. The calculation of the page data corresponding to the i+1-th word line is completed.
  • the (i+1)th RAID check data is used to check the page data corresponding to the first word line to the (i+1)th word line.
  • the controller 101 may store the i+1th RAID check data in the three-dimensional non-volatile memory 102.
  • the i+1th RAID check data may be used to check the page data corresponding to the first word line to the i+1th word line, that is, if any data in the page data corresponding to the first word line to the i+1th word line is damaged, it may be restored according to the i+1th RAID check data and other data corresponding to the first word line to the i+1th word line.
  • Fig. 13 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • the electronic device 100 includes a host computer 11 and a storage system 10 in some embodiments of the present disclosure.
  • the storage system 10 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multi-media card (eMMC) package). That is, the storage system 10 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.
  • UFS universal flash storage
  • eMMC embedded multi-media card
  • the storage system 10 may include a controller 101 and a three-dimensional non-volatile memory 102 , and the storage system 10 may be integrated into a memory card.
  • the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital (SD) card or UFS.
  • PCMCIA Personal Computer Memory Card International Association
  • CF compact flash
  • SM smart media
  • MMC multimedia card
  • SD secure digital
  • a storage system 10 includes a storage controller 101 and a plurality of three-dimensional non-volatile memories 102, and the storage system 10 is integrated into solid state drives (SSD).
  • SSD solid state drives
  • the storage controller 101 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.
  • a low duty cycle environment such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.
  • the controller 101 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, or laptops, as well as enterprise storage arrays.
  • the electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.
  • the electronic device may include the storage system 10 described above, and may also include at least one of a central processing unit and a cache.

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Abstract

本公开提供了一种存储系统和存储系统的操作方法，涉及存储技术领域，旨在解决校验数据的缓存效率问题。存储系统包括耦合的控制器和三维非易失性存储器，三维非易失性存储器包括三维存储阵列，三维存储阵列包括耦合的多个字线和多个页面；控制器被配置为：以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间；对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将第i+1个RAID校验数据存储至校验缓存空间，第i+1个RAID校验数据覆盖第i个RAID校验数据，i为大于等于1的正整数。

Description

存储系统和存储系统的操作方法 技术领域
本公开涉及存储技术领域，尤其涉及一种存储系统和存储系统的操作方法。
背景技术
独立冗余磁盘阵列(redundant array of independent disk，RAID)技术广泛应用于存储系统中。RAID技术可理解为一种将多个磁盘驱动器组合成为一个逻辑单元，用于数据冗余处理和性能改进的技术，以对存储的数据提供可靠性保证。
RAID技术根据不同的性能被划分为不同的等级。其中，对于RAID5方案而言，控制器可以基于有效数据生成RAID校验数据，并将RAID校验数据存储于磁盘中。若某一块磁盘损坏，控制器可以基于当前的有效数据和对应的RAID校验数据恢复损坏的磁盘中的数据。目前，存储系统中的控制器计算得到的RAID校验数据会先存储于控制器的缓存空间中。在存储的过程中，在RAID校验数据多于缓存空间的容量的情况下，可采用交换(swap)操作来分时共享有限的缓存空间的容量。也就是说，在计算得到RAID校验数据并对RAID数据进行缓存的过程中，可能需要执行多次swap操作，甚至会出现需要等待swap操作结束后才继续计算的情况，从而影响控制器的写入性能。
发明内容
本公开的实施例提供一种存储系统和存储系统的操作方法，旨在解决控制器的写入性能差的问题。
为达到上述目的，本公开的实施例采用如下技术方案：
一方面，提供一种存储系统，该存储系统包括控制器和三维非易失性存储器，三维非易失性存储器包括三维存储阵列，三维存储阵列包括耦合的多个字线和多个页面；控制器耦合至三维非易失性存储器，控制器被配置为：以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个独立冗余磁盘阵列RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间；对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将第i+1个RAID校验数据存储至校验缓存空间，第i+1个RAID校验数据覆盖第i个RAID校验数据，i为大于等于1的正整数。
通常，控制器在存储RAID校验数据的过程中，若RAID校验数据多于校验缓存空间的容量，需采用交换(swap)操作来分时共享有限的校验缓存空间。由于本申请实施例中的RAID校验数据由一个字线对应的页面数据计算得到，校验缓存空间可满足一个字线对应的页面数据计算得到的RAID校验数据。因此本申请实施例中，RAID校验数据的存储过程可以降低存储压力，并减少控制器执行swap操作的次数，从而提高控制器的写入性能。
在一些实施例中，控制器还被配置为：当i的取值为w-1时，将第w个RAID校验数据写入三维非易失性存储器，w为一个集对应的字线的数量。
其中，将多次计算后得到的第w个RAID写入三维非易失性存储器，可以减少控制器和三维非易失性存储器的写入次数，以及可以减少三维非易失性存储器存储RAID校验数据所需的存储空间。
在一些实施例中，控制器还被配置为：在校验缓存空间不足的情况下，设置写缓存空间的第一存储空间用于缓存RAID校验数据。
其中，将写缓存空间的第一存储空间也用于缓存RAID校验数据，可以满足RAID校验数据所需的存储空间，进而无需进行swap操作，实现了RAID校验数据缓存的连续性，可以提高控制器的写入性能。
在一些实施例中，控制器还被配置为：将第一字线对应的页面数据至第i+1字线对应的页面数据存储在写缓存空间的第二存储空间中。
其中，第一字线和第i+1字线对应的页面数据可以为主机计算机存储于三维非易失性存储器的数据，将每个字线对应的页面数据先存储在写缓存空间的第二存储空间，可以提高主机计算机向三维非易失性存储器读取或写入数据的速率。
在一些实施例中，写缓存空间的第二存储空间的配置优先级高于第一存储空间的配置优先级。
其中，在满足多个字线对应的页面数据需存储的第二存储空间的容量下，再分配第一存储空间至校验缓存空间用以缓存RAID校验数据，可以保证多个字线对应的页面数据的存储。
在一些实施例中，校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，校验数据缓存空间用于缓存RAID校验数据，垃圾回收缓存用于缓存垃圾回收数据，垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
其中，校验缓存空间中还分配垃圾回收缓存空间，用于缓存多个字线对 应的页面数据中需回收的数据对应的RAID校验数据，这样可以释放三维非易失性存储器中垃圾回收数据所占的内存。
在一些实施例中，控制器还被配置为：在上电后执行交换操作。
其中，在控制器上电后进行缓存空间的初始化，可以清空校验缓存空间以开始缓存RAID校验数据。
在一些实施例中，控制器还被配置为：在对接收到的第i字线对应的页面数据计算完成之后，连续执行第i+1字线对应的页面数据的计算操作。
其中，控制器连续执行等待计算、计算等操作，将计算完成后的RAID校验数据存储至校验缓存空间，无需执行swap操作，实现了RAID校验数据缓存的连续性，提高了控制器的写入性能。
在一些实施例中，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
在一些实施例中，第i+1个RAID校验数据用于校验第一字线至第i+1字线对应的页面数据。
其中，当第一字线至第i+1字线对应的页面数据存在损坏的页面数据时，可以通过第i+1个RAID校验数据恢复该损坏的页面数据。
另一方面，提供一种存储系统的操作方法，存储系统包括控制器和三维非易失性存储器，三维非易失性存储器包括三维存储阵列，三维存储阵列包括耦合的多个字线和多个页面；控制器耦合至三维非易失性存储器，方法包括：以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个独立冗余磁盘阵列RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间；对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将第i+1个RAID校验数据存储至校验缓存空间，第i+1个RAID校验数据覆盖第i个RAID校验数据，i为大于等于1的正整数。
在一些实施例中，该方法还包括：当i的取值为w-1时，控制器将第w个RAID校验数据写入三维非易失性存储器，w为一个集对应的字线的数量。
在一些实施例中，在将第一个RAID校验数据存储至校验缓存空间之前，方法还包括：在校验缓存空间不足的情况下，控制器设置写缓存空间的第一存储空间用于缓存RAID校验数据。
在一些实施例中，该方法还包括：控制器将第一字线对应的页面数据至第i+1字线对应的页面数据存储在写缓存空间的第二存储空间中。
在一些实施例中，写缓存空间的第二存储空间的配置优先级高于第一存 储空间的配置优先级。
在一些实施例中，校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，校验数据缓存空间用于缓存RAID校验数据，垃圾回收缓存用于缓存垃圾回收数据，垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
在一些实施例中，该方法还包括：在控制器上电后执行交换操作。
在一些实施例中，该方法还包括：控制器在对接收到的第i字线对应的页面数据计算完成之后，连续执行第i+1字线对应的页面数据的计算操作。
在一些实施例中，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
在一些实施例中，第i+1个RAID校验数据用于校验第一字线至第i+1字线对应的页面数据。
又一方面，提供一种控制器，控制器用于和三维非易失性存储器耦合，三维非易失性存储器包括三维存储阵列，三维存储阵列包括耦合的多个字线和多个页面；控制器被配置为：以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个独立冗余磁盘阵列RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间；对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将第i+1个RAID校验数据存储至校验缓存空间，第i+1个RAID校验数据覆盖第i个RAID校验数据，i为大于等于1的正整数。
在一些实施例中，控制器还被配置为：当i的取值为w-1时，将第w个RAID校验数据写入所述三维非易失性存储器，w为一个集对应的字线的数量。
在一些实施例中，控制器还被配置为：在校验缓存空间不足的情况下，设置写缓存空间的第一存储空间用于缓存RAID校验数据。
在一些实施例中，控制器还被配置为：将第一字线对应的页面数据至第i+1字线对应的页面数据存储在写缓存空间的第二存储空间中。
在一些实施例中，写缓存空间的第二存储空间的配置优先级高于第一存储空间的配置优先级。
在一些实施例中，校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，校验数据缓存空间用于缓存RAID校验数据，垃圾回收缓存用于缓存垃圾回收数据，垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
在一些实施例中，控制器还被配置为：在上电后执行交换操作。
在一些实施例中，控制器还被配置为：在对接收到的第i字线对应的页面数据计算完成之后，连续执行第i+1字线对应的页面数据的计算操作。
在一些实施例中，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
在一些实施例中，第i+1个RAID校验数据用于校验第一字线至第i+1字线对应的页面数据。
又一方面，提供一种电子系统，该电子系统包括主机计算机和如上的存储系统。
可以理解地，本公开的上述实施例提供的存储系统和存储系统的操作方法，其所能达到的有益效果可参考上文中存储控制器的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本申请实施例提供的一种存储系统的示意图；
图2为本申请实施例提供的一种NAND闪存的结构示意图；
图3为本申请实施例提供的采用两个字线进行数据保护的数据的结构示意图；
图4为本申请实施例提供的一种存储空间类型示意图；
图5为本申请实施例提供的另一个round计算得到RAID校验数据的示意图；
图6为本申请实施例提供的一种swap操作的流程示意图；
图7为本申请实施例提供的一种控制器的结构示意图；
图8为本申请实施例提供的一种存储系统操作方法的流程图；
图9为本申请实施例提供的采用一个字线进行数据保护的数据的结构示意图；
图10为本申请实施例提供的一种存储系统的操作方法的流程图；
图11为本申请实施例提供的一种存储空间示意图；
图12为本申请实施例提供的一种控制器缓存数据的流程图；
图13为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差 范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文所使用的，术语“衬底”是指可以在其上添加后续的材料层的材料。衬底本身可以被图案化。被添加在衬底上的材料可以被图案化或者可以保持不被图案化。此外，衬底可以包括诸如硅、锗、砷化镓、磷化铟等的多种半导体材料。替代地，衬底可以由诸如玻璃、塑料或蓝宝石晶圆之类的非导电材料制成。
术语“三维非易失性存储器”是指，在衬底或源极层的主表面上阵列布置，且沿垂直于衬底或源极层的方向延伸的存储单元晶体管串(在本文中被称为“存储单元串”，例如NAND存储单元串)所形成的半导体器件。如本文所使用的，术语“垂直/垂直地”意味着标称上垂直于衬底或源极层的主表面(即横向表面)。
如在本公开中所使用的，术语“RAID”是指“独立磁盘冗余阵列”技术。应当理解的是，尽管“RAID”是指任何独立磁盘的阵列，但本申请的实施方式可使用任何类型的非易失性存储装置在硬件层面上来实现，例如NAND闪存存储装置。
图1为本申请实施例提供的一种存储系统的示意图。存储系统10包括控制器101和三维非易失性存储器102。控制器101可与存储系统10外的主机计算机11进行通信。控制器101还可经由存储通道连接到三维非易失性存储器102。在一些实施例中，如图1所示，存储系统10可以包括至少一个三维非易失性存储器102，每个三维非易失性存储器102可以由控制器101管理。
其中，主机计算机11可向控制器101发送要存储在三维非易失性存储器102中的数据，主机计算机11还可以通过控制器101从三维非易失性存储器102读取数据。控制器101可以处理从主机计算机11接收到的输入/输出(input/output，I/O)请求，并根据I/O请求确保待存储的数据 的完整性和有效存储。例如，控制器101可对从主机计算机11接收到的数据进行缓存，并根据接收到的数据进行RAID计算，得到RAID校验数据并对RAID校验数据进行缓存。其中，RAID校验数据用于恢复编码或存储过程中受损的数据。控制器101还可以将从主机计算机11接收到的数据和计算得到的RAID校验数据发送给三维非易失性存储器102进行存储。
主机计算机11是用于执行三维非易失性存储器102的数据处理的专用处理器。例如，主机计算机11可以包括中央处理单元(central processing unit，CPU)或片上系统(system-on-chip，SoC)，例如应用处理器。数据在主机计算机11和控制器101之间通过多种接口协议中的至少一种进行传输。
例如，接口协议包括通用串行总线(universal serial bus，USB)协议、微软管理控制台(microsoft management console，MMC)协议、外围部件互连(peripheral component interconnect，PCI)协议、PCI高速(peripheral component interconnect express，PCI-E)协议、高级技术附件(advanced technology attachment，ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(small computer system interface，SCSI)协议、集成驱动电子设备(integrated drive electronic，IDE)协议或者火线(firewire)协议中的至少一种。
在一些实施方式中，控制器101可以被配置为控制三维非易失性存储器102中的操作，例如读取、写入、擦除或者编码等操作。控制器101还可以被配置为管理三维非易失性存储器102中存储的或要存储的数据的各种功能，包括但不限于坏块管理、垃圾收集、逻辑到物理地址转换、或者损耗均衡等功能。在一些实施方式中，控制器101还被配置为对从三维非易失性存储器102中读取的数据或向三维非易失性存储器102写入的数据处理纠错码(error correction code，ECC)。当然，控制器101也可以对三维非易失性存储器102执行任何其他合适的功能，例如，对三维非易失性存储器102进行格式化，本申请实施例对此不做具体限定。
在一些实施方式中，控制器101可以通过生成的控制信号来控制三维非易失性存储器102的操作，以控制三维非易失性存储器102的数据的条带化、计算或者存储。或者，控制器101可以从主机计算机11中接收用于三维非易失性存储器102的操作的信号，以控制三维非易失性存储器102的数据的条带化、计算或者存储。
在一些实施方式中，控制器101可以在单个装置中具有不同的模块，该单个装置诸如集成电路芯片，例如，专用集成电路(application specific integrated circuits，ASIC)或现场可编程门阵列(field programmable gate array，FPGA)，或者具有专用功能的单独装置。在一些实施方式中，控制器101的部件可以在集成设备中，或者分布在不同位置但是彼此通过网络进行通信。
在一些实施例中，本公开中的三维非易失性存储器102可以为闪存，例如可以为NAND闪存。NAND闪存还可以简称为闪存或NAND。当然，本公开中的三维非易失性存储器102还可以是其他存储器，本申请对此不作限定，仅以三维非易失性存储器102为NAND闪存为例进行说明。
如图2所示，图2为本申请实施例提供的一种NAND闪存的结构示意图。为了增加存储容量，NAND闪存20通常包括多个管芯(DIE)201，例如D0和D1。每个DIE201具有多个面(plane，PL)，例如PL0、PL1、PL2和PL3。
其中，每个PL可包括一个或多个存储器区块，每个存储器区块可进一步划分成多个串(string，STR)。每个STR包括用于存储较上页(upper page，UP)数据部分、中页(middle page，MP)数据部分和较低页(lower page，LP)数据部分的存储器单元。存储器单元耦接到垂直排列的多条字线(wordline，WL)，以及耦接到水平排列的多条位线(bitline，BL)。在结构上，每个STR可包括横向延伸的多个栅极导电层。一个存储器区块包括多个层级垂直堆叠的多个栅极导电层，且每个栅极导电层耦接到横向分布在存储器区块中的STR中的多个页面中的存储器单元。随着栅极导电层的数量继续在垂直方向上增加，NAND闪存的存储容量也随之增加，并且相邻栅极导电层之间的空间变得更小，从而导致相邻栅极导电层之间的干扰变得显著。
为了改善存储器单元的完整性和可读性，RAID5已经广泛用于NAND闪存中。通常，RAID5采用存储器区块中的条带化将存储器区块中的存储器数据划分为多个数据部分，在条带中的数据部分之间执行异或(XOR)操作以生成相应的奇偶校验数据，并且将奇偶校验数据存储在存储器单元中。其中，一个条带可理解为包括位于两个维度中的数据部分，例如一个条带包括横向位于跨不同DIE和不同PL的不同存储器区块，且垂直位于相同存储器区块中的不同层级的数据。或者说，在横向方向上，一个条带可以包括在不同PL中的相同位置处的数据部分。在 垂直方向上，一个条带可以包括在不同层级中的相同位置处的数据部分。该数据部分包括条带的奇偶校验数据。在条带的一个数据部分中编程失败的情况下，可以通过使用条带的奇偶校验数据和条带中的其余数据部分执行XOR运算来恢复受损的数据。例如，对于具有128个数据部分的条带，127个数据部分用于存储存储器数据，1个数据部分用于存储条带的奇偶校验数据，因此使用这种条带化配置的RAID 5的纠错能力可被描述为(127+1)。即，一个奇偶校验数据部分保护127个存储器数据部分。
以三层单元(Triple-Level Cell，TLC)NAND为例，如表1所示，表1示出的是将要存储在三维非易失性存储器102中的存储器数据的部分或全部。存储器数据在被存储在三维非易失性存储器102之前需要由控制器101执行RAID计算操作。在一个示例中，假设存储器数据将被存储在两个DIE(DIE0和DIE1)中。其中，每个DIE包括4个PL：PL0、PL1、PL2和PL3。每个PL包括6个STR：STR0、STR1、STR2、STR3、STR4和STR5，且每个STR包括用于存储UP数据部分、MP数据部分和LP数据部分的存储器单元。存储器单元耦接到垂直排列的多个字线。
为了便于描述，在表1中，字线标有字线编号，例如WL0和WL1等。同时，为了便于图示，对数据部分(例如UP数据部分、MP数据部分和LP数据部分)也进行了进行编号。例如，存储在第0串(STR0)中的存储器单元中且耦接到第0字线(WL0)的LP数据部分具有数据编号“0”；存储在第0串(STR0)中的存储器单元中且耦接到第0字线(WL0)的MP数据部分具有数据编号“1”；存储在第0串(STR0)中的存储器单元中且耦接到第0字线(WL0)的UP数据部分具有数据编号“2”。其中，存储在耦接到不同面中的相同页面的相同字线的存储器单元中的数据部分具有相同的数据编号。例如存储在耦接到PL0和PL1中WL0的存储器单元中的数据部分具有相同的数据编号“0”。
其中，在表1中，字线的数量可从32、64、96、128变化到256。应当注意的是，RAID操作可以应用于任何合适的三维非易失性存储器102，不限于三维非易失性存储器102的管芯、面、串和字线的确切数量的限制。在一些实施方式中，在每个PL(例如PL0和PL1)中，每个层级的字线可以(例如WL0)耦接到18个数据部分(例如0-17数据部分)。
表1
Figure PCTCN2022133312-appb-000001
Figure PCTCN2022133312-appb-000002
由于WL0和WL1之间存在干扰，为了实现对数据的保护，控制器101在从主机计算机11接收到数据时，可采用RAID5，并基于两个字线分别对应的数据页(data page)的页面数据计算得到RAID校验数据，即采用两个字线对应的页面数据进行数据保护。
在一个示例中，例如在包括2个DIE的TLC NAND中，1个字线和18个页面(page)耦接,每个页面包括1个校验页(parity page)和127个数据页。其中，校验页中的RAID校验数据是通过页中的127个数据页计算得到的。即1个校验页可用于保护127个data page。由此，两个字线对应36个校验页。36个校验页为一个轮(round)。如图3所示，图3中示出了DIE0和DIE1中的576个页行(page line)，记为P0～P575。每个页行包括多个PL的页面。其中，轮0(301)包括P0-P35，轮2(302)包括P36-P71，……，轮16包括P540-P575(303)。也即存储576个页面需要16个轮，16个轮为一个集(fund)。
其中，当控制器101接收到数据和计算得到RAID校验数据时，都需先对接收到的数据和RAID校验数据进行缓存后，再发送至NAND闪存进行存储。因此，这里先对控制器101中的存储空间进行介绍。
如图4所示为控制器101中的存储空间类型示意图。存储空间可包 括读缓存(read buffer)空间、复制缓存(copy buffer)空间或者校验缓存(parity buffer，PB)空间等，图4仅是示例性示意，并不限定控制器101中还包括其他缓存空间。其中，校验缓存空间可用于存储RAID校验数据和垃圾回收(garbage collection，GC)数据。
基于图4的说明，在一个示例中，若采用两个字线进行RAID校验保护的方式，两个字线对应的RAID校验数据和垃圾回收数据通常需要1152KB的存储空间进行缓存。由于校验缓存空间的存储空间有限，通常只有320KB的存储空间提供给RAID校验数据和垃圾回收数据使用，因此控制器101需要通过swap操作来分时共享有限的校验缓存空间。
如图5所示，图5为本申请实施例提供的一个轮计算得到RAID校验数据的示意图。其中，竖轴的P0-P35表示一个轮中的36个页行的索引(page line index)。假设控制器101在缓存RAID校验数据时分配到12个PB，每个PB的容量为16KB，用于存储1个校验页的RAID校验数据。其中，横轴表示每12个PB(0-11PB)在不同阶段的使用状态，例如t1时刻至t17时刻。例如，控制器101在t1时刻可计算得到3个PB的RAID校验数据，例如P0-P2。在t2时刻也可计算得到3个PB的RAID校验数据，例如P3-P5，此时已经存储6个PB的RAID校验数据，例如P0-P5。在t3时刻计算得到2个PB的RAID校验数据时，例如P6和P7，此时已经存储8个PB的RAID校验数据，例如P0-P7，在t4时刻执行一次swap操作。即每8个PB存储满RAID校验数据时，控制器101需要执行一次swap操作，即备份(backup)已经计算完成的8个校验页的RAID校验数据到三维非易失性存储器102中。而后，三维非易失性存储器102可恢复(restore)得到8个即将要使用的校验页的RAID校验数据。
其中，上述swap操作的流程可以参见图6，图6示出了一种swap操作的流程示意图。在每8个PB存储满RAID校验数据时，存储控制器101需先发送程序命令(program command)，以加载交换操作(load swap)，而后等待计算(wait encoding)、计算(encoding)、结束计算(encoding done)和执行交换程序(prog swap)。
由此，在一个轮中，控制器101总计需进行5次swap操作，分别是t4时刻、t7时刻、t10时刻、t13时刻和t16时刻。每次swap操作包括对8个校验页的计算操作和8个校验页的读取操作。甚至在某次swap操作时需要等待上一次swap操作完成才能继续发送程序命令用于执行下一 次swap操作，控制器101的写入性能较低。
本申请实施例提供一种存储系统操作方法。该方法以一个字线对应的页面数据为单位，计算得到RAID校验数据并将该RAID校验数据缓存到缓存模块的校验缓存空间，该校验缓存空间在缓存第一个RAID校验数据后继续缓存第二RAID校验数据，并将第二RAID校验数据覆盖第一个RAID校验数据。由于本公开提供的存储系统操作方法中，RAID校验数据由一个字线对应的页面数据计算得到，校验缓存空间可满足缓存RAID校验数据，因此本申请的RAID校验存储过程可以降低存储压力，减少控制器101执行swap操作的次数，从而提高控制器的写入性能。
如图7所示，图7为本申请实施例提供的一种控制器的结构示意图。
其中，控制器101可以执行计算操作，例如控制器101以一个字线对应的页面数据为单位，分别对接收到的第一字线对应的页面数据进行计算，得到第一个RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间。在一个实施例中，第一个RAID校验数据可以由第一字线对应的18个页面数据计算得到，因此第一个RAID校验数据可以对应于18个校验页的数据。
另外，控制器101和三维非易失性存储器102耦合，并且可以响应控制信号来执行数据写入操作或数据读取操作。控制器101可以被配置为临时存储主机计算机11和三维非易失性存储器102之间传输的数据。例如，在主机计算机11向三维非易失性存储器102写入数据或者主机计算机11从三维非易失性存储器102读取数据期间，控制器101可以被配置为临时存储一个字线对应的页面数据或以一个字线对应的页面数据为单位计算的RAID校验数据。在一些实施方式中，控制器101可以包括静态随机存储器(static random access memory，SRAM)或者动态随机存储器(dynamic random access memory，DRAM)，本申请实施例对此不做具体限定。
另外，控制器101可以经由数据总线与三维非易失性存储器102之间提供数据和控制通信。
控制器101可以包括任何适当类型的通用或专用微处理器、数字信号处理器或微控制器。控制器101可以被配置为专用于对信号进行分析或对扫描方案进行控制的独立处理器模块。可选的，控制器101也可以被配置为用于执行与信号分析/扫描方案无关的其他功能的共享处理器模块。控制器101可以包括可以使用软件、硬件、中间件、固件或其任 何组合来实现的多个功能单元或模块。多个功能单元可以基于来自主机计算机11的信号或预先存储的控制数据来对RAID校验数据的存储执行读取、写入、擦除、条带化、计算、决策制定或者控制等操作。
在一些实施方式中，控制器101可以执行配置工作，例如设置写缓存空间的第一存储空间用于缓存RAID校验数据。在一些实施方式中，控制器101也可以执行swap操作。
应用于图1所示的存储系统结构，本申请实施例提供一种存储系统操作方法。如图8所示，图8为本申请实施例提供的一种存储系统操作方法的流程图。该方法包括：
步骤801、控制器101以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个RAID校验数据，并将第一个RAID校验数据存储至校验缓存空间。
在一些实施例中，如图9所示，图9为本申请实施例提供的采用一个字线进行数据保护的数据的结构示意图。其中，一个字线对应的页面数据可以为18个页面的数据。图9中示出了DIE0和DIE1中的288个页的数据，其中，轮0(901)包括P0-P17，轮1(902)包括P18-P31，……，轮16(903)包括P270-P287。也即存储288个页需要16个轮，其中，16个轮为一个集。
其中，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
在一些实施例中，控制器101可以对一个字线对应的页面数据执行异或操作，得到第一个RAID校验数据。在一个示例中，若一个字线对应的18页数据中的一页数据为d1、d2、d3、d4和d5，则这一页对应的RAID校验数据为
Figure PCTCN2022133312-appb-000003
另外，控制器101可以采用奇偶校验(parity check)算法对计算得到的第一个RAID校验数据添加奇偶校验位。奇偶校验可以理解为根据被传输的一组二进制代码的数位中“1”的个数是奇数或偶数来进行校验，其中，采用奇数的称为奇校验，反之，称为偶校验。
其中，若采用奇校验的方式，则将第一个RAID校验数据执行异或操作后，再将结果与“1”相异或，可以得到第一个RAID校验数据中奇校验位的值。若采用偶校验的方式，则将第一个RAID校验数据执行异或操作后，再将结果与“0”相异或，可以得到第一个RAID校验数据中偶校验位的值。由此可以保证第一个RAID校验数据的准确性。
另外，RAID校验数据还可以是对一个字线对应的页面数据执行除异或操作以外的其他操作，本申请不进行限定。
需要说明的是，一个字线对应的页面数据可以是主机计算机11向三维非易失性存储器102预写入的数据，例如页面数据可以是符号、文字、数字、语音、图像、视频或者其组合的二进制的数字数据。
步骤802、控制器101对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将第i+1个RAID校验数据存储至校验缓存空间中，第i+1个RAID校验数据覆盖第i个RAID校验数据，i为大于等于1的正整数。
控制器101在将第一个RAID校验数据存储至校验缓存空间后，可以对接收到的第二字线对应的页面数据和第一个RAID校验数据执行计算操作，得到第二个RAID校验数据。其中，假设第一字线对应18页的页面数据，分别为D1、D2、……、D18，分别对D1-D18的页面数据进行异或操作，每个页的页面数据对应得到一组RAID校验数据，则第一个RAID校验数据可以包括18组RAID校验数据，分别为P1、P2、……、P18。第二字线也对应18页的页面数据，分别为D19、D20、……、D36，此时将第二字线对应的页面数据中的第一页的数据D19和18组RAID校验数据中的第一组RAID校验数据P1执行异或操作，得到第二个RAID校验数据中的第一组RAID校验数据P19，即
Figure PCTCN2022133312-appb-000004
第二个RAID校验数据中的其余组的RAID校验数据也可以采用与第二个RAID校验数据中的第一组RAID校验数据类似的方法得到。而后，控制器101将计算得到的第二个RAID校验数据覆盖第一个RAID校验数据存储至校验缓存空间。
由此可以推导，控制器101在将第i个RAID校验数据存储至校验缓存空间后，可以对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据。可选的，如图10所示，图10为本申请实施例提供的另一种存储系统的操作方法。该方法还可以包括步骤803、当i的取值为w-1时，控制器101将第w个RAID校验数据写入三维非易失性存储器102，w为一个集对应的字线的数量。
在本申请实施例中，若一个集中包括w个字线，在第w字线为当前数据存储过程中的最后一个字线的情况下，控制器101在将第w个RAID校验数据缓存在校验缓存空间后，再将第w个RAID校验数据发送至三维非易失性存储器102。例如，若一个集包括16个字线，即w＝16时， 此时，对接收到的第15字线对应的页面数据和第14个RAID校验数据执行异或操作，可以得到第15个RAID校验数据，并将第15个RAID校验数据覆盖第14个RAID校验数据存储至校验缓存空间。对于接收到的第16字线对应的页面数据和第15个RAID校验数据执行异或操作，可以得到第16个RAID校验数据，并将第16个RAID校验数据覆盖第15个RAID校验数据存储至校验缓存空间。此时，控制器101已经对一个集的字线对应的页面数据完成RAID校验数据的计算，从而可以将第16个RAID校验数据发送至三维非易失性存储器102。其中，若一个集的字线对应的任意一个页面数据出现损坏，可以根据第16个RAID校验数据和一个集的字线对应的其他页面数据进行恢复。
本领域技术人员可以理解的是，三维非易失性存储器102中的有效数据可能由于存储器单元的物理状态或者存储过程中的编程干扰等原因，使得存储于三维非易失性存储器102中的有效数据位翻转而转变为错误数据。由此，需要将错误数据恢复为有效数据。由此，将RAID校验数据也存入三维非易失性存储器102中，可以根据与有效数据对应的RAID校验数据恢复有效数据，提高了三维非易失性存储器102存储有效数据的正确性。
可选的，在步骤801之前，该方法还可以包括：
步骤804、在校验缓存空间不足的情况下，控制器101设置写缓存空间的第一存储空间用于缓存RAID校验数据。
如图11所示，图11为本申请实施例提供的一种存储空间示意图。在一个示例中，若采用一个字线保护的方式，RAID校验数据和垃圾回收数据总计需要448KB的存储空间。假设校验缓存空间的容量为384KB，则控制器101可以分配写缓存空间中的第一存储空间的容量为128KB，用于缓存RAID校验数据。此时，校验缓存空间中用于存储RAID校验数据和垃圾回收数据的总存储空间为512KB，控制器101可以从校验缓存空间中分配448KB的存储空间用于缓存RAID校验数据和垃圾回收数据，剩余存储空间可以用于存储其他系统数据。
当然，由于校验缓存空间中用于存储RAID校验数据和垃圾回收数据的总存储空间为512KB，若采用一个字线保护的方式，RAID校验数据和垃圾回收数据总计需要的存储空间大于512KB，则控制器101可以从校验缓存空间中分配部分存储空间用于缓存RAID校验数据和垃圾回收数据，剩余存储空间可以用于存储其他系统数据。例如，RAID校验数 据和垃圾回收数据总计需要576KB的存储空间，控制器101可以从校验缓存空间中分配448KB的存储空间用于缓存RAID校验数据和垃圾回收数据。其中，从校验缓存空间中分配的用于缓存RAID校验数据和垃圾回收数据的部分存储空间优先保证RAID校验数据的存储，剩余存储空间用于存储垃圾回收数据。
其中，在校验缓存空间的448KB的存储空间中，控制器101分配18个PB的存储空间用于存储RAID校验数据，每个PB占用16KB。在第一个RAID校验数据包括18组RAID校验数据的情况下，此时校验缓存空间缓存RAID校验数据时无需进行swap操作，实现了RAID校验数据缓存的连续性，可以提高控制器的写入性能。
需要说明的是，在确定第一存储空间的容量时，应先保证写缓存空间的使用。
可选的，该方法还可以包括：
步骤805、控制器101将第一字线对应的页面数据至第i+1字线对应的页面数据存储在写缓存空间的第二存储空间中。
示例性的，写缓存空间的第二存储空间可以缓存主机计算机11和三维非易失性存储器102之间传递的数据，也即多个字线对应的页面数据。写缓存空间的第二存储空间在缓存数据时，以一个字线对应的页面数据为单位进行存储。由此，在主机计算机11和三维非易失性存储器102之间执行读取或写入操作时，将多个字线对应的页面数据存储在写缓存空间的第二存储空间中，可以提高主机计算机11向三维非易失性存储器102读取或写入数据的速率。
其中，写缓存空间的第二存储空间的配置优先级高于第一存储空间的配置优先级。
示例性的，控制器101应在满足多个字线对应页面的数据需缓存的第二存储空间的容量下，再分配第一存储空间至校验缓存空间用以缓存RAID校验数据。
此外，在本公开的一些实施例中，若校验缓存空间的容量加上第一存储空间的容量足以缓存全部RAID校验数据，则控制器101无需执行swap操作即可缓存全部RAID校验数据，提高了控制器的写入性能。
在本公开的一些实施例中，若校验缓存空间的容量加上第一存储空间的容量可能仍不足以缓存全部RAID校验数据，可以通过执行swap操作来分时共享第一存储空间和校验缓存空间，但较于两个字线保护的方 式，由于其执行swap的操作的次数减少，因此依然可提高控制器的写入性能。
在本公开的一些实施例中，校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，校验数据缓存空间用于缓存RAID校验数据，垃圾回收缓存用于缓存垃圾回收数据，垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
在一个示例中，在控制器101从写缓存空间分配了128KB的第一存储空间至校验缓存空间后，可以分配10个PB用于存储垃圾回收数据。
示例性的，由于三维非易失性存储器102中的多个数据块中存储的无效数据的量可能随着越多地处理来自主机计算机11的编码命令而增加，因此为了重复使用存储这种无效数据的数据块，可执行GC操作。例如，控制器101可执行GC操作以将有效数据所存储的数据块改变为空闲块。另外，可以在控制器101中设置若剩余空闲块的数量等于或小于阈值时触发GC机制。当触发GC机制时，控制器101可以识别三维非易失性存储器102中的多个数据块中的封闭块，将封闭块之中有效页面数量小于阈值的封闭块作为牺牲块。控制器101可以复制牺牲块中的有效数据，并且将这些有效数据存储在尚未被执行编码操作的作为空闲块的目标块中。在将有效数据复制并存储在目标块中之后，控制器101可以擦除牺牲块。
在GC操作期间，为了将数据从三维非易失性存储器102的封闭块移动到空闲块，控制器101可以从三维非易失性存储器102的封闭块读取数据，将读取数据加载到缓存空间中，然后将缓存空间存储的数据写入到空闲块中。由于控制器101对三维非易失性存储器102执行读取/写入操作，所以当执行GC操作的同时从主机计算机11传送读取命令或写入命令时，控制器101可停止GC操作以执行该命令的操作。
其中，GC机制在执行过程中，控制器101会标记有效数据和无效数据。其中，标记无效数据的方法称为垃圾标记算法，该算法可以分为引用计数算法和根搜索算法。
其中，引用计数算法是对每一个数据都维护一个内存字段来统计该数据被引用的数量，当数据被引用的时候计数器加1，引用失效后减1，当计数器的计数为0时，该数据被标记为无效数据，等待下一步的回收。根搜索算法是从一个名为“GC Roots”的数据作为根出发点，通过引用关系遍历对象图，搜索过的路径称为引用链。当一个数据与GC Roots之 间没有任何的引用链，即从GC Roots到该数据不可到达，则该数据被标记为无效数据，等待下一步的回收。
可选的，如图10所示，在步骤801之前，该方法还包括：
步骤806、控制器101在上电后执行交换操作。
在一个实施例中，在控制器101上电后，控制器101可以执行加载交换操作的程序，以对校验缓存空间和写缓存空间等进行初始化。
在本申请实施例中，在存储控制器上电后，执行swap操作。在RAID校验数据的缓存过程中，校验缓存空间可满足基于一个字线对应的页面数据计算得到的RAID校验数据。由此，本申请的RAID校验数据缓存过程无需执行swap操作，实现了RAID校验数据缓存的连续性，提高了控制器的写入性能。
在一些实施例中，也可以由主机计算机11向控制器101发出重置信号，重置信号用于清空缓存空间中缓存的数据。
可选的，该方法还包括：在对接收到的第i字线对应的页面数据计算完成之后，连续执行第i+1字线对应的页面数据的计算操作。
如图12所示，图12为本申请实施例提供的一种控制器缓存数据的流程图。在控制器101上电后，控制器101执行加载交换操作的程序。在执行交换操作后，会执行等待计算、计算、计算完成等步骤，然后重复执行以上步骤。例如，对于第i字线和第i+1字线，控制器101会连续执行以下步骤：a.等待计算第i字线对应的页面数据；b.计算第i字线对应的页面数据；c.第i字线对应的页面数据计算完成；d.等待计算第i+1字线对应的页面数据；e.计算第i+1字线对应的页面数据；f.第i+1字线对应的页面数据计算完成。
其中，第i+1个RAID校验数据用于校验第一字线至第i+1字线对应的页面数据。
在一个实施例中，在第i+1字线为当前数据存储过程中的最后一个字线的情况下，控制器101可以将第i+1个RAID校验数据存储至三维非易失性存储器102。此时，第i+1个RAID校验数据可以用来校验第一字线至第i+1字线对应的页面数据，即若第一字线至第i+1字线对应的页面数据中的任意数据出现了损坏，可以根据第i+1个RAID校验数据和第一字线至第i+1字线对应的其他数据进行恢复。
如图13所示，图13为本申请实施例提供的一种电子设备的结构示意图。该电子设备100包括主机计算机11和本公开的一些实施例中的存储系统10。
其中，存储系统10可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(universal flash storage，UFS)封装或嵌入式多媒体卡(embedded multi media card，eMMC)封装)中。也就是说，存储系统10可以应用于并且封装到不同类型的电子产品中，例如，移动电话(例如手机)、台式计算机、平板电脑、笔记本电脑、服务器、车载设备、游戏控制台、打印机、定位设备、可穿戴设备、智能传感器、移动电源、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备或者其中具有储存器的任何其他合适的电子设备。
在一些实施例中，存储系统10可以包括控制器101和一个三维非易失性存储器102，存储系统10可以被集成到存储器卡中。
其中，存储器卡包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、紧凑型闪存(compact flash，CF)卡、智能媒体(smart media，SM)卡、存储器棒、多媒体卡(multimedia card，MMC)、安全数码(secure digital memory card，SD)卡或者UFS中的任一种。
在另一些实施例中，参见图1，存储系统10包括存储控制器101和多个三维非易失性存储器102，存储系统10集成到固态硬盘(solid state drives，SSD)中。
在存储系统10中，在一些实施例中，存储控制器101被配置为用于在低占空比环境中操作，例如，SD卡、CF卡、通用串行总线(universal serial bus，USB)闪存驱动器、或用于个人计算器、数字相机、移动电话等电子设备中使用的其他介质。
在另一些实施例中，控制器101被配置为用于在高占空比环境SSD或eMMC中操作，SSD或eMMC用于智能电话、平板电脑或者笔记本电脑等移动设备的数据储存器以及企业存储阵列。
本公开的一些实施例还提供了一种电子设备。电子设备可以是手机、台式计算机、平板电脑、笔记本电脑、服务器、车载设备、可穿戴设备(例如智能手表、智能手环、智能眼镜等)、移动电源、游戏机、数字多媒体播放器等中的任一种。
电子设备可以包括上文所述的存储系统10，还可以包括中央处理器和缓存器(cache)等中的至少一种。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因 此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种存储系统，其特征在于，包括控制器和三维非易性失存储器，所述三维非易失性存储器包括三维存储阵列，所述三维存储阵列包括耦合的多个字线和多个页面；所述控制器耦合至所述三维非易失性存储器，所述控制器被配置为：
    以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个独立冗余磁盘阵列RAID校验数据，并将所述第一个RAID校验数据存储至校验缓存空间；
    对接收到的第i+1字线对应的页面数据和第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将所述第i+1个RAID校验数据存储至所述校验缓存空间，所述第i+1个RAID校验数据覆盖所述第i个RAID校验数据，i为大于等于1的正整数。
  2. 根据权利要求1所述的存储系统，其特征在于，所述控制器还被配置为：当i的取值为w-1时，将第w个RAID校验数据写入所述三维非易失性存储器，w为一个集对应的字线的数量。
  3. 根据权利要求1所述的存储系统，其特征在于，所述控制器还被配置为：
    在所述校验缓存空间不足的情况下，设置写缓存空间的第一存储空间用于缓存RAID校验数据。
  4. 根据权利要求3所述的存储系统，其特征在于，所述控制器还被配置为：
    将所述第一字线对应的页面数据至所述第i+1字线对应的页面数据存储在所述写缓存空间的第二存储空间中。
  5. 根据权利要求4所述的存储系统，其特征在于，所述写缓存空间的所述第二存储空间的配置优先级高于所述第一存储空间。
  6. 根据权利要求4所述的存储系统，其特征在于，所述校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，所述校验数据缓存空间用于缓存所述RAID校验数据，所述垃圾回收缓存用于缓存垃圾回收数据，所述垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
  7. 根据权利要求1所述的存储系统，其特征在于，所述控制器还被配置为：
    在上电后执行交换操作。
  8. 根据权利要求1所述的存储系统，其特征在于，所述控制器还被配置为：
    在对接收到的第i字线对应的页面数据计算完成之后，连续执行所述第 i+1字线对应的页面数据的计算操作。
  9. 根据权利要求1所述的存储系统，其特征在于，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
  10. 根据权利要求1所述的存储系统，其特征在于，所述第i+1个RAID校验数据用于校验所述第一字线至所述第i+1字线对应的页面数据。
  11. 一种存储系统的操作方法，其特征在于，所述存储系统包括控制器和三维非易失性存储器，所述三维非易失性存储器包括三维存储阵列，所述三维存储阵列包括耦合的多个字线和多个页面；所述控制器耦合至所述三维非易失性存储器，所述方法包括：
    所述控制器以一个字线对应的页面数据为单位，对接收到的第一字线对应的页面数据进行计算，得到第一个独立冗余磁盘阵列RAID校验数据，并将所述第一个RAID校验数据存储至校验缓存空间；
    所述控制器对接收到的第i+1字线对应的页面数据和所述第i个RAID校验数据进行计算，得到第i+1个RAID校验数据，并将所述第i+1个RAID校验数据存储至所述校验缓存空间中，所述第i+1个RAID校验数据覆盖所述第i个RAID校验数据，i为大于等于1的正整数。
  12. 根据权利要求11所述的方法，其特征在于，所述方法还包括：当i的取值为w-1时，所述控制器将第w个RAID校验数据写入所述三维非易失性存储器，w为一个集对应的字线的数量。
  13. 根据权利要求11所述的方法，其特征在于，在将所述第一个RAID校验数据存储至校验缓存空间之前，所述方法还包括：
    在所述校验缓存空间不足的情况下，所述控制器设置写缓存空间的第一存储空间用于缓存RAID校验数据。
  14. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    所述控制器将所述第一字线对应的页面数据至所述第i+1字线对应的页面数据存储在所述写缓存空间的第二存储空间中。
  15. 根据权利要求14所述的方法，其特征在于，所述写缓存空间的所述第二存储空间的配置优先级高于所述第一存储空间。
  16. 根据权利要求14所述的方法，其特征在于，所述校验缓存空间包括校验数据缓存空间和垃圾回收缓存空间，所述校验数据缓存空间用于缓存所述RAID校验数据，所述垃圾回收缓存用于缓存垃圾回收数据，所述垃圾回收数据包括页面数据中需回收的数据对应的RAID校验数据。
  17. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    所述控制器在上电后执行交换操作。
  18. 根据权利要求11所述的方法，其特征在于，所述方法还包括：
    所述控制器在对接收到的第i字线对应的页面数据计算完成之后，连续执行所述第i+1字线对应的页面数据的计算操作。
  19. 根据权利要求11所述的方法，其特征在于，RAID校验数据是对一个字线对应的页面数据执行异或操作得到。
  20. 根据权利要求11所述的方法，其特征在于，所述第i+1个RAID校验数据用于校验所述第一字线至所述第i+1字线对应的页面数据。
  21. 一种电子系统，其特征在于，包括主机计算机和如权利要求1至10任一项所述的存储系统。
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