WO2024105516A1 - 半導体装置、及びその作製方法 - Google Patents

半導体装置、及びその作製方法 Download PDF

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Publication number
WO2024105516A1
WO2024105516A1 PCT/IB2023/061351 IB2023061351W WO2024105516A1 WO 2024105516 A1 WO2024105516 A1 WO 2024105516A1 IB 2023061351 W IB2023061351 W IB 2023061351W WO 2024105516 A1 WO2024105516 A1 WO 2024105516A1
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Prior art keywords
layer
insulating layer
conductive layer
opening
semiconductor
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PCT/IB2023/061351
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English (en)
French (fr)
Japanese (ja)
Inventor
肥塚純一
神長正美
島行徳
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US19/123,202 priority Critical patent/US20260040620A1/en
Priority to CN202380073158.9A priority patent/CN120077758A/zh
Priority to JP2024558479A priority patent/JPWO2024105516A1/ja
Priority to KR1020257015702A priority patent/KR20250111306A/ko
Publication of WO2024105516A1 publication Critical patent/WO2024105516A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0318—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] of vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a manufacturing method thereof.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a CPU Central Processing Units
  • memories and other LSIs (Large Scale Integrations) are mainly used in semiconductor devices.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are processed from semiconductor wafers and made into chips, and on which electrodes that serve as connection terminals are formed.
  • CPUs, memories, and other LSI semiconductor circuits are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply called display devices).
  • image display devices also simply called display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Literature 1 discloses a low-power consumption CPU that utilizes the property of small leakage current.
  • Patent Literature 2 discloses a memory device that can retain stored contents for a long period of time.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulating layer.
  • An object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Or, an object of the present invention is to provide a semiconductor device with reduced parasitic capacitance. Or, an object of the present invention is to provide a semiconductor device that operates at high speed. Or, an object of the present invention is to provide a highly reliable semiconductor device. Or, an object of the present invention is to provide a semiconductor device that exhibits favorable electrical characteristics.
  • Another object of the present invention is to provide a method for manufacturing a miniaturized semiconductor device.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device with reduced parasitic capacitance.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device that operates at high speed.
  • Another object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device with a high yield.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device that exhibits good electrical characteristics.
  • One aspect of the present invention includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and wiring, the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a fourth insulating layer, the first insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the second insulating layer is provided on the second conductive layer, the first insulating layer, the second conductive layer, and the second insulating layer have a first opening that reaches the first conductive layer, the semiconductor layer is located inside the first opening, and A semiconductor device having a region in contact with the first conductive layer and a region in contact with the second conductive layer, a fourth insulating layer is provided between the semiconductor layer and the third conductive layer inside the first opening, the third conductive layer is provided so as to fill the first opening, the third insulating layer is provided on the second insulating layer, the semiconductor layer, the
  • one aspect of the present invention includes a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a wiring
  • the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a fourth insulating layer
  • the first insulating layer is provided on the first conductive layer
  • the second conductive layer is provided on the first insulating layer
  • the first insulating layer and the second conductive layer have a first opening that reaches the first conductive layer
  • the second insulating layer is provided on the second conductive layer
  • the second insulating layer has a second opening that reaches the second conductive layer and has a region overlapping with the first opening
  • the semiconductor layer includes an inside of the first opening
  • the semiconductor device is located inside the second opening and has a region in contact with the first conductive layer and a region in contact with the second conductive layer
  • the fourth insulating layer is provided between the semiconductor layer and the third conductive layer inside
  • the semiconductor layer may have a region in contact with the upper surface of the second conductive layer.
  • the height of the upper surface of the second insulating layer, the height of the upper surface of the semiconductor layer, the height of the upper surface of the fourth insulating layer, and the height of the upper surface of the third conductive layer may be the same or approximately the same as each other.
  • the semiconductor layer may contain a metal oxide.
  • the metal oxide has two or three elements selected from In, element M, and Zn, and element M may be one or more elements selected from Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.
  • one aspect of the present invention is a method for manufacturing a semiconductor device that includes forming a first insulating layer, forming a first conductive layer on the first insulating layer, forming a second insulating layer on the first conductive layer, forming a first opening in the second insulating layer, the first conductive layer, and the first insulating layer, forming a semiconductor layer having a region in contact with the first conductive layer inside the first opening, a third insulating layer on the semiconductor layer, and a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second insulating layer, the semiconductor layer, the third insulating layer, and the second conductive layer, forming a second opening in the fourth insulating layer that reaches the second conductive layer, and forming wiring so that the wiring has a region in contact with the second conductive layer inside the second opening and has a region that overlaps with the semiconductor layer via the fourth insulating layer.
  • a semiconductor film, an insulating film on the semiconductor film, and a conductive film on the insulating film may be formed so as to have a region located inside the first opening and a region overlapping with the second insulating layer, and a planarization process may be performed on the conductive film, insulating film, and semiconductor film to expose the top surface of the second insulating layer, thereby forming a semiconductor layer, a third insulating layer, and a second conductive layer.
  • One aspect of the present invention can provide a miniaturized semiconductor device.
  • a semiconductor device with reduced parasitic capacitance can be provided.
  • a semiconductor device that operates at high speed can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device that exhibits good electrical characteristics can be provided.
  • a method for manufacturing a miniaturized semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with reduced parasitic capacitance can be provided.
  • a method for manufacturing a semiconductor device that operates at high speed can be provided.
  • a method for manufacturing a highly reliable semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with a high yield can be provided.
  • a method for manufacturing a semiconductor device that exhibits good electrical characteristics can be provided.
  • a semiconductor device, a memory device, a display device, or an electronic device having a novel configuration can be provided.
  • a method for manufacturing a semiconductor device, a memory device, a display device, or an electronic device having a novel configuration can be provided.
  • One aspect of the present invention can at least alleviate at least one of the problems of the prior art.
  • FIG. 1A and 1B are perspective views showing a configuration example of a semiconductor device.
  • Fig. 2A is a plan view showing a configuration example of a semiconductor device
  • Fig. 2B and Fig. 2C are cross-sectional views showing the configuration example of the semiconductor device.
  • 3A and 3B are cross-sectional views showing a configuration example of a semiconductor device.
  • 4A and 4B are cross-sectional and plan views illustrating an example of the configuration of a semiconductor device.
  • Fig. 5A is a plan view showing a configuration example of a semiconductor device
  • Fig. 5B and Fig. 5C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 6A is a plan view showing a configuration example of a semiconductor device
  • Fig. 6A is a plan view showing a configuration example of a semiconductor device
  • Fig. 6A is a plan view showing a configuration example of a semiconductor device
  • Fig. 6A is a plan view showing
  • FIG. 6B and Fig. 6C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 7A is a plan view showing a configuration example of a semiconductor device
  • Fig. 7B and Fig. 7C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 8A is a plan view showing a configuration example of a semiconductor device
  • Fig. 8B and Fig. 8C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 9A is a plan view showing a configuration example of a semiconductor device
  • Fig. 9B and Fig. 9C are cross-sectional views showing the configuration example of a semiconductor device.
  • 10A to 10C are cross-sectional views showing configuration examples of a semiconductor device.
  • FIG. 11A to 11C are plan views showing configuration examples of a semiconductor device.
  • Fig. 12A is a plan view showing a configuration example of a semiconductor device
  • Fig. 12B and Fig. 12C are cross-sectional views showing the configuration example of a semiconductor device.
  • 13A to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 14A and 14B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 15A and 15B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 16A and 16B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 17A and 17B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 18A and 18B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 19A and 19B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 20 is a circuit diagram showing an example of the configuration of a storage device.
  • 21A1 and 21A2 are plan views showing a configuration example of a storage device, and Fig. 21B and Fig. 21C are cross-sectional views showing a configuration example of a storage device.
  • Fig. 22A is a plan view showing a configuration example of a storage device, and Fig. 22B and Fig.
  • FIG. 22C are cross-sectional views showing the configuration example of the storage device.
  • 23A is a plan view showing a configuration example of a storage device
  • FIG 23B is a cross-sectional view showing the configuration example of a storage device.
  • 24A is a plan view showing a configuration example of a storage device
  • FIG 24B is a cross-sectional view showing the configuration example of a storage device.
  • 25A is a plan view showing a configuration example of a storage device
  • FIG 25B is a cross-sectional view showing the configuration example of a storage device.
  • FIG. 26 is a cross-sectional view showing a configuration example of a storage device.
  • FIG. 27 is a block diagram showing an example of the configuration of a storage device.
  • FIG. 28A and 28B are a perspective view and a circuit diagram showing a configuration example of a memory device;
  • Fig. 29A is a circuit diagram showing a configuration example of a storage device,
  • Fig. 29B is a block diagram showing a configuration example of a storage device,
  • Fig. 29C is a circuit diagram showing a configuration example of a storage device,
  • Fig. 29D is a block diagram showing a configuration example of a storage device.
  • FIG. 30 is a block diagram showing an example of the configuration of a storage device.
  • 31A and 31B are perspective views showing a configuration example of a display device.
  • FIG. 32 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 29A is a circuit diagram showing a configuration example of a storage device
  • Fig. 29B is a block diagram showing a configuration example of a storage device
  • Fig. 29C is a circuit diagram showing a configuration example of a storage device
  • FIG. 33 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 34 is a cross-sectional view showing a configuration example of a display device.
  • Fig. 35A is a plan view showing a configuration example of a display device, and Fig. 35B and Fig. 35C are cross-sectional views showing the configuration example of the display device.
  • 36A and 36B are cross-sectional views showing a configuration example of a display device.
  • 37A to 37D are diagrams showing an example of an electronic device.
  • 38A to 38F are diagrams showing an example of an electronic device.
  • 39A to 39G are diagrams showing an example of an electronic device.
  • 40A and 40B are diagrams showing an example of an electronic component.
  • 41A to 41C are diagrams showing an example of a mainframe computer.
  • Fig. 42A is a diagram showing an example of space equipment
  • Fig. 42B is a diagram showing an example of a data center.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • electrically connected includes a connection via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switches such as transistors, resistors, coils, capacitance, and other elements with various functions.
  • the top surface shape of a certain component refers to the contour shape of the component when viewed from a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.
  • the top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in these cases, it may also be said that "the top surface shapes roughly match.”
  • film and “layer” may be interchangeable.
  • conductive layer and “insulating layer” may be interchangeable with the terms “conductive film” and “insulating film.”
  • a memory device and a display device are considered to be aspects of a semiconductor device.
  • a device having a circuit including a semiconductor element, a device that can function by utilizing semiconductor characteristics, and a device having a semiconductor material may be referred to as a semiconductor device.
  • a computing device and an imaging device may be considered to be aspects of a semiconductor device.
  • the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a vertical transistor or a vertical channel transistor, etc.
  • an insulating layer that functions as a first spacer is provided between a lower electrode, which is one of the source and drain electrodes of the transistor, and an upper electrode, which is the other, and an insulating layer that functions as a second spacer is provided on the upper electrode.
  • the insulating layer that functions as a spacer may be simply referred to as a spacer, but spacer may also be interpreted as an insulating layer.
  • a first opening is provided in the first spacer, the upper electrode, and the second spacer, reaching the lower electrode.
  • a semiconductor layer in which a channel is formed is provided inside the first opening so as to connect the lower electrode and the upper electrode.
  • a gate insulating layer and a gate electrode are provided inside the first opening, overlapping the semiconductor layer. Since the source electrode, the semiconductor layer, and the drain electrode can be provided overlapping, the occupied area can be significantly reduced compared to so-called planar type transistors in which the semiconductor layer is arranged on a flat surface.
  • the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode are planarized, and the heights of their upper surfaces can be the same or approximately the same.
  • An interlayer insulating layer is provided on the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode.
  • a second opening is provided in the interlayer insulating layer, reaching the gate electrode.
  • the gate electrode has a region inside the second opening that contacts the wiring provided on the interlayer insulating layer.
  • the heights are the same or approximately the same” refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are the same in a cross-sectional view.
  • a planarization process such as CMP (Chemical Mechanical Polishing) may be performed to expose the surface of a single layer or multiple layers.
  • CMP Chemical Mechanical Polishing
  • the surfaces treated in the CMP process have a configuration in which the heights from the reference surface are the same.
  • the heights of multiple layers may differ depending on the processing device, processing method, or material of the surface to be treated during the CMP process. In this specification, this case is also treated as "the heights are the same or approximately the same”.
  • the heights are the same or approximately the same.
  • the channel length of the transistor can be precisely controlled by the film thickness of the insulating layer that functions as the first spacer, and therefore the variation in the channel length can be made extremely small compared to planar type transistors. Furthermore, by making the insulating layer thin, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured.
  • a transistor with an extremely short channel length that could not be realized by a mass production exposure apparatus can be realized.
  • a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure apparatus used in cutting-edge LSI technology.
  • a transistor according to one embodiment of the present invention can have an extremely short channel length, a small occupied area, a large current, a small parasitic capacitance, and can operate at high speed.
  • FIG. 1A and 1B are schematic perspective views of a semiconductor device according to one embodiment of the present invention.
  • Fig. 1B is a perspective view in which a part of Fig. 1A is cut away.
  • Fig. 1A and 1B only the outlines of some components (such as an interlayer insulating layer) are indicated by dashed lines.
  • FIG. 2A shows an example of a planar configuration of a semiconductor device according to one embodiment of the present invention
  • FIG. 2B and FIG. 2C show examples of cross-sectional configurations taken along the cutting lines A1-A2 and B1-B2 in FIG. 2A, respectively.
  • some components e.g., insulating layers
  • FIG. 2A shows an example of a planar configuration of a semiconductor device according to one embodiment of the present invention
  • FIG. 2B and FIG. 2C show examples of cross-sectional configurations taken along the cutting lines A1-A2 and B1-B2 in FIG. 2A, respectively.
  • some components e.g., insulating layers
  • a semiconductor device includes a transistor 10, an insulating layer 11, an insulating layer 41, an insulating layer 42, an insulating layer 44, an insulating layer 45, an insulating layer 46, an insulating layer 49, and a conductive layer 33.
  • the transistor 10 is provided on the insulating layer 11 that is provided on a substrate (not shown).
  • the insulating layer 11 functions as an interlayer insulating layer.
  • the transistor 10 has a conductive layer 31 that functions as one of the source electrode and the drain electrode, a conductive layer 32 that functions as the other of the source electrode and the drain electrode, a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, and a conductive layer 23 that functions as a gate electrode.
  • the conductive layer 31 and the conductive layer 32 also function as wiring.
  • the conductive layer 31 and the insulating layer 44 are provided on the insulating layer 11.
  • the insulating layer 41 is provided on the conductive layer 31 and the insulating layer 44.
  • the conductive layer 32 and the insulating layer 45 are provided on the insulating layer 41.
  • the insulating layer 41 and the conductive layer 32 have an opening 20a that reaches the conductive layer 31.
  • the insulating layer 42 is provided on the conductive layer 32 and on the insulating layer 45.
  • the insulating layer 42 has an opening 20b that reaches the conductive layer 32 and has an area that overlaps with the opening 20a.
  • the diameter of the opening 20b can be larger than the diameter of the opening 20a.
  • the entire opening 20a can be configured to overlap with the opening 20b. Note that since the opening 20b has an area that overlaps with the opening 20a, the openings 20a and 20b can be considered as one opening 20.
  • the insulating layer 41 functions as a first spacer, and the insulating layer 42 functions as a second spacer.
  • the insulating layer 42 may function as the first spacer, and the insulating layer 41 may function as the second spacer.
  • the insulating layer 41 and the insulating layer 42 can function as interlayer insulating layers.
  • the semiconductor layer 21 is located inside the opening 20.
  • the semiconductor layer 21 is provided along the sidewall of the opening 20.
  • the semiconductor layer 21 has a region in contact with the conductive layer 31 inside the opening 20a.
  • the semiconductor layer 21 also has one or both of a region in contact with the side of the conductive layer 32 inside the opening 20a and a region in contact with the top surface of the conductive layer 32 inside the opening 20b.
  • the semiconductor layer 21 may have a region in contact with the side of the insulating layer 41 inside the opening 20a, and may have a region in contact with the side of the insulating layer 42 inside the opening 20b.
  • the opening 20b may reach not only the conductive layer 32 but also the insulating layer 45.
  • an insulating material for the insulating layer 45 that can increase the etching rate selectivity with respect to the insulating layer 42.
  • an insulating film having a different composition or density from the insulating layer 42 for the insulating layer 45 This makes it possible to prevent the insulating layer 45 from being unintentionally processed when the insulating layer 42 is processed.
  • an insulating layer that functions as an etching stopper when forming the opening 20b in the insulating layer 42 may be provided between the insulating layer 45 and the insulating layer 42.
  • insulating films having the same composition and density can be used for the insulating layer 45 and the insulating layer 42, and the range of materials to be selected for the insulating layer 45 and the insulating layer 42 can be expanded.
  • the insulating layer that functions as an etching stopper may be included in the insulating layer 45, for example.
  • the top of the insulating layer 45 can be the insulating layer that functions as the etching stopper.
  • the insulating layer 22 is located inside the opening 20 and is provided along the shape of the semiconductor layer 21.
  • the insulating layer 22 can have an area inside the opening 20 that contacts the semiconductor layer 21.
  • the conductive layer 23 is provided on the insulating layer 22 so as to fill the opening 20.
  • the insulating layer 22 is provided inside the opening 20, between the semiconductor layer 21 and the conductive layer 23.
  • the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 each have a flattened upper surface, and the heights of the upper surfaces can be made equal or approximately equal.
  • the upper surface of the insulating layer 42, the top surface of the semiconductor layer 21, the top surface of the insulating layer 22, and the upper surface of the conductive layer 23 can each be made equal or approximately equal in height.
  • An insulating layer 46 is provided on the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23, and an insulating layer 49 is provided on the insulating layer 46.
  • the insulating layer 46 and the insulating layer 49 function as interlayer insulating layers.
  • the insulating layer 46 has an opening 26 that reaches the conductive layer 23.
  • the insulating layer 49 has an opening 29 that reaches the insulating layer 46 and has an area that overlaps with the opening 26.
  • the opening 29 has an area that overlaps with the opening 26, the opening 26 and the opening 29 may be considered as one opening.
  • the opening 26 can be formed by processing the insulating layer 46, for example, by etching.
  • the opening 29 can be formed by processing the insulating layer 49, for example, by etching.
  • the insulating layer 49 can be made of an insulating material that can increase the etching rate selectivity with respect to the insulating layer 46. This can prevent the insulating layer 46 from being unintentionally processed during processing of the insulating layer 49, for example, exposing the top surface of the semiconductor layer 21 and causing contact with the conductive layer 33. This can realize a highly reliable semiconductor device.
  • the insulating layer 49 uses an insulating film having at least a different composition or density from the insulating layer 46. Note that the insulating layer 46 and the insulating layer 49 may contain the same constituent elements.
  • an insulating layer that functions as an etching stopper when forming the opening 29 in the insulating layer 49 may be provided between the insulating layer 46 and the insulating layer 49.
  • insulating films having the same composition and density can be used for the insulating layer 46 and the insulating layer 49, and the range of material choices for the insulating layer 46 and the insulating layer 49 can be expanded.
  • the insulating layer that functions as the etching stopper may be included in the insulating layer 46, for example. In this case, the topmost part of the insulating layer 46 can be the insulating layer that functions as the etching stopper.
  • the conductive layer 33 functions as wiring, specifically, as wiring (also referred to as gate wiring) for the gate electrode of the transistor 10.
  • the conductive layer 33 is provided so as to fill the opening 26 and the opening 29.
  • the conductive layer 33 can have a region in contact with the conductive layer 23 inside the opening 26.
  • the opening 26 can reach the semiconductor layer 21, and the conductive layer 33 can be prevented from contacting the semiconductor layer 21.
  • the diameter of the opening 20b is made larger than the diameter of the opening 20a, for example, the width of the conductive layer 32 (the length in the region not including the opening 20a in the Y direction in FIG.
  • the transistors included in the semiconductor device can be miniaturized, and the semiconductor device can be made highly reliable.
  • the conductive layer 33 has a region located on the insulating layer 46. In this region, the conductive layer 33 has a region overlapping with the insulating layer 42 via the insulating layer 46, a region overlapping with the semiconductor layer 21, a region overlapping with the insulating layer 22, and a region overlapping with the conductive layer 23. Specifically, the conductive layer 33 has a region overlapping with the top surface of the insulating layer 42 via the insulating layer 46, a region overlapping with the top surface of the semiconductor layer 21, a region overlapping with the top surface of the insulating layer 22, and a region overlapping with the top surface of the conductive layer 23.
  • the height of the top surface of the conductive layer 33 can be the same or approximately the same as the height of the top surface of the insulating layer 49.
  • the conductive layer 31 is embedded in the insulating layer 44, and the conductive layer 32 is embedded in the insulating layer 45. Furthermore, the upper surfaces of these are flattened, and the heights of the upper surfaces of the conductive layer and the insulating layer are roughly the same. This configuration is preferable because it can eliminate the effect of steps.
  • the insulating layer 44 and the insulating layer 45 function as interlayer insulating layers.
  • an inorganic insulating material with a low dielectric constant such as silicon oxide or silicon oxynitride. Note that materials that can be used for the insulating layer 41 will be described later.
  • an oxynitride refers to a material that contains more oxygen than nitrogen.
  • a nitride oxide refers to a material that contains more nitrogen than oxygen.
  • an insulating material containing oxygen can be used for insulating layer 46
  • an insulating material containing nitrogen can be used for insulating layer 49.
  • silicon oxide can be used for insulating layer 46
  • silicon nitride can be used for insulating layer 49.
  • an insulating material containing nitrogen can be used for insulating layer 46
  • an insulating layer material containing oxygen can be used for insulating layer 49.
  • the source electrode and the drain electrode are located at different heights, so the current flowing through the semiconductor flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction)
  • the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, or a vertical channel transistor. Since the source electrode, semiconductor, and drain electrode of the transistor 10 can be provided overlapping each other, the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor or LFET (Lateral FET) etc.) in which the semiconductor is arranged on a plane.
  • planar type transistor which can also be called a lateral transistor or LFET (Lateral FET) etc.
  • the channel length of the transistor 10 can be precisely controlled by the film thickness of the insulating layer 41, the variation in channel length between multiple transistors 10 can be made extremely small compared to planar transistors. Furthermore, by making the insulating layer 41 thin, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, a transistor with a channel length of less than 10 nm can be realized even with a conventional mass-production exposure tool, without using the extremely expensive exposure tool used in cutting-edge LSI technology.
  • Various semiconductor materials can be used for the semiconductor layer 21, but it is particularly preferable to use an oxide semiconductor containing a metal oxide.
  • an oxide semiconductor formed under appropriate conditions a transistor that combines a high on-current and an extremely low off-current can be realized at low cost.
  • the conductive layers 31 and 32 can each be configured so that the semiconductor layer 21 is in contact with the upper surface. Therefore, when an oxide semiconductor is used for the semiconductor layer 21, the exposed surfaces of the conductive layers 31 and 32 may be oxidized due to the influence of heat during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, forming an insulating oxide film between the conductive layers 31 and 32 and increasing the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost part of the conductive layers 31 and 32. This makes it possible to prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layers 31 and 32.
  • the conductive layer 31 can be used as one of the source wiring and the drain wiring.
  • the conductive layer 32 can be used as the other of the source wiring and the drain wiring.
  • the electrical resistance is low. Therefore, it is preferable to use a material having a higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof.
  • one or both of the conductive layer 31 and the conductive layer 32 have a stacked structure including a layer of the highly conductive material, and that the above-mentioned oxide conductor is used at least in the uppermost portion.
  • the transistor 10 is provided at the intersection of the conductive layer 33 functioning as a gate wiring and the conductive layer 32 functioning as a source wiring or drain wiring. Therefore, at the intersection of the conductive layer 33 and the conductive layer 32, a parasitic capacitance is generated in the region where they overlap.
  • the insulating layer 42 and the insulating layer 46 are provided between the conductive layer 33 and the conductive layer 32, so that the parasitic capacitance is significantly reduced compared to a case where the insulating layer 42 and the insulating layer 46 are not provided (for example, a region where the conductive layer 33 and the conductive layer 32 overlap only via the insulating layer 22). Therefore, a semiconductor device that operates at high speed can be realized.
  • the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be suitably reduced.
  • the total thickness of the insulating layer 42 and the insulating layer 46 can be made larger than the thickness of the insulating layer 22. It is also preferable that the total thickness of the insulating layer 42 and the insulating layer 46 is made larger than at least one of the thicknesses of the insulating layer 44, the insulating layer 45, and the insulating layer 49.
  • the thicker the insulating layer 42 and the insulating layer 46 the more the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be reduced, and therefore the thickness may be determined taking productivity into consideration.
  • the total thickness of the insulating layer 42 and the insulating layer 46 can be, for example, two or three times the thickness of the insulating layer 41.
  • Figures 3A and 3B are cross-sectional views showing an example in which an insulating layer 43 is provided between the conductive layer 32 and insulating layer 42 of the semiconductor device shown in Figures 2B and 2C, respectively.
  • Figure 2A For the planar configuration of the semiconductor device shown in Figures 3A and 3B, refer to Figure 2A.
  • the insulating layer 43 has an opening 20a. Also, the insulating layer 42 has an opening 20b that reaches the insulating layer 43 and has an area that overlaps with the opening 20a.
  • the semiconductor layer 21 has a region in contact with the side of the conductive layer 32 inside the opening 20a.
  • the semiconductor layer 21 may also have a region in contact with the side of the insulating layer 43 inside the opening 20a, and may also have a region in contact with the top surface of the insulating layer 43 inside the opening 20b.
  • an insulating layer 43 is provided between the conductive layer 32 and the conductive layer 23 in addition to the semiconductor layer 21 and the insulating layer 22. This allows the parasitic capacitance in the region where the upper surface of the conductive layer 32 overlaps with the conductive layer 23 to be reduced more than in the semiconductor device shown in Figures 2B and 2C.
  • the semiconductor layer 21 can have a region that contacts not only the side surface of the conductive layer 32 but also the upper surface. Therefore, the conductive layer 32 and the semiconductor layer 21 can make better contact than in the semiconductor device shown in Figures 3A and 3B.
  • the opening 20a in the insulating layer 43 can be formed by processing the insulating layer 43, for example, by an etching method.
  • the opening 20b in the insulating layer 42 can be formed by processing the insulating layer 42, for example, by an etching method.
  • the insulating layer 43 can be made of an insulating material that can increase the etching rate selectivity with respect to the insulating layer 42.
  • the insulating layer 43 uses an insulating film having at least a different composition or density from the insulating layer 42.
  • the insulating layer 42 and the insulating layer 43 may contain the same constituent elements.
  • the insulating layer 42 may use a material similar to the material that can be used for the insulating layer 49, and the insulating layer 43 may use a material similar to the material that can be used for the insulating layer 46.
  • the insulating layer 42 may use a material similar to the material that can be used for the insulating layer 46, and the insulating layer 43 may use a material similar to the material that can be used for the insulating layer 49.
  • an insulating layer that functions as an etching stopper when forming the opening 20b in the insulating layer 42 may be provided between the insulating layer 43 and the insulating layer 42.
  • insulating films having the same composition and density can be used for the insulating layer 43 and the insulating layer 42, which can broaden the range of material selection for the insulating layer 43 and the insulating layer 42.
  • the insulating layer that functions as the etching stopper may be included in the insulating layer 43, for example.
  • the topmost part of the insulating layer 43 can be the insulating layer that functions as the etching stopper.
  • Figures 2B, 2C, 3A, and 3B show a case where a laminated film of insulating layers 41a, 41b, and 41c is used as the insulating layer 41. Also, Figure 4A shows an enlarged view of Figure 2B.
  • the semiconductor layer 21 can be provided so as to have a region in contact with the side surface of the insulating layer 41b at the opening 20a. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between the insulating layer 41a and the insulating layer 41c, which have a barrier property against oxygen.
  • the region of the semiconductor layer 21 that contacts the insulating layer 41b is a region in which oxygen vacancies are reduced, and can be said to be an i-type region.
  • the region that does not contact the insulating layer 41b is an n-type region that contains many carriers.
  • the region of the semiconductor layer 21 that contacts the insulating layer 41b can be a channel formation region, and the region outside of that can be a low resistance region (also called a source region or drain region).
  • the channel formation region 21i and the low resistance region 21n of the semiconductor layer 21 are shown with different hatching patterns.
  • the channel length L of the transistor 10 can be said to be the length of the region in contact with the insulating layer 41b on the path that connects the region in contact with the conductive layer 31 of the semiconductor layer 21 and the region in contact with the conductive layer 32 over the shortest distance, as shown in FIG. 4A.
  • the angle ( ⁇ ) of the sidewall of the opening 20a of the insulating layer 41b is 90 degrees
  • the channel length L is equal to the film thickness of the insulating layer 41b.
  • the channel length L can be increased by increasing ⁇ .
  • the channel width W of the transistor 10 depends on the shape of the opening 20a.
  • FIG. 4B is a plan view of a cut surface cut along the cutting line C1-C2 in FIG. 4A at the height where the insulating layer 41b is provided, as viewed from the Z direction.
  • the opening 20a is shown to have a cylindrical shape.
  • the channel width W can be regarded as the circumference of the opening 20a (i.e., ⁇ R).
  • the angle ⁇ of the sidewall of the opening 20a of the insulating layer 41b deviates from 90 degrees, the circumference of the opening 20a differs depending on the height.
  • the circumference at the height where the diameter of the opening 20a is smallest may be regarded as the channel width W, or the circumference at the height of the upper end of the opening 20a may be regarded as the channel width W.
  • a circular shape is not limited to a perfect circle.
  • the thickness of this region may be thin depending on the film formation method.
  • film formation methods such as sputtering or plasma enhanced chemical vapor deposition (PECVD)
  • PECVD plasma enhanced chemical vapor deposition
  • films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface.
  • film formation methods such as atomic layer deposition (ALD) or thermal CVD (TCVD)
  • ALD atomic layer deposition
  • TCVD thermal CVD
  • the angle ⁇ of the side surface of the opening 20a of the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.
  • an insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate are available.
  • a semiconductor substrate for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride, a substrate having a metal oxide, or the like can be used.
  • a substrate in which a conductive layer or a semiconductor layer is provided on an insulating substrate a substrate in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and a substrate in which a semiconductor layer or an insulating layer is provided on a conductive substrate.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element (also called a light-emitting device), a memory element (also called a memory device), and the like.
  • the semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).
  • the metal oxide preferably contains at least In or Zn.
  • the metal oxide preferably contains two or three elements selected from In, element M, and Zn.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium.
  • Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.
  • the element M contained in the metal oxide is preferably one or more of the above elements, and is preferably one or more of Al, Ga, Y, and Sn, and more preferably gallium.
  • a metal oxide having indium, M, and zinc may be referred to as In-M-Zn oxide.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and "metalloid elements" described in this specification may include metalloid elements.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the composition close to these includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the semiconductor layer 21 may be, for example, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, or In-Ga-Al-Zn oxide.
  • Ga-Zn oxide may also be used.
  • the metal oxide may contain one or more metal elements with a large periodic number instead of or in addition to indium.
  • metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide.
  • the content of metal element X can be expressed as Ax /( Ax + Ay + Az ).
  • a transistor with a large on-state current can be realized by increasing the In content.
  • a transistor with high reliability when a positive bias is applied can be obtained.
  • a transistor with a small amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained.
  • the Ga content it is possible to obtain a transistor with high reliability against light.
  • NBTIS Near Bias Temperature Illumination Stress
  • a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and it is possible to reduce the amount of variation in threshold voltage in NBTIS testing of a transistor.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the semiconductor layer 21 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers of the semiconductor layer 21 may have the same or approximately the same composition.
  • the same sputtering target can be used to form the semiconductor layer 21, thereby reducing the manufacturing cost.
  • a stacked structure in which two or more oxide semiconductor layers having different compositions are stacked may be formed.
  • a metal oxide layer whose composition continuously varies in the film thickness direction can be formed. This not only widens the range of design options compared to the case where a film of a fixed composition is used, but also makes it possible to prevent the generation of interface states between two layers of different compositions, thereby improving electrical characteristics and reliability.
  • the semiconductor layer 21 has a two-layer structure
  • a material with higher mobility (high conductivity) than the first layer for the second layer, i.e., the side closer to the gate electrode.
  • This makes it possible to obtain a transistor that is normally off and has a large on-current.
  • a material with higher mobility than the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This makes it possible to reduce the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and making it possible to obtain a transistor with a large on-current.
  • the semiconductor layer 21 has a three-layer structure, it is preferable to use a material with higher mobility for the second layer than for the first and third layers. This makes it possible to realize a transistor with high on-current and high reliability.
  • the difference in the mobility and conductivity described above can be expressed, for example, by the content of indium.
  • an element other than indium that contributes to improving conductivity also affects the mobility and conductivity.
  • the semiconductor layer 21 is preferably a crystalline metal oxide layer.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nano-crystalline (nc: nano-crystal) structure can be used.
  • CAAC c-axis aligned crystal
  • nc nano-crystalline
  • Transistors using an oxide semiconductor have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • the leakage current between the source and drain in an off state (hereinafter also referred to as off-current) of an OS transistor is extremely small, and the charge accumulated in a capacitance connected in series with the transistor can be held for a long period of time.
  • the use of an OS transistor can reduce the power consumption of a semiconductor device.
  • the semiconductor device can be applied to, for example, a display device.
  • a display device In order to increase the light emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter, referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light emission luminance of the light-emitting device.
  • the OS transistor When the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be finely controlled. This allows for a larger number of gradations in the pixel circuit. Furthermore, a stable current can be passed even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or there is variation in the electrical characteristics.
  • the electrical characteristics e.g., resistance
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., are highly resistant to radiation, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, proton rays, and neutron rays).
  • the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.
  • the semiconductor layer 21 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tellurium
  • the crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a crystalline semiconductor is preferable because it can suppress deterioration of the transistor characteristics.
  • the insulating layer 22 functions as a gate insulating layer of the transistor.
  • an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21.
  • silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used.
  • a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can be used as the insulating layer 22.
  • the insulating layer 22 may have a stacked structure, and may have, for example, a stacked structure having one or more oxide insulating films and one or more nitride insulating films.
  • Conductive Layer It is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. as the conductive layer 31 and the conductive layer 32. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized.
  • conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide can be used as the conductive layers 31 and 32.
  • Conductive oxides containing indium are particularly preferred because of their high conductivity.
  • the conductive layer 23 functions as a gate electrode, and various conductive materials can be used.
  • a metal element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an alloy containing the metal element.
  • a nitride of the above metal or alloy, or an oxide of the above metal or alloy may be used.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductive layer 23 may also be made of nitrides and oxides that can be used for the conductive layers 31 and 32.
  • the conductive layers 31 and 32 also function as wiring, low-resistance conductive materials can be stacked and used. The lower the resistance of the conductive layer 33, the more preferable it is.
  • the conductive layers 31, 32, and 33 can be made of the same conductive material as the conductive layer 23.
  • Insulating layer 41 (or the insulating layer 41b) has a region in contact with the semiconductor layer 21.
  • an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide for at least the region of the insulating layer 41 in contact with the semiconductor layer 21 in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 41.
  • silicon oxide or silicon oxynitride can be suitably used.
  • a film that releases oxygen when heated for the insulating layer 41 it is more preferable to use a film that releases oxygen when heated for the insulating layer 41.
  • oxygen is supplied to the semiconductor layer 21 by the heat applied during the manufacturing process of the transistor 10, and oxygen vacancies in the semiconductor layer 21 can be reduced, thereby improving reliability.
  • Methods for supplying oxygen to the insulating layer 41 include heat treatment in an oxygen atmosphere and plasma treatment in an oxygen atmosphere.
  • Oxygen may also be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulating layer 41 by a sputtering method. The oxide film may then be removed.
  • the insulating layer 41 is preferably formed by a deposition method such as a sputtering method or a plasma CVD method.
  • a deposition method such as a sputtering method or a plasma CVD method.
  • a sputtering method that does not use hydrogen gas as a deposition gas a film with an extremely low hydrogen content can be obtained. This makes it possible to suppress the supply of hydrogen to the semiconductor layer 21 and stabilize the electrical characteristics of the transistor 10.
  • the insulating layers 41a and 41c are preferably made of a film through which oxygen does not easily diffuse. This makes it possible to prevent oxygen contained in the insulating layer 41b from permeating to the insulating layer 11 side through the insulating layer 41a due to heating, and from permeating to the insulating layer 22 side through the insulating layer 41c. In other words, by sandwiching the insulating layer 41b from above and below with the insulating layers 41a and 41c, through which oxygen does not easily diffuse, the oxygen contained in the insulating layer 41b can be trapped. This makes it possible to effectively supply oxygen to the semiconductor layer 21.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used as the insulating layer 41a and the insulating layer 41c.
  • silicon nitride and silicon nitride oxide have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used as the insulating layer 41a and the insulating layer 41c.
  • ⁇ Variation 1> 5A, 5B, and 5C show an example in which the sidewall of the opening 20a and the sidewall of the opening 20b are provided on the same plane (also called flush).
  • the opening 20a and the opening 20b can be formed in the same process, so that the manufacturing process can be simplified compared to the semiconductor device shown in FIGS. 2A to 2C.
  • the semiconductor device shown in FIGS. 2A to 2C for example, the area occupied by the transistor 10 can be reduced. Therefore, the transistor included in the semiconductor device can be miniaturized more than the transistor included in the semiconductor device shown in FIGS. 5A to 5C, and the semiconductor device can be made highly reliable.
  • the semiconductor layer 21 can have a region in contact with not only the side surface but also the top surface of the conductive layer 32. This allows the conductive layer 32 and the semiconductor layer 21 to have good contact, and a highly reliable semiconductor device can be realized.
  • FIGS. 6A, 6B, and 6C show an example in which the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have regions located outside the opening 20.
  • the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have regions located on the insulating layer 42.
  • FIGS. 6B and 6C show an example in which the insulating layer 22 is provided so as to cover the side surface of the semiconductor layer 21 outside the opening 20.
  • FIGS. 6A to 6C show an example in which the side surface of the conductive layer 23 outside the opening 20 is located outside (opposite the opening 20) of the side surface of the semiconductor layer 21 outside the opening 20.
  • the side surface of the conductive layer 23 outside the opening 20 may be located inside (the opening 20 side) of the side surface of the semiconductor layer 21 outside the opening 20.
  • FIGS. 6A to 6C show an example in which the insulating layer 22 is not patterned, but the insulating layer 22 may be patterned.
  • the insulating layer 22 and the conductive layer 23 may be formed in the same pattern.
  • the side surface of the insulating layer 22 outside the opening 20 and the side surface of the conductive layer 23 outside the opening 20 can be flush with each other.
  • the conductive layer 23 functioning as a gate electrode can be routed without providing the insulating layer 46, the insulating layer 49, and the conductive layer 33.
  • a planarized insulating layer also referred to as a planarizing layer
  • ⁇ Modification 3> 7A to 7C show an example in which the sidewall of the opening 20 a has a tapered shape.
  • the diameter (opening diameter) of the opening 20 a at the upper end is larger than the diameter (opening diameter) at the lower end.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a fine curvature, or approximately planar with fine irregularities.
  • the angle ⁇ can be 45 degrees or more and 90 degrees or less, or 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. Note that when a film formation method with extremely high coverage such as an ALD method is used, the angle ⁇ may be greater than 90 degrees.
  • the diameter of the opening 20a which corresponds to the channel width of the transistor 10
  • the diameter of the opening 20a increases from the conductive layer 31 side toward the insulating layer 42 side.
  • the magnitude of the current flowing through the transistor 10 is limited to the area with the smallest diameter. Therefore, the channel width of the transistor 10 can be regarded as the perimeter of the area with the smallest diameter. Therefore, by making the sidewall of the opening 20a tapered, it is possible to fabricate a transistor 10 with a channel width smaller than the diameter of the upper end of the opening 20a.
  • the diameter (opening diameter) of the upper end of not only the opening 20a but also the opening 20b is larger than the diameter (opening diameter) of the lower end.
  • the diameter of the upper end of opening 20b is larger than the diameter of the lower end, since this increases the contact area between conductive layer 23 and conductive layer 33.
  • the conductive layer 27 functions as a second gate electrode (or a back gate electrode).
  • the insulating layer 28 is located between the conductive layer 27 and the semiconductor layer 21 and functions as a second gate insulating layer (or a back gate insulating layer).
  • a fixed potential or any signal can be applied to the conductive layer 27.
  • the conductive layer 27 may be electrically connected to any one of the conductive layers 31, 32, and 33.
  • the conductive layer 27 is embedded in the insulating layer 41b. Therefore, the conductive layer 27 is provided between the insulating layer 41a and the insulating layer 41c.
  • the insulating layer 28 is provided along the side surfaces of the insulating layer 41a, the conductive layer 27, the insulating layer 41c, and the conductive layer 32.
  • the insulating layer 28 can be formed by forming an opening in the conductive layer 32, the insulating layer 41c, the conductive layer 27, and the insulating layer 41a, depositing an insulating film that covers the opening by a film deposition method with high coverage, and then performing anisotropic etching.
  • the semiconductor layer 21 has an area in contact with the upper surface of the conductive layer 32, so that the semiconductor layer 21 and the conductive layer 32 can be electrically connected.
  • 9A to 9C show an example in which conductive layer 31 and conductive layer 32 extend in the X direction, and conductive layer 27 and conductive layer 33 extend in the Y direction.
  • conductive layer 31 and conductive layer 27 By extending conductive layer 31 and conductive layer 27 in different directions, the parasitic capacitance between conductive layer 31 and conductive layer 27 can be reduced more than when conductive layer 31 and conductive layer 27 extend in the same direction.
  • conductive layer 27 and conductive layer 32 in different directions, the parasitic capacitance between conductive layer 27 and conductive layer 32 can be reduced more than when conductive layer 27 and conductive layer 32 extend in the same direction.
  • conductive layer 31 and conductive layer 27 may extend in the same direction, or conductive layer 27 and conductive layer 32 may extend in the same direction.
  • the parasitic capacitance between conductive layer 31 and conductive layer 27 can be reduced, and by increasing the thickness of insulating layer 41c, the parasitic capacitance between conductive layer 27 and conductive layer 32 can be reduced.
  • FIG. 10A and 10B show examples in which recesses are provided in the conductive layer 31 shown in Fig. 2B and Fig. 2C, respectively.
  • Fig. 2A can be referred to for a plan view.
  • Fig. 10C is an enlarged view of the conductive layer 31 and its surrounding area shown in Fig. 10A and Fig. 10B.
  • the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are provided along the recess of the conductive layer 31.
  • the height of the bottom surface of the conductive layer 23 is lower than the height of the top surface of the conductive layer 31.
  • the region of the semiconductor layer 21 in contact with the conductive layer 31 is a region with lower resistance than the channel formation region. Therefore, as shown in Figure 10C, by positioning the bottom surface of the conductive layer 23 lower than the top surface of the conductive layer 31, it is possible to apply a gate electric field uniformly to the entire channel formation region of the semiconductor layer 21, and it is possible to prevent the formation of a high-resistance region (offset region) due to the difficulty of the gate electric field reaching the semiconductor layer 21. As a result, a transistor with an increased on-current can be realized.
  • the film thickness of the conductive layer 31 is made thicker than the sum of the film thickness of the semiconductor layer 21 and the film thickness of the insulating layer 22.
  • Fig. 11A shows an example in which the shape of the opening 20a and the opening 20b shown in Fig. 2A in a plan view is an ellipse. Note that, although Fig. 11A shows an example in which the major axis of the ellipse is parallel to the X direction, it may be parallel to the Y direction, or may not be parallel to either the X direction or the Y direction.
  • Figure 11B shows an example in which the shape of the opening 20a and the opening 20b shown in Figure 2A in a plan view is a rectangle.
  • the shape of the opening 20a and the opening 20b in a plan view is a square, but the shape of the opening 20a and the opening 20b in a plan view is not limited to this and may be, for example, a rectangle, a rhombus, or a parallelogram.
  • the shape of the opening 20a and the opening 20b in a plan view may be, for example, a triangle, or a polygon with pentagons or more sides, or may be a star shape.
  • Figure 11C shows an example in which the corners of the openings 20a and 20b shown in Figure 11B are rounded. That is, Figure 11C shows an example in which the shape of the openings 20a and 20b in plan view is a rectangle with rounded corners. Note that in Figure 11C, the shape of the openings 20a and 20b in plan view is a square with rounded corners, but the shape of the openings 20a and 20b in plan view is not limited to this, and may be, for example, a rectangle with rounded corners, a rhombus with rounded corners, a parallelogram with rounded corners, a triangle with rounded corners, a polygon with 5 or more sides with rounded corners, or a star with rounded corners.
  • opening 20a and 11A to 11C show an example in which the shape of opening 20b in plan view is the same as the shape of opening 20a in plan view, but the type of shape of opening 20a in plan view and the type of shape of opening 20b in plan view may be different.
  • opening 20a may have a circular or elliptical shape in plan view
  • opening 20b may have a rectangular or rounded-corner rectangular shape in plan view.
  • opening 20a may have a rectangular shape in plan view
  • opening 20b may have a rectangular shape in plan view with rounded corners, a circular shape, or an elliptical shape in plan view.
  • ⁇ Modification 7> 12A, 12B, and 12C show an example in which the shape of the opening 20a in the insulating layer 41 does not match the shape of the opening 20a in the conductive layer 32 in a plan view.
  • the opening 20a in the insulating layer 41 is defined as the opening 20a1
  • the opening 20a in the conductive layer 32 is defined as the opening 20a2.
  • the shape of the opening 20a2 in a plan view is a circle with a larger radius than the opening 20a1. Note that one or both of the shape of the opening 20a1 in a plan view and the shape of the opening 20a2 in a plan view do not have to be a circle.
  • one or both of the shape of the opening 20a1 in a plan view and the shape of the opening 20a2 in a plan view can be an ellipse, a rectangle, a rectangle with rounded corners, or the like, which is a shape that the above-mentioned opening 20a can have.
  • the conductive layer 32 has an area that protrudes beyond the side wall of the opening 20a1.
  • the shape of the opening 20a1 in a plan view may differ from the shape of the opening 20a2 in a plan view.
  • the opening 20a1 and the opening 20a2 are formed in the same process, for example, when the etching rate of the conductive layer 32 in the X direction and the Y direction is different from the etching rate of the insulating layer 41 in the X direction and the Y direction, the shape of the opening 20a1 in a plan view may differ from the shape of the opening 20a2 in a plan view.
  • the area of the opening 20a2 in a plan view may be larger than the area of the opening 20a1 in a plan view, even when the opening 20a1 and the opening 20a2 are formed in the same process.
  • Figures 13A to 16B are cross-sectional views of each step in the manufacturing method of a semiconductor device, which will be described below.
  • the cross section corresponding to Figure 2B is shown on the left side
  • the cross section corresponding to Figure 2C is shown on the right side.
  • the insulating material for forming the insulating layer, the conductive material for forming the conductive layer, and the semiconductor material for forming the semiconductor layer can be formed as films using a sputtering method, a CVD method, an MBE (Molecular Beam Epitaxy) method, a PLD (Pulsed Laser Deposition) method, an ALD method, or the like, as appropriate.
  • Sputtering methods include RF (Radio Frequency) sputtering, which uses a high-frequency power source as the sputtering power source, DC (Direct Current) sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD, which uses plasma, thermal CVD, which uses heat, and photo CVD, which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures.
  • the thermal CVD method does not use plasma, it is possible to reduce plasma damage to the workpiece.
  • the thermal CVD method does not cause plasma damage during film formation, it produces films with fewer defects.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • ALD has excellent step coverage and excellent film thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods with a faster film formation speed, such as CVD.
  • the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases.
  • the CVD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Also, like the CVD method, a film with a continuously changing composition can be formed.
  • a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate (FIG. 13A).
  • An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11.
  • the insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, it is preferable to perform a planarization process so that the upper surface of the insulating layer 11 becomes flat after the insulating layer 11 is formed.
  • a conductive film that will become the conductive layer 31 is formed on the insulating layer 11.
  • a resist mask is formed on the conductive film, for example, by photolithography, and the area of the conductive film that is not covered by the resist mask is removed by etching, and then the resist mask is removed. This allows the conductive layer 31 to be formed.
  • an insulating film that will become the insulating layer 44 is formed, and the area that overlaps with the conductive layer 31 is removed, thereby forming the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 (FIG. 13A).
  • the insulating film that will become the insulating layer 44 is preferably processed by CMP, and for example, the insulating film is processed until the top surface of the conductive layer 31 is exposed, thereby forming the insulating layer 44 shown in FIG. 13A.
  • the insulating layer 44 and the conductive layer 31 may be formed by first forming an insulating film that will become the insulating layer 44, then forming an opening in the insulating film, forming a conductive film so as to fill the opening, and performing a polishing process (planarization process) using the CMP method until the top surface of the insulating film is exposed.
  • the upper surface of the subsequently formed insulating layer 41 can be made flat.
  • the insulating layer 41 may be provided to cover the conductive layer 31 without providing the insulating layer 44. In that case, it is preferable to perform a planarization process by CMP on the upper surface of the insulating layer 41 to flatten the upper surface.
  • insulating layers 41a, 41b, and 41c are formed on the conductive layer 31 and the insulating layer 44 (FIG. 13B).
  • the insulating layers 41a, 41b, and 41c may be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating layer 41 affects the channel length of the transistor, it is important to prevent variation in the thickness of the insulating layer 41.
  • the insulating layer 41b by sputtering in an oxygen-containing atmosphere, the insulating layer 41b containing a large amount of oxygen can be formed.
  • the hydrogen concentration in the insulating layer 41b can be reduced.
  • Conductive layer 32 and insulating layer 45 are formed on insulating layer 41 (FIG. 13C). Conductive layer 32 and insulating layer 45 can be formed in the same manner as conductive layer 31 and insulating layer 44, respectively.
  • the insulating layer 42 is formed on the conductive layer 32 and the insulating layer 45 (FIG. 13D).
  • the insulating layer 42 can be formed, for example, in a manner similar to that of the insulating layer 41b.
  • a portion of the insulating layer 42 is processed to form an opening 20b that reaches the conductive layer 32.
  • a portion of the conductive layer 32 and a portion of the insulating layer 41 are processed to form an opening 20a that has an area that overlaps with the opening 20b and reaches the conductive layer 31 (FIG. 14A).
  • the openings 20a and 20b can be considered as one opening 20.
  • a resist mask is first formed on the insulating layer 42 by photolithography, and the area of the insulating layer 42 that is not covered by the resist mask is removed by etching, and then the resist mask is removed. As a result, an opening 20b is formed in the insulating layer 42.
  • a resist mask is formed on the insulating layer 42 and the conductive layer 32 by photolithography, and the area of the conductive layer 32 and the insulating layer 41 that is not covered by the resist mask is removed by etching, and then the resist mask is removed. As a result, an opening 20a is formed in the conductive layer 32 and the insulating layer 41.
  • an opening 20 is formed in the insulating layer 41, the conductive layer 32, and the insulating layer 42.
  • the opening 20a may be formed in the same process as the opening 20b. Specifically, the opening 20a may be formed under the same etching conditions as the opening 20b. Even in this case, the diameter of the opening 20b can be made larger than the diameter of the opening 20a, for example, by the resist mask receding when the opening 20a is formed. Since the insulating layer 41 can be processed using the conductive layer 32 as a hard mask and the insulating layer 42 can be processed based on the resist pattern, the diameter of the opening 20b can be made larger than the diameter of the opening 20a, even when the opening 20a is formed in the same process as the opening 20b, by the resist mask receding when the opening 20a is formed.
  • openings 20b may be formed in insulating layer 42 so as to reach insulating layer 45 as well as conductive layer 32.
  • etching insulating layer 42 under conditions in which the etching rate of insulating layer 42 is faster than the etching rate of insulating layer 45 is preferable because etching of insulating layer 45 can be suppressed.
  • the sidewalls of the opening 20 are preferably perpendicular to the top surface of the conductive layer 31. With this configuration, a transistor with a small occupancy area can be fabricated.
  • the sidewalls of the opening 20 may be tapered. By making the sidewalls tapered, the coverage of the film formed inside the opening 20 can be improved.
  • the maximum width of the opening 20a (maximum diameter when the opening 20a is circular in plan view) is preferably as fine as possible.
  • the maximum width of the opening 20a is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 5 nm or more.
  • the maximum width of the opening 20b can be made larger than the maximum width of the opening 20a, but it is preferable to form the opening 20b using a lithography method using short-wavelength light such as EUV light or an electron beam, like the opening 20a.
  • the opening 20 has a large aspect ratio, it is preferable to form it using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the etching conditions in this processing may be different for each of the insulating layer 42, the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a.
  • the angle of the sidewall of the opening 20b may be different from the angle of the sidewall of the opening 20a.
  • the angle of the sidewall of the opening 20a may be different for each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a.
  • a part of the upper part of the conductive layer 32 may be etched, and the conductive layer 32 at the bottom of the opening 20b may become thin.
  • a part of the upper part of the conductive layer 31 may be etched, and the conductive layer 31 at the bottom of the opening 20a may become thin.
  • a part of the upper part of the conductive layer 32 may be etched to thin the conductive layer 32.
  • a part of the upper part of the conductive layer 31 may be etched to thin the conductive layer 31.
  • the heat treatment may be performed at 250° C. to 650° C., preferably 300° C. to 500° C., more preferably 320° C. to 450° C.
  • the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere.
  • impurities such as water contained in the insulating layer 41 can be reduced before the formation of the oxide semiconductor film to be the semiconductor layer.
  • the gas used in the heat treatment is highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • a semiconductor film 21f is formed to cover the conductive layer 31, the insulating layer 41, the conductive layer 32, and the insulating layer 42 so as to have a region located inside the opening 20 (FIG. 14B).
  • the semiconductor film 21f is a semiconductor film that will later become the semiconductor layer 21.
  • An oxide semiconductor film can be used as the semiconductor film 21f.
  • the semiconductor film 21f can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the semiconductor film 21f is preferably formed in contact with the bottom and sidewall of the opening 20 having a large aspect ratio.
  • the semiconductor film 21f is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like.
  • the semiconductor film 21f may be formed by forming an In-Ga-Zn oxide film using the ALD method. Note that when the opening 20 has a tapered shape, the semiconductor film 21f can be formed by a sputtering method.
  • the microwave process refers to a process using an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • oxygen gas By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency such as RF, and the oxygen plasma can be applied to the semiconductor film 21f, which can use an oxide semiconductor.
  • the oxygen that acts on the semiconductor film 21f can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, atoms, molecules, or ions with unpaired electrons). Note that the oxygen that acts on the semiconductor film 21f may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.
  • the substrate may be heated to a temperature of 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.
  • the carbon concentration in the semiconductor film 21f obtained by SIMS can be set to less than 1 ⁇ 10 atoms/cm 3 , preferably less than 1 ⁇ 10 atoms/cm 3 , and more preferably less than 1 ⁇ 10 atoms/cm 3 .
  • the microwave treatment is performed on the semiconductor film 21f in an atmosphere containing oxygen, but the present invention is not limited to this.
  • the microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the semiconductor film 21f in an atmosphere containing oxygen. This allows hydrogen contained in the silicon oxide film to be released to the outside as H2O . By releasing hydrogen from the silicon oxide film located near the semiconductor film 21f, a highly reliable semiconductor device can be realized.
  • the deposition method of each layer may be the same or different.
  • the lower layer of the semiconductor film 21f may be deposited by a sputtering method
  • the upper layer of the semiconductor film 21f may be deposited by an ALD method.
  • An oxide semiconductor film deposited by a sputtering method is likely to have crystallinity. Therefore, by providing an oxide semiconductor film having crystallinity as the lower layer of the semiconductor film 21f, the crystallinity of the upper layer of the semiconductor film 21f can be improved.
  • the area overlapping with them can be blocked by the upper layer of the semiconductor film 21f deposited by an ALD method, which has good coverage.
  • the semiconductor film 21f is formed so as to have an area in contact with the upper surface of the conductive layer 31 in the opening 20a, the side surface of the insulating layer 41 in the opening 20a, the side surface of the conductive layer 32 in the opening 20a, the upper surface of the conductive layer 32 in the opening 20b, and the side surface of the insulating layer 42 in the opening 20b.
  • the heat treatment may be performed in a temperature range in which the semiconductor film 21f does not become polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed after the heat treatment in a nitrogen gas or inert gas atmosphere.
  • the gas used in the heat treatment is highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the heat treatment is performed after the semiconductor film 21f is formed, but the heat treatment may be performed in a later process.
  • an insulating film 22f is formed on the semiconductor film 21f so as to have a region located inside the opening 20 (FIG. 14B).
  • the insulating film 22f is an insulating film that will later become the insulating layer 22.
  • the insulating film 22f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • the insulating film 22f is provided on the side surface of the semiconductor film 21f in the opening 20a with a thickness as uniform as possible. Therefore, it is particularly preferable to form the insulating film 22f by the ALD method, which is a film formation method with extremely excellent coverage. If the side walls of the openings 20a and 20b are tapered, a film formation method with lower coverage than the ALD method, such as a sputtering method, can be used for the insulating layer 22.
  • a conductive film 23f is formed on the insulating film 22f so as to have a region located inside the opening 20 (FIG. 14B).
  • the conductive film 23f is a conductive film that will later become the conductive layer 23.
  • the conductive film 23f is provided so that a portion of it is embedded in the opening 20.
  • the conductive film 23f is preferably formed by a film forming method with high coverage or embedding properties, and more preferably, for example, a CVD method or an ALD method. If the sidewall of the opening 20 has a tapered shape, the conductive film can be formed by, for example, a sputtering method.
  • the semiconductor film 21f, the insulating film 22f, and the conductive film 23f are planarized by, for example, a CMP method to expose the upper surface of the insulating layer 42.
  • the semiconductor layer 21 having a region in contact with the conductive layer 31 and a region in contact with the conductive layer 32, the insulating layer 22 on the semiconductor layer 21, and the conductive layer 23 on the insulating layer 22 are formed (FIG. 15A).
  • the conductive layer 23 can be formed so as to fill the opening 20.
  • the conductive layer 23, the insulating layer 22, and the semiconductor layer 21 may be formed by processing the upper part of the conductive film 23f, the upper part of the insulating film 22f, and the upper part of the semiconductor film 21f by an etching method such as a dry etching method until the upper surface of the insulating layer 42 is exposed.
  • an etching method such as a dry etching method until the upper surface of the insulating layer 42 is exposed.
  • the upper surface of the insulating layer 42, the uppermost surface of the semiconductor layer 21, the uppermost surface of the insulating layer 22, and the upper surface of the conductive layer 23 can be made to be the same or approximately the same height.
  • an insulating layer 46 is formed on the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23.
  • an insulating layer 49 is formed on the insulating layer 46 (FIG. 15B).
  • the insulating layer 46 and the insulating layer 49 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • a portion of the insulating layer 49 is processed to form an opening 29 that reaches the insulating layer 46.
  • a portion of the insulating layer 46 is processed to form an opening 26 that has an area that overlaps with the opening 29 and reaches the conductive layer 23 (FIG. 16A).
  • a resist mask is formed on the insulating layer 49 by photolithography, the areas of the insulating layer 49 that are not covered by the resist mask are removed by etching, and then the resist mask is removed. As a result, an opening 29 is formed in the insulating layer 49.
  • a resist mask is formed on the insulating layer 49 and the insulating layer 46 by photolithography, the areas of the insulating layer 49 and the insulating layer 46 that are not covered by the resist mask are removed by etching, and then the resist mask is removed. As a result, an opening 26 is formed in the insulating layer 46.
  • the insulating layer 49 when the opening 29 is formed, if the insulating layer 49 is etched under conditions where the etching rate of the insulating layer 49 is faster than the etching rate of the insulating layer 46, the insulating layer 46 can be prevented from being unintentionally etched. This can prevent, for example, the upper surface of the semiconductor layer 21 from being exposed.
  • An insulating layer that functions as an etching stopper when forming the opening 29 in the insulating layer 49 may be formed between the insulating layer 46 and the insulating layer 49.
  • the opening 29 when the opening 29 is formed, it is not necessary to etch the insulating layer 49 under conditions where the etching rate of the insulating layer 49 is faster than the etching rate of the insulating layer 46, so that the range of etching conditions can be expanded.
  • the insulating layer that functions as an etching stopper may be included in the insulating layer 46, for example.
  • the top of the insulating layer 46 can be the insulating layer that functions as an etching stopper.
  • the diameter of the opening 20b is larger than the diameter of the opening 20a, the area of the upper surface of the conductive layer 23 can be increased while suppressing an increase in the area occupied by the transistor 10. This prevents, for example, the opening 26 from reaching the semiconductor layer 21 and the conductive layer 33 formed in a later process from coming into contact with the semiconductor layer 21. As a result, a method for manufacturing a semiconductor device having miniaturized transistors and a high yield can be realized.
  • a conductive film that becomes conductive layer 33 is formed by covering conductive layer 23, insulating layer 46, and insulating layer 49 so as to have a region located inside opening 26 and a region located inside opening 29.
  • the conductive film can be formed so as to have a region inside opening 26 that contacts the upper surface of conductive layer 23.
  • the conductive film is then planarized by, for example, a CMP method to expose the upper surface of the insulating layer 49.
  • the conductive layer 33 is formed to have a region that contacts the conductive layer 23 inside the opening 26.
  • the conductive layer 33 also has a region located on the insulating layer 46, and is formed to have a region that overlaps with the insulating layer 42 through the insulating layer 46, a region that overlaps with the semiconductor layer 21, a region that overlaps with the insulating layer 22, and a region that overlaps with the conductive layer 23.
  • the conductive layer 33 is formed to have a region that overlaps with the upper surface of the insulating layer 42 through the insulating layer 46, a region that overlaps with the top surface of the semiconductor layer 21, a region that overlaps with the top surface of the insulating layer 22, and a region that overlaps with the upper surface of the conductive layer 23.
  • the conductive layer 33 may be formed by processing the upper portion of the conductive film that will become the conductive layer 33 by, for example, an etching method such as a dry etching method until the upper surface of the insulating layer 49 is exposed.
  • the height of the upper surface of the conductive layer 33 can be made to coincide or approximately coincide with the height of the upper surface of the insulating layer 49.
  • the transistor 10 shown in Figures 2B and 2C can be manufactured.
  • the conductive layer 32 and the insulating layer 45 are formed.
  • the insulating layer 43 is formed on the conductive layer 32 and the insulating layer 45 (FIG. 17A).
  • the insulating layer 43 can be formed, for example, by the same method as the insulating layer 46.
  • insulating layer 42 is formed on insulating layer 43 (FIG. 17B).
  • insulating layer 42 see the above-mentioned Example Manufacturing Method 1.
  • a portion of the insulating layer 42 is processed to form an opening 20b that reaches the insulating layer 43.
  • a portion of the insulating layer 43, a portion of the conductive layer 32, and a portion of the insulating layer 41 are processed to form an opening 20a that has an area that overlaps with the opening 20b and reaches the conductive layer 31 (FIG. 18A).
  • the insulating layer 43 can be prevented from being unintentionally etched. This can prevent, for example, the insulating layer 43 from becoming thinner, and the distance between the upper surface of the conductive layer 32 and the conductive layer 23 to be formed later from becoming shorter. Therefore, it is possible to prevent the parasitic capacitance in the region where the upper surface of the conductive layer 32 and the conductive layer 23 overlap from becoming large.
  • an insulating layer that functions as an etching stopper when forming the opening 20b in the insulating layer 42 may be formed between the insulating layer 43 and the insulating layer 42.
  • the insulating layer that functions as an etching stopper may be included in, for example, the insulating layer 43.
  • the top of the insulating layer 43 can be the insulating layer that functions as an etching stopper.
  • a semiconductor film 21f is formed covering the conductive layer 31, the insulating layer 41, the conductive layer 32, the insulating layer 43, and the insulating layer 42 so as to have a region located inside the opening 20 (FIG. 18B).
  • the semiconductor film 21f refer to the above-mentioned manufacturing method example 1.
  • the semiconductor film 21f is formed so as to have a region in contact with the upper surface of the conductive layer 31 in the opening 20a, the side of the insulating layer 41 in the opening 20a, the side of the conductive layer 32 in the opening 20a, the side of the insulating layer 43 in the opening 20a, the upper surface of the insulating layer 43 in the opening 20b, and the side of the insulating layer 42 in the opening 20b.
  • an insulating film 22f is formed on the semiconductor film 21f so as to have a region located inside the opening 20.
  • a conductive film 23f is formed on the insulating film 22f so as to have a region located inside the opening 20 (FIG. 18B).
  • Example 1 For the subsequent steps, refer to the above-mentioned Example 1 of the manufacturing method.
  • the transistor 10 shown in Figures 3A and 3B can be manufactured.
  • the semiconductor film 21f is formed in the same manner as in the above-mentioned manufacturing method example 1.
  • a resist mask is formed on the semiconductor film 21f, for example, by photolithography, and the portion of the semiconductor film 21f that is not covered by the resist mask is removed by etching, and then the resist mask is removed. This allows the semiconductor layer 21 to be formed (FIG. 19A).
  • insulating layer 22 is formed to cover semiconductor layer 21 and insulating layer 42 (FIG. 19B).
  • insulating layer 22 the description of the formation of insulating film 22f in manufacturing method example 1 above can be referred to.
  • a conductive film that will become conductive layer 23 is formed on insulating layer 22.
  • the explanation of the formation of conductive film 23f in Manufacturing Method Example 1 above can be referred to.
  • a resist mask is formed on the conductive film that will become the conductive layer 23, for example, by photolithography, and the portion of the conductive film 23f that is not covered by the resist mask is removed by etching, and then the resist mask is removed. This allows the conductive layer 23 to be formed (FIG. 19B).
  • the transistor 10 shown in Figures 6A to 6C can be manufactured.
  • Figure 20 shows an example of a circuit configuration of a memory cell 30 included in a memory device of one embodiment of the present invention.
  • the memory cell 30 includes one transistor Tr and one capacitor C, and can also be referred to as 1Tr1C.
  • the gate of the transistor Tr is electrically connected to a wiring WL
  • one of the source and drain is electrically connected to a wiring BL
  • the other of the source and drain is electrically connected to one electrode of the capacitor C.
  • the other electrode of the capacitor C is connected to a wiring PL.
  • the memory cell 30 can store data by holding in the capacitance C the data potential input from the wiring BL via the transistor Tr. Data can also be held by turning the transistor Tr off. By turning the transistor Tr on, a potential corresponding to the held data is output to the wiring BL, and the data can be read out. A signal that controls the conduction and non-conduction of the transistor Tr is applied to the wiring WL. A predetermined potential (e.g., a fixed potential) is applied to the wiring PL.
  • a predetermined potential e.g., a fixed potential
  • FIG. 21A1 shows a planar configuration example of a memory device according to one embodiment of the present invention
  • FIG. 21B and FIG. 21C show cross-sectional configuration examples taken along the cutting lines A1-A2 and B1-B2 in FIG. 21A1, respectively.
  • FIG. 21A1, FIG. 21B, and FIG. 21C show a configuration example of the memory cell 30 shown in FIG. 20.
  • the memory cell 30 has a configuration in which a transistor 10 is stacked on a capacitor 50.
  • the transistor 10 corresponds to the transistor Tr
  • the capacitor 50 corresponds to the capacitor C.
  • Figure 21A2 is a plan view showing the capacitor 50 excerpted from Figure 21A1.
  • Capacitor 50 has conductive layer 51, conductive layer 52, and insulating layer 53 sandwiched between them. Capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.
  • a conductive layer 34 is provided on the insulating layer 11, and an insulating layer 47 is provided on the conductive layer 34.
  • An opening 54a is provided in the insulating layer 47, reaching the conductive layer 34.
  • a conductive layer 51 is provided inside the opening 54a, so as to have an area in contact with the side of the insulating layer 47 and the upper surface of the conductive layer 34.
  • An insulating layer 53 is provided to cover the insulating layer 47 and the conductive layer 51.
  • An insulating layer 48 is provided on the insulating layer 53, and an opening 54b is provided in the insulating layer 48, which has an area overlapping with the opening 54a and reaches the insulating layer 53.
  • the conductive layer 52 is provided so as to be embedded in the opening 54b.
  • the conductive layer 52 and the insulating layer 48 have flattened upper surfaces and are aligned or approximately aligned at the same height.
  • An insulating layer 44 and a conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48.
  • the conductive layer 31 is provided so as to have an area in contact with the upper surface of the conductive layer 52.
  • conductive layer 32 corresponds to the wiring BL shown in Figure 20
  • conductive layer 33 corresponds to the wiring WL shown in Figure 20
  • conductive layer 34 corresponds to the wiring PL shown in Figure 20.
  • a low-resistance conductive material can be used for the conductive layer 34, the conductive layer 51, and the conductive layer 52.
  • the material that can be used for the conductive layer 23 can be used.
  • the insulating layer 53 functions as a dielectric layer of the capacitor 50, the thinner the film thickness and the higher the relative dielectric constant, the larger the capacitance of the capacitor 50.
  • the insulating layer 53 is preferably made of a material with a high relative dielectric constant (high-k).
  • the insulating layer 53 is preferably made of a laminate of layers having a high-k material.
  • the insulating layer 53 is preferably made of a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material.
  • an insulating film also called ZAZ in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulating layer 53.
  • an insulating film also called ZAZA in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • a material exhibiting ferroelectricity may be used as the insulating layer 53.
  • materials exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • FIGS. 22A, 22B, and 22C show an example in which the conductive layer 31, insulating layer 48, and insulating layer 44 shown in FIGS. 21A1, 21B, and 21C are not provided, and the insulating layer 41 is a single layer.
  • FIGS. 22B and 22C an example is shown in which the opening 20a reaches the conductive layer 52, and the bottom surface of the semiconductor layer 21 contacts the conductive layer 52.
  • FIGS. 22B and 22C an example is shown in which the insulating layer 41 covers a part of the upper surface of the conductive layer 52 and the side surface outside the opening 54.
  • FIGS. 22A, 22B, and 22C show an example in which the conductive layer 31, insulating layer 48, and insulating layer 44 shown in FIGS. 21A1, 21B, and 21C are not provided, and the insulating layer 41 is a single layer.
  • FIGS. 22B and 22C an example is shown in which the opening 20a reaches the conductive layer 52, and the bottom surface of
  • the insulating layer 41 can have a region that contacts the upper surface of the conductive layer 52 and a region that contacts the side surface of the conductive layer 52. Note that the opening corresponding to the opening 54a in FIGS. 21B and 21C is the opening 54 in FIGS. 22B and 22C.
  • the opening 20 may reach the insulating layer 53, and the semiconductor layer 21 may cover the upper surface of the conductive layer 52 and the side surface outside the opening 54.
  • the insulating layer 41 may not be in contact with the conductive layer 52.
  • the insulating layer 41 has a single-layer structure in the examples shown in FIGS. 22B and 22C, the insulating layer 41 may have a laminated structure of two or more layers. For example, it may have a three-layer laminated structure as shown in FIGS. 21B and 21C.
  • the conductive layer 52 functions as one of the source electrode and the drain electrode of the transistor 10.
  • the conductive layer 52 is made of a material similar to that which can be used for the conductive layer 31 shown in FIG. 21A1, FIG. 21B, FIG. 21C, etc.
  • FIG. 23A and 23B show an example of a memory device in which two memory cells 30 are connected to a common wiring.
  • FIG. 23A shows an example of the planar configuration of the memory device
  • FIG. 23B shows an example of the cross-sectional configuration along the cutting line A3-A4 in FIG. 23A.
  • the conductive layer 33 functioning as the wiring WL shown in FIG. 20 is provided individually for the two memory cells 30.
  • the conductive layer 32 functioning as the wiring BL shown in FIG. 20 is provided in common to the two memory cells 30.
  • the conductive layer 32 functioning as the wiring BL shown in FIG. 20 is electrically connected to the conductive layers 61 and 62 that are embedded in the interlayer insulating layers and function as plugs (also called connection electrodes).
  • the conductive layer 61 may be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11.
  • the insulating layer 65 functions as a barrier layer and prevents impurities such as water and hydrogen from diffusing into the memory device from the outside.
  • a memory cell array can be configured by arranging the memory cells 30 in a three-dimensional matrix.
  • FIG. 24A shows a planar configuration example of a memory device in which 4 ⁇ 2 ⁇ 4 memory cells 30 are arranged in the X, Y, and Z directions.
  • FIG. 24B shows a cross-sectional configuration example taken along the cutting line A3-A4 in FIG. 24A.
  • a group of four memory cells 30 is called a memory unit 60.
  • Eight memory units 60 (memory unit 60[1,1] to memory unit 60[2,4]) are shown in Figure 24A.
  • Four memory units 60 (memory unit 60[1,1] to memory unit 60[1,4]) are shown in Figure 24B.
  • memory unit 60[a,b] (a and b are positive integers), a indicates an address in the Y direction, and b indicates an address in the Z direction.
  • the memory unit 60 two memory cells 30 are arranged symmetrically around the conductive layer 61 or conductive layer 62.
  • the conductive layer 62 electrically connects the conductive layers 32 of the memory units 60 stacked in the Z direction. In this way, by stacking multiple memory units 60, the memory capacity per unit area can be increased. This makes it possible to realize a miniaturized or highly integrated memory device.
  • Figure 25A shows an example of the planar configuration of a memory device in which the connection portion is arranged at the end of the memory unit.
  • Figure 25B shows an example of the cross-sectional configuration along the cutting line A5-A6 in Figure 25A.
  • Figures 25A and 25B show an example of a memory device in which 3 x 3 x 4 memory cells 30 are arranged as an example of a memory cell array.
  • the first to fourth layers are denoted as layer 70[1] to layer 70[4], respectively.
  • a conductive layer 63 is provided outside the memory unit.
  • the conductive layer 63 may be electrically connected to the conductive layer 35 of the layer 70 above the layer 70 including the conductive layer 63.
  • the conductive layer 63 provided in the layer 70[1] is electrically connected to the conductive layer 35 provided in the layer 70[2].
  • the conductive layer 63 may be electrically connected to the conductive layer 35 of the layer 70 including the conductive layer 63, or may be electrically connected to the conductive layer 35 of the layer 70 located below the layer 70 including the conductive layer 63. Note that FIG.
  • the conductive layer 35 is provided in the same layer as the conductive layer 34, that is, the conductive layer 35 is formed in the same process as the conductive layer 34 and has the same material, but one embodiment of the present invention is not limited to this.
  • the conductive layer 35 may be provided in the same layer as the conductive layer 33, the same layer as the conductive layer 52, or the same layer as the conductive layer 31.
  • Figure 26 shows an example of the cross-sectional configuration of a memory device in which a layer having memory cells 30 is stacked on a layer in which a driving circuit including a sense amplifier is provided.
  • FIG. 26 an example is shown in which a capacitor 50 is provided above a transistor 90, and a transistor 10 is provided on the capacitor 50.
  • the transistor 90 can be one of the transistors included in the sense amplifier.
  • the bit line can be made shorter. This reduces the load on the bit line, improving the sensitivity of the readout by the sense amplifier. This allows the storage capacitance of the memory cell 30 to be reduced.
  • the transistor 90 is provided on a substrate 91 and has a conductive layer 94 that functions as a gate electrode, an insulating layer 93 that functions as a gate insulating layer, a semiconductor region 92 that is a part of the substrate 91, a low-resistance region 95a that functions as one of the source region or drain region, and a low-resistance region 95b that functions as the other of the source region or drain region.
  • the transistor 90 may be either a p-channel type or an n-channel type.
  • the transistor 90 shown in FIG. 26 has a semiconductor region 92 (part of the substrate 91) in which the channel is formed that has a convex shape.
  • a transistor 90 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate.
  • an insulating layer 520 is provided on a substrate 91 so as to cover the convex region.
  • An opening is provided in the insulating layer 520 reaching the semiconductor region 92, and an insulating layer 93 is provided along the upper surface of the semiconductor region 92 and the side surface of the insulating layer 520 at the opening.
  • a conductive layer 94 is provided on the insulating layer 93 so as to fill the opening. The height of the upper surface of the insulating layer 520, the height of the top surface of the insulating layer 93, and the height of the upper surface of the conductive layer 94 can be made to match or approximately match each other.
  • insulating layers 522, 524, and 526 are stacked in this order on insulating layer 520.
  • Conductive layer 528 electrically connected to low resistance region 95a or low resistance region 95b is embedded in insulating layer 520 and insulating layer 522.
  • Conductive layer 530 electrically connected to conductive layer 528 is embedded in insulating layer 524 and insulating layer 526.
  • a wiring layer may be provided on the insulating layer 526 and on the conductive layer 530.
  • an insulating layer 550, an insulating layer 582, and an insulating layer 584 are stacked in this order on the insulating layer 526 and on the conductive layer 530.
  • a conductive layer 586 electrically connected to the conductive layer 530 is embedded in the insulating layer 550, the insulating layer 582, and the insulating layer 584.
  • the insulating layers 520, 522, 524, 526, 550, 582, and 584 function as interlayer insulating layers.
  • the conductive layers 528, 530, and 586 function as plugs or wiring.
  • An insulating layer 11 is provided on the insulating layer 584 and on the conductive layer 586.
  • a conductive layer 12 electrically connected to the conductive layer 586 is embedded in the insulating layer 11.
  • An insulating layer 55 is provided on the insulating layer 11. The insulating layer 55 functions as an interlayer insulating layer.
  • a conductive layer 34 electrically connected to the conductive layer 51 of the capacitor 50, and a conductive layer 36 electrically connected to the conductive layer 12 are embedded in the insulating layer 55.
  • Insulating layer 47, insulating layer 53, and insulating layer 48 are stacked in this order on insulating layer 55, conductive layer 34, and conductive layer 36.
  • Conductive layer 37, which is electrically connected to conductive layer 36, is embedded in insulating layer 47, insulating layer 53, and insulating layer 48.
  • An insulating layer 44 is provided on the insulating layer 48.
  • a conductive layer 38 that is electrically connected to the conductive layer 37 is embedded in the insulating layer 44.
  • insulating layers 41a, 41b, and 41c are stacked in this order to form the insulating layer 41.
  • a conductive layer 39 that is electrically connected to the conductive layer 38 is embedded in the insulating layer 41.
  • a conductive layer 32 is provided on the insulating layer 41 and on the conductive layer 39, and the conductive layer 39 and the conductive layer 32 are electrically connected.
  • the low resistance region 95a or the low resistance region 95b is electrically connected to the conductive layer 32 via the conductive layer 528, the conductive layer 530, the conductive layer 586, the conductive layer 12, the conductive layer 36, the conductive layer 37, the conductive layer 38, and the conductive layer 39.
  • Figure 26 shows an example in which the low resistance region 95a and the conductive layer 32 are electrically connected.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • ⁇ Configuration example of storage device> 27 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention.
  • the memory device 480 illustrated in FIG. 27 includes a layer 420 and a stacked layer 470.
  • Layer 420 is a layer having a Si transistor.
  • element layers 430[1] to 430[m] (m is an integer of 2 or more) are stacked.
  • Element layers 430[1] to 430[m] are layers having an OS transistor.
  • Layer 470, in which layers having OS transistors are stacked, can be stacked on layer 420.
  • FIG. 27 shows an example in which the element layers 430[1] to 430[m] have a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n is an integer of 2 or more).
  • the memory cell 432 in the first row and first column is indicated as memory cell 432[1,1] and the memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n].
  • an arbitrary row may be indicated as row i.
  • an arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j].
  • the first wiring WL (first row) is shown as wiring WL[1]
  • the mth wiring WL (mth row) is shown as wiring WL[m].
  • the first wiring PL (first row) is shown as wiring PL[1]
  • the mth wiring PL (mth row) is shown as wiring PL[m].
  • the first wiring BL (first column) is shown as wiring BL[1]
  • the nth wiring BL (nth column) is shown as wiring BL[n]. Note that the number of layers of the element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.
  • the multiple memory cells 432 provided in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row.
  • the multiple memory cells 432 provided in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on/off (conductive or non-conductive) of an access transistor that functions as a switch.
  • the wiring PL functions as a constant potential line connected to a capacitor. Note that a separate wiring for transmitting the backgate potential can be provided.
  • the memory cells 432 of the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via the wiring BL.
  • the wiring BL can be arranged in a parallel direction and a vertical direction of the substrate surface on which the layer 420 is provided.
  • the wiring BL extending from the memory cells 432 of the element layers 430[1] to 430[m] can be configured with wiring arranged in a vertical direction in addition to wiring arranged in a horizontal direction on the substrate surface, thereby shortening the length of the wiring between the element layer 430 and the sense amplifier 446.
  • the signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing the power consumption and signal delay. Therefore, the power consumption and signal delay of the memory device 480 can be reduced. In addition, it is possible to operate even if the capacitance of the capacitor of the memory cell 432 is reduced. Therefore, the memory device 480 can be made smaller.
  • Layer 420 has PSW 471 (power switch), PSW 472, and peripheral circuit 422.
  • Peripheral circuit 422 has drive circuit 440, control circuit 473, and voltage generation circuit 474.
  • Each circuit in layer 420 has a Si transistor.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 473.
  • the control circuit 473 is a logic circuit that has the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480.
  • the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.
  • the voltage generation circuit 474 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.
  • the drive circuit 440 is a circuit for writing and reading data to the memory cells 432.
  • the drive circuit 440 has a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the sense amplifier 446 described above.
  • the row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR.
  • the row decoder 442 is a circuit for specifying the row to be accessed
  • the column decoder 444 is a circuit for specifying the column to be accessed.
  • the row driver 443 has a function of selecting the wiring WL specified by the row decoder 442.
  • the column driver 445 has a function of writing data to the memory cell 432, a function of reading data from the memory cell 432, a function of holding the read data, and the like.
  • the input circuit 447 has a function of holding a signal WDA.
  • the data held by the input circuit 447 is output to the column driver 445.
  • the output data of the input circuit 447 is data (Din) to be written to the memory cell 432.
  • the data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448.
  • the output circuit 448 has a function of holding Dout.
  • the output circuit 448 has a function of outputting Dout to the outside of the memory device 480.
  • the data output from the output circuit 448 is the signal RDA.
  • PSW471 has a function of controlling the supply of VDD to the peripheral circuit 422.
  • PSW472 has a function of controlling the supply of VHM to the row driver 443.
  • the high power supply voltage of the memory device 480 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW471 is controlled by signal PON1, and the on/off of PSW472 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • the element layer 430 provided in the first layer is shown as element layer 430[1]
  • the element layer 430 provided in the second layer is shown as element layer 430[2]
  • the element layer 430 provided in the fifth layer is shown as element layer 430[5].
  • Also shown in FIG. 28A are wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided).
  • the wiring BLB is an inverted bit line. Note that in order to make the drawing easier to understand, some of the wiring WL and wiring PL of each element layer 430 are omitted.
  • Figure 28B shows a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and wiring BLB shown in Figure 28A, and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. Note that a configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also called a "memory string.”
  • Figure 28B shows an example of the circuit configuration of the memory cell 432 connected to the wiring BLB.
  • the memory cell 432 includes a transistor 437 and a capacitor 438.
  • the transistor 437, the capacitor 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], etc.
  • the memory cell 30 illustrated in the previous embodiment can be applied to the memory cell 432. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438.
  • the transistor included in the sense amplifier 446 can be a transistor 90 (see Figure 26).
  • one of the source and drain of the transistor 437 is connected to the wiring BL.
  • the other of the source and drain of the transistor 437 is connected to one electrode of the capacitor 438.
  • the other electrode of the capacitor 438 is connected to the wiring PL.
  • the gate of the transistor 437 is connected to the wiring WL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitor 438. By connecting multiple wirings PL together and using them as one wiring, the number of wirings can be reduced.
  • OS transistors are stacked and wirings that function as bit lines are arranged in a direction perpendicular to the surface of the substrate on which the layer 420 is provided.
  • the transistor 437 and the capacitor 438 of the memory cell 432 are arranged in a direction perpendicular to the surface of the substrate on which the layer 420 is provided.
  • 29A and 29B show a circuit diagram corresponding to the memory cell 432 described above and a circuit block diagram corresponding to the circuit diagram.
  • the memory cell 432 may be shown as a block in the drawings. Note that the wiring BL shown in Fig. 29A and Fig. 29B can be similarly expressed when replaced with a wiring BLB.
  • 29C and 29D show a circuit diagram corresponding to the above-mentioned sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram.
  • the sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485.
  • wiring SA_OUT and wiring SA_OUTB that output the read signal are also shown.
  • the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2.
  • the transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.
  • the precharge circuit 483 is composed of n-channel transistors 483_1, 483_2, and 483_3.
  • the precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQ.
  • the precharge circuit 484 is composed of p-channel transistors 484_1, 484_2, and 484_3.
  • the precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQB.
  • the amplifier circuit 485 is composed of p-channel transistors 485_1 and 485_2, and n-channel transistors 485_3 and 485_4, which are connected to the wiring SAP or wiring SAN.
  • the wiring SAP or wiring SAN is a wiring that has a function of supplying VDD or VSS.
  • the transistors 485_1 to 485_4 are transistors that form an inverter loop.
  • FIG. 29D also shows a circuit block diagram corresponding to the sense amplifier 446 described in FIG. 29C, for example. As shown in FIG. 29D, the sense amplifier 446 may be represented as a block in the drawing.
  • Figure 30 is a block diagram of the memory device 480 of Figure 27.
  • Figure 30 illustrates the circuit blocks shown in Figures 29B and 29D.
  • the layer 470 including the element layer 430[m] has a memory cell 432.
  • the memory cell 432 shown in FIG. 30 is connected to a pair of wirings BL[1] and BLB[1], or wirings BL[2] and BLB[2].
  • the memory cell 432 connected to the wiring BL is a memory cell to which data is written or read.
  • the wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 446[2].
  • the sense amplifier 446[1] and the sense amplifier 446[2] can read data in response to the various signals described in FIG. 29D.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • a display device to which the transistor of one embodiment of the present invention is applied can be a display device with extremely high resolution.
  • the display device of one embodiment of the present invention can be used in the display portion of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display portion of a device that can be worn on the head (HMD: Head Mounted Display), such as a VR device such as a head mounted display, and a glasses-type AR device.
  • HMD Head Mounted Display
  • Display module 31A shows a perspective view of a display module 280.
  • the display module 280 includes a display device 200A and an FPC 290.
  • the display panel included in the display module 280 is not limited to the display device 200A, and may be a display device 200B or a display device 200C described later.
  • the display module 280 has a substrate 291 and a substrate 292.
  • the display module 280 has a display unit 281.
  • the display unit 281 is an area that displays an image.
  • Figure 31B shows a perspective view that shows a schematic configuration on the substrate 291 side.
  • a circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked.
  • a terminal portion 285 for connecting to an FPC 290 is provided in an area on the substrate 291 that does not overlap with the pixel portion 284.
  • the terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 that is composed of multiple wirings.
  • the pixel section 284 has a number of pixels 284a arranged periodically. An enlarged view of one pixel 284a is shown on the right side of FIG. 31B.
  • the pixel 284a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.
  • the pixel circuit section 283 has a number of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices in one pixel 284a.
  • One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device.
  • the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance for each light-emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.
  • the circuit portion 282 has a circuit that drives each pixel circuit 283a of the pixel circuit portion 283.
  • a gate line driver circuit and a source line driver circuit may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.
  • the FPC 290 functions as wiring for supplying video signals, power supply potential, etc. from the outside to the circuit section 282.
  • An IC may also be mounted on the FPC 290.
  • the display module 280 can be configured such that one or both of the pixel circuit section 283 and the circuit section 282 are provided overlappingly under the pixel section 284, so that the aperture ratio (effective display area ratio) of the display section 281 can be extremely high.
  • the aperture ratio of the display section 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
  • the pixels 284a can be arranged at an extremely high density, so that the resolution of the display section 281 can be extremely high.
  • the pixels 284a are arranged in the display section 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.
  • Such a display module 280 has extremely high resolution and can therefore be suitably used in VR devices such as head-mounted displays, or glasses-type AR devices.
  • the display module 280 has an extremely high resolution display section 281, so that even if the display section is enlarged with a lens, the pixels are not visible, and a highly immersive display can be performed.
  • the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display sections. For example, it can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • the display device 200A shown in FIG. 32 includes a substrate 331, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 240, and a transistor 10.
  • Substrate 331 corresponds to substrate 291 in FIG. 31A.
  • the configuration of transistor 10 can be seen in embodiment 1, so a description thereof will be omitted.
  • An insulating layer 332 is provided on a substrate 331, and a transistor 10 is provided on the insulating layer 332.
  • the insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 10 and prevents oxygen from being released from the semiconductor layer 21 to the insulating layer 332 side.
  • a film in which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • the insulating layer 42, the insulating layer 46, the insulating layer 49, and the insulating layer 266 function as interlayer insulating layers.
  • a barrier layer may be provided between the insulating layer 266 and the insulating layer 49 to prevent impurities such as water or hydrogen from diffusing from the insulating layer 266 to the transistor 10.
  • As the barrier layer an insulating film similar to the insulating layer 332 can be used.
  • the plug 274 electrically connected to one side of the conductive layer 32 is provided so as to be embedded in the insulating layer 266, the insulating layer 49, the insulating layer 46, and the insulating layer 42.
  • the plug 274 preferably has a conductive layer 274a that covers the side surfaces of the openings of the insulating layer 266, the insulating layer 49, the insulating layer 46, and the insulating layer 42, and a part of the upper surface of the conductive layer 32, and a conductive layer 274b that is located inside the conductive layer 274a and fills the opening.
  • a capacitor 240 is provided on the insulating layer 266.
  • the capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located between them.
  • the conductive layer 241 functions as one electrode of the capacitor 240
  • the conductive layer 245 functions as the other electrode of the capacitor 240
  • the insulating layer 243 functions as a dielectric of the capacitor 240.
  • the conductive layer 241 is provided on the plug 274 and on the insulating layer 266, and is embedded in the insulating layer 254.
  • the conductive layer 241 is electrically connected to the conductive layer 32 of the transistor 10 by the plug 274.
  • the insulating layer 243 is provided to cover the conductive layer 241.
  • the conductive layer 245 is provided in a region that overlaps with the conductive layer 241 via the insulating layer 243.
  • An insulating layer 255a is provided covering the capacitor 240, an insulating layer 255b is provided on the insulating layer 255a, and an insulating layer 255c is provided on the insulating layer 255b.
  • Insulating layer 255a, insulating layer 255b, and insulating layer 255c can each preferably be made of an inorganic insulating film.
  • a silicon oxide film for insulating layer 255a and insulating layer 255c and a silicon nitride film for insulating layer 255b. This allows insulating layer 255b to function as an etching protection film.
  • an example is shown in which part of insulating layer 255c is etched to form a recess, but insulating layer 255c does not necessarily have to have a recess.
  • Light emitting elements 110R, 110G, and 110B are provided on insulating layer 255c. Details of light emitting elements 110R, 110G, and 110B are described in embodiment 3.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be referred to as an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • display device 200A a different light-emitting device is created for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance.
  • organic layer 112R, organic layer 112G, and organic layer 112B are spaced apart from each other, crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. This makes it possible to realize a display panel that is both high-definition and has high display quality.
  • an insulating layer 125 In the area between adjacent light-emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.
  • the pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 32 of the transistor 10 by the plug 256 embedded in the insulating layers 255a, 255b, and 255c, the conductive layer 241 embedded in the insulating layer 254, and the plug 274.
  • the height of the upper surface of the insulating layer 255c and the height of the upper surface of the plug 256 are the same or approximately the same.
  • Various conductive materials can be used for the plug.
  • a protective layer 121 is provided on the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.
  • a substrate 170 is attached to the protective layer 121 by an adhesive layer 171.
  • Display device 200B A display device having a configuration partially different from that described above will be described below, but the same configuration as the above will be referred to and the description thereof may be omitted.
  • the display device 200B shown in FIG. 33 shows an example in which a transistor 10A, which is a planar type transistor in which a semiconductor layer is formed on a flat surface, and a transistor 10, which is a vertical channel type transistor, are stacked.
  • Transistor 10A has a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.
  • An insulating layer 352 is provided on the substrate 331.
  • the insulating layer 352 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 10 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352.
  • a film in which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • a conductive layer 357 is provided on the insulating layer 352, and an insulating layer 356 is provided on the insulating layer 352 so as to cover the conductive layer 357.
  • the conductive layer 357 functions as a first gate electrode of the transistor 10A, and a part of the insulating layer 356 functions as a first gate insulating layer.
  • An oxide insulating film such as a silicon oxide film is preferably used for at least the region of the insulating layer 356 that is in contact with the semiconductor layer 351.
  • the top surface of the insulating layer 356 is preferably planarized.
  • the semiconductor layer 351 is provided on the insulating layer 356.
  • the semiconductor layer 351 preferably has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor characteristics.
  • a pair of conductive layers 355 is provided on and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.
  • An insulating layer 358 and an insulating layer 350 are provided to cover the top and side surfaces of the pair of conductive layers 355 and the side surfaces of the semiconductor layer 351.
  • the insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351.
  • the insulating layer 358 can be an insulating film similar to the insulating layer 352.
  • An opening is provided in the insulating layer 358 and the insulating layer 350, reaching the semiconductor layer 351.
  • the conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.
  • the top surface of the conductive layer 354, the top surface of the insulating layer 353, and the top surface of the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them.
  • the insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 10.
  • the insulating layer 359 can be an insulating film similar to the insulating layer 352 described above.
  • Transistor 10 has a configuration in which a semiconductor layer in which a channel is formed is sandwiched between two gates.
  • the two gates may be connected and the transistor may be driven by supplying the same signal to them.
  • the threshold voltage of the transistor may be controlled by applying a potential to one of the two gates for controlling the threshold voltage and a potential to drive the other.
  • An insulating layer 361 is provided on the insulating layer 359, and a plug 374 is provided so as to be embedded in the insulating layer 361, the insulating layer 359, the insulating layer 350, and the insulating layer 358.
  • the plug 374 preferably has a conductive layer 374a that covers the side surfaces of the openings of the insulating layer 361, the insulating layer 359, the insulating layer 350, and the insulating layer 358 and a part of the upper surface of the conductive layer 355, and a conductive layer 374b that is located inside the conductive layer 374a and fills the opening.
  • the conductive layer 374a can be made of a material similar to that which can be used for the conductive layer 274a
  • the conductive layer 374b can be made of a material similar to that which can be used for the conductive layer 274b.
  • a conductive layer 371 is provided on the plug 374 and on the insulating layer 361.
  • the conductive layer 371 is electrically connected to the conductive layer 355 of the transistor 10A by the plug 374.
  • an insulating layer 362 is provided on the insulating layer 361 so as to cover the conductive layer 371.
  • an insulating layer 332 is provided on the insulating layer 362.
  • a display device 200C shown in FIG. 34 has a structure in which a transistor 310 having a channel formed in a semiconductor substrate and a transistor 10 which is a vertical channel transistor are stacked.
  • the transistor 310 has a channel formation region in the substrate 301.
  • the substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate.
  • the transistor 310 has a part of the substrate 301, a conductive layer 311, a low resistance region 312, an insulating layer 313, and an insulating layer 314.
  • the conductive layer 311 functions as a gate electrode.
  • the insulating layer 313 is located between the substrate 301 and the conductive layer 311, and functions as a gate insulating layer.
  • the low resistance region 312 is a region in which the substrate 301 is doped with impurities, and functions as one of the source and drain.
  • the insulating layer 314 is provided to cover the side surface of the conductive layer 311.
  • an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.
  • An insulating layer 261 is provided covering the transistor 310, and a plug 271 is provided so as to be embedded in the insulating layer 261.
  • a conductive layer 251 is provided on the plug 271 and on the insulating layer 261.
  • the conductive layer 251 is electrically connected to the low resistance region 312 of the transistor 310 by the plug 271.
  • An insulating layer 262 is provided on the insulating layer 261 so as to cover the conductive layer 251.
  • a conductive layer 252 is provided on the insulating layer 262, an insulating layer 263 is provided on the conductive layer 252, and an insulating layer 332 is provided on the insulating layer 263.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • Embodiment 4 a structural example of a display device that can be used for a display device manufactured using a transistor according to one embodiment of the present invention will be described.
  • the display device described below can be used for the pixel portion 284 in the above embodiment 3, for example.
  • One aspect of the present invention is a display device having a light-emitting element.
  • the display device has two or more pixels that emit light of different colors.
  • Each pixel has a light-emitting element.
  • Each light-emitting element has a pair of electrodes and an EL layer between them.
  • the light-emitting element is preferably an organic EL element (organic electroluminescence element).
  • Two or more light-emitting elements that emit different colors each have an EL layer that contains a different light-emitting material.
  • a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light.
  • the shape and position of the island-shaped organic film deviate from the design, making it difficult to achieve high resolution and a high aperture ratio of the display device.
  • the contour of the layer may become blurred and the film thickness at the end may become thin.
  • the film thickness of the island-shaped light-emitting layer may vary depending on the location.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM).
  • FMM fine metal mask
  • the EL layer can be produced separately, a display device that is extremely vivid, has high contrast, and has high display quality can be realized.
  • the EL layer may be processed into a fine pattern using both a metal mask and photolithography.
  • a part or the whole of the EL layer can be physically separated. This makes it possible to suppress leakage current between light-emitting elements via a layer shared between adjacent light-emitting elements (also called a common layer). This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.
  • One aspect of the present invention can be a display device that combines a white light-emitting light-emitting element and a color filter.
  • light-emitting elements of the same configuration can be applied to light-emitting elements provided in pixels (subpixels) that emit light of different colors, and all layers can be common layers. Furthermore, a part or all of each EL layer may be divided by photolithography. This suppresses leakage current through the common layer, and a display device with high contrast can be realized.
  • leakage current through the intermediate layer can be effectively prevented, and a display device that combines high brightness, high definition, and high contrast can be realized.
  • an insulating layer that covers at least the side surface of the island-shaped light-emitting layer.
  • the insulating layer may be configured to cover a part of the upper surface of the island-shaped EL layer.
  • a material that has barrier properties against water and oxygen For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This makes it possible to suppress deterioration of the EL layer and realize a highly reliable display device.
  • FIG. 35A shows a plan view of a display device 100 of one embodiment of the present invention.
  • the display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101.
  • the light-emitting regions of the light-emitting elements are labeled with R, G, or B.
  • Light emitting elements 110R, 110G, and 110B are each arranged in a matrix.
  • Figure 35A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be applied, and a pentile arrangement, a diamond arrangement, or the like may also be used.
  • the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B for example, it is preferable to use an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode).
  • the light-emitting material possessed by the EL element include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), and a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material).
  • TADF thermally activated delayed fluorescence
  • the light-emitting material possessed by the EL element not only organic compounds but also inorganic compounds (for example, quantum dot materials) can be used.
  • FIG. 35A also shows a connection electrode 111C that is electrically connected to the common electrode 113.
  • the connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113.
  • the connection electrode 111C is provided, for example, outside the display area in which the light-emitting elements 110R are arranged.
  • connection electrode 111C can be provided along the outer periphery of the display area. For example, it may be provided along one side of the outer periphery of the display area, or it may be provided over two or more sides of the outer periphery of the display area. In other words, if the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangle), L-shaped, U-shaped (square bracket shaped), square, etc.
  • Figures 35B and 35C are cross sections corresponding to the cutting lines D1-D2 and D3-D4 in Figure 35A, respectively.
  • Figure 35B shows cross sections of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B
  • Figure 35C shows a cross section of connection portion 140 where connection electrode 111C and common electrode 113 are connected.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be referred to as an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • light-emitting element 110R when describing matters common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, they may be referred to as light-emitting element 110.
  • components distinguished by alphabets such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabet.
  • the organic layer 112 and the common layer 114 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the organic layer 112 can have a laminated structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 can have an electron injection layer.
  • the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element.
  • the common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element.
  • a conductive film having translucency to visible light is used for either one of the pixel electrodes or the common electrode 113, and a conductive film having reflective properties is used for the other.
  • a protective layer 121 is provided on the common electrode 113, covering the light-emitting elements 110R, 110G, and 110B.
  • the protective layer 121 has the function of preventing impurities such as water from diffusing from above into each light-emitting element.
  • the end of the pixel electrode 111 is preferably tapered.
  • the organic layer 112 provided along the end of the pixel electrode 111 can also be tapered.
  • the coverage of the organic layer 112 provided over the end of the pixel electrode 111 can be improved.
  • foreign matter for example, also called dust or particles
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface.
  • the organic layer 112 is processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of the organic layer 112 at its edge is close to 90 degrees.
  • an organic film formed using FMM Fine Metal Mask
  • the top surface is formed in a slope shape over a range of 1 ⁇ m to 10 ⁇ m to the edge, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • an insulating layer 125 Between two adjacent light-emitting elements, there is an insulating layer 125, a resin layer 126, and a layer 128.
  • the resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the area between the two organic layers 112.
  • the resin layer 126 has a smooth convex upper surface shape, and the common layer 114 and common electrode 113 are provided covering the upper surface of the resin layer 126.
  • the resin layer 126 functions as a planarization film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the phenomenon in which the common electrode 113 is divided by the step at the end of the organic layer 112 (also called step disconnection), which occurs and causes the common electrode 113 on the organic layer 112 to become insulated.
  • the resin layer 126 can also be called an LFP (Local Filling Planarization) layer.
  • An insulating layer containing an organic material can be suitably used as the resin layer 126.
  • acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be used as the resin layer 126.
  • organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.
  • a photosensitive resin can be used as the resin layer 126.
  • a photoresist can be used as the photosensitive resin.
  • a positive type material or a negative type material can be used as the photosensitive resin.
  • the resin layer 126 may contain a material that absorbs visible light.
  • the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light.
  • a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix, etc. can be used.
  • the insulating layer 125 is provided so as to have an area in contact with the side surface of the organic layer 112.
  • the insulating layer 125 is also provided so as to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is also provided in contact with the upper surface of the substrate 101.
  • the insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact, the organic layer 112 may be dissolved by, for example, an organic solvent used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surface of the organic layer 112.
  • the insulating layer 125 can be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be used for the insulating layer 125.
  • the insulating layer 125 may have a single layer structure or a laminated structure.
  • the oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film.
  • the nitride insulating film include a silicon nitride film and an aluminum nitride film.
  • the oxynitride insulating film examples include a silicon oxynitride film and an aluminum oxynitride film.
  • nitride oxide insulating film examples include a silicon nitride oxide film and an aluminum nitride oxide film.
  • an inorganic insulating film such as a metal oxide film such as an aluminum oxide film or a hafnium oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with few pinholes and excellent function of protecting the EL layer can be formed.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • the insulating layer 125 can be formed by sputtering, CVD, PLD, ALD, or the like. It is preferable to form the insulating layer 125 by the ALD method, which has good coverage.
  • a reflective film e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.
  • a reflective film may be provided between the insulating layer 125 and the resin layer 126, and the light emitted from the light-emitting layer may be reflected by the reflective film. This can improve the light extraction efficiency.
  • Layer 128 is a portion of a protective layer (also called a mask layer or a sacrificial layer) for protecting organic layer 112 when organic layer 112 is etched.
  • the material that can be used for insulating layer 125 can be used for layer 128.
  • using the same material for layer 128 and insulating layer 125 is preferable because, for example, a common processing device can be used for both layers.
  • metal oxide films such as aluminum oxide films or hafnium oxide films, or inorganic insulating films such as silicon oxide films formed by the ALD method have few pinholes, so they have excellent functionality for protecting the EL layer and can be suitably used for the insulating layer 125 and layer 128.
  • the protective layer 121 can have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film.
  • the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.
  • a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide may be used as the protective layer 121.
  • the protective layer 121 may be a laminated film of an inorganic insulating film and an organic insulating film.
  • an organic insulating film is sandwiched between a pair of inorganic insulating films.
  • the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties.
  • the upper surface of the protective layer 121 is flat, it is preferable that when a structure (e.g., a color filter, an electrode of a touch sensor, or a lens array, etc.) is provided above the protective layer 121, the influence of the uneven shape caused by the structure below can be reduced.
  • a structure e.g., a color filter, an electrode of a touch sensor, or a lens array, etc.
  • Figure 35C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected.
  • connection portion 140 an opening portion is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C.
  • the connection electrode 111C and the common electrode 113 are electrically connected in the opening portion.
  • FIG. 35C shows a connection portion 140 that electrically connects the connection electrode 111C and the common electrode 113
  • the common electrode 113 may be provided on the connection electrode 111C via the common layer 114.
  • the electrical resistivity of the material used for the common layer 114 is sufficiently low and the layer can be formed thin, so that there are often no problems even if the common layer 114 is located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same masking mask, thereby reducing manufacturing costs.
  • Figure 36A shows a cross section of the display device 100a.
  • the main differences between the display device 100 and the display device 100 described above are that the light-emitting element has a different configuration and that the display device 100a has a colored layer.
  • the display device 100a has a light-emitting element 110W that emits white light.
  • the light-emitting element 110W has a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113.
  • the organic layer 112W emits white light.
  • the organic layer 112W can be configured to include two or more types of light-emitting materials whose emitted light colors are complementary to each other.
  • the organic layer 112W can be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. It may also be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.
  • the organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, and to suppress crosstalk caused by the leakage current. This makes it possible to realize a display device with high contrast and color reproducibility.
  • An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and colored layers 116R, 116G, and 116B are provided on the insulating layer 122.
  • the insulating layer 122 can be an organic resin film or an inorganic insulating film with a flattened upper surface.
  • the insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed.
  • the flat upper surface of the insulating layer 122 allows the thicknesses of the colored layers 116R, 116G, and 116B to be uniform, thereby improving color purity. If the thicknesses of the colored layers 116R, 116G, and 116B are not uniform, the amount of light absorbed varies depending on the location of the colored layers 116R, 116G, and 116B, which may result in a decrease in color purity.
  • FIG. 36B shows a cross section of the display device 100b.
  • Light-emitting element 110R has pixel electrode 111, conductive layer 115R, organic layer 112W, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111, conductive layer 115G, organic layer 112W, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111, conductive layer 115B, organic layer 112W, and common electrode 113.
  • Conductive layer 115R, conductive layer 115G, and conductive layer 115B each have light-transmitting properties and function as optical adjustment layers.
  • a microresonator (microcavity) structure By using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113, a microresonator (microcavity) structure can be realized.
  • a microresonator (microcavity) structure By adjusting the film thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when an organic layer 112 that emits white light is used, light with different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.
  • colored layers 116R, 116G, and 116B are provided on the optical paths of light-emitting elements 110R, 110G, and 110B, respectively, to obtain light with high color purity.
  • an insulating layer 123 is provided to cover the ends of the pixel electrode 111 and the conductive layer 115.
  • the insulating layer 123 preferably has a tapered end.
  • the organic layer 112W and the common electrode 113 are each provided as a continuous film common to each light-emitting element. This configuration is preferable because it can greatly simplify the manufacturing process of the display device.
  • the pixel electrode 111 has an end shape that is nearly vertical. This allows a steeply inclined region to be formed on the surface of the insulating layer 123, and a thin region can be formed in a part of the organic layer 112W that covers this region, or a part of the organic layer 112W can be divided. Therefore, it is possible to suppress leakage current through the organic layer 112W that occurs between adjacent light-emitting elements without processing the organic layer 112W by, for example, photolithography.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the electronic device of this embodiment has a display panel (display device) in which the transistor of one embodiment of the present invention is applied to a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution, and can also achieve high display quality. Therefore, the display device can be used in the display portion of various electronic devices.
  • Examples of electronic devices include television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display panel of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.
  • the display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 37A to 37D An example of a wearable device that can be worn on the head will be described using Figures 37A to 37D.
  • These wearable devices have one or both of the functions of displaying AR content and VR content. Note that these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR.
  • Electronic device 700A shown in FIG. 37A and electronic device 700B shown in FIG. 37B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply, for example, a video signal through the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • electronic device 700A and electronic device 700B are provided with batteries, which can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation, a slide operation, or the like by the user, and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding.
  • a tap operation can execute processes such as pausing or resuming a video
  • a slide operation can execute processes such as fast-forwarding or rewinding.
  • the range of operations can be expanded.
  • Various touch sensors can be applied to the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, or an optical type.
  • a capacitance type or an optical type sensor it is preferable to apply to the touch sensor module.
  • a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element).
  • the active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 37C and electronic device 800B shown in FIG. 37D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Electrical device 800A and electronic device 800B can each be considered electronic devices for VR.
  • a user wearing electronic device 800A or electronic device 800B can view the image displayed on display unit 820 through lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head.
  • the mounting unit 823 is illustrated as having a shape similar to the temples of glasses (for example, but is not limited to this).
  • the mounting unit 823 only needs to be wearable by the user, and may be, for example, in the shape of a helmet or band.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal may be connected to a cable that supplies, for example, a video signal from a video output device and power for charging a battery provided in the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 37A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 37C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • Electronic device 700B shown in FIG. 37B has an earphone unit 727.
  • earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.
  • the electronic device 800B shown in FIG. 37D has an earphone unit 827.
  • the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the mounting unit 823.
  • the earphone unit 827 and the mounting unit 823 may also have a magnet. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • the electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.
  • a display panel of one embodiment of the present invention can be applied to the display portion 6502.
  • Figure 38B is a cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in an area outside the display portion 6502, and an FPC 6515 is connected to the folded back area.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 38C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the television device 7100 shown in FIG. 38C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 38D shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7216 includes, for example, one or more of a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like.
  • the use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.
  • Figures 38E and 38F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 38E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 38F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • a display panel of one embodiment of the present invention can be applied to the display portion 7000.
  • the electronic device shown in Figures 39A to 39G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • the electronic device shown in Figures 39A to 39G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic device are not limited to these, and it can have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a function of, for example, providing a camera, taking still images or videos, and storing them on a recording medium (external or built into the camera), a function of displaying the taken images on the display unit, etc.
  • Figure 39A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, or the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • Figure 39A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of the e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • the icon 9050, etc. may be displayed at the position where the information 9051 is displayed.
  • Figure 39B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while storing the mobile information terminal 9102 in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.
  • FIG 39C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG 39D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself through the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • Figures 39E to 39G are perspective views showing a foldable mobile information terminal 9201.
  • Figure 39E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • Figure 39G is a folded state
  • Figure 39F is a perspective view of a state in the middle of changing from one of Figures 39E and 39G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, large scale computers, space equipment, and data centers (DCs).
  • DCs data centers
  • Electronic components, electronic devices, large scale computers, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • an electronic component to which a semiconductor device according to one embodiment of the present invention is applied can be applied to the electronic device exemplified in embodiment 5.
  • FIG. 40A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 40A has a semiconductor device 710 in a mold 711. In FIG. 40A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • a bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSVs, and therefore to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip, for example, by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a graphics processing unit (GPU), or a field programmable gate array (FPGA).
  • a CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable gate array
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer is sometimes called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode is provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrode.
  • a TSV can also be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 40B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • [Mainframe computers] 41A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • Figure 41B shows an oblique view of an example of a computer 5620.
  • Computer 5620 has a motherboard 5630.
  • Motherboard 5630 has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, each of which is connected to motherboard 5630.
  • Figure 41C shows an example of a PC card 5621.
  • the PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, and a storage device.
  • the PC card 5621 has a board 5622, and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622.
  • Figure 41C illustrates components other than electronic components 5626, 5627, and 5628.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 and inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621.
  • Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface).
  • Examples of the standards for each include HDMI (registered trademark).
  • the electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, soldering the terminals by a reflow method.
  • Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the electronic component 5627.
  • the electronic component 5628 includes a memory device.
  • the electronic component 700 can be used as the electronic component 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.
  • Figure 42A shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 42A also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the power required for the operation of the satellite 6800 is generated.
  • the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated.
  • the solar panel is sometimes called a solar cell module.
  • the satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another satellite.
  • the position of the receiver that received the signal can be measured.
  • the satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object located on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center, for example.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 42B shows a storage system that can be applied to a data center.
  • the storage system 6000 shown in Figure 42B has multiple servers 6001sb as hosts 6001. It also has multiple storage devices 6003md as storage 6003.
  • the host 6001 and storage 6003 are shown connected via a storage area network 6004 and a storage control circuit 6002.
  • the host 6001 corresponds to a computer that accesses data stored in the storage 6003.
  • the hosts 6001 may be connected to each other via a network.
  • Storage 6003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems typically provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data
  • the frequency of refreshing can be reduced and power consumption can be reduced.
  • miniaturization is possible.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • 10A transistor, 10: transistor, 11: insulating layer, 12: conductive layer, 20a: opening, 20b: opening, 20: opening, 21f: semiconductor film, 21i: channel formation region, 21n: low resistance region, 21: semiconductor layer, 22f: insulating film, 22: insulating layer, 23f: conductive film, 23: conductive layer, 26: opening, 27: conductive layer, 28: insulating layer, 29: opening, 30: memory cell, 31: conductive layer, 32 : conductive layer, 33: conductive layer, 34: conductive layer, 35: conductive layer, 36: conductive layer, 37: conductive layer, 38: conductive layer, 39: conductive layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 41: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47: insulating layer, 48: insulating layer, 49: insulating

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