WO2024103588A1

WO2024103588A1 - Semiconductor structure manufacturing method, semiconductor structure, and memory

Info

Publication number: WO2024103588A1
Application number: PCT/CN2023/082606
Authority: WO
Inventors: 李浩然
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-11-17
Filing date: 2023-03-20
Publication date: 2024-05-23
Also published as: CN118099085A

Abstract

Disclosed are a semiconductor structure manufacturing method, a semiconductor structure, and a memory. The method comprises: forming an initial conductive layer on an initial semiconductor structure; at least etching the initial conductive layer to form conductive structures and a first groove located between the conductive structures; forming protective layers covering the tops of the conductive structures and the inner surface of the first groove, wherein the protective layer located at the tops of the conductive structures is defined as a first protective layer, and the protective layer located at the bottom of the first groove is defined as a second protective layer; and etching the second protective layer and the bottom surface of the first groove by using the first protective layer as a mask, so that the depth of the first groove is increased to form a second groove.

Description

A method for manufacturing a semiconductor structure, a semiconductor structure, and a memory

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to a Chinese patent application filed with the Chinese Patent Office on November 17, 2022, with application number 202211443124.8 and application name “A method for manufacturing a semiconductor structure, a semiconductor structure, and a memory”, the entire contents of which are incorporated by reference in this application.

Technical Field

The embodiments of the present application relate to, but are not limited to, a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory.

Background technique

As the size of dynamic random access memory (DRAM) continues to shrink, the key dimensions of semiconductor devices continue to decrease, and the circuit lines in the memory are becoming more and more dense. Due to the small spacing between wires, the process window is getting narrower and narrower, making it more difficult to manufacture. The etching residues produced in the preparation process often cause the final manufactured memory to have problems such as poor circuit performance. Therefore, how to improve the reliability of the circuit to ensure the performance of the memory has become a technical problem that needs to be solved urgently.

Summary of the invention

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing an initial semiconductor structure; forming an initial conductive layer on the initial semiconductor structure; etching at least the initial conductive layer to form a conductive structure and a first groove located between the conductive structures; forming a protective layer covering the top of the conductive structure and the inner surface of the first groove, wherein the protective layer located at the top of the conductive structure is defined as a first protective layer, and the protective layer located at the bottom of the first groove is defined as a second protective layer, and the thickness of the first protective layer is greater than the thickness of the second protective layer; using the first protective layer as a mask, etching the second protective layer and the bottom surface of the first groove so that the depth of the first groove increases to form a second groove.

The embodiment of the present disclosure also provides a semiconductor structure, including: a substrate, and a conductive structure located above the substrate; a third protective layer covering the side walls of the conductive structure; a first dielectric layer covering the third protective layer and located between adjacent conductive structures, wherein the lower surface of the first dielectric layer is lower than the lower surface of the third protective layer.

An embodiment of the present disclosure further provides a memory, comprising the semiconductor structure in any embodiment provided in the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

2a to 2q are schematic diagrams of the structure of a semiconductor structure provided by an embodiment of the present disclosure during the manufacturing process;

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

Reference numerals:

10-initial semiconductor structure; 100-substrate; active area-101; isolation structure-102; transistor-103; second dielectric layer-104; contact hole-105; source-106; drain-107; diffusion barrier layer-108; metal layer-109; initial conductive layer-110; etching stop layer-111; spacer-19; conductive structure-20; first groove-21; protective layer-22; first protective layer-221; second protective layer-222; third protective layer-223; fourth protective layer-224; second groove-23; first dielectric layer-24; air gap-25; first adjustment layer-26; second adjustment layer-27; third adjustment layer-28; third groove-29; substrate-30.

Detailed ways

The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. The same reference numerals denote the same elements throughout.

It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

Spatially relative terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that except for the figures, Spatially relative terms are intended to include different orientations of devices in use and operation in addition to the orientations shown in the drawings. For example, if the device in the drawings is flipped, then elements or features described as "below" or "beneath" or "under" other elements will be oriented "above" other elements or features. Thus, the exemplary terms "below" and "under" may include both upper and lower orientations. Devices may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said/the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

As the size of dynamic random access memory (DRAM) continues to shrink, the critical dimensions of semiconductor devices continue to decrease, and the circuit lines in the memory are becoming more and more dense and complex. Since the spacing between wires is too small, the process window is getting narrower and narrower, and the manufacturing is more difficult. For example, when forming a conductive structure through an etching process, it is easy to cause residual conductive material between the lines. The residual conductive material is easy to cause leakage or even short circuit and other adverse effects, which in turn affects the reliability of the circuit and the performance of the memory.

Based on this, the present disclosure provides a method for manufacturing a semiconductor structure. Please refer to FIG. 1 for details. As shown in FIG. 1 , the method includes:

Step 101: providing an initial semiconductor structure 10;

Step 102: forming an initial conductive layer 110 on the initial semiconductor structure 10; etching at least the initial conductive layer to form conductive structures 20 and first grooves 21 between the conductive structures 20;

Step 103: forming a protective layer 22 covering the top of the conductive structure 20 and the inner surface of the first groove 21, wherein the protective layer 22 located on the top of the conductive structure 20 is defined as a first protective layer 221, and the protective layer 22 located at the bottom of the first groove 21 is defined as a second protective layer 222, and the thickness of the first protective layer 221 is greater than the thickness of the second protective layer 222;

Step 104 : using the first protection layer 221 as a mask, etching the second protection layer 222 and the bottom surface of the first groove 21 , so that the depth of the first groove 21 increases to form the second groove 23 .

The manufacturing method of the semiconductor structure provided by the present disclosure is further described in detail below in conjunction with specific embodiments.

First, step 101 is performed, referring to FIG. 2 a , to provide an initial semiconductor structure 10 .

Here, the initial semiconductor structure 10 may be any semiconductor structure, including but not limited to a semiconductor structure obtained in various process steps during the preparation of a dynamic random access memory (DRAM).

In some embodiments, referring to FIG. 2a and FIG. 2b, the initial semiconductor structure 10 can be prepared by the following method. Specifically, the initial semiconductor structure 10 is provided, including: providing a substrate 100; forming an active region 101 and an isolation structure 102 defining the active region 101 in the substrate 100; forming a transistor 103 based on the active region 101; forming a second dielectric layer 104 covering the substrate 100 and the transistor 103; etching the second dielectric layer 104 to form a contact hole 105, wherein the contact hole 105 exposes the source 106 or the drain 107 of the transistor 103; wherein the initial conductive layer 110 is filled in the contact hole 105, and the conductive structure 20 is partially They are respectively located in the contact holes 105 .

The conductive structure 20 in the contact hole 105 can play a role similar to a contact plug to connect the transistor 103 to an external circuit.

In actual operation, the substrate 100 includes, for example, but is not limited to, a single semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (for example, a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate 100 may be doped or undoped, or may include both doped and undoped regions. The substrate 100 may also include one or more doped ( ^n- or ^p- ) regions. In some specific embodiments, the substrate 100 includes a doped or undoped silicon substrate. The second dielectric layer 104 may be prepared by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes, wherein the material of the second dielectric layer 104 may include an insulating material, such as oxide, nitride, oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or fluorine-doped silicate glass (FSG), etc. The second dielectric layer 104 may be etched by using an anisotropic etching process, such as a plasma etching process, to form the contact hole 105 .

Next, perform step 102, see Figures 2a and 2b, form an initial conductive layer 110 on the initial semiconductor structure 10 (see Figure 2a); at least etch the initial conductive layer 110 to form conductive structures 20 and first grooves 21 located between the conductive structures 20 (see Figure 2b).

In actual operation, the initial conductive layer 110 can be prepared by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, and after the contact hole 105 is filled with a conductive material, the conductive material is continuously deposited to form the initial conductive layer 110 covering the initial semiconductor structure 10, wherein the material of the initial conductive layer 110 can include metal, carbon-containing material or metal nitride, etc., specifically, for example, any combination of one or more of tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride. When etching the initial conductive layer 110, only the initial conductive layer 110 can be etched, that is, the etching process stops after the initial conductive layer 110 is etched through, and the initial semiconductor structure 10 below the initial conductive layer 110 will not be etched. Of course, in actual operation, in order to better ensure that the initial conductive layer 110 is completely cut off and prevent problems such as short circuits, the initial semiconductor structure 10 can continue to be over-etched after the initial conductive layer 110 is etched through. At the same time, in order to avoid excessive impact on the initial semiconductor structure 10, an etching stop layer 111 can also be set above the second dielectric layer 104, so that the bottom of the first groove 21 stops in the etching stop layer 111, and the material of the etching stop layer 111 includes but is not limited to one or more of silicon nitride, silicon carbide or silicon carbonitride.

In some embodiments, referring to FIG. 2 q , the conductive structure 20 may further include a diffusion barrier layer 108 conformally covering the contact hole 105 and a portion of the second dielectric layer 104 , and a metal layer 109 covering the diffusion barrier layer 108 .

When the conductive structure 20 includes the metal layer 109 , the diffusion barrier layer 108 can prevent the diffusion of the metal material, thereby ensuring the reliability of the circuit.

In actual operation, the diffusion barrier layer 108 and the metal layer 109 can be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. When the material of the metal layer 109 includes tungsten, the material of the diffusion barrier layer 108 may include titanium nitride; when the material of the metal layer 109 includes copper, the material of the diffusion barrier layer 108 may include tantalum nitride.

The conductive structure 20 formed in the embodiment of the present disclosure can be used as a word line in the storage area or a peripheral area. The metal wiring may also be used as a contact pad for connecting to external structures, such as a node contact plug or a bit line contact. It is to be understood that the above is merely an example of the use of the conductive structure 20 and is not intended to limit the use of the conductive structure 20.

Next, step 103 is performed, see Figure 2c, to form a protective layer 22 covering the top of the conductive structure 20 and the inner surface of the first groove 21. The protective layer 22 located at the top of the conductive structure 20 is defined as a first protective layer 221, and the protective layer 22 located at the bottom of the first groove 21 is defined as a second protective layer 222. The thickness of the first protective layer 221 is greater than the thickness of the second protective layer 222.

In actual operation, when forming the protective layer 22, due to the geometric structure of the first groove 21, the flow and diffusion of the reactants in the first groove 21 are subject to certain restrictions, thereby reducing the amount of reactants delivered to the bottom of the first groove 21 relative to the amount of reactants on the surface of the conductive structure 20. This causes the deposition rate of the material of the protective layer 22 at the bottom of the first groove 21 to be lower than the deposition rate of the material of the protective layer 22 at the top of the conductive structure 20. Therefore, the thickness of the first protective layer 221 located at the top of the conductive structure 20 is ultimately greater than the thickness of the second protective layer 222 located at the bottom of the first groove 21.

The thickness of the first protective layer 221 is greater than that of the second protective layer 222 , so that in the subsequent process of etching the second protective layer 222 and the bottom surface of the first groove 21 , the first protective layer 221 can protect the conductive structure 20 .

Here, the material of the protective layer 22 may include an insulating material, for example, including but not limited to one or more of silicon nitride, silicon oxynitride, polymer materials, etc., and may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The material of the protective layer 22 is an insulating material, which can avoid or reduce the generation of new conductive material byproducts remaining at the bottom of the second groove 23 during the subsequent etching of the second protective layer 222 and the bottom surface of the first groove 21, so that it will not have an adverse effect on the circuit performance of the semiconductor device.

In some specific embodiments, the deposition parameters may be controlled so that the ratio of the thickness of the first protective layer 221 to the thickness of the second protective layer 222 is 3-5, including end points.

When the ratio of the thickness of the first protective layer 221 to the thickness of the second protective layer 222 is too small, in the subsequent process of etching the second protective layer 222 and the bottom surface of the first groove 21, the first protective layer 221 is easily removed during etching, thereby causing the conductive structure 20 to be over-etched, so the first protective layer 221 cannot play a role in protecting the conductive structure 20. On the other hand, when the ratio of the thickness of the first protective layer 221 to the thickness of the second protective layer 222 is too large, the manufacturing process time is extended, and after the subsequent process of etching the second protective layer 222 and the bottom surface of the first groove 21, the remaining thickness of the first protective layer 221 is relatively thick, which affects the improvement of the integration of the semiconductor structure. Therefore, in some more specific embodiments, the ratio of the thickness of the first protective layer 221 to the thickness of the second protective layer 222 is preferably 3.5-4.5, including endpoint values, such as 3.8, 4.0, 4.2 or 4.4, so that the first protective layer 221 can play a better protective role on the conductive structure 20 while simplifying the manufacturing process and taking into account the improvement of the integration.

Finally, step 104 is performed, referring to FIGS. 2 d and 2 e , using the first protective layer 221 as a mask, the second protective layer 222 and the bottom surface of the first groove 21 are etched, so that the depth of the first groove 21 is increased to form the second groove 23 .

When the bottom surface of the second groove 21 is further etched, the initial conductive layer residue remaining on the bottom surface of the second groove 21 will be removed together, thereby reducing the short circuit problem caused by the conductive residue. The anisotropic etching process, such as a plasma etching process, is used to form the

When etching the second protective layer 222 and the bottom surface of the first groove 21, the first protective layer 221 is consumed. In actual operation, when performing step 104, it is possible to choose whether to completely consume the first protective layer 221 or to retain a certain thickness of the first protective layer 221 according to actual conditions.

For example, in the first embodiment, referring to FIG. 2 d , the second protective layer 222 and the bottom surface of the first groove 21 are etched using the first protective layer 221 as a mask until the first protective layer 221 is removed.

The second protective layer 222 and the bottom surface of the first groove 21 are etched until the first protective layer 221 is removed, so that the depth of the first groove 21 can be increased as much as possible, thereby making it possible to remove the conductive material byproducts remaining at the bottom of the first groove 21 more thoroughly, so as to avoid or reduce problems such as leakage or even short circuit that may be caused by the residual conductive material byproducts.

In the second embodiment, referring to FIG. 2e, the second protective layer 222 and the bottom surface of the first groove 21 are etched using the first protective layer 221 as a mask until the first protective layer 221 reaches a preset thickness, and the remaining first protective layer 221 is defined as a fourth protective layer 224. Here, the preset thickness may be, for example, 3-20 nm, including endpoint values, specifically, 5 nm, 10 nm, 15 nm, or 18 nm.

The second protective layer 222 and the bottom surface of the first groove 21 are etched until the first protective layer 221 reaches a preset thickness, so that the top of the conductive structure 20 has the remaining first protective layer 221, thereby better ensuring that the conductive structure 20 will not be over-etched, thereby avoiding or reducing adverse effects on the conductive structure 20, and further ensuring the stability of the circuit performance of the semiconductor device.

After the second groove 23 is formed, as shown in FIGS. 2 f to 2 h , the process further includes forming a first dielectric layer 24 and patterning the first dielectric layer 24 to expose the conductive structure 20 .

When the first embodiment is used to perform step 104, referring to FIGS. 2f and 2g, after etching the second protective layer 222 and the bottom surface of the first groove 21, the first protective layer 221 is completely removed, and then a first dielectric layer 24 is formed. The first dielectric layer 24 fills the second groove 23 and covers the third protective layer 223 (the protective layer 22 located on the side wall of the first groove 21 is defined as the third protective layer 223) and the conductive structure 20 (see FIG. 2f); the first dielectric layer 24 located above the conductive structure 20 is removed to expose the conductive structure 20 (see FIG. 2g).

The first dielectric layer 24 can be used as an insulating layer between the conductive structures 20 to avoid or reduce short circuits or other circuit failures, and the third protective layer 223 covering the sidewalls of the conductive structure 20 can protect the sidewalls of the conductive structure 20 during the process of etching to form the second groove 23. In addition, the third protective layer 223 can also serve as a barrier layer for the conductive structure 20, for example, when the material of the conductive structure 20 includes a metal material, it can prevent the diffusion of the metal material.

When the second embodiment is used to perform step 104, referring to FIGS. 2h and 2g, after etching the second protective layer 222 and the bottom surface of the first groove 21, the fourth protective layer 224 is retained, and then the first dielectric layer 24 is formed, the first dielectric layer 24 fills the second groove 23, and covers the third protective layer 223 (the protective layer 22 located on the side wall of the first groove 21 is defined as the third protective layer 223) and the fourth protective layer 224 (see FIG. 2h); the first dielectric layer 24 and the fourth protective layer 224 located above the conductive structure 20 are removed to expose the conductive structure 20 (see FIG. 2g).

Compared with the first embodiment, the third protective layer 223 covering the sidewall of the conductive structure 20 and the fourth protective layer 224 covering the top of the conductive structure 20 can better protect the conductive structure 20 during the process of etching to form the second groove 23. Both can be used as barrier layers of the conductive structure 20 . When the conductive structure 20 is made of metal material, the third protective layer 223 and the fourth protective layer 224 can better block the diffusion of the metal material.

In actual operation, the first dielectric layer 24 may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes, wherein the material of the first dielectric layer 24 may include an insulating material, and in some specific embodiments, the dielectric constant of the material of the first dielectric layer 24 is less than or equal to the dielectric constant of the material of the third protective layer 223. In actual operation, the material of the first dielectric layer 24 may include a low dielectric constant material, such as a low-k dielectric material with a dielectric constant (k value) lower than about 3.0, lower than about 2.5 or a lower k value, including but not limited to silicon oxide, carbon-based materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) or other silicon-based polymer materials. The dielectric constant of the material of the first dielectric layer 24 is less than or equal to the dielectric constant of the material of the third protective layer 223, and the low dielectric constant material with a lower dielectric constant as much as possible can effectively reduce the parasitic capacitance between the conductive structures 20, thereby improving the resistance-capacitance (RC) delay, so as to improve the performance of the semiconductor device.

In some embodiments, referring to FIGS. 2 i to 2 k , forming the first dielectric layer 24 may include: depositing a first dielectric layer material such that the first dielectric layer material includes an air gap 25 , wherein the air gap 25 is located in the second groove 23 .

The first dielectric layer material includes an air gap 25, because the dielectric constant of air or vacuum is significantly lower than the dielectric constant of commonly used dielectric layer materials. For example, the dielectric constant value of commonly used dielectric layer materials with low dielectric constants is generally 2-3, while the dielectric constant value of air is 1. Therefore, the first dielectric layer 24 is combined with the air gap 25 located in the second groove 23. The dielectric constant of the dielectric layer between the conductive structures 20 can be further reduced on the basis of making the first dielectric layer material have a low dielectric constant. Therefore, the parasitic capacitance between the conductive structures 20 can be further reduced, thereby better improving the resistance-capacitance (RC) delay, so as to further enhance the performance of the semiconductor device.

Since two implementations of step 104 are given above, after forming the second groove 23, the top of the conductive structure may include the fourth protective layer 224, or may not include the fourth protective layer 224. After performing step 104 in any of the two implementations, in actual operation, the first dielectric layer material is deposited so that the first dielectric layer material includes the air gap 25, and the following three processes may be used but are not limited to:

In the first manufacturing process, taking the top of the conductive structure 20 including the fourth protective layer 224 as an example, referring to FIGS. 2i to 2k , firstly, a first adjustment layer 26 covering the sidewall and bottom of the second groove 23 and the third protective layer 223 and the fourth protective layer 224 is formed, and then, a second adjustment layer 27 covering the first adjustment layer 26 is formed (see FIG. 2i ); next, the second adjustment layer 27 located on the top and bottom of the first adjustment layer 26 is removed by etching, and the second adjustment layer 27 located on the sidewall of the first adjustment layer 26 is retained (see FIG. 2j );

In actual operation, the first adjustment layer 26 can be formed by using tetraethyl orthosilicate and ozone as reaction gases, and the second adjustment layer 27 can be formed by using silane and oxygen as reaction gases, using a plasma enhanced chemical vapor deposition (PECVD) process. Specifically, in the process of forming the first adjustment layer 26 and the second adjustment layer 27, the temperature in the reaction chamber can be 300°C to 400°C, including end values, such as 320°C, 350°C or 380°C, and the deposition rate of silane or tetraethyl orthosilicate can be Includes endpoint values, for example or Reaction time can be The reaction time is 3s to 150s, including endpoint values, such as 50s, 80s or 100s. Silane reacts with oxygen to produce silicon oxide, and ethyl orthosilicate reacts with ozone to produce silicon oxide. Although the materials of the first adjustment layer 26 and the second adjustment layer 27 are both silicon oxide, due to the different reaction gases for forming the first adjustment layer 26 and the second adjustment layer 27, the surface of the second adjustment layer 27 is rougher than that of the first adjustment layer 26, which is more conducive to the deposition of the reaction product oxide on its surface.

Next, a first dielectric layer 24 is formed, wherein the first dielectric layer material includes an air gap 25 (see FIG. 2k );

In actual operation, the first dielectric layer 24 can be formed by a subatmospheric pressure chemical vapor deposition (SACVD) process using tetraethyl orthosilicate and ozone as reaction gases. The material of the first dielectric layer 24 is silicon oxide. Since the surface of the second adjustment layer 27 is rougher than the surface of the first adjustment layer 26, the deposition rate of the first dielectric layer 24 on the second adjustment layer 27 located on the side wall of the second groove 23 is greater than the deposition rate of the first dielectric layer 24 on the first adjustment layer 26 located at the bottom of the second groove 23. Therefore, when the first dielectric layer 24 fills the second groove 23, premature sealing will occur, thereby forming an air gap 25 in the first dielectric layer 24.

In the second manufacturing process, taking the case where the top of the conductive structure 20 does not include the fourth protective layer 224 as an example, referring to FIGS. 21 to 2n, firstly, a first dielectric layer 24 covering the sidewall and bottom of the second groove 23, the third protective layer 223 and the conductive structure 20 is formed, and then a third adjustment layer 28 is formed above the first dielectric layer 24 (see FIG. 21). Next, the third adjustment layer 28 and the first dielectric layer 24 are etched to form a third groove 29 (see FIG. 2m). The third groove 29 is separated from the third protective layer 223 by the remaining first dielectric layer 24 so that the third protective layer 223 is not affected during the etching process.

In actual operation, appropriate materials of the first dielectric layer 24 and the third adjustment layer 28 are selected according to the deposition rates of dielectric materials commonly used in semiconductor processes, and the material of the third adjustment layer 28 should be different from that of the first dielectric layer 24. In some specific embodiments, the first dielectric layer 24 can be formed by using ethyl orthosilicate and oxygen as reaction gases, and the third adjustment layer 28 can be formed by using silane and nitrous oxide as reaction gases, using a plasma enhanced chemical vapor deposition (PECVD) process.

Next, a first dielectric layer material is deposited in the third groove 29, wherein the first dielectric layer material includes an air gap 25 (see FIG. 2n);

In actual operation, the first dielectric layer material is deposited in the third groove 29 by using tetraethyl orthosilicate and ozone as reaction gases and using a subatmospheric pressure chemical vapor deposition (SACVD) process. The deposition temperature may be 350° C. to 400° C., including endpoint values, such as 360° C., 370° C., 380° C. or 390° C. The flow ratio of ozone to tetraethyl orthosilicate may be 5 to 20, including endpoint values, such as 8, 10, 15 or 18. Since the third adjustment layer 28 and the first dielectric layer 24 are film layers of different materials formed by different processes, the growth rate of the first dielectric layer material on the sidewall of the third adjustment layer 28 at the upper part of the third groove 29 may be greater than the growth rate of the first dielectric layer material on the sidewall of the first dielectric layer 24 at the lower part of the third groove. Therefore, a seal may be formed in advance above the third groove 29 so that the first dielectric layer material includes an air gap 25.

In the third manufacturing process, taking the case where the top of the conductive structure 20 does not include the fourth protective layer 224 as an example, referring to FIGS. 2o to 2p, firstly, an insulating material is deposited in the second groove 23 to form a spacer material layer. The material of the spacer material layer may include, for example, silicon nitride, silicon carbide or silicon carbonitride. Next, the spacer material layer in the second groove 23 may be etched through the patterned mask layer. Spacers 19 are formed between the structures 20 (see FIG. 2o), and the area between the adjacent conductive structures 20 is subdivided into a plurality of smaller spaced areas by the spacers 19. Then, a first dielectric layer 24 is formed to fill the spaced area in the second groove 23. Since the spaced area is small enough, when the first dielectric layer 24 is formed, air gaps 25 are formed in the material of the first dielectric layer 24 in the spaced area (see FIG. 2p).

It is understandable that only when the area between adjacent conductive structures 20 is separated into sufficiently small interval areas by the spacers 19, when the first dielectric layer 24 is formed, the air gap 25 is formed in the material of the first dielectric layer 24 located in the interval area. In some embodiments, one spacer 19 may be formed between adjacent conductive structures 20. In some other embodiments, when the spacing between adjacent conductive structures 20 is large, multiple spacers 19 may be formed to separate the area between adjacent conductive structures 20 by the spacers 19 into sufficiently small preset interval areas, so as to form the air gap 25 in the material of the first dielectric layer 24 located in the interval area.

The present disclosure also provides a semiconductor structure. Please refer to FIG. 3 for details. As shown in the figure, the semiconductor structure includes:

A substrate 30, and a conductive structure 20 located above the substrate 30;

A third protection layer 223 covering the sidewalls of the conductive structure 20;

The first dielectric layer 24 covers the third protection layer 223 and is located between adjacent conductive structures 20 . The lower surface of the first dielectric layer 24 is lower than the lower surface of the third protection layer 223 .

The lower surface of the first dielectric layer 24 is lower than the lower surface of the third protective layer 223 because the first groove 21 is deepened in order to better remove the conductive material byproducts remaining at the bottom of the first groove 21 in the actual manufacturing process.

The semiconductor structure obtained by the above process can avoid or reduce the problems of leakage or even short circuit caused by the residual conductive material byproducts at the bottom of the first groove 21, thereby ensuring the reliability of the circuit. In addition, the first dielectric layer 24 can be used as an insulating isolation between the conductive structures 20 to avoid or reduce the occurrence of short circuits or other circuit failures. The third protective layer 223 covering the sidewalls of the conductive structure 20 can be used as a barrier layer for the conductive structure 20. For example, when the material of the conductive structure 20 includes a metal material, it can prevent the diffusion of the metal material.

Here, the conductive structure 20 can be used as a word line in the storage area or a metal connection in the peripheral area, or as a contact pad connecting an external structure, such as a node contact plug or a bit line contact, etc. It can be understood that the above is only an example of the use of the conductive structure 20 and is not intended to limit the use of the conductive structure 20.

In actual operation, the material of the conductive structure 20 may include, for example, metal, carbon-containing material or metal nitride, etc., specifically, for example, including but not limited to tungsten, copper, graphene or titanium nitride, etc. The material of the third protective layer 223 may be an insulating material. The material of the third protective layer 223 is an insulating material, which can avoid or reduce the generation of new conductive material byproduct residues during the etching process of the manufacturing process, so that the circuit performance of the semiconductor device will not be adversely affected by the new conductive material byproduct residues. For example, the material of the third protective layer 223 may include but is not limited to one or more of silicon nitride, silicon oxynitride, polymer materials, etc. The dielectric constant of the material of the first dielectric layer 24 is less than or equal to the dielectric constant of the material of the third protective layer 223. The dielectric constant of the material of the first dielectric layer 24 is less than or equal to the dielectric constant of the material of the third protective layer 223, and the low dielectric constant material with a lower dielectric constant as much as possible can effectively reduce the parasitic capacitance between the conductive structures 20, thereby improving the resistance-capacitance (RC) delay to enhance the performance of the semiconductor device. For example, the material of the first dielectric layer 24 may be a dielectric constant (k Low-k dielectric materials with a k value (k value) lower than about 3.0, lower than about 2.5 or lower, include but are not limited to silicon oxide, carbon-based materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) or other silicon-based polymer materials.

In some embodiments, referring to FIG. 3 , a lower surface of the third protection layer 223 is lower than a lower surface of the conductive structure 20 .

The lower surface of the third protective layer 223 is lower than the lower surface of the conductive structure 20 , so that the third protective layer 223 has a better protective effect and a better blocking effect on the conductive structure 20 .

In some embodiments, referring to FIGS. 2 k , 2 n and 2 p , the first dielectric layer 24 includes air gaps 25 , and the air gaps 25 are located between adjacent conductive structures 20 .

The first dielectric layer 24 includes an air gap 25. Because the dielectric constant of air or vacuum is usually significantly lower than the dielectric constant of commonly used dielectric layer materials, for example, the dielectric constant value of commonly used dielectric layer materials with low dielectric constants is generally 2-3, while the dielectric constant value of air is 1. Therefore, the first dielectric layer 24 is combined with the air gap 25 located between adjacent conductive structures 20. The dielectric constant of the dielectric layer between the conductive structures 20 can be further reduced on the basis of making the first dielectric layer 24 have a low dielectric constant. Therefore, the parasitic capacitance between the conductive structures 20 can be further reduced, thereby better improving the resistance-capacitance (RC) delay and further improving the performance of the semiconductor device.

In some embodiments, referring to FIG. 3 , the base 30 includes: a substrate 100 including an active area 101 and an isolation structure 102 defining the active area 101 ; a transistor 103 based on the active area 101 ; a second dielectric layer 104 covering the substrate 100 and the transistor 103 ; wherein the conductive structure 20 penetrates the second dielectric layer 104 and is electrically connected to a source 106 / a drain 107 of the transistor 103 .

The conductive structure 20 penetrating the second dielectric layer 104 can play a role similar to a contact plug to connect the transistor 103 to an external circuit.

In actual operation, the substrate 100 includes, for example, but is not limited to, a single semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (for example, a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate 100 may be doped or undoped, or may include both doped and undoped regions therein. The substrate 100 may also include one or more doped ( ^n- or ^p- ) regions. In a specific embodiment, the substrate 100 includes a doped or undoped silicon substrate. The material of the second dielectric layer 104 may include an insulating material, such as an oxide, a nitride, or a nitride oxide, etc. In some specific embodiments, referring to FIG. 3 , the semiconductor structure further includes an etch stop layer 111 located above the second dielectric layer 104, and the material of the etch stop layer 111 includes, but is not limited to, one or more of silicon nitride, silicon carbide, or silicon carbonitride, etc. In the actual manufacturing process, when the initial conductive layer 110 is etched to form the conductive structure 20 and the first groove 21 located between the conductive structures 20, the bottom of the first groove 21 can stop in the etching stop layer 111, which can ensure that the initial conductive layer 110 is completely cut off without causing excessive impact on the substrate 30, thereby ensuring the stable performance of the semiconductor device.

The embodiments of the present disclosure also provide a memory, which includes the semiconductor structure of any one of the above embodiments.

In actual operation, the memory provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM), but is not limited thereto.

In summary, in the present disclosure, the top of the conductive structure 20 and the first groove 21 are first formed. The protective layer 22 on the inner surface of the conductive structure 20 is formed, and the thickness of the first protective layer 221 located on the top of the conductive structure 20 is greater than the thickness of the second protective layer 222 located at the bottom of the first groove 21. Then, the first protective layer 221 is used as a mask to etch the second protective layer 222 and the bottom surface of the first groove 21, so that the depth of the first groove 21 is increased to form a second groove 23, so as to remove the conductive material byproducts remaining at the bottom of the first groove 21 when the conductive structure 20 is formed. Therefore, leakage or even short circuit problems caused by residual conductive material byproducts can be avoided or reduced. Since the thickness of the first protective layer 221 is greater than the thickness of the second protective layer 222, the first protective layer 221 can protect the conductive structure 20 during the etching process, thereby ensuring the reliability of the circuit and improving the performance of the memory.

It should be noted that the manufacturing method of the semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure can be applied to any integrated circuit including the structure, such as a dynamic random access memory (DRAM). The technical features in the technical solutions described in the embodiments can be combined arbitrarily without conflict.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Industrial Applicability

In the present disclosure, a protective layer is first formed to cover the top of the conductive structure and the inner surface of the first groove, and the thickness of the first protective layer located at the top of the conductive structure is greater than the thickness of the second protective layer located at the bottom of the first groove. Then, the first protective layer is used as a mask to etch the second protective layer and the bottom surface of the first groove, so that the depth of the first groove is increased to form a second groove, so as to remove the conductive material byproducts remaining at the bottom of the first groove when the conductive structure is formed. Therefore, leakage or even short circuit problems caused by residual conductive material byproducts can be avoided or reduced. Since the thickness of the first protective layer is greater than the thickness of the second protective layer, the first protective layer can protect the conductive structure during the etching process, thereby ensuring the reliability of the circuit and improving the performance of the memory.

Claims

A method for manufacturing a semiconductor structure, comprising:

Providing an initial semiconductor structure (10);

forming an initial conductive layer (110) on the initial semiconductor structure (10);

At least etching the initial conductive layer (110) to form conductive structures (20) and first grooves (21) located between the conductive structures (20);

forming a protective layer (22) covering the top of the conductive structure (20) and the inner surface of the first groove (21), wherein the protective layer (22) located at the top of the conductive structure (20) is defined as a first protective layer (221), and the protective layer (22) located at the bottom of the first groove (21) is defined as a second protective layer (222), and the thickness of the first protective layer (221) is greater than the thickness of the second protective layer (222);

Using the first protective layer (221) as a mask, the second protective layer (222) and the bottom surface of the first groove (21) are etched, so that the depth of the first groove (21) is increased, thereby forming a second groove (23).
The method for manufacturing a semiconductor structure according to claim 1, wherein:

Using the first protective layer (221) as a mask, the second protective layer (222) and the bottom surface of the first groove (21) are etched until the first protective layer (221) is removed.
The method for manufacturing a semiconductor structure according to claim 2, wherein:

The protective layer (22) located on the side wall of the first groove (21) is defined as a third protective layer (223); after etching the second protective layer (222) and the bottom surface of the first groove (21), the method further comprises:

forming a first dielectric layer (24), wherein the first dielectric layer (24) fills the second groove (23) and covers the third protective layer (223) and the conductive structure (20);

The first dielectric layer (24) located above the conductive structure (20) is removed to expose the conductive structure (20).
According to the method for manufacturing a semiconductor structure according to claim 1, the second protective layer (222) and the bottom surface of the first groove (21) are etched using the first protective layer (221) as a mask until the first protective layer (221) reaches a preset thickness, and the remaining first protective layer (221) is defined as a fourth protective layer (224).
The method for manufacturing a semiconductor structure according to claim 4, wherein the preset thickness is 3-20 nm.
The method for manufacturing a semiconductor structure according to any one of claims 4 to 5, wherein:

The protective layer (22) located on the side wall of the first groove (21) is defined as a third protective layer (223); after etching the second protective layer (222) and the bottom surface of the first groove (21), the method further comprises:

forming a first dielectric layer (24), wherein the first dielectric layer (24) fills the second groove (23) and covers the third protective layer (223) and the fourth protective layer (224);

The first dielectric layer (24) and the fourth protective layer (224) located above the conductive structure (20) are removed to expose the conductive structure (20).
The method for manufacturing a semiconductor structure according to claim 3 or 6, wherein the dielectric constant of the material of the first dielectric layer (24) is less than or equal to the dielectric constant of the material of the third protective layer (223).
The method for manufacturing a semiconductor structure according to claim 3, 6 or 7, wherein forming the first dielectric layer (24) comprises:

A first dielectric layer material is deposited so that the first dielectric layer (24) material includes an air gap therein, wherein the air gap is located in the second groove (23).
The method for manufacturing a semiconductor structure according to any one of claims 1 to 8, wherein providing the initial semiconductor structure (10) comprises:

Providing a substrate (100);

An active region (101) and an isolation structure (102) defining the active region (101) are formed in the substrate (100);

forming a transistor (103) based on the active region (101);

forming a second dielectric layer (104) covering the substrate (100) and the transistor (103);

Etching the second dielectric layer (104) to form a contact hole (105), wherein the contact hole (105) exposes the source (106) or the drain (107) of the transistor (103);

The initial conductive layer (110) fills the contact hole (105), and a portion of the conductive structure (20) is located in the contact hole (105).
The method for manufacturing a semiconductor structure according to any one of claims 1 to 9, wherein:

The conductive structure (20) comprises a diffusion barrier layer (108) conformally covering the contact hole (105) and a portion of the second dielectric layer (104), and a metal layer (109) covering the diffusion barrier layer (108).
The method for manufacturing a semiconductor structure according to any one of claims 1 to 10, wherein the material of the protective layer (22) is an insulating material.
The method for manufacturing a semiconductor structure according to any one of claims 1 to 11, wherein:

The ratio of the thickness of the first protective layer (221) to the thickness of the second protective layer (222) is 3-5.
A semiconductor structure comprises: a substrate (30), and a conductive structure (20) located above the substrate (30);

a third protective layer (223) covering the side wall of the conductive structure (20);

A first dielectric layer (24) covers the third protective layer (223) and is located between adjacent conductive structures (20), wherein a lower surface of the first dielectric layer (24) is lower than a lower surface of the third protective layer (223).
The semiconductor structure according to claim 13, wherein a lower surface of the third protection layer (223) is lower than a lower surface of the conductive structure (20).
The semiconductor structure according to any one of claims 13-14, wherein the material of the third protective layer (223) is an insulating material.
The semiconductor structure according to any one of claims 13 to 15, wherein the dielectric constant of the material of the first dielectric layer (24) is less than or equal to the dielectric constant of the material of the third protective layer (223).
The semiconductor structure according to any one of claims 13 to 16, wherein the first dielectric The material layer (24) includes air gaps, and the air gaps are located between adjacent conductive structures (20).
The semiconductor structure according to any one of claims 13 to 17, wherein the substrate (30) comprises:

A substrate (100) comprising an active region (101) and an isolation structure (102) defining the active region (101);

A transistor (103) based on the active region (101);

a second dielectric layer (104) covering the substrate (100) and the transistor (103);

The conductive structure (20) penetrates the second dielectric layer (104) and is electrically connected to the source (106)/drain (107) of the transistor (103).
The semiconductor structure according to any one of claims 13 to 18, wherein the conductive structure (20) comprises a diffusion barrier layer (108) and a metal layer (109) covering the diffusion barrier layer (108).
A memory comprising the semiconductor structure according to any one of claims 13 to 19.