CN111933578A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
- Publication number
- CN111933578A CN111933578A CN202011013439.XA CN202011013439A CN111933578A CN 111933578 A CN111933578 A CN 111933578A CN 202011013439 A CN202011013439 A CN 202011013439A CN 111933578 A CN111933578 A CN 111933578A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- interlayer dielectric
- opening
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 342
- 239000011229 interlayer Substances 0.000 claims abstract description 113
- 238000005530 etching Methods 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 38
- 239000011241 protective layer Substances 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 12
- 239000000758 substrate Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Abstract
The invention provides a method for manufacturing a semiconductor structure, which comprises the steps of firstly forming a groove in a hard mask layer on an interlayer dielectric layer, then forming a first opening in the interlayer dielectric layer within the range of the groove, then covering a protective layer, then removing the protective layer on the bottom surface of the groove and the first opening and etching downwards, meanwhile, keeping the protective layer on the side surface, after removing all the protective layer, forming a second opening with a wide upper part and a narrow lower part in the interlayer dielectric layer, and then etching downwards from the second opening to form a through hole which penetrates through the interlayer dielectric layer and exposes a conducting layer on the top part below the through hole. In the method, in the process of forming the second opening, under the protection of the protective layer on the side surface, the side wall of the formed second opening is not easy to enter the lower part of the hard mask layer, so that the interlayer dielectric layer below the hard mask layer is prevented from being removed by etching, and the risk that a subsequently obtained through hole opening enters the lower part of the hard mask layer can be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor structure.
Background
In the Back end of line (BEOL) of an integrated circuit, a plurality of interconnection layers including conductive metal lines are formed on a wafer, and the conductive metal lines on adjacent interconnection layers are connected by columnar metal arranged in an interlayer dielectric layer, so that interconnection inside the integrated circuit is realized. With the development of very large scale integrated circuits, the feature size of the integrated circuit is smaller and smaller, and the delay of Resistance and Capacitance (RC) of interconnections between interconnection layers is significantly increased, which affects the performance of the integrated circuit.
In order to reduce RC delay, the conventional method is generally improved from two aspects, on one hand, the metal wire is replaced by a conventional metal aluminum interconnection wire to a metal copper interconnection wire to reduce the wire resistance R, and on the other hand, a material with a lower dielectric constant (Low-k material) is used as an interlayer dielectric layer to reduce the parasitic capacitance C. With the gradual reduction of the process node, for example, when the process node is reduced to below 40nm, in the above subsequent processes, an Ultra-low K (ULK) material is often used to fabricate an interlayer dielectric layer, which is called an interlayer dielectric layer, and a dual damascene process is used to fabricate a through hole in the interlayer dielectric layer, expose a conductive metal line below the interlayer dielectric layer, and then fill copper in the through hole.
Specifically, when the through hole is formed in the interlayer dielectric layer in the prior art, a groove is formed on the interlayer dielectric layer by using the hard mask layer, a shallow hole is formed at the top of the interlayer dielectric layer from the groove, and then the through hole penetrating through the interlayer dielectric layer is formed by etching downwards on the basis of the whole body of the groove and the shallow hole, wherein the through hole is in a step shape with a wide upper part and a narrow lower part. However, in the prior art, after the via hole is formed in the interlayer dielectric layer, a phenomenon that the via hole in the interlayer dielectric layer is enlarged due to the groove in the mask layer, which is harder in size, is easily generated, that is, the sidewall of the via hole in the interlayer dielectric layer enters below the hard mask layer, and the phenomenon is called a kink defect (as shown by the circle in fig. 6, the ultra-low dielectric constant interlayer dielectric layer 104 at the top of the via hole is retracted toward the lower surface of the hard mask layer 105).
After the through hole is formed, copper is filled in the through hole of the interlayer dielectric layer subsequently, however, the kink defect can affect the filling quality of the through hole, so that the impedance of the through hole is increased and the reliability is reduced easily, the performance of a semiconductor device is affected, and the production yield is reduced. It will be appreciated that the problems with the via etch process described herein may also arise when some interlevel dielectric layers other than ULK are used.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor structure, which aims to avoid the influence on filling quality and reliability caused by the fact that a through hole in an interlayer dielectric layer is too wide.
The manufacturing method of the semiconductor structure provided by the invention comprises the following steps:
the method comprises the following steps: providing a back-end semiconductor structure, wherein the back-end semiconductor structure is provided with a top conducting layer;
step two: sequentially overlapping and forming an interlayer dielectric layer and a hard mask layer on the rear-section semiconductor structure, and forming a groove in the hard mask layer;
step three: performing photoetching and etching processes, and forming a first opening at the position, located in the middle area of the groove, of the interlayer dielectric layer, wherein the side surface of the first opening is connected with the bottom surface of the groove;
step four: forming a protective layer on the back-end semiconductor structure, the protective layer conformally covering the groove and the inner surface of the first opening;
step five: removing part of the protective layer on the bottom surfaces of the groove and the first opening by using an anisotropic etching process, etching downwards, and reserving the protective layer on the side surface of the groove and the side surface of the first opening;
step six: removing the protective layer, and forming a second opening in the interlayer dielectric layer within the range of the bottom surface of the groove, wherein the second opening is in a step shape with a wide upper part and a narrow lower part;
step seven: and etching the interlayer dielectric layer downwards from the second opening by using the hard mask layer as a mask to form a through hole penetrating through the interlayer dielectric layer, wherein the top conductive layer is exposed out of the through hole.
Optionally, the dielectric constant of the interlayer dielectric layer ranges from 2.3 to 2.7.
Optionally, the hard mask layer includes a first dielectric layer, a metal layer, and a second dielectric layer sequentially disposed on the interlayer dielectric layer; in the second step, the bottom surface of the groove formed in the hard mask layer is positioned in the first dielectric layer.
Optionally, the first dielectric layer is a silicon oxide layer formed by TEOS, and the second dielectric layer includes a silicon oxynitride layer located on the metal layer and a pad silicon oxide layer located on the silicon oxynitride layer.
Optionally, in the second step, before forming the interlayer dielectric layer, an etching barrier layer is formed on the back-end semiconductor structure; in the seventh step, the through hole also penetrates through the etching barrier layer.
Optionally, the third step includes:
forming an anti-reflection layer on the back-end semiconductor structure, wherein the anti-reflection layer fills the groove and is provided with a flat upper surface;
forming a photoresist layer on the upper surface of the anti-reflection layer and patterning the photoresist layer to expose part of the anti-reflection layer in the range of the groove;
sequentially etching the anti-reflection layer and the interlayer dielectric layer by taking the patterned photoresist layer as a mask, and forming the first opening in the interlayer dielectric layer; and
and removing the residual photoresist layer and the anti-reflection layer.
Optionally, the depth of the first opening is less than or equal to 1/2 of the thickness of the interlayer dielectric layer.
Optionally, the material of the protective layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride; the thickness of the protective layer is 80-100 angstroms.
Optionally, in the sixth step, the protective layer is removed by using a wet etching process.
Optionally, the distance between the bottom surface of the second opening and the lower surface of the interlayer dielectric layer is 80 nm-100 nm.
In the process of manufacturing the through hole by using the manufacturing method of the semiconductor structure, after the protective layers are formed on the inner surfaces of the groove and the first opening, the protective layers on the bottom surfaces of the groove and the first opening are removed by using an anisotropic etching process and etched downwards, the protective layers on the side surfaces of the groove are remained, then the protective layers are removed, a second opening is formed in the interlayer dielectric layer within the range of the bottom surface of the groove, and then the interlayer dielectric layer is etched downwards from the second opening to form the through hole penetrating through the interlayer dielectric layer. In the manufacturing method, the second opening is formed first and then is further etched downwards, so that a through hole with a wide top and a narrow bottom can be conveniently obtained, the side wall of the second opening is not easy to enter the lower part of the hard mask layer under the protection of the protective layer on the side surface of the groove, the interlayer dielectric layer below the hard mask layer is prevented from being etched and removed, the risk that a through hole orifice formed in the interlayer dielectric layer subsequently enters the lower part of the hard mask layer can be reduced, and the Kink defect can be avoided. Further, through the adjustment the thickness of protective layer can make the second open-ended lateral wall with the lateral wall of recess has certain distance or cuts flatly, can effectively avoid the kink defect.
Drawings
Fig. 1 to 6 are schematic cross-sectional views illustrating a conventional process for forming a via in an interlayer dielectric layer.
Fig. 7 is a schematic cross-sectional view illustrating a via hole formed in an interlayer dielectric layer by a conventional process.
FIG. 8 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 9 to 17 are schematic cross-sectional views illustrating the fabrication of a via hole by using the method for fabricating a semiconductor structure according to an embodiment of the present invention.
The reference numerals of fig. 1 to 7 illustrate: 101-a back-end semiconductor structure; 102-a top conductive layer; 103-a barrier layer; 104-an ultra-low dielectric constant interlayer dielectric layer; 105-a hard mask layer; 105' -a remaining partial thickness of the hard mask layer; 106-a first photoresist layer; 107-an anti-reflection layer; 108-a second photoresist layer; 109-low dielectric constant interlayer dielectric layer; 201-grooves; 202-a first opening; a through hole-203.
The reference numerals of fig. 9 to 17 illustrate: 301-a back-end semiconductor structure; 302-a top conductive layer; 303-a barrier layer; 304-interlayer dielectric layer; 305-a hard mask layer; 315-first dielectric layer; 325-metal layer; 335-a silicon oxynitride layer; 345-pad oxide layer; 306-a photoresist layer; 307-an anti-reflection layer; 308-a photoresist layer; 309-a protective layer; 401-grooves; 401' -groove sidewalls; 402-a first opening; 403-a second opening; 404-through vias.
Detailed Description
The method for fabricating the semiconductor structure according to the present invention is further described in detail with reference to the drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
To facilitate an understanding of the features and advantages of the method of fabricating a semiconductor structure of the present invention, a conventional method of fabricating a semiconductor structure is described below.
Fig. 1 to 6 are schematic cross-sectional views illustrating a conventional process for forming a via in an interlayer dielectric layer. The conventional method for manufacturing a semiconductor structure comprises the following steps:
a) as shown in fig. 1, a back-end semiconductor structure 101 is provided, the back-end semiconductor structure 101 having a top conductive layer 102;
b) sequentially overlapping and forming a barrier layer 103, an ultralow dielectric constant interlayer dielectric layer 104 and a hard mask layer 105 on the back-stage semiconductor structure 101, coating photoresist on the upper surface of the hard mask layer 105, and exposing and developing the photoresist to form a patterned first photoresist layer 106;
c) as shown in fig. 2, the hard mask layer 105 is etched by using the first photoresist layer 106 as a mask to form a groove 201, a bottom surface of the groove 201 is located in the hard mask layer 105, and then the first photoresist layer 106 is removed;
d) as shown in fig. 3, an anti-reflection layer 107 is formed on the back-end semiconductor structure, wherein the anti-reflection layer 107 fills the groove 201 and has a flat upper surface;
e) as shown in fig. 4, forming a second photoresist layer 108 on the upper surface of the anti-reflection layer 107 and patterning the second photoresist layer 108 to expose a portion of the anti-reflection layer 107 within the groove 201;
f) as shown in fig. 5, the anti-reflection layer 107, the remaining hard mask layer 105, and a portion of the ultra-low dielectric constant interlayer dielectric layer 104 are sequentially etched by using the patterned second photoresist layer 108 as a mask, the first opening 202 is formed in the ultra-low dielectric constant interlayer dielectric layer 104, and then the second photoresist layer 108 and the anti-reflection layer 107 are removed;
g) as shown in fig. 6, using the hard mask layer 105 as a mask, the remaining hard mask layer 105, the remaining ultra-low-k interlayer dielectric layer 104, and the barrier layer 103 are etched downward from the trench 201 and the first opening 202 to form a via 203 penetrating through the ultra-low-k interlayer dielectric layer 104, where the via 203 exposes the top conductive layer 102, and in the etching process, the hard mask layer 105 is etched to remove a portion of the thickness of the hard mask layer 105' remaining on the ultra-low-k interlayer dielectric layer 104.
Because the etching removal rate of the ultralow dielectric constant interlayer dielectric layer 104 is higher than that of the hard mask layer 105, the formed through hole 203 easily laterally enters the lower part of the hard mask layer to generate a kink defect, and the depth of the through hole laterally entering the lower part of the hard mask layer even reaches 3 nm-4 nm in severe cases can influence the filling quality of the subsequent through hole 203, so that the impedance of the formed conductive plug is increased, the reliability is reduced, the performance of a semiconductor device is influenced, and the production yield is reduced.
Fig. 7 is a schematic cross-sectional view illustrating a via hole formed in an interlayer dielectric layer by a conventional process. As shown in fig. 7, in order to improve the above-mentioned kink defect, a conventional improvement method is to form a low-K interlayer dielectric layer 109 between the hard mask layer 105 and the ultra-low-K interlayer dielectric layer 104, wherein the dielectric constant (K value) of the low-K interlayer dielectric layer 109 is higher than that of the ultra-low-K interlayer dielectric layer 104, and then etch the hard mask layer 105, the low-K interlayer dielectric layer 109 and the ultra-low-K interlayer dielectric layer 104 to form a through hole 203 penetrating through the low-K interlayer dielectric layer 109 and the ultra-low-K interlayer dielectric layer 104. Under the same etching condition, the larger the K value is, the smaller the rate of lateral etching removal of the interlayer dielectric layer is, so that the depth of the through hole 203 in the figure 7, which laterally enters the lower part of the hard mask layer, is smaller than that in the figure 6, and the kink defect can be improved. Although the method can improve the kink defect, the kink defect still exists, and the filling quality of the subsequent through hole is still influenced, and the impedance and the reliability of the through hole are influenced.
In order to better solve the above problems, the present embodiment provides a method for fabricating a semiconductor structure. FIG. 8 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present invention. As shown in fig. 8, the method of manufacturing the semiconductor device includes:
the method comprises the following steps: providing a back-end semiconductor structure, wherein the back-end semiconductor structure is provided with a top conducting layer;
step two: sequentially overlapping and forming an interlayer dielectric layer and a hard mask layer on the rear-section semiconductor structure, and forming a groove in the hard mask layer;
step three: performing photoetching and etching processes, and forming a first opening at the position, located in the middle area of the groove, of the interlayer dielectric layer, wherein the side surface of the first opening is connected with the bottom surface of the groove;
step four: forming a protective layer on the back-end semiconductor structure, the protective layer conformally covering the groove and the inner surface of the first opening;
step five: removing part of the protective layer on the bottom surfaces of the groove and the first opening by using an anisotropic etching process, etching downwards, and reserving the protective layer on the side surface of the groove and the side surface of the first opening;
step six: removing the protective layer to form a second opening in the interlayer dielectric layer within the range of the bottom surface of the groove, wherein the second opening is in a step shape with a wide upper part and a narrow lower part;
step seven: and etching the interlayer dielectric layer downwards from the second opening by using the hard mask layer as a mask to form a through hole penetrating through the interlayer dielectric layer, wherein the top conductive layer is exposed out of the through hole.
In the process of manufacturing the through hole by using the manufacturing method of the semiconductor structure, the second opening is formed firstly and then is further etched downwards, so that the through hole with a wide upper part and a narrow lower part can be conveniently obtained; in the process of forming the second opening, due to the influence of etching, although the side wall of the second opening may slightly enter below the side surface protection layer to form a lateral recess, under the protection of the groove side surface protection layer, the lateral recess (or the side wall of the second opening) is not easy to laterally enter below the hard mask layer, and after the side surface protection layer is removed, the lateral recess is eliminated because the upper protection layer is removed, so that the protection layer has little influence on the size of a through hole formed in a subsequent interlayer dielectric layer, and is also favorable for avoiding the interlayer dielectric layer below the hard mask layer from being removed by etching, so that a through hole orifice is not easy to laterally enter below the hard mask layer, that is, the generation of a Kink defect can be avoided, the filling quality of a conductive plug obtained by subsequently filling the through hole is favorable for improving, the impedance of the conductive plug is reduced, and the reliability is improved, and thus the performance of the semiconductor device can be improved.
Fig. 9 to 17 are schematic cross-sectional views illustrating the fabrication of a via hole by using the method for fabricating a semiconductor structure according to an embodiment of the present invention. The following describes a method for fabricating the semiconductor structure according to this embodiment with reference to fig. 9 to 17.
As shown in fig. 9, in the first step, the back-end semiconductor structure 301 has a top conductive layer 302. The top conductive layer 302 may be a metallic conductive material, such as copper metal or aluminum metal. In another embodiment, the top conductive layer may be doped polysilicon or other material.
In this embodiment, the back-end semiconductor structure 301 may include a silicon substrate, and various semiconductor devices may be formed in the silicon substrate. In another embodiment, the Silicon substrate may be replaced with a Germanium substrate, a Silicon Germanium substrate, a SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like.
And step two, sequentially forming an interlayer dielectric layer 304 and a hard mask layer 305 on the back-end semiconductor structure 301 in an overlapping manner, and forming a groove 401 in the hard mask layer 305.
The method specifically comprises the following steps:
s1: as shown in fig. 9, an interlayer dielectric layer 304 and a hard mask layer 305 are sequentially formed on the back-end semiconductor structure 301;
s2: forming a photoresist layer 306 on the upper surface of the hard mask layer 305, and exposing and developing the photoresist layer 306 to expose a portion of the upper surface of the hard mask layer 305;
s3: as shown in fig. 10, the patterned photoresist layer 306 is used as a mask to etch the hard mask layer 305, and a groove 401 is formed in the hard mask layer 305;
s4: the photoresist layer 306 is removed.
In step S1, before the interlayer dielectric layer 304 is formed, a barrier layer 303 may be formed on the back-end semiconductor structure 301, that is, the barrier layer 303 is formed between the surface of the back-end semiconductor structure 301 and the interlayer dielectric layer 304, and the barrier layer 303 may protect the underlying top conductive layer 302, so as to prevent the top conductive layer 302 from being exposed prematurely during the process of forming a via hole by etching, which may affect the conductive performance of the top conductive layer.
In order to reduce the parasitic capacitance C of the interlayer dielectric layer and improve the delay of the interconnect resistance capacitance between the interconnect layers, in this embodiment, the interlayer dielectric layer 304 may be a Low dielectric constant (Low K) material, for example, the interlayer dielectric layer 304 may be silicon fluoride (SiF), silicon oxycarbide (SiOC), parylene or xerogel. And the lower the dielectric constant of the interlayer dielectric layer is, the larger the etching selection ratio of the interlayer dielectric layer to the hard mask layer is, the parasitic capacitance of the interlayer dielectric layer and the etching selection ratio of the interlayer dielectric layer to the hard mask layer are comprehensively considered, and the dielectric constant range of the interlayer dielectric layer 304 is preferably 2.3-2.7. In this embodiment, the original thickness of the interlayer dielectric layer 304 may be 280nm to 310 nm.
The hard mask layer 305 may include a first dielectric layer 315, a metal layer 325, and a second dielectric layer sequentially disposed on the interlayer dielectric layer 304; the first dielectric layer 315 may be a silicon oxide layer formed by TEOS, and the second dielectric layer may include a silicon oxynitride layer (SiON) 335 on the metal layer 325 and a pad silicon oxide layer 345 on the silicon oxynitride layer 335; the metal layer 325 layer may be metallic titanium or titanium nitride (TiN).
Referring to fig. 10, the bottom surface of the recess 401 may be located in the first dielectric layer 315 to protect the interlayer dielectric layer 304 under the first dielectric layer 315. In another embodiment, the bottom surface of the groove may also be located right on the upper surface of the interlayer dielectric layer.
In the step S2, the silicon oxynitride layer 335 may be used as an anti-reflection layer during an exposure process, so as to effectively improve the problems of line deformation and surface roughness increase of the patterned photoresist layer caused by light reflection, standing wave and other factors in the photolithography process, and improve the etching accuracy of the pad oxide layer 345 on the silicon oxynitride layer 335.
Next, a third step is performed, that is, as shown in fig. 11 to 13, a photolithography and etching process is performed, a first opening 402 is formed at a position of the interlayer dielectric layer 304, which is located in the middle region of the groove 401, and a side surface of the first opening 402 is connected to the bottom surface of the groove 401.
Specifically, as shown in fig. 11, an anti-reflection layer 307 is formed on the back-end semiconductor structure 301, wherein the anti-reflection layer 307 fills the groove 401 and has a flat upper surface. The anti-reflection layer 307 may be a liquid polymer (polymer) having an anti-reflection function, and the anti-reflection layer 307 may be formed by a spin Coating process (Coating).
As shown in fig. 12, a photoresist layer 308 is formed on the upper surface of the anti-reflection layer 307 and the photoresist layer 308 is patterned to expose a portion of the anti-reflection layer 307 within the groove 401.
As shown in fig. 13, the patterned photoresist layer 308 is used as a mask to sequentially etch the anti-reflection layer 307 and the interlayer dielectric layer 304, form the first opening 402 in the interlayer dielectric layer 304, and remove the remaining photoresist layer 308 and the anti-reflection layer 307.
When the bottom surface of the groove 401 is located in the first dielectric layer 315, the etching to form the first opening 402 further includes etching the remaining first dielectric layer 315 at the bottom of the groove 402; in the thickness direction of the back-end semiconductor structure 301, the depth of the first opening 402 may be less than or equal to 1/2 of the thickness of the interlayer dielectric layer 304, or may be slightly greater than 1/2 of the thickness of the interlayer dielectric layer 304, that is, a certain thickness of the interlayer dielectric layer 304 may remain under the first opening 402, so that a subsequent etching process may have a sufficient operation space (window), for example, the depth of the first opening 402 may be 140nm to 160nm, and the distance between the bottom surface of the first opening 402 and the lower surface of the interlayer dielectric layer 304 may be greater than 100 nm.
As shown in fig. 14, a fourth step is performed to form a protection layer 309 on the back-end semiconductor structure 301, where the protection layer 309 conformally covers the inner surfaces of the groove 401 and the first opening 402, and the protection layer 309 may also cover the upper surface of the hard mask layer 305, so as to serve as a sacrificial layer to protect the hard mask layer 305 in a subsequent etching process.
The material of the protection layer 309 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, the thickness of the protection layer 309 may be 80 angstroms to 100 angstroms, and the thickness of the protection layer may also be set according to the size of a through hole to be formed; the protective layer 309 may be formed using an atomic layer deposition process (ALD) to improve uniformity of the protective layer. In another embodiment, the protective layer may also be formed by a Chemical Vapor Deposition (CVD) process.
As shown in fig. 15, step five is performed, and by using an anisotropic etching process, a portion of the protection layer 309 on the bottom surfaces of the groove 401 and the first opening 402 is removed and etched downward, and the protection layer 309 on the side surfaces of the groove 401 and the first opening 402 may remain.
As shown in fig. 16, step six is performed to remove the protection layer 309, so that a second opening 403 is formed in the interlayer dielectric layer 304 within the bottom surface of the groove 401, and the second opening 403 is in a step shape with a wide top and a narrow bottom.
Wherein, by adjusting the thickness of the protection layer 309, the distance between the sidewall of the upper portion of the second opening 403 and the sidewall of the recess can be adjusted. Specifically, as shown in fig. 15 and fig. 16, due to the influence of etching, the sidewall of the formed second opening 403 may slightly enter below the protection layer of the groove sidewall 401 'to form a lateral recess, but when the protection layer 309 is set to be thicker, the lateral recess does not easily enter below the hard mask layer 305, that is, a certain distance may be provided between the sidewall of the upper portion of the second opening 403 and the groove sidewall 401', and the residual thickness of the interlayer dielectric layer 304 in the bottom surface of the groove 401 increases the allowance of subsequent lateral etching; when the thickness of the protection layer is set to be just equal to the width of the lateral recess, the sidewall of the upper portion of the second opening 403 may be cut flat with the groove sidewall 401'. The sidewall of the upper portion of the second opening 403 is spaced from or flattened against the sidewall 401' of the recess to help prevent the subsequently formed via opening from entering under the hard mask layer 305, i.e., to avoid the kid defect. Moreover, after the protective layer 309 is removed, the above-mentioned lateral recess is opened, i.e., the lateral recess is eliminated, and the size and filling quality of the subsequently formed through hole are not greatly affected.
In this embodiment, the protective layer 309 may be removed by a wet etching process, and the liquid medicine used in the wet etching process may be phosphoric acid (H)3PO4). The bottom surface of the second opening 403 and the lower surface of the interlayer dielectric layer 304 may have a certain distance, that is, the interlayer dielectric layer below the second opening may have a certain thickness, so that the subsequent overall etching may be performed to make the through hole reach a required size, but the remaining thickness of the interlayer dielectric layer 304 may not be too large, so as to prevent the subsequent overall etching from exhausting the interlayer dielectric layer between the sidewall of the upper portion of the second opening 403 and the sidewall of the groove 401, which may cause the formed through hole to laterally enter the lower portion of the hard mask layer to generate a kink defect, preferably, the distance between the bottom surface of the second opening 403 and the lower surface of the interlayer dielectric layer 304 may be 80nm to 100 nm.
Next, as shown in fig. 17, step seven is performed, and the interlayer dielectric layer 304 and the barrier layer 303 are etched downward from the second opening 403 by using the hard mask layer 305 as a mask to form a via hole 404 penetrating through the interlayer dielectric layer 304, where the via hole 404 exposes the top conductive layer 302. During the etching process, the hard mask layer 305 is also consumed, the pad oxide layer 345 and the silicon oxynitride layer 335 on the hard mask layer 305 may be removed during the etching process, and when the etching process is stopped, the hard mask layer 305 may leave the metal layer 325 and the silicon oxide layer 315.
In step seven, after the protection layer 309 is removed, the interlayer dielectric layer 304 is integrally etched by using the hard mask layer 305 as a mask, so that the size of the formed through hole 404 can meet the requirement.
After forming the through hole 404, the method for manufacturing the semiconductor structure may further include: depositing a diffusion barrier layer on the inner surface of the through hole 404; and filling a conductive material into the through hole and carrying out planarization treatment to form a conductive plug. The diffusion barrier layer may prevent the layer of conductive material from diffusing into the material of the via sidewall.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (9)
1. A method for fabricating a semiconductor structure, comprising:
the method comprises the following steps: providing a back-end semiconductor structure, wherein the back-end semiconductor structure is provided with a top conducting layer;
step two: sequentially overlapping and forming an interlayer dielectric layer and a hard mask layer on the rear-section semiconductor structure, and forming a groove in the hard mask layer, wherein the dielectric constant of the interlayer dielectric layer ranges from 2.3 to 2.7;
step three: performing photoetching and etching processes, and forming a first opening at the position, located in the middle area of the groove, of the interlayer dielectric layer, wherein the side surface of the first opening is connected with the bottom surface of the groove;
step four: forming a protective layer on the back-end semiconductor structure, the protective layer conformally covering the groove and the inner surface of the first opening;
step five: removing part of the protective layer on the bottom surfaces of the groove and the first opening by using an anisotropic etching process, etching downwards, and reserving the protective layer on the side surface of the groove and the side surface of the first opening;
step six: removing the protective layer to form a second opening in the interlayer dielectric layer within the range of the bottom surface of the groove, wherein the second opening is in a step shape with a wide upper part and a narrow lower part;
step seven: and etching the interlayer dielectric layer downwards from the second opening by using the hard mask layer as a mask to form a through hole penetrating through the interlayer dielectric layer, wherein the top conductive layer is exposed out of the through hole.
2. The method of fabricating a semiconductor structure according to claim 1, wherein the hard mask layer comprises a first dielectric layer, a metal layer, and a second dielectric layer sequentially disposed on the interlayer dielectric layer; in the second step, the bottom surface of the groove formed in the hard mask layer is positioned in the first dielectric layer.
3. The method of fabricating a semiconductor structure according to claim 2, wherein the first dielectric layer is a silicon oxide layer formed by TEOS, and the second dielectric layer includes a silicon oxynitride layer on the metal layer and a pad silicon oxide layer on the silicon oxynitride layer.
4. The method for fabricating a semiconductor structure according to claim 1, wherein in the second step, an etching stop layer is formed on the back-end semiconductor structure before the interlayer dielectric layer is formed; in the seventh step, the through hole also penetrates through the etching barrier layer.
5. The method of fabricating a semiconductor structure according to claim 1, wherein the third step comprises:
forming an anti-reflection layer on the back-end semiconductor structure, wherein the anti-reflection layer fills the groove and is provided with a flat upper surface;
forming a photoresist layer on the upper surface of the anti-reflection layer and patterning the photoresist layer to expose part of the anti-reflection layer in the range of the groove;
sequentially etching the anti-reflection layer and the interlayer dielectric layer by taking the patterned photoresist layer as a mask, and forming the first opening in the interlayer dielectric layer; and
and removing the residual photoresist layer and the anti-reflection layer.
6. The method of claim 1, wherein a depth of said first opening is less than or equal to 1/2 a thickness of said interlayer dielectric layer.
7. The method of claim 1, wherein the material of the protective layer comprises at least one of silicon nitride, silicon oxide, and silicon oxynitride; the thickness of the protective layer is 80-100 angstroms.
8. The method for fabricating a semiconductor structure according to claim 7, wherein in the sixth step, the protective layer is removed by a wet etching process.
9. The method of claim 1, wherein a distance between a bottom surface of the second opening and a lower surface of the interlayer dielectric layer is 80nm to 100 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011013439.XA CN111933578B (en) | 2020-09-24 | 2020-09-24 | Method for manufacturing semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011013439.XA CN111933578B (en) | 2020-09-24 | 2020-09-24 | Method for manufacturing semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111933578A true CN111933578A (en) | 2020-11-13 |
| CN111933578B CN111933578B (en) | 2021-01-01 |
Family
ID=73334149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011013439.XA Active CN111933578B (en) | 2020-09-24 | 2020-09-24 | Method for manufacturing semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111933578B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021631A1 (en) * | 2022-07-26 | 2024-02-01 | 华进半导体封装先导技术研发中心有限公司 | Through-silicon-via structure and manufacturing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881583A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving defects in dual damascene process |
| CN102881639A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving KINK defect in dual damascene process |
| CN102881641A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving etched via bottom critical dimension of 40 nm dual damascene structure |
-
2020
- 2020-09-24 CN CN202011013439.XA patent/CN111933578B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881583A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving defects in dual damascene process |
| CN102881639A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving KINK defect in dual damascene process |
| CN102881641A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving etched via bottom critical dimension of 40 nm dual damascene structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021631A1 (en) * | 2022-07-26 | 2024-02-01 | 华进半导体封装先导技术研发中心有限公司 | Through-silicon-via structure and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111933578B (en) | 2021-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8860225B2 (en) | Devices formed with dual damascene process | |
| US6696222B2 (en) | Dual damascene process using metal hard mask | |
| US6744090B2 (en) | Damascene capacitor formed in metal interconnection layer | |
| TWI610343B (en) | Semiconductor structure having tapered damascene aperture and method of the same | |
| TWI579962B (en) | A technique for increasing adhesion of metallization layers by providing dummy vias | |
| TWI497591B (en) | Structure and method for manufacturing interconnect structures having self-aligned dielectric caps | |
| US9966309B2 (en) | Contact plug without seam hole and methods of forming the same | |
| US20070128847A1 (en) | Semiconductor device and a method for manufacturing the same | |
| US11594419B2 (en) | Reduction of line wiggling | |
| KR20020045657A (en) | Metal contact structure in semiconductor device and forming method thereof | |
| CN112151608B (en) | Semiconductor structure and forming method thereof | |
| US20180130660A1 (en) | Semiconductor device having interconnect structure | |
| CN104347488B (en) | The forming method of interconnection structure | |
| US9431292B1 (en) | Alternate dual damascene method for forming interconnects | |
| CN111933578B (en) | Method for manufacturing semiconductor structure | |
| US20090286396A1 (en) | Method for manufacturing a semiconductor device having a stepped through-hole | |
| US20120270403A1 (en) | Method of fabricating openings | |
| US20030222349A1 (en) | Semiconductor device with multilayer interconnection structure | |
| CN112435983A (en) | Metal internal connection structure and its making method | |
| US20210384072A1 (en) | Semiconductor structure and forming method thereof | |
| US20050142861A1 (en) | Method of forming an interconnection line in a semiconductor device | |
| CN111211095A (en) | Method for manufacturing conductive interconnection line | |
| US7112537B2 (en) | Method of fabricating interconnection structure of semiconductor device | |
| US9859208B1 (en) | Bottom self-aligned via | |
| TWI803209B (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240321 Address after: 230012 No.88, xifeihe Road, Hefei comprehensive free trade zone, Xinzhan District, Hefei City, Anhui Province Patentee after: Hefei crystal integrated circuit Co.,Ltd. Country or region after: Zhong Guo Address before: No.18-h1105, Yinchun Road, science and technology R & D base, Maigaoqiao entrepreneurship Park, Qixia District, Nanjing, Jiangsu Province, 210046 Patentee before: Nanjing crystal drive integrated circuit Co.,Ltd. Country or region before: Zhong Guo |