WO2024098672A1 - Structure semi-conductrice et son procédé de fabrication - Google Patents

Structure semi-conductrice et son procédé de fabrication Download PDF

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Publication number
WO2024098672A1
WO2024098672A1 PCT/CN2023/089517 CN2023089517W WO2024098672A1 WO 2024098672 A1 WO2024098672 A1 WO 2024098672A1 CN 2023089517 W CN2023089517 W CN 2023089517W WO 2024098672 A1 WO2024098672 A1 WO 2024098672A1
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WIPO (PCT)
Prior art keywords
conductive layer
substrate
layer
projection area
size
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PCT/CN2023/089517
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English (en)
Chinese (zh)
Inventor
曹新满
吴耆贤
黄炜
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长鑫存储技术有限公司
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Publication of WO2024098672A1 publication Critical patent/WO2024098672A1/fr

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  • the embodiments of the present disclosure relate to, but are not limited to, a semiconductor structure and a method for manufacturing the same.
  • DRAM Dynamic Random Access Memory
  • the active area cannot be fully exposed when a storage node contact is subsequently formed between adjacent bit lines, resulting in a relatively small contact area between the storage node contact and the active area and a relatively large read/write resistance.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.
  • an embodiment of the present disclosure provides a semiconductor structure, including:
  • bit lines are disposed on the substrate, wherein the bit lines include a first conductive layer and a second conductive layer located on the first conductive layer;
  • the first conductive layer includes a first portion and a second portion located below the first portion, and a projection area of the second portion on the substrate is within a projection area of the first portion on the substrate.
  • a projection area of the second conductive layer on the substrate is within a projection area of the first portion on the substrate.
  • a projection area of the second conductive layer on the substrate is within a projection area of the second portion on the substrate.
  • a minimum dimension of the second portion is greater than or equal to a dimension of the second conductive layer.
  • the maximum dimension of the second portion is larger than a dimension of the second conductive layer and smaller than or equal to a maximum dimension of the first portion.
  • the bit lines include first bit lines and second bit lines that are alternately arranged.
  • the first bit line is located on a bit line contact plug, and the bit line contact plug extends into the substrate.
  • the second bit line is located on a first insulating layer, and the first insulating layer is located on the substrate.
  • a projection area of the first insulating layer on the substrate is within a projection area of the first conductive layer on the substrate.
  • a maximum dimension of the first insulating layer is smaller than a maximum dimension of the first portion and larger than a dimension of the second conductive layer.
  • a minimum dimension of the first insulating layer is equal to a minimum dimension of the first conductive layer.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
  • bit lines include a first conductive layer and a second conductive layer located on the first conductive layer;
  • the first conductive layer includes a first portion and a second portion located below the first portion, and a projection area of the second portion on the substrate is within a projection area of the first portion on the substrate.
  • the method before forming the bit line, the method further includes:
  • a bit line contact plug is formed in the trench, and the bit line contact plug is coplanar with the first insulating layer.
  • the step of forming the bit line includes:
  • first initial conductive layer on the substrate, wherein the first initial conductive layer covers the first insulating layer and the bit line contact plug;
  • the second initial conductive layer and the first initial conductive layer are etched to form the second conductive layer and the first conductive layer, respectively.
  • a projection area of the second conductive layer on the substrate is within a projection area of the first conductive layer on the substrate.
  • the method further comprises:
  • barrier layer on the sidewall of the second conductive layer, wherein the barrier layer covers a portion of the first conductive layer
  • the portion of the first conductive layer covered by the barrier layer forms the first portion, and the portion of the first conductive layer below the first portion forms the second portion.
  • the first insulating layer when etching the first initial conductive layer, is also etched;
  • a projection area of the first conductive layer on the substrate is within a projection area of the first insulating layer on the substrate.
  • the method further includes:
  • the first insulating layer continues to be etched, wherein a projection area of the first insulating layer on the substrate is within a projection area of the first conductive layer on the substrate.
  • a minimum dimension of the first insulating layer is equal to a dimension of the second conductive layer.
  • the method further comprises:
  • the bit line contact plug is etched.
  • the first conductive layer includes a titanium nitride layer; the second conductive layer includes a tungsten layer; the first insulating layer includes a silicon nitride layer; the bit line contact plug includes a polysilicon layer; and the barrier layer includes a silicon oxide layer.
  • the semiconductor structure comprises: a plurality of bit lines arranged on a substrate, wherein the bit lines comprise a first conductive layer and a second conductive layer located on the first conductive layer; wherein the first conductive layer comprises a first portion and a second portion located below the first portion. Since the projection area of the second portion of the first conductive layer on the substrate is within the projection area of the first portion on the substrate, the first conductive layer can be reduced.
  • the contact area between the layer and the substrate is conducive to etching the substrate, so that when a storage node contact is formed between adjacent bit lines, the active area can be fully exposed, thereby increasing the contact area between the storage node and the active area and reducing the read and write resistance.
  • FIG1 is a schematic diagram of a process of manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIGS 2 to 17 are schematic diagrams of structures during the manufacturing process of the semiconductor structure provided by the embodiments of the present disclosure.
  • first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
  • the three directions may include the X-axis, Y-axis, and Z-axis directions.
  • the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side.
  • the direction intersecting for example, perpendicular
  • the top surface and the bottom surface of the substrate is defined as the third direction.
  • two directions intersecting for example, perpendicular to each other are defined.
  • the arrangement direction of the bit lines can be defined as the first direction
  • the extension direction of the bit lines can be defined as the second direction.
  • the plane direction of the substrate can be determined based on the first direction and the second direction.
  • the first direction, the second direction and the third direction can be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • FIG. 1 is a flow chart of the method for manufacturing a semiconductor structure provided by the present disclosure.
  • FIG. 2 to FIG. 17 are schematic diagrams of structures during the manufacturing process of the semiconductor structure provided by the present disclosure. As shown in FIG. 1 to FIG. 17, the method for manufacturing a semiconductor structure includes the following steps:
  • Step S101 providing a substrate.
  • the base at least includes a substrate 10; the substrate 10 may be a silicon substrate, and the substrate 10 may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.
  • germanium germanium
  • GaAs gallium arsenide
  • the substrate 10 further includes a plurality of active regions 101 and shallow trench isolation structures 102 between the active regions 101, and the active regions 101 and the shallow trench isolation structures 102 are alternately arranged along a first direction.
  • the shallow trench isolation structures 102 are used to isolate two active regions 101 adjacent to each other along the first direction, and it can also be understood that the active regions 101 are defined by the shallow trench isolation structures 102.
  • the substrate may further include other functional structures, for example, a buried word line structure.
  • bit lines are formed on the substrate, wherein the bit lines include a first conductive layer 14 and a second conductive layer 15 located on the first conductive layer 14; wherein the first conductive layer 14 includes a first portion 141 and a second portion 142 located below the first portion 141, and a projection area of the second portion 142 on the substrate is within a projection area of the first portion 141 on the substrate.
  • a plurality of bit lines are arranged at intervals on the substrate, and the bit lines are located on the surface of the active area 101 and the shallow trench isolation structure 102.
  • the bit line includes a first conductive layer 14 and a second conductive layer 15 located on the first conductive layer 14, wherein the first conductive layer 14 may be a titanium nitride layer, and the second conductive layer 15 may be a tungsten layer.
  • the materials of the first conductive layer 14 and the second conductive layer 15 may also be other suitable conductive materials, such as cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), polysilicon or any combination thereof.
  • the first conductive layer 14 includes a first portion 141 and a second portion 142 located below the first portion 141, which are sequentially arranged along the third direction, and the top surface of the first portion 141 is in contact with the second conductive layer 15.
  • the projection area of the second portion 142 on the substrate is within the projection area of the first portion 141 on the substrate, that is, the size of the second portion 142 is smaller than the size of the first portion 141.
  • the size of the second part 142 is smaller than the size of the first part 141, which means that the size of the second part 142 in the first direction is smaller than the size of the first part 141 in the first direction, or the maximum projection area of the second part 142 on the plane where the substrate is located is smaller than the maximum projection area of the first part 141 on the plane where the substrate is located.
  • the projection area of the second part 142 on the substrate is within the projection area of the first part 141 on the substrate, which can reduce the contact area between the second part 142 and the substrate, thereby facilitating the etching of the substrate.
  • the active area can be fully exposed, thereby increasing the contact area between the storage node and the active area and reducing the read and write resistance.
  • the base includes a substrate 10; the substrate 10 includes active areas 101 and shallow trench isolation structures 102 alternately arranged along the X-axis direction.
  • the shallow trench isolation structure 102 is filled with isolation material, and due to process reasons, the isolation material is usually also formed on the surface of the active area 101. As shown in FIG2 , there is also some isolation material on the surface of the active area 101.
  • the manufacturing process of the semiconductor structure may further include the following steps: forming a first insulating layer 11 on the substrate; etching the first insulating layer 11 and the substrate to form a plurality of grooves 12 on the substrate; forming a bit line contact plug 13 in the groove 12, and the bit line contact plug 13 is coplanar with the first insulating layer 11.
  • a first insulating layer 11 is formed on the surface of a base (e.g., a substrate 10), and the first insulating layer 11 and the base (i.e., the active area 101 and the shallow trench isolation structure 102) are etched to form an etched groove 12.
  • a first photoresist layer (not shown) having a first preset pattern can be formed on the surface of the first insulating layer 11; the first preset pattern exposes the first insulating layer 11 located on the surface of the active area 101 and a portion of the shallow trench isolation structure 102; the exposed first insulating layer 11, the active area 101 and a portion of the shallow trench isolation structure 102 located under the first insulating layer 11 are etched and removed through the first photoresist layer to form a trench 12.
  • the dimension h1 of the trench 12 in the X-axis direction is larger than the dimension h2 of the active area 101 under the trench 12 in the X-axis direction.
  • the electrical connection area between the active area and the subsequently formed bit line contact plug can be larger.
  • the first insulating layer 11 may be a silicon oxide layer, and the first insulating layer 11 is used to isolate the active area 101 from other functional structures located on the surface of the substrate 10, for example, isolating the active area 101 from the conductive structure on the surface of the substrate 10 (such as a bit line or a storage node contact).
  • the method for manufacturing the semiconductor structure further includes a step of removing the first photoresist layer.
  • the first photoresist layer may be removed by dry or wet etching technology.
  • bit line contact material is filled in the trench 12 to form a bit line contact plug 13.
  • bit line contact plug 13 is coplanar with the first insulating layer 11, that is, the top surface of the bit line contact plug 13 is flush with the top surface of the first insulating layer 11.
  • the bit line contact material can be any material with good conductivity, such as polysilicon.
  • the step of forming the bit line may include: forming a first initial conductive layer 14a on the substrate, the first initial conductive layer 14a covering the first insulating layer 11 and the bit line contact plug 13; forming a second initial conductive layer 15a on the first initial conductive layer 14a; etching the second initial conductive layer 15a and the first initial conductive layer 14a to respectively form a second conductive layer 15 and a first conductive layer 14.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the first conductive layer 14 on the substrate.
  • a first conductive material is deposited on the surface of the substrate (i.e., the first insulating layer 11 and the bit line contact plug 13) to form a first initial conductive layer 14a covering the first insulating layer 11 and the bit line contact plug 13.
  • a second conductive material is deposited on the surface of the first initial conductive layer 14a to form a second initial conductive layer 15a.
  • the first initial conductive layer 14a and the second initial conductive layer 15a may be formed by any of the following deposition processes: chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin coating process, coating process or thin film process, etc.
  • the first conductive material and the second conductive material may be tungsten, cobalt, copper, aluminum, nickel, titanium nitride, etc.
  • the first initial conductive layer 14a may be a titanium nitride layer
  • the second initial conductive layer 15a may be a tungsten layer.
  • the method for manufacturing the semiconductor structure further includes: depositing a second insulating material on the surface of the second initial conductive layer 15a to form an initial bit line insulating layer 16a.
  • the second insulating material may be silicon oxide, silicon nitride or silicon oxynitride.
  • the second initial conductive layer 15a and the first initial conductive layer 14a are sequentially etched to form the first The second conductive layer 15 and the first conductive layer 14.
  • a second photoresist layer (not shown) having a second preset pattern may be formed on the surface of the second initial conductive layer 15a, and the second preset pattern exposes a portion of the second initial conductive layer 15a; the exposed second initial conductive layer 15a and the first initial conductive layer 14a located under the second initial conductive layer 15a are etched and removed through the second photoresist layer to form the second conductive layer 15 and the first conductive layer 14.
  • the initial bit line insulating layer 16 a is also etched to correspondingly form a bit line insulating layer 16 located on the surface of the second conductive layer 15 .
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the first conductive layer 14 on the substrate, that is, the dimension d1 of the second conductive layer 15 in the X-axis direction is less than or equal to the minimum dimension d2 of the first conductive layer 14 in the X-axis direction, or, the projection area of the second conductive layer 15 in the XY plane is smaller than the projection area of the first conductive layer 14 in the XY plane.
  • the first insulating layer 11 is also etched. Since the etching selectivity of the first insulating layer 11 is relatively low relative to the first initial conductive layer 14a, the size of the first insulating layer 11 in the X-axis direction will be larger, that is, the projection area of the first conductive layer 14 on the substrate is within the projection area of the first insulating layer 11 on the substrate. In addition, due to the blocking effect of the first insulating layer 11 during the etching process, the formed first conductive layer 14 cannot have a straight contour line.
  • the projection area of the first conductive layer 14 on the substrate is within the projection area of the first insulating layer 11 on the substrate, that is, the maximum dimension d3 of the first conductive layer 14 in the X-axis direction is less than or equal to the minimum dimension d4 of the first insulating layer 11 in the X-axis direction, or, the maximum projection area of the first conductive layer 14 in the XY plane is less than or equal to the minimum projection area of the first insulating layer 11 in the XY plane.
  • bit line contact plug 13 located between the first insulating layers 11 is also etched, so that the bit line contact plug 13 has a shape as shown in the elliptical dotted box in Figure 5.
  • the bit line contact plug 13 includes an etched portion a and an unetched portion b; wherein the etched portion a and the unetched portion b are both trapezoidal, and the maximum size of the etched portion a is smaller than the minimum size of the unetched portion b; the size of the top of the etched portion a is smaller than the size of the bottom of the etched portion a, and the size of the top of the unetched portion b is larger than the size of the bottom of the unetched portion b.
  • the method for manufacturing the semiconductor structure may further include the following steps: forming a barrier layer 17 on the side wall of the second conductive layer 15, and the barrier layer 17 covers a portion of the first conductive layer 14; etching the first conductive layer 14; wherein the portion of the first conductive layer 14 covered by the barrier layer 17 forms a first portion 141, and the portion of the first conductive layer 14 located below the first portion 141 forms a second portion 142.
  • barrier layer 17 includes a silicon oxide layer.
  • a barrier layer 17 is formed on the sidewalls of the second conductive layer 15.
  • a barrier material may be deposited on the substrate surface, the sidewalls of the first insulating layer 11, the sidewalls of the first conductive layer 14, the sidewalls of the second conductive layer 15, and the sidewalls and surface of the bit line insulating layer 16 to form an initial barrier layer (not shown), and the initial barrier layer located on the substrate surface, the sidewalls of the first insulating layer 11, part of the sidewalls of the first conductive layer 14, and the top surface of the bit line insulating layer 16 is removed by etching to expose the sidewalls of the first insulating layer 11 and part of the first conductive layer 14 to form a barrier layer 17. That is, the barrier layer 17 in the embodiment of the present disclosure covers part of the first conductive layer 14.
  • the thickness of the barrier layer 17 can be 1 nanometer (nm) to 1.5 nm, for example, 1.2 nm.
  • the barrier layer 17 can be formed by dry etching technology. Due to the anisotropic etching characteristics of dry etching, the initial barrier layer at the bottom and the bevel position is removed, leaving the initial barrier layer on the side wall, and the remaining initial barrier layer is also located at the upper position of the first conductive layer (for example, titanium nitride), so as to prevent excessive etching at the interface between the first conductive layer and the second conductive layer (for example, tungsten) during the subsequent wet etching of the first conductive layer, resulting in a smaller contact area between the first conductive layer and the second conductive layer and an increased contact resistance.
  • first conductive layer for example, titanium nitride
  • the first conductive layer 14 is etched to form the first conductive layer 14 as shown in FIG7.
  • the first conductive layer 14 includes a first portion 141 and a second portion 142 (as shown in the enlarged view on the left in FIG. 7 ).
  • the portion of the first conductive layer 14 covered by the barrier layer 17 forms the first portion 141
  • the portion of the first conductive layer 14 below the first portion 141 forms the second portion 142 .
  • a wet solution with a high wet etching selectivity ratio for the first conductive layer 14 can be selected to etch the first conductive layer 14 to avoid damaging the barrier layer 17 during the etching process of the first conductive layer 14 .
  • the projection area of the second part 142 on the substrate is within the projection area of the first part 141 on the substrate, that is, the maximum size of the second part 142 on the X-axis is less than or equal to the maximum size of the first part 141 on the X-axis.
  • the size of the second portion 142 is smaller than that of the first portion 141 , which can reduce the contact area between the first conductive layer and the substrate, and is beneficial for etching the substrate.
  • FIGS. 8 to 13 show schematic structural diagrams of the first conductive layer and the second conductive layer.
  • the specific structure of the first conductive layer 14 and the size relationship between the first conductive layer 14 and the second conductive layer 15 are described below in conjunction with FIGS. 8 to 13 .
  • the size of the first conductive layer 14 in the X-axis direction increases first and then decreases, and the first conductive layer 14 includes a first portion 141 and a second portion 142, wherein the size of the first portion 141 in the X-axis direction gradually increases, and the size of the second portion 142 in the X-axis direction gradually decreases.
  • the minimum size d7 of the second portion 142 in the X-axis direction is equal to the size d5 of the second conductive layer 15 in the X-axis direction, and is equal to the minimum size of the first portion 141 in the X-axis direction; the maximum size d6 of the first portion 141 in the X-axis direction is equal to the maximum size d8 of the second portion 142 in the X-axis direction.
  • the size of the first conductive layer 14 in the X-axis direction increases first and then decreases, and the first conductive layer 14 includes a first portion 141 and a second portion 142.
  • the size of the first portion 141 in the X-axis direction gradually increases, and the size of the second portion 142 in the X-axis direction gradually decreases.
  • the minimum size d7 of the second portion 142 in the X-axis direction is greater than the size d5 of the second conductive layer 15 in the X-axis direction, and is less than the maximum size d6 of the first portion 141 in the X-axis direction.
  • the minimum size of the first portion 141 in the X-axis direction is equal to the size d5 of the second conductive layer 15 in the X-axis direction; the maximum size d6 of the first portion 141 in the X-axis direction is equal to the maximum size d8 of the second portion 142 in the X-axis direction.
  • the size of the first conductive layer 14 in the X-axis direction increases first, then decreases, and then increases again, and the first conductive layer 14 includes a first portion 141 and a second portion 142.
  • the size of the first portion 141 in the X-axis direction gradually increases, and the size of the second portion 142 in the X-axis direction first decreases and then increases.
  • the minimum size d7 of the second portion 142 in the X-axis direction is equal to the size d5 of the second conductive layer 15 in the X-axis direction, and the maximum size d6 of the first portion 141 is equal to the maximum size d8 of the second portion 142 in the X-axis direction.
  • the size of the first conductive layer 14 in the X-axis direction increases first and then remains unchanged, and the first conductive layer 14 includes a first portion 141 and a second portion 142.
  • the size of the first portion 141 in the X-axis direction gradually increases, and the size of the second portion 142 in the X-axis direction remains unchanged.
  • the minimum size of the first portion 141 in the X-axis direction is equal to the size d5 of the second conductive layer 15 in the X-axis direction, and the maximum size d6 of the first portion 141 in the X-axis direction is equal to the maximum size d8 of the second portion 142 in the X-axis direction.
  • the size of the first conductive layer 14 in the X-axis direction first increases and then suddenly decreases, and the first conductive layer 14 includes a first portion 141 and a second portion 142.
  • the size of the first portion 141 in the X-axis direction gradually increases, and the size of the second portion 142 in the X-axis direction gradually decreases.
  • the minimum size d7 of the second portion 142 in the X-axis direction is equal to the size of the second conductive layer 15 in the X-axis direction.
  • d5 and a maximum dimension d6 of the first portion 141 in the X-axis direction is greater than a maximum dimension d8 of the second portion 142 in the X-axis direction.
  • the first part 141 at the top of the first conductive layer 14 has a barrier layer 17 when etching the first conductive layer 14, the first part 141 is not etched under the protection of the barrier layer 17, and still maintains the morphology before etching, that is, the size of the first part 141 gradually increases.
  • the etching of the first conductive layer 14 is mainly the etching of the second part 142, so the size of the second part 142 gradually decreases from the junction of the first part 141 and the second part 142 (as shown in Figures 8 and 9).
  • the second part 142 since the etching of the second part 142 is wet etching, and since wet etching is an isotropic etching process, the second part 142 will present a dumbbell-shaped structure as shown in Figure 10, that is, the size of the middle of the second part 142 is smaller than the size of the top or bottom, but in order not to increase the contact resistance and play a good supporting role, the size of the middle of the second part 142 will not be smaller than the size of the second conductive layer 15.
  • the structure of the second part 142 shown in Figures 8 to 12 can be formed by controlling the time of wet etching.
  • FIG13 is a top perspective view of FIG12 , and it can be seen from FIG8 to FIG13 that the projection area of the second conductive layer 15 on the substrate is within the projection area of the first portion 141 on the substrate, and the projection area of the second conductive layer 15 on the substrate is within the projection area of the second portion 142 on the substrate. That is, the dimension d5 of the second conductive layer 15 in the X-axis direction is smaller than the maximum dimension d6 of the first portion 141 in the X-axis direction, and the dimension d5 of the second conductive layer 15 in the X-axis direction is smaller than the maximum dimension d8 of the second portion 142 in the X-axis direction.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the first part 141 on the substrate.
  • it can prevent the size of the first conductive layer 14 from being too small, and prevent the contact area between the first conductive layer 14 and the second conductive layer 15 from being reduced, thereby increasing the contact resistance between the first conductive layer 14 and the second conductive layer 15 and increasing the signal transmission loss.
  • it can also prevent the size of the first part 141 from being too small, resulting in an increase in the resistance of the first conductive layer 14 itself.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the second part 142 on the substrate.
  • this can prevent the second part 142 from being too small, thereby preventing the contact area between the second part 142 and the substrate from becoming smaller and the contact resistance from increasing.
  • it can also ensure that the second part 142 has a good supporting effect.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the second portion 142 on the substrate, which can also ensure that the second portion 142 has a good size, thereby preventing the resistance of the first conductive layer 14 itself from increasing.
  • the minimum dimension d7 of the second part 142 in the X-axis direction is greater than (as shown in Figure 9) or equal to (as shown in Figures 8, 10, and 12) the dimension d5 of the second conductive layer 15 in the X-axis direction.
  • the contact resistance between the second conductive layer 15 and the first conductive layer 14 can be ensured to be low, and at the same time, the contact area between the second part 142 and the substrate can be ensured to be within a suitable range to prevent bit line collapse.
  • the maximum dimension d8 of the second portion 142 in the X-axis direction is greater than the dimension d5 of the second conductive layer 15 in the X-axis direction, and is less than (as shown in Figure 12) or equal to (as shown in Figures 8 to 11) the maximum dimension d6 of the first portion 141 in the X-axis direction; or, the maximum projection area of the second portion 142 on the XY plane is greater than the minimum projection area of the second conductive layer 15 on the XY plane, and is less than or equal to the maximum projection area of the first portion 141 on the XY plane.
  • the projection area of the second portion 142 on the substrate is within the projection area of the first portion 141 on the substrate.
  • the first insulating layer is further etched, wherein a projection area of the first insulating layer on the substrate is within a projection area of the first conductive layer on the substrate.
  • the projection area of the first insulating layer 11 on the substrate is within the projection area of the first conductive layer 14 on the substrate.
  • the maximum dimension of the first insulating layer 11 in the X-axis direction is less than or equal to the maximum dimension of the first conductive layer 14 in the X-axis direction
  • the maximum dimension d9 of the first insulating layer 11 in the X-axis direction is less than or equal to the maximum dimension d6 (or d8) of the first conductive layer 14 in the X-axis direction
  • the maximum projection area of the first insulating layer 11 on the XY plane is less than or equal to the maximum projection area of the first conductive layer 14 on the XY plane.
  • the maximum dimension d9 of the first insulating layer 11 in the X-axis direction is less than the maximum dimension d6 of the first portion 141 in the X-axis direction, and is greater than the dimension d5 of the second conductive layer 15 in the X-axis direction.
  • the minimum dimension d10 of the first insulating layer 11 in the X-axis direction is equal to the dimension d5 of the second conductive layer 15 in the X-axis direction.
  • the minimum dimension d10 of the first insulating layer 11 in the X-axis direction is equal to the minimum dimension d7 of the second portion 142 (i.e., the first conductive layer 14).
  • a wet solution with a high wet etching selectivity ratio for the first insulating layer 11, such as a hot phosphoric acid solution, may be selected to etch the first insulating layer 11 to avoid damaging the substrate during the etching of the first insulating layer 11.
  • the structure of the first insulating layer 11 may also refer to the structure of the second portion 142, for example, the structure of the first insulating layer 11 is substantially the same as or identical to the structure of the second portion 142.
  • the barrier layer 17 is removed and the bit line contact plug 13 is etched.
  • a wet etching solution is used to etch away the barrier layer 17 , exposing the sidewalls of the first portion 141 , the second conductive layer 15 , and the bit line insulating layer 16 .
  • a diluted hydrofluoric acid (DHF) solution can be used to etch away the barrier layer 17, and the wet etching rate of the barrier layer 17 should be slow, about 1 nm is etched away every 10 seconds, and the time can be controlled to etch away the previously deposited 1 nm to 1.5 nm barrier layer 17.
  • DHF diluted hydrofluoric acid
  • bit line contact plug 13 is etched to form the bit line contact plug 13 as shown in Fig. 17.
  • the bit line contact plug 13 includes a polysilicon layer.
  • the bit lines include first bit lines 21 and second bit lines 22 alternately arranged along the X-axis direction; the first bit lines 21 are located on the bit line contact plugs 13, and the bit line contact plugs 13 extend into the substrate.
  • the second bit lines 22 are located on the first insulating layer 11, and the first insulating layer 11 is located on the substrate.
  • the method for manufacturing the semiconductor structure further includes: forming a sidewall isolation layer on the sidewalls of the first bit line 21 and the second bit line 22, and on the surface of the substrate.
  • the sidewall isolation layer may include a first sidewall layer, a second sidewall layer, and a third sidewall layer arranged sequentially from the inside to the outside.
  • the sidewall isolation layer is used to isolate the bit line from other functional structures formed subsequently to prevent leakage.
  • the first sidewall layer and the third sidewall layer may be silicon nitride layers, and the second sidewall layer may be a silicon oxide layer or air.
  • the substrate between the first bit line 21 and the second bit line 22 is etched until the active area 101 is exposed; and a storage node contact is formed on the surface of the exposed active area 101 .
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is that since the projection area of the second part of the first conductive layer on the substrate is within the projection area of the first part on the substrate, it is possible to reduce the contact area between the first conductive layer and the substrate, which is beneficial to etching the substrate. Therefore, when a storage node contact is formed between adjacent bit lines, the active area can be fully exposed, thereby increasing the contact area between the storage node and the active area and reducing the read and write resistance.
  • the embodiment of the present disclosure further provides a semiconductor structure as shown in FIG17.
  • the semiconductor structure in the embodiment of the present disclosure is formed by the manufacturing method of the semiconductor structure in the above embodiment.
  • the semiconductor structure includes: a substrate; a plurality of bit lines, which are arranged on the substrate, and the bit lines include a first conductive layer 14 and a second conductive layer 15 located on the first conductive layer 14; wherein the first conductive layer 14 includes a first portion 141 and a second portion 142 located below the first portion 141, and the projection area of the second portion 142 on the substrate is within the projection area of the first portion 141 on the substrate.
  • the first conductive layer 14 includes a titanium nitride layer
  • the second conductive layer 15 includes a tungsten layer
  • the base includes a substrate 10, and the substrate 10 includes a Active areas 101 and shallow trench isolation structures 102 are arranged alternately. It should be noted that the shallow trench isolation structures 102 are filled with isolation materials. Due to process reasons, isolation materials are usually formed on the surface of the active areas 101. As shown in FIG. 14 , some isolation materials also exist on the surface of the active areas 101.
  • the projection area of the second portion 142 on the substrate is within the projection area of the first portion 141 on the substrate, that is, the size of the second portion 142 is smaller than the size of the first portion 141.
  • the size of the second portion 142 in the X-axis direction is smaller than the size of the first portion 141 in the X-axis direction, or the projection area of the second portion 142 on the substrate (that is, the maximum projection area on the XY plane) is smaller than the projection area of the first portion 141 on the substrate (that is, the maximum projection area on the XY plane).
  • the projection area of the second part 142 on the substrate is within the projection area of the first part 141 on the substrate, which can reduce the contact area between the first part 141 and the substrate, thereby facilitating the etching of the substrate.
  • the active area can be fully exposed, thereby increasing the contact area between the storage node and the active area and reducing the read and write resistance.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the first portion 141 on the substrate, that is, the size of the second conductive layer 15 is smaller than the size of the first portion 141.
  • the size of the second conductive layer 15 in the X-axis direction is smaller than the maximum size of the first portion 141 in the X-axis direction; or, the projection area of the second conductive layer 15 on the XY plane is smaller than the projection area of the first portion 141 on the XY plane.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the first part 141 on the substrate.
  • it can prevent the size of the first conductive layer 14 from being too small, and prevent the contact area between the first conductive layer 14 and the second conductive layer 15 from being reduced, thereby causing the contact resistance between the first conductive layer 14 and the second conductive layer 15 to increase and the signal transmission loss to increase; on the other hand, it can also prevent the size of the first part 141 from being too small, resulting in an increase in the resistance of the first conductive layer 14 itself.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the second portion 142 on the substrate, that is, the size of the second conductive layer 15 is smaller than the size of the second portion 142.
  • the size of the second conductive layer 15 in the X-axis direction is smaller than the maximum size of the second portion 142 in the X-axis direction; or, the projection area of the second conductive layer 15 on the XY plane is smaller than the projection area of the second portion 142 on the XY plane.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the second part 142 on the substrate.
  • this can prevent the second part 142 from being too small, thereby preventing the contact area between the second part 142 and the substrate from becoming smaller and the contact resistance from increasing; on the other hand, it can also ensure that the second part 142 has a good supporting effect.
  • the projection area of the second conductive layer 15 on the substrate is within the projection area of the second portion 142 on the substrate, which can also ensure that the second portion 142 has a good size, thereby preventing the resistance of the first conductive layer 14 itself from increasing.
  • the minimum size of the second portion 142 is greater than or equal to the size of the second conductive layer 15. That is, the minimum size of the second portion 142 in the X-axis direction is greater than or equal to the size of the second conductive layer 15 in the X-axis direction; or, the minimum projection area of the second portion 142 on the XY plane is greater than or equal to the projection area of the second conductive layer 15 on the XY plane.
  • the minimum size of the second part 142 is greater than or equal to the size of the second conductive layer 15, which can ensure that the contact resistance between the second conductive layer 15 and the first conductive layer 14 is low, and at the same time ensure that the contact area between the second part 142 and the substrate is within a suitable range to prevent bit line collapse.
  • the maximum size of the second portion 142 is larger than the size of the second conductive layer 15 , and smaller than or equal to the maximum size of the first portion 141 .
  • the maximum size of the second portion 142 is smaller than or larger than the size of the second conductive layer 15 , which can ensure that the second conductive layer 15 and the first conductive layer 14 have a smaller contact resistance.
  • bit lines include first bit lines 21 and second bit lines 22 that are alternately arranged.
  • the first bit line 21 is located on the bit line contact plug 13 , and the bit line contact plug 13 extends into the substrate; the bit line contact plug 13 includes a polysilicon layer.
  • the second bit line 22 is located on the first insulating layer 11 , and the first insulating layer 11 is located on the substrate; the first insulating layer 11 includes a silicon nitride layer.
  • the second bit line 22 does not include an underlying conductive layer (eg, a polysilicon layer), so that not only the height of the second bit line 22 can be reduced, but also the parasitic capacitance between the second bit line 22 and the subsequent storage node contacts can be reduced.
  • an underlying conductive layer eg, a polysilicon layer
  • the first bit line 21 and the second bit line 22 further include a bit line insulating layer 16 located on the surface of the second conductive layer 15 .
  • the projection area of the first insulating layer 11 on the substrate is within the projection area of the first conductive layer 14 on the substrate, that is, the size of the first insulating layer 11 is smaller than the size of the first conductive layer 14.
  • the size of the first insulating layer 11 in the X-axis direction is smaller than the size of the first conductive layer 14 in the X-axis direction; or, the projection area of the first insulating layer 11 on the XY plane is smaller than the projection area of the first conductive layer 14 on the XY plane.
  • the size of the first insulating layer 11 is smaller than that of the first conductive layer 14 , so that when etching the substrate subsequently, the first insulating layer 11 does not need to be etched, which is beneficial to etching the substrate.
  • the maximum dimension d9 of the first insulating layer 11 in the X-axis direction is smaller than the maximum dimension d6 of the first portion 141 in the X-axis direction, and is larger than the dimension d5 of the second conductive layer 15 in the X-axis direction.
  • the minimum dimension d10 of the first insulating layer 11 in the X-axis direction is equal to the minimum dimension d7 of the second portion 142 (ie, the first conductive layer 14 ) in the X-axis direction.
  • the semiconductor structure provided by the embodiment of the present disclosure is formed by the manufacturing method of the semiconductor structure in the above embodiment.
  • the technical features not fully disclosed in the embodiment of the present disclosure please refer to the above embodiment for understanding, and no further details will be given here.
  • the semiconductor structure provided by the embodiment of the present disclosure can reduce the contact area between the first part and the substrate because the projection area of the second part on the substrate is within the projection area of the first part on the substrate, which is beneficial to etching the substrate.
  • the active area can be fully exposed, thereby increasing the contact area between the storage node contact and the active area and reducing the read and write resistance.
  • the present disclosure provides a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure comprises: A plurality of bit lines on a substrate, the bit lines include a first conductive layer and a second conductive layer located on the first conductive layer; wherein the first conductive layer includes a first portion and a second portion located below the first portion. Since the projection area of the second portion of the first conductive layer on the substrate is within the projection area of the first portion on the substrate, the contact area between the first conductive layer and the substrate can be reduced, which is beneficial to etching the substrate, so that when a storage node contact is formed between adjacent bit lines, the active area can be fully exposed, thereby increasing the contact area between the storage node and the active area and reducing the read/write resistance.

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  • Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

Des modes de réalisation de la présente invention concernent une structure semi-conductrice et son procédé de fabrication. La structure semi-conductrice comprend : un substrat ; et une pluralité de lignes de bits, disposées sur le substrat, chaque ligne de bits comprenant une première couche conductrice et une seconde couche conductrice située sur la première couche conductrice, la première couche conductrice comprenant une première partie et une seconde partie située sous la première partie, et une zone de projection de la seconde partie sur le substrat tombant dans une zone de projection de la première partie sur le substrat.
PCT/CN2023/089517 2022-11-08 2023-04-20 Structure semi-conductrice et son procédé de fabrication WO2024098672A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080093741A1 (en) * 2006-10-20 2008-04-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
CN101443902A (zh) * 2006-04-13 2009-05-27 美光科技公司 用于在形成快闪存储器装置期间形成位线触点及位线的方法，及包括所述位线及位线触点的装置
CN110085551A (zh) * 2018-01-25 2019-08-02 长鑫存储技术有限公司 存储元件的位线的制作过程、存储元件及其制作方法
CN210296375U (zh) * 2019-09-17 2020-04-10 福建省晋华集成电路有限公司 半导体器件、存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101443902A (zh) * 2006-04-13 2009-05-27 美光科技公司 用于在形成快闪存储器装置期间形成位线触点及位线的方法，及包括所述位线及位线触点的装置
US20080093741A1 (en) * 2006-10-20 2008-04-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
CN110085551A (zh) * 2018-01-25 2019-08-02 长鑫存储技术有限公司 存储元件的位线的制作过程、存储元件及其制作方法
CN210296375U (zh) * 2019-09-17 2020-04-10 福建省晋华集成电路有限公司 半导体器件、存储器

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