WO2024095835A1 - Semiconductor laser device, semiconductor laser module, and sensor - Google Patents

Semiconductor laser device, semiconductor laser module, and sensor Download PDF

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Publication number
WO2024095835A1
WO2024095835A1 PCT/JP2023/038388 JP2023038388W WO2024095835A1 WO 2024095835 A1 WO2024095835 A1 WO 2024095835A1 JP 2023038388 W JP2023038388 W JP 2023038388W WO 2024095835 A1 WO2024095835 A1 WO 2024095835A1
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layer
semiconductor laser
laser device
thickness
light
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PCT/JP2023/038388
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French (fr)
Japanese (ja)
Inventor
圭二 日▲高▼
良宜 田中
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ローム株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/023Mount members, e.g. sub-mount members
    • H01S5/0231Stems
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/34Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers

Definitions

  • This disclosure relates to a semiconductor laser device, a semiconductor laser module, and a sensor.
  • Patent Document 1 discloses a semiconductor laser device.
  • This semiconductor laser device includes a double heterostructure having an n-type cladding layer, an active layer, and a p-type cladding layer. Such a semiconductor laser device emits laser light from an end face of the active layer.
  • a semiconductor laser device includes an active layer including a barrier layer and well layers provided on both sides of the barrier layer in the thickness direction of the barrier layer, and an n-type semiconductor layer and a p-type semiconductor layer sandwiching the active layer in the thickness direction of the active layer, and the thickness of the well layer is greater than the thickness of the barrier layer.
  • a semiconductor laser module includes the semiconductor laser device, a stem to which the semiconductor laser device is attached, a cap attached to the stem, covering the semiconductor laser device and having an opening through which laser light from the semiconductor laser device passes, and a terminal pin electrically connected to the semiconductor laser device.
  • a sensor includes the semiconductor laser module, a bandpass filter, and a light receiving module including a light receiving element that receives light that has passed through the bandpass filter.
  • the above-mentioned semiconductor laser device, semiconductor laser module, and sensor can reduce the temperature dependence of the wavelength of laser light.
  • FIG. 1 is a perspective view showing a semiconductor laser device according to an embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor laser device shown in FIG. 1 taken along line F2-F2.
  • FIG. 3 is an explanatory diagram showing an example of the structure of the light-emitting unit shown in FIG.
  • FIG. 4 is an explanatory diagram showing an example of the structure of the active layer shown in FIG.
  • FIG. 5 is an explanatory diagram showing an example of the structure of the tunnel layer shown in FIG.
  • FIG. 6 is a perspective view showing a semiconductor laser module including a semiconductor laser device.
  • FIG. 7 is a cross-sectional view of the semiconductor laser module shown in FIG.
  • FIG. 8 is a plan view showing a semiconductor laser unit on which a semiconductor laser device is mounted.
  • FIG. 9 is a rear view showing the semiconductor laser unit of FIG.
  • FIG. 10 is an explanatory diagram showing an example of the structure of a sensor equipped with a semiconductor laser module.
  • FIG. 11 is a table showing the relationship between the thickness of the well layer and the thickness of the barrier layer and the wavelength temperature coefficient and optical spectrum of the laser light.
  • FIG. 12 is a graph showing the optical spectrum of the emission intensity versus wavelength at temperatures from 10° C. to 90° C. for the semiconductor laser device included in region R of FIG.
  • FIG. 13 is a graph showing optical spectra of emission intensity versus wavelength at temperatures from 10° C. to 90° C. for a semiconductor laser device outside the region R in FIG.
  • FIG. 14 is a table showing the relationship between the well layer thickness and the optical output.
  • FIG. 15 is a table showing the relationship between the emission width of the laser light and the wavelength temperature coefficient.
  • FIG. 16 is a cross-sectional view showing a semiconductor laser device according to a first modified example.
  • FIG. 17 is a cross-sectional view showing a semiconductor laser device according to a second modification.
  • FIG. 18 is a perspective view showing a semiconductor laser module according to a modified example.
  • FIG. 19 is a cross-sectional view of the semiconductor laser module shown in FIG.
  • FIGS. Fig. 1 shows a perspective structure of a semiconductor laser device 10
  • Fig. 2 shows a cross-sectional structure of the semiconductor laser device of Fig. 1.
  • Fig. 3 shows a schematic example of a structure of the light emitting unit of Fig. 2
  • Fig. 4 shows a schematic example of a structure of the active layer shown in Fig. 3
  • Fig. 5 shows a schematic example of a structure of the tunnel layer of Fig. 2.
  • the semiconductor laser device 10 has a semiconductor substrate 20, a light emitting portion 30, an insulating film 70, a first electrode 81, and a second electrode 82.
  • the semiconductor substrate 20 is formed, for example, in the shape of a rectangular plate.
  • the semiconductor substrate 20 is configured, for example, of an n-type semiconductor substrate (n-GaAs substrate) containing GaAs (gallium arsenide).
  • the semiconductor substrate 20 contains at least one of Si (silicon), Te (tellurium), and Se (selenium) as an n-type impurity.
  • the semiconductor substrate 20 has a substrate main surface 21, a substrate back surface 22, and substrate side surfaces 23 to 26.
  • the substrate main surface 21 and the substrate back surface 22 face in opposite directions.
  • the direction perpendicular to the substrate main surface 21 will be referred to as the "Z direction”
  • the two directions perpendicular to the Z direction will be referred to as the "X direction” and "Y direction”, respectively.
  • the Z direction can be said to be the thickness direction of the semiconductor substrate 20.
  • the substrate side surfaces 23 and 24 face in opposite directions in the Y direction, and the substrate side surfaces 25 and 26 face in opposite directions in the X direction.
  • the semiconductor substrate 20 is formed in a rectangular shape that is long in the Y direction.
  • the light emitting portion 30 is provided on a substrate main surface 21 of a semiconductor substrate 20.
  • the light emitting portion 30 protrudes from the substrate main surface 21 toward the side opposite to the substrate back surface 22.
  • the light emitting unit 30 has an electrode connection surface 31, a substrate connection surface 32, light emitting unit end surfaces 33, 34, and light emitting unit side surfaces 35, 36.
  • the electrode connection surface 31 faces the same direction as the substrate main surface 21 in the Z direction.
  • the electrode connection surface 31 is disposed apart from the substrate main surface 21 in the Z direction.
  • the substrate connection surface 32 faces the semiconductor substrate 20 side and is connected to the substrate main surface 21.
  • the light emitting unit side surfaces 35, 36 face opposite each other in the X direction.
  • the light emitting unit side surfaces 35, 36 connect the electrode connection surface 31 and the substrate main surface 21.
  • the light emitting unit end surfaces 33, 34 face opposite each other in the Y direction.
  • the light emitting unit end surfaces 33, 34 constitute resonator end surfaces.
  • the light emitting unit 30 emits laser light L1 from the light emitting unit end surface 33.
  • the light emitting section 30 has a mesa structure and is formed in a trapezoidal shape (ridge shape) protruding from the substrate main surface 21 when viewed from the Y direction.
  • the light emitting section side surface 35 is inclined so as to face the electrode connection surface 31 side with respect to the direction in which the substrate side surface 25 faces.
  • the light emitting section side surface 36 is inclined so as to face the electrode connection surface 31 side with respect to the direction in which the substrate side surface 26 faces. Therefore, when viewed from the Y direction, the light emitting section 30 is formed in a trapezoidal shape in which the width of the electrode connection surface 31 is narrower than the width of the substrate connection surface 32 that is connected to the substrate main surface 21.
  • the light emitting section 30 extends in the Y direction.
  • the length of the light emitting section 30 in the Y direction is equal to the length of the semiconductor substrate 20.
  • the light emitting section end surface 33 of the light emitting section 30 is flush with the substrate side surface 23 of the semiconductor substrate 20, and the light emitting section end surface 34 is flush with the substrate side surface 24 of the semiconductor substrate 20.
  • the insulating film 70 is formed so as to cover a part of the substrate main surface 21 of the semiconductor substrate 20.
  • the insulating film 70 is also formed so as to cover the light emitting portion 30.
  • the insulating film 70 is formed so as to cover the electrode connection surface 31 and the light emitting portion side surfaces 35, 36 of the light emitting portion 30.
  • the insulating film 70 of this embodiment has substrate covering portions 72, 73 that cover the substrate main surface 21 of the semiconductor substrate 20, and a light emitting portion covering portion 74 that covers the light emitting portion 30.
  • the insulating film 70 is made of, for example, SiN (silicon nitride), SiO 2 (silicon oxide), or the like.
  • the first electrode 81 is provided on the upper surface 71 of the insulating film 70 that covers the electrode connection surface 31 of the light-emitting section 30.
  • the insulating film 70 that covers the electrode connection surface 31 of the light-emitting section 30 has a first opening 71X that exposes a portion of the electrode connection surface 31.
  • the first electrode 81 is electrically connected to the electrode connection surface 31 exposed from the first opening 71X of the insulating film 70. In other words, the first electrode 81 is electrically connected to the light-emitting section 30.
  • the first electrode 81 is formed so as to cover the end that forms the first opening 71X of the insulating film 70.
  • the first electrode 81 may be composed of multiple electrode layers.
  • the first electrode 81 includes a first electrode layer and a second electrode layer.
  • the first electrode layer and the second electrode layer are laminated in this order from the electrode connection surface 31 side.
  • the first electrode layer is composed of, for example, Ti (titanium)/Au (gold).
  • the second electrode layer is, for example, a plating layer containing Au.
  • the second electrode 82 is provided on the rear surface 22 of the semiconductor substrate 20.
  • the second electrode 82 covers the entire rear surface 22 of the substrate.
  • the second electrode 82 is electrically connected to the semiconductor substrate 20.
  • the second electrode 82 may be composed of multiple electrode layers.
  • the second electrode 82 may include at least one of a Ni (nickel) layer, an AuGe (gold-germanium alloy) layer, a Ti layer, and an Au layer.
  • the second electrode 82 may include a Ni layer, an AuGe layer, a Ti layer, and an Au layer stacked in this order from the rear surface 22 of the substrate.
  • the light-emitting section 30 includes light-emitting units 40 stacked on the substrate main surface 21 of the semiconductor substrate 20.
  • the light-emitting units 40 generate light by recombination of holes and electrons.
  • the light-emitting section 30 of this embodiment has three light-emitting units 40.
  • the light-emitting section 30 may have at least one light-emitting unit 40. In other words, the number of light-emitting units 40 may be one, two, or four or more.
  • the light-emitting section 30 of this embodiment includes a tunnel layer 60 disposed between adjacent light-emitting units 40.
  • the tunnel layer 60 generates a tunnel current due to the tunnel effect and supplies it to the light-emitting unit 40.
  • the light-emitting section 30 of this embodiment includes two tunnel layers 60.
  • the tunnel layer 60 is disposed between two adjacent light-emitting units 40.
  • the emission width of the laser light L1 (see FIG. 1) emitted from the light-emitting unit 30 is, for example, 50 ⁇ m or more and 300 ⁇ m or less. In this embodiment, the emission width is 270 ⁇ m.
  • the emission width can be defined by the length in the X direction of the laser light L1 at the light-emitting end surface 33 of the light-emitting unit 30.
  • FIG. 3 shows an example of the structure of the light-emitting unit 40 .
  • the light-emitting unit 40 includes an active layer 41, and an n-type semiconductor layer 42 and a p-type semiconductor layer 43 which sandwich the active layer 41 in the thickness direction of the active layer 41.
  • the thickness direction of the active layer 41 coincides with the Z direction.
  • the light-emitting section end surface 33 of the light-emitting section 30 includes an end surface of the active layer 41. For this reason, it can be said that the active layer 41 includes an end surface that emits laser light.
  • the n-type semiconductor layer 42 is disposed on the side of the active layer 41 that faces the semiconductor substrate 20 shown in Figures 1 and 2.
  • the p-type semiconductor layer 43 is disposed on the side of the active layer 41 that faces the opposite side to the n-type semiconductor layer 42, that is, on the side of the first electrode 81 shown in Figures 1 and 2. For this reason, it can be said that the light-emitting unit 40 has a layered structure that includes the n-type semiconductor layer 42, the active layer 41, and the p-type semiconductor layer 43, which are layered in this order from the semiconductor substrate 20 side.
  • the n-type semiconductor layer 42 includes aluminum gallium arsenide (AlGaAs).
  • the n-type semiconductor layer 42 includes at least one of Si, Te, and Se as an n-type impurity.
  • the impurity concentration of the n-type semiconductor layer 42 is, for example, not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the n-type semiconductor layer 42 includes a first n-type cladding layer 44 and a second n-type cladding layer 45.
  • the first n-type cladding layer 44 is disposed adjacent to the active layer 41.
  • the second n-type cladding layer 45 is disposed on the opposite side of the active layer 41 with respect to the first n-type cladding layer 44.
  • the n-type semiconductor layer 42 includes the first n-type cladding layer 44 adjacent to the active layer 41, and the second n-type cladding layer 45 located on the opposite side of the active layer 41 with respect to the first n-type cladding layer 44.
  • the n-type semiconductor layer 42 includes the first n-type cladding layer 44 and the second n-type cladding layer 45 stacked in this order from the active layer 41 side.
  • the first n-type cladding layer 44 includes Al A1 Ga (1-A1) As having an Al composition A1. In one example, the Al composition A1 of the first n-type cladding layer 44 is 0.2 or more and 0.5 or less.
  • the second n-type cladding layer 45 includes Al A2 Ga (1-A2) As having an Al composition A2 different from the Al composition A1 of the first n-type cladding layer 44.
  • the Al composition A2 of the second n-type cladding layer 45 is larger than the Al composition A1 of the first n-type cladding layer 44 (A2>A1). In one example, the Al composition A2 of the second n-type cladding layer 45 is 0.4 or more and 0.7 or less.
  • the impurity concentration of the second n-type cladding layer 45 is different from the impurity concentration of the first n-type cladding layer 44. More specifically, the impurity concentration of the second n-type cladding layer 45 is higher than the impurity concentration of the first n-type cladding layer 44.
  • the impurity concentration of the second n-type cladding layer 45 may be equal to the impurity concentration of the first n-type cladding layer 44.
  • the impurity concentration of the second n-type cladding layer 45 may also be lower than the impurity concentration of the first n-type cladding layer 44.
  • P-type semiconductor layer 43 includes AlGaAs.
  • P-type semiconductor layer 43 includes p-type impurities, for example, C (carbon).
  • the impurity concentration of p-type semiconductor layer 43 is, for example, not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the p-type semiconductor layer 43 includes a first p-type cladding layer 46 and a second p-type cladding layer 47.
  • the first p-type cladding layer 46 is disposed adjacent to the active layer 41.
  • the second p-type cladding layer 47 is disposed on the opposite side of the active layer 41 with respect to the first p-type cladding layer 46.
  • the p-type semiconductor layer 43 includes the first p-type cladding layer 46 adjacent to the active layer 41, and the second p-type cladding layer 47 located on the opposite side of the active layer 41 with respect to the first p-type cladding layer 46.
  • the p-type semiconductor layer 43 includes the first p-type cladding layer 46 and the second p-type cladding layer 47 stacked in this order from the active layer 41 side.
  • the first p-type cladding layer 46 includes Al B1 Ga (1-B1) As having an Al composition B1. In one example, the Al composition B1 of the first p-type cladding layer 46 is 0.2 or more and 0.5 or less.
  • the second p-type cladding layer 47 includes Al B2 Ga (1-B2) As having an Al composition B2 different from the Al composition B1 of the first p-type cladding layer 46.
  • the Al composition B2 of the second p-type cladding layer 47 is larger than the Al composition B1 of the first p-type cladding layer 46 (B2>B1). In one example, the Al composition B2 of the second p-type cladding layer 47 is 0.4 or more and 0.7 or less.
  • the impurity concentration of the second p-type cladding layer 47 is different from the impurity concentration of the first p-type cladding layer 46. More specifically, the impurity concentration of the second p-type cladding layer 47 is higher than the impurity concentration of the first p-type cladding layer 46. The impurity concentration of the second p-type cladding layer 47 may be equal to the impurity concentration of the first p-type cladding layer 46. The impurity concentration of the second p-type cladding layer 47 may be lower than the impurity concentration of the first p-type cladding layer 46.
  • FIG. 4 shows an example of the configuration of the active layer 41 .
  • the active layer 41 includes a barrier layer 51 and well layers 52 provided on both sides of the barrier layer 51 in the thickness direction of the barrier layer 51.
  • the well layer 52 is a quantum well layer
  • the barrier layer 51 is a barrier layer that acts as a barrier against the movement of carriers (electrons and holes) between the well layers 52.
  • the thickness direction of the barrier layer 51 coincides with the Z direction.
  • the well layers 52 provided on both sides of the barrier layer 51 are referred to as a "first well layer 52A" and a "second well layer 52B".
  • the active layer 41 has a multiple quantum well structure including the barrier layer 51, the first well layer 52A, and the second well layer 52B.
  • the first well layer 52A and the second well layer 52B are arranged with the barrier layer 51 in between.
  • the first well layer 52A is arranged adjacent to the barrier layer 51 on the side of the n-type semiconductor layer 42 shown in FIG. 3 with respect to the barrier layer 51.
  • the second well layer 52B is arranged on the opposite side of the barrier layer 51 to the first well layer 52A.
  • the active layer 41 includes the first well layer 52A, the barrier layer 51, and the second well layer 52B, which are stacked in this order from the n-type semiconductor layer 42 (first n-type cladding layer 44) shown in FIG. 3.
  • the active layer 41 of this embodiment further includes a first guiding layer 53 and a second guiding layer 54 .
  • the first guide layer 53 is disposed adjacent to the first well layer 52A.
  • the first guide layer 53 is disposed on the opposite side of the barrier layer 51 with respect to the first well layer 52A.
  • the second guide layer 54 is disposed adjacent to the second well layer 52B.
  • the second guide layer 54 is disposed on the opposite side of the barrier layer 51 with respect to the second well layer 52B. It can be said that the first guide layer 53 and the second guide layer 54 are disposed to sandwich the first well layer 52A, the barrier layer 51, and the second well layer 52B.
  • the active layer 41 includes the first guide layer 53, the first well layer 52A, the barrier layer 51, the second well layer 52B, and the second guide layer 54, which are stacked in this order from the n-type semiconductor layer 42 (first n-type cladding layer 44) shown in FIG. 3.
  • the barrier layer 51 includes AlGaAs.
  • the barrier layer 51 includes Al C1 Ga (1-C1) As having an Al composition C1.
  • the Al composition C1 of the barrier layer 51 is different from the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42 and the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43.
  • the Al composition C1 of the barrier layer 51 is smaller than the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42 and the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43.
  • the Al composition C1 of the barrier layer 51 is 0.05 or more and 0.3 or less.
  • the barrier layer 51 may be free of impurities.
  • the first well layer 52A includes In D1 Ga (1-D1) As having an In composition D1.
  • the In composition D1 is greater than 0 and equal to or less than 0.15.
  • the first well layer 52A may be undoped.
  • the second well layer 52B includes In D2 Ga (1-D2) As having an In composition D2.
  • the In composition D2 may be equal to the In composition D1 of the first well layer 52A. In one example, the In composition D2 is greater than 0 and equal to or less than 0.15.
  • the second well layer 52B may be undoped.
  • the first guide layer 53 includes AlGaAs.
  • the first guide layer 53 includes Al C2 Ga (1-C2) As having an Al composition C2.
  • the Al composition C2 of the first guide layer 53 is different from the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42.
  • the Al composition C2 of the first guide layer 53 is smaller than the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42.
  • the Al composition C2 of the first guide layer 53 is 0.05 or more and 0.3 or less.
  • the first guide layer 53 may be free of impurities.
  • the second guide layer 54 includes AlGaAs.
  • the second guide layer 54 includes Al C3 Ga (1-C3) As having an Al composition C3.
  • the Al composition C3 of the second guide layer 54 is different from the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43.
  • the Al composition C3 of the second guide layer 54 is smaller than the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43.
  • the Al composition C3 of the second guide layer 54 may be equal to the Al composition C2 of the first guide layer 53.
  • the Al composition C3 of the second guide layer 54 is 0.05 or more and 0.3 or less.
  • the second guide layer 54 may be free of impurities.
  • FIG. 5 shows an example of the configuration of the tunnel layer 60 .
  • the tunnel layer 60 includes a p-type tunnel layer 61 and an n-type tunnel layer 62.
  • the p-type tunnel layer 61 is disposed adjacent to the p-type semiconductor layer 43 (second p-type cladding layer 47) shown in FIG. 3.
  • the n-type tunnel layer 62 is disposed adjacent to the n-type semiconductor layer 42 (second n-type cladding layer 45) shown in FIG. 3. Therefore, the p-type tunnel layer 61 and the n-type tunnel layer 62 are laminated in this order from the side of the semiconductor substrate 20 shown in FIG. 1 and FIG. 2.
  • the tunnel layer 60 is disposed between the light-emitting units 40 in such a manner that the p-type tunnel layer 61 is electrically connected to the p-type semiconductor layer 43 and the n-type tunnel layer 62 is electrically connected to the n-type semiconductor layer 42.
  • the p-type tunnel layer 61 contains GaAs.
  • the p-type tunnel layer 61 contains, for example, C as a p-type impurity.
  • the impurity concentration of the p-type tunnel layer 61 is different from the impurity concentration of the p-type semiconductor layer 43.
  • the impurity concentration of the p-type tunnel layer 61 is higher than the impurity concentration of the p-type semiconductor layer 43.
  • the n-type tunnel layer 62 includes GaAs.
  • the n-type tunnel layer 62 includes at least one of the following n-type impurities: Si, Te, and Se.
  • the impurity concentration of the n-type tunnel layer 62 is different from the impurity concentration of the n-type semiconductor layer 42.
  • the impurity concentration of the n-type tunnel layer 62 is higher than the impurity concentration of the n-type semiconductor layer 42.
  • the thickness TWA of the first well layer 52A and the thickness TWB of the second well layer 52B are thicker than the thickness TB of the barrier layer 51. In other words, the thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51. In one example, the thickness TWA of the first well layer 52A and the thickness TWB of the second well layer 52B are equal to each other. In one example, the ratio (TW/TB) of the thickness TW of the well layer 52 to the thickness TB of the barrier layer 51 is 1.9 or more and 4.3 or less.
  • the thickness TW of the well layer 52 is greater than 100 ⁇ and less than or equal to 130 ⁇ . In one example, the thickness TW of the well layer 52 is greater than or equal to 105 ⁇ and less than or equal to 130 ⁇ . In one example, the thickness TW of the well layer 52 is greater than or equal to 110 ⁇ and less than or equal to 130 ⁇ .
  • the thickness TB of the barrier layer 51 is greater than 0 ⁇ and equal to or less than 60 ⁇ . In one example, the thickness TB of the barrier layer 51 is equal to or greater than 30 ⁇ and equal to or less than 60 ⁇ . As an example of a combination of the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52, the thickness TB of the barrier layer 51 is greater than 0 ⁇ and less than 60 ⁇ , and the thickness TW of the well layer 52 is greater than 100 ⁇ and less than 140 ⁇ .
  • the thickness TB of the barrier layer 51 is greater than 30 ⁇ and less than 60 ⁇ , and the thickness TW of the well layer 52 is greater than 100 ⁇ and less than 13 ...5 ⁇ and less than 130 ⁇ . In another example, the thickness TB of the barrier layer 51 is greater than 30 ⁇ and less than 60 ⁇ , and the thickness TW of the well layer 52 is greater than 110 ⁇ and less than 130 ⁇ .
  • the semiconductor laser module 200 includes a stem 210, a semiconductor laser unit 100 mounted on the stem 210, a cap 220 that covers the semiconductor laser unit 100, and terminal pins 231 to 234 that are electrically connected to the semiconductor laser unit 100.
  • the semiconductor laser unit 100 includes a semiconductor laser device 10.
  • the stem 210 includes a flat base 211 and a heat sink 212 standing on the base 211.
  • the semiconductor laser unit 100 is mounted on the heat sink 212.
  • the cap 220 is attached to the base 211 so as to cover the semiconductor laser unit 100 and the heat sink 212.
  • the cap 220, together with the base 211 forms an accommodation space SP that accommodates the semiconductor laser unit 100 and the heat sink 212.
  • the cap 220, together with the base 211 makes the accommodation space SP (see Figure 7) airtight in a hollow state, forming a hollow sealing structure.
  • the cap 220 is made of a light-shielding material and has an opening 221 through which the laser light from the semiconductor laser unit 100 passes.
  • a light-transmitting plate 222 (see FIG. 7) is attached to the opening 221.
  • Terminal pins 231 to 234 are provided on base 211. More specifically, each of terminal pins 231 to 233 penetrates base 211 in the thickness direction of base 211. Insulating material 235 is filled between terminal pins 231 to 233 and base 211. Terminal pin 234 is formed integrally with base 211.
  • FIG. 8 shows the planar structure of the semiconductor laser unit 100 in a state where the insulating layer covering the substrate main surface 111 of the substrate 110 is omitted.
  • the semiconductor laser unit 100 includes a substrate 110, and a semiconductor laser device 10, a switching element 120, and capacitors 131 and 132 mounted on the substrate 110.
  • the substrate 110 is formed in a rectangular flat plate shape.
  • the substrate 110 is formed from an insulating material such as glass epoxy resin.
  • the substrate 110 has a substrate main surface 111 and a substrate back surface 112 (see FIG. 9) facing the opposite side to the substrate main surface 111.
  • First to third main surface side wirings 111A to 111C are formed on the main surface side wirings of the substrate 110.
  • the semiconductor laser device 10, the switching element 120, and the capacitors 131 and 132 are mounted on the first and second main surface side wirings 111A and 111B.
  • the semiconductor laser device 10 is bonded to the center of the first main surface side wiring 111A in the X direction by a conductive bonding material SD such as solder paste or Ag (silver) paste. This electrically connects the semiconductor laser device 10 and the first main surface side wiring 111A.
  • a conductive bonding material SD such as solder paste or Ag (silver) paste.
  • the switching element 120 is a semiconductor element that controls the current supplied to the semiconductor laser device 10.
  • the switching element 120 is, for example, a transistor.
  • a MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • a source electrode 121 and a gate electrode 122 are formed on the element principal surface of the switching element 120 facing the same side as the substrate principal surface 111, and a drain electrode (not shown) is formed on the element rear surface facing the substrate principal surface 111.
  • the switching element 120 is a vertical structure MOSFET.
  • the switching element 120 is joined to the center of the second principal surface side wiring 111B in the X direction by a conductive bonding material SD. This electrically connects the drain of the switching element 120 to the second principal surface side wiring 111B.
  • the source electrode 121 is electrically connected to the semiconductor laser device 10 by a wire W1.
  • the capacitors 131 and 132 are electronic components that cooperate with the switching element 120 to supply current to the semiconductor laser device 10.
  • the capacitances of the capacitors 131 and 132 are equal to each other.
  • the capacitors 131 and 132 are arranged so as to straddle the first main surface side wiring 111A and the second main surface side wiring 111B.
  • the capacitors 131 and 132 are joined to both the first main surface side wiring 111A and the second main surface side wiring 111B by a conductive bonding material SD.
  • the capacitors 131 and 132 are electrically connected to both the first main surface side wiring 111A and the second main surface side wiring 111B.
  • the capacitors 131 and 132 are arranged symmetrically with respect to the semiconductor laser device 10 and the switching element 120 on the substrate main surface 111.
  • a loop-shaped first wiring path through which a current flows from the capacitor 131 to the semiconductor laser device 10 via the switching element 120, and a loop-shaped second wiring path through which a current flows from the capacitor 132 to the semiconductor laser device 10 via the switching element 120 are formed symmetrically with respect to the semiconductor laser device 10 and the switching element 120.
  • the magnetic flux formed by the current flowing through the first wiring path and the magnetic flux formed by the current flowing through the second wiring path cancel each other out. This makes it possible to reduce both the parasitic inductance present in the first wiring path and the parasitic inductance present in the second wiring path.
  • a first back surface side wiring 112A and a second back surface side wiring 112B are formed as back surface side wiring on the back surface 112 of the substrate 110.
  • the first back surface side wiring 112A and the second back surface side wiring 112B constitute the external terminals of the semiconductor laser unit 100.
  • the first back surface side wiring 112A is electrically connected to both the first main surface side wiring 111A and the third main surface side wiring 111C by one or more through holes 113.
  • the second back surface side wiring 112B is formed at a position overlapping the switching element 120 shown in a dashed line frame in FIG. 9 in a plan view.
  • the first back surface side wiring 112A is formed in a substantially U-shape surrounding the second back surface side wiring 112B.
  • the second back surface side wiring 112B is electrically connected to the second main surface side wiring 111B (see FIG. 8) by one or more through holes 114.
  • the terminal pins 231 to 233 protrude from both sides of the base 211 in the thickness direction of the base 211.
  • the portions of the terminal pins 231 to 233 protruding toward the heat sink 212 side from the base 211 are electrically connected to the semiconductor laser unit 100 by wires W2 to W4, respectively.
  • the wire W2 electrically connects the terminal pin 231 to the source electrode 121 of the switching element 120.
  • the wire W3 electrically connects the terminal pin 232 to the gate electrode 122 of the switching element 120.
  • the wire W4 electrically connects the terminal pin 233 to the third main surface side wiring 111C.
  • the terminal pin 234 is formed integrally with the base 211 and is therefore electrically connected to the base 211. It can also be said that the terminal pin 234 is electrically connected to the heat sink 212.
  • the semiconductor laser unit 100 is mounted on the heat sink 212 so that the second back surface side wiring 112B of the substrate 110 is joined to the heat sink 212 by a conductive bonding material.
  • the first back surface side wiring 112A is not electrically connected to the heat sink 212. Therefore, the terminal pin 234 is electrically connected to the drain electrode of the switching element 120.
  • the sensor 400 can be used as a distance measuring sensor such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging), which is an example of three-dimensional distance measurement.
  • the sensor 400 may also be used as a distance measuring sensor for two-dimensional distance measurement.
  • the sensor 400 includes a semiconductor laser module 200 as an emitting module, and a light receiving module 300.
  • the semiconductor laser module 200 emits laser light toward the measurement object MX.
  • the light receiving module 300 receives the laser light (reflected light) reflected by the measurement object MX.
  • the sensor 400 measures the time difference between when the semiconductor laser module 200 emits the laser light and when the light receiving module 300 receives the reflected light. This allows the distance between the sensor 400 and the measurement object MX to be calculated.
  • the light receiving module 300 includes a light receiving element 310 and a bandpass filter 320.
  • the bandpass filter 320 is a filter configured to transmit light in a specific wavelength range that includes the wavelength of the reflected light.
  • the light receiving element 310 is configured to receive the light that has passed through the bandpass filter 320.
  • the light receiving module 300 of this embodiment is equipped with a bandpass filter 320 that transmits light in a specific wavelength range.
  • the bandpass filter 320 is configured to include the wavelength of the reflected light in the specific wavelength range.
  • This bandpass filter 320 removes light other than the specific wavelength range from the light receiving element 310. It is preferable that such a bandpass filter 320 has a narrow light transmission width (transmitting wavelength range).
  • the laser light from a semiconductor laser device has wavelength temperature dependency, in which the central wavelength of the laser light (the wavelength at the peak of the optical spectrum) changes depending on the temperature of the semiconductor laser device. Specifically, the wavelength of the laser light shifts to the longer wavelength side as the temperature increases.
  • the bandpass filter 320 needs to transmit laser light (reflected light) whose wavelength changes within a certain temperature range. For this reason, it is necessary to widen the transmission wavelength range width of the bandpass filter 320. Sunlight contains light of various wavelengths. Therefore, if the transmission wavelength range width of the bandpass filter 320 is widened, more sunlight will pass through the bandpass filter 320, increasing the risk of the sunlight being mistaken for reflected light.
  • the thickness TW of the well layer 52 which is a quantum well layer, is thicker than the thickness TB of the barrier layer 51. This weakens the quantum size effect, making it possible to widen the available energy range. In other words, the spectral width of the laser light that can be oscillated in the well layer 52 can be increased.
  • the energy and the wavelength are inversely related, oscillation occurs at a short wavelength at high energy. This allows the semiconductor laser device 10 to oscillate a short-wavelength laser light corresponding to high energy. Since such a semiconductor laser device 10 attempts to oscillate a short-wavelength laser light even when the temperature is high, the change in the wavelength of the laser light due to temperature change is suppressed. Therefore, the amount of change (shift) in the wavelength of the laser light due to temperature change is reduced. As a result, the wavelength temperature dependency of the laser light is reduced.
  • this semiconductor laser device 10 can be considered as follows. Increasing the thickness TW of the well layer 52 (quantum well layer) weakens the quantum size effect of the quantum well layer, and increases the number of energy levels that can be taken in the well layer 52. Increasing the thickness TW of the well layer 52 weakens the quantum size effect, and the energy width in the well layer 52 can be expanded. When carriers accumulate in the well layer 52, high-energy oscillation occurs, and the well layer 52 emits laser light with a short wavelength in the spectral width. Therefore, this semiconductor laser device 10 attempts to maintain oscillation in the short-wavelength wavelength range by using energy density, even when the temperature becomes high.
  • the thickness TW of the well layer 52 is increased, there is a risk of bias in the carriers (electrons and holes) in the first well layer 52A and the second well layer 52B arranged on both sides of the barrier layer 51. As a result, there is a risk of multiple peaks in the optical spectrum of the laser light (see FIG. 13).
  • the thickness TB of the barrier layer 51 is made thin.
  • the thickness TB of the barrier layer 51 is thinner than the thickness TW of the well layer 52.
  • carriers can move more easily between the quantum well layers (the first well layer 52A and the second well layer 52B) on both sides of the barrier layer 51 due to the resonant tunneling effect. This reduces the bias of carriers in the first well layer 52A and the second well layer 52B, thereby suppressing the occurrence of multiple peaks in the optical spectrum of the laser light.
  • Example 1 As Experimental Example 1, the relationship between the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 of the semiconductor laser device 10 and the wavelength temperature dependency of the semiconductor laser device 10 and the optical spectrum of the laser light was confirmed.
  • FIG. 11 is a table showing the relationship between the wavelength temperature coefficient (nm/°C) and the state of the optical spectrum of the laser light for a number of semiconductor laser devices 10 in which the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 are changed.
  • FIGS. 12 and 13 show the optical spectrum of the semiconductor laser device 10 in the case temperature range of 10°C to 90°C.
  • FIG. 12 shows the optical spectrum of the semiconductor laser device 10 included in the region R of FIG. 11.
  • FIG. 13 shows the optical spectrum of the semiconductor laser device 10 outside the region R of FIG. 11. Note that in FIGS. 12 and 13, the optical spectrum at each temperature is shown with the peak emission intensity set to 100%.
  • the case temperature is the temperature of the base 211 of the semiconductor laser module 200. In Experimental Example 1, the emission width is set to 270 ⁇ m.
  • the wavelength temperature coefficient measured in Experimental Example 1 is a coefficient that indicates how much the wavelength changes when the temperature changes by 1°C.
  • the wavelength temperature coefficient is calculated as follows. That is, for example, the amount of change in wavelength when the case temperature is changed over a preset range (set temperature range) is calculated.
  • the wavelength temperature coefficient is calculated by dividing this amount of change in wavelength by the set temperature range. For example, if the set temperature range is 10°C to 90°C and the amount of change in wavelength within this set temperature range is 8 nm, then the coefficient is 0.1 nm/°C.
  • the conditions are that the wavelength temperature coefficient is 0.12 nm/°C or less when the case temperature is in the range of 25°C to 90°C (condition 1), and that the optical spectrum of the laser light does not have multiple peaks (condition 2).
  • condition 1 the optical spectrum state that satisfies condition 2 is marked with a "o” and that that does not satisfy condition 2 is marked with an "x”.
  • the wavelength temperature coefficient is 0.18 nm/°C, which is the largest in the table of FIG. 11. In other words, when the thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51, the wavelength temperature coefficient is small.
  • the region R enclosed by the thick line frame in FIG. 11 is the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 that satisfy both conditions 1 and 2.
  • the thickness TB of the barrier layer 51 is 30 ⁇ or more and 60 ⁇ or less
  • the thickness TW of the well layer 52 is greater than 100 ⁇ and less than 130 ⁇ .
  • the thickness TB of the barrier layer 51 may be greater than 20 ⁇ and less than 90 ⁇ .
  • the wavelength temperature coefficient is 0.1 nm/°C or less, and the wavelength temperature dependence of the semiconductor laser device 10 is relatively small. Also, if the thickness TB of the barrier layer 51 is 40 ⁇ or more and 50 ⁇ or less, and the thickness TW of the well layer 52 is 120 ⁇ or more and 125 ⁇ or less, the wavelength temperature coefficient is 0.06 to 0.07 nm/°C, and the wavelength temperature dependence of the semiconductor laser device 10 is relatively small.
  • the wavelength temperature coefficient is 0.06 nm/°C, and the wavelength temperature dependence of the semiconductor laser device 10 is even smaller. Furthermore, if the thickness TB of the barrier layer 51 is 50 ⁇ and the thickness TW of the well layer 52 is 125 ⁇ , the wavelength temperature coefficient is 0.06 nm/°C, so the wavelength temperature dependence of the semiconductor laser device 10 becomes smaller.
  • Figure 12 shows the optical spectrum of the semiconductor laser device 10 in Experimental Example 1 shown in the table of Figure 11, where the thickness TW of the well layer 52 is 115 ⁇ and the thickness TB of the barrier layer 51 is 30 ⁇ .
  • the optical spectrum has one peak when the case temperature is between 10°C and 90°C.
  • Figure 13 shows the optical spectrum of the semiconductor laser device 10 in Experimental Example 1 shown in the table of Figure 11, where the thickness TW of the well layer 52 is 120 ⁇ and the thickness TB of the barrier layer 51 is 90 ⁇ .
  • the optical spectrum has multiple peaks. Furthermore, the wavelength of the peak shifts to the longer wavelength side as the case temperature increases from 10°C to 75°C, whereas at 85°C and 90°C, the wavelength is shorter than the peak wavelength at 10°C.
  • Fig. 14 is a table showing the change in optical output when the thickness TW of the well layer 52 is made thicker than 70 ⁇ , with the optical output being 100% when the thickness TW of the well layer 52 is 70 ⁇ .
  • the thickness TW of the well layer 52 when the thickness TW of the well layer 52 is in the range of 100 ⁇ or more and 130 ⁇ or less, the light output is 100% or more. On the other hand, when the thickness TW of the well layer 52 is 140 ⁇ , the light output is less than half, at 43%. For this reason, it is preferable that the thickness TW of the well layer 52 is less than 140 ⁇ . More preferably, the thickness TW of the well layer 52 is 130 ⁇ or less.
  • Example 3 In Experimental Example 3, the relationship between the emission width of the laser light and the wavelength temperature coefficient of the semiconductor laser device 10 was confirmed.
  • the thickness TW of the well layer 52 of the semiconductor laser device 10 is 115 ⁇
  • the thickness TB of the barrier layer 51 is 30 ⁇ .
  • the wavelength temperature coefficient is calculated in a case temperature range of 25°C or more and 90°C or less.
  • the wavelength temperature coefficient is 0.06 nm/°C to 0.08 nm/°C, and is 0.1 nm or less. More specifically, the wavelength temperature coefficient when the emission width is 50 ⁇ m is 0.06 nm/°C, the wavelength temperature coefficient when the emission width is 130 ⁇ m is 0.07 nm/°C, the wavelength temperature coefficient when the emission width is 225 ⁇ m is 0.08 nm/°C, the wavelength temperature coefficient when the emission width is 270 ⁇ m is 0.07 nm/°C, the wavelength temperature coefficient when the emission width is 290 ⁇ m is 0.06 nm/°C, and the wavelength temperature coefficient when the emission width is 300 ⁇ m is 0.06 nm/°C. In this way, if the emission width is 50 ⁇ m or 290 ⁇ m to 300 ⁇ m, the wavelength temperature coefficient is 0.06 nm/°C, and the wavelength temperature dependency of the semiconductor
  • the optical spectrum had one peak when the case temperature was in the range of 25°C or higher and 90°C or lower.
  • the semiconductor laser device 10 includes an active layer 41 including a barrier layer 51 and well layers 52 provided on both sides of the barrier layer 51 in the Z direction, which is the thickness direction of the barrier layer 51, and an n-type semiconductor layer 42 and a p-type semiconductor layer 43 that sandwich the active layer 41 in the Z direction.
  • the thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51. With this configuration, the wavelength temperature dependence of the semiconductor laser device 10 can be reduced by increasing the thickness TW of the well layer 52.
  • the thickness TW of the well layer 52 is greater than 100 ⁇ and less than 140 ⁇ . With this configuration, the thickness TW of the well layer 52 is greater than 100 ⁇ , so the wavelength temperature dependency of the semiconductor laser device 10 can be reduced. In addition, the thickness TW of the well layer 52 is less than 140 ⁇ , so the decrease in optical output can be suppressed.
  • the thickness TW of the well layer 52 is 110 ⁇ or more and 130 ⁇ or less.
  • the thickness TB of the barrier layer 51 is 30 ⁇ or more and 60 ⁇ or less.
  • the active layer 41 is configured so that the emission width at its end face (light-emitting portion end face 33) is 50 ⁇ m or more and 300 ⁇ m or less.
  • the well layer 52 in the active layer 41 has a thickness TW of 115 ⁇ , and the barrier layer 51 has a thickness TB of 30 ⁇ .
  • the wavelength temperature coefficient can be made 0.1 nm/°C or less, and the optical spectrum of the laser light can have one peak.
  • the semiconductor laser module 200 includes a semiconductor laser device 10, a stem 210 to which the semiconductor laser device 10 is attached, a cap 220 attached to the stem 210, covering the semiconductor laser device 10 and having an opening 221 through which the laser light from the semiconductor laser device 10 passes, and terminal pins 231-234 electrically connected to the semiconductor laser device 10.
  • the semiconductor laser device 10 is attached to the stem 210, so that heat from the semiconductor laser device 10 can be efficiently dissipated to the outside.
  • the semiconductor laser unit 100 including the semiconductor laser device 10 and the switching element 120 the semiconductor laser device 10 can be turned on and off at high speed, and the laser light can be easily pulsed.
  • the sensor 400 includes a semiconductor laser module 200, a bandpass filter 320, and a light receiving module 300 that receives light that has passed through the bandpass filter 320.
  • a semiconductor laser device 10 with small wavelength temperature dependency makes it possible to narrow the light transmission width of the bandpass filter 320. Therefore, the bandpass filter 320 transmits the laser light of the semiconductor laser device 10 but is less likely to transmit sunlight, thereby suppressing erroneous recognition by the sensor 400. This makes it possible to improve the measurement accuracy of the sensor 400.
  • FIG. 16 shows a semiconductor laser device 10 according to a first modified example.
  • the first electrode 81 extends from the electrode connection surface 31 of the light emitting portion 30 to the substrate covering portion 73 of the insulating film 70 that covers the substrate main surface 21.
  • the semiconductor laser device 10 can be driven by connecting a pillar, a wire, or the like to the first electrode 81 extending to the substrate main surface 21.
  • FIG. 17 shows a semiconductor laser device 10 according to a second modification.
  • the semiconductor laser device 10 like the semiconductor laser device 10 of the first modification shown in FIG. 16, the semiconductor laser device 10 has a first electrode 81 extending from the electrode connection surface 31 of the light emitting portion 30 to the substrate covering portion 73 of the insulating film 70 covering the substrate main surface 21.
  • the semiconductor laser device 10 of the second modification has a second opening 72X in the substrate covering portion 72 of the insulating film 70, which exposes a part of the substrate main surface 21 of the semiconductor substrate 20.
  • the second electrode 82 is electrically connected to the semiconductor substrate 20 exposed from the second opening 72X of the insulating film 70.
  • the light emitting portion 30 is connected to the substrate main surface 21 of the semiconductor substrate 20.
  • the second electrode 82 is electrically connected to the light emitting portion 30 via the semiconductor substrate 20.
  • the semiconductor laser device 10 of the second modification can be driven by the first electrode 81 and the second electrode 82 arranged on the substrate main surface 21 side.
  • the first electrode 81 and the second electrode 82 are on the main surface 21 side of the substrate, it is possible to connect wires or the like from the same direction, or to perform flip-chip mounting using pillars or the like.
  • the shape of the first electrode 81 can be the same as the shape of the first electrode 81 of the semiconductor laser device 10 of the above embodiment.
  • the shapes of the first electrode 81 and the second electrode 82 can be changed as appropriate.
  • the light-emitting section 30 includes three light-emitting units 40 and two tunnel layers 60.
  • the number of light-emitting units 40 is arbitrary and is not limited to three.
  • the light-emitting section 30 may have one, two, or four or more light-emitting units 40.
  • the number of tunnel layers 60 is adjusted according to the number of light-emitting units 40 and is not limited to two.
  • the capacitors 131 and 132 may be omitted from the semiconductor laser unit 100.
  • the switching element 120 may be omitted from the semiconductor laser unit 100.
  • the semiconductor laser module 200 has a CAN package structure in which the semiconductor laser unit 100 is attached to the stem 210 and covered by the cap 220, but the configuration of the semiconductor laser module 200 is not limited to this.
  • the semiconductor laser module 200 may have a light-transmitting sealing resin that seals the semiconductor laser device 10, the switching element 120, and the capacitors 131 and 132 on the substrate 110.
  • the semiconductor laser module 200 has a surface-mount type package structure.
  • the semiconductor laser module 200 of the above embodiment may be configured to include only the semiconductor laser device 10.
  • the semiconductor laser module may be configured in which the semiconductor laser device 10 is mounted on the heat sink 212 of the stem 210 using a submount 140.
  • the submount 140 is a support and a heat sink for the semiconductor laser device 10.
  • the submount 140 is formed of, for example, silicon or aluminum nitride.
  • the submount 140 is formed with a conductive path (not shown) such as a wiring pattern or a through hole for conducting the semiconductor laser device 10 and the heat sink 212.
  • the cap 220 is attached to the base 211 while covering the heat sink 212, the submount 140, and the semiconductor laser device 10.
  • the cap 220 has a transparent plate 222 attached to the opening 221 as in the above embodiment.
  • the semiconductor laser device 10 may be directly mounted on the heat sink 212.
  • the modified semiconductor laser module 200 has three terminal pins 236-238 instead of the four terminal pins 231-234.
  • Terminal pin 236 is a terminal pin that is electrically connected to the semiconductor laser device 10 via wire W5.
  • Terminal pin 237 is a terminal pin that is in an electrically floating state in the modified semiconductor laser module 200.
  • Terminal pin 238 is a terminal pin that is connected to the base 211.
  • a and B should be understood to mean “A only, or B only, or both A and B.”
  • the term “on” as used in this disclosure includes both the meanings of “on” and “above” unless the context clearly indicates otherwise.
  • the expression “a first member is formed on a second member” is intended to mean that in some embodiments, the first member may be directly disposed on the second member in contact with the second member, while in other embodiments, the first member may be disposed above the second member without contacting the second member. In other words, the term “on” does not exclude a structure in which another member is formed between the first member and the second member.
  • the Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction.
  • the various structures according to this disclosure are not limited to the "up” and “down” of the Z direction described in this specification being “up” and “down” in the vertical direction.
  • the X direction may be the vertical direction
  • the Y direction may be the vertical direction.
  • An active layer (41) including a barrier layer (51) and well layers (52) provided on both sides of the barrier layer (51) in a thickness direction (Z direction) of the barrier layer (51); an n-type semiconductor layer (42) and a p-type semiconductor layer (43) sandwiching the active layer (41) in a thickness direction (Z direction) of the active layer (41); A semiconductor laser device (10), wherein the well layer (52) has a thickness (TW) greater than a thickness (TB) of the barrier layer (51).
  • barrier layer (51) has a thickness (TB) of more than 0 ⁇ and not more than 60 ⁇ .
  • the active layer (41) includes an end face (33) for emitting light, and is configured to have an emission width at the end face (33) of 270 ⁇ m.
  • the active layer (41) includes an end face (33) for emitting light, and is configured to have an emission width at the end face (33) of 50 ⁇ m or more and 300 ⁇ m or less.
  • the well layer (52) is a first well layer (52A) adjacent to the barrier layer (51); a second well layer (52B) disposed on the opposite side of the barrier layer (51) to the first well layer (52A);
  • the active layer (41) is a first guide layer (53) sandwiched between the first well layer (52A) and the n-type semiconductor layer (42);
  • the n-type semiconductor layer (42) is a first n-type cladding layer (44) adjacent to the active layer (41); a second n-type cladding layer (45) disposed on the opposite side of the first n-type cladding layer (44) to the active layer (41);
  • the p-type semiconductor layer (43) is a first p-type cladding layer (46) adjacent to the active layer (41);
  • a semiconductor laser device (10) according to any one of appendices 1 to 12; a stem (210) on which the semiconductor laser device (10) is attached; a cap (220) attached to the stem (210), covering the semiconductor laser device (10) and having an opening (221) through which laser light from the semiconductor laser device (10) passes; A semiconductor laser module (200) comprising terminal pins (231 to 234) electrically connected to the semiconductor laser device (10).
  • a sensor (400) comprising a light receiving module (300) including a bandpass filter (320) and a light receiving element (310) that receives light that has passed through the bandpass filter (320).

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

This semiconductor laser device comprises: an active layer that includes a barrier layer and well layers which are provided respectively on both sides of the barrier layer in the thickness direction of the barrier layer; and an n-type semiconductor layer and a p-type semiconductor layer that sandwich the active layer therebetween in the thickness direction of the barrier layer. The thickness of the well layers is greater than the thickness of the barrier layer.

Description

半導体レーザ装置、半導体レーザモジュール、およびセンサSemiconductor laser device, semiconductor laser module, and sensor
 本開示は、半導体レーザ装置、半導体レーザモジュール、およびセンサに関する。 This disclosure relates to a semiconductor laser device, a semiconductor laser module, and a sensor.
 特許文献1には、半導体レーザ装置が開示されている。この半導体レーザ装置は、n型クラッド層、活性層、およびp型クラッド層を有するダブルヘテロ構造を含む。このような半導体レーザ装置は、活性層の端面からレーザ光を出射する。 Patent Document 1 discloses a semiconductor laser device. This semiconductor laser device includes a double heterostructure having an n-type cladding layer, an active layer, and a p-type cladding layer. Such a semiconductor laser device emits laser light from an end face of the active layer.
特開2019-186387号公報JP 2019-186387 A
 ところで、半導体レーザ装置のレーザ光の波長温度依存性を低減することが望まれている。 Incidentally, it is desirable to reduce the temperature dependency of the wavelength of the laser light from a semiconductor laser device.
 本開示の一態様である半導体レーザ装置は、バリア層と、前記バリア層の厚さ方向において前記バリア層の両側に設けられたウエル層と、を含む活性層と、前記活性層の厚さ方向において前記活性層を挟むn型半導体層およびp型半導体層と、を備え、前記ウエル層の厚さは、前記バリア層の厚さよりも厚い。 A semiconductor laser device according to one aspect of the present disclosure includes an active layer including a barrier layer and well layers provided on both sides of the barrier layer in the thickness direction of the barrier layer, and an n-type semiconductor layer and a p-type semiconductor layer sandwiching the active layer in the thickness direction of the active layer, and the thickness of the well layer is greater than the thickness of the barrier layer.
 本開示の一態様である半導体レーザモジュールは、前記半導体レーザ装置と、前記半導体レーザ装置が取り付けられたステムと、前記ステムに取り付けられ、前記半導体レーザ装置を覆うとともに前記半導体レーザ装置からのレーザ光が通過する開口部を有するキャップと、前記半導体レーザ装置と電気的に接続された端子ピンと、を備える。 A semiconductor laser module according to one aspect of the present disclosure includes the semiconductor laser device, a stem to which the semiconductor laser device is attached, a cap attached to the stem, covering the semiconductor laser device and having an opening through which laser light from the semiconductor laser device passes, and a terminal pin electrically connected to the semiconductor laser device.
 本開示の一態様であるセンサは、前記半導体レーザモジュールと、バンドパスフィルタと、前記バンドパスフィルタを通過した光を受光する受光素子と、を含む受光モジュールと、を備える。 A sensor according to one aspect of the present disclosure includes the semiconductor laser module, a bandpass filter, and a light receiving module including a light receiving element that receives light that has passed through the bandpass filter.
 上記半導体レーザ装置、半導体レーザモジュール、およびセンサによれば、レーザ光の波長温度依存性を低減することができる。 The above-mentioned semiconductor laser device, semiconductor laser module, and sensor can reduce the temperature dependence of the wavelength of laser light.
図1は、一実施形態の半導体レーザ装置を示す斜視図である。FIG. 1 is a perspective view showing a semiconductor laser device according to an embodiment. 図2は、図1に示す半導体レーザ装置のF2-F2線で切断した断面図である。FIG. 2 is a cross-sectional view of the semiconductor laser device shown in FIG. 1 taken along line F2-F2. 図3は、図2に示す発光ユニットの一構造例を示す説明図である。FIG. 3 is an explanatory diagram showing an example of the structure of the light-emitting unit shown in FIG. 図4は、図3に示す活性層の一構造例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of the structure of the active layer shown in FIG. 図5は、図2に示すトンネル層の一構造例を示す説明図である。FIG. 5 is an explanatory diagram showing an example of the structure of the tunnel layer shown in FIG. 図6は、半導体レーザ装置を備える半導体レーザモジュールを示す斜視図である。FIG. 6 is a perspective view showing a semiconductor laser module including a semiconductor laser device. 図7は、図6に示す半導体レーザモジュールの断面図である。FIG. 7 is a cross-sectional view of the semiconductor laser module shown in FIG. 図8は、半導体レーザ装置が搭載された半導体レーザユニットを示す平面図である。FIG. 8 is a plan view showing a semiconductor laser unit on which a semiconductor laser device is mounted. 図9は、図8の半導体レーザユニットを示す裏面図である。FIG. 9 is a rear view showing the semiconductor laser unit of FIG. 図10は、半導体レーザモジュールを備えるセンサの一構造例を示す説明図である。FIG. 10 is an explanatory diagram showing an example of the structure of a sensor equipped with a semiconductor laser module. 図11は、ウエル層の厚さおよびバリア層の厚さとレーザ光の波長温度係数および光スペクトルとの関係を示す表である。FIG. 11 is a table showing the relationship between the thickness of the well layer and the thickness of the barrier layer and the wavelength temperature coefficient and optical spectrum of the laser light. 図12は、図11の領域Rに含まれる半導体レーザ装置について、各10℃から90℃の温度における波長に対する発光強度の光スペクトルを示すグラフである。FIG. 12 is a graph showing the optical spectrum of the emission intensity versus wavelength at temperatures from 10° C. to 90° C. for the semiconductor laser device included in region R of FIG. 図13は、図11の領域R外の半導体レーザ装置について、各10℃から90℃の温度における波長に対する発光強度の光スペクトルを示すグラフである。FIG. 13 is a graph showing optical spectra of emission intensity versus wavelength at temperatures from 10° C. to 90° C. for a semiconductor laser device outside the region R in FIG. 図14は、ウエル層の厚さと光出力との関係を示す表である。FIG. 14 is a table showing the relationship between the well layer thickness and the optical output. 図15は、レーザ光の発光幅と波長温度係数との関係を示す表である。FIG. 15 is a table showing the relationship between the emission width of the laser light and the wavelength temperature coefficient. 図16は、第1変更例の半導体レーザ装置を示す断面図である。FIG. 16 is a cross-sectional view showing a semiconductor laser device according to a first modified example. 図17は、第2変更例の半導体レーザ装置を示す断面図である。FIG. 17 is a cross-sectional view showing a semiconductor laser device according to a second modification. 図18は、変更例の半導体レーザモジュールを示す斜視図である。FIG. 18 is a perspective view showing a semiconductor laser module according to a modified example. 図19は、図18に示す半導体レーザモジュールの断面図である。FIG. 19 is a cross-sectional view of the semiconductor laser module shown in FIG.
 以下、添付図面を参照して本開示の半導体レーザ装置、半導体レーザモジュール、およびセンサの実施形態を説明する。なお、説明を簡単かつ明確にするため、図面に示される構成要素は必ずしも一定の縮尺で描かれていない。また、理解を容易にするため、断面図では、ハッチング線が省略されている場合がある。添付図面は、本開示の実施形態を例示するものに過ぎず、本開示を制限するものとみなされるべきではない。 Below, embodiments of the semiconductor laser device, semiconductor laser module, and sensor of the present disclosure will be described with reference to the attached drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatched lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.
 以下の詳細な記載は、本開示の例示的な実施形態を具体化する装置、システム、および方法を含む。この詳細な記載は、本来説明のためのものに過ぎず、本開示の実施形態またはこのような実施形態の適用および使用を限定することを意図していない。 The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. The detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.
 [半導体レーザ装置の構成]
 図1~図5を参照して、一実施形態の半導体レーザ装置10の構成について説明する。
 図1は半導体レーザ装置10の斜視構造を示し、図2は図1の半導体レーザ装置の断面構造を示している。図3は図2の発光ユニットの一構造例を模式的に示し、図4は図3に示す活性層の一構造例を模式的に示し、図5は図2のトンネル層の一構造例を模式的に示している。
[Configuration of Semiconductor Laser Device]
The configuration of a semiconductor laser device 10 according to one embodiment will be described with reference to FIGS.
Fig. 1 shows a perspective structure of a semiconductor laser device 10, and Fig. 2 shows a cross-sectional structure of the semiconductor laser device of Fig. 1. Fig. 3 shows a schematic example of a structure of the light emitting unit of Fig. 2, Fig. 4 shows a schematic example of a structure of the active layer shown in Fig. 3, and Fig. 5 shows a schematic example of a structure of the tunnel layer of Fig. 2.
 図1および図2に示すように、半導体レーザ装置10は、半導体基板20、発光部30、絶縁膜70、第1電極81、および第2電極82を有する。
 半導体基板20は、たとえば長方形板状に形成されている。半導体基板20は、たとえばGaAs(ガリウム-ヒ素)を含むn型の半導体基板(n-GaAs基板)によって構成されている。半導体基板20は、n型不純物としてたとえばSi(シリコン)、Te(テルル)、Se(セレン)の少なくとも1種を含む。
As shown in FIGS. 1 and 2, the semiconductor laser device 10 has a semiconductor substrate 20, a light emitting portion 30, an insulating film 70, a first electrode 81, and a second electrode 82.
The semiconductor substrate 20 is formed, for example, in the shape of a rectangular plate. The semiconductor substrate 20 is configured, for example, of an n-type semiconductor substrate (n-GaAs substrate) containing GaAs (gallium arsenide). The semiconductor substrate 20 contains at least one of Si (silicon), Te (tellurium), and Se (selenium) as an n-type impurity.
 半導体基板20は、基板主面21、基板裏面22、および基板側面23~26を有する。基板主面21と基板裏面22とは、互いに反対側を向いている。以降では、基板主面21と垂直な方向を「Z方向」とし、Z方向と直交する方向のうち互いに直交する2方向をそれぞれ「X方向」および「Y方向」とする。Z方向は、半導体基板20の厚さ方向であるといえる。基板側面23,24はY方向において互いに反対側を向いており、基板側面25,26はX方向において互いに反対側を向いている。半導体基板20は、Z方向から視て、Y方向に長い長方形状に形成されている。 The semiconductor substrate 20 has a substrate main surface 21, a substrate back surface 22, and substrate side surfaces 23 to 26. The substrate main surface 21 and the substrate back surface 22 face in opposite directions. Hereinafter, the direction perpendicular to the substrate main surface 21 will be referred to as the "Z direction", and the two directions perpendicular to the Z direction will be referred to as the "X direction" and "Y direction", respectively. The Z direction can be said to be the thickness direction of the semiconductor substrate 20. The substrate side surfaces 23 and 24 face in opposite directions in the Y direction, and the substrate side surfaces 25 and 26 face in opposite directions in the X direction. When viewed from the Z direction, the semiconductor substrate 20 is formed in a rectangular shape that is long in the Y direction.
 発光部30は、半導体基板20の基板主面21に設けられている。発光部30は、基板主面21から基板裏面22とは反対側に向けて突出している。
 発光部30は、電極接続面31、基板接続面32、発光部端面33,34、および発光部側面35,36を有する。電極接続面31は、Z方向において、基板主面21と同じ方向を向いている。電極接続面31は、基板主面21に対してZ方向に離隔して配置されている。基板接続面32は、半導体基板20の側を向いており、基板主面21に接続されている。発光部側面35,36は、X方向において互いに反対側を向いている。発光部側面35,36は、電極接続面31と基板主面21とを接続している。発光部端面33,34は、Y方向において互いに反対側を向いている。発光部端面33,34は、共振器端面を構成している。一例では、発光部30は、発光部端面33からレーザ光L1を出射する。
The light emitting portion 30 is provided on a substrate main surface 21 of a semiconductor substrate 20. The light emitting portion 30 protrudes from the substrate main surface 21 toward the side opposite to the substrate back surface 22.
The light emitting unit 30 has an electrode connection surface 31, a substrate connection surface 32, light emitting unit end surfaces 33, 34, and light emitting unit side surfaces 35, 36. The electrode connection surface 31 faces the same direction as the substrate main surface 21 in the Z direction. The electrode connection surface 31 is disposed apart from the substrate main surface 21 in the Z direction. The substrate connection surface 32 faces the semiconductor substrate 20 side and is connected to the substrate main surface 21. The light emitting unit side surfaces 35, 36 face opposite each other in the X direction. The light emitting unit side surfaces 35, 36 connect the electrode connection surface 31 and the substrate main surface 21. The light emitting unit end surfaces 33, 34 face opposite each other in the Y direction. The light emitting unit end surfaces 33, 34 constitute resonator end surfaces. In one example, the light emitting unit 30 emits laser light L1 from the light emitting unit end surface 33.
 本実施形態において、発光部30は、メサ構造を有し、Y方向から視て、基板主面21から突出した台形状(リッジ状)に形成されている。発光部側面35は、基板側面25が向く方向に対して、電極接続面31の側を向くように傾いている。発光部側面36は、基板側面26が向く方向に対して、電極接続面31の側を向くように傾いている。このため、発光部30は、Y方向から視て、基板主面21と接続される基板接続面32の幅に対して、電極接続面31の幅が狭い台形状に形成されている。 In this embodiment, the light emitting section 30 has a mesa structure and is formed in a trapezoidal shape (ridge shape) protruding from the substrate main surface 21 when viewed from the Y direction. The light emitting section side surface 35 is inclined so as to face the electrode connection surface 31 side with respect to the direction in which the substrate side surface 25 faces. The light emitting section side surface 36 is inclined so as to face the electrode connection surface 31 side with respect to the direction in which the substrate side surface 26 faces. Therefore, when viewed from the Y direction, the light emitting section 30 is formed in a trapezoidal shape in which the width of the electrode connection surface 31 is narrower than the width of the substrate connection surface 32 that is connected to the substrate main surface 21.
 図1に示すように、発光部30は、Y方向に延びている。一例では、Y方向における発光部30の長さは、半導体基板20の長さと等しい。つまり、発光部30の発光部端面33は半導体基板20の基板側面23と面一であり、発光部端面34は半導体基板20の基板側面24と面一である。 As shown in FIG. 1, the light emitting section 30 extends in the Y direction. In one example, the length of the light emitting section 30 in the Y direction is equal to the length of the semiconductor substrate 20. In other words, the light emitting section end surface 33 of the light emitting section 30 is flush with the substrate side surface 23 of the semiconductor substrate 20, and the light emitting section end surface 34 is flush with the substrate side surface 24 of the semiconductor substrate 20.
 絶縁膜70は、半導体基板20の基板主面21の一部を覆うように形成されている。また、絶縁膜70は、発光部30を覆うように形成されている。本実施形態において、絶縁膜70は、発光部30の電極接続面31と発光部側面35,36とを覆うように形成されている。本実施形態の絶縁膜70は、半導体基板20の基板主面21を覆う基板被覆部72,73と、発光部30を覆う発光部被覆部74とを有する。絶縁膜70は、たとえばSiN(窒化シリコン)、SiO(酸化シリコン)等によって構成されている。 The insulating film 70 is formed so as to cover a part of the substrate main surface 21 of the semiconductor substrate 20. The insulating film 70 is also formed so as to cover the light emitting portion 30. In this embodiment, the insulating film 70 is formed so as to cover the electrode connection surface 31 and the light emitting portion side surfaces 35, 36 of the light emitting portion 30. The insulating film 70 of this embodiment has substrate covering portions 72, 73 that cover the substrate main surface 21 of the semiconductor substrate 20, and a light emitting portion covering portion 74 that covers the light emitting portion 30. The insulating film 70 is made of, for example, SiN (silicon nitride), SiO 2 (silicon oxide), or the like.
 図1および図2に示すように、第1電極81は、発光部30の電極接続面31を覆う絶縁膜70の上面71に設けられている。図2に示すように、発光部30の電極接続面31を覆う絶縁膜70は、電極接続面31の一部を露出する第1開口部71Xを有する。第1電極81は、絶縁膜70の第1開口部71Xから露出する電極接続面31に電気的に接続されている。つまり、第1電極81は、発光部30と電気的に接続されている。第1電極81は、絶縁膜70の第1開口部71Xを形成する端部を覆うように形成されている。 As shown in Figures 1 and 2, the first electrode 81 is provided on the upper surface 71 of the insulating film 70 that covers the electrode connection surface 31 of the light-emitting section 30. As shown in Figure 2, the insulating film 70 that covers the electrode connection surface 31 of the light-emitting section 30 has a first opening 71X that exposes a portion of the electrode connection surface 31. The first electrode 81 is electrically connected to the electrode connection surface 31 exposed from the first opening 71X of the insulating film 70. In other words, the first electrode 81 is electrically connected to the light-emitting section 30. The first electrode 81 is formed so as to cover the end that forms the first opening 71X of the insulating film 70.
 第1電極81は、複数の電極層によって構成されていてもよい。一例では、第1電極81は、第1電極層と第2電極層とを含む。第1電極層と第2電極層とは、電極接続面31の側からこの順番で積層されている。第1電極層は、たとえばTi(チタン)/Au(金)によって構成されている。第2電極層は、たとえばAuを含むめっき層である。 The first electrode 81 may be composed of multiple electrode layers. In one example, the first electrode 81 includes a first electrode layer and a second electrode layer. The first electrode layer and the second electrode layer are laminated in this order from the electrode connection surface 31 side. The first electrode layer is composed of, for example, Ti (titanium)/Au (gold). The second electrode layer is, for example, a plating layer containing Au.
 図1および図2に示すように、第2電極82は、半導体基板20の基板裏面22に設けられている。本実施形態では、第2電極82は、基板裏面22の全面を覆っている。第2電極82は、半導体基板20に電気的に接続されている。 As shown in Figures 1 and 2, the second electrode 82 is provided on the rear surface 22 of the semiconductor substrate 20. In this embodiment, the second electrode 82 covers the entire rear surface 22 of the substrate. The second electrode 82 is electrically connected to the semiconductor substrate 20.
 第2電極82は、複数の電極層によって構成されていてもよい。一例では、第2電極82は、Ni(ニッケル)層、AuGe(金-ゲルマニウム合金)層、Ti層、およびAu層のうち少なくとも1つを含んでいてもよい。一例では、第2電極82は、基板裏面22から順に積層されたNi層、AuGe層、Ti層、およびAu層を含んでいてもよい。 The second electrode 82 may be composed of multiple electrode layers. In one example, the second electrode 82 may include at least one of a Ni (nickel) layer, an AuGe (gold-germanium alloy) layer, a Ti layer, and an Au layer. In one example, the second electrode 82 may include a Ni layer, an AuGe layer, a Ti layer, and an Au layer stacked in this order from the rear surface 22 of the substrate.
 [発光部]
 次に、発光部30の詳細な構成について説明する。
 図2に示すように、発光部30は、半導体基板20の基板主面21の上に積層された発光ユニット40を含む。発光ユニット40は、正孔および電子の結合によって光を生成する。本実施形態の発光部30は、3つの発光ユニット40を有する。なお、発光部30は、少なくとも1つの発光ユニット40を有する構成であってもよい。つまり、発光ユニット40の数は、1つ、2つ、または4つ以上であってもよい。
[Light-emitting section]
Next, the detailed configuration of the light-emitting unit 30 will be described.
2, the light-emitting section 30 includes light-emitting units 40 stacked on the substrate main surface 21 of the semiconductor substrate 20. The light-emitting units 40 generate light by recombination of holes and electrons. The light-emitting section 30 of this embodiment has three light-emitting units 40. Note that the light-emitting section 30 may have at least one light-emitting unit 40. In other words, the number of light-emitting units 40 may be one, two, or four or more.
 本実施形態の発光部30は、互いに隣り合う発光ユニット40の間に配置されたトンネル層60を含む。トンネル層60は、トンネル効果に起因するトンネル電流を生成し、発光ユニット40に供給する。本実施形態の発光部30は、2つのトンネル層60を含む。トンネル層60は、互いに隣り合う2つの発光ユニット40の間に配置されている。 The light-emitting section 30 of this embodiment includes a tunnel layer 60 disposed between adjacent light-emitting units 40. The tunnel layer 60 generates a tunnel current due to the tunnel effect and supplies it to the light-emitting unit 40. The light-emitting section 30 of this embodiment includes two tunnel layers 60. The tunnel layer 60 is disposed between two adjacent light-emitting units 40.
 発光部30から出射されるレーザ光L1(図1参照)の発光幅は、たとえば50μm以上300μm以下である。本実施形態では、発光幅は270μmである。ここで、発光幅は、発光部30の発光部端面33におけるレーザ光L1のX方向の長さによって定義できる。 The emission width of the laser light L1 (see FIG. 1) emitted from the light-emitting unit 30 is, for example, 50 μm or more and 300 μm or less. In this embodiment, the emission width is 270 μm. Here, the emission width can be defined by the length in the X direction of the laser light L1 at the light-emitting end surface 33 of the light-emitting unit 30.
 図3は、発光ユニット40の一構造例を示している。
 発光ユニット40は、活性層41と、活性層41の厚さ方向において、活性層41を挟むn型半導体層42およびp型半導体層43とを含む。ここで、本実施形態では、活性層41の厚さ方向はZ方向と一致している。また、発光部30の発光部端面33は、活性層41の端面を含む。このため、活性層41は、レーザ光を出射する端面を含むともいえる。
FIG. 3 shows an example of the structure of the light-emitting unit 40 .
The light-emitting unit 40 includes an active layer 41, and an n-type semiconductor layer 42 and a p-type semiconductor layer 43 which sandwich the active layer 41 in the thickness direction of the active layer 41. In this embodiment, the thickness direction of the active layer 41 coincides with the Z direction. The light-emitting section end surface 33 of the light-emitting section 30 includes an end surface of the active layer 41. For this reason, it can be said that the active layer 41 includes an end surface that emits laser light.
 n型半導体層42は、活性層41に対して図1および図2に示す半導体基板20の側に配置されている。p型半導体層43は、活性層41に対して、n型半導体層42とは反対側、つまり、図1および図2に示す第1電極81の側に配置されている。このため、発光ユニット40は、半導体基板20の側から順に積層されたn型半導体層42と活性層41とp型半導体層43とを含む積層構造を有するといえる。 The n-type semiconductor layer 42 is disposed on the side of the active layer 41 that faces the semiconductor substrate 20 shown in Figures 1 and 2. The p-type semiconductor layer 43 is disposed on the side of the active layer 41 that faces the opposite side to the n-type semiconductor layer 42, that is, on the side of the first electrode 81 shown in Figures 1 and 2. For this reason, it can be said that the light-emitting unit 40 has a layered structure that includes the n-type semiconductor layer 42, the active layer 41, and the p-type semiconductor layer 43, which are layered in this order from the semiconductor substrate 20 side.
 n型半導体層42は、AlGaAs(アルミニウム-ガリウム-ヒ素)を含む。n型半導体層42は、n型不純物として、たとえばSi、Te、およびSeの少なくとも1種を含む。n型半導体層42の不純物濃度は、たとえば1×1017cm-3以上1×1019cm-3以下である。 The n-type semiconductor layer 42 includes aluminum gallium arsenide (AlGaAs). The n-type semiconductor layer 42 includes at least one of Si, Te, and Se as an n-type impurity. The impurity concentration of the n-type semiconductor layer 42 is, for example, not less than 1×10 17 cm −3 and not more than 1×10 19 cm −3 .
 n型半導体層42は、第1n型クラッド層44と第2n型クラッド層45とを含む。第1n型クラッド層44は、活性層41に隣り合うように配置されている。第2n型クラッド層45は、第1n型クラッド層44に対して活性層41とは反対側に配置されている。つまり、n型半導体層42は、活性層41に隣り合う第1n型クラッド層44と、第1n型クラッド層44に対して活性層41とは反対側に位置する第2n型クラッド層45とを含むといえる。また、n型半導体層42は、活性層41の側からこの順に積層された第1n型クラッド層44および第2n型クラッド層45を含むともいえる。 The n-type semiconductor layer 42 includes a first n-type cladding layer 44 and a second n-type cladding layer 45. The first n-type cladding layer 44 is disposed adjacent to the active layer 41. The second n-type cladding layer 45 is disposed on the opposite side of the active layer 41 with respect to the first n-type cladding layer 44. In other words, it can be said that the n-type semiconductor layer 42 includes the first n-type cladding layer 44 adjacent to the active layer 41, and the second n-type cladding layer 45 located on the opposite side of the active layer 41 with respect to the first n-type cladding layer 44. It can also be said that the n-type semiconductor layer 42 includes the first n-type cladding layer 44 and the second n-type cladding layer 45 stacked in this order from the active layer 41 side.
 第1n型クラッド層44は、Al組成A1を有するAlA1Ga(1-A1)Asを含む。一例では、第1n型クラッド層44のAl組成A1は、0.2以上0.5以下である。第2n型クラッド層45は、第1n型クラッド層44のAl組成A1とは異なるAl組成A2を有するAlA2Ga(1-A2)Asを含む。第2n型クラッド層45のAl組成A2は、第1n型クラッド層44のAl組成A1よりも大きい(A2>A1)。一例では、第2n型クラッド層45のAl組成A2は、0.4以上0.7以下である。 The first n-type cladding layer 44 includes Al A1 Ga (1-A1) As having an Al composition A1. In one example, the Al composition A1 of the first n-type cladding layer 44 is 0.2 or more and 0.5 or less. The second n-type cladding layer 45 includes Al A2 Ga (1-A2) As having an Al composition A2 different from the Al composition A1 of the first n-type cladding layer 44. The Al composition A2 of the second n-type cladding layer 45 is larger than the Al composition A1 of the first n-type cladding layer 44 (A2>A1). In one example, the Al composition A2 of the second n-type cladding layer 45 is 0.4 or more and 0.7 or less.
 本実施形態では、第2n型クラッド層45の不純物濃度は、第1n型クラッド層44の不純物濃度と異なる。より詳細には、第2n型クラッド層45の不純物濃度は、第1n型クラッド層44の不純物濃度よりも高い。なお、第2n型クラッド層45の不純物濃度は、第1n型クラッド層44の不純物濃度と等しくてもよい。また、第2n型クラッド層45の不純物濃度は、第1n型クラッド層44の不純物濃度よりも低くてもよい。 In this embodiment, the impurity concentration of the second n-type cladding layer 45 is different from the impurity concentration of the first n-type cladding layer 44. More specifically, the impurity concentration of the second n-type cladding layer 45 is higher than the impurity concentration of the first n-type cladding layer 44. The impurity concentration of the second n-type cladding layer 45 may be equal to the impurity concentration of the first n-type cladding layer 44. The impurity concentration of the second n-type cladding layer 45 may also be lower than the impurity concentration of the first n-type cladding layer 44.
 p型半導体層43は、AlGaAsを含む。p型半導体層43は、p型不純物として、たとえばC(炭素)を含む。p型半導体層43の不純物濃度は、たとえば1×1017cm-3以上1×1019cm-3以下である。 P-type semiconductor layer 43 includes AlGaAs. P-type semiconductor layer 43 includes p-type impurities, for example, C (carbon). The impurity concentration of p-type semiconductor layer 43 is, for example, not less than 1×10 17 cm −3 and not more than 1×10 19 cm −3 .
 p型半導体層43は、第1p型クラッド層46と第2p型クラッド層47とを含む。第1p型クラッド層46は、活性層41に隣り合うように配置されている。第2p型クラッド層47は、第1p型クラッド層46に対して活性層41とは反対側に配置されている。つまり、p型半導体層43は、活性層41に隣り合う第1p型クラッド層46と、第1p型クラッド層46に対して活性層41とは反対側に位置する第2p型クラッド層47とを含むといえる。また、p型半導体層43は、活性層41の側からこの順に積層された第1p型クラッド層46および第2p型クラッド層47を含むともいえる。 The p-type semiconductor layer 43 includes a first p-type cladding layer 46 and a second p-type cladding layer 47. The first p-type cladding layer 46 is disposed adjacent to the active layer 41. The second p-type cladding layer 47 is disposed on the opposite side of the active layer 41 with respect to the first p-type cladding layer 46. In other words, it can be said that the p-type semiconductor layer 43 includes the first p-type cladding layer 46 adjacent to the active layer 41, and the second p-type cladding layer 47 located on the opposite side of the active layer 41 with respect to the first p-type cladding layer 46. It can also be said that the p-type semiconductor layer 43 includes the first p-type cladding layer 46 and the second p-type cladding layer 47 stacked in this order from the active layer 41 side.
 第1p型クラッド層46は、Al組成B1を有するAlB1Ga(1-B1)Asを含む。一例では、第1p型クラッド層46のAl組成B1は、0.2以上0.5以下である。第2p型クラッド層47は、第1p型クラッド層46のAl組成B1とは異なるAl組成B2を有するAlB2Ga(1-B2)Asを含む。第2p型クラッド層47のAl組成B2は、第1p型クラッド層46のAl組成B1よりも大きい(B2>B1)。一例では、第2p型クラッド層47のAl組成B2は、0.4以上0.7以下である。 The first p-type cladding layer 46 includes Al B1 Ga (1-B1) As having an Al composition B1. In one example, the Al composition B1 of the first p-type cladding layer 46 is 0.2 or more and 0.5 or less. The second p-type cladding layer 47 includes Al B2 Ga (1-B2) As having an Al composition B2 different from the Al composition B1 of the first p-type cladding layer 46. The Al composition B2 of the second p-type cladding layer 47 is larger than the Al composition B1 of the first p-type cladding layer 46 (B2>B1). In one example, the Al composition B2 of the second p-type cladding layer 47 is 0.4 or more and 0.7 or less.
 本実施形態では、第2p型クラッド層47の不純物濃度は、第1p型クラッド層46の不純物濃度と異なる。より詳細には、第2p型クラッド層47の不純物濃度は、第1p型クラッド層46の不純物濃度よりも高い。なお、第2p型クラッド層47の不純物濃度は、第1p型クラッド層46の不純物濃度と等しくてもよい。また、第2p型クラッド層47の不純物濃度は、第1p型クラッド層46の不純物濃度よりも低くてもよい。 In this embodiment, the impurity concentration of the second p-type cladding layer 47 is different from the impurity concentration of the first p-type cladding layer 46. More specifically, the impurity concentration of the second p-type cladding layer 47 is higher than the impurity concentration of the first p-type cladding layer 46. The impurity concentration of the second p-type cladding layer 47 may be equal to the impurity concentration of the first p-type cladding layer 46. The impurity concentration of the second p-type cladding layer 47 may be lower than the impurity concentration of the first p-type cladding layer 46.
 図4は、活性層41の構成の一例を示している。
 活性層41は、バリア層51と、バリア層51の厚さ方向においてバリア層51の両側に設けられたウエル層52とを含む。ウエル層52は量子井戸層であり、バリア層51はウエル層52間のキャリア(電子および正孔)の移動に対する障壁となる障壁層である。ここで、バリア層51の厚さ方向はZ方向と一致している。また、バリア層51の両側に設けられたウエル層52を便宜上、「第1ウエル層52A」および「第2ウエル層52B」とする。この場合、活性層41は、バリア層51、第1ウエル層52A、および第2ウエル層52Bを含む多重量子井戸構造を有する。
FIG. 4 shows an example of the configuration of the active layer 41 .
The active layer 41 includes a barrier layer 51 and well layers 52 provided on both sides of the barrier layer 51 in the thickness direction of the barrier layer 51. The well layer 52 is a quantum well layer, and the barrier layer 51 is a barrier layer that acts as a barrier against the movement of carriers (electrons and holes) between the well layers 52. Here, the thickness direction of the barrier layer 51 coincides with the Z direction. For convenience, the well layers 52 provided on both sides of the barrier layer 51 are referred to as a "first well layer 52A" and a "second well layer 52B". In this case, the active layer 41 has a multiple quantum well structure including the barrier layer 51, the first well layer 52A, and the second well layer 52B.
 第1ウエル層52Aと第2ウエル層52Bとは、バリア層51を挟んで配置されている。第1ウエル層52Aは、バリア層51に対して、図3に示すn型半導体層42の側に、バリア層51と隣り合うように配置されている。第2ウエル層52Bは、バリア層51に対して、第1ウエル層52Aとは反対側に配置されている。つまり、活性層41は、図3に示すn型半導体層42(第1n型クラッド層44)からこの順に積層された第1ウエル層52A、バリア層51、および第2ウエル層52Bを含むといえる。 The first well layer 52A and the second well layer 52B are arranged with the barrier layer 51 in between. The first well layer 52A is arranged adjacent to the barrier layer 51 on the side of the n-type semiconductor layer 42 shown in FIG. 3 with respect to the barrier layer 51. The second well layer 52B is arranged on the opposite side of the barrier layer 51 to the first well layer 52A. In other words, it can be said that the active layer 41 includes the first well layer 52A, the barrier layer 51, and the second well layer 52B, which are stacked in this order from the n-type semiconductor layer 42 (first n-type cladding layer 44) shown in FIG. 3.
 本実施形態の活性層41は、第1ガイド層53および第2ガイド層54をさらに含む。
 第1ガイド層53は、第1ウエル層52Aと隣り合うように配置されている。第1ガイド層53は、第1ウエル層52Aに対して、バリア層51とは反対側に配置されている。第2ガイド層54は、第2ウエル層52Bと隣り合うように配置されている。第2ガイド層54は、第2ウエル層52Bに対して、バリア層51とは反対側に配置されている。第1ガイド層53と第2ガイド層54とは、第1ウエル層52A、バリア層51、および第2ウエル層52Bを挟むように配置されているといえる。また、本実施形態では、活性層41は、図3に示すn型半導体層42(第1n型クラッド層44)からこの順に積層された第1ガイド層53、第1ウエル層52A、バリア層51、第2ウエル層52B、および第2ガイド層54を含むといえる。
The active layer 41 of this embodiment further includes a first guiding layer 53 and a second guiding layer 54 .
The first guide layer 53 is disposed adjacent to the first well layer 52A. The first guide layer 53 is disposed on the opposite side of the barrier layer 51 with respect to the first well layer 52A. The second guide layer 54 is disposed adjacent to the second well layer 52B. The second guide layer 54 is disposed on the opposite side of the barrier layer 51 with respect to the second well layer 52B. It can be said that the first guide layer 53 and the second guide layer 54 are disposed to sandwich the first well layer 52A, the barrier layer 51, and the second well layer 52B. In this embodiment, it can be said that the active layer 41 includes the first guide layer 53, the first well layer 52A, the barrier layer 51, the second well layer 52B, and the second guide layer 54, which are stacked in this order from the n-type semiconductor layer 42 (first n-type cladding layer 44) shown in FIG. 3.
 バリア層51は、AlGaAsを含む。バリア層51は、Al組成C1を有するAlC1Ga(1-C1)Asを含む。バリア層51のAl組成C1は、n型半導体層42のAl組成(Al組成A1,A2)、p型半導体層43のAl組成(Al組成B1,B2)と異なる。バリア層51のAl組成C1は、n型半導体層42のAl組成(Al組成A1,A2)、p型半導体層43のAl組成(Al組成B1,B2)よりも小さい。一例では、バリア層51のAl組成C1は、0.05以上0.3以下である。バリア層51は、不純物無添加であってもよい。 The barrier layer 51 includes AlGaAs. The barrier layer 51 includes Al C1 Ga (1-C1) As having an Al composition C1. The Al composition C1 of the barrier layer 51 is different from the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42 and the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43. The Al composition C1 of the barrier layer 51 is smaller than the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42 and the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43. In one example, the Al composition C1 of the barrier layer 51 is 0.05 or more and 0.3 or less. The barrier layer 51 may be free of impurities.
 第1ウエル層52Aは、In組成D1を有するInD1Ga(1-D1)Asを含む。一例では、In組成D1は、0よりも大きく0.15以下である。なお、第1ウエル層52Aは、不純物無添加であってもよい。 The first well layer 52A includes In D1 Ga (1-D1) As having an In composition D1. In one example, the In composition D1 is greater than 0 and equal to or less than 0.15. The first well layer 52A may be undoped.
 第2ウエル層52Bは、In組成D2を有するInD2Ga(1-D2)Asを含む。In組成D2は、第1ウエル層52AのIn組成D1と等しくてもよい。一例では、In組成D2は、0よりも大きく0.15以下である。なお、第2ウエル層52Bは、不純物無添加であってもよい。 The second well layer 52B includes In D2 Ga (1-D2) As having an In composition D2. The In composition D2 may be equal to the In composition D1 of the first well layer 52A. In one example, the In composition D2 is greater than 0 and equal to or less than 0.15. The second well layer 52B may be undoped.
 第1ガイド層53は、AlGaAsを含む。第1ガイド層53は、Al組成C2を有するAlC2Ga(1-C2)Asを含む。第1ガイド層53のAl組成C2は、n型半導体層42のAl組成(Al組成A1,A2)と異なる。第1ガイド層53のAl組成C2は、n型半導体層42のAl組成(Al組成A1,A2)よりも小さい。一例では、第1ガイド層53のAl組成C2は、0.05以上0.3以下である。なお、第1ガイド層53は、不純物無添加であってもよい。 The first guide layer 53 includes AlGaAs. The first guide layer 53 includes Al C2 Ga (1-C2) As having an Al composition C2. The Al composition C2 of the first guide layer 53 is different from the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42. The Al composition C2 of the first guide layer 53 is smaller than the Al composition (Al compositions A1, A2) of the n-type semiconductor layer 42. In one example, the Al composition C2 of the first guide layer 53 is 0.05 or more and 0.3 or less. The first guide layer 53 may be free of impurities.
 第2ガイド層54は、AlGaAsを含む。第2ガイド層54は、Al組成C3を有するAlC3Ga(1-C3)Asを含む。第2ガイド層54のAl組成C3は、p型半導体層43のAl組成(Al組成B1,B2)と異なる。第2ガイド層54のAl組成C3は、p型半導体層43のAl組成(Al組成B1,B2)よりも小さい。また、第2ガイド層54のAl組成C3は、第1ガイド層53のAl組成C2と等しくてもよい。一例では、第2ガイド層54のAl組成C3は、0.05以上0.3以下である。なお、第2ガイド層54は、不純物無添加であってもよい。 The second guide layer 54 includes AlGaAs. The second guide layer 54 includes Al C3 Ga (1-C3) As having an Al composition C3. The Al composition C3 of the second guide layer 54 is different from the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43. The Al composition C3 of the second guide layer 54 is smaller than the Al composition (Al compositions B1, B2) of the p-type semiconductor layer 43. The Al composition C3 of the second guide layer 54 may be equal to the Al composition C2 of the first guide layer 53. In one example, the Al composition C3 of the second guide layer 54 is 0.05 or more and 0.3 or less. The second guide layer 54 may be free of impurities.
 図5は、トンネル層60の構成の一例を示している。
 トンネル層60は、p型トンネル層61およびn型トンネル層62を含む。p型トンネル層61は、図3に示すp型半導体層43(第2p型クラッド層47)と隣り合うように配置されている。n型トンネル層62は、図3に示すn型半導体層42(第2n型クラッド層45)と隣り合うように配置されている。したがって、p型トンネル層61およびn型トンネル層62は、図1および図2に示す半導体基板20の側からこの順番で積層されている。トンネル層60は、p型トンネル層61がp型半導体層43に電気的に接続され、n型トンネル層62がn型半導体層42に電気的に接続される態様で、各発光ユニット40の間に配置されている。
FIG. 5 shows an example of the configuration of the tunnel layer 60 .
The tunnel layer 60 includes a p-type tunnel layer 61 and an n-type tunnel layer 62. The p-type tunnel layer 61 is disposed adjacent to the p-type semiconductor layer 43 (second p-type cladding layer 47) shown in FIG. 3. The n-type tunnel layer 62 is disposed adjacent to the n-type semiconductor layer 42 (second n-type cladding layer 45) shown in FIG. 3. Therefore, the p-type tunnel layer 61 and the n-type tunnel layer 62 are laminated in this order from the side of the semiconductor substrate 20 shown in FIG. 1 and FIG. 2. The tunnel layer 60 is disposed between the light-emitting units 40 in such a manner that the p-type tunnel layer 61 is electrically connected to the p-type semiconductor layer 43 and the n-type tunnel layer 62 is electrically connected to the n-type semiconductor layer 42.
 p型トンネル層61は、GaAsを含む。p型トンネル層61は、p型不純物として、たとえばCを含む。p型トンネル層61の不純物濃度は、p型半導体層43の不純物濃度と異なる。p型トンネル層61の不純物濃度は、p型半導体層43の不純物濃度よりも高い。 The p-type tunnel layer 61 contains GaAs. The p-type tunnel layer 61 contains, for example, C as a p-type impurity. The impurity concentration of the p-type tunnel layer 61 is different from the impurity concentration of the p-type semiconductor layer 43. The impurity concentration of the p-type tunnel layer 61 is higher than the impurity concentration of the p-type semiconductor layer 43.
 n型トンネル層62は、GaAsを含む。n型トンネル層62は、n型不純物として、たとえばSi、Te、Seの少なくとも1種を含む。n型トンネル層62の不純物濃度は、n型半導体層42の不純物濃度と異なる。n型トンネル層62の不純物濃度は、n型半導体層42の不純物濃度よりも高い。 The n-type tunnel layer 62 includes GaAs. The n-type tunnel layer 62 includes at least one of the following n-type impurities: Si, Te, and Se. The impurity concentration of the n-type tunnel layer 62 is different from the impurity concentration of the n-type semiconductor layer 42. The impurity concentration of the n-type tunnel layer 62 is higher than the impurity concentration of the n-type semiconductor layer 42.
 [バリア層およびウエル層の厚さ関係]
 次に、バリア層51、第1ウエル層52A、および第2ウエル層52Bの厚さ関係について説明する。なお、以下では、第1ウエル層52Aおよび第2ウエル層52Bに共通の事項の場合、単にウエル層52とする。
[Relationship between barrier layer and well layer thickness]
Next, a description will be given of the thickness relationship between the barrier layer 51, the first well layer 52A, and the second well layer 52B. In the following, when a matter common to the first well layer 52A and the second well layer 52B is mentioned, it will be simply referred to as the well layer 52.
 第1ウエル層52Aの厚さTWAおよび第2ウエル層52Bの厚さTWBは、バリア層51の厚さTBよりも厚い。つまり、ウエル層52の厚さTWは、バリア層51の厚さTBよりも厚い。一例では、第1ウエル層52Aの厚さTWAと第2ウエル層52Bの厚さTWBとは互いに等しい。一例では、バリア層51の厚さTBに対するウエル層52の厚さTWの比率(TW/TB)は、1.9以上4.3以下である。 The thickness TWA of the first well layer 52A and the thickness TWB of the second well layer 52B are thicker than the thickness TB of the barrier layer 51. In other words, the thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51. In one example, the thickness TWA of the first well layer 52A and the thickness TWB of the second well layer 52B are equal to each other. In one example, the ratio (TW/TB) of the thickness TW of the well layer 52 to the thickness TB of the barrier layer 51 is 1.9 or more and 4.3 or less.
 一例では、ウエル層52の厚さTWは、100Åよりも厚く130Å以下である。一例では、ウエル層52の厚さTWは、105Å以上130Å以下である。一例では、ウエル層52の厚さTWは、110Å以上130Å以下である。 In one example, the thickness TW of the well layer 52 is greater than 100 Å and less than or equal to 130 Å. In one example, the thickness TW of the well layer 52 is greater than or equal to 105 Å and less than or equal to 130 Å. In one example, the thickness TW of the well layer 52 is greater than or equal to 110 Å and less than or equal to 130 Å.
 一例では、バリア層51の厚さTBは、0Åよりも厚く60Å以下である。一例では、バリア層51の厚さTBは、30Å以上60Å以下である。
 また、バリア層51の厚さTBとウエル層52の厚さTWとの組み合わせの一例として、バリア層51の厚さTBが0Åよりも厚く60Å以下であり、ウエル層52の厚さTWが100Åよりも厚く140Å未満である。また一例では、バリア層51の厚さTBが30Å以上60Å以下であり、ウエル層52の厚さTWが100Åよりも厚く130Å以下である。また一例では、バリア層51の厚さTBが30Å以上60Å以下であり、ウエル層52の厚さTWが105Å以上130Å以下である。また一例では、バリア層51の厚さTBが30Å以上60Å以下であり、ウエル層52の厚さTWが110Å以上130Å以下である。
In one example, the thickness TB of the barrier layer 51 is greater than 0 Å and equal to or less than 60 Å. In one example, the thickness TB of the barrier layer 51 is equal to or greater than 30 Å and equal to or less than 60 Å.
As an example of a combination of the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52, the thickness TB of the barrier layer 51 is greater than 0 Å and less than 60 Å, and the thickness TW of the well layer 52 is greater than 100 Å and less than 140 Å. In another example, the thickness TB of the barrier layer 51 is greater than 30 Å and less than 60 Å, and the thickness TW of the well layer 52 is greater than 100 Å and less than 13 ...5 Å and less than 130 Å. In another example, the thickness TB of the barrier layer 51 is greater than 30 Å and less than 60 Å, and the thickness TW of the well layer 52 is greater than 110 Å and less than 130 Å.
 [半導体レーザ装置の適用例]
 図6~図9を参照して、半導体レーザ装置10を備える半導体レーザモジュール200の一例について説明する。
[Application examples of semiconductor laser devices]
An example of a semiconductor laser module 200 including the semiconductor laser device 10 will be described with reference to FIGS.
 図6および図7に示すように、半導体レーザモジュール200は、ステム210と、ステム210に実装された半導体レーザユニット100と、半導体レーザユニット100を覆うキャップ220と、半導体レーザユニット100と電気的に接続された端子ピン231~234と、を備える。半導体レーザユニット100は、半導体レーザ装置10を備える。 As shown in Figures 6 and 7, the semiconductor laser module 200 includes a stem 210, a semiconductor laser unit 100 mounted on the stem 210, a cap 220 that covers the semiconductor laser unit 100, and terminal pins 231 to 234 that are electrically connected to the semiconductor laser unit 100. The semiconductor laser unit 100 includes a semiconductor laser device 10.
 ステム210は、平板状のベース211と、ベース211上に立設したヒートシンク212と、を含む。半導体レーザユニット100は、ヒートシンク212に実装されている。キャップ220は、半導体レーザユニット100およびヒートシンク212を覆うようにベース211に取り付けられている。キャップ220は、半導体レーザユニット100およびヒートシンク212を収容する収容空間SPをベース211とともに形成している。キャップ220は、ベース211とともに収容空間SP(図7参照)を中空状態に気密にして中空封止構造を形成している。 The stem 210 includes a flat base 211 and a heat sink 212 standing on the base 211. The semiconductor laser unit 100 is mounted on the heat sink 212. The cap 220 is attached to the base 211 so as to cover the semiconductor laser unit 100 and the heat sink 212. The cap 220, together with the base 211, forms an accommodation space SP that accommodates the semiconductor laser unit 100 and the heat sink 212. The cap 220, together with the base 211, makes the accommodation space SP (see Figure 7) airtight in a hollow state, forming a hollow sealing structure.
 キャップ220は、遮光性を有する材料によって形成されており、半導体レーザユニット100からのレーザ光が通過する開口部221が形成されている。一例では、開口部221には、透光板222(図7参照)が取り付けられている。 The cap 220 is made of a light-shielding material and has an opening 221 through which the laser light from the semiconductor laser unit 100 passes. In one example, a light-transmitting plate 222 (see FIG. 7) is attached to the opening 221.
 端子ピン231~234は、ベース211に設けられている。より詳細には、端子ピン231~233の各々は、ベース211の厚さ方向においてベース211を貫通している。端子ピン231~233とベース211との間には、絶縁材235が充填されている。端子ピン234は、ベース211と一体に形成されている。 Terminal pins 231 to 234 are provided on base 211. More specifically, each of terminal pins 231 to 233 penetrates base 211 in the thickness direction of base 211. Insulating material 235 is filled between terminal pins 231 to 233 and base 211. Terminal pin 234 is formed integrally with base 211.
 図8は、基板110の基板主面111を覆う絶縁層を省略した状態の半導体レーザユニット100の平面構造を示している。
 図8に示すように、半導体レーザユニット100は、基板110と、基板110に実装された半導体レーザ装置10、スイッチング素子120、およびキャパシタ131,132と、を備える。
FIG. 8 shows the planar structure of the semiconductor laser unit 100 in a state where the insulating layer covering the substrate main surface 111 of the substrate 110 is omitted.
As shown in FIG. 8, the semiconductor laser unit 100 includes a substrate 110, and a semiconductor laser device 10, a switching element 120, and capacitors 131 and 132 mounted on the substrate 110.
 基板110は、矩形平板状に形成されている。基板110は、たとえばガラスエポキシ樹脂等の絶縁材料によって形成されている。基板110は、基板主面111と、基板主面111とは反対側を向く基板裏面112(図9参照)と、を有する。 The substrate 110 is formed in a rectangular flat plate shape. The substrate 110 is formed from an insulating material such as glass epoxy resin. The substrate 110 has a substrate main surface 111 and a substrate back surface 112 (see FIG. 9) facing the opposite side to the substrate main surface 111.
 基板110の基板主面111には、主面側配線として、第1~第3主面側配線111A~111Cが形成されている。第1および第2主面側配線111A,111Bには、半導体レーザ装置10、スイッチング素子120、およびキャパシタ131,132が実装されている。 First to third main surface side wirings 111A to 111C are formed on the main surface side wirings of the substrate 110. The semiconductor laser device 10, the switching element 120, and the capacitors 131 and 132 are mounted on the first and second main surface side wirings 111A and 111B.
 半導体レーザ装置10は、はんだペーストまたはAg(銀)ペースト等の導電性接合材SDによって第1主面側配線111AのX方向の中央に接合されている。これにより、半導体レーザ装置10と第1主面側配線111Aとが電気的に接続されている。 The semiconductor laser device 10 is bonded to the center of the first main surface side wiring 111A in the X direction by a conductive bonding material SD such as solder paste or Ag (silver) paste. This electrically connects the semiconductor laser device 10 and the first main surface side wiring 111A.
 スイッチング素子120は、半導体レーザ装置10に供給される電流を制御する半導体素子である。スイッチング素子120は、たとえばトランジスタである。一例では、スイッチング素子120としてMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)が用いられている。 The switching element 120 is a semiconductor element that controls the current supplied to the semiconductor laser device 10. The switching element 120 is, for example, a transistor. In one example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the switching element 120.
 スイッチング素子120のうち基板主面111と同じ側を向く素子主面にはソース電極121およびゲート電極122が形成され、基板主面111と対面する素子裏面にはドレイン電極(図示略)が形成されている。つまり、スイッチング素子120は、縦型構造のMOSFETである。スイッチング素子120は、導電性接合材SDによって第2主面側配線111BのX方向の中央に接合されている。これにより、スイッチング素子120のドレインと第2主面側配線111Bとが電気的に接続されている。ソース電極121は、ワイヤW1によって半導体レーザ装置10と電気的に接続されている。 A source electrode 121 and a gate electrode 122 are formed on the element principal surface of the switching element 120 facing the same side as the substrate principal surface 111, and a drain electrode (not shown) is formed on the element rear surface facing the substrate principal surface 111. In other words, the switching element 120 is a vertical structure MOSFET. The switching element 120 is joined to the center of the second principal surface side wiring 111B in the X direction by a conductive bonding material SD. This electrically connects the drain of the switching element 120 to the second principal surface side wiring 111B. The source electrode 121 is electrically connected to the semiconductor laser device 10 by a wire W1.
 キャパシタ131,132は、スイッチング素子120と協働して半導体レーザ装置10に電流を供給する電子部品である。キャパシタ131,132の容量は互いに等しい。キャパシタ131,132は、第1主面側配線111Aと第2主面側配線111Bとの間を跨るように配置されている。キャパシタ131,132は、導電性接合材SDによって第1主面側配線111Aと第2主面側配線111Bとの双方に接合されている。これにより、キャパシタ131,132は、第1主面側配線111Aと第2主面側配線111Bの双方と電気的に接続されている。 The capacitors 131 and 132 are electronic components that cooperate with the switching element 120 to supply current to the semiconductor laser device 10. The capacitances of the capacitors 131 and 132 are equal to each other. The capacitors 131 and 132 are arranged so as to straddle the first main surface side wiring 111A and the second main surface side wiring 111B. The capacitors 131 and 132 are joined to both the first main surface side wiring 111A and the second main surface side wiring 111B by a conductive bonding material SD. As a result, the capacitors 131 and 132 are electrically connected to both the first main surface side wiring 111A and the second main surface side wiring 111B.
 図8に示すとおり、キャパシタ131とキャパシタ132とは、基板主面111上で半導体レーザ装置10およびスイッチング素子120に対して対称的に配置されている。これにより、キャパシタ131からスイッチング素子120を経て半導体レーザ装置10に電流が流れるループ状の第1配線経路と、キャパシタ132からスイッチング素子120を経て半導体レーザ装置10に電流が流れるループ状の第2配線経路とが半導体レーザ装置10およびスイッチング素子120に対して対称的に形成されている。このように、第1配線経路と第2配線経路とが対称的に配置されることによって、第1配線経路を流れる電流によって形成される磁束と、第2配線経路を流れる電流によって形成される磁束とが互いに打ち消し合うようになる。これにより、第1配線経路に存在する寄生インダクタンスおよび第2配線経路に存在する寄生インダクタンスの双方を低減することができる。 As shown in FIG. 8, the capacitors 131 and 132 are arranged symmetrically with respect to the semiconductor laser device 10 and the switching element 120 on the substrate main surface 111. As a result, a loop-shaped first wiring path through which a current flows from the capacitor 131 to the semiconductor laser device 10 via the switching element 120, and a loop-shaped second wiring path through which a current flows from the capacitor 132 to the semiconductor laser device 10 via the switching element 120 are formed symmetrically with respect to the semiconductor laser device 10 and the switching element 120. In this way, by symmetrically arranging the first wiring path and the second wiring path, the magnetic flux formed by the current flowing through the first wiring path and the magnetic flux formed by the current flowing through the second wiring path cancel each other out. This makes it possible to reduce both the parasitic inductance present in the first wiring path and the parasitic inductance present in the second wiring path.
 図9に示すように、基板110の基板裏面112には、裏面側配線として、第1裏面側配線112Aおよび第2裏面側配線112Bが形成されている。第1裏面側配線112Aおよび第2裏面側配線112Bは、半導体レーザユニット100の外部端子を構成している。 As shown in FIG. 9, a first back surface side wiring 112A and a second back surface side wiring 112B are formed as back surface side wiring on the back surface 112 of the substrate 110. The first back surface side wiring 112A and the second back surface side wiring 112B constitute the external terminals of the semiconductor laser unit 100.
 第1裏面側配線112Aは、1または複数のスルーホール113によって第1主面側配線111Aおよび第3主面側配線111Cの双方と電気的に接続されている。第2裏面側配線112Bは、図9の破線枠で示すスイッチング素子120と平面視で重なる位置に形成されている。第1裏面側配線112Aは、第2裏面側配線112Bを囲う略U字状に形成されている。第2裏面側配線112Bは、1または複数のスルーホール114によって第2主面側配線111B(図8参照)と電気的に接続されている。 The first back surface side wiring 112A is electrically connected to both the first main surface side wiring 111A and the third main surface side wiring 111C by one or more through holes 113. The second back surface side wiring 112B is formed at a position overlapping the switching element 120 shown in a dashed line frame in FIG. 9 in a plan view. The first back surface side wiring 112A is formed in a substantially U-shape surrounding the second back surface side wiring 112B. The second back surface side wiring 112B is electrically connected to the second main surface side wiring 111B (see FIG. 8) by one or more through holes 114.
 次に、半導体レーザユニット100と端子ピン231~233との電気的接続構造について説明する。
 図6に示すように、端子ピン231~233は、ベース211に対してベース211の厚さ方向の両側から突出している。端子ピン231~233のうちベース211に対してヒートシンク212側に突出している部分はそれぞれ、ワイヤW2~W4によって半導体レーザユニット100に電気的に接続されている。より詳細には、ワイヤW2は、端子ピン231とスイッチング素子120のソース電極121とを電気的に接続している。ワイヤW3は、端子ピン232とスイッチング素子120のゲート電極122とを電気的に接続している。ワイヤW4は、端子ピン233と第3主面側配線111Cとを電気的に接続している。
Next, the electrical connection structure between the semiconductor laser unit 100 and the terminal pins 231 to 233 will be described.
6, the terminal pins 231 to 233 protrude from both sides of the base 211 in the thickness direction of the base 211. The portions of the terminal pins 231 to 233 protruding toward the heat sink 212 side from the base 211 are electrically connected to the semiconductor laser unit 100 by wires W2 to W4, respectively. More specifically, the wire W2 electrically connects the terminal pin 231 to the source electrode 121 of the switching element 120. The wire W3 electrically connects the terminal pin 232 to the gate electrode 122 of the switching element 120. The wire W4 electrically connects the terminal pin 233 to the third main surface side wiring 111C.
 図7に示すように、端子ピン234は、ベース211と一体に形成されているため、ベース211と電気的に接続されている。端子ピン234は、ヒートシンク212と電気的に接続されているともいえる。 As shown in FIG. 7, the terminal pin 234 is formed integrally with the base 211 and is therefore electrically connected to the base 211. It can also be said that the terminal pin 234 is electrically connected to the heat sink 212.
 半導体レーザユニット100は、導電性接合材によって基板110の第2裏面側配線112Bがヒートシンク212と接合されるようにヒートシンク212に実装されている。一方、第1裏面側配線112Aは、ヒートシンク212と電気的に接続されていない。このため、端子ピン234は、スイッチング素子120のドレイン電極と電気的に接続されている。 The semiconductor laser unit 100 is mounted on the heat sink 212 so that the second back surface side wiring 112B of the substrate 110 is joined to the heat sink 212 by a conductive bonding material. On the other hand, the first back surface side wiring 112A is not electrically connected to the heat sink 212. Therefore, the terminal pin 234 is electrically connected to the drain electrode of the switching element 120.
 [半導体レーザモジュールの適用例]
 図10を参照して、半導体レーザモジュール200の適用例として、半導体レーザモジュール200を含むセンサ400について説明する。
[Application examples of semiconductor laser modules]
With reference to FIG. 10, a sensor 400 including the semiconductor laser module 200 will be described as an application example of the semiconductor laser module 200.
 センサ400は、たとえば3次元距離計測の一例であるLiDAR(Light Detection and Ranging、Laser Imaging Detection and Ranging)としての測距センサに適用することができる。なお、センサ400は、2次元距離計測としての測距センサに適用してもよい。 The sensor 400 can be used as a distance measuring sensor such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging), which is an example of three-dimensional distance measurement. The sensor 400 may also be used as a distance measuring sensor for two-dimensional distance measurement.
 センサ400は、発光モジュールとしての半導体レーザモジュール200と、受光モジュール300と、を備える。センサ400においては、半導体レーザモジュール200が測定対象物MXに向けてレーザ光を出射する。受光モジュール300は、測定対象物MXで反射したレーザ光(反射光)を受光する。センサ400は、半導体レーザモジュール200がレーザ光を出射してから受光モジュール300が反射光を受光するまでの時間差を計測する。これにより、センサ400と測定対象物MXとの間の距離が算出される。 The sensor 400 includes a semiconductor laser module 200 as an emitting module, and a light receiving module 300. In the sensor 400, the semiconductor laser module 200 emits laser light toward the measurement object MX. The light receiving module 300 receives the laser light (reflected light) reflected by the measurement object MX. The sensor 400 measures the time difference between when the semiconductor laser module 200 emits the laser light and when the light receiving module 300 receives the reflected light. This allows the distance between the sensor 400 and the measurement object MX to be calculated.
 受光モジュール300は、受光素子310と、バンドパスフィルタ320と、を含む。バンドパスフィルタ320は、反射光の波長を含む特定の波長域の光を透過するように構成されたフィルタである。受光素子310は、バンドパスフィルタ320を透過した光を受光するように構成されている。 The light receiving module 300 includes a light receiving element 310 and a bandpass filter 320. The bandpass filter 320 is a filter configured to transmit light in a specific wavelength range that includes the wavelength of the reflected light. The light receiving element 310 is configured to receive the light that has passed through the bandpass filter 320.
 [作用]
 本実施形態の半導体レーザ装置10の作用について説明する。
 LiDARとしての測距センサに用いられるセンサは、屋外で使用される場合、受光素子は、図10に示される反射光を受光するとともに、太陽光を受光する。この場合、受光した太陽光を反射光として誤認識するおそれがある。
[Action]
The operation of the semiconductor laser device 10 of this embodiment will now be described.
When a sensor used as a distance measuring sensor as LiDAR is used outdoors, the light receiving element receives sunlight as well as the reflected light shown in Fig. 10. In this case, there is a risk that the received sunlight may be erroneously recognized as reflected light.
 このような問題に鑑み、本実施形態の受光モジュール300は、特定の波長域の光を透過するバンドパスフィルタ320を備える。つまり、バンドパスフィルタ320は、特定の波長域に反射光の波長を含むように構成されている。このバンドパスフィルタ320は、受光素子310に対して、特定の波長域以外の光を除去する。このようなバンドパスフィルタ320は、光の透過幅(透過する波長範囲)が狭いことが好ましい。 In consideration of these problems, the light receiving module 300 of this embodiment is equipped with a bandpass filter 320 that transmits light in a specific wavelength range. In other words, the bandpass filter 320 is configured to include the wavelength of the reflected light in the specific wavelength range. This bandpass filter 320 removes light other than the specific wavelength range from the light receiving element 310. It is preferable that such a bandpass filter 320 has a narrow light transmission width (transmitting wavelength range).
 ところで、半導体レーザ装置のレーザ光は、半導体レーザ装置の温度に応じてレーザ光の中心波長(光スペクトルのピークの波長)が変化する、波長温度依存性を有する。具体的には、レーザ光の波長は、温度が高くなるにつれて長波長側にシフトする。 The laser light from a semiconductor laser device has wavelength temperature dependency, in which the central wavelength of the laser light (the wavelength at the peak of the optical spectrum) changes depending on the temperature of the semiconductor laser device. Specifically, the wavelength of the laser light shifts to the longer wavelength side as the temperature increases.
 このようにレーザ光が高い波長温度依存性を有するため、バンドパスフィルタ320は、所定の温度範囲において変化した波長のレーザ光(反射光)を透過させる必要がある。このため、バンドパスフィルタ320の透過波長範囲幅を広げる必要がある。太陽光は様々な波長の光を含む。したがって、バンドパスフィルタ320の透過波長範囲幅を広げると、バンドパスフィルタ320を透過する太陽光が多くなるため、太陽光を反射光と誤認識するおそれが高くなる。 As described above, since laser light has a high wavelength-temperature dependency, the bandpass filter 320 needs to transmit laser light (reflected light) whose wavelength changes within a certain temperature range. For this reason, it is necessary to widen the transmission wavelength range width of the bandpass filter 320. Sunlight contains light of various wavelengths. Therefore, if the transmission wavelength range width of the bandpass filter 320 is widened, more sunlight will pass through the bandpass filter 320, increasing the risk of the sunlight being mistaken for reflected light.
 本実施形態の半導体レーザ装置10では、量子井戸層であるウエル層52の厚さTWがバリア層51の厚さTBよりも厚い。これにより、量子サイズ効果が弱くなるため、取り得るエネルギー幅を広げることができる。つまり、ウエル層52において発振可能なレーザ光のスペクトル幅を大きくできる。一方で、エネルギーと波長とは逆数の関係であるため、高いエネルギーでは短波長で発振することとなる。これにより、半導体レーザ装置10は、高いエネルギーに対応する短波長のレーザ光を発振することができる。このような半導体レーザ装置10は、温度が高くなった場合であっても、短波長のレーザ光を発振しようとするため、温度変化に対するレーザ光の波長の変化が抑制される。したがって、温度変化に対するレーザ光の波長の変化量(シフト量)が低減される。その結果、レーザ光の波長温度依存性が小さくなる。 In the semiconductor laser device 10 of this embodiment, the thickness TW of the well layer 52, which is a quantum well layer, is thicker than the thickness TB of the barrier layer 51. This weakens the quantum size effect, making it possible to widen the available energy range. In other words, the spectral width of the laser light that can be oscillated in the well layer 52 can be increased. On the other hand, since the energy and the wavelength are inversely related, oscillation occurs at a short wavelength at high energy. This allows the semiconductor laser device 10 to oscillate a short-wavelength laser light corresponding to high energy. Since such a semiconductor laser device 10 attempts to oscillate a short-wavelength laser light even when the temperature is high, the change in the wavelength of the laser light due to temperature change is suppressed. Therefore, the amount of change (shift) in the wavelength of the laser light due to temperature change is reduced. As a result, the wavelength temperature dependency of the laser light is reduced.
 この半導体レーザ装置10の動作は、以下のように考えられる。ウエル層52(量子井戸層)の厚さTWを厚くすると、量子井戸層の量子サイズ効果が弱まり、ウエル層52において取り得るエネルギー準位が多くなる。また、ウエル層52の厚さTWを厚くすると、量子サイズ効果が弱まり、ウエル層52におけるエネルギー幅を拡大できる。ウエル層52にキャリアが溜まると、高エネルギー発振となって、ウエル層52においてスペクトル幅のうち短い波長のレーザ光を出射する。したがって、この半導体レーザ装置10は、温度が高くなる場合でもエネルギー密度によって短波長側の波長域での発振を維持しようとする。 The operation of this semiconductor laser device 10 can be considered as follows. Increasing the thickness TW of the well layer 52 (quantum well layer) weakens the quantum size effect of the quantum well layer, and increases the number of energy levels that can be taken in the well layer 52. Increasing the thickness TW of the well layer 52 weakens the quantum size effect, and the energy width in the well layer 52 can be expanded. When carriers accumulate in the well layer 52, high-energy oscillation occurs, and the well layer 52 emits laser light with a short wavelength in the spectral width. Therefore, this semiconductor laser device 10 attempts to maintain oscillation in the short-wavelength wavelength range by using energy density, even when the temperature becomes high.
 上述したように、ウエル層52の厚さTWを厚くすると、バリア層51の両側に配置された第1ウエル層52Aおよび第2ウエル層52Bにおいてキャリア(電子および正孔)の偏りが生じるおそれがある。その結果、レーザ光の光スペクトルにおいて複数のピークを有するおそれがある(図13参照)。 As described above, if the thickness TW of the well layer 52 is increased, there is a risk of bias in the carriers (electrons and holes) in the first well layer 52A and the second well layer 52B arranged on both sides of the barrier layer 51. As a result, there is a risk of multiple peaks in the optical spectrum of the laser light (see FIG. 13).
 そこで、本実施形態の半導体レーザ装置10では、バリア層51の厚さTBを薄くしている。一例では、バリア層51の厚さTBがウエル層52の厚さTWよりも薄い。バリア層51の厚さTBを薄くすると、共鳴トンネル効果によって、バリア層51の両側の量子井戸層(第1ウエル層52Aおよび第2ウエル層52B)間のキャリアが移動しやすくなる。これにより、第1ウエル層52Aおよび第2ウエル層52Bのキャリアの偏りが低減されるため、レーザ光の光スペクトルにおいて複数のピークが生じることを抑制できる。 Therefore, in the semiconductor laser device 10 of this embodiment, the thickness TB of the barrier layer 51 is made thin. In one example, the thickness TB of the barrier layer 51 is thinner than the thickness TW of the well layer 52. When the thickness TB of the barrier layer 51 is made thin, carriers can move more easily between the quantum well layers (the first well layer 52A and the second well layer 52B) on both sides of the barrier layer 51 due to the resonant tunneling effect. This reduces the bias of carriers in the first well layer 52A and the second well layer 52B, thereby suppressing the occurrence of multiple peaks in the optical spectrum of the laser light.
 (実験例1)
 実験例1として、半導体レーザ装置10について、バリア層51の厚さTBおよびウエル層52の厚さTWと、半導体レーザ装置10の波長温度依存性およびレーザ光の光スペクトルとの関係を確認した。
(Experimental Example 1)
As Experimental Example 1, the relationship between the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 of the semiconductor laser device 10 and the wavelength temperature dependency of the semiconductor laser device 10 and the optical spectrum of the laser light was confirmed.
 図11は、バリア層51の厚さTBとウエル層52の厚さTWとを変更した複数の半導体レーザ装置10について、波長温度係数(nm/℃)とレーザ光の光スペクトルの状態との関係を示す表である。図12および図13は、半導体レーザ装置10について、ケース温度が10℃以上90℃以下の範囲における光スペクトルを示す。図12は、図11の領域Rに含まれる半導体レーザ装置10の光スペクトルを示す。図13は、図11の領域R外の半導体レーザ装置10の光スペクトルを示す。なお、図12および図13において、各温度の光スペクトルは、ピークの発光強度を100%として示されている。また、ケース温度は、半導体レーザモジュール200のベース211の温度である。また、実験例1では、発光幅が270μmに設定されている。 FIG. 11 is a table showing the relationship between the wavelength temperature coefficient (nm/°C) and the state of the optical spectrum of the laser light for a number of semiconductor laser devices 10 in which the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 are changed. FIGS. 12 and 13 show the optical spectrum of the semiconductor laser device 10 in the case temperature range of 10°C to 90°C. FIG. 12 shows the optical spectrum of the semiconductor laser device 10 included in the region R of FIG. 11. FIG. 13 shows the optical spectrum of the semiconductor laser device 10 outside the region R of FIG. 11. Note that in FIGS. 12 and 13, the optical spectrum at each temperature is shown with the peak emission intensity set to 100%. The case temperature is the temperature of the base 211 of the semiconductor laser module 200. In Experimental Example 1, the emission width is set to 270 μm.
 実験例1にて測定した波長温度係数は、温度が1℃変化したときに波長がどの程度変化するかを示す係数である。波長温度係数は、次のように算出される。すなわち、たとえばケース温度を予め設定した範囲(設定温度範囲)にわたり変化させたときの波長の変化量が算出される。この波長の変化量を設定温度範囲で除算することによって波長温度係数が算出される。たとえば、設定温度範囲が10℃~90℃であり、この設定温度範囲における波長の変化量が8nmであれば、0.1nm/℃となる。 The wavelength temperature coefficient measured in Experimental Example 1 is a coefficient that indicates how much the wavelength changes when the temperature changes by 1°C. The wavelength temperature coefficient is calculated as follows. That is, for example, the amount of change in wavelength when the case temperature is changed over a preset range (set temperature range) is calculated. The wavelength temperature coefficient is calculated by dividing this amount of change in wavelength by the set temperature range. For example, if the set temperature range is 10°C to 90°C and the amount of change in wavelength within this set temperature range is 8 nm, then the coefficient is 0.1 nm/°C.
 実験例1では、ケース温度が25℃以上90℃以下の範囲において波長温度係数が0.12nm/℃以下であること(条件1)と、レーザ光の光スペクトルのピークが複数ないこと(条件2)とを条件としている。図11では、光スペクトルの状態として、条件2を満たすものに「〇」を付し、条件2を満たさないものに「×」を付している。これら条件1および条件2を満たすことによって、波長温度依存性が小さくかつ光スペクトルのピークが1つとなるレーザ光が得られる。 In experimental example 1, the conditions are that the wavelength temperature coefficient is 0.12 nm/°C or less when the case temperature is in the range of 25°C to 90°C (condition 1), and that the optical spectrum of the laser light does not have multiple peaks (condition 2). In Figure 11, the optical spectrum state that satisfies condition 2 is marked with a "o" and that that does not satisfy condition 2 is marked with an "x". By satisfying conditions 1 and 2, laser light with small wavelength temperature dependency and a single optical spectrum peak is obtained.
 図11に示すように、ウエル層52の厚さTWがバリア層51の厚さTBよりも薄い場合(ウエル層52の厚さTWが70Å、バリア層51の厚さTBが90Å)、波長温度係数が0.18nm/℃になり、図11の表において最も大きくなる。換言すると、ウエル層52の厚さTWがバリア層51の厚さTBよりも厚いと、波長温度係数が小さいことが分かる。 As shown in FIG. 11, when the thickness TW of the well layer 52 is thinner than the thickness TB of the barrier layer 51 (the thickness TW of the well layer 52 is 70 Å and the thickness TB of the barrier layer 51 is 90 Å), the wavelength temperature coefficient is 0.18 nm/°C, which is the largest in the table of FIG. 11. In other words, when the thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51, the wavelength temperature coefficient is small.
 図11における太線の枠で囲まれた領域Rは、条件1および条件2の両方を満たすバリア層51の厚さTBおよびウエル層52の厚さTWである。具体的には、バリア層51の厚さTBは30Å以上60Å以下であり、ウエル層52の厚さTWは100Aよりも大きく130Å以下である。バリア層51の厚さTBは、20Åよりも大きく90Å未満であってもよい。 The region R enclosed by the thick line frame in FIG. 11 is the thickness TB of the barrier layer 51 and the thickness TW of the well layer 52 that satisfy both conditions 1 and 2. Specifically, the thickness TB of the barrier layer 51 is 30 Å or more and 60 Å or less, and the thickness TW of the well layer 52 is greater than 100 Å and less than 130 Å. The thickness TB of the barrier layer 51 may be greater than 20 Å and less than 90 Å.
 この領域Rにおいて、バリア層51の厚さTBが30Å以上60Å以下であり、ウエル層52の厚さTWが110Å以上125Å以下であれば、波長温度係数が0.1nm/℃以下となるため、半導体レーザ装置10の波長温度依存性が比較的小さくなる。また、バリア層51の厚さTBが40Å以上50Å以下であり、ウエル層52の厚さTWが120Å以上125Å以下であると、波長温度係数が0.06~0.07nm/℃となるため、半導体レーザ装置10の波長温度依存性が比較的小さくなる。また、バリア層51の厚さTBが40Åであり、ウエル層52の厚さTWが120Åであると、波長温度係数が0.06nm/℃となるため、半導体レーザ装置10の波長温度依存性がより小さくなる。また、バリア層51の厚さTBが50Åであり、ウエル層52の厚さTWが125Åであると、波長温度係数が0.06nm/℃となるため、半導体レーザ装置10の波長温度依存性がより小さくなる。 In this region R, if the thickness TB of the barrier layer 51 is 30 Å or more and 60 Å or less, and the thickness TW of the well layer 52 is 110 Å or more and 125 Å or less, the wavelength temperature coefficient is 0.1 nm/°C or less, and the wavelength temperature dependence of the semiconductor laser device 10 is relatively small. Also, if the thickness TB of the barrier layer 51 is 40 Å or more and 50 Å or less, and the thickness TW of the well layer 52 is 120 Å or more and 125 Å or less, the wavelength temperature coefficient is 0.06 to 0.07 nm/°C, and the wavelength temperature dependence of the semiconductor laser device 10 is relatively small. Also, if the thickness TB of the barrier layer 51 is 40 Å and the thickness TW of the well layer 52 is 120 Å, the wavelength temperature coefficient is 0.06 nm/°C, and the wavelength temperature dependence of the semiconductor laser device 10 is even smaller. Furthermore, if the thickness TB of the barrier layer 51 is 50 Å and the thickness TW of the well layer 52 is 125 Å, the wavelength temperature coefficient is 0.06 nm/°C, so the wavelength temperature dependence of the semiconductor laser device 10 becomes smaller.
 図12は、図11の表に示す実験例1のうち、ウエル層52の厚さTWを115Å、バリア層51の厚さTBを30Åとした半導体レーザ装置10における光スペクトルを示す。この半導体レーザ装置10では、ケース温度が10℃以上90℃以下において、1つのピークを有する光スペクトルとなっている。 Figure 12 shows the optical spectrum of the semiconductor laser device 10 in Experimental Example 1 shown in the table of Figure 11, where the thickness TW of the well layer 52 is 115 Å and the thickness TB of the barrier layer 51 is 30 Å. In this semiconductor laser device 10, the optical spectrum has one peak when the case temperature is between 10°C and 90°C.
 図13は、図11の表に示す実験例1のうち、ウエル層52の厚さTWを120Å、バリア層51の厚さTBを90Åとした半導体レーザ装置10における光スペクトルを示す。この半導体レーザ装置10では、ケース温度が75℃以上90℃以下において、複数のピークを有する光スペクトルとなっている。また、ピークの波長は、ケース温度が10℃から75℃までの温度上昇に対して長波長側にシフトしているのに対し、85℃および90℃では10℃のときのピークの波長よりも短波長となっている。 Figure 13 shows the optical spectrum of the semiconductor laser device 10 in Experimental Example 1 shown in the table of Figure 11, where the thickness TW of the well layer 52 is 120 Å and the thickness TB of the barrier layer 51 is 90 Å. In this semiconductor laser device 10, when the case temperature is between 75°C and 90°C, the optical spectrum has multiple peaks. Furthermore, the wavelength of the peak shifts to the longer wavelength side as the case temperature increases from 10°C to 75°C, whereas at 85°C and 90°C, the wavelength is shorter than the peak wavelength at 10°C.
 (実験例2)
 実験例2として、半導体レーザ装置10のウエル層52の厚さTWと光出力との関係について確認した。図14は、ウエル層52の厚さTWが70Åの場合の光出力を100%として、ウエル層52の厚さTWを70Åよりも厚くした場合の光出力の変化を示す表である。
(Experimental Example 2)
As Experimental Example 2, the relationship between the thickness TW of the well layer 52 of the semiconductor laser device 10 and the optical output was confirmed. Fig. 14 is a table showing the change in optical output when the thickness TW of the well layer 52 is made thicker than 70 Å, with the optical output being 100% when the thickness TW of the well layer 52 is 70 Å.
 図14に示すように、ウエル層52の厚さTWが100Å以上130Å以下の範囲では、光出力は100%以上となる。一方、ウエル層52の厚さTWが140Åになると、光出力が43%と半分以下となる。このため、ウエル層52の厚さTWは、140Å未満が好ましい。より好ましくは、ウエル層52の厚さTWは、130Å以下である。 As shown in FIG. 14, when the thickness TW of the well layer 52 is in the range of 100 Å or more and 130 Å or less, the light output is 100% or more. On the other hand, when the thickness TW of the well layer 52 is 140 Å, the light output is less than half, at 43%. For this reason, it is preferable that the thickness TW of the well layer 52 is less than 140 Å. More preferably, the thickness TW of the well layer 52 is 130 Å or less.
 (実験例3)
 実験例3として、半導体レーザ装置10のレーザ光の発光幅と波長温度係数との関係について確認した。図15は、半導体レーザ装置10のウエル層52の厚さTWが115Åであり、バリア層51の厚さTBが30Åである。実験例3では、波長温度係数は、ケース温度が25℃以上90℃以下の範囲で算出される。
(Experimental Example 3)
In Experimental Example 3, the relationship between the emission width of the laser light and the wavelength temperature coefficient of the semiconductor laser device 10 was confirmed. In Fig. 15, the thickness TW of the well layer 52 of the semiconductor laser device 10 is 115 Å, and the thickness TB of the barrier layer 51 is 30 Å. In Experimental Example 3, the wavelength temperature coefficient is calculated in a case temperature range of 25°C or more and 90°C or less.
 図15に示すように、レーザ光の発光幅が50μm以上300μm以下の範囲において、波長温度係数は0.06nm/℃以上0.08nm/℃以下であり、0.1nm以下となっている。より詳細には、発光幅が50μmにおける波長温度係数が0.06nm/℃であり、発光幅が130μmにおける波長温度係数が0.07nm/℃であり、発光幅が225μmにおける波長温度係数が0.08nm/℃であり、発光幅が270μmにおける波長温度係数が0.07nm/℃であり、発光幅が290μmにおける波長温度係数が0.06nm/℃であり、発光幅が300μmにおける波長温度係数が0.06nm/℃である。このように、発光幅が50μm、または290μm以上300μm以下であれば、波長温度係数が0.06nm/℃となるので、半導体レーザ装置10の波長温度依存性がより小さくなる。 As shown in FIG. 15, when the emission width of the laser light is in the range of 50 μm to 300 μm, the wavelength temperature coefficient is 0.06 nm/°C to 0.08 nm/°C, and is 0.1 nm or less. More specifically, the wavelength temperature coefficient when the emission width is 50 μm is 0.06 nm/°C, the wavelength temperature coefficient when the emission width is 130 μm is 0.07 nm/°C, the wavelength temperature coefficient when the emission width is 225 μm is 0.08 nm/°C, the wavelength temperature coefficient when the emission width is 270 μm is 0.07 nm/°C, the wavelength temperature coefficient when the emission width is 290 μm is 0.06 nm/°C, and the wavelength temperature coefficient when the emission width is 300 μm is 0.06 nm/°C. In this way, if the emission width is 50 μm or 290 μm to 300 μm, the wavelength temperature coefficient is 0.06 nm/°C, and the wavelength temperature dependency of the semiconductor laser device 10 is smaller.
 またレーザ光の発光幅を50μm、130μm、225μm、270μm、290μm、および300μmとした半導体レーザ装置10の各々においてケース温度が25℃以上90℃以下の範囲で、光スペクトルが1つのピークを有する結果が得られた。 Furthermore, for each of the semiconductor laser devices 10 with laser light emission widths of 50 μm, 130 μm, 225 μm, 270 μm, 290 μm, and 300 μm, the optical spectrum had one peak when the case temperature was in the range of 25°C or higher and 90°C or lower.
 [効果]
 本実施形態の半導体レーザ装置10、半導体レーザモジュール200、およびセンサ400によれば、以下の効果が得られる。
[effect]
According to the semiconductor laser device 10, the semiconductor laser module 200, and the sensor 400 of this embodiment, the following effects can be obtained.
 (1)半導体レーザ装置10は、バリア層51と、バリア層51の厚さ方向であるZ方向においてバリア層51の両側に設けられたウエル層52と、を含む活性層41と、Z方向において活性層41を挟むn型半導体層42およびp型半導体層43と、を備える。ウエル層52の厚さTWは、バリア層51の厚さTBよりも厚い。この構成によれば、ウエル層52の厚さTWを厚くすることによって、半導体レーザ装置10の波長温度依存性を低減することができる。 (1) The semiconductor laser device 10 includes an active layer 41 including a barrier layer 51 and well layers 52 provided on both sides of the barrier layer 51 in the Z direction, which is the thickness direction of the barrier layer 51, and an n-type semiconductor layer 42 and a p-type semiconductor layer 43 that sandwich the active layer 41 in the Z direction. The thickness TW of the well layer 52 is thicker than the thickness TB of the barrier layer 51. With this configuration, the wavelength temperature dependence of the semiconductor laser device 10 can be reduced by increasing the thickness TW of the well layer 52.
 (2)ウエル層52の厚さTWが100Åよりも厚く140Å未満である。この構成によれば、ウエル層52の厚さTWが100Åよりも厚いため、半導体レーザ装置10の波長温度依存性を低減することができる。加えて、ウエル層52の厚さTWが140Å未満のため、光出力の低下を抑制することができる。 (2) The thickness TW of the well layer 52 is greater than 100 Å and less than 140 Å. With this configuration, the thickness TW of the well layer 52 is greater than 100 Å, so the wavelength temperature dependency of the semiconductor laser device 10 can be reduced. In addition, the thickness TW of the well layer 52 is less than 140 Å, so the decrease in optical output can be suppressed.
 (3)ウエル層52の厚さTWが110Å以上130Å以下である。バリア層51の厚さTBが30Å以上60Å以下である。この構成によれば、波長温度係数を0.12nm/℃以下とすることができ、かつレーザ光の光スペクトルのピークを1つとすることができる。 (3) The thickness TW of the well layer 52 is 110 Å or more and 130 Å or less. The thickness TB of the barrier layer 51 is 30 Å or more and 60 Å or less. With this configuration, the wavelength temperature coefficient can be made 0.12 nm/°C or less, and the optical spectrum of the laser light can have one peak.
 (4)活性層41は、その端面(発光部端面33)における発光幅を50μm以上300μm以下とするように構成されている。活性層41におけるウエル層52の厚さTWが115Åであり、バリア層51の厚さTBが30Åである。この構成によれば、波長温度係数を0.1nm/℃以下とすることができ、かつレーザ光の光スペクトルのピークを1つとすることができる。 (4) The active layer 41 is configured so that the emission width at its end face (light-emitting portion end face 33) is 50 μm or more and 300 μm or less. The well layer 52 in the active layer 41 has a thickness TW of 115 Å, and the barrier layer 51 has a thickness TB of 30 Å. With this configuration, the wavelength temperature coefficient can be made 0.1 nm/°C or less, and the optical spectrum of the laser light can have one peak.
 (5)半導体レーザモジュール200は、半導体レーザ装置10と、半導体レーザ装置10が取り付けられたステム210と、ステム210に取り付けられ、半導体レーザ装置10を覆うとともに半導体レーザ装置10からのレーザ光が通過する開口部221を有するキャップ220と、半導体レーザ装置10と電気的に接続された端子ピン231~234と、を備える。この構成によれば、半導体レーザ装置10がステム210に取り付けられることによって、半導体レーザ装置10の熱を外部へ効率よく放熱することができる。また、半導体レーザ装置10とスイッチング素子120とを含む半導体レーザユニット100を用いることによって、半導体レーザ装置10を高速にオンオフすることができ、レーザ光の短パルス化を容易に実現することができる。 (5) The semiconductor laser module 200 includes a semiconductor laser device 10, a stem 210 to which the semiconductor laser device 10 is attached, a cap 220 attached to the stem 210, covering the semiconductor laser device 10 and having an opening 221 through which the laser light from the semiconductor laser device 10 passes, and terminal pins 231-234 electrically connected to the semiconductor laser device 10. With this configuration, the semiconductor laser device 10 is attached to the stem 210, so that heat from the semiconductor laser device 10 can be efficiently dissipated to the outside. In addition, by using the semiconductor laser unit 100 including the semiconductor laser device 10 and the switching element 120, the semiconductor laser device 10 can be turned on and off at high speed, and the laser light can be easily pulsed.
 (6)センサ400は、半導体レーザモジュール200と、バンドパスフィルタ320と、バンドパスフィルタ320を通過した光を受光する受光モジュール300と、を備える。この構成によれば、波長温度依存性の小さい半導体レーザ装置10を用いることで、バンドパスフィルタ320の光の透過幅を狭くすることができる。したがって、バンドパスフィルタ320が半導体レーザ装置10のレーザ光を透過しかつ太陽光を透過しにくくなるため、センサ400における誤認識を抑制できる。そして、センサ400による測定精度の向上を図ることができる。 (6) The sensor 400 includes a semiconductor laser module 200, a bandpass filter 320, and a light receiving module 300 that receives light that has passed through the bandpass filter 320. With this configuration, the use of a semiconductor laser device 10 with small wavelength temperature dependency makes it possible to narrow the light transmission width of the bandpass filter 320. Therefore, the bandpass filter 320 transmits the laser light of the semiconductor laser device 10 but is less likely to transmit sunlight, thereby suppressing erroneous recognition by the sensor 400. This makes it possible to improve the measurement accuracy of the sensor 400.
 <変更例>
 上記実施形態は、以下のように変更して実施することができる。また、上記実施形態および以下の変更例は、技術的に矛盾しない範囲で互いに組み合わせて実施することができる。
<Example of change>
The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other as long as they are not technically inconsistent.
 ・上記実施形態の半導体レーザ装置10の構成を適宜変更してもよい。
 図16は、第1変更例の半導体レーザ装置10を示す。
 この半導体レーザ装置10において、第1電極81は、発光部30の電極接続面31から基板主面21を覆う絶縁膜70の基板被覆部73まで延びている。このように、基板主面21に延びる第1電極81に対して、ピラーやワイヤ等を接続することによって、半導体レーザ装置10を駆動することができる。
The configuration of the semiconductor laser device 10 of the above embodiment may be modified as appropriate.
FIG. 16 shows a semiconductor laser device 10 according to a first modified example.
In this semiconductor laser device 10, the first electrode 81 extends from the electrode connection surface 31 of the light emitting portion 30 to the substrate covering portion 73 of the insulating film 70 that covers the substrate main surface 21. In this manner, the semiconductor laser device 10 can be driven by connecting a pillar, a wire, or the like to the first electrode 81 extending to the substrate main surface 21.
 図17は、第2変更例の半導体レーザ装置10を示す。
 この半導体レーザ装置10において、図16に示す第1変更例の半導体レーザ装置10と同様に、発光部30の電極接続面31から基板主面21を覆う絶縁膜70の基板被覆部73まで延びる第1電極81を有する。さらに、第2変更例の半導体レーザ装置10は、絶縁膜70の基板被覆部72に、半導体基板20の基板主面21の一部を露出する第2開口部72Xを有する。第2電極82は、絶縁膜70の第2開口部72Xから露出する半導体基板20に電気的に接続されている。半導体基板20の基板主面21には発光部30が接続されている。つまり、第2電極82は、半導体基板20を介して発光部30と電気的に接続されている。このように、基板主面21の側に配置された第1電極81および第2電極82によって第2変更例の半導体レーザ装置10を駆動することができる。また、第1電極81および第2電極82が基板主面21側にあることによって、同一方向からのワイヤ等の接続や、ピラーなどによるフリップチップ実装を行うことができる。
FIG. 17 shows a semiconductor laser device 10 according to a second modification.
In this semiconductor laser device 10, like the semiconductor laser device 10 of the first modification shown in FIG. 16, the semiconductor laser device 10 has a first electrode 81 extending from the electrode connection surface 31 of the light emitting portion 30 to the substrate covering portion 73 of the insulating film 70 covering the substrate main surface 21. Furthermore, the semiconductor laser device 10 of the second modification has a second opening 72X in the substrate covering portion 72 of the insulating film 70, which exposes a part of the substrate main surface 21 of the semiconductor substrate 20. The second electrode 82 is electrically connected to the semiconductor substrate 20 exposed from the second opening 72X of the insulating film 70. The light emitting portion 30 is connected to the substrate main surface 21 of the semiconductor substrate 20. That is, the second electrode 82 is electrically connected to the light emitting portion 30 via the semiconductor substrate 20. In this way, the semiconductor laser device 10 of the second modification can be driven by the first electrode 81 and the second electrode 82 arranged on the substrate main surface 21 side. Furthermore, since the first electrode 81 and the second electrode 82 are on the main surface 21 side of the substrate, it is possible to connect wires or the like from the same direction, or to perform flip-chip mounting using pillars or the like.
 なお、第2変更例の半導体レーザ装置10において、第1電極81の形状を、上記実施形態の半導体レーザ装置10の第1電極81の形状と同一とすることもできる。また、第1電極81および第2電極82の形状を適宜変更することができる。 In addition, in the semiconductor laser device 10 of the second modified example, the shape of the first electrode 81 can be the same as the shape of the first electrode 81 of the semiconductor laser device 10 of the above embodiment. In addition, the shapes of the first electrode 81 and the second electrode 82 can be changed as appropriate.
 ・上記実施形態では、発光部30が3つの発光ユニット40および2つのトンネル層60を含む例について説明した。しかし、発光ユニット40の数は、任意であり、3つに限定されない。発光部30は、1つ、2つもしくは4つ以上の発光ユニット40を有してもよい。また、トンネル層60の数は、発光ユニット40の数に応じて調整されるものであり、2つに限定されるものではない。 In the above embodiment, an example was described in which the light-emitting section 30 includes three light-emitting units 40 and two tunnel layers 60. However, the number of light-emitting units 40 is arbitrary and is not limited to three. The light-emitting section 30 may have one, two, or four or more light-emitting units 40. In addition, the number of tunnel layers 60 is adjusted according to the number of light-emitting units 40 and is not limited to two.
 ・上記実施形態において、半導体レーザユニット100からキャパシタ131,132を省略してもよい。また、半導体レーザユニット100からスイッチング素子120を省略してもよい。 - In the above embodiment, the capacitors 131 and 132 may be omitted from the semiconductor laser unit 100. Also, the switching element 120 may be omitted from the semiconductor laser unit 100.
 ・上記実施形態では、半導体レーザモジュール200は、半導体レーザユニット100がステム210に取り付けられ、キャップ220によって覆われたCANパッケージ構造であったが、半導体レーザモジュール200の構成はこれに限定されない。半導体レーザモジュール200は、ステム210、キャップ220、および端子ピン231~234に代えて、基板110上において半導体レーザ装置10、スイッチング素子120、およびキャパシタ131,132を封止する透光性の封止樹脂を備えていてもよい。この場合、半導体レーザモジュール200は、表面実装型のパッケージ構造となる。 - In the above embodiment, the semiconductor laser module 200 has a CAN package structure in which the semiconductor laser unit 100 is attached to the stem 210 and covered by the cap 220, but the configuration of the semiconductor laser module 200 is not limited to this. Instead of the stem 210, the cap 220, and the terminal pins 231 to 234, the semiconductor laser module 200 may have a light-transmitting sealing resin that seals the semiconductor laser device 10, the switching element 120, and the capacitors 131 and 132 on the substrate 110. In this case, the semiconductor laser module 200 has a surface-mount type package structure.
 ・上記実施形態の半導体レーザモジュール200について、半導体レーザ装置10のみを備える構成としてもよい。たとえば、図18および図19に示すように、半導体レーザ装置10がサブマウント140を用いてステム210のヒートシンク212に実装された半導体レーザモジュールとしてもよい。サブマウント140は、半導体レーザ装置10の支持体かつ放熱体である。サブマウント140は、たとえばシリコンまたは窒化アルミニウムによって形成されている。サブマウント140には、半導体レーザ装置10とヒートシンク212とを導通させるための配線パターンやスルーホール等の導電経路(図示略)が形成されている。キャップ220は、ヒートシンク212、サブマウント140、および半導体レーザ装置10を覆った状態でベース211に取り付けられている。キャップ220は上記実施形態と同様に開口部221に透光板222が取り付けられている。なお、半導体レーザ装置10が直接ヒートシンク212に搭載される構成としてもよい。 - The semiconductor laser module 200 of the above embodiment may be configured to include only the semiconductor laser device 10. For example, as shown in FIG. 18 and FIG. 19, the semiconductor laser module may be configured in which the semiconductor laser device 10 is mounted on the heat sink 212 of the stem 210 using a submount 140. The submount 140 is a support and a heat sink for the semiconductor laser device 10. The submount 140 is formed of, for example, silicon or aluminum nitride. The submount 140 is formed with a conductive path (not shown) such as a wiring pattern or a through hole for conducting the semiconductor laser device 10 and the heat sink 212. The cap 220 is attached to the base 211 while covering the heat sink 212, the submount 140, and the semiconductor laser device 10. The cap 220 has a transparent plate 222 attached to the opening 221 as in the above embodiment. The semiconductor laser device 10 may be directly mounted on the heat sink 212.
 また、変更例の半導体レーザモジュール200は、4本の端子ピン231~234に代えて、3本の端子ピン236~238を備える。端子ピン236は、ワイヤW5を介して半導体レーザ装置10と電気的に接続された端子ピンである。端子ピン237は、変更例の半導体レーザモジュール200においては電気的にフローティング状態となる端子ピンである。端子ピン238は、ベース211に接続された端子ピンである。 In addition, the modified semiconductor laser module 200 has three terminal pins 236-238 instead of the four terminal pins 231-234. Terminal pin 236 is a terminal pin that is electrically connected to the semiconductor laser device 10 via wire W5. Terminal pin 237 is a terminal pin that is in an electrically floating state in the modified semiconductor laser module 200. Terminal pin 238 is a terminal pin that is connected to the base 211.
 本明細書において、「AおよびBのうちの少なくとも1つ」とは、「Aのみ、または、Bのみ、または、AおよびBの両方」を意味するものとして理解されるべきである。
 本開示で使用される「~上に」という用語は、文脈によって明らかにそうでないことが示されない限り、「~上に」と「~の上方に」との双方の意味を含む。したがって、「第1部材が第2部材上に形成される」という表現は、或る実施形態では第1部材が第2部材に接触して第2部材上に直接配置され得るが、他の実施形態では第1部材が第2部材に接触することなく第2部材の上方に配置され得ることが意図される。すなわち、「~上に」という用語は、第1部材と第2部材との間に他の部材が形成される構造を排除しない。
In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."
The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "a first member is formed on a second member" is intended to mean that in some embodiments, the first member may be directly disposed on the second member in contact with the second member, while in other embodiments, the first member may be disposed above the second member without contacting the second member. In other words, the term "on" does not exclude a structure in which another member is formed between the first member and the second member.
 本開示で使用されるZ方向は必ずしも鉛直方向である必要はなく、鉛直方向に完全に一致している必要もない。したがって、本開示による種々の構造は、本明細書で説明されるZ方向の「上」および「下」が鉛直方向の「上」および「下」であることに限定されない。例えば、X方向が鉛直方向であってもよく、またはY方向が鉛直方向であってもよい。 The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Thus, the various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.
 <付記>
 上記実施形態および変更例から把握できる技術的思想を以下に記載する。なお、限定する意図ではなく理解の補助のため、付記に記載した構成について実施形態中の対応する符号を括弧書きで示す。符号は、理解の補助のために例として示すものであり、各付記に記載された構成要素は、符号で示される構成要素に限定されるべきではない。
<Additional Notes>
The technical ideas that can be understood from the above-mentioned embodiment and modified examples are described below. Note that, for the configurations described in the appendices, the corresponding symbols in the embodiment are shown in parentheses in order to aid in understanding, not to limit the scope of the invention. The symbols are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the symbols.
 [付記1]
 バリア層(51)と、前記バリア層(51)の厚さ方向(Z方向)において前記バリア層(51)の両側に設けられたウエル層(52)と、を含む活性層(41)と、
 前記活性層(41)の厚さ方向(Z方向)において前記活性層(41)を挟むn型半導体層(42)およびp型半導体層(43)と、を備え、
 前記ウエル層(52)の厚さ(TW)は、前記バリア層(51)の厚さ(TB)よりも厚い
 半導体レーザ装置(10)。
[Appendix 1]
An active layer (41) including a barrier layer (51) and well layers (52) provided on both sides of the barrier layer (51) in a thickness direction (Z direction) of the barrier layer (51);
an n-type semiconductor layer (42) and a p-type semiconductor layer (43) sandwiching the active layer (41) in a thickness direction (Z direction) of the active layer (41);
A semiconductor laser device (10), wherein the well layer (52) has a thickness (TW) greater than a thickness (TB) of the barrier layer (51).
 [付記2]
 前記ウエル層(52)の厚さ(TW)が100Åよりも厚く140Å未満である
 付記1に記載の半導体レーザ装置。
[Appendix 2]
2. The semiconductor laser device according to claim 1, wherein the well layer (52) has a thickness (TW) greater than 100 Å and less than 140 Å.
 [付記3]
 前記ウエル層(52)の厚さ(TW)が110Å以上130Å以下である
 付記2に記載の半導体レーザ装置。
[Appendix 3]
3. The semiconductor laser device according to claim 2, wherein the well layer (52) has a thickness (TW) of 110 Å or more and 130 Å or less.
 [付記4]
 前記バリア層(51)の厚さ(TB)が0Åよりも厚く60Å以下である
 付記1~3のいずれか1つに記載の半導体レーザ装置。
[Appendix 4]
4. The semiconductor laser device according to claim 1, wherein the barrier layer (51) has a thickness (TB) of more than 0 Å and not more than 60 Å.
 [付記5]
 前記バリア層(51)の厚さ(TB)が30Å以上60Å以下である
 付記4に記載の半導体レーザ装置。
[Appendix 5]
5. The semiconductor laser device according to claim 4, wherein the barrier layer (51) has a thickness (TB) of 30 Å or more and 60 Å or less.
 [付記6]
 前記活性層(41)は、光を出射する端面(33)を含み、前記端面(33)における発光幅を270μmとするように構成されている
 付記1~5のいずれか1つに記載の半導体レーザ装置。
[Appendix 6]
The active layer (41) includes an end face (33) for emitting light, and is configured to have an emission width at the end face (33) of 270 μm.
 [付記7]
 前記活性層(41)は、光を出射する端面(33)を含み、前記端面(33)における発光幅を50μm以上300μm以下とするように構成されている
 付記1~5のいずれか1つに記載の半導体レーザ装置。
[Appendix 7]
The active layer (41) includes an end face (33) for emitting light, and is configured to have an emission width at the end face (33) of 50 μm or more and 300 μm or less.
 [付記8]
 前記ウエル層(52)の厚さ(TW)が115Åであり、前記バリア層(51)の厚さ(TB)が30Åである
 付記7に記載の半導体レーザ装置。
[Appendix 8]
8. The semiconductor laser device according to claim 7, wherein the well layer (52) has a thickness (TW) of 115 Å and the barrier layer (51) has a thickness (TB) of 30 Å.
 [付記9]
 前記ウエル層(52)は、
 前記バリア層(51)に隣り合う第1ウエル層(52A)と、
 前記バリア層(51)に対して前記第1ウエル層(52A)とは反対側に配置された第2ウエル層(52B)と、を含み、
 前記活性層(41)は、
 前記第1ウエル層(52A)と前記n型半導体層(42)とに挟まれる第1ガイド層(53)と、
 前記第2ウエル層(52B)と前記p型半導体層(43)とに挟まれる第2ガイド層(54)と、を含む、付記1~8のいずれか1つに記載の半導体レーザ装置。
[Appendix 9]
The well layer (52) is
a first well layer (52A) adjacent to the barrier layer (51);
a second well layer (52B) disposed on the opposite side of the barrier layer (51) to the first well layer (52A);
The active layer (41) is
a first guide layer (53) sandwiched between the first well layer (52A) and the n-type semiconductor layer (42);
9. The semiconductor laser device according to claim 1, further comprising a second guide layer (54) sandwiched between the second well layer (52B) and the p-type semiconductor layer (43).
 [付記10]
 前記n型半導体層(42)は、
 前記活性層(41)に隣り合う第1n型クラッド層(44)と、
 前記第1n型クラッド層(44)に対して前記活性層(41)とは反対側に配置された第2n型クラッド層(45)と、を含み、
 前記p型半導体層(43)は、
 前記活性層(41)に隣り合う第1p型クラッド層(46)と、
 前記第1p型クラッド層(46)に対して前記活性層(41)とは反対側に配置された第2p型クラッド層(47)と、を含む、付記1~9のいずれか1つに記載の半導体レーザ装置。
[Appendix 10]
The n-type semiconductor layer (42) is
a first n-type cladding layer (44) adjacent to the active layer (41);
a second n-type cladding layer (45) disposed on the opposite side of the first n-type cladding layer (44) to the active layer (41);
The p-type semiconductor layer (43) is
a first p-type cladding layer (46) adjacent to the active layer (41);
A second p-type cladding layer (47) disposed on the opposite side of the first p-type cladding layer (46) to the active layer (41).
 [付記11]
 前記活性層(41)、前記n型半導体層(42)、および前記p型半導体層(43)を含む複数の発光ユニット(40)が前記活性層(41)の厚さ方向(Z方向)に積層されている
 付記1~10のいずれか1つに記載の半導体レーザ装置。
[Appendix 11]
The semiconductor laser device according to any one of claims 1 to 10, wherein a plurality of light-emitting units (40) including the active layer (41), the n-type semiconductor layer (42), and the p-type semiconductor layer (43) are stacked in a thickness direction (Z direction) of the active layer (41).
 [付記12]
 前記複数の発光ユニット(40)は、トンネル層(60)を挟んで積層されている
 付記11に記載の半導体レーザ装置。
[Appendix 12]
The semiconductor laser device according to claim 11, wherein the plurality of light emitting units (40) are stacked with a tunnel layer (60) interposed therebetween.
 [付記13]
 付記1~12のいずれか1つに記載の半導体レーザ装置(10)と、
 前記半導体レーザ装置(10)が取り付けられたステム(210)と、
 前記ステム(210)に取り付けられ、前記半導体レーザ装置(10)を覆うとともに前記半導体レーザ装置(10)からのレーザ光が通過する開口部(221)を有するキャップ(220)と、
 前記半導体レーザ装置(10)と電気的に接続された端子ピン(231~234)と、を備える、半導体レーザモジュール(200)。
[Appendix 13]
A semiconductor laser device (10) according to any one of appendices 1 to 12;
a stem (210) on which the semiconductor laser device (10) is attached;
a cap (220) attached to the stem (210), covering the semiconductor laser device (10) and having an opening (221) through which laser light from the semiconductor laser device (10) passes;
A semiconductor laser module (200) comprising terminal pins (231 to 234) electrically connected to the semiconductor laser device (10).
 [付記14]
 付記13に記載の半導体レーザモジュール(200)と、
 バンドパスフィルタ(320)と、前記バンドパスフィルタ(320)を通過した光を受光する受光素子(310)と、を含む受光モジュール(300)と、を備える、センサ(400)。
[Appendix 14]
A semiconductor laser module (200) according to claim 13;
A sensor (400) comprising a light receiving module (300) including a bandpass filter (320) and a light receiving element (310) that receives light that has passed through the bandpass filter (320).
 以上の説明は単に例示である。本開示の技術を説明する目的のために列挙された構成要素および方法(製造プロセス)以外に、より多くの考えられる組み合わせおよび置換が可能であることを当業者は認識し得る。本開示は、特許請求の範囲および付記を含む本開示の範囲内に含まれるすべての代替、変形、および変更を包含することが意図される。 The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) enumerated for purposes of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that are within the scope of the present disclosure, including the claims and appendices.
 10…半導体レーザ装置
 20…半導体基板
 21…基板主面
 22…基板裏面
 23~26…基板側面
 30…発光部
 31…電極接続面
 32…基板接続面
 33,34…発光部端面
 35,36…発光部側面
 40…発光ユニット
 41…活性層
 42…n型半導体層
 43…p型半導体層
 44…第1n型クラッド層
 45…第2n型クラッド層
 46…第1p型クラッド層
 47…第2p型クラッド層
 51…バリア層
 52…ウエル層
 52A…第1ウエル層
 52B…第2ウエル層
 53…第1ガイド層
 54…第2ガイド層
 60…トンネル層
 61…p型トンネル層
 62…n型トンネル層
 70…絶縁膜
 71…上面
 71X…第1開口部
 72,73…基板被覆部
 72X…第2開口部
 74…発光部被覆部
 81…第1電極
 82…第2電極
 100…半導体レーザユニット
 110…基板
 111…基板主面
 111A~111C…第1~第3主面側配線
 112…基板裏面
 112A…第1裏面側配線
 112B…第2裏面側配線
 113,114…スルーホール
 120…スイッチング素子
 121…ソース電極
 122…ゲート電極
 131,132…キャパシタ
 140…サブマウント
 200…半導体レーザモジュール
 210…ステム
 211…ベース
 212…ヒートシンク
 220…キャップ
 221…開口部
 222…透光板
 231~234,236~238…端子ピン
 235…絶縁材
 300…受光モジュール
 310…受光素子
 320…バンドパスフィルタ
 400…センサ
 R…領域
 L1…レーザ光
 SD…導電性接合材
 SP…収容空間
 TB…バリア層の厚さ
 TW,TWA,TWB…ウエル層の厚さ
 W1~W5…ワイヤ
REFERENCE SIGNS LIST 10...Semiconductor laser device 20...Semiconductor substrate 21...Substrate main surface 22...Substrate back surface 23-26...Substrate side surface 30...Light emitting portion 31...Electrode connection surface 32...Substrate connection surface 33, 34...Light emitting portion end surface 35, 36...Light emitting portion side surface 40...Light emitting unit 41...Active layer 42...n-type semiconductor layer 43...p-type semiconductor layer 44...First n-type cladding layer 45...Second n-type cladding layer 46...First p-type cladding layer 47...Second p-type cladding layer 51...Barrier layer 52...Well layer 52A...First well layer 52B...Second well layer 53...First guide layer 54...Second guide layer 60...Tunnel layer 61...p-type tunnel layer 62...n-type tunnel layer 70...Insulating film 71...Upper surface 71X...First opening 72, 73...Substrate covering portion 72X...second opening 74...light emitting portion covering portion 81...first electrode 82...second electrode 100...semiconductor laser unit 110...substrate 111...substrate main surface 111A-111C...first to third main surface side wiring 112...substrate back surface 112A...first back surface side wiring 112B...second back surface side wiring 113, 114...through hole 120...switching element 121...source electrode 122...gate electrode 131, 132...capacitor 140...submount 200...semiconductor laser module 210...stem 211...base 212...heat sink 220...cap 221...opening 222...translucent plate 231-234, 236-238...terminal pin 235...insulating material 300...light receiving module 310...light receiving element 320...bandpass filter 400...sensor R...area L1...laser light SD...conductive bonding material SP...accommodation space TB...barrier layer thickness TW, TWA, TWB...well layer thickness W1 to W5...wires

Claims (14)

  1.  バリア層と、前記バリア層の厚さ方向において前記バリア層の両側に設けられたウエル層と、を含む活性層と、
     前記活性層の厚さ方向において前記活性層を挟むn型半導体層およびp型半導体層と、を備え、
     前記ウエル層の厚さは、前記バリア層の厚さよりも厚い
     半導体レーザ装置。
    an active layer including a barrier layer and well layers provided on both sides of the barrier layer in a thickness direction of the barrier layer;
    an n-type semiconductor layer and a p-type semiconductor layer sandwiching the active layer in a thickness direction of the active layer,
    the well layer is thicker than the barrier layer.
  2.  前記ウエル層の厚さが100Åよりも厚く140Å未満である
     請求項1に記載の半導体レーザ装置。
    2. The semiconductor laser device according to claim 1, wherein the well layer has a thickness greater than 100 Å and less than 140 Å.
  3.  前記ウエル層の厚さが110Å以上130Å以下である
     請求項2に記載の半導体レーザ装置。
    3. The semiconductor laser device according to claim 2, wherein the well layer has a thickness of 110 Å or more and 130 Å or less.
  4.  前記バリア層の厚さが0Åよりも厚く60Å以下である
     請求項1~3のいずれか一項に記載の半導体レーザ装置。
    4. The semiconductor laser device according to claim 1, wherein the barrier layer has a thickness greater than 0 Å and equal to or less than 60 Å.
  5.  前記バリア層の厚さが30Å以上60Å以下である
     請求項4に記載の半導体レーザ装置。
    5. The semiconductor laser device according to claim 4, wherein the barrier layer has a thickness of 30 Å or more and 60 Å or less.
  6.  前記活性層は、光を出射する端面を含み、前記端面における発光幅を270μmとするように構成されている
     請求項1~5のいずれか一項に記載の半導体レーザ装置。
    6. The semiconductor laser device according to claim 1, wherein the active layer includes an end face for emitting light, and is configured so that an emission width at the end face is 270 μm.
  7.  前記活性層は、光を出射する端面を含み、前記端面における発光幅を50μm以上300μm以下とするように構成されている
     請求項1~5のいずれか一項に記載の半導体レーザ装置。
    6. The semiconductor laser device according to claim 1, wherein the active layer includes an end face for emitting light, and the end face has an emission width of 50 μm or more and 300 μm or less.
  8.  前記ウエル層の厚さが115Åであり、前記バリア層の厚さが30Åである
     請求項7に記載の半導体レーザ装置。
    8. The semiconductor laser device according to claim 7, wherein the well layer has a thickness of 115 Å, and the barrier layer has a thickness of 30 Å.
  9.  前記ウエル層は、
     前記バリア層に隣り合う第1ウエル層と、
     前記バリア層に対して前記第1ウエル層とは反対側に配置された第2ウエル層と、
    を含み、
     前記活性層は、
     前記第1ウエル層と前記n型半導体層とに挟まれる第1ガイド層と、
     前記第2ウエル層と前記p型半導体層とに挟まれる第2ガイド層と、
    を含む、請求項1~8のいずれか一項に記載の半導体レーザ装置。
    The well layer is
    a first well layer adjacent to the barrier layer;
    a second well layer disposed on an opposite side of the barrier layer from the first well layer;
    Including,
    The active layer is
    a first guide layer sandwiched between the first well layer and the n-type semiconductor layer;
    a second guide layer sandwiched between the second well layer and the p-type semiconductor layer;
    9. The semiconductor laser device according to claim 1, further comprising:
  10.  前記n型半導体層は、
     前記活性層に隣り合う第1n型クラッド層と、
     前記第1n型クラッド層に対して前記活性層とは反対側に配置された第2n型クラッド層と、
    を含み、
     前記p型半導体層は、
     前記活性層に隣り合う第1p型クラッド層と、
     前記第1p型クラッド層に対して前記活性層とは反対側に配置された第2p型クラッド層と、
    を含む、請求項1~9のいずれか一項に記載の半導体レーザ装置。
    The n-type semiconductor layer is
    a first n-type cladding layer adjacent to the active layer;
    a second n-type cladding layer disposed on an opposite side of the first n-type cladding layer from the active layer;
    Including,
    The p-type semiconductor layer is
    a first p-type cladding layer adjacent to the active layer;
    a second p-type cladding layer disposed on an opposite side of the first p-type cladding layer from the active layer;
    10. The semiconductor laser device according to claim 1, further comprising:
  11.  前記活性層、前記n型半導体層、および前記p型半導体層を含む複数の発光ユニットが前記活性層の厚さ方向に積層されている
     請求項1~10のいずれか一項に記載の半導体レーザ装置。
    11. The semiconductor laser device according to claim 1, wherein a plurality of light-emitting units, each including the active layer, the n-type semiconductor layer, and the p-type semiconductor layer, are stacked in a thickness direction of the active layer.
  12.  前記複数の発光ユニットは、トンネル層を挟んで積層されている
     請求項11に記載の半導体レーザ装置。
    The semiconductor laser device according to claim 11 , wherein the plurality of light emitting units are stacked with a tunnel layer interposed therebetween.
  13.  請求項1~12のいずれか一項に記載の半導体レーザ装置と、
     前記半導体レーザ装置が取り付けられたステムと、
     前記ステムに取り付けられ、前記半導体レーザ装置を覆うとともに前記半導体レーザ装置からのレーザ光が通過する開口部を有するキャップと、
     前記半導体レーザ装置と電気的に接続された端子ピンと、
    を備える、半導体レーザモジュール。
    A semiconductor laser device according to any one of claims 1 to 12,
    a stem on which the semiconductor laser device is attached; and
    a cap attached to the stem, covering the semiconductor laser device and having an opening through which laser light from the semiconductor laser device passes;
    a terminal pin electrically connected to the semiconductor laser device;
    A semiconductor laser module comprising:
  14.  請求項13に記載の半導体レーザモジュールと、
     バンドパスフィルタと、前記バンドパスフィルタを通過した光を受光する受光素子と、を含む受光モジュールと、
    を備える、センサ。
    The semiconductor laser module according to claim 13 ;
    a light receiving module including a bandpass filter and a light receiving element that receives light that has passed through the bandpass filter;
    A sensor comprising:
PCT/JP2023/038388 2022-11-01 2023-10-24 Semiconductor laser device, semiconductor laser module, and sensor WO2024095835A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174226A (en) * 2001-09-28 2003-06-20 Mitsui Chemicals Inc Semiconductor laser device and laser module using the same
JP2013168587A (en) * 2012-02-16 2013-08-29 Sharp Corp Light emitting device, semiconductor laser element and lighting device
WO2020183812A1 (en) * 2019-03-11 2020-09-17 ローム株式会社 Semiconductor light emitting device
JP2021163822A (en) * 2020-03-31 2021-10-11 浜松ホトニクス株式会社 Semiconductor laser element and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174226A (en) * 2001-09-28 2003-06-20 Mitsui Chemicals Inc Semiconductor laser device and laser module using the same
JP2013168587A (en) * 2012-02-16 2013-08-29 Sharp Corp Light emitting device, semiconductor laser element and lighting device
WO2020183812A1 (en) * 2019-03-11 2020-09-17 ローム株式会社 Semiconductor light emitting device
JP2021163822A (en) * 2020-03-31 2021-10-11 浜松ホトニクス株式会社 Semiconductor laser element and manufacturing method thereof

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