WO2024093701A1 - 静电放电保护器件 - Google Patents

静电放电保护器件 Download PDF

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Publication number
WO2024093701A1
WO2024093701A1 PCT/CN2023/125966 CN2023125966W WO2024093701A1 WO 2024093701 A1 WO2024093701 A1 WO 2024093701A1 CN 2023125966 W CN2023125966 W CN 2023125966W WO 2024093701 A1 WO2024093701 A1 WO 2024093701A1
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WIPO (PCT)
Prior art keywords
region
doping region
well region
electrostatic discharge
gate structure
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Ceased
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PCT/CN2023/125966
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English (en)
French (fr)
Inventor
黄勇
黄璐
周婉艺
毕睿
吴林
史海丽
郭乐乐
朱丽娟
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Publication of WO2024093701A1 publication Critical patent/WO2024093701A1/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H10D89/813—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements specially adapted to provide an electrical current path other than the field-effect induced current path
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, and in particular to an electrostatic discharge protection device.
  • Electrostatic discharge refers to the charge transfer phenomenon that occurs when objects with different electric potentials are close to or in contact with each other. With the continuous reduction of semiconductor manufacturing process size and the continuous expansion of integrated circuit scale, the chip is increasingly seriously damaged by static electricity during production, transportation and use. Therefore, it is of great significance to study electrostatic discharge protection.
  • the purpose of the present disclosure is to provide an electrostatic discharge protection device.
  • the electrostatic discharge protection device includes a substrate and a gate structure located on the substrate; a first well region and a second well region connected to each other are formed in the substrate, the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from above a portion of the first well region to above a portion of the second well region; a first doped region and a second doped region are formed on the top of the first well region, the first doped region and the second doped region are located on one side of the gate structure, the first doped region has the first conductivity type, and the second doped region has the second conductivity type; a third doped region and a fourth doped region are formed on the top of the second well region, the third doped region and the fourth doped region are located on the other side of the gate structure, the third doped region has the first conductivity type, and the fourth doped region has the second conduct
  • the first well region, the second well region and the third doped region constitute a first parasitic transistor; the second doped region, the first well region and the second well region constitute a second parasitic transistor; the first parasitic transistor and the second parasitic transistor share the first well region and the second well region, and are used together for electrostatic discharge.
  • the first well region, the second well region and the third doped region respectively serve as the collector, base and emitter of the first parasitic transistor; the second well region, the first well region and the second doped region respectively serve as the collector, base and emitter of the second parasitic transistor.
  • the first doped region and the second doped region are arranged along the width of the conductive channel below the gate structure. Arrangement in degree direction.
  • the second doping region is formed at both ends of the first doping region.
  • the third doping region is located between the gate structure and the fourth doping region, and the third doping region and the fourth doping region extend along a width direction of the conductive trench below the gate structure.
  • an isolation structure is formed at the top of the substrate between the gate structure and the first doping region, at the top of the substrate between the gate structure and the second doping region, and at the top of the substrate between the first doping region and the second doping region; and/or an isolation structure is formed at the top of the substrate between the third doping region and the fourth doping region.
  • a first side wall of the gate structure contacts the isolation structure, and a second side wall of the gate structure contacts the third doping region.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first potential end is an anode end
  • the second potential end is a cathode end
  • the electrostatic discharge protection device includes a substrate and a gate structure located on the substrate, wherein a first well region and a second well region connected to each other are formed in the substrate, the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from above a portion of the first well region to above a portion of the second well region; a first doped region and a second doped region are formed on the top of the first well region, the first doped region and the second doped region are located on one side of the gate structure, the first doped region has the first conductivity type, and the second doped region has the second conductivity type; a third doped region and a fourth doped region are formed on the top of the second well region, the third doped region and the fourth doped region are located on the other side of the gate structure, the third doped region has the first conductivity type, and the fourth doped region has the second conductivity type.
  • the first well region, the second well region and the third doped region can constitute a first parasitic transistor
  • the second doped region, the first well region and the second well region can constitute a second parasitic transistor
  • the first parasitic transistor and the second parasitic transistor share the first well region and the second well region and are thus connected to each other
  • the first parasitic transistor can trigger the second parasitic transistor to turn on, thereby forming an SCR path with strong electrostatic discharge capability.
  • FIG. 1 is a top view of an LDMOS for ESD protection.
  • FIG. 2 is a cross-sectional view of the LDMOS shown in FIG. 1 and a schematic diagram of an equivalent triode circuit therein.
  • FIG. 3 is a current-voltage curve diagram of an LDMOS for ESD protection.
  • FIG. 4 is a top view of an electrostatic discharge protection device according to an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view of the electrostatic discharge protection device shown in FIG. 4 along the BB line and its internal equivalent Schematic diagram of a triode circuit.
  • FIG. 6 is a cross-sectional view of the electrostatic discharge protection device shown in FIG. 4 along line CC and a schematic diagram of an equivalent triode circuit therein.
  • FIG. 7 is a current-voltage curve diagram of an electrostatic discharge protection device according to an embodiment of the present disclosure.
  • FIG. 1 to FIG. 2 101-N well; 102-P well; 103-gate; 104-first N+ region;
  • FIG. 4 to FIG. 6 200 - substrate; 201 - first well region; 202 - second well region; 203 - first doping region; 204 - second doping region; 205 - third doping region; 206 - fourth doping region; 207 - isolation structure; 300 - gate structure.
  • an ESD protection structure is usually used between the anode and the cathode, and the type of the ESD protection structure is usually the same as the type of the protected circuit.
  • a high-voltage LDMOS Laser Diffused Metal Oxide Semiconductor
  • LDMOS Laterally Diffused Metal Oxide Semiconductor
  • Fig. 1 is a top view of an LDMOS for ESD protection.
  • Fig. 2 is a cross-sectional view of the LDMOS shown in Fig. 1 and a schematic diagram of an equivalent triode circuit inside the LDMOS.
  • Fig. 2 is a cross-sectional view along line AA in Fig. 1, and the LDMOS shown in Figs. 1 and 2 is an N-type.
  • a parasitic NPN transistor T1 is formed between the N-well 101 (N-well), the P-well 102 (P-well) and the first N+ region 104 of the LDMOS, wherein the N-well 101 is the collector of T1, the P-well 102 is the base of T1, and the first N+ region 104 is the emitter of T1.
  • the reverse PN junction of the N-well 101 and the P-well 102 forms a leakage current, and the ESD pulse can also cause the gate 103 voltage to rise instantly through the coupling effect of the parasitic capacitance, thereby forming an inversion layer on the substrate surface below the gate 103. Therefore, as the voltage at the anode terminal increases, the leakage current gradually increases.
  • FIG3 is a current-voltage curve of the LDMOS used for ESD protection.
  • the leakage current reaches a certain value
  • the base-emitter of the parasitic NPN tube T1 is forward biased, and the parasitic NPN tube T1 is turned on to form a current from the anode to the cathode, corresponding to the trigger point (Vt1, It1) of FIG3, thereby discharging the ESD current and protecting the protected circuit.
  • the parasitic NPN tube T1 After the parasitic NPN tube T1 is triggered, the LDMOS will have a rapid snapback phenomenon. After the voltage returns to the holding voltage Vh, as the ESD pulse further increases, the LDMOS continues to discharge, and the voltage at both ends increases accordingly. After reaching the breakdown voltage Vt2, the LDMOS burns out.
  • LDMOS is used for ESD protection, usually with a parallel multi-finger structure, which can increase the total device width.
  • the trigger voltage Vt1 of the parasitic NPN tube T1 is relatively high.
  • the transistors near the middle part of the parallel multi-finger structure are easier to turn on. Once some of the finger transistors are turned on, hysteresis will occur immediately. The voltage of LDMOS will drop rapidly until it reaches the breakdown voltage Vt2. It is difficult for other finger transistors that have not been turned on to turn on, which makes the electrostatic discharge ability of the LDMOS used for ESD protection poor and cannot meet the ESD protection requirements of high-voltage devices.
  • the electrostatic discharge protection device includes a substrate and a gate structure located on the substrate.
  • a first well region and a second well region connected to each other are formed in the substrate, the first well region has a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type; the gate structure spans from the top of part of the first well region to the top of part of the second well region.
  • a first doping region and a second doping region are formed on the top of the first well region, the first doping region and the second doping region are located on one side of the gate structure, the first doping region has a first conductivity type, and the second doping region has a second conductivity type; a third doping region and a fourth doping region are formed on the top of the second well region, the third doping region and the fourth doping region are located on the other side of the gate structure, the third doping region has a first conductivity type, and the fourth doping region has a second conductivity type.
  • the first doping region and the second doping region are electrically connected to the first potential end, and the gate structure and the third doping region are electrically connected to the second potential end.
  • the first well region, the second well region and the third doped region can constitute a first parasitic transistor
  • the second doped region, the first well region and the second well region can constitute a second parasitic transistor
  • the first parasitic transistor and the second parasitic transistor share the first well region and the second well region and are thus connected to each other
  • the first parasitic transistor can trigger the second parasitic transistor to turn on, thereby forming an SCR (Silicon Controlled Rectifier, Chinese name: silicon controlled rectifier) path with strong electrostatic discharge capability, which is beneficial to improving the electrostatic discharge capability of the circuit and meeting the electrostatic discharge protection requirements of high-voltage devices.
  • SCR Silicon Controlled Rectifier
  • FIG4 is a top view of an electrostatic discharge protection device according to an embodiment of the present disclosure.
  • FIG5 is a cross-sectional view of the electrostatic discharge protection device shown in FIG4 along the position shown by the BB line and a schematic diagram of an equivalent triode circuit therein.
  • FIG6 is a cross-sectional view of the electrostatic discharge protection device shown in FIG4 along the CC line and a schematic diagram of an equivalent triode circuit therein.
  • the electrostatic discharge protection device includes a substrate 200 and a gate structure 300 located on the substrate 200 .
  • the substrate 200 is formed with a first well region 201 and a second well region 202 connected to each other, for example, as shown in FIG. 5 and FIG. 6 In the horizontal direction, the boundary of the first well region 201 is connected to the boundary of the second well region 202, the first well region 201 has a first conductivity type, and the second well region 202 has a second conductivity type opposite to the first conductivity type.
  • the substrate 200 may be a silicon substrate, but is not limited thereto.
  • the substrate 200 may also be a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc.
  • Certain doping particles may be injected into the substrate 200 according to design requirements to change electrical parameters.
  • the gate structure 300 spans from above a portion of the first well region 201 to above a portion of the second well region 202, that is, the gate structure 300 is located at the junction of the first well region 201 and the second well region 202, and the gate structure 300 covers a portion of the first well region 201 and a portion of the second well region 202.
  • the gate structure 300 may include a gate oxide layer (not shown in the figure) located above the substrate 200 and a gate (not shown in the figure) located on the gate oxide layer.
  • the material of the gate oxide layer may include silicon oxide, and the gate may be a polysilicon gate, but is not limited thereto.
  • a first doping region 203 and a second doping region 204 are formed on the top of the first well region 201.
  • the first doping region 203 and the second doping region 204 are located on one side of the gate structure 300.
  • the first doping region 203 has a first conductivity type
  • the second doping region 204 has a second conductivity type.
  • a third doping region 205 and a fourth doping region 206 are formed on the top of the second well region 202.
  • the third doping region 205 and the fourth doping region 206 are located on the other side of the gate structure 300.
  • the third doping region 205 has a first conductivity type
  • the fourth doping region 206 has a second conductivity type.
  • the first doping region 203 and the second doping region 204 are electrically connected to a first potential terminal
  • the gate structure 300 and the third doping region 205 are electrically connected to a second potential terminal.
  • the first conductivity type may be N-type, and the second conductivity type may be P-type, but the present invention is not limited thereto.
  • the first well region 201 is an N-well
  • the second well region 202 is a P-well
  • the first doping region 203 and the third doping region 205 are N+ doping regions
  • the second doping region 204 and the fourth doping region 206 are P+ doping regions.
  • the first well region 201, the second well region 202, the first doping region 203, the second doping region 204, the third doping region 204 and the fourth doping region 205 can all be formed by implanting doping substances into the substrate 200.
  • the first potential end may be an anode end (Anode), and the second potential end may be a cathode end (Cathode), but is not limited thereto.
  • the first well region 201, the second well region 202 and the third doped region 205 constitute a first parasitic transistor T1
  • the first well region 201, the second well region 202 and the third doped region 205 serve as the collector, base and emitter of the first parasitic transistor T1, respectively.
  • the first parasitic transistor T1 is an NPN transistor.
  • the second doped region 204, the first well region 201 and the second well region 202 constitute a second parasitic transistor T2
  • the second well region 202, the first well region 201 and the second doped region 204 are respectively are the collector, base and emitter of the second parasitic transistor T2.
  • the second parasitic transistor T2 is a PNP transistor.
  • the first parasitic transistor T1 and the second parasitic transistor T2 share the first well region 201 and the second well region 202, that is, the collector of the first parasitic transistor T1 and the base of the second parasitic transistor T2 are shared, and the base of the first parasitic transistor T1 and the collector of the second parasitic transistor T2 are shared.
  • the collector of the first parasitic transistor T1 and the base of the second parasitic transistor T2 are connected, and the base of the first parasitic transistor T1 and the collector of the second parasitic transistor T2 are connected.
  • the first parasitic transistor T1 and the second parasitic transistor T2 are used together for electrostatic discharge.
  • FIG7 is a current-voltage curve diagram of an electrostatic discharge protection device of an embodiment of the present disclosure.
  • the ESD pulse can also cause the voltage of the gate structure 300 to rise instantly through the coupling effect of the parasitic capacitance, thereby forming an inversion layer on the surface of the substrate below the gate structure 300. Therefore, as the voltage at the anode end increases, the leakage current gradually increases.
  • the base-emitter of the first parasitic transistor T1 is forward biased, and the first parasitic transistor T1 is turned on to form a current from the anode to the cathode, corresponding to the trigger point (Vt1, It1) of FIG7, thereby discharging the ESD current and protecting the protected circuit.
  • the electrostatic discharge protection device After the first parasitic transistor T1 is triggered, the electrostatic discharge protection device will experience a rapid hysteresis phenomenon, and the voltage returns to the holding voltage Vh.
  • the first parasitic transistor T1 continues to discharge, and the collector current of the first parasitic transistor T1 is fed back to the base of the second parasitic transistor T2, making the base-emitter of the second parasitic transistor T2 forward biased, so that the second parasitic transistor T2 is turned on, corresponding to the second trigger point (Vt1', It1') in Figure 7.
  • the PNPN SCR path is formed, and the secondary hysteresis phenomenon occurs, and the voltage of the electrostatic discharge protection structure returns to the holding voltage Vh'.
  • the ESD pulse increases, most of the ESD current is quickly discharged through the SCR path until it reaches the secondary breakdown point (Vt2, It2).
  • the electrostatic discharge protection structure disclosed in the present invention is a secondary triggered device, which is embedded with a second parasitic transistor T2 connected to the first parasitic transistor T1 on the basis of the traditional LDMOS device for ESD, so as to form an SCR path in the electrostatic discharge protection structure.
  • the first parasitic transistor T1 is first triggered to discharge part of the ESD current, and the electrostatic discharge protection device has the first hysteresis phenomenon; when the ESD pulse continues to increase, the second parasitic transistor T2 is triggered to conduct, forming an SCR path, and the second hysteresis phenomenon occurs.
  • the ESD pulse increases further, the ESD current is assisted to be discharged through the SCR path until the secondary breakdown point of the electrostatic discharge protection device is reached.
  • the electrostatic discharge protection device disclosed in the present invention is superior to the traditional ESD protection device. Embedding a second parasitic transistor on the basis of the LDMOS device can greatly increase the ability of the electrostatic discharge protection device to discharge ESD current.
  • the gate structure 300 may be elongated along the X direction, the width direction of the conductive channel below the gate structure 300 is the X direction, and the first doping region 203 and the second doping region 204 may be arranged along the width direction of the conductive channel below the gate structure 300.
  • the widths of the first doping region 203 and the second doping region 204 may be the same, and the ends of the first doping region 203 and the second doping region 204 are aligned, which helps to reduce the size of the electrostatic discharge protection device, but is not limited thereto.
  • both ends of the first doping region 203 may be formed with the second doping region 204, which is beneficial to improve the discharge uniformity of the electrostatic discharge protection device, but is not limited thereto.
  • the second doping region 204 may be provided only at one end of the first doping region 203.
  • the third doping region 205 may be located between the gate structure 300 and the fourth doping region 206 , and the third doping region 205 and the fourth doping region 206 may extend along the width direction of the conductive channel below the gate structure 300 .
  • an isolation structure 207 is formed on the top of the substrate between the gate structure 300 and the first doping region 203, the top of the substrate between the gate structure 300 and the second doping region 204, and the top of the substrate between the first doping region 203 and the second doping region 204.
  • An isolation structure 207 may also be formed on the top of the substrate between the third doping region 205 and the fourth doping region 206.
  • the isolation structure 207 may be a field oxide (FOX) or a shallow trench isolation (STI) using a local oxidation of silicon (LOCOS) process.
  • the first sidewall of the gate structure 300 contacts the isolation structure 207
  • the second sidewall of the gate structure 300 contacts the third doping region 205
  • the first sidewall and the second sidewall are opposite to each other.
  • the first sidewall of the gate structure 300 is the left sidewall
  • the second sidewall is the right sidewall
  • the first sidewall contacts the isolation structure 207 between the gate structure 300 and the first doping region 203 and the isolation structure 207 between the gate structure 300 and the second doping region 204
  • the second sidewall contacts the third doping region 205.
  • the electrostatic discharge protection device of this embodiment includes a substrate 200 and a gate structure 300 located on the substrate 200; a first well region 201 and a second well region 202 connected to each other are formed in the substrate 200, the first well region 201 has a first conductivity type, and the second well region 202 has a second conductivity type opposite to the first conductivity type; the gate structure 300 spans from above a portion of the first well region 201 to above a portion of the second well region 202; a first doping region 203 and a second doping region 204 are formed on the top of the first well region 201, the first doping region 203 and the second doping region 204 are located on one side of the gate structure 300, the first doping region 203 has a first conductivity type, and the second doping region 204 has a second conductivity type; a third doping region 203 is formed on the top of the second well region 202.
  • the third doping region 205 and the fourth doping region 206 are located on the other side of the gate structure 300, the third doping region 205 has a first conductivity type, and the fourth doping region 206 has a second conductivity type.
  • the first well region 201, the second well region 202 and the third doping region 205 can constitute a first parasitic transistor T1
  • the second doping region 204, the first well region 201 and the second well region 202 can constitute a second parasitic transistor T2
  • the first parasitic transistor T1 and the second parasitic transistor T2 share the first well region 201 and the second well region 202 and are thus connected to each other
  • the first parasitic transistor T1 can trigger the second parasitic transistor T2 to turn on, thereby forming an SCR path with a strong electrostatic discharge capability, which is beneficial to improving the electrostatic discharge capability of the circuit and meeting the electrostatic discharge protection requirements of high-voltage devices.

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Abstract

本公开提供一种静电放电保护器件。所述静电放电保护器件包括基底和位于基底上的栅极结构，基底中形成有相连接的第一阱区和第二阱区，第一阱区具有第一导电类型，第二阱区具有第二导电类型，栅极结构从部分第一阱区的上方跨越到部分第二阱区的上方，第一阱区的顶部形成有位于栅极结构一侧的第一掺杂区和第二掺杂区，第一掺杂区具有第一导电类型，第二掺杂区具有第二导电类型，第二阱区的顶部形成有位于栅极结构另一侧的第三掺杂区和第四掺杂区，第三掺杂区具有第一导电类型，第四掺杂区具有第二导电类型。如此静电放电保护器件内可以形成用于泄放静电的第一寄生三极管和第二寄生三极管，有利于提升电路的静电泄放能力。

Description

静电放电保护器件 技术领域
本公开涉及半导体器件技术领域，特别涉及一种静电放电保护器件。
背景技术
静电放电(Electro-Static Discharge，ESD)现象是指具有不同电势的物体相互靠近或接触时发生的电荷转移现象。随着半导体制造工艺尺寸的不断缩小和集成电路规模的不断扩大，芯片在生产、运输和使用过程中受到静电的破坏越来越严重。因此，研究静电放电保护具有重要意义。
目前，一些高压应用的电压较高，对于集成电路(Integrated Circuit，IC)的静电放电保护提出了更高的要求。但是，传统的静电放电保护结构的静电泄放能力不足。
发明内容
本公开的目的在于提供一种静电放电保护器件。
为了实现上述目的，本公开提供的静电放电保护器件包括基底和位于所述基底上的栅极结构；所述基底中形成有相连接的第一阱区和第二阱区，所述第一阱区具有第一导电类型，所述第二阱区具有与所述第一导电类型相反的第二导电类型；所述栅极结构从部分所述第一阱区的上方跨越到部分所述第二阱区的上方；所述第一阱区的顶部形成有第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区位于所述栅极结构的一侧，所述第一掺杂区具有所述第一导电类型，所述第二掺杂区具有所述第二导电类型；所述第二阱区的顶部形成有第三掺杂区和第四掺杂区，所述第三掺杂区和所述第四掺杂区位于所述栅极结构的另一侧，所述第三掺杂区具有所述第一导电类型，所述第四掺杂区具有所述第二导电类型；所述第一掺杂区和所述第二掺杂区电连接至第一电位端，所述栅极结构和所述第三掺杂区电连接至第二电位端。
可选的，所述第一阱区、所述第二阱区和所述第三掺杂区构成第一寄生三极管；所述第二掺杂区、所述第一阱区和所述第二阱区构成第二寄生三极管；所述第一寄生三极管和所述第二寄生三极管共用所述第一阱区和所述第二阱区，且共同用于静电放电。
可选的，所述第一阱区、所述第二阱区和所述第三掺杂区分别作为所述第一寄生三极管的集电极、基极和发射极；所述第二阱区、所述第一阱区和所述第二掺杂区分别作为所述第二寄生三极管的集电极、基极和发射极。
可选的，所述第一掺杂区和所述第二掺杂区沿着所述栅极结构下方的导电沟道的宽 度方向排布。
可选的，所述第一掺杂区的两端均形成有所述第二掺杂区。
可选的，所述第三掺杂区位于所述栅极结构和所述第四掺杂区之间，所述第三掺杂区和所述第四掺杂区沿所述栅极结构下方的导电沟槽的宽度方向伸长。
可选的，所述栅极结构与所述第一掺杂区之间的基底顶部、所述栅极结构与所述第二掺杂区之间的基底顶部、以及所述第一掺杂区和所述第二掺杂区之间的基底顶部均形成有隔离结构；和/或，所述第三掺杂区和所述第四掺杂区之间的基底顶部形成有隔离结构。
可选的，所述栅极结构的第一侧壁与所述隔离结构接触，所述栅极结构的第二侧壁与所述第三掺杂区接触。
可选的，所述第一导电类型为N型，所述第二导电类型为P型。
可选的，所述第一电位端为阳极端，所述第二电位端为阴极端。
本公开提供的静电放电保护器件包括基底和位于基底上的栅极结构，所述基底中形成有相连接的第一阱区和第二阱区，所述第一阱区具有第一导电类型，所述第二阱区具有与所述第一导电类型相反的第二导电类型；所述栅极结构从部分所述第一阱区的上方跨越到部分所述第二阱区的上方；所述第一阱区的顶部形成有第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区位于所述栅极结构的一侧，所述第一掺杂区具有所述第一导电类型，所述第二掺杂区具有所述第二导电类型；所述第二阱区的顶部形成有第三掺杂区和第四掺杂区，所述第三掺杂区和所述第四掺杂区位于所述栅极结构的另一侧，所述第三掺杂区具有所述第一导电类型，所述第四掺杂区具有所述第二导电类型。如此，第一阱区、第二阱区和第三掺杂区能够构成第一寄生三极管，第二掺杂区、第一阱区和第二阱区能够构成第二寄生三极管，第一寄生三极管和第二寄生三极管共用第一阱区和第二阱区从而相互连接，第一寄生三极管能够触发第二寄生三极管导通，进而形成静电泄放能力较强的SCR通路。
附图说明
图1为一种用于ESD保护的LDMOS的俯视图。
图2为图1所示的LDMOS的剖视图及其内部的等效三极管电路的示意图。
图3为用于ESD保护的LDMOS的电流-电压曲线图。
图4为本公开一实施例的静电放电保护器件的俯视图。
图5为图4所示的静电放电保护器件沿BB线所示的位置的剖视图及其内部的等效 三极管电路的示意图。
图6为图4所示的静电放电保护器件沿CC线所示的位置的剖视图及其内部的等效三极管电路的示意图。
图7为本公开一实施例的静电放电保护器件的电流-电压曲线图。
附图标记说明：
(图1至图2)101-N阱；102-P阱；103-栅极；104-第一N+区；
(图4至图6)200-基底；201-第一阱区；202-第二阱区；203-第一掺杂区；204-第二掺杂区；205-第三掺杂区；206-第四掺杂区；207-隔离结构；300-栅极结构。
具体实施方式
在集成电路中，通常阳极(Anode)和阴极(Cathode)之间会用到ESD保护结构，且ESD保护结构的类型通常和被保护电路的类型相同，例如高压应用时，用高压LDMOS(Laterally Diffused Metal Oxide Semiconductor，横向扩散金属氧化物半导体)去保护LDMOS电路。
图1为一种用于ESD保护的LDMOS的俯视图。图2为图1所示的LDMOS的剖视图及其内部的等效三极管电路的示意图。其中，图2为沿图1中AA线的剖视图，图1和图2所示的LDMOS为N型。
参考图1和图2所示，LDMOS的N阱101(N-well)、P阱102(P-well)以及第一N+区104之间构成寄生NPN管T1，其中，N阱101为T1的集电极，P阱102为T1的基极，第一N+区104为T1的发射极。当有正的ESD脉冲加到阳极时，N阱101和P阱102的反向PN结形成漏电流，同时ESD脉冲还能通过寄生电容的耦合效应使得栅极103电压瞬间抬升，从而在栅极103下方的基底表层形成反型层。因此，随着阳极端电压的升高，漏电流也逐渐变大。
图3为用于ESD保护的LDMOS的电流-电压曲线图。参考图1至图3所示，当漏电流大到一定值时，寄生NPN管T1的基极-发射极发生正偏，寄生NPN管T1导通形成从阳极到阴极的电流，对应图3的触发点(Vt1，It1)，从而泄放ESD电流，对被保护电路起到保护作用。寄生NPN管T1触发后，LDMOS会出现一个迅速的回滞现象(snapback)，电压回到保持电压Vh后，随着ESD脉冲的进一步升高，LDMOS继续放电，且两端电压随之升高，达到击穿电压Vt2后，LDMOS烧毁。
此外，LDMOS用于ESD保护，通常采用并联的多指结构，这样能加大总的器件宽度。但是，由于高压LDMOS的高压特性决定了寄生NPN管T1的触发电压Vt1较高， 而通常并联多指结构靠近中间部分的晶体管更容易导通，而一旦有某几根叉指晶体管导通就会立刻发生回滞现象，LDMOS的电压迅速降低，直到达到击穿电压Vt2时，其它还没开启的叉指晶体管都很难打开，从而使得该用于ESD保护的LDMOS的静电泄放能力较差，无法满足高压器件的ESD保护需求。
为了提升电路的静电泄放能力，满足高压器件的ESD保护需求，本公开提供一种静电放电保护器件。所述静电放电保护器件包括基底和位于所述基底上的栅极结构。所述基底中形成有相连接的第一阱区和第二阱区，所述第一阱区具有第一导电类型，所述第二阱区具有与所述第一导电类型相反的第二导电类型；所述栅极结构从部分所述第一阱区的上方跨越到部分所述第二阱区的上方。所述第一阱区的顶部形成有第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区位于所述栅极结构的一侧，所述第一掺杂区具有第一导电类型，所述第二掺杂区具有第二导电类型；所述第二阱区的顶部形成有第三掺杂区和第四掺杂区，所述第三掺杂区和所述第四掺杂区位于所述栅极结构的另一侧，所述第三掺杂区具有第一导电类型，所述第四掺杂区具有第二导电类型。所述第一掺杂区和所述第二掺杂区电连接至第一电位端，所述栅极结构和所述第三掺杂区电连接至第二电位端。
本公开的静电放电保护器件中，第一阱区、第二阱区和第三掺杂区能够构成第一寄生三极管，第二掺杂区、第一阱区和所第二阱区能够构成第二寄生三极管，第一寄生三极管和第二寄生三极管共用第一阱区和第二阱区从而相互连接，第一寄生三极管能够触发第二寄生三极管导通，进而形成静电泄放能力较强的SCR(Silicon Controlled Rectifier，中文称为硅可控整流器)通路，有利于提升电路的静电泄放能力，满足高压器件的静电放电保护需求。
以下结合附图和具体实施例对本公开提出的静电放电保护器件作进一步详细说明。根据下面说明，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
图4为本公开一实施例的静电放电保护器件的俯视图。图5为图4所示的静电放电保护器件沿BB线所示的位置的剖视图及其内部的等效三极管电路的示意图。图6为图4所示的静电放电保护器件沿CC线所示的位置的剖视图及其内部的等效三极管电路的示意图。
如图4至图6所示，所述静电放电保护器件包括基底200和位于所述基底200上的栅极结构300。
所述基底200中形成有相连接的第一阱区201和第二阱区202，例如在图5和图6 的水平方向上，第一阱区201的边界与第二阱区202的边界相接，所述第一阱区201具有第一导电类型，所述第二阱区202具有与所述第一导电类型相反的第二导电类型。
所述基底200可以是硅基底，但不限于此。所述基底200还可以是锗基底、硅锗基底、绝缘体上硅(Silicon On Insulator，SOI)或绝缘体上锗(Germanium On Insulator，GOI)等，基底200中还可以根据设计需求注入一定的掺杂粒子以改变电学参数。
所述栅极结构300从部分所述第一阱区201的上方跨越到部分所述第二阱区202的上方，即所述栅极结构300位于所述第一阱区201和第二阱区202的交接处，且栅极结构300覆盖部分第一阱区201和部分第二阱区202。所述栅极结构300可以包括位于基底200上方的栅氧化层(图中未示出)和位于栅氧化层上的栅极(图中未示出)。栅氧化层的材料可以包括氧化硅，栅极可以为多晶硅栅极，但不限于此。
如图4至图6所示，所述第一阱区201的顶部形成有第一掺杂区203和第二掺杂区204，所述第一掺杂区203和所述第二掺杂区204位于所述栅极结构300的一侧，所述第一掺杂区203具有第一导电类型，所述第二掺杂区204具有第二导电类型；所述第二阱区202的顶部形成有第三掺杂区205和第四掺杂区206，所述第三掺杂区205和所述第四掺杂区206位于所述栅极结构300的另一侧，所述第三掺杂区205具有第一导电类型，所述第四掺杂区206具有第二导电类型。所述第一掺杂区203和所述第二掺杂区204电连接至第一电位端，所述栅极结构300和所述第三掺杂区205电连接至第二电位端。
本实施例中，所述第一导电类型可以为N型，所述第二导电类型可以为P型，但不限于此。
作为示例，第一阱区201为N阱(N-well)，第二阱区202为P阱(P-well)，第一掺杂区203和第三掺杂区205为N+掺杂区，第二掺杂区204和第四掺杂区206为P+掺杂区。第一阱区201、第二阱区202、第一掺杂区203、第二掺杂区204、第三掺杂区204和第四掺杂区205均可以通过在所述基底200中注入掺杂物质形成。
所述第一电位端可以为阳极端(Anode)，所述第二电位端可以为阴极端(Cathode)，但不限于此。
如图5所示，所述第一阱区201、所述第二阱区202和所述第三掺杂区205构成第一寄生三极管T1，所述第一阱区201、所述第二阱区202和所述第三掺杂区205分别作为所述第一寄生三极管T1的集电极、基极和发射极。本公开的一个实施例中，第一寄生三极管T1为NPN管。
如图6所示，所述第二掺杂区204、所述第一阱区201和所述第二阱区202构成第二寄生三极管T2，所述第二阱区202、所述第一阱区201和所述第二掺杂区204分别作 为所述第二寄生三极管T2的集电极、基极和发射极。本公开的一个实施例中，第二寄生三极管T2为PNP管。
如图4至图6所示，第一寄生三极管T1和第二寄生三极管T2共用第一阱区201和第二阱区202，即第一寄生三极管T1的集电极和第二寄生三极管T2的基极共用，第一寄生三极管T1的基极和第二寄生三极管T2的集电极共用，在电路图中表现为，第一寄生三极管T1的集电极和第二寄生三极管T2的基极相连接，第一寄生三极管T1的基极和第二寄生三极管T2的集电极相连接。所述第一寄生三极管T1和第二寄生三极管T2共同用于静电放电。
图7为本公开一实施例的静电放电保护器件的电流-电压曲线图。参考图4至图7所示，当阳极端(Anode)有正的ESD脉冲时，第一阱区201和第二阱区202的反向PN结形成漏电流，同时ESD脉冲还能通过寄生电容的耦合效应使得栅极结构300的电压瞬间抬升，从而在栅极结构300下方的基底表层形成反型层。因此，随着阳极端电压的升高，漏电流也逐渐变大。当漏电流大到一定值时，第一寄生三极管T1的基极-发射极发生正偏，第一寄生三极管T1导通形成从阳极到阴极的电流，对应于图7的触发点(Vt1，It1)，从而泄放ESD电流，对被保护电路起到保护作用。
第一寄生三极管T1触发后，静电放电保护器件会出现一个迅速的回滞现象，电压回到保持电压Vh。随着ESD脉冲的进一步升高，第一寄生三极管T1继续放电，第一寄生三极管T1的集电极电流反馈到第二寄生三极管T2的基极，使得第二寄生三极管T2的基极-发射极正偏，从而第二寄生三极管T2导通，对应于图7的第二个触发点(Vt1＇，It1＇)，此时形成了PNPN的SCR通路，并发生二次回滞现象，静电放电保护结构的电压回到保持电压Vh＇。接着，随着ESD脉冲的增加，大部分ESD电流迅速通过SCR通路泄放出去，直至达到二次击穿点(Vt2，It2)。
需要说明的是，本公开的静电放电保护结构为一个二次触发的器件，其在传统的用于ESD的LDMOS器件的基础上嵌设了与第一寄生三极管T1连接的第二寄生三极管T2，以在静电放电保护结构中形成SCR通路。当ESD脉冲的增加时，首先触发第一寄生三极管T1泄放部分ESD电流，静电放电保护器件出现第一次回滞现象；当ESD脉冲继续增加时，第二寄生三极管T2被触发导通，形成SCR通路，并出现第二次回滞现象，当ESD脉冲进一步增加时，通过SCR通路辅助泄放ESD电流，直到达到静电放电保护器件的二次击穿点。
由于第一寄生三极管T1和第二寄生三极管T2连接形成SCR结构的单位面积ESD保护能力远高于LDMOS，因此，本公开的静电放电保护器件在传统的用于ESD的 LDMOS器件的基础上嵌设入第二寄生三极管，能够大幅度增加静电放电保护器件泄放ESD电流的能力。
如图4所示，栅极结构300可以沿X方向伸长，栅极结构300下方的导电沟道的宽度方向为X方向，所述第一掺杂区203和所述第二掺杂区204可以沿着所述栅极结构300下方的导电沟道的宽度方向排布。在Y方向上，所述第一掺杂区203和所述第二掺杂区204的宽度可以相同，且第一掺杂区203和第二掺杂区204的端部对齐，如此有助于减小静电放电保护器件的尺寸，但不限于此。
本实施例中，如图4所示，在X方向上，所述第一掺杂区203的两端可以均形成有所述第二掺杂区204，如此有利于提高静电放电保护器件的放电均匀性，但不限于此。在其它实施例中，在X方向上，可以仅在第一掺杂区203的一端设置第二掺杂区204。
如图4和图5所示，在Y方向上，所述第三掺杂区205可以位于所述栅极结构300和所述第四掺杂区206之间，所述第三掺杂区205和所述第四掺杂区206可以沿所述栅极结构300下方的导电沟道的宽度方向伸长。
如图4至图6所示，所述栅极结构300与所述第一掺杂区203之间的基底顶部、所述栅极结构300与所述第二掺杂区204之间的基底顶部、以及所述第一掺杂区203和所述第二掺杂区204之间的基底顶部均形成有隔离结构207。所述第三掺杂区205和所述第四掺杂区206之间的基底顶部也可以形成有隔离结构207。所述隔离结构207可以为场氧化物(Field Oxide，FOX)或使用硅的局部氧化(Local Oxidation of Silicon，LOCOS)工艺的浅沟槽隔离(Shallow Trench Isolation，STI)。
所述栅极结构300的第一侧壁与隔离结构207接触，所述栅极结构300的第二侧壁与所述第三掺杂区205接触，所述第一侧壁和所述第二侧壁位置相对。示例性的，如图4、图5和图6所示，栅极结构300的第一侧壁为左侧壁，第二侧壁为右侧壁，第一侧壁接触栅极结构300与第一掺杂区203之间的隔离结构207以及接触栅极结构300与第二掺杂区204之间的隔离结构207，第二侧壁与第三掺杂区205接触。
本实施例的静电放电保护器件包括基底200和位于所述基底200上的栅极结构300；所述基底200中形成有相连接的第一阱区201和第二阱区202，所述第一阱区201具有第一导电类型，所述第二阱区202具有与所述第一导电类型相反的第二导电类型；所述栅极结构300从部分所述第一阱区201的上方跨越到部分所述第二阱区202的上方；所述第一阱区201的顶部形成有第一掺杂区203和第二掺杂区204，所述第一掺杂区203和所述第二掺杂区204位于所述栅极结构300的一侧，所述第一掺杂区203具有第一导电类型，所述第二掺杂区204具有第二导电类型；所述第二阱区202的顶部形成有第三 掺杂区205和第四掺杂区206，所述第三掺杂区205和所述第四掺杂区206位于所述栅极结构300的另一侧，所述第三掺杂区205具有第一导电类型，所述第四掺杂区206具有第二导电类型。如此，第一阱区201、第二阱区202和第三掺杂区205能够构成第一寄生三极管T1，第二掺杂区204、第一阱区201和第二阱区202能够构成第二寄生三极管T2，第一寄生三极管T1和第二寄生三极管T2共用第一阱区201和第二阱区202从而相互连接，第一寄生三极管T1能够触发第二寄生三极管T2导通，进而形成静电泄放能力较强的SCR通路，有利于提升电路的静电泄放能力，满足高压器件的静电放电保护需求。
上述描述仅是对本公开较佳实施例的描述，并非对本公开权利范围的任何限定，任何本领域技术人员在不脱离本公开的精神和范围内，都可以利用上述揭示的方法和技术内容对本公开技术方案做出可能的变动和修改，因此，凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本公开技术方案的保护范围。

Claims (10)

  1. 一种静电放电保护器件，其特征在于，包括基底和位于所述基底上的栅极结构；
    所述基底中形成有相连接的第一阱区和第二阱区，所述第一阱区具有第一导电类型，所述第二阱区具有与所述第一导电类型相反的第二导电类型；所述栅极结构从部分所述第一阱区的上方跨越到部分所述第二阱区的上方；
    所述第一阱区的顶部形成有第一掺杂区和第二掺杂区，所述第一掺杂区和所述第二掺杂区位于所述栅极结构的一侧，所述第一掺杂区具有所述第一导电类型，所述第二掺杂区具有所述第二导电类型；所述第二阱区的顶部形成有第三掺杂区和第四掺杂区，所述第三掺杂区和所述第四掺杂区位于所述栅极结构的另一侧，所述第三掺杂区具有所述第一导电类型，所述第四掺杂区具有所述第二导电类型；
    所述第一掺杂区和所述第二掺杂区电连接至第一电位端，所述栅极结构和所述第三掺杂区电连接至第二电位端。
  2. 如权利要求1所述的静电放电保护器件，其特征在于，所述第一阱区、所述第二阱区和所述第三掺杂区构成第一寄生三极管；所述第二掺杂区、所述第一阱区和所述第二阱区构成第二寄生三极管；所述第一寄生三极管和所述第二寄生三极管共用所述第一阱区和所述第二阱区，且共同用于静电放电。
  3. 如权利要求2所述的静电放电保护器件，其特征在于，所述第一阱区、所述第二阱区和所述第三掺杂区分别作为所述第一寄生三极管的集电极、基极和发射极；所述第二阱区、所述第一阱区和所述第二掺杂区分别作为所述第二寄生三极管的集电极、基极和发射极。
  4. 如权利要求1所述的静电放电保护器件，其特征在于，所述第一掺杂区和所述第二掺杂区沿着所述栅极结构下方的导电沟道的宽度方向排布。
  5. 如权利要求4所述的静电放电保护器件，其特征在于，所述第一掺杂区的两端均形成有所述第二掺杂区。
  6. 如权利要求1所述的静电放电保护器件，其特征在于，所述第三掺杂区位于所述栅极结构和所述第四掺杂区之间，所述第三掺杂区和所述第四掺杂区沿所述栅极结构下方的导电沟槽的宽度方向伸长。
  7. 如权利要求1所述的静电放电保护器件，其特征在于，所述栅极结构与所述第一掺杂区之间的基底顶部、所述栅极结构与所述第二掺杂区之间的基底顶部、以及所述第一掺杂区和所述第二掺杂区之间的基底顶部均形成有隔离结构；和/或，所述第三掺杂区和所述第四掺杂区之间的基底顶部形成有隔离结构。
  8. 如权利要求7所述的静电放电保护器件，其特征在于，所述栅极结构的第一侧壁与所述隔离结构接触，所述栅极结构的第二侧壁与所述第三掺杂区接触。
  9. 如权利要求1至8任一项所述的静电放电保护器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型。
  10. 如权利要求1至8任一项所述的静电放电保护器件，其特征在于，所述第一电位端为阳极端，所述第二电位端为阴极端。
PCT/CN2023/125966 2022-10-31 2023-10-23 静电放电保护器件 Ceased WO2024093701A1 (zh)

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CN102832233A (zh) * 2012-08-30 2012-12-19 北京大学 Scr型ldmos esd器件
CN205319155U (zh) * 2015-12-08 2016-06-15 无锡中感微电子股份有限公司 一种静电保护电路及集成电路
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