WO2024093417A1 - 晶振启动控制电路及方法、晶振装置、soc芯片 - Google Patents

晶振启动控制电路及方法、晶振装置、soc芯片 Download PDF

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WO2024093417A1
WO2024093417A1 PCT/CN2023/111570 CN2023111570W WO2024093417A1 WO 2024093417 A1 WO2024093417 A1 WO 2024093417A1 CN 2023111570 W CN2023111570 W CN 2023111570W WO 2024093417 A1 WO2024093417 A1 WO 2024093417A1
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crystal oscillator
signal
voltage
output
logic circuit
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PCT/CN2023/111570
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English (en)
French (fr)
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郭术明
李有慧
彭莉
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无锡华润上华科技有限公司
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Publication of WO2024093417A1 publication Critical patent/WO2024093417A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

  • the present application relates to a crystal oscillator, and in particular to a crystal oscillator startup control circuit and a crystal oscillator startup control method, and also to a crystal oscillator device and a SOC chip.
  • Crystal oscillators are increasingly used in integrated circuits.
  • Crystal oscillators can provide a high-precision, stable clock signal to the chip, which is often an important input reference clock for key modules such as the phase-locked loop (PLL) in the SOC (System on Chip).
  • PLL phase-locked loop
  • SOC System on Chip
  • a crystal oscillator with extremely low power consumption is often required to provide a clock source.
  • the crystal oscillator voltage is often reduced. However, this may cause the crystal oscillator to start up for too long or even fail to start up. Therefore, it is necessary to comprehensively consider the power consumption and start-up issues to improve the structure of the crystal oscillator.
  • a crystal oscillator startup control circuit comprises: a logic circuit for outputting a first signal; a linear voltage regulator connected to the logic circuit and used to determine the voltage of a power signal output to a crystal oscillator according to the first signal, the power signal serving as the power supply of the crystal oscillator; wherein the logic circuit is also used to detect a clock signal output by the crystal oscillator, and if the logic circuit detects the clock signal output by the crystal oscillator within a preset time after outputting the first signal, the logic circuit changes the output first signal to reduce the voltage of the power signal output by the linear voltage regulator until the clock signal is not detected within the preset time, at which time the logic circuit changes the output first signal again to increase the voltage of the power signal output by the linear voltage regulator, and then provides the first power signal with a stable voltage to the crystal oscillator.
  • the above crystal oscillator startup control circuit can flexibly lower the LDO output voltage (ie, the voltage of the power supply signal) according to the oscillation condition of the crystal oscillator, thereby reducing the power consumption of the crystal oscillator as much as possible.
  • the logic circuit is configured to: If the logic circuit does not detect the clock signal, the logic circuit changes the first signal output so that the voltage of the power signal output by the linear regulator increases until the clock signal is detected within the preset time period. At this time, the first signal is kept stable so that the linear regulator provides a second power signal with a stable voltage to the crystal oscillator.
  • the logic circuit changes the first output signal again by returning the first signal to the state when the clock signal was detected last time, thereby returning the voltage of the power supply signal output by the linear regulator to the previous voltage.
  • the linear regulator has a power signal voltage level corresponding to the digital code of the first signal, and the voltage of the power signal output by the linear regulator is determined according to the digital code of the first signal.
  • the changing of the output first signal so as to reduce the voltage of the power signal output by the linear regulator is to reduce the power signal by one level.
  • the changing of the output first signal so as to increase the voltage of the power signal output by the linear regulator is to increase the power signal by one level.
  • it also includes a memory connected to the logic circuit, for storing the digital code corresponding to the first power signal and the digital code corresponding to the second power signal; when the logic circuit is powered on again, it outputs a first signal corresponding to the digital code stored in the memory to the linear regulator.
  • an oscillator connected to the logic circuit is further included to provide a clock signal to the logic circuit.
  • the present application accordingly provides a crystal oscillator device, including a crystal oscillator and a crystal oscillator startup control circuit as described in any of the aforementioned embodiments.
  • the present application accordingly provides a SOC chip, comprising the aforementioned crystal oscillator device.
  • the present application accordingly provides a crystal oscillator startup control method.
  • a crystal oscillator startup control method includes: step A, outputting a power signal to a crystal oscillator as the power supply of the crystal oscillator; step B1, after outputting the power signal, if a clock signal output by the crystal oscillator is detected within a preset time length, then reducing the voltage of the power signal before outputting it to the crystal oscillator; step B2, repeatedly executing step B1 until the clock signal is not detected within the preset time length, at which time the voltage of the current power signal is increased once and provided to the crystal oscillator as a first power signal with stable voltage.
  • the above crystal oscillator startup control method can flexibly lower the voltage of the power supply signal output to the crystal oscillator according to the oscillation status of the crystal oscillator, thereby reducing the power consumption of the crystal oscillator as much as possible.
  • the method further includes: step C1, after step A outputs the power signal, if the clock signal is not detected within a preset time period, the voltage of the power signal is increased before being output to the crystal oscillator; step C2, repeatedly executing step C1 until the clock signal is detected within the preset time period, at which time the current power signal is provided to the crystal oscillator as a second power signal with stable voltage.
  • the step B2 increases the voltage of the corresponding power signal once, which is to change the power signal back to the voltage corresponding to the last time the clock signal was detected.
  • the method further comprises: when power is turned on again, using the voltage-stable first power signal of step B2 or the voltage-stable second power signal of step C2 as the power signal of step A.
  • FIG1 is a circuit schematic diagram of a crystal oscillator startup control circuit in an embodiment of the present application.
  • FIG2 is a circuit diagram of a crystal oscillator device in one embodiment of the present application.
  • FIG3 is a flow chart of a crystal oscillator startup control method in one embodiment of the present application.
  • FIG4 is a flow chart of a crystal oscillator startup control method in another embodiment of the present application.
  • FIG. 5 is a schematic diagram of an exemplary low-power crystal oscillator circuit.
  • the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • FIG5 An exemplary low-power crystal oscillator circuit is shown in FIG5 , in which a linear regulator (LDO) is used to reduce a higher voltage VDDH to VDDL, which is provided to the crystal oscillator circuit as a power source.
  • LDO linear regulator
  • VDDL is significantly lower than VDDH, which can greatly reduce the power consumption of the crystal oscillator circuit.
  • VDDL is too low, it may also cause the crystal oscillator circuit to fail to oscillate or the oscillation start-up time to be too long, reducing the reliability of the crystal oscillator. Therefore, in order to ensure that the crystal oscillator can oscillate smoothly under all process conditions and temperature and voltage conditions, the VDDL output by the LDO can only be fixed at a higher voltage, which limits further reduction.
  • the potential of low crystal power consumption is not flexible enough. In order to tap the potential of low power consumption of crystal oscillators as much as possible without sacrificing the reliability of crystal oscillators, it is necessary to improve and expand the design of crystal oscillators.
  • the EN signal in Figure 5 is the enable signal of the LDO and crystal oscillator circuit
  • VDDH is the original high-voltage power supply signal input
  • VSSH is the ground potential
  • VDDL is the low-voltage power supply signal output by the LDO
  • XIN and XOUT are interfaces for the crystal oscillator circuit to connect the quartz crystal and the capacitive load CL
  • the XC signal is the clock signal output by the crystal oscillator circuit.
  • FIG. 1 is a circuit schematic diagram of a crystal oscillator startup control circuit in an embodiment of the present application, wherein the crystal oscillator startup control circuit 120 includes a logic circuit 122 and a linear regulator (LDO) 124.
  • the linear regulator 124 is connected to the logic circuit 122.
  • the linear regulator 124 outputs a power supply signal VDDL to the crystal oscillator 110 as the power supply of the crystal oscillator 110.
  • the logic circuit 122 outputs a first signal to the linear regulator 124, and the linear regulator 124 determines the voltage of the power supply signal VDDL output to the crystal oscillator 110 according to the first signal output by the logic circuit 122.
  • the logic circuit 122 determines whether the crystal oscillator 110 starts smoothly by detecting the clock signal XC output by the crystal oscillator 110. If the current VDDL voltage can enable the crystal oscillator 110 to start smoothly, then the logic circuit 122 will reduce the voltage value of the power supply signal VDDL to further reduce the power consumption of the crystal oscillator 110.
  • the logic circuit 122 detects that the crystal oscillator 110 outputs a normal clock signal XC within a preset time after outputting the first signal, the logic circuit 122 changes the output first signal to reduce the voltage of the power signal VDDL output by the linear regulator 124, and repeatedly attempts to further reduce the voltage - observe the process of crystal oscillator startup until the clock signal XC is not detected within the preset time. At this time, the logic circuit 122 changes the output first signal again to increase the voltage of the power signal VDDL, and then provides it to the crystal oscillator 110 as a power signal with a stable voltage.
  • changing the first signal again means changing the first signal back to the state when the clock signal XC was detected last time, so that the voltage of the power signal VDDL output by the linear regulator 124 is changed back to the previous voltage.
  • the crystal oscillator startup control circuit 120 can flexibly lower the LDO output voltage (ie, the voltage of the power supply signal VDDL) according to the oscillation status of the crystal oscillator, thereby reducing the power consumption of the crystal oscillator as much as possible.
  • the logic circuit 122 if the logic circuit 122 does not detect the clock signal XC within a preset time after outputting the first signal, the logic circuit 122 changes the output first signal to increase the voltage of the power signal VDDL output by the linear regulator 124, and repeatedly attempts to further increase the voltage - observe the crystal oscillator startup process until the clock signal XC is detected within the preset time. At this time, the first signal is kept stable so that the LDO provides a stable power signal to the crystal oscillator 110.
  • the above-mentioned crystal oscillator startup control circuit 120 can flexibly increase the LDO output voltage to ensure that the crystal oscillator can start smoothly, thereby improving the flexibility and application range of the crystal oscillator.
  • the LDO output voltage can be increased.
  • the logic circuit 122 can timely increase the output voltage of the LDO to allow the crystal oscillator to maintain stable operation, thereby improving the reliability of the crystal oscillator circuit.
  • the linear regulator 124 has a power signal voltage level corresponding to the digital code of the first signal output by the logic circuit 122 , so the voltage of the power signal VDDL output by the linear regulator 124 is determined according to the digital code of the first signal.
  • the logic circuit 122 detects the clock signal XC within a preset time period after outputting the first signal, the digital code of the output first signal is changed to reduce the voltage of the power signal VDDL by one level.
  • the logic circuit 122 if the logic circuit 122 does not detect the clock signal XC within a preset time after outputting the first signal, the digital code of the output first signal is changed to increase the voltage of the power signal VDDL by one level.
  • the crystal oscillator startup control circuit 120 further includes a memory 126 connected to the logic circuit 122, which is used to store the digital code corresponding to the power supply signal VDDL after stabilization. In this way, when the logic circuit 122 is subsequently powered on again (i.e., the crystal oscillator startup control circuit 120 is restarted), the logic circuit 122 reads the stored digital code from the memory 126 and sends the corresponding first signal to the linear regulator 124.
  • the digital code stored in the memory 126 can also be updated in real time, for example, the logic circuit 122 updates the code stored in the memory 126 each time it sends the first signal to the linear regulator 124, or the logic circuit 122 updates the stored digital code in the memory 126 each time it detects the clock signal XC within the preset time length.
  • the crystal oscillator start-up control circuit 120 further includes an oscillator (OSC) 128 connected to the logic circuit 122 for providing a clock signal to the logic circuit 122.
  • the oscillator 128 is a low-precision oscillator, so a crystal oscillator is also required to provide a high-precision clock signal XC for the system.
  • the present application provides a crystal oscillator device, including a crystal oscillator, and also includes the crystal oscillator startup control circuit described in any of the above embodiments.
  • Figure 2 is a circuit schematic diagram of the crystal oscillator device in an embodiment of the present application, which adds a logic circuit for adjusting the crystal oscillator startup time and power consumption, a low-precision oscillator OSC and a memory relative to the circuit shown in Figure 5.
  • the basic principle is to divide the output voltage VDDL of the LDO into multiple gears, which are controlled by D0 ⁇ Dn output by the logic circuit.
  • the logic circuit will adjust the digital code D0 ⁇ Dn to reduce the voltage value of VDDL, so as to further reduce the power consumption of the crystal oscillator; when the VDDL voltage is too low to make the crystal oscillator start smoothly, the logic circuit raises the voltage of VDDL by adjusting the code, so that the crystal oscillator can start smoothly, ensuring the reliability of the circuit.
  • the EN signal is the enable signal of the logic circuit
  • the ENI signal is the enable signal of the LDO and the crystal oscillator circuit
  • VDDH is the input original high-voltage power supply signal
  • VSSH is the ground potential
  • XIN and XOUT are the crystal oscillator circuit connected to the quartz crystal
  • the XC signal is the interface between the crystal body and the capacitive load CL.
  • the XC signal is the clock signal output by the crystal oscillator circuit.
  • VDDL0 to VDDL15 gradually increase. As the code value gradually increases (from 0000 to 1111), the corresponding voltages of VDDL0 to VDDL15 also increase from low to high.
  • the logic circuit After the chip is powered on for the first time, when the logic circuit receives the EN signal, the logic circuit sends the ENI signal to start the LDO and crystal oscillator circuits. At this time, the logic circuit will output a set of default D0 ⁇ D3 initial codes 1000 to the LDO. Assuming that the voltage output by the LDO is VDDL8 at this time, referring to Table 1, this voltage is in the middle of the voltage range of VDDL0 ⁇ VDDL15.
  • the logic circuit will reduce the output code from 1000 to 0111, so that the output voltage of the LDO is reduced from VDDL8 to VDDL7, and then resend the ENI signal to restart the crystal oscillator. If the crystal oscillator can still start in time at this time, the logic circuit will continue to reduce the code and the VDDL voltage output by the LDO in turn to repeatedly try to start the crystal oscillator until the crystal oscillator cannot start within the expected time.
  • the logic circuit will increase the code D0 ⁇ D3 by one bit as the current determined value, and write the code into the memory as the current default value.
  • the default value is directly retrieved from the memory to run. For example, when the code drops to 0100, the logic circuit detects that the crystal oscillator cannot start normally, and automatically increases the code to 0101 and writes 0101 to the memory. Similarly, if the chip If the initial code 1000 corresponding to VDDL8 cannot start the crystal oscillator during the first operation, the logic circuit will automatically increase the code gradually to increase the voltage of VDDL until the crystal oscillator can start normally, and write the current code into the memory.
  • Low-precision OSC is used to provide a low-precision clock signal for the logic circuit.
  • the present application accordingly provides a SOC (System on Chip) chip, including the crystal oscillator device described in any of the aforementioned embodiments.
  • SOC System on Chip
  • a typical SOC chip it originally contains an original memory and an original low-precision OSC, as well as an original large-scale logic circuit, so the added logic circuit, low-precision OSC and memory in the crystal oscillator device of FIG2 can be supplemented and designed on the basis of the original large-scale logic circuit, original low-precision OSC and original memory of the SOC chip, without adding additional functional modules to the SOC chip, and only a few gate-level circuits need to be added to the SOC chip without adding additional functional modules, which will not increase the complexity of the SOC chip.
  • FIG3 is a flow chart of a crystal oscillator startup control method in an embodiment of the present application, comprising the following steps:
  • a power supply signal with a voltage value of a default value may be output to the crystal oscillator.
  • the voltage of the power signal output to the crystal oscillator is reduced.
  • step S330 determining whether a clock signal is detected within a preset time period, if so, returning to step S320, otherwise executing step S340.
  • the clock signal output by the crystal oscillator is detected within the preset time, it means that the voltage of the current power signal can still enable the crystal oscillator to oscillate smoothly, and you can try to further reduce the voltage.
  • the power supply signal is adjusted to the voltage when the clock signal was detected last time.
  • the above crystal oscillator startup control method can flexibly lower the voltage of the power supply signal output to the crystal oscillator according to the oscillation status of the crystal oscillator, thereby reducing the power consumption of the crystal oscillator as much as possible.
  • FIG4 is a flow chart of a crystal oscillator startup control method in another embodiment of the present application, comprising the following steps:
  • a power supply signal with a voltage value of a default value may be output to the crystal oscillator.
  • step S422 determine whether a clock signal is detected within a preset time period, if so, execute step S424, otherwise execute step S432.
  • Whether the crystal oscillator starts oscillating successfully is determined based on whether the clock signal output by the crystal oscillator is detected within a preset time period.
  • the voltage of the power signal output to the crystal oscillator is reduced.
  • step S426 determine whether a clock signal is detected within a preset time period, if so, return to step S424, otherwise execute step S428.
  • the clock signal output by the crystal oscillator is detected within the preset time, it means that the voltage of the current power signal can still enable the crystal oscillator to oscillate smoothly, and you can try to further reduce the voltage.
  • the power supply signal is adjusted to the voltage when the clock signal was detected last time.
  • step S422 if the clock signal output by the crystal oscillator is not detected within the preset time period, the voltage of the power signal output to the crystal oscillator is increased.
  • step S434 determine whether a clock signal is detected within a preset time period, if so, execute step S436, otherwise return to step S432.
  • the method further includes: when the system is powered on again (restarted), the voltage-stable power signal of step S428 or step S436 is used as the power signal of step S410, that is, the voltage value of the stable power signal is used as the default voltage value of the power signal after the restart.
  • steps in the flowchart of the present application are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in different times. The step may be executed in rotation or alternation with other steps or at least part of the steps or phases in other steps.

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Abstract

一种晶振启动控制电路（120）及方法、晶振装置、SOC芯片，该电路（120）包括：逻辑电路（122）；线性稳压器（124），根据逻辑电路（122）输出的第一信号确定输出给晶体振荡器（110）的电源信号的电压，电源信号作为晶体振荡器（110）的电源；逻辑电路（122）还用于检测晶体振荡器（110）输出的时钟信号，若在输出第一信号后的预设时长内逻辑电路（122）检测到晶体振荡器（110）输出的时钟信号，则逻辑电路（122）改变输出的第一信号，以使线性稳压器（124）输出的电源信号的电压减小，直到在预设时长内未检测到时钟信号，此时逻辑电路（122）再改变一次第一信号从而将电源信号的电压增大后，作为稳定的电源信号提供给晶体振荡器（110）。可以根据晶振的起振情况灵活调低LDO输出电压，尽可能地降低晶振的功耗。

Description

晶振启动控制电路及方法、晶振装置、SOC芯片 技术领域
本申请涉及晶体振荡器，特别是涉及一种晶振启动控制电路，以及一种晶振启动控制方法，还涉及一种晶振装置，及一种SOC芯片。
背景技术
随着技术的进步，晶振在集成电路中的应用越来越广泛。晶振能够给芯片提供一个高精度、稳定的时钟信号，这个时钟信号往往是SOC(System on Chip，片上系统)中锁相环(PLL)等关键模块的重要输入参考时钟。当SOC工作在低功耗模式下时，往往需要一个功耗极低的晶振来提供时钟源。而在成熟工艺上设计晶振时为了降低晶振的功耗，往往会采用降低晶振电压的方式来做，但这样一来又有可能导致晶振起振时间过长甚至无法起振，故需要综合考虑功耗和起振问题来对晶振的结构进行改进。
发明内容
基于此，有必要提供一种能够兼顾功耗和晶振起振的可靠性的晶振启动控制电路。
一种晶振启动控制电路，包括：逻辑电路，用于输出第一信号；线性稳压器，与所述逻辑电路连接，用于根据所述第一信号确定输出给晶体振荡器的电源信号的电压，所述电源信号作为晶体振荡器的电源；其中，所述逻辑电路还用于检测所述晶体振荡器输出的时钟信号，若在输出所述第一信号后的预设时长内所述逻辑电路检测到所述晶体振荡器输出的时钟信号，则所述逻辑电路改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压减小，直到在所述预设时长内未检测到所述时钟信号，此时所述逻辑电路再改变一次输出的所述第一信号从而将所述线性稳压器输出的电源信号的电压增大后，作为电压稳定的第一电源信号提供给所述晶体振荡器。
上述晶振启动控制电路，可以根据晶振的起振情况灵活调低LDO输出电压(即电源信号的电压)，尽可能地降低晶振的功耗。
在其中一个实施例中，所述逻辑电路被配置为若在输出所述第一信号后的预设时长内所 述逻辑电路未检测到所述时钟信号，则所述逻辑电路改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压增大，直到在所述预设时长内检测到所述时钟信号，此时保持所述第一信号稳定从而使所述线性稳压器向所述晶体振荡器提供电压稳定的第二电源信号。
在其中一个实施例中，所述逻辑电路再改变一次输出的所述第一信号，是将所述第一信号变回前一次检测到所述时钟信号时的状态，从而使所述线性稳压器输出的电源信号的电压变回前一次的电压。
在其中一个实施例中，所述线性稳压器具有与所述第一信号的数字编码对应的电源信号电压档位，所述线性稳压器输出的电源信号的电压根据所述第一信号的数字编码确定。
在其中一个实施例中，所述改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压减小，是使所述电源信号减小一档。
在其中一个实施例中，所述改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压增大，是使所述电源信号增大一档。
在其中一个实施例中，还包括与所述逻辑电路连接的存储器，用于存储与所述第一电源信号对应的所述数字编码和与所述第二电源信号对应的所述数字编码；所述逻辑电路重新上电时向所述线性稳压器输出与所述存储器存储的数字编码对应的第一信号。
在其中一个实施例中，还包括与所述逻辑电路连接的振荡器，用于向所述逻辑电路提供时钟信号。
本申请相应提供一种晶振装置，包括晶体振荡器，还包括如前述任一实施例所述的晶振启动控制电路。
本申请相应提供一种SOC芯片，包括前述晶振装置。
本申请相应提供一种晶振启动控制方法。
一种晶振启动控制方法，包括：步骤A，输出电源信号给晶体振荡器，作为晶体振荡器的电源；步骤B1，输出所述电源信号后，若在预设时长内检测到所述晶体振荡器输出的时钟信号，则将所述电源信号的电压减小后再输出给所述晶体振荡器；步骤B2，反复执行所述步骤B1，直到在所述预设时长内未检测到所述时钟信号，此时将当前的电源信号的电压增大一次后作为电压稳定的第一电源信号提供给所述晶体振荡器。
上述晶振启动控制方法，可以根据晶振的起振情况灵活调低输出给晶振的电源信号的电压，尽可能地降低晶振的功耗。
在其中一个实施例中，所述方法还包括：步骤C1，所述步骤A输出所述电源信号后，若在预设时长内未检测到所述时钟信号，则将所述电源信号的电压增大后再输出给所述晶体振荡器；步骤C2，反复执行所述步骤C1，直到在所述预设时长内检测到所述时钟信号，此时将当前的电源信号作为电压稳定的第二电源信号提供给所述晶体振荡器。
在其中一个实施例中，所述步骤B2将对应的电源信号的电压增大一次，是将所述电源信号变回前一次检测到所述时钟信号时对应的电压。
在其中一个实施例中，所述方法还包括：在重新上电时将所述步骤B2的电压稳定的第一电源信号或所述步骤C2的电压稳定的第二电源信号作为所述步骤A的电源信号。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例中晶振启动控制电路的电路原理图；
图2是本申请一实施例中晶振装置的电路原理图；
图3是本申请一实施例中晶振启动控制方法的流程图；
图4是本申请另一实施例中晶振启动控制方法的流程图；
图5是一种示例性的低功耗晶振电路的电路原理图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层 时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
一种示例性的低功耗晶振电路如图5所示，通过一个线性稳压器(LDO)将较高的电压VDDH降低到VDDL，提供给晶振电路做电源。一般来说VDDL显著低于VDDH，这样就能大幅度地降低晶振电路的功耗。但是如果VDDL过低，也有可能导致晶振电路不起振或者起振时间过长，降低了晶振的可靠性。因此为了保证晶振在所有的工艺条件和温度电压条件下都能顺利起振，只能将LDO输出的VDDL固定在一个较高的电压上，这就限制了进一步降 低晶振功耗的潜力，使用起来不够灵活。为了尽可能挖掘晶振低功耗方面的潜力，同时又要不牺牲晶振的可靠性，则需要对晶振的设计进行改进和拓展。
其中，图5的EN信号是LDO和晶振电路的使能信号，VDDH是输入的原始高压电源信号，VSSH为地电位，VDDL为LDO输出的低压电源信号，XIN和XOUT是晶振电路连接石英晶体和电容负载CL的接口，XC信号是晶振电路输出的时钟信号。
本申请提供一种能够自适应调节功耗的晶振启动控制电路。图1是本申请一实施例中晶振启动控制电路的电路原理图，晶振启动控制电路120包括逻辑电路122和线性稳压器(LDO)124。线性稳压器124与逻辑电路122相连接。线性稳压器124向晶体振荡器110输出电源信号VDDL，作为晶体振荡器110的电源。逻辑电路122向线性稳压器124输出第一信号，线性稳压器124根据逻辑电路122输出的第一信号确定输出给晶体振荡器110的电源信号VDDL的电压大小。其中，逻辑电路122通过检测晶体振荡器110输出的时钟信号XC，来判断晶体振荡器110是否顺利起振。如果当前的VDDL电压能够使得晶体振荡器110顺利起振，那么逻辑电路122就会降低电源信号VDDL的电压值，以便进一步降低晶体振荡器110的功耗。
具体地，若逻辑电路122在输出第一信号后的预设时长内检测到晶体振荡器110输出正常的时钟信号XC，则逻辑电路122改变输出的第一信号，以使线性稳压器124输出的电源信号VDDL的电压减小，反复尝试进一步减小电压——观察晶振启动情况的过程，直到在预设时长内未检测到时钟信号XC。此时逻辑电路122再改变一次输出的第一信号从而将电源信号VDDL的电压增大后，作为电压稳定的电源信号提供给晶体振荡器110。在本申请的一个实施例中，再改变一次第一信号，是将第一信号变回前一次检测到时钟信号XC时的状态，从而使线性稳压器124输出的电源信号VDDL的电压变回前一次的电压。
上述晶振启动控制电路120，可以根据晶振的起振情况灵活调低LDO输出电压(即电源信号VDDL的电压)，尽可能地降低晶振的功耗。
在本申请的一个实施例中，若逻辑电路122在输出第一信号后的预设时长内未检测到时钟信号XC，则逻辑电路122改变输出的第一信号，以使线性稳压器124输出的电源信号VDDL的电压增大，反复尝试进一步增大电压——观察晶振启动情况的过程，直到在预设时长内检测到时钟信号XC。此时保持第一信号稳定从而使LDO向晶体振荡器110提供稳定的电源信号。上述晶振启动控制电路120在晶振启动时间过长或者无法起振时，可以灵活调高LDO输出电压，保证晶振能够顺利起振，提高了晶振使用的灵活性和应用范围。当晶振在工作中碰 到工作环境发生大幅度变化(例如温度发生大幅度变化)导致晶振工作异常时，逻辑电路122能够及时调高LDO的输出电压来让晶振能够保持稳定工作，从而提高了晶振电路的可靠性。
在本申请的一个实施例中，线性稳压器124具有与逻辑电路122输出的第一信号的数字编码对应的电源信号电压档位，因此线性稳压器124输出的电源信号VDDL的电压根据第一信号的数字编码来确定。
在本申请的一个实施例中，逻辑电路122若在输出第一信号后的预设时长内检测到时钟信号XC，则改变输出的第一信号的数字编码，使电源信号VDDL的电压减小一档。
在本申请的一个实施例中，逻辑电路122若在输出第一信号后的预设时长内未检测到时钟信号XC，则改变输出的第一信号的数字编码，使电源信号VDDL的电压增大一档。
在图1所示的实施例中，晶振启动控制电路120还包括与逻辑电路122连接的存储器126，用于存储与电源信号VDDL稳定后对应的数字编码。这样在后续逻辑电路122重新上电(即晶振启动控制电路120重新启动)时，逻辑电路122从存储器126中读取存储的数字编码，并发送对应的第一信号给线性稳压器124。在本申请的一个实施例中，存储器126存储的该数字编码也可以实时更新，例如逻辑电路122每次向线性稳压器124发送第一信号时相应更新存储器126存储的编码，或者逻辑电路122每次在所述预设时长内检测到时钟信号XC后使存储器126更新存储的数字编码。
在图1所示的实施例中，晶振启动控制电路120还包括与逻辑电路122连接的振荡器(OSC)128，用于向逻辑电路122提供时钟信号。振荡器128是一个低精度的振荡器，因此还需要晶振为系统提供一个高精度的时钟信号XC。
本申请相应提供一种晶振装置，包括晶体振荡器，还包括前述任一实施例所述的晶振启动控制电路。图2是本申请一实施例中晶振装置的电路原理图，其相对于图5所示的电路增加了一个用来调节晶振启动时间和功耗的逻辑电路，一个低精度的振荡器OSC及一个存储器。其基本原理是将LDO的输出电压VDDL分成多档，由逻辑电路输出的D0～Dn来控制，如果当前的VDDL电压能够使得晶振顺利起振，那么逻辑电路就会通过调整数字编码D0～Dn来降低VDDL的电压值，以便进一步降低晶振的功耗；当VDDL电压过低而不能够使得晶振顺利起振时，逻辑电路通过调整编码来抬高VDDL的电压，使晶振能够顺利起振，保证电路的可靠性。图2中EN信号是逻辑电路的使能信号，ENI信号是LDO和晶振电路的使能信号，VDDH是输入的原始高压电源信号，VSSH为地电位，XIN和XOUT是晶振电路连接石英晶 体和电容负载CL的接口，XC信号是晶振电路输出的时钟信号。
下面通过一个实施例来详细描述图2中电路结构的具体工作原理和流程。假设n＝3，也即逻辑电路的输出为4位编码D0～D3,4位编码可以将LDO输出的电压分成16档，具体对应关系参见表1。
表1
其中VDDL0～VDDL15的电压值逐渐递增。随着编码数值的逐渐升高(从0000到1111)，对应的VDDL0～VDDL15的电压也是由低到高。
在芯片第一次上电后，当逻辑电路接收到EN信号，则逻辑电路发送出ENI信号让LDO和晶振电路开始启动，此时逻辑电路会输出一组默认的D0～D3初始编码1000到LDO中。假设此时LDO输出的电压为VDDL8，参照表1，这个电压位于VDDL0～VDDL15这个电压范围的中间。此时如果VDDL8的电压足够晶振及时起振，也即逻辑电路在预计启动时间内能够检测到时钟信号XC，则逻辑电路此时会将输出编码从1000降为0111，使LDO的输出电压从VDDL8降为VDDL7，然后重新发送ENI信号让晶振再次重启。如果此时晶振依然能够及时启动则逻辑电路会继续依次调降编码和LDO输出的VDDL电压来反复尝试晶振的启动情况，直到晶振无法在预计的时间内启动为止，这时逻辑电路会将编码D0～D3调升一位作为当前的确定值，并将该编码写入存储器作为当前的默认值。当后续EN信号进行重启的时候，就直接从存储器中调取该默认值来运行。例如当编码降到0100时逻辑电路检测到晶振不能正常启动了，则自动调高一位编码为0101，并将0101写入存储器。同理，如果当芯片 第一次工作时发现初始的编码1000对应的VDDL8无法让晶振起振的话，逻辑电路就自动逐渐调高编码来提高VDDL的电压，直到晶振能够正常起振为止，并将当前编码写入存储器。低精度OSC用来提供一个精度较低的时钟信号给逻辑电路使用。
本申请相应提供一种SOC(System on Chip，片上系统)芯片，包括前述任一实施例所述的晶振装置。对于一个典型的SOC芯片而言，里面本来就包含了原始存储器和原始低精度的OSC，还有一个原始大规模的逻辑电路，所以图2晶振装置中的添加的逻辑电路、低精度的OSC及存储器都可以在SOC芯片的原始大规模的逻辑电路、原始低精度的OSC、原始存储器基础上补充设计，无需再在SOC芯片中增加额外的功能模块，只需要在SOC芯片中增加很少的门级电路而不需要增加额外的功能模块就能实现，不会增加SOC芯片的复杂度。
本申请相应提供一种晶振启动控制方法。图3是本申请一实施例中晶振启动控制方法的流程图，包括下列步骤：
S310，输出电源信号给晶体振荡器，作为晶体振荡器的电源。
可以先向晶体振荡器输出一个电压值为默认值的电源信号。
S320，若在预设时长内检测到时钟信号，则将电源信号的电压减小。
若在预设时长内检测到晶体振荡器输出的时钟信号，则将输出给晶体振荡器的电源信号的电压减小。
S330，判断预设时长内是否检测到时钟信号，若是，则返回步骤S320，否则执行步骤S340。
若在预设时长内检测到晶体振荡器输出的时钟信号，则说明当前的电源信号的电压仍然可以使晶体振荡器顺利起振，可以尝试继续降低电压。
S340，将电源信号的电压增大一次后作为电压稳定的电源信号提供给晶体振荡器。
在本申请的一个实施例中，是将电源信号调整为前一次检测到时钟信号时的电压。
上述晶振启动控制方法，可以根据晶振的起振情况灵活调低输出给晶振的电源信号的电压，尽可能地降低晶振的功耗。
图4是本申请另一实施例中晶振启动控制方法的流程图，包括下列步骤：
S410，输出电源信号给晶体振荡器，作为晶体振荡器的电源。
可以先向晶体振荡器输出一个电压值为默认值的电源信号。
S422，判断预设时长内是否检测到时钟信号，若是，则执行步骤S424，否则执行步骤 S432。
根据在预设时长内是否检测到晶体振荡器输出的时钟信号，来判断晶体振荡器是否顺利起振。
S424，将电源信号的电压减小。
若在预设时长内检测到晶体振荡器输出的时钟信号，则将输出给晶体振荡器的电源信号的电压减小。
S426，判断预设时长内是否检测到时钟信号，若是，则返回步骤S424，否则执行步骤S428。
若在预设时长内检测到晶体振荡器输出的时钟信号，则说明当前的电源信号的电压仍然可以使晶体振荡器顺利起振，可以尝试继续降低电压。
S428，将电源信号的电压增大一次后作为电压稳定的电源信号提供给晶体振荡器。
在本申请的一个实施例中，是将电源信号调整为前一次检测到时钟信号时的电压。
S432，将电源信号的电压增大。
步骤S422中若在预设时长内未检测到晶体振荡器输出的时钟信号，则将输出给晶体振荡器的电源信号的电压增大。
S434，判断预设时长内是否检测到时钟信号，若是，则执行步骤S436，否则返回步骤S432。
若在预设时长内仍未检测到晶体振荡器输出的时钟信号，则说明当前的电源信号的电压过低，需要继续增大电源信号的电压。
S436，将此时的电源信号作为电压稳定的电源信号提供给晶体振荡器。
在本申请的一个实施例中，还包括：在系统重新上电(重启)时将步骤S428或步骤S436的电压稳定的电源信号作为步骤S410的电源信号。即将稳定的电源信号的电压值作为重启后的电源信号的电压默认值。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而 是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种晶振启动控制电路，其特征在于，包括：
    逻辑电路，用于输出第一信号；
    线性稳压器，与所述逻辑电路连接，用于根据所述第一信号确定输出给晶体振荡器的电源信号的电压，所述电源信号作为晶体振荡器的电源；
    其中，所述逻辑电路还用于检测所述晶体振荡器输出的时钟信号，若在输出所述第一信号后的预设时长内所述逻辑电路检测到所述晶体振荡器输出的时钟信号，则所述逻辑电路改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压减小，直到在所述预设时长内未检测到所述时钟信号，此时所述逻辑电路再改变一次输出的所述第一信号从而将所述线性稳压器输出的电源信号的电压增大后，作为电压稳定的第一电源信号提供给所述晶体振荡器。
  2. 根据权利要求1所述的晶振启动控制电路，其特征在于，所述逻辑电路被配置为若在输出所述第一信号后的预设时长内所述逻辑电路未检测到所述时钟信号，则所述逻辑电路改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压增大，直到在所述预设时长内检测到所述时钟信号，此时保持所述第一信号稳定从而使所述线性稳压器向所述晶体振荡器提供电压稳定的第二电源信号。
  3. 根据权利要求1或2所述的晶振启动控制电路，其特征在于，所述逻辑电路再改变一次输出的所述第一信号，是将所述第一信号变回前一次检测到所述时钟信号时的状态，从而使所述线性稳压器输出的电源信号的电压变回前一次的电压。
  4. 根据权利要求2所述的晶振启动控制电路，其特征在于，所述线性稳压器具有与所述第一信号的数字编码对应的电源信号电压档位，所述线性稳压器输出的电源信号的电压根据所述第一信号的数字编码确定；
    所述改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压减小，是使所述电源信号减小一档；
    所述改变输出的所述第一信号，以使所述线性稳压器输出的电源信号的电压增大，是使所述电源信号增大一档。
  5. 根据权利要求4所述的晶振启动控制电路，其特征在于，还包括与所述逻辑电路连接的存储器，用于存储与所述第一电源信号对应的所述数字编码和与所述第二电源信号对应的所述数字编码；所述逻辑电路被配置为在重新上电时向所述线性稳压器输出与所述存 储器存储的数字编码对应的第一信号。
  6. 根据权利要求5所述的晶振启动控制电路，其特征在于，所述存储器中存储的所述数字编码实时更新。
  7. 根据权利要求6所述的晶振启动控制电路，其特征在于，所述存储器被配置为在所述逻辑电路每次向所述线性稳压器输出所述第一信号时更新所述存储器中存储的所述数字编码。
  8. 根据权利要求6所述的晶振启动控制电路，其特征在于，所述存储器被配置为在所述逻辑电路每次在所述预设时长内检测到所述时钟信号后更新所述存储器中存储的所述数字编码。
  9. 根据权利要求1或2所述的晶振启动控制电路，其特征在于，还包括与所述逻辑电路连接的振荡器，用于向所述逻辑电路提供时钟信号。
  10. 一种晶振装置，包括晶体振荡器，其特征在于，还包括如权利要求1-9中任一项所述的晶振启动控制电路。
  11. 一种SOC芯片，其特征在于，包括如权利要求10所述的晶振装置。
  12. 一种晶振启动控制方法，包括：
    步骤A，输出电源信号给晶体振荡器，作为晶体振荡器的电源；
    步骤B1，输出所述电源信号后，若在预设时长内检测到所述晶体振荡器输出的时钟信号，则将所述电源信号的电压减小后再输出给所述晶体振荡器；
    步骤B2，反复执行所述步骤B1，直到在所述预设时长内未检测到所述时钟信号，此时将当前的电源信号的电压增大一次后作为电压稳定的第一电源信号提供给所述晶体振荡器。
  13. 根据权利要求12所述的晶振启动控制方法，其特征在于，所述将当前的电源信号的电压增大一次，是将所述电源信号的电压变回前一次检测到所述时钟信号时的电压。
  14. 根据权利要求12所述的晶振启动控制方法，其特征在于，还包括：
    步骤C1，所述步骤A输出所述电源信号后，若在预设时长内未检测到所述时钟信号，则将所述电源信号的电压增大后再输出给所述晶体振荡器；
    步骤C2，反复执行所述步骤C1，直到在所述预设时长内检测到所述时钟信号，此时将当前的电源信号作为电压稳定的第二电源信号提供给所述晶体振荡器。
  15. 根据权利要求14所述的晶振启动控制方法，其特征在于，还包括：在系统重新上电时将 步骤B2的电压稳定的第一电源信号或步骤C2的电压稳定的第二电源信号作为步骤A中输出给所述晶体振荡器的电源信号。
PCT/CN2023/111570 2022-10-31 2023-08-07 晶振启动控制电路及方法、晶振装置、soc芯片 WO2024093417A1 (zh)

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