WO2024093396A1 - 一种图像处理方法、装置及电子设备和非易失性可读存储介质 - Google Patents

一种图像处理方法、装置及电子设备和非易失性可读存储介质 Download PDF

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WO2024093396A1
WO2024093396A1 PCT/CN2023/109982 CN2023109982W WO2024093396A1 WO 2024093396 A1 WO2024093396 A1 WO 2024093396A1 CN 2023109982 W CN2023109982 W CN 2023109982W WO 2024093396 A1 WO2024093396 A1 WO 2024093396A1
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image processing
synchronization signal
signal
processing module
image
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PCT/CN2023/109982
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English (en)
French (fr)
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刘家豪
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山东云海国创云计算装备产业创新中心有限公司
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Publication of WO2024093396A1 publication Critical patent/WO2024093396A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of image processing technology, and in particular, to an image processing method, an image processing device, an electronic device, and a non-volatile readable storage medium.
  • the schematic diagram of the general processing flow of video image processing is shown in Figure 1, including source image output module, common module n1 (no matrix operation), algorithm module m1 containing matrix operation, algorithm module m2 containing matrix operation, algorithm module m3 containing matrix operation, common module n2 (no matrix operation) and image display and other output applications.
  • the typical synchronization signals of video image output are horizontal synchronization signal Hs (Horizontal synchronizing signal) and vertical synchronization signal Vs (Vertical Sync signal). Taking Hs high effective, Vs high effective, and image size 768 times 576 as an example, the signal format is generally shown in Figure 2.
  • FIG3 is a schematic diagram of the image edge matrix algorithm sliding window processing.
  • Traditional processing methods for image edges are generally divided into two types: the first method is to use the image data of the adjacent frames before and after to fill the array of the starting row and the end row of the frame at the upper and lower edges, and the image data of the adjacent rows before and after to fill the array of the starting column and the end column of the row at the left and right edges.
  • the second method is to add an edge processing module or an edge processing method to each algorithm module containing matrix operation to process the image edge.
  • the control process is often complicated, and each algorithm module containing matrix operation needs to use a corresponding edge processing module or edge processing method according to its own algorithm characteristics for processing. With the increase of algorithm modules, it is easy to consume logical resources, make the system complex, and reduce the reliability of system processing.
  • the purpose of the present application is to provide an image processing method, an apparatus, an electronic device and a non-volatile readable storage medium, and the technical problem to be solved is: how to improve the quality of image edge data processing and reduce the processing complexity.
  • the present application provides an image processing method, comprising:
  • the image processing system includes a plurality of image processing modules connected in series;
  • the image processing operations of the target image processing module in the image processing system include:
  • the output signal is expanded, and the expanded output signal is used as the input signal of the next image processing module.
  • the output signal is expanded, including:
  • the image data is filled in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the extended horizontal synchronization signal.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • the preset value is filled in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended common envelope of the horizontal synchronization signal and the field synchronization signal is filled with 0.
  • the last pixel value of the corresponding row is filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the first half is filled with the last pixel value of the corresponding row, and the second half is filled with 0.
  • the method further includes:
  • the source image signal is input into the image processing system for image processing, including:
  • the expanded source image signal is input into the image processing system for image processing.
  • an image processing method comprising:
  • the image processing system includes a plurality of image processing modules connected in series;
  • the image processing operations of the target image processing module in the image processing system include:
  • the input signal is expanded, and the image processing operation corresponding to the target image processing module is performed on the expanded input signal to obtain the output signal of the target image processing module.
  • the input signal is expanded, including:
  • the image data is filled in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the extended horizontal synchronization signal.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • the preset value is filled in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended common envelope of the horizontal synchronization signal and the field synchronization signal is filled with 0.
  • the last pixel value of the corresponding row is filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the first half is filled with the last pixel value of the corresponding row, and the second half is filled with 0.
  • the method further includes:
  • the source image signal is input into the image processing system for image processing, including:
  • the expanded source image signal is input into the image processing system for image processing.
  • the present application provides an image processing device, which is configured to obtain a source image signal and input the source image signal into an image processing system for image processing; wherein the image processing system includes a plurality of image processing modules connected in series;
  • the target image processing modules in the image processing system include:
  • a first processing unit is configured to perform an image processing operation corresponding to a target image processing module on an input signal to obtain an output signal;
  • a first judgment unit is configured to judge whether the image processing operation corresponding to the next image processing module of the target image processing module includes a matrix operation; if it is judged that the image processing operation corresponding to the next image processing module of the target image processing module includes a matrix operation, the workflow of the first extension unit is started;
  • the first expansion unit is configured to expand the output signal and use the expanded output signal as the input signal of the next image processing module.
  • the present application provides an image processing device, which is configured to obtain a source image signal and input the source image signal into an image processing system for image processing; wherein the image processing system includes a plurality of image processing modules connected in series;
  • the target image processing modules in the image processing system include:
  • An acquisition unit is configured to acquire an output signal of a previous image processing module of a target image processing module as an input signal
  • a second judgment unit is configured to judge whether the image processing operation corresponding to the target image processing module includes a matrix operation; if it is judged that the image processing operation corresponding to the target image processing module includes a matrix operation, the workflow of the second extension unit is started;
  • a second expansion unit is configured to expand the input signal
  • the second processing unit is configured to perform an image processing operation corresponding to the target image processing module on the expanded input signal to obtain an output signal of the target image processing module.
  • the present application provides an electronic device, including:
  • a memory arranged to store a computer program
  • the processor is configured to implement the steps of the above-mentioned image processing method when executing the computer program.
  • the present application provides a non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned image processing method are implemented.
  • an image processing method includes: obtaining a source image signal, and inputting the source image signal into an image processing system for image processing; wherein the image processing system includes multiple image processing modules connected in series; the image processing operation of the target image processing module in the image processing system includes: performing an image processing operation corresponding to the target image processing module on the input signal to obtain an output signal; determining whether the image processing operation corresponding to the next image processing module of the target image processing module includes matrix operations; if it is determined that the image processing operation corresponding to the next image processing module of the target image processing module includes matrix operations, then expanding the output signal, and using the expanded output signal as the input signal of the next image processing module.
  • the image processing method provided in the present application is to process the image processing module of the previous image according to whether the image processing operation corresponding to the next image processing module includes matrix operation.
  • the output signal of each image processing module is expanded and then input into the next image processing module to facilitate the processing of the image edge by the algorithm module.
  • the present application simplifies the processing flow of the algorithm module containing matrix operations, so that the image edge data and the internal image data can be uniformly processed when performing matrix operations and no longer require additional treatment. It can also improve the image edge data processing quality to a certain extent, and the expansion principle is simple and easy to implement, requiring very few design resources or logic resources. It can be seen that the image processing method provided by the present application improves the image edge data processing quality and reduces the processing complexity.
  • the present application also discloses an image processing device, an electronic device and a non-volatile readable storage medium, which can also achieve the above-mentioned technical effects.
  • FIG1 is a schematic diagram of a video image processing flow in the related art
  • FIG2 is a schematic diagram of a general signal format
  • FIG3 is a schematic diagram of the sliding window processing of the image edge matrix algorithm
  • FIG4 is an architecture diagram of a first image processing system
  • FIG5 is a flow chart of a first image processing method
  • FIG6 is a schematic diagram of an extended forward synchronization signal
  • FIG7 is a schematic diagram of an extended rear synchronization signal
  • FIG8 is a schematic diagram of extending a pre-field synchronization signal
  • FIG9 is a schematic diagram of an extended back field synchronization signal
  • FIG10 is a schematic diagram of an original source image signal
  • FIG11 is a schematic diagram of an expanded source image signal
  • FIG12 is a schematic diagram showing an expansion when a certain module at a later stage needs to expand a field synchronization signal
  • FIG13 is an architecture diagram of a second image processing system
  • FIG14 is a flow chart of a second image processing method
  • FIG15 is a schematic diagram of an image signal input from a front-stage module to a Gaussian filter algorithm module before expansion;
  • FIG16 is a schematic diagram of an image signal input from an expanded front-stage module to a Gaussian filter algorithm module
  • FIG17 is a schematic diagram of a sliding window processing of image edge matrix operation before signal expansion
  • FIG18 is a schematic diagram of a sliding window processing of image edge matrix operation after signal expansion
  • FIG19 is a structural diagram of a target image processing module in the first image processing system
  • FIG20 is a structural diagram of a target image processing module in a second image processing system
  • FIG. 21 is a structural diagram of an electronic device.
  • the embodiment of the present application discloses an image processing method, which improves the image edge data processing quality and reduces the processing complexity.
  • the method includes the following steps:
  • the image processing system includes a plurality of image processing modules connected in series;
  • a source image signal is acquired and input into an image processing system for image processing.
  • the image processing system includes a plurality of image processing modules connected in series, including image processing modules including matrix operations and image processing modules not including matrix operations.
  • Figure 4 is an architecture diagram of the first image processing system. As shown in Figure 4, it includes a source image output module, a common module n1 (without matrix operation), an algorithm module m1 containing matrix operation, an algorithm module m2 containing matrix operation, an algorithm module m3 containing matrix operation, a common module n2 (without matrix operation) and image display and other output applications.
  • a flowchart of an image processing operation of a target image processing module in a first image processing system includes:
  • S102 Determine whether the image processing operation corresponding to the next image processing module of the target image processing module includes matrix operation; if it is determined that the image processing operation corresponding to the next image processing module of the target image processing module includes matrix operation, proceed to S103;
  • each image module in the image processing system determines whether the image processing operation corresponding to the next image processing module includes matrix operations. If it is determined that the image processing operation corresponding to the next image processing module includes matrix operations, the output signal is expanded and then input into the next image processing module for processing. If it is determined that the image processing operation corresponding to the next image processing module does not include matrix operations, the output signal is directly input into the next image processing module for processing.
  • the output signal is expanded, including: expanding the line synchronization signal and the field synchronization signal of the output signal; and filling the image data in the common envelope of the expanded line synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the extended horizontal synchronization signal.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • Extending the line synchronization signal means increasing the length of the line synchronization signal on the basis of the actual line synchronization signal.
  • the minimum value of the increased length is half of the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • the line synchronization signal is extended, and the envelope length of the extended line synchronization signal is at least 4 pixel cycles longer than the actual line synchronization signal.
  • the synchronization signal line is extended for the 7x7 Gaussian filter matrix operation.
  • the line synchronization signal before extension is shown in Figure 6, and the line synchronization signal after extension is shown in Figure 7.
  • Extending the field synchronization signal means increasing the length of the field synchronization signal on the basis of the actual field synchronization signal, and filling the line synchronization signal in the increased field synchronization signal.
  • the increased length of the field synchronization signal is calculated in units of image line cycles, and the minimum value of the increased length is half of the side length of the array data window required in the image processing operation corresponding to the next image processing module. For example, if a certain level of module output is to be processed by a Gaussian filter module, and the algorithm uses a 7x7 array matrix, the field synchronization signal is extended, and the envelope length of the extended field synchronization signal is at least 4 line cycles longer than the actual field synchronization signal.
  • the field synchronization signal is extended for the 7x7 Gaussian filter matrix operation, and the field synchronization signal before the extension is shown in Figure 8, and the field synchronization signal after the extension is shown in Figure 9.
  • the filled data may vary depending on the algorithm used by the subsequent algorithm module, and this embodiment does not limit it.
  • a preset value such as 0, may be filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the last pixel value of the corresponding line may be filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the first half of the data expanded by Gaussian filtering may also be filled. Fill the last pixel value of each row, and the second half can be filled with 0.
  • the image processing method provided in the embodiment of the present application expands the output signal of the previous image processing module according to whether the image processing operation corresponding to the next image processing module contains matrix operations, and then inputs it into the next image processing module to facilitate the processing of the image edge by the algorithm module.
  • the present application simplifies the processing flow of the algorithm module containing matrix operations, so that the image edge data and the internal image data can be uniformly processed when performing matrix operations and no longer require additional treatment. It can also improve the image edge data processing quality to some extent, and the expansion principle is simple and easy to implement, requiring very few design resources or logic resources. It can be seen that the image processing method provided in the embodiment of the present application improves the image edge data processing quality and reduces the processing complexity.
  • the source image signal after acquiring the source image signal, it also includes: expanding the source image signal so that the expanded source image signal continues to output the line synchronization signal during the period when the field synchronization signal is invalid; accordingly, the source image signal is input into the image processing system for image processing, including: inputting the expanded source image signal into the image processing system for image processing.
  • the source image output signal can be processed, or if the source image module is an autonomous controllable module, the source image module is processed.
  • the processing is to continue to output the line synchronization signal during the invalid period of the field synchronization signal, so that the line synchronization signal is not affected by the field synchronization signal, and start from the source of the signal flow, and keep the line synchronization signal output uninterruptedly according to the line cycle, so that when the subsequent module needs to expand the field synchronization signal and needs to use the line synchronization signal to fill the increased field synchronization signal, it is not necessary to generate a line synchronization signal separately, and the line synchronization signal outside the original actual field synchronization signal envelope can be directly included as needed.
  • the original source image signal is shown in Figure 10, and the expanded source image signal is shown in Figure 11.
  • the envelope of the field synchronization signal can still be used to determine which line periods are valid lines and which line periods are invalid lines. Therefore, it has no effect on ordinary processing modules that do not contain matrix operations.
  • the present embodiment expands the actual field synchronization signal, line synchronization signal, and image data signal of the original input, and adds the actual image edge data, so that when the subsequent stage uses the algorithm module containing matrix operation to process the data of the image edge, the expanded field synchronization signal, line synchronization signal, and image data signal are used to fill the array window, thereby assisting the operation processing of the image edge.
  • the specific edge processing module required by each algorithm module which is complex to control and easy to consume logic resources, can be omitted, and the problem of serious distortion of the image edge and dislocation of the line and field synchronization signals caused by the absence of the edge processing module can be avoided.
  • the embodiment of the present application discloses an image processing method, which improves the image edge data processing quality and reduces the processing complexity.
  • the method includes the following steps:
  • the image processing system includes a plurality of image processing modules connected in series;
  • a source image signal is acquired and input into an image processing system for image processing.
  • the image processing system includes a plurality of image processing modules connected in series, including image processing modules including matrix operations and image processing modules not including matrix operations.
  • Figure 13 is an architecture diagram of the second image processing system. As shown in Figure 13, it includes a source image output module, a common module n1 (without matrix operation), an algorithm module m1 containing matrix operation, an algorithm module m2 containing matrix operation, an algorithm module m3 containing matrix operation, a common module n2 (without matrix operation) and image display and other output applications.
  • FIG. 14 a flowchart of an image processing operation of a target image processing module in a second image processing system, as shown in FIG. 14 , includes:
  • S201 Acquire an output signal of a previous image processing module of a target image processing module as an input signal
  • S202 Determine whether the image processing operation corresponding to the target image processing module includes matrix operation; if it is determined that the image processing operation corresponding to the target image processing module includes matrix operation, proceed to S203;
  • S203 Expand the input signal, and perform image processing operations corresponding to the target image processing module on the expanded input signal to obtain an output signal of the target image processing module.
  • each image module in the image processing system obtains the output signal of the previous image processing module as an input signal, and determines whether the image processing operation corresponding to this module includes matrix operations. If it is determined that the image processing operation corresponding to this module includes matrix operations, the input signal is expanded and then the image processing operation of this module is performed to obtain the output signal of this module. If it is determined that the image processing operation corresponding to this module does not include matrix operations, the image processing operation of this module is directly performed on the input signal to obtain the output signal of this module.
  • the input signal is expanded, including: expanding the line synchronization signal and the field synchronization signal of the input signal; and filling the image data in the common envelope of the expanded line synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the extended horizontal synchronization signal.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • Extending the line synchronization signal means increasing the length of the line synchronization signal on the basis of the actual line synchronization signal.
  • the minimum value of the increased length is half of the side length of the array data window required in the image processing operation corresponding to the next image processing module. For example, if a certain level of module output is to be processed by a Gaussian filter module, and the algorithm uses a 7 by 7 array matrix, the line synchronization signal is expanded.
  • the envelope length of the extended line synchronization signal must be at least 4 pixel periods longer than the actual line synchronization signal.
  • Extending the field synchronization signal means increasing the length of the field synchronization signal on the basis of the actual field synchronization signal, and filling the line synchronization signal in the increased field synchronization signal.
  • the increased length of the field synchronization signal is calculated in units of image line periods, and the minimum increased length is half of the side length of the array data window required in the image processing operation corresponding to the next image processing module. For example, if a certain level of module output is to be processed by a Gaussian filter module, and the algorithm uses a 7 by 7 array matrix, the field synchronization signal is expanded, and the envelope length of the extended field synchronization signal is at least 4 line periods longer than the actual field synchronization signal.
  • the image data is filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the filled data may vary depending on the algorithm used by the subsequent algorithm module, and this embodiment does not limit this.
  • a preset value such as 0, may be filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the last pixel value of the corresponding row may be filled in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the first half of the data expanded by Gaussian filtering may be filled with the last pixel value of each row, and the second half may be filled with 0.
  • the image processing method provided in the embodiment of the present application expands the output signal of the previous image processing module according to whether the image processing operation corresponding to the next image processing module contains matrix operations, and then inputs it into the next image processing module to facilitate the processing of the image edge by the algorithm module.
  • the present application simplifies the processing flow of the algorithm module containing matrix operations, so that the image edge data and the internal image data can be uniformly processed when performing matrix operations and no longer require additional treatment. It can also improve the image edge data processing quality to some extent, and the expansion principle is simple and easy to implement, requiring very few design resources or logic resources. It can be seen that the image processing method provided in the embodiment of the present application improves the image edge data processing quality and reduces the processing complexity.
  • the source image signal after acquiring the source image signal, it also includes: expanding the source image signal so that the expanded source image signal continues to output the line synchronization signal during the period when the field synchronization signal is invalid; accordingly, the source image signal is input into the image processing system for image processing, including: inputting the expanded source image signal into the image processing system for image processing.
  • the source image output signal can be processed, or if the source image module is an autonomous and controllable module, the source image module is processed.
  • the processing is to continue to output the line synchronization signal during the period when the field synchronization signal is invalid, so that the line synchronization signal is not affected by the field synchronization signal.
  • the line synchronization signal is kept output uninterruptedly according to the line cycle, so that when subsequent modules need to expand the field synchronization signal and need to use the line synchronization signal to fill the increased field synchronization signal, there is no need to generate a line synchronization signal separately, and the line synchronization signal outside the original actual field synchronization signal envelope can be directly included as needed.
  • the envelope of the field synchronization signal can still be used to determine which line periods are valid lines and which line periods are invalid lines. Therefore, it has no effect on ordinary processing modules that do not contain matrix operations.
  • the present embodiment expands the original input actual field synchronization signal, line synchronization signal, and image data signal, adds actual image edge data, and enables the subsequent stage to use the expanded field synchronization signal, line synchronization signal, and image data signal when processing the image edge data using the algorithm module containing matrix operations.
  • the array window is filled with the step signal and the image data signal, thereby assisting the calculation and processing of the image edge. This can not only save the specific edge processing module required by each algorithm module, which is complex to control and easy to consume logic resources, but also avoid the problem of serious distortion of the image edge and dislocation of the line and field synchronization signal caused by the absence of the edge processing module.
  • FIG15 A schematic diagram of the image edge matrix operation sliding window processing before signal expansion is shown in FIG17 , in which the solid line frame in FIG17 represents a valid image, and there is no image data in the portion between the dotted line frame and the solid line frame.
  • FIG18 A schematic diagram of the image edge matrix operation sliding window processing after signal expansion is shown in FIG18 , in which the inner solid line frame represents a valid image, and the outer solid line frame represents the portion where image data exists after filling the image data.
  • the edge part of the actual image is expanded and amplified before being input into the algorithm module containing matrix operation, so that when the algorithm module uses matrix operation to process the image edge data, the process is simple, convenient and reliable, and the whole image operation and processing process is simplified and unified, thereby eliminating the image edge specific processing logic required by each algorithm module, and avoiding the problem of continuous misalignment of the line field synchronization signal, and can improve the image quality to a certain extent.
  • the design principle is simple and easy to implement, which saves resources and improves reliability. It not only overcomes the shortcomings of traditional image edge processing methods, but also can realize the non-differentiated pipeline processing process of matrix operation modules and non-matrix operation modules to a certain extent, which is conducive to system unification and efficiency improvement.
  • the edge of the image is expanded and enlarged for the matrix operation required by the relevant algorithm module, so that the process of matrix operation processing of the entire image is simplified and unified, and there is no need to consider the image edge data separately.
  • the whole process is simple and reliable, and the quality of the image edge pixels can be improved to some extent.
  • This embodiment can be applied to the scene of processing images using ASIC (Application Specific Integrated Circuit) or FPGA (Field-Programmable Gate Array), which is easy to implement and consumes very few logic resources or design resources.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • An image processing device provided in an embodiment of the present application is introduced below.
  • the image processing device described below and the image processing method described above can be referenced to each other.
  • the image processing device is configured to obtain a source image signal and input the source image signal into an image processing system for image processing; wherein the image processing system includes a plurality of image processing modules connected in series;
  • the target image processing module includes:
  • the first processing unit 101 is configured to perform an image processing operation corresponding to a target image processing module on an input signal to obtain an output signal;
  • the first judging unit 102 is configured to judge whether the image processing operation corresponding to the next image processing module of the target image processing module includes a matrix operation; if it is judged that the image processing operation corresponding to the next image processing module of the target image processing module includes a matrix operation, the workflow of the first extension unit is started;
  • the first expansion unit 103 is configured to expand the output signal and use the expanded output signal as the input signal of the next image processing module.
  • the image processing device provided in the embodiment of the present application expands the output signal of the previous image processing module according to whether the image processing operation corresponding to the next image processing module contains matrix operations, and then inputs it to the next image processing module to facilitate the algorithm module to process the image edge.
  • the present application simplifies the processing flow of the algorithm module containing matrix operations, so that the image edge data and the internal image data can be uniformly processed when performing matrix operations and no longer require additional treatment. It can also improve the image edge data processing quality to a certain extent, and the expansion principle is simple and easy to implement, requiring very few design resources or logic resources. It can be seen that the image processing device provided in the embodiment of the present application improves the image edge data processing quality and reduces the processing complexity.
  • the first expansion unit 103 includes:
  • a first expansion subunit is configured to expand a horizontal synchronization signal and a vertical synchronization signal of an output signal
  • the first filling subunit is configured to fill the image data in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the horizontal synchronization signal before the extension.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • the first filling subunit may be configured to fill a preset value in the common envelope of the extended horizontal synchronization signal and the vertical synchronization signal.
  • the first filling subunit may be configured to fill the last pixel value of the corresponding row in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the image processing device can be configured to: acquire a source image signal; expand the source image signal so that the expanded source image signal continues to output a line synchronization signal during the period when the field synchronization signal is invalid; and input the expanded source image signal into an image processing system for image processing.
  • An image processing device provided in an embodiment of the present application is introduced below.
  • the image processing device described below and the image processing method described above can be referenced to each other.
  • the image processing device is configured to obtain a source image signal and input the source image signal into an image processing system for image processing; wherein the image processing system includes a plurality of image processing modules connected in series;
  • the target image processing module includes:
  • An acquisition unit 201 is configured to acquire an output signal of a previous image processing module of a target image processing module as an input signal
  • the second judgment unit 202 is configured to judge whether the image processing operation corresponding to the target image processing module includes a matrix operation; if it is judged that the image processing operation corresponding to the target image processing module includes a matrix operation, the workflow of the second extension unit is started;
  • the second expansion unit 203 is configured to expand the input signal
  • the second processing unit 204 is configured to perform an image processing operation corresponding to the target image processing module on the expanded input signal to obtain an output signal of the target image processing module.
  • the image processing device provided in the embodiment of the present application expands the output signal of the previous image processing module according to whether the image processing operation corresponding to the next image processing module contains matrix operations, and then inputs it to the next image processing module to facilitate the algorithm module to process the image edge.
  • the present application simplifies the processing flow of the algorithm module containing matrix operations, so that the image edge data and the internal image data can be uniformly processed when performing matrix operations and no longer require additional treatment. It can also improve the image edge data processing quality to a certain extent, and the expansion principle is simple and easy to implement, requiring very few design resources or logic resources. It can be seen that the image processing device provided in the embodiment of the present application improves the image edge data processing quality and reduces the processing complexity.
  • the second expansion unit 203 includes:
  • a second expansion subunit is configured to expand a horizontal synchronization signal and a vertical synchronization signal of an input signal
  • the second filling subunit is configured to fill the image data in the common envelope of the extended horizontal synchronization signal and the field synchronization signal.
  • the extended horizontal synchronization signal is at least longer than the horizontal synchronization signal before the extension.
  • the extended field synchronization signal is at least longer than the extended field synchronization signal row periods, and N is the side length of the array data window required in the image processing operation corresponding to the next image processing module.
  • the second filling subunit may be configured to fill a preset value in the common envelope of the extended horizontal synchronization signal and the vertical synchronization signal.
  • the second filling subunit may be configured to fill the last pixel value of the corresponding row in the common envelope of the extended line synchronization signal and the field synchronization signal.
  • the image processing device can be configured to: acquire a source image signal; expand the source image signal so that the expanded source image signal continues to output a line synchronization signal during the period when the field synchronization signal is invalid; and input the expanded source image signal into an image processing system for image processing.
  • FIG. 21 is a structural diagram of an electronic device. As shown in FIG. 21, the electronic device includes:
  • Communication interface 1 capable of exchanging information with other devices such as network devices;
  • the processor 2 is connected to the communication interface 1 to realize information exchange with other devices, and is configured to execute the image processing method provided by one or more of the above technical solutions when running a computer program.
  • the computer program is stored in the memory 3.
  • bus system 4 is configured to realize the connection and communication between these components.
  • the bus system 4 also includes a power bus, a control bus and a status signal bus.
  • various buses are marked as the bus system 4 in FIG. 21.
  • the memory 3 in the embodiment of the present application is configured to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on the electronic device.
  • the embodiment of the present application also provides a non-volatile readable storage medium, for example, including a memory 3 storing a computer program, and the above-mentioned computer program can be executed by the processor 2 to complete the above-mentioned method steps.
  • the non-volatile readable storage medium can be a FRAM (ferromagnetic random access memory), ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), Flash Memory, magnetic surface memory, optical disk, or CD-ROM (compact disc read-only memory) and other memories.

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Abstract

本申请公开了一种图像处理方法、装置及电子设备和非易失性可读存储介质，涉及图像处理技术领域，该方法包括：获取源图像信号，并将所述源图像信号输入图像处理系统中进行图像处理；所述图像处理系统中的目标图像处理模块的图像处理操作包括：对输入信号进行所述目标图像处理模块对应的图像处理操作得到输出信号；判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对所述输出信号进行扩展，并将扩展后的输出信号作为所述下一个图像处理模块的输入信号。本申请提高了图像边缘数据处理质量、且降低了处理复杂度。

Description

一种图像处理方法、装置及电子设备和非易失性可读存储介质
相关申请的交叉引用
本申请要求于2022年11月01日提交中国专利局，申请号为202211352901.8，申请名称为“一种图像处理方法、装置及电子设备和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及图像处理技术领域，特别的，涉及一种图像处理方法、装置及一种电子设备和一种非易失性可读存储介质。
背景技术
对视频图像处理一般的处理流程的示意图如图1所示，包括源图像输出模块，普通模块n1(无矩阵运算)、含矩阵运算的算法模块m1、含矩阵运算的算法模块m2、含矩阵运算的算法模块m3、普通模块n2(无矩阵运算)和图像显示及其他输出应用。视频图像输出的典型同步信号为行同步信号Hs(Horizontal synchronizing signal)和场同步信号Vs(Vertical Sync signal)，以Hs高有效，Vs高有效，图像大小768乘576为例，信号格式一般如图2所示。由此可见，在进行含有矩阵运算的算法滑窗处理时，以7乘7正方形阵列为例，在图像最上方前六行数据、最下方后六行数据、最左侧前六列数据及最右侧后六列数据进行矩阵运算时，由于四个边缘数据无法填满7乘7的阵列窗口，所以在进行矩阵运算时，每帧图像的上下左右边缘数据均无法进行正常的运算处理，而需要额外考虑处理方法。
如图3所示，图3为图像边缘矩阵算法滑窗处理示意图。传统针对图像边缘的处理方法一般分为两种：第一种方法为上下边缘使用前后相邻帧的图像数据进行该帧起始行和末尾行的阵列填充，左右边缘使用前后相邻行的图像数据进行该行起始列和末尾列的阵列填充，采用该方法，由于上一帧/上一行的图像末尾数据与下一帧/下一行的图像起始数据往往相差较大，在参与矩阵运算处理后容易造成图像边缘失真严重，且由于图像前后帧前后行的数据互相补充连贯，在经矩阵运算处理后，实际的行同步信号场同步信号均会发生连贯错位，不利于图像分割断帧应用。第二种方法为在每一个含有矩阵运算的算法模块中额外添加一个边缘处理模块或者额外采用一种边缘处理方法来对图像边缘进行处理。使用该方法，往往控制过程复杂，且每个含有矩阵运算的算法模块均需要按照自己的算法特征采用一个相应的边缘处理模块或者边缘处理方法进行处理，随着算法模块的增多，既容易消耗逻辑资源，又会使系统复杂，降低系统处理的可靠性。
因视频图像在进行含有矩阵运算的某种算法处理时，图像边缘有效数据无法填满阵列窗口，所以存在一定问题，需要额外对待处理，传统处理方法要么会导致图像边缘容易失真严重，且行场同步信号连贯错位，要么使得每个算法模块都需要额外添加相应的边缘处理模块或边缘处理方法，增加系统复杂度，既容易消耗逻辑资源又会降低系统可靠性。
相关技术中存在的上述技术问题，当前尚未得到解决。
发明内容
本申请的目的在于提供一种图像处理方法、装置及一种电子设备和一种非易失性可读存储介质，解决的技术问题是：如何提高图像边缘数据处理质量、且降低了处理复杂度。
本申请实施例的第一个方面，为实现上述目的，本申请提供了一种图像处理方法，包括：
获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
图像处理系统中的目标图像处理模块的图像处理操作包括：
对输入信号进行目标图像处理模块对应的图像处理操作得到输出信号；
判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；
在判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对输出信号进行扩展，并将扩展后的输出信号作为下一个图像处理模块的输入信号。
其中，对输出信号进行扩展，包括：
扩展输出信号的行同步信号和场同步信号；
在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
其中，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充0。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中前半部分填充对应行的最后一个像素值，后半部分填充0。
其中，获取源图像信号之后，还包括：
对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；
相应的，将源图像信号输入图像处理系统中进行图像处理，包括：
将扩展后的源图像信号输入图像处理系统中进行图像处理。
为实现上述目的，本申请提供了一种图像处理方法，包括：
获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
图像处理系统中的目标图像处理模块的图像处理操作包括：
获取目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
判断目标图像处理模块对应的图像处理操作中是否包含矩阵运算；
在判断目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对输入信号进行扩展，并对扩展后的输入信号进行目标图像处理模块对应的图像处理操作得到目标图像处理模块的输出信号。
其中，对输入信号进行扩展，包括：
扩展输入信号的行同步信号和场同步信号；
在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
其中，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充0。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
其中，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
在扩展出的行同步信号与场同步信号共同的包络中前半部分填充对应行的最后一个像素值，后半部分填充0。
其中，获取源图像信号之后，还包括：
对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；
相应的，将源图像信号输入图像处理系统中进行图像处理，包括：
将扩展后的源图像信号输入图像处理系统中进行图像处理。
本申请实施例的的第二个方面，为实现上述目的，本申请提供了一种图像处理装置，图像处理装置被设置为获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
图像处理系统中的目标图像处理模块包括：
第一处理单元，被设置为对输入信号进行目标图像处理模块对应的图像处理操作得到输出信号；
第一判断单元，被设置为判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第一扩展单元的工作流程；
第一扩展单元，被设置为对输出信号进行扩展，并将扩展后的输出信号作为下一个图像处理模块的输入信号。
为实现上述目的，本申请提供了一种图像处理装置，图像处理装置被设置为获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
图像处理系统中的目标图像处理模块包括：
获取单元，被设置为获取目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
第二判断单元，被设置为判断目标图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第二扩展单元的工作流程；
第二扩展单元，被设置为对输入信号进行扩展；
第二处理单元，被设置为对扩展后的输入信号进行目标图像处理模块对应的图像处理操作得到目标图像处理模块的输出信号。
本申请实施例的的第三个方面，为实现上述目的，本申请提供了一种电子设备，包括：
存储器，被设置为存储计算机程序；
处理器，被设置为执行计算机程序时实现如上述图像处理方法的步骤。
本申请实施例的的第四个方面，为实现上述目的，本申请提供了一种非易失性可读存储介质，非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述图像处理方法的步骤。
通过以上方案可知，本申请提供的一种图像处理方法，包括：获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；图像处理系统中的目标图像处理模块的图像处理操作包括：对输入信号进行目标图像处理模块对应的图像处理操作得到输出信号；判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对输出信号进行扩展，并将扩展后的输出信号作为下一个图像处理模块的输入信号。
本申请提供的图像处理方法，根据下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，对上一 个图像处理模块的输出信号进行扩展，然后输入到下一个图像处理模块，以便于算法模块对于图像边缘的处理。本申请既简化了含有矩阵运算的算法模块处理流程，使得图像边缘数据和图像内部数据一样，在进行矩阵运算时可统一处理，不再需要额外对待，又可在某种程度上提高图像边缘数据处理质量，且扩展原理简单，容易实现，需要的设计资源或逻辑资源极少。由此可见，本申请提供的图像处理方法，提高了图像边缘数据处理质量、且降低了处理复杂度。本申请还公开了一种图像处理装置及一种电子设备和一种非易失性可读存储介质，同样能实现上述技术效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本申请。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的可选实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为相关技术中对视频图像处理流程的示意图；
图2为一般的信号格式示意图；
图3为图像边缘矩阵算法滑窗处理示意图；
图4为第一种图像处理系统的架构图；
图5为第一种图像处理方法的流程图；
图6为一种扩展前行同步信号的示意图；
图7为一种扩展后行同步信号的示意图；
图8为一种扩展前场同步信号的示意图；
图9为一种扩展后场同步信号的示意图；
图10为一种原始的源图像信号的示意图；
图11为一种扩展后的源图像信号的示意图；
图12为一种后级某模块需要扩展场同步信号时扩展示意图；
图13为第二种图像处理系统的架构图；
图14为第二种图像处理方法的流程图；
图15为一种扩展前前级模块输入给高斯滤波算法模块的图像信号的示意图；
图16为一种扩展后前级模块输入给高斯滤波算法模块的图像信号的示意图；
图17为一种信号扩展前图像边缘矩阵运算滑窗处理示意图；
图18为一种信号扩展后图像边缘矩阵运算滑窗处理示意图；
图19为第一种图像处理系统中的目标图像处理模块的结构图；
图20为第二种图像处理系统中的目标图像处理模块的结构图；
图21为一种电子设备的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。另外，在本申请实施例中， “第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本申请实施例公开了一种图像处理方法，提高了图像边缘数据处理质量、且降低了处理复杂度。可选的，包括以下步骤：
获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
在本实施例中，获取源图像信号，将其输入图像处理系统中进行图像处理，该图像处理系统包括多个串联的图像处理模块，其中包括包含矩阵运算的图像处理模块和不包含矩阵运算的图像处理模块。
图4为第一种图像处理系统的架构图，如图4所示，包括源图像输出模块，普通模块n1(无矩阵运算)、含矩阵运算的算法模块m1、含矩阵运算的算法模块m2、含矩阵运算的算法模块m3、普通模块n2(无矩阵运算)和图像显示及其他输出应用。
参见图5，第一种图像处理系统中的目标图像处理模块的图像处理操作的流程图，如图5所示，包括：
S101：对输入信号进行目标图像处理模块对应的图像处理操作得到输出信号；
S102：判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则进入S103；
S103：对输出信号进行扩展，并将扩展后的输出信号作为下一个图像处理模块的输入信号。
在可选实施中，图像处理系统中的每一个图像模块，也即上述目标图像处理模块，对输入信号执行本模块的图像处理操作得到输出信号之后，判断下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，在判断下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对输出信号进行扩展后再输入下一个图像处理模块进行处理，在判断下一个图像处理模块对应的图像处理操作中不包含矩阵运算的情况下，则直接将输出信号输入下一个图像处理模块进行处理。
作为一种可行的实施方式，对输出信号进行扩展，包括：扩展输出信号的行同步信号和场同步信号；在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
其中，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
扩展行同步信号即在实际行同步信号的基础上增加行同步信号的长度，增加长度最小值为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长值的一半，如某级模块输出后要进行高斯滤波模块处理，算法采用7乘7阵列矩阵，则对行同步信号进行扩展，扩展的行同步信号包络长度最少要比实际行同步信号长4个像素周期。以图像尺寸768乘576为例，针对7乘7高斯滤波矩阵运算进行同步信号行扩展，扩展前行同步信号如图6所示，扩展后行同步信号如图7所示。
扩展场同步信号即在实际场同步信号的基础上增加场同步信号的长度，同时在增加的场同步信号中填充行同步信号，增加的场同步信号长度以图像行周期为单位计算，增加长度最小值为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长值的一半，如某级模块输出后要进行高斯滤波模块处理，算法采用7乘7阵列矩阵，则对场同步信号进行扩展，扩展的场同步信号包络长度最少要比实际场同步信号长4个行周期。以图像尺寸768乘576为例，针对7乘7高斯滤波矩阵运算进行场同步信号扩展，扩展前场同步信号如图8所示，扩展后场同步信号如图9所示。
可选的，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。填充的数据可视后级算法模块所使用的算法情况不同而不同，本实施例不进行限定。作为一种可行的实施方式，可以在扩展出的行同步信号与场同步信号共同的包络中填充预设值，例如0。作为另一种可行的实施方式，可以在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。当然，也可以对高斯滤波扩展出来的数据前半部分可 填充每行最后一个像素值，后半部分可填充0。
本申请实施例提供的图像处理方法，根据下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，对上一个图像处理模块的输出信号进行扩展，然后输入到下一个图像处理模块，以便于算法模块对于图像边缘的处理。本申请既简化了含有矩阵运算的算法模块处理流程，使得图像边缘数据和图像内部数据一样，在进行矩阵运算时可统一处理，不再需要额外对待，又可在某种程度上提高图像边缘数据处理质量，且扩展原理简单，容易实现，需要的设计资源或逻辑资源极少。由此可见，本申请实施例提供的图像处理方法，提高了图像边缘数据处理质量、且降低了处理复杂度。
在上述实施例的基础上，作为一种可选实施方式，获取源图像信号之后，还包括：对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；相应的，将源图像信号输入图像处理系统中进行图像处理，包括：将扩展后的源图像信号输入图像处理系统中进行图像处理。
为便于各级模块进行场同步信号的扩展，可对源图像输出信号进行处理，或者源图像模块为自主可控模块，则对源图像模块进行处理，该处理为，在场同步信号无效期间，继续输出行同步信号，使得行同步信号不受场同步信号影响，从信号流向的源头上开始，保持行同步信号按行周期不间断的进行输出，以使得后续模块在需要时对场同步信号进行扩展后，需要使用行同步信号填充增加的场同步信号时，不必再单独生成行同步信号，直接按需将原来实际场同步信号包络之外的行同步信号包络进去即可。原始的源图像信号如图10所示，扩展后的源图像信号如图11所示。
可以理解的是，源图像输出处理后虽然行同步信号在无间断的输出，却依然可以通过场同步信号的包络来判断出哪些行周期是有效行哪些行周期是无效行，因此对于不含矩阵运算的普通处理模块没有任何影响。
源图像模块输出信号经过处理之后，保持行同步信号不间断输出，后级某模块需要扩展场同步信号时，扩展示意图如图12所示。
由此可见，本实施例对原输入的实际的场同步信号、行同步信号、图像数据信号进行扩展，增加实际图像边缘数据，使后级使用含有矩阵运算的算法模块在处理图像边缘的数据时，使用扩展出来的场同步信号、行同步信号及图像数据信号进行阵列窗口填充，从而辅助图像边缘的运算处理，这样既可以省去每个算法模块所需要的控制复杂且容易消耗逻辑资源的特定边缘处理模块，也可以避免因没有边缘处理模块而造成图像边缘容易失真严重以及行场同步信号连贯错位的问题。
本申请实施例公开了一种图像处理方法，提高了图像边缘数据处理质量、且降低了处理复杂度。可选的，包括以下步骤：
获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
在本实施例中，获取源图像信号，将其输入图像处理系统中进行图像处理，该图像处理系统包括多个串联的图像处理模块，其中包括包含矩阵运算的图像处理模块和不包含矩阵运算的图像处理模块。
图13为第二种图像处理系统的架构图，如图13所示，包括源图像输出模块，普通模块n1(无矩阵运算)、含矩阵运算的算法模块m1、含矩阵运算的算法模块m2、含矩阵运算的算法模块m3、普通模块n2(无矩阵运算)和图像显示及其他输出应用。
参见图14，第二种图像处理系统中的目标图像处理模块的图像处理操作的流程图，如图14所示，包括：
S201：获取目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
S202：判断目标图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则进入S203；
S203：对输入信号进行扩展，并对扩展后的输入信号进行目标图像处理模块对应的图像处理操作得到目标图像处理模块的输出信号。
在可选实施中，图像处理系统中的每一个图像模块，也即上述目标图像处理模块，获取上一个图像处理模块的输出信号作为输入信号，判断本模块对应的图像处理操作中是否包含矩阵运算，在判断本模块对应的图像处理操作中包含矩阵运算的情况下，则对输入信号进行扩展后执行本模块的图像处理操作得到本模块输出信号，在判断本模块对应的图像处理操作中不包含矩阵运算的情况下，则直接对输入信号执行本模块的图像处理操作得到本模块输出信号。
作为一种可行的实施方式，对输入信号进行扩展，包括：扩展输入信号的行同步信号和场同步信号；在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
其中，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
扩展行同步信号即在实际行同步信号的基础上增加行同步信号的长度，增加长度最小值为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长值的一半，如某级模块输出后要进行高斯滤波模块处理，算法采用7乘7阵列矩阵，则对行同步信号进行扩展，扩展的行同步信号包络长度最少要比实际行同步信号长4个像素周期。
扩展场同步信号即在实际场同步信号的基础上增加场同步信号的长度，同时在增加的场同步信号中填充行同步信号，增加的场同步信号长度以图像行周期为单位计算，增加长度最小值为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长值的一半，如某级模块输出后要进行高斯滤波模块处理，算法采用7乘7阵列矩阵，则对场同步信号进行扩展，扩展的场同步信号包络长度最少要比实际场同步信号长4个行周期。
可选的，在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。填充的数据可视后级算法模块所使用的算法情况不同而不同，本实施例不进行限定。作为一种可行的实施方式，可以在扩展出的行同步信号与场同步信号共同的包络中填充预设值，例如0。作为另一种可行的实施方式，可以在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。当然，也可以对高斯滤波扩展出来的数据前半部分可填充每行最后一个像素值，后半部分可填充0。
本申请实施例提供的图像处理方法，根据下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，对上一个图像处理模块的输出信号进行扩展，然后输入到下一个图像处理模块，以便于算法模块对于图像边缘的处理。本申请既简化了含有矩阵运算的算法模块处理流程，使得图像边缘数据和图像内部数据一样，在进行矩阵运算时可统一处理，不再需要额外对待，又可在某种程度上提高图像边缘数据处理质量，且扩展原理简单，容易实现，需要的设计资源或逻辑资源极少。由此可见，本申请实施例提供的图像处理方法，提高了图像边缘数据处理质量、且降低了处理复杂度。
在上述实施例的基础上，作为一种可选实施方式，获取源图像信号之后，还包括：对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；相应的，将源图像信号输入图像处理系统中进行图像处理，包括：将扩展后的源图像信号输入图像处理系统中进行图像处理。
为便于各级模块进行场同步信号的扩展，可对源图像输出信号进行处理，或者源图像模块为自主可控模块，则对源图像模块进行处理，该处理为，在场同步信号无效期间，继续输出行同步信号，使得行同步信号不受场同步信号影响，从信号流向的源头上开始，保持行同步信号按行周期不间断的进行输出，以使得后续模块在需要时对场同步信号进行扩展后，需要使用行同步信号填充增加的场同步信号时，不必再单独生成行同步信号，直接按需将原来实际场同步信号包络之外的行同步信号包络进去即可。
可以理解的是，源图像输出处理后虽然行同步信号在无间断的输出，却依然可以通过场同步信号的包络来判断出哪些行周期是有效行哪些行周期是无效行，因此对于不含矩阵运算的普通处理模块没有任何影响。
由此可见，本实施例对原输入的实际的场同步信号、行同步信号、图像数据信号进行扩展，增加实际图像边缘数据，使后级使用含有矩阵运算的算法模块在处理图像边缘的数据时，使用扩展出来的场同步信号、行同 步信号及图像数据信号进行阵列窗口填充，从而辅助图像边缘的运算处理，这样既可以省去每个算法模块所需要的控制复杂且容易消耗逻辑资源的特定边缘处理模块，也可以避免因没有边缘处理模块而造成图像边缘容易失真严重以及行场同步信号连贯错位的问题。
下面介绍本申请提供的一种应用实施例，以图像大小768乘576为例，针对7乘7高斯滤波矩阵运算进行示意，扩展前前级模块输入给高斯滤波算法模块的图像信号如图15所示，扩展后前级模块输入给高斯滤波算法模块的图像信号如图16所示。信号扩展前图像边缘矩阵运算滑窗处理示意图如图17所示，图17中实线框表示有效图像，虚线框与实线框之间的部分不存在图像数据，信号扩展后图像边缘矩阵运算滑窗处理示意图如图18所示，图18中，内侧实线框表示有效图像，外侧实线框表示填充图像数据之后存在图像数据的部分。
采用预先扩展输入信号的方法，将实际图像边缘部分进行扩展放大后再输入给含有矩阵运算的算法模块，使得算法模块在使用矩阵运算处理图像边缘数据时，流程简单，方便可靠，整副图像运算处理流程得以简化统一，从而既省去了各个算法模块所需的图像边缘特定处理逻辑，又不会发生行场同步信号连贯错位的问题，并可在一定程度上提高图像质量，本设计原理简单，易于实现，既节省了资源，又提高了可靠性，不但克服了传统图像边缘处理方法的缺点，而且可在某种程度上实现矩阵运算模块和非矩阵运算模块的无差异化流水线处理流程，有助于系统统一，提高效率。
采用将实际信号进行扩展的方法，为相关算法模块所需的矩阵运算扩展放大图像边缘部分，使得整副图像进行矩阵运算处理时流程得以简化统一，不必再单独为图像边缘数据进行考虑，整个过程既简单又可靠，还可以在某种程度上提高图像边缘像素质量。本实施例可以应用于利用ASIC(Application Specific Integrated Circuit，专用集成电路)或FPGA(Field-Programmable Gate Array，现场可编程逻辑器件)处理图像的场景，易于实现，消耗的逻辑资源或设计资源极少。
下面对本申请实施例提供的一种图像处理装置进行介绍，下文描述的一种图像处理装置与上文描述的一种图像处理方法可以相互参照。
图像处理装置被设置为获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
参见图19，第一种图像处理系统中的目标图像处理模块的结构图，如图19所示，该目标图像处理模块包括：
第一处理单元101，被设置为对输入信号进行目标图像处理模块对应的图像处理操作得到输出信号；
第一判断单元102，被设置为判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第一扩展单元的工作流程；
第一扩展单元103，被设置为对输出信号进行扩展，并将扩展后的输出信号作为下一个图像处理模块的输入信号。
本申请实施例提供的图像处理装置，根据下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，对上一个图像处理模块的输出信号进行扩展，然后输入到下一个图像处理模块，以便于算法模块对于图像边缘的处理。本申请既简化了含有矩阵运算的算法模块处理流程，使得图像边缘数据和图像内部数据一样，在进行矩阵运算时可统一处理，不再需要额外对待，又可在某种程度上提高图像边缘数据处理质量，且扩展原理简单，容易实现，需要的设计资源或逻辑资源极少。由此可见，本申请实施例提供的图像处理装置，提高了图像边缘数据处理质量、且降低了处理复杂度。
在上述实施例的基础上，作为一种可选实施方式，第一扩展单元103包括：
第一扩展子单元，被设置为扩展输出信号的行同步信号和场同步信号；
第一填充子单元，被设置为在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
在上述实施例的基础上，作为一种可选实施方式，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
在上述实施例的基础上，作为一种可选实施方式，第一填充子单元可以被设置为：在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
在上述实施例的基础上，作为一种可选实施方式，第一填充子单元可以被设置为：在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
在上述实施例的基础上，作为一种可选实施方式，图像处理装置可以被设置为：获取源图像信号；对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；将扩展后的源图像信号输入图像处理系统中进行图像处理。
下面对本申请实施例提供的一种图像处理装置进行介绍，下文描述的一种图像处理装置与上文描述的一种图像处理方法可以相互参照。
图像处理装置被设置为获取源图像信号，并将源图像信号输入图像处理系统中进行图像处理；其中，图像处理系统包括多个串联的图像处理模块；
参见图20，第二种图像处理系统中的目标图像处理模块的结构图，如图20所示，该目标图像处理模块包括：
获取单元201，被设置为获取目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
第二判断单元202，被设置为判断目标图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第二扩展单元的工作流程；
第二扩展单元203，被设置为对输入信号进行扩展；
第二处理单元204，被设置为对扩展后的输入信号进行目标图像处理模块对应的图像处理操作得到目标图像处理模块的输出信号。
本申请实施例提供的图像处理装置，根据下一个图像处理模块对应的图像处理操作中是否包含矩阵运算，对上一个图像处理模块的输出信号进行扩展，然后输入到下一个图像处理模块，以便于算法模块对于图像边缘的处理。本申请既简化了含有矩阵运算的算法模块处理流程，使得图像边缘数据和图像内部数据一样，在进行矩阵运算时可统一处理，不再需要额外对待，又可在某种程度上提高图像边缘数据处理质量，且扩展原理简单，容易实现，需要的设计资源或逻辑资源极少。由此可见，本申请实施例提供的图像处理装置，提高了图像边缘数据处理质量、且降低了处理复杂度。
在上述实施例的基础上，作为一种可选实施方式，第二扩展单元203包括：
第二扩展子单元，被设置为扩展输入信号的行同步信号和场同步信号；
第二填充子单元，被设置为在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
在上述实施例的基础上，作为一种可选实施方式，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
在上述实施例的基础上，作为一种可选实施方式，第二填充子单元可以被设置为：在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
在上述实施例的基础上，作为一种可选实施方式，第二填充子单元可以被设置为：在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
在上述实施例的基础上，作为一种可选实施方式，图像处理装置可以被设置为：获取源图像信号；对源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；将扩展后的源图像信号输入图像处理系统中进行图像处理。
关于上述实施例中的装置，其中各个模块执行操作的方式已经在有关该方法的实施例中进行了详细描述，此处将不做详细阐述说明。
基于上述程序模块的硬件实现，且为了实现本申请实施例的方法，本申请实施例还提供了一种电子设备，图21为一种电子设备的结构图，如图21所示，电子设备包括：
通信接口1，能够与其它设备比如网络设备等进行信息交互；
处理器2，与通信接口1连接，以实现与其它设备进行信息交互，被设置为运行计算机程序时，执行上述一个或多个技术方案提供的图像处理方法。而计算机程序存储在存储器3上。
当然，实际应用时，电子设备中的各个组件通过总线系统4耦合在一起。可理解，总线系统4被设置为实现这些组件之间的连接通信。总线系统4除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图21中将各种总线都标为总线系统4。
本申请实施例中的存储器3被设置为存储各种类型的数据以支持电子设备的操作。这些数据的示例包括：用于在电子设备上操作的任何计算机程序。
本申请实施例还提供了一种非易失性可读存储介质，例如包括存储计算机程序的存储器3，上述计算机程序可由处理器2执行，以完成前述方法步骤。非易失性可读存储介质可以是FRAM(磁性随机存取存储器，ferromagnetic random access memory)、ROM(只读存储器，Read Only Memory)、PROM(可编程只读存储器，Programmable Read-Only Memory)、EPROM(可擦除可编程只读存储器，Erasable Programmable Read-Only Memory)、EEPROM(电可擦除可编程只读存储器，Electrically Erasable Programmable Read-Only Memory)、Flash Memory(快闪存储器)、磁表面存储器、光盘、或CD-ROM(只读光盘，Compact Disc Read-Only Memory)等存储器。
以上，仅为本申请的可选实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种图像处理方法，其特征在于，包括：
    获取源图像信号，并将所述源图像信号输入图像处理系统中进行图像处理；其中，所述图像处理系统包括多个串联的图像处理模块；
    所述图像处理系统中的目标图像处理模块的图像处理操作包括：
    对输入信号进行所述目标图像处理模块对应的图像处理操作得到输出信号；
    判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；
    在判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对所述输出信号进行扩展，并将扩展后的输出信号作为所述下一个图像处理模块的输入信号。
  2. 根据权利要求1所述图像处理方法，其特征在于，对所述输出信号进行扩展，包括：
    扩展所述输出信号的行同步信号和场同步信号；
    在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
  3. 根据权利要求2所述图像处理方法，其特征在于，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为所述下一个图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
  4. 根据权利要求2所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
  5. 根据权利要求4所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充0。
  6. 根据权利要求2所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
  7. 根据权利要求6所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中前半部分填充对应行的最后一个像素值，后半部分填充0。
  8. 根据权利要求1所述图像处理方法，其特征在于，所述获取源图像信号之后，还包括：
    对所述源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；
    相应的，将所述源图像信号输入图像处理系统中进行图像处理，包括：
    将扩展后的源图像信号输入图像处理系统中进行图像处理。
  9. 一种图像处理方法，其特征在于，包括：
    获取源图像信号，并将所述源图像信号输入图像处理系统中进行图像处理；其中，所述图像处理系统包括多个串联的图像处理模块；
    所述图像处理系统中的目标图像处理模块的图像处理操作包括：
    获取所述目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
    判断所述目标图像处理模块对应的图像处理操作中是否包含矩阵运算；
    在判断所述目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则对所述输入信号进行扩展，并对扩展后的输入信号进行所述目标图像处理模块对应的图像处理操作得到所述目标图像处理模块的输出信号。
  10. 根据权利要求9所述图像处理方法，其特征在于，对所述输入信号进行扩展，包括：
    扩展所述输入信号的行同步信号和场同步信号；
    在扩展出的行同步信号与场同步信号共同的包络中填充图像数据。
  11. 根据权利要求10所述图像处理方法，其特征在于，扩展后的行同步信号至少比扩展前的行同步信号长个像素周期，扩展后的场同步信号至少比扩展前的场同步信号长个行周期，N为所述目标图像处理模块对应的图像处理操作中所需阵列数据窗口的边长。
  12. 根据权利要求10所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充预设值。
  13. 根据权利要求12所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充0。
  14. 根据权利要求10所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中填充对应行的最后一个像素值。
  15. 根据权利要求14所述图像处理方法，其特征在于，所述在扩展出的行同步信号与场同步信号共同的包络中填充图像数据，包括：
    在扩展出的行同步信号与场同步信号共同的包络中前半部分填充对应行的最后一个像素值，后半部分填充0。
  16. 根据权利要求9所述图像处理方法，其特征在于，所述获取源图像信号之后，还包括：
    对所述源图像信号进行扩展，以使扩展后的源图像信号中在场同步信号无效期间继续输出行同步信号；
    相应的，将所述源图像信号输入图像处理系统中进行图像处理，包括：
    将扩展后的源图像信号输入图像处理系统中进行图像处理。
  17. 一种图像处理装置，其特征在于，所述图像处理装置被设置为获取源图像信号，并将所述源图像信号输入图像处理系统中进行图像处理；其中，所述图像处理系统包括多个串联的图像处理模块；
    所述图像处理系统中的目标图像处理模块包括：
    第一处理单元，被设置为对输入信号进行所述目标图像处理模块对应的图像处理操作得到输出信号；
    第一判断单元，被设置为判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断所述目标图像处理模块的下一个图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第一扩展单元的工作流程；
    所述第一扩展单元，被设置为对所述输出信号进行扩展，并将扩展后的输出信号作为所述下一个图像处理模块的输入信号。
  18. 一种图像处理装置，其特征在于，所述图像处理装置被设置为获取源图像信号，并将所述源图像信号输入图像处理系统中进行图像处理；其中，所述图像处理系统包括多个串联的图像处理模块；
    所述图像处理系统中的目标图像处理模块包括：
    获取单元，被设置为获取所述目标图像处理模块的上一个图像处理模块的输出信号作为输入信号；
    第二判断单元，被设置为判断所述目标图像处理模块对应的图像处理操作中是否包含矩阵运算；在判断所述目标图像处理模块对应的图像处理操作中包含矩阵运算的情况下，则启动第二扩展单元的工作流程；
    所述第二扩展单元，被设置为对所述输入信号进行扩展；
    第二处理单元，被设置为对扩展后的输入信号进行所述目标图像处理模块对应的图像处理操作得到所 述目标图像处理模块的输出信号。
  19. 一种电子设备，其特征在于，包括：
    存储器，被设置为存储计算机程序；
    处理器，被设置为执行所述计算机程序时实现如权利要求1至16任一项所述图像处理方法的步骤。
  20. 一种非易失性可读存储介质，其特征在于，所述非易失性可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至16任一项所述图像处理方法的步骤。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110771159A (zh) * 2018-09-26 2020-02-07 深圳市大疆创新科技有限公司 图像处理系统和图像处理方法
CN114519690A (zh) * 2020-11-19 2022-05-20 京东方科技集团股份有限公司 图像处理方法及装置、图像检测方法及系统、存储介质
CN115103097A (zh) * 2022-06-17 2022-09-23 深圳市雨滴科技有限公司 一种图像处理装置、方法、计算机设备及可读存储介质
CN115760600A (zh) * 2022-11-01 2023-03-07 山东云海国创云计算装备产业创新中心有限公司 一种图像处理方法、装置及电子设备和存储介质

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1111464A (zh) * 1993-06-30 1995-11-08 世嘉企业股份有限公司 图像处理装置及其方法和带图像处理装置的电子装置
US6750835B2 (en) * 1999-12-27 2004-06-15 Semiconductor Energy Laboratory Co., Ltd. Image display device and driving method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110771159A (zh) * 2018-09-26 2020-02-07 深圳市大疆创新科技有限公司 图像处理系统和图像处理方法
CN114519690A (zh) * 2020-11-19 2022-05-20 京东方科技集团股份有限公司 图像处理方法及装置、图像检测方法及系统、存储介质
CN115103097A (zh) * 2022-06-17 2022-09-23 深圳市雨滴科技有限公司 一种图像处理装置、方法、计算机设备及可读存储介质
CN115760600A (zh) * 2022-11-01 2023-03-07 山东云海国创云计算装备产业创新中心有限公司 一种图像处理方法、装置及电子设备和存储介质

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