WO2024093281A1 - 集成电路及其制备方法、三维集成电路、电子设备 - Google Patents

集成电路及其制备方法、三维集成电路、电子设备 Download PDF

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WO2024093281A1
WO2024093281A1 PCT/CN2023/102965 CN2023102965W WO2024093281A1 WO 2024093281 A1 WO2024093281 A1 WO 2024093281A1 CN 2023102965 W CN2023102965 W CN 2023102965W WO 2024093281 A1 WO2024093281 A1 WO 2024093281A1
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layer
integrated circuit
substrate
bonding
conductive
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PCT/CN2023/102965
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English (en)
French (fr)
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王成
白晓阳
董金文
陈嘉伟
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a method for manufacturing the same, a three-dimensional integrated circuit and a method for manufacturing the same, and an electronic device.
  • 3D IC three-dimensional integrated circuit
  • HBM high-bandwidth memory
  • 5/6G fifth or sixth-generation mobile networks
  • AI artificial intelligence
  • metal/dielectric hybrid bonding is considered to be a promising technology for achieving high interconnection density and high-performance integrated circuits.
  • HB metal/dielectric hybrid bonding
  • the embodiments of the present application provide an integrated circuit and a method for manufacturing the same, a three-dimensional integrated circuit and a method for manufacturing the same, and an electronic device, which are used to reduce the temperature of heat treatment during mixed bonding of different integrated circuits.
  • an integrated circuit comprising: a substrate, a functional layer located on the substrate, a dielectric bonding layer located on the functional layer, and a plurality of bonding patterns located in the dielectric bonding layer.
  • the bonding pattern is electrically connected to the functional layer.
  • the bonding pattern comprises a conductive portion electrically connected to the functional layer, and a metal passivation layer located on the conductive portion. The melting point of the alloy formed by the material of the conductive portion and the material of the metal passivation layer is lower than the melting point of the material of the conductive portion.
  • the integrated circuits provided in some embodiments of the present application by providing a dielectric bonding layer on a functional layer and providing a plurality of bonding patterns located in the dielectric bonding layer and electrically connected to the functional layer, can enable the integrated circuit to be interconnected with other integrated circuits by means of a hybrid bonding method, thereby improving the reliability of the three-dimensional integrated circuit formed by the interconnections.
  • the embodiment of the present application by providing a conductive part in the bonding pattern and providing a metal passivation layer covering at least a portion of the conductive part, can utilize the physical properties of the alloy layer formed by the conductive part and the metal passivation layer, that is, the property that the melting point of the alloy layer is lower than the melting point of the material of the conductive part, to reduce the bonding temperature of the bonding pattern and reduce the temperature of the heat treatment during the hybrid bonding process.
  • a metal passivation layer can be used to protect the surface of the conductive part from oxidation, reduce the impact of heat treatment on the conductive part, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer. This can improve the oxidation of the conductive part in the bonding pattern, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, thereby further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the grain boundary diffusion coefficient of the material of the conductive part in the metal passivation layer is greater than the grain boundary diffusion coefficient of the material of the metal passivation layer in the conductive part.
  • the alloy layer formed by the conductive part and the metal passivation layer can be mainly located at the top of the bonding pattern (i.e., the end away from the substrate), so that the alloy layer can be used to reduce the temperature of the heat treatment during the hybrid bonding process, and the good electrical properties of the conductive part (such as lower resistance and better anti-electromigration and thermal conductivity) can be used to ensure the electrical properties of the three-dimensional integrated circuit formed by the interconnection, and reduce the influence of the alloy layer on the electrical properties of the three-dimensional integrated circuit.
  • At least a portion of the surface of the metal passivation layer on the side away from the substrate is lower than the surface of the dielectric bonding layer on the side away from the substrate.
  • the surface of the metal passivation layer on one side away from the substrate is in an arc shape and is concave toward the substrate.
  • the surface of the metal passivation layer on one side away from the substrate 1 is in a bowl shape, a disc shape, or a groove shape. This facilitates the preparation and formation of the metal passivation layer.
  • the surface of the conductive part away from the substrate is lower than the surface of the dielectric bonding layer away from the substrate.
  • space can be reserved for the metal passivation layer located on the conductive part, ensuring that the metal passivation layer as a whole can be lower than the surface of the dielectric bonding layer away from the substrate 1 relative to the substrate, thereby providing a buffer space for the thermal expansion of the conductive part.
  • the surface of the conductive part away from the substrate is in an arc shape and is concave toward the substrate.
  • the surface of the conductive part away from the substrate is in a bowl shape, a disc shape, or a groove shape. This facilitates the preparation of the conductive part.
  • the material of the conductive part includes copper
  • the material of the metal passivation layer includes nickel, titanium, tin, silver, gold or palladium. This can ensure that the bonding temperature of the bonding pattern is reduced, or the temperature of the mixed bonding heat treatment is reduced, thereby effectively improving the oxidation of the conductive part in the bonding pattern, wafer warping, and the destruction of the thermal balance and structural reliability of the wafer.
  • the material of the dielectric bonding layer includes silicon nitride, silicon carbide, and silicon oxide.
  • the bonding pattern further includes: a seed layer and a barrier layer.
  • the seed layer surrounds the conductive portion and is located between the conductive portion and the dielectric bonding layer.
  • the barrier layer surrounds the seed layer and is located between the seed layer and the dielectric bonding layer. The barrier layer can separate the seed layer from the dielectric bonding layer, and can prevent the seed layer from directly contacting the dielectric bonding layer and causing copper diffusion, thereby improving the product reliability of the integrated circuit.
  • a method for preparing an integrated circuit comprising: sequentially forming a functional layer and a dielectric bonding layer on a substrate, the dielectric bonding layer having a plurality of hybrid bonding through holes, the hybrid bonding through holes exposing a portion of the surface of the functional layer; forming a conductive portion in the hybrid bonding through holes, the conductive portion being electrically connected to the functional layer, to obtain an initial integrated circuit; placing the initial integrated circuit in a processing gas, the processing gas comprising a metal carbonyl organic compound precursor vapor, to selectively deposit a metal passivation layer on the conductive portion.
  • the melting point of the alloy formed by the material of the conductive portion and the material of the metal passivation layer is lower than the melting point of the material of the conductive portion.
  • Some embodiments of the present application provide a method for preparing an integrated circuit.
  • the high selectivity of the metal carbonyl organic compound precursor to the conductive part and the dielectric bonding layer can be utilized to achieve highly selective deposition of heterogeneous metals.
  • the physical properties of the alloy layer formed by the conductive part and the metal passivation layer that is, the melting point of the alloy layer is lower than the melting point of the material of the conductive part, can be utilized to reduce the temperature of the heat treatment during the hybrid bonding process.
  • a metal passivation layer can be used to protect the surface of the conductive part from oxidation, reduce the impact of heat treatment on the conductive part, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer. This can improve the oxidation of the conductive part in the bonding pattern, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, thereby further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the above preparation method does not introduce organic substances and solvents. Not only does it not require complicated post-processing to remove organic matter after selective deposition to form a metal passivation layer, thus avoiding affecting the preparation efficiency of 3D ICs, it can also avoid the generation of carbon residues and impurity contamination at the interface of hybrid bonding, thus avoiding affecting the bonding effect.
  • the thickness of the metal passivation layer is in the range of 10 nm to 30 nm.
  • the material of the conductive part can have a better diffusion effect in the metal passivation layer, thereby making the alloy layer formed by the conductive part and the metal passivation layer can effectively reduce the temperature of the heat treatment.
  • the material of the conductive part includes copper
  • the metal carbonyl organic compound precursor includes Ni(CO) 4.
  • Ni(CO) 4 undergoes thermal decomposition, nickel can be precipitated on the conductive part.
  • the melting point of the copper-nickel binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in nickel is greater than the grain boundary diffusion coefficient of nickel in copper.
  • forming a conductive portion in a hybrid bonding through hole includes: forming a conductive film in the hybrid bonding through hole and on the dielectric bonding layer; performing a first grinding process on the conductive film to remove the conductive film located on the dielectric bonding layer; The conductive part is obtained by removing the conductive part and retaining the part of the conductive film located in the hybrid bonding through hole. Compared with the substrate, the conductive part is farther away from the substrate side surface than the dielectric bonding layer.
  • the grinding liquid used in the first grinding process has an ultra-high selectivity for the dielectric bonding layer and the conductive film.
  • the butterfly-shaped recessed structure can be constructed, and space can be reserved for the metal passivation layer subsequently deposited on the conductive part, ensuring that the metal passivation layer as a whole can be lower than the dielectric bonding layer away from the substrate side surface relative to the substrate, thereby providing a buffer space for the thermal expansion of the conductive part.
  • the preparation method further includes: flattening the surface of the dielectric bonding layer on the side away from the substrate. In this way, in the process of hybrid bonding of different integrated circuits, the flattening requirement for the bonding interface can be met, and a large number of diffuse bubbles can be avoided at the bonding interface of the three-dimensional integrated circuit formed by bonding, thereby improving the bonding effect.
  • a maximum distance between a surface of the conductive portion away from the substrate and a surface of the dielectric bonding layer away from the substrate is in a range of 10 nm to 30 nm.
  • the maximum distance may be 10 nm, 13 nm, 15 nm, 21 nm, 25 nm, or 30 nm.
  • the preparation method further includes: performing a second grinding process on the surface of the metal passivation layer and the dielectric bonding layer away from the substrate. Compared with the substrate, at least a portion of the surface of the metal passivation layer away from the substrate is lower than the surface of the dielectric bonding layer away from the substrate. In this way, when different integrated circuits are mixed and bonded, a certain buffer can be provided for the thermal expansion of the conductive part, which can avoid the wafer from being topped off and the separation of the bonded dielectric bonding layer 3, thereby improving the structural reliability of the three-dimensional integrated circuit formed by the interconnection.
  • the preparation method before forming a conductive film in the hybrid bonding through hole and on the dielectric bonding layer, the preparation method further includes: forming a barrier film and a seed crystal film in the hybrid bonding through hole and on the dielectric bonding layer in sequence.
  • the seed crystal film and the barrier film are also subjected to the first grinding treatment, removing the portions of the seed crystal film and the barrier film located on the dielectric bonding layer, and retaining the portions of the seed crystal film and the barrier film located in the hybrid bonding through hole, so as to obtain a seed crystal layer and a barrier layer; the seed crystal layer surrounds the conductive portion, and the barrier layer surrounds the seed crystal layer.
  • the formed barrier film can prevent the metal in the seed crystal film and the conductive film from diffusing into the dielectric bonding layer.
  • the formed seed crystal film can facilitate the subsequent formation of a conductive film by an electroplating process.
  • a method for preparing an integrated circuit comprising: sequentially forming a functional layer and a dielectric bonding layer on a substrate, the dielectric bonding layer having a plurality of hybrid bonding through holes, the hybrid bonding through holes exposing a portion of the surface of the functional layer; forming a conductive portion in the hybrid bonding through hole, the conductive portion being electrically connected to the functional layer, and the conductive portion having a surface on one side away from the substrate and lower than the surface on the one side of the dielectric bonding layer away from the substrate compared to the substrate; forming a metal passivation film on the conductive portion and the dielectric bonding layer, the thickness of the portion of the metal passivation film located on the conductive portion being greater than the thickness of the portion of the metal passivation film located on the dielectric bonding layer; performing a third grinding process on the metal passivation film, removing the portion of the metal passivation film located on the dielectric bonding layer, and retaining the portion of
  • Some embodiments of the present application provide a method for preparing an integrated circuit, by forming a conductive part in a dielectric bonding layer, and making the conductive part away from the surface of one side of the substrate, lower than the substrate and away from the surface of the side of the dielectric bonding layer, and the thickness of the portion of the subsequently formed metal passivation film located on the conductive part is greater than the thickness of the portion of the metal passivation film located on the dielectric bonding layer.
  • the portion of the metal passivation film located on the conductive part is retained to obtain a metal passivation layer, thereby achieving selective deposition of heterogeneous metals.
  • the physical properties of the alloy layer formed by the conductive part and the metal passivation layer that is, the property that the melting point of the alloy layer is lower than the melting point of the material of the conductive part, can be utilized to reduce the temperature of the heat treatment during the hybrid bonding process.
  • a metal passivation layer can be used to protect the surface of the conductive part from oxidation, reduce the impact of heat treatment on the conductive part, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer. This can improve the oxidation of the conductive part in the bonding pattern, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, thereby further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the above preparation method does not introduce organic substances and solvents. Not only does it not require complicated post-processing to remove organic matter after selective deposition to form a metal passivation layer, thus avoiding affecting the preparation efficiency of 3D ICs, it can also avoid the generation of carbon residues and impurity contamination at the interface of hybrid bonding, thus avoiding affecting the bonding effect.
  • the material of the conductive part includes copper
  • the material of the metal passivation layer includes titanium, tin, silver, gold or palladium.
  • the conductive part is formed by copper
  • the metal passivation layer is formed by titanium, tin, silver, gold or palladium, so that the conductive part and the metal passivation layer are
  • the alloy layer formed by the passivation layer is located on the top of the bonding pattern, and the temperature of the heat treatment can be reduced by using the alloy layer located on the top of the bonding pattern.
  • the thickness of a portion of the metal passivation film located on the conductive portion is in the range of 10 nm to 60 nm.
  • the portion remaining on the conductive portion still has a certain thickness, and then during the heat treatment process of mixed bonding of different integrated circuits, the material of the conductive portion has a better diffusion effect in the metal passivation layer, and then the alloy layer formed by the conductive portion and the metal passivation layer can effectively reduce the temperature of the heat treatment.
  • a conductive portion is formed in a hybrid bonding through hole, including: forming a conductive film in the hybrid bonding through hole and on the dielectric bonding layer; performing a first grinding process on the conductive film to remove the portion of the conductive film located on the dielectric bonding layer, and retaining the portion of the conductive film located in the hybrid bonding through hole, thereby obtaining the conductive portion.
  • the grinding liquid used in the first grinding process has an ultra-high selectivity ratio for the dielectric bonding layer and the conductive film.
  • a butterfly-shaped recessed structure can be constructed, thereby reserving space for a metal passivation layer subsequently deposited on the conductive portion, ensuring that the metal passivation layer as a whole can be lower than the surface of the dielectric bonding layer on the side away from the substrate relative to the substrate, thereby providing a buffer space for the thermal expansion of the conductive portion.
  • the preparation method further includes: flattening the surface of the dielectric bonding layer on the side away from the substrate. In this way, in the process of hybrid bonding of different integrated circuits, the flattening requirement for the bonding interface can be met, and a large number of diffuse bubbles can be avoided at the bonding interface of the three-dimensional integrated circuit formed by bonding, thereby improving the bonding effect.
  • a maximum distance between a surface of the conductive portion away from the substrate and a surface of the dielectric bonding layer away from the substrate is in a range of 20 nm to 70 nm.
  • the maximum distance may be 20 nm, 30 nm, 35 nm, 43 nm, 59 nm, or 70 nm.
  • forming a metal passivation film on the conductive part and the dielectric bonding layer includes: using an ionized physical vapor deposition process to deposit a metal passivation material on the conductive part and the dielectric bonding layer to form a metal passivation film.
  • the metal passivation film formed by the ionized physical vapor deposition process can satisfy the requirement that the thickness of the portion located on the conductive part is greater than the thickness of the portion located on the dielectric bonding layer, so that after the metal passivation film is subjected to the third grinding process, the portion of the metal passivation film located on the conductive part can be retained, thereby achieving selective deposition of heterogeneous metals.
  • the preparation method before forming the first conductive film in the hybrid bonding through hole and on the dielectric bonding layer, the preparation method further includes: forming a barrier film and a seed crystal film in the hybrid bonding through hole and on the dielectric bonding layer in sequence.
  • the seed crystal film and the barrier film are also subjected to the first grinding treatment, removing the portions of the seed crystal film and the barrier film located on the dielectric bonding layer, retaining the portions of the seed crystal film and the barrier film located in the hybrid bonding through hole, and obtaining the seed crystal layer and the barrier layer.
  • the seed crystal layer surrounds the conductive portion and the metal passivation layer
  • the barrier layer surrounds the seed crystal layer.
  • the formed barrier film can prevent the metal in the seed crystal film and the conductive film from diffusing into the dielectric bonding layer.
  • the formed seed crystal film can facilitate the subsequent formation of the conductive film by electroplating process.
  • a three-dimensional integrated circuit comprising: a first integrated circuit and a second integrated circuit arranged opposite to each other.
  • the first integrated circuit and the second integrated circuit are integrated circuits as described in any embodiment of the first aspect.
  • the bonding pattern in the first integrated circuit is bonded to the bonding pattern in the second integrated circuit, and the dielectric bonding layer of the first integrated circuit is bonded to the dielectric bonding layer of the second integrated circuit.
  • the material of either the dielectric bonding layer of the first integrated circuit or the dielectric bonding layer of the second integrated circuit includes silicon nitride or silicon carbide.
  • the orthographic projections of the bonding pattern of the first integrated circuit and the bonding pattern of the second integrated circuit on the reference plane overlap or partially overlap.
  • the reference plane is a surface of a side of the substrate of the first integrated circuit away from the second integrated circuit. In this way, the alignment accuracy of the first integrated circuit and the second integrated circuit can be effectively reduced, and the difficulty of bonding the first integrated circuit and the second integrated circuit can be reduced.
  • the material of the dielectric bonding layer of the first integrated circuit includes silicon nitride or silicon carbide
  • the material of the dielectric bonding layer of the second integrated circuit includes silicon oxide.
  • the orthographic projection of the bonding pattern of the first integrated circuit on the reference plane is located within the orthographic projection range of the bonding pattern of the second integrated circuit on the reference plane.
  • the reference plane is a side surface of the substrate of the first integrated circuit away from the second integrated circuit.
  • a method for preparing a three-dimensional integrated circuit comprising: providing a first integrated circuit and a third integrated circuit; Two integrated circuits, the first integrated circuit and the second integrated circuit are the integrated circuits as described in any embodiment of the first aspect; the first integrated circuit and the second integrated circuit are aligned and bonded; the bonded first integrated circuit and the second integrated circuit are heat treated at a temperature ranging from 120°C to 400°C.
  • an electronic device comprising the three-dimensional integrated circuit as described in any embodiment of the fourth aspect.
  • FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG2 is a partial structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG3 is a structural diagram of a three-dimensional integrated circuit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a solid-liquid diffusion bonding provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of an anisotropic conductive film/paste bonding provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of a hybrid bonding provided in an embodiment of the present application.
  • FIG7 is a structural diagram of an integrated circuit provided in an embodiment of the present application.
  • FIG8 is a structural diagram of another integrated circuit provided in an embodiment of the present application.
  • FIG9 is a flow chart of a method for preparing an integrated circuit provided in an embodiment of the present application.
  • 10a to 10f are diagrams showing steps for preparing an integrated circuit according to an embodiment of the present application.
  • FIG. 11a to 11e are diagrams showing another step of preparing an integrated circuit provided in an embodiment of the present application.
  • FIG12 is a flow chart of another method for preparing an integrated circuit provided in an embodiment of the present application.
  • FIGS. 13a to 13g are diagrams showing another step of preparing an integrated circuit provided in an embodiment of the present application.
  • FIG14 is a structural diagram of a film layer formed by a physical vapor deposition process provided in an embodiment of the present application.
  • FIG15 is a structural diagram of a film layer formed by an ionized physical vapor deposition process provided in an embodiment of the present application.
  • FIG16 is a schematic diagram of performing a third grinding process on a metal passivation film according to an embodiment of the present application.
  • FIG17 is a structural diagram of a three-dimensional integrated circuit provided in an embodiment of the present application.
  • FIG18 is a structural diagram of another three-dimensional integrated circuit provided in an embodiment of the present application.
  • FIG19 is a structural diagram of another three-dimensional integrated circuit provided in an embodiment of the present application.
  • FIG20 is a flow chart of a method for preparing a three-dimensional integrated circuit provided in an embodiment of the present application.
  • 21a to 21b are diagrams showing steps for preparing a three-dimensional integrated circuit according to an embodiment of the present application.
  • plural means two or more than two.
  • At least one item or similar expressions refers to any combination of these items, including any combination of single items or plural items.
  • at least one item of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • the words “first”, “second” and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words “first”, “second” and the like do not limit the quantity and execution order, and the words “first”, “second” and the like do not necessarily limit the difference.
  • the words “exemplary” or “for example” are used to indicate examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as “exemplary” or “for example” is intended to present related concepts in a concrete manner for easy understanding.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the embodiment of the present application provides an electronic device.
  • the electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and/or a smart city device.
  • PDA personal digital assistant
  • AR augmented reality
  • VR virtual reality
  • AI artificial intelligence
  • smart wearable device e.g., a smart watch, a smart bracelet
  • an in-vehicle device e.g., a smart home device and/or a smart city device.
  • the embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.
  • FIG1 is a structural diagram of an electronic device in some embodiments.
  • the electronic device 1000 mainly includes a cover plate 11, a display screen 12, a middle frame 13, and a rear shell 14.
  • the rear shell 14 and the display screen 12 are respectively located on both sides of the middle frame 13, and the middle frame 13 and the display screen 12 are arranged in the rear shell 14, the cover plate 11 is arranged on a side of the display screen 12 away from the middle frame 13, and the display surface of the display screen 12 faces the cover plate 11.
  • the display screen 12 may be a liquid crystal display (LCD).
  • the liquid crystal display includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is arranged between the cover plate 11 and the backlight module.
  • the backlight module is used to provide a light source for the liquid crystal display panel.
  • the display screen 12 may also be an organic light emitting diode (OLED) display screen, a quantum dot light emitting diode (QLED) display screen, a mini light emitting diode (Mini LED) display screen or a micro light emitting diode (Micro LED) display screen. Since the OLED display screen, QLED display screen, Mini LED display screen, Micro LED display screen, etc. are all self-luminous display screens, there is no need to set a backlight module.
  • the middle frame 13 includes a carrier plate 131 and a frame 132 surrounding the carrier plate 131.
  • the electronic device 1000 also includes a circuit board 15, a battery, a camera and other electronic components disposed on the carrier plate 131.
  • the electronic device 1000 may further include a three-dimensional integrated circuit 16 disposed on the circuit board 15 , and the three-dimensional integrated circuit 16 is electrically connected to the circuit board 15 .
  • the electronic device 1000 further includes a first connector 17 disposed between the circuit board 15 and the three-dimensional integrated circuit 16, and the three-dimensional integrated circuit 16 is electrically connected to the circuit board 15 via the first connector 17.
  • the first connector 17 may be, for example, a ball grid array (BGA).
  • the three-dimensional integrated circuit 16 includes a plurality of integrated circuits 100 stacked in sequence, a packaging substrate 18, and a second connector 19 disposed between the plurality of integrated circuits 100 and the packaging substrate 18, and the plurality of integrated circuits 100 are electrically connected to the packaging substrate 18 through the second connector 19.
  • the second connector 19 may be, for example, a controlled collapse chip connection bump (C4 bump).
  • the number of integrated circuits 100 may be two, three, four or even more.
  • FIG. 2 schematically shows two integrated circuits 100.
  • stacking multiple integrated circuits 100 in sequence has more advantages than setting up multiple integrated circuits separately, such as being able to obtain higher bandwidth, thereby obtaining higher storage or computing density, etc., and can also reduce the package size and improve the integration of the chip.
  • each integrated circuit 100 includes a substrate 1 and a The functional layer 2 on the substrate 1 can enable the integrated circuit 100 to realize its own functions during operation, such as logic calculation functions or storage functions, etc.
  • the functional layer 2 includes but is not limited to functional devices, circuit structures, interconnected metal lines, and dielectric layers, etc.
  • the three-dimensional integrated circuit 16 includes two integrated circuits 100 that are bonded and electrically connected, wherein the functional layer 2 of one integrated circuit 100 enables the integrated circuit 100 to implement a storage function, and accordingly, the integrated circuit 100 is a memory chip, and the functional layer 2 of the other integrated circuit 100 enables the integrated circuit 100 to implement a logical computing function, and accordingly, the integrated circuit 100 is a processor chip.
  • the material of the substrate 1 of the integrated circuit 100 may include one or more of silicon (Si), germanium (Ge), gallium nitride (GaN), gallium arsenide (GaAs) or other semiconductor materials.
  • the material of the substrate 1 may also be glass, organic materials, etc.
  • the integrated circuit 100 in the three-dimensional integrated circuit 16 may refer to a wafer having a functional layer 2 formed thereon, or may refer to a bare chip (die) obtained by cutting a wafer having a functional layer 2 formed thereon, and a bare chip may also be referred to as a grain or particle.
  • the integrated circuit 100 may also be a packaged chip obtained by packaging a bare chip.
  • the plurality of integrated circuits 100 in the above-mentioned three-dimensional integrated circuit 16 may all be bare chips or chips obtained by packaging bare chips. In other embodiments, the plurality of integrated circuits 100 in the above-mentioned three-dimensional integrated circuit 16 may all be wafers.
  • the plurality of integrated circuits 100 in the above-mentioned three-dimensional integrated circuit 16 may be a part of the integrated circuits 100 being wafers, and a part of the integrated circuits 100 being bare chips and/or chips obtained by packaging bare chips.
  • FIG4 (a) shows a structure of an integrated circuit interconnected by solid-liquid diffusion bonding (SLID Bonding), with a redistribution layer (RDL) 1' and solder (solder) provided on the functional layer.
  • FIG4 (b) shows an ideal bonding result after two integrated circuits are bonded, with dielectric underfilled between the conductive part in the redistribution layer 1' and the solder 2'.
  • FIG4 (c) shows a problem (finer pitch bonding concern) in the case of finer pitch bonding, for example, the narrow gap between some conductive parts in the redistribution layer 1' is not filled with dielectric, and some solders 2' squeeze each other (squeeze).
  • FIG5(a) shows a structure of an integrated circuit interconnected by anisotropic conductive film bonding (ACF Bonding), with a rewiring layer 1' and anisotropic conductive film 3' provided on the functional layer.
  • FIG5(b) shows an ideal bonding result after two integrated circuits are bonded, with the conductive particles (CPs) in the anisotropic conductive film 3' being dispersed, and the rewiring layers 1' in the two integrated circuits being filled with conductive particles.
  • FIG5(a) shows an enlarged view of the conductive particles, which include a polymer and a conductive layer (conductive layer) wrapping the polymer.
  • FIG5(c) shows problems that occur in the case of finer pitch bonding, for example, the bonding filling (Bonding filling) between some conductive parts in the rewiring layer 1' fails, and no conductive particles are filled, so that no electrical connection is formed; or the conductive particles aggregate, and the adjacent conductive parts in the rewiring layer 1' form a short circuit (leakage) through the aggregated conductive particles.
  • the bonding filling Biting filling
  • FIG6 (a) shows a structure of an integrated circuit interconnected by hybrid bonding, where a rewiring layer 1' and a dielectric bonding layer 4' are provided on the functional layer.
  • FIG6 (b) shows an ideal bonding result after two integrated circuits are bonded, where the rewiring layers 1' are bonded to the rewiring layers 1', and the dielectric bonding layers 4' are bonded to the dielectric bonding layers 4'.
  • the hybrid bonding method can make the three-dimensional integrated circuit have better interconnection effect.
  • FIG7 and FIG8 respectively illustrate the structure of an integrated circuit.
  • FIG7 and FIG8 are both illustrated by taking the example that the functional layer 2 includes an electronic device 21 and an interconnection layer 22 located on a side of the electronic device away from the substrate 1.
  • the electronic device 21 is electrically connected to the interconnection layer 22.
  • the electronic device 21 includes, but is not limited to, a transistor, a capacitor, an inductor, etc.
  • the transistor includes a gate, a source and a drain.
  • the interconnection layer 22 includes a plurality of conductive layers.
  • four conductive layers are shown schematically in Figures 7 and 8.
  • Some of the conductive layers are provided with metal traces, and some of the conductive layers are provided with conductive patterns, which are used to connect electronic devices and corresponding metal traces, or to connect traces in different conductive layers.
  • the integrated circuit 100 further includes: a dielectric bonding layer 3 and a plurality of bonding patterns 4.
  • the dielectric bonding layer 3 is located on the functional layer 2.
  • the functional layer 2 includes an electronic device 21 and an interconnection layer 22
  • the dielectric bonding layer 3 is located on a side of the interconnection layer 22 away from the electronic device 21.
  • the plurality of bonding patterns 4 are located in the dielectric bonding layer 3 and are substantially not protruded from a surface of the dielectric bonding layer 3 on a side away from the substrate 1. At least some of the plurality of bonding patterns 4 will penetrate the dielectric bonding layer 3 and extend to the functional layer 2, and be electrically connected to the functional layer 2.
  • the bonding pattern 4 contacts the metal trace or conductive pattern in the interconnection layer 22 to form an electrical connection.
  • the arrangement of the plurality of bonding patterns 4 can be selected and set according to actual needs.
  • the plurality of bonding patterns 4 are arranged in an array, and there is a smaller spacing between two adjacent bonding patterns 4 to achieve finer spacing interconnection.
  • the bonding pattern 4 includes a conductive portion 41, and the conductive portion 41 is electrically connected to the functional layer 2.
  • the conductive portion 41 is made of a metal material, which is relatively active, has a small resistance, and has good anti-electromigration and thermal conductivity.
  • the bonding pattern 4 further includes a metal passivation layer 42, which is located on the conductive portion 41, that is, the metal passivation layer 42 is located on the surface of the conductive portion 41 on one side away from the substrate 1.
  • the metal passivation layer 42 covers the conductive portion 41 or covers a portion of the conductive portion 41, and is in contact with the conductive portion 41. That is, the conductive portion 41 and the metal passivation layer 42 are arranged in sequence in a direction perpendicular to and away from the substrate 1, and the orthographic projection of the conductive portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the metal passivation layer 42 on the substrate 1.
  • the thickness (or height) of the conductive portion 41 is greater than the thickness of the metal passivation layer 42 .
  • the melting point of the alloy formed by the material of the conductive part 41 and the material of the metal passivation layer 42 is lower than the melting point of the material of the conductive part 41 .
  • the conductive part 41 is in contact with the metal passivation layer 42. Under the action of heat, the material of the conductive part 41 will diffuse into the metal passivation layer 42, and the material of the metal passivation layer 42 will diffuse into the conductive part 41, so that an alloy layer can be formed on the side of the bonding pattern 4 away from the substrate 1. Since the melting point of the alloy composed of the material of the conductive part 41 and the material of the metal passivation layer 42 is lower than the melting point of the material of the conductive part 41, in the process of mixed bonding of different (for example, two) integrated circuits 100, the lower melting point of the alloy layer can be utilized to achieve mutual melting and bonding of the bonding pattern 4 at a lower heat treatment temperature. On this basis, the oxidation of the conductive part 41 in the bonding pattern 4, the warping of the wafer, the destruction of the thermal balance and structural reliability of the wafer, and other problems can also be improved.
  • the integrated circuit 100 provided in some embodiments of the present application, by providing a dielectric bonding layer 3 on the functional layer 2, and providing a plurality of bonding patterns 4 located in the dielectric bonding layer 3 and electrically connected to the functional layer 2, can enable the integrated circuit 100 to form an interconnection with other integrated circuits 100 by means of a hybrid bonding method, thereby improving the reliability of the three-dimensional integrated circuit formed by the interconnection.
  • the embodiment of the present application by providing a conductive part 41 in the bonding pattern 4 and providing a metal passivation layer 42 covering at least a portion of the conductive part 41, can utilize the physical properties of the alloy layer formed by the conductive part 41 and the metal passivation layer 42, that is, the property that the melting point of the alloy layer is lower than the melting point of the material of the conductive part 41, to reduce the bonding temperature of the bonding pattern 4 and reduce the temperature of the heat treatment during the hybrid bonding process.
  • the metal passivation layer 42 can be used to provide anti-oxidation protection for the surface of the conductive part 41, reduce the impact of heat treatment on the conductive part 41, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer, thereby improving the oxidation of the conductive part 41 in the bonding pattern 4, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, and further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the grain boundary diffusion coefficient of the material of the conductive part 41 in the metal passivation layer 42 is greater than the grain boundary diffusion coefficient of the material of the metal passivation layer 42 in the conductive part 41. That is, the material of the conductive part 41 diffuses faster in the bulk phase of the metal passivation layer 42, and the material of the metal passivation layer 42 diffuses slower in the bulk phase of the conductive part 41.
  • the alloy layer formed by the conductive part 41 and the metal passivation layer 42 is mainly located at the top of the bonding pattern 4 (ie, the end away from the substrate 1 ), and the material of the metal passivation layer 42 diffuses only to the top of the conductive part 41 .
  • the bonding interface of two bonded integrated circuits 100 is sliced, and the TEM (transmission electron microscope) of the cut surface is used to analyze the bonding interface of the two bonded integrated circuits 100.
  • TEM transmission electron microscope
  • EDX energy dispersive X-Ray spectroscopy
  • the alloy layer can be used to reduce the temperature of heat treatment during the hybrid bonding process, and the good electrical properties of the conductive part 41 (such as smaller resistance and better resistance to electromigration and thermal conductivity) can be used to ensure the electrical properties of the three-dimensional integrated circuit formed by interconnection and reduce the influence of the alloy layer on the electrical properties of the three-dimensional integrated circuit.
  • the surface of the side of the dielectric bonding layer 3 away from the substrate 1 is a flat surface or a substantially flat surface. Compared with the substrate 1, at least a portion of the surface of the side of the metal passivation layer 42 away from the substrate 1 is lower than the surface of the side of the dielectric bonding layer 3 away from the substrate 1.
  • the entire surface of the side of the metal passivation layer 42 away from the substrate 1 is lower than the surface of the side of the dielectric bonding layer 3 away from the substrate 1; or, the boundary of the surface of the side of the metal passivation layer 42 away from the substrate 1 is flush with the surface of the side of the dielectric bonding layer 3 away from the substrate 1, and the rest of the surface of the side of the metal passivation layer 42 away from the substrate 1 is lower than the surface of the side of the dielectric bonding layer 3 away from the substrate 1.
  • a certain space is formed between the surface of the metal passivation layer 42 away from the substrate 1 and the horizontal plane where the surface of the dielectric bonding layer 3 away from the substrate 1 is located.
  • the above space can be used to provide a certain buffer for the thermal expansion of the conductive portion 41, which can avoid wafer top cracking and separation of the bonded dielectric bonding layer 3, thereby improving the structural reliability of the three-dimensional integrated circuit formed by interconnection.
  • the surface of the metal passivation layer 42 on one side away from the substrate 1 is in an arc shape and is concave toward the direction close to the substrate 1 .
  • the surface of the metal passivation layer 42 on one side away from the substrate 1 is in a bowl, disc or groove shape, which facilitates the preparation and formation of the metal passivation layer 42 .
  • a surface of the conductive portion 41 on one side away from the substrate 1 is lower than a surface of the dielectric bonding layer 3 on one side away from the substrate 1 .
  • a certain distance exists between a side surface of the conductive portion 41 away from the substrate 1 and a side surface of the dielectric bonding layer 3 away from the substrate 1 .
  • a surface of the conductive portion 41 on a side away from the substrate 1 is in an arc shape and is concave toward the direction close to the substrate 1 .
  • the surface of the conductive part 41 on one side away from the substrate 1 is in a bowl-shaped, disc-shaped or groove-shaped shape, which facilitates the preparation and formation of the conductive part 41 .
  • the material of the conductive portion 41 includes copper
  • the material of the metal passivation layer 42 includes nickel, titanium, tin, silver, gold, or palladium.
  • the conductive part 41 and the metal passivation layer 42 can diffuse on the top of the bonding pattern 4 to form a copper-nickel binary alloy, a copper-titanium binary alloy, a copper-tin binary alloy, a copper-silver binary alloy, a copper-gold binary alloy or a copper-palladium binary alloy, etc., and the melting points of the various binary alloys are all lower than the melting point of the conductive part 41. In this way, it can ensure that the bonding temperature of the bonding pattern 4 is reduced, or the temperature of the mixed bonding heat treatment is reduced, and then the oxidation of the conductive part 41 in the bonding pattern 4, the wafer warping, the thermal balance of the wafer, and the destruction of the structural reliability can be effectively improved.
  • the material of the dielectric bonding layer 3 includes, but is not limited to, silicon nitride ( SiNx ), silicon carbide nitride (SiCN), and silicon oxide ( SiO2 ).
  • the bonding pattern 4 further includes: a seed layer 43 and a barrier layer 44.
  • the seed layer 43 surrounds the conductive portion 41 and is located between the conductive portion 41 and the dielectric bonding layer 3.
  • the barrier layer 44 surrounds the seed layer 43 and is located between the seed layer 43 and the dielectric bonding layer 3.
  • the seed layer 43 surrounds the side of the conductive portion 41 and contacts the bottom of the conductive portion 41.
  • the barrier layer 44 surrounds the side of the seed layer 43 and contacts the bottom of the seed layer 43.
  • the conductive portion 41 is electrically connected to the functional layer 2 through the seed layer 43 and the barrier layer 44 in sequence.
  • the material of the seed layer 43 includes copper, which can be used as the base metal to be plated. During the electroplating process, copper grows on the surface of the seed layer 43 to form the conductive part 41. Generally, the average diameter of the copper grains in the seed layer 43 is smaller than the average diameter of the copper grains in the conductive part 41.
  • the barrier layer 44 can adhere the seed layer 43 to the dielectric bonding layer 3, thereby ensuring a stable connection between the seed layer 43 and the conductive portion 41 and the dielectric bonding layer 3.
  • the barrier layer 44 can separate the seed layer 43 from the dielectric bonding layer 3, thereby preventing the seed layer 43 from directly contacting the dielectric bonding layer 3 and causing copper diffusion, thereby improving the product reliability of the integrated circuit 100.
  • the material of the barrier layer 44 includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), so that the barrier layer 44 has a barrier force.
  • the inventor of the present application has found through research that the solution of depositing heterogeneous metals on copper surface has been realized in some fields, but it is difficult to realize the selective construction of heterogeneous metals due to the limitation of preparation process, so it is difficult to apply it in hybrid bonding.
  • the current technical solution for selective deposition of heterogeneous metals in specific areas mainly adopts the area-selective atomic layer deposition (AS-ALD) process, that is, mainly passivating or activating specific areas by self-assembly monolayers (SAMs) and polymer methods, and then making the precursor have different reactivity with these areas from the original surface.
  • AS-ALD area-selective atomic layer deposition
  • the selective deposition process involves the use of trimethoxysilyl propyl diethylenetriamine (DETA) as a SAMs precursor, p-dimethylaminobenzaldehyde (DMAB) and ammonium chloride as palladium metal reducing agents, and ethylenediamine (EDA) as a complexing agent.
  • DETA trimethoxysilyl propyl diethylenetriamine
  • DMAB p-dimethylaminobenzaldehyde
  • EDA ethylenediamine
  • FIG. 9 is a flow chart of preparing an integrated circuit in some embodiments
  • FIG. 10a to FIG. 10f are diagrams of the steps of preparing an integrated circuit in some embodiments.
  • the above preparation method includes: S110 to S130.
  • a functional layer 2 and a dielectric bonding layer 3 are sequentially formed on a substrate 1 , wherein the dielectric bonding layer 3 has a plurality of hybrid bonding through holes G, and the hybrid bonding through holes G expose a portion of the surface of the functional layer 2 .
  • the material of the substrate 1, the structure of the functional layer 2, and the structure and material of the dielectric bonding layer 3 can be found in the above description and will not be described in detail here.
  • sequentially forming a functional layer 2 and a dielectric bonding layer 3 on the substrate 1 includes: as shown in FIG. 11a, providing a substrate 1, and cleaning the substrate 1 by using an RCA standard cleaning method (RCA clean); as shown in FIG. 11b, forming a functional layer 2 on the substrate 1 by using processes including but not limited to a deposition process, a photolithography process, a dry etching process, etc.; as shown in FIG. 11c, depositing a dielectric film 3a on the functional layer 2 by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; as shown in FIG.
  • PECVD Laser Deposition
  • the embodiment of the present application may also adopt a dual damascene process to form the hybrid bonding through hole G, wherein, as shown in FIG10a, the hybrid bonding through hole G includes a through hole close to the functional layer 2, and a groove connected to the through hole and located on the side of the through hole away from the functional layer 2.
  • the embodiment of the present application is schematically described by taking the hybrid bonding through hole G shown in FIG10a as an example.
  • a conductive portion 41 is formed in the hybrid bonding via G, and the conductive portion 41 is electrically connected to the functional layer 2, thereby obtaining an initial integrated circuit.
  • the embodiments of the present application may form the conductive portion 41 by processes including but not limited to electrochemical plating (ECP) and chemical-mechanical polishing (CMP).
  • ECP electrochemical plating
  • CMP chemical-mechanical polishing
  • the initial integrated circuit is placed in a processing gas, the processing gas comprising a metal carbonyl organic compound precursor vapor, to selectively deposit a metal passivation layer 42 on the conductive portion 41.
  • the processing gas comprising a metal carbonyl organic compound precursor vapor
  • the melting point of the alloy that constitutes the material of the layer 42 is lower than the melting point of the material of the conductive portion 41 .
  • the embodiments of the present application may place the above-mentioned processing gas in a processing chamber of related equipment, such as a chemical vapor deposition (CVD) equipment, and the above-mentioned metal carbonyl organic compound precursor may be called a CVD reaction precursor.
  • a processing chamber of related equipment such as a chemical vapor deposition (CVD) equipment
  • CVD reaction precursor the above-mentioned metal carbonyl organic compound precursor
  • the adsorption capacity of the conductive part 41 for carbonyl groups is greater than the adsorption capacity of the dielectric bonding layer 3 for carbonyl groups.
  • the above-mentioned metal carbonyl organic compound precursor will undergo thermal decomposition (or it can be understood as an oxidation-reduction reaction), and the metal in the metal carbonyl organic compound precursor will precipitate on the surface of the conductive part 41 away from the substrate 1, thereby achieving highly selective deposition of heterogeneous metals.
  • the metal deposited on the surface of the conductive part 41 away from the substrate 1 constitutes a metal passivation layer 42.
  • heat treatment for example, annealing
  • the material of the conductive part 41 will diffuse into the metal passivation layer 42 under the action of heat, so that an alloy layer is formed on the side of the bonding pattern 4 away from the substrate 1. Since the melting point of the alloy formed by the material of the conductive part 41 and the material of the metal passivation layer 42 is lower than the melting point of the material of the conductive part 41, the mutual melting and bonding of the bonding pattern 4 can be achieved at a lower heat treatment temperature.
  • some embodiments of the present application provide a method for preparing an integrated circuit, by placing the above-mentioned processed integrated circuit in a vapor including a metal carbonyl organic compound precursor, the metal carbonyl organic compound precursor can be used as a CVD reaction precursor, and the high selectivity of the metal carbonyl organic compound precursor to the conductive part 41 and the dielectric bonding layer 3 can be utilized to achieve highly selective deposition of heterogeneous metals, and then the physical properties of the alloy layer formed by the conductive part 41 and the metal passivation layer 42, that is, the melting point of the alloy layer is lower than the melting point of the material of the conductive part 41, can be utilized to reduce the temperature of the heat treatment during the hybrid bonding process.
  • the metal passivation layer 42 can be used to provide anti-oxidation protection for the surface of the conductive part 41, reduce the impact of heat treatment on the conductive part 41, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer, thereby improving the oxidation of the conductive part 41 in the bonding pattern 4, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, and further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the above preparation method does not introduce organic substances and solvents. Not only does it not require complicated post-processing to remove organic matter after selective deposition to form the metal passivation layer 42, thereby avoiding affecting the preparation efficiency of 3D ICs, it can also avoid the generation of carbon residues and impurity contamination at the interface of the hybrid bonding, thereby avoiding affecting the bonding effect.
  • the above preparation method can realize the entire back end of line (BEOL) process, and the process cost adopted by the above preparation method is low and the efficiency is high.
  • BEOL back end of line
  • the thickness of the metal passivation layer 42 is in the range of 10 nm to 30 nm.
  • the thickness refers to the maximum size or average size of the metal passivation layer 42 in the direction perpendicular to the substrate 1 .
  • the thickness of the metal passivation layer 42 is 10 nm, 12 nm, 16 nm, 21 nm, 25 nm, 30 nm, etc.
  • the material of the conductive part 41 can have a better diffusion effect in the metal passivation layer 42, so that the alloy layer formed by the conductive part 41 and the metal passivation layer 42 can effectively reduce the heat treatment temperature.
  • the thickness of the metal passivation layer 42 selectively deposited on the conductive part 41 can be adjusted. It is understandable that the material of the conductive part 41 has different grain boundary diffusion coefficients in different metals. Accordingly, the thickness of the metal passivation layer 42 selectively deposited can be the same or different depending on the metal in the metal carbonyl organic compound precursor, and can be selected and set as needed.
  • the material of the conductive portion 41 includes copper, and the metal carbonyl organic compound precursor includes but is not limited to Ni(CO) 4 (nickel tetracarbonyl).
  • Ni(CO) 4 is basically deposited on copper and thermally decomposed under high temperature environment, and then Ni (nickel) is precipitated on the surface of the conductive part 41 away from the substrate 1, achieving highly selective deposition of heterogeneous metal nickel.
  • the equation for thermal decomposition of Ni(CO) 4 is: Ni(CO) 4 ⁇ Ni+4CO.
  • the melting point of the copper-nickel binary alloy is lower than that of copper, and the grain boundary diffusion coefficient of copper in nickel is greater than that of nickel in copper.
  • metal carbonyl organic compound precursor is not limited to Ni(CO) 4 , and any metal carbonyl organic compound precursor and metal target material suitable for PVD equipment or CVD equipment can be applied to the above preparation method.
  • forming a conductive portion 41 in the hybrid bonding via G includes: S121 - S122 .
  • a conductive film 41 a is formed in the hybrid bonding via G and on the dielectric bonding layer 3 .
  • the above-mentioned “on the dielectric bonding layer 3 ” refers to the surface of the dielectric bonding layer 3 on the side away from the substrate 1 .
  • the embodiment of the present application may use, but is not limited to, an ECP process to form the conductive film 41a.
  • the surface of the conductive film 41a on the side away from the substrate 1 is, for example, a relatively flat surface.
  • the conductive film 41a is subjected to a first grinding process to remove the portion of the conductive film 41a located on the dielectric bonding layer 3, and retain the portion of the conductive film 41a located in the hybrid bonding through hole G, thereby obtaining the conductive portion 41.
  • the surface of the conductive portion 41 on one side away from the substrate 1 is lower than the surface of the dielectric bonding layer 3 on one side away from the substrate 1.
  • the embodiment of the present application can use a CMP process to perform a first grinding process on the conductive film 41a, and the CMP grinding liquid used has an ultra-high selectivity ratio for the dielectric bonding layer 3 and the conductive film 41a.
  • the entire surface of the conductive film 41a is ground, so the portion of the conductive film 41a located on the hybrid bonding through hole G is also removed, and the portion retained in the hybrid bonding through hole G is lower than the dielectric bonding layer 3 compared to the substrate 1.
  • the morphology of the conductive part 41 is, for example, as shown in FIG10e , where the surface of the conductive part 41 away from the substrate 1 is in an arc shape and is concave toward the substrate 1.
  • This concave can also be called a butterfly-shaped concave.
  • a butterfly-shaped recessed structure can be constructed, thereby reserving space for the metal passivation layer 42 subsequently deposited on the conductive part 41, ensuring that the metal passivation layer 42 as a whole can be lower than the surface of the dielectric bonding layer 3 on the side away from the substrate 1 relative to the substrate 1, thereby providing a buffer space for the thermal expansion of the conductive part 41.
  • a maximum distance between a surface of the conductive portion 41 away from the substrate 1 and a surface of the dielectric bonding layer 3 away from the substrate 1 ranges from 10 nm to 30 nm.
  • the maximum spacing may be 10 nm, 13 nm, 15 nm, 21 nm, 25 nm or 30 nm, etc.
  • the preparation method further includes: S123.
  • the embodiment of the present application may use a CMP process to grind and polish the surface of the dielectric bonding layer 3 away from the substrate 1.
  • the surface roughness of the dielectric bonding layer 3 may be increased.
  • the surface roughness of the dielectric bonding layer 3 can be reduced, and the flatness of the surface of the dielectric bonding layer 3 away from the substrate 1 can be improved.
  • the flattening requirement for the bonding interface can be met, avoiding the appearance of a large number of diffuse bubbles at the bonding interface of the three-dimensional integrated circuit formed by bonding, thereby improving the bonding effect.
  • the CMP polishing liquid used in the above S123 may be the same as or different from the CMP polishing liquid used in the above S122.
  • the surface of the side of the dielectric bonding layer 3 away from the substrate 1 can be planarized by adjusting parameters such as pressure.
  • the selection ratio of the two can be different to achieve planarization of the surface of the side of the dielectric bonding layer 3 away from the substrate 1.
  • the preparation method further includes: S140.
  • the metal passivation layer 42 and the dielectric bonding layer 3 may be secondly ground by a CMP process.
  • the second grinding process may be referred to as a light polishing process.
  • the surface roughness of the metal passivation layer 42 is reduced.
  • the morphology of the metal passivation layer 42 is shown in FIG. 10f, where the surface of the metal passivation layer 42 away from the substrate 1 is in an arc shape and is concave toward the substrate 1. This concave can also be called a butterfly concave.
  • the above-mentioned recess can be used to provide a certain buffer for the thermal expansion of the conductive part 41, which can avoid wafer top cracking and separation of the bonded dielectric bonding layer 3, thereby improving the structural reliability of the three-dimensional integrated circuit formed by interconnection.
  • the side surface of the metal passivation layer 42 formed selectively away from the substrate 1 is lower than the side surface of the dielectric bonding layer 3 away from the substrate 1 relative to the substrate 1, so that the metal passivation layer 42 is in a concave state.
  • the depth of the concave can be deepened, so as to further provide a buffer space for the thermal expansion of the conductive part 41 when different integrated circuits are mixed and bonded.
  • the preparation method before the above S121, that is, before forming the conductive film 41a in the hybrid bonding via G and on the dielectric bonding layer 3, as shown in FIG10b and FIG10c, the preparation method further includes: sequentially forming a barrier film 44a and a seed crystal film 43a in the hybrid bonding via G and on the dielectric bonding layer 3.
  • the conductive film 41a formed in S121 is located on the seed crystal film 43a.
  • the embodiment of the present application may adopt a deposition process (including but not limited to physical vapor deposition, chemical vapor deposition, etc.) to form the barrier film 44a and the seed film 43a.
  • a deposition process including but not limited to physical vapor deposition, chemical vapor deposition, etc.
  • the structure after the barrier film 44a is deposited (barrier layer deposition) is shown in FIG10b
  • the structure after the seed film 43a is deposited is shown in FIG10c.
  • the material of the barrier film 44a may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc.
  • the material of the seed film 43a may include, for example, one or more of titanium, copper, nickel, cobalt, tungsten or related alloys.
  • the formed barrier film 44a can prevent the metal in the seed crystal film 43a and the conductive film 41a from diffusing into the dielectric bonding layer 3.
  • the formed seed crystal film 43a can facilitate the subsequent formation of the conductive film 41a using the ECP process.
  • the seed crystal film 43a and the barrier film 44a are also subjected to first grinding, and the portions of the seed crystal film 43a and the barrier film 44a located on the dielectric bonding layer 3 are removed, and the portions of the seed crystal film 43a and the barrier film 44a located in the hybrid bonding through hole G are retained, thereby obtaining the seed crystal layer 43 and the barrier layer 44.
  • the seed crystal layer 43 surrounds the conductive portion 41, and the barrier layer 44 surrounds the seed crystal layer 43.
  • the morphologies of the conductive part 41, the seed crystal layer 43 and the barrier layer 44 are, for example, as shown in FIG. 10e.
  • the top of the barrier layer 44 is, for example, flush with the surface of the side of the dielectric bonding layer 3 away from the substrate 1.
  • the surfaces of the side of the conductive part 41 and the seed crystal layer 43 away from the substrate 1 are curved and concave toward the substrate 1.
  • the metal passivation layer 42 subsequently formed in the concave for example, also covers the seed crystal layer 43.
  • FIG. 12 is a flow chart of preparing an integrated circuit in some embodiments
  • FIG. 13a to FIG. 13g are diagrams of the steps of preparing an integrated circuit in some embodiments.
  • the above-mentioned preparation method includes: S210 to S240.
  • a functional layer 2 and a dielectric bonding layer 3 are sequentially formed on a substrate 1 , wherein the dielectric bonding layer 3 has a plurality of hybrid bonding through holes G, and the hybrid bonding through holes G expose a portion of the surface of the functional layer 2 .
  • the material of the substrate 1, the structure of the functional layer 2, and the structure and material of the dielectric bonding layer 3 can be found in the above description and will not be described in detail here.
  • the material of the dielectric bonding layer 3 includes but is not limited to silicon nitride, silicon carbide, and silicon oxide.
  • a conductive portion 41 is formed in the hybrid bonding via G, and the conductive portion 41 is electrically connected to the functional layer 2. Compared with the substrate 1, the conductive portion 41 is farther from the substrate 1 and is lower than the dielectric bonding layer 3.
  • the embodiments of the present application may form the conductive portion 41 by processes including but not limited to electrochemical plating (ECP) and chemical-mechanical polishing (CMP).
  • ECP electrochemical plating
  • CMP chemical-mechanical polishing
  • the portion of the metal passivation film 42a formed in S240 located on the conductive part 41 can have a certain thickness.
  • a metal passivation film 42a is formed on the conductive portion 41 and the dielectric bonding layer 3.
  • the thickness of the metal passivation film 42a located on the conductive portion 41 is greater than the thickness of the metal passivation film 42a located on the dielectric bonding layer 3.
  • the embodiment of the present application may adopt a deposition process to form the metal passivation film 42 a .
  • the metal passivation film 42 a is in a planar shape, covering both the conductive portion 41 and the dielectric bonding layer 3 .
  • the side surface of the conductive part 41 is away from the substrate 1 and is lower than the side surface of the substrate 1 and away from the dielectric bonding layer 3, more metal material can be deposited on the conductive part 41, so that the metal passivation film 42a is a film layer with uneven thickness, and compared with the part of the metal passivation film 42a located on the dielectric bonding layer 3, the part of the metal passivation film 42a located on the conductive part 41 is thicker.
  • the metal passivation film 42a is subjected to a third grinding process to remove the portion of the metal passivation film 42a located on the dielectric bonding layer 3, and retain the portion of the metal passivation film 42a located on the conductive portion 41, thereby obtaining the metal passivation layer 42.
  • the melting point of the alloy formed by the material of the conductive portion 41 and the material of the metal passivation layer 42 is lower than the melting point of the material of the conductive portion 41.
  • the CMP process may be used to perform a third grinding treatment on the metal passivation film 42a.
  • the grinding pad used in the third grinding treatment is, for example, a hard grinding pad, and the removal of different positions of the metal passivation film 42a is, for example, equal removal.
  • the grinding pressure can be controlled, and the third grinding process of the metal passivation film 42a can be completed by capturing the cutoff signal.
  • the cutoff signal comes from the parameters of the grinding equipment, for example, and can be specifically expressed as grinding to the side surface of the dielectric bonding layer 3 away from the substrate 1, and the grinding is stopped after the metal on the side surface of the dielectric bonding layer 3 away from the substrate 1 is removed.
  • the thickness of the portion of the metal passivation film 42a located on the conductive part 41 is greater than the thickness of the portion of the metal passivation film 42a located on the dielectric bonding layer 3, after removing the portion of the metal passivation film 42a located on the dielectric bonding layer 3, only the portion of the metal passivation film 42a located on the conductive part 41 can be retained, and this portion constitutes the metal passivation layer 42.
  • the morphology of the metal passivation layer 42 is shown in FIG. 13f, where the surface of the metal passivation layer 42 on one side away from the substrate 1 is in an arc shape and is concave toward the substrate 1.
  • the concave can also be called a butterfly-shaped concave.
  • the amount of the butterfly-shaped concave is less than or equal to 5nm, so as to ensure that when different integrated circuits are subsequently mixed and bonded, the bonding pattern 4 can be mutually melted to avoid the situation of a circuit break due to non-mutual melting.
  • heat treatment for example, annealing
  • the material of the conductive part 41 will diffuse into the metal passivation layer 42 under the action of heat, so that an alloy layer is formed on the side of the bonding pattern 4 away from the substrate 1. Since the melting point of the alloy formed by the material of the conductive part 41 and the material of the metal passivation layer 42 is lower than the melting point of the material of the conductive part 41, the mutual melting and bonding of the bonding pattern 4 can be achieved at a lower heat treatment temperature.
  • a conductive portion 41 is formed in the dielectric bonding layer 3, and the conductive portion 41 is away from the side surface of the substrate 1, which is lower than the substrate 1 and away from the side surface of the dielectric bonding layer 3.
  • the thickness of the portion of the subsequently formed metal passivation film 42a located on the conductive portion 41 is greater than the thickness of the portion of the metal passivation film 42a located on the dielectric bonding layer 3.
  • the physical properties of the alloy layer formed by the conductive portion 41 and the metal passivation layer 42 that is, the property that the melting point of the alloy layer is lower than the melting point of the material of the conductive portion 41, can be utilized to reduce the temperature of the heat treatment during the hybrid bonding process.
  • the metal passivation layer 42 can be used to provide anti-oxidation protection for the surface of the conductive part 41, reduce the impact of heat treatment on the conductive part 41, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer, thereby improving the oxidation of the conductive part 41 in the bonding pattern 4, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, and further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.
  • the above preparation method does not introduce organic substances and solvents. Not only does it not require complicated post-processing to remove organic matter after selective deposition to form the metal passivation layer 42, thereby avoiding affecting the preparation efficiency of 3D ICs, it can also avoid the generation of carbon residues and impurity contamination at the interface of the hybrid bonding, thereby avoiding affecting the bonding effect.
  • the preparation method can realize the whole back end of line (BEOL) process, and the process cost adopted by the preparation method is low and the efficiency is high.
  • BEOL back end of line
  • a portion of the metal passivation film 42 a located on the conductive portion 41 has a thickness ranging from 10 nm to 60 nm.
  • a portion of the metal passivation film 42 a located on the conductive portion 41 has a thickness of 10 nm, 19 nm, 25 nm, 38 nm, 55 nm, or 60 nm.
  • the material of the conductive part 41 has a better diffusion effect in the metal passivation layer 42, and thus the alloy layer formed by the conductive part 41 and the metal passivation layer 42 can effectively reduce the temperature of the heat treatment.
  • the material of the conductive portion 41 includes copper
  • the material of the metal passivation layer 42 includes titanium, tin, silver, gold, or palladium.
  • the melting point of the copper-titanium binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in titanium is greater than the grain boundary diffusion coefficient of titanium in copper; the melting point of the copper-tin binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in tin is greater than the grain boundary diffusion coefficient of tin in copper; the melting point of the copper-silver binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in silver is greater than the grain boundary diffusion coefficient of silver in copper; the melting point of the copper-gold binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in gold is greater than the grain boundary diffusion coefficient of gold in copper; the melting point of the copper-palladium binary alloy is lower than the melting point of copper, and the grain boundary diffusion coefficient of copper in palladium is greater than the grain boundary diffusion coefficient of palladium in copper.
  • the alloy layer formed by the conductive part 41 and the metal passivation layer 42 can be located at the top of the bonding pattern 4, and the alloy layer located at the top of the bonding pattern 4 can be used to reduce the temperature of the heat treatment.
  • forming a conductive portion 41 in the hybrid bonding via G includes: S221 ⁇ S222 .
  • a conductive film 41 a is formed in the hybrid bonding via G and on the dielectric bonding layer 3 .
  • the embodiment of the present application may use, but is not limited to, an ECP process to form the conductive film 41a.
  • the surface of the conductive film 41a on the side away from the substrate 1 is, for example, a relatively flat surface.
  • the conductive film 41a is subjected to a first grinding process to remove the portion of the conductive film 41a located on the dielectric bonding layer 3, and retain the portion of the conductive film 41a located in the hybrid bonding through hole G to obtain the conductive portion 41.
  • the embodiment of the present application can use a CMP process to perform a first grinding process on the conductive film 41a, and the CMP grinding liquid used has an ultra-high selectivity ratio for the dielectric bonding layer 3 and the conductive film 41a.
  • the entire surface of the conductive film 41a is ground, so the portion of the conductive film 41a located on the hybrid bonding through hole G is also removed, and the portion retained in the hybrid bonding through hole G is lower than the dielectric bonding layer 3 compared to the substrate 1.
  • the morphology of the conductive part 41 is, for example, as shown in FIG13e , where the surface of the conductive part 41 away from the substrate 1 is in an arc shape and is concave toward the substrate 1.
  • This concave can also be called a butterfly-shaped concave.
  • the butterfly-shaped recessed structure can be constructed, thereby reserving space for the metal passivation film 42a subsequently deposited on the conductive part 41, ensuring that the thickness of the portion of the metal passivation film 42a located on the conductive part 41 is greater than the thickness of the portion of the metal passivation film 42a located on the dielectric bonding layer 3.
  • a maximum distance between a surface of the conductive portion 41 away from the substrate 1 and a surface of the dielectric bonding layer 3 away from the substrate 1 is in a range of 20 nm to 70 nm.
  • the maximum spacing may be 20 nm, 30 nm, 35 nm, 43 nm, 59 nm or 70 nm, etc.
  • the preparation method further includes: S223.
  • the embodiment of the present application may use a CMP process to grind and polish the surface of the dielectric bonding layer 3 away from the substrate 1.
  • the surface roughness of the dielectric bonding layer 3 may be increased.
  • the surface roughness of the dielectric bonding layer 3 can be reduced, and the flatness of the surface of the dielectric bonding layer 3 away from the substrate 1 can be improved.
  • the flattening requirement for the bonding interface can be met, avoiding the appearance of a large number of diffuse bubbles at the bonding interface of the three-dimensional integrated circuit formed by bonding, thereby improving the bonding effect.
  • the CMP polishing liquid used in S223 may be the same as or different from the CMP polishing liquid used in S222.
  • the surface of the side of the dielectric bonding layer 3 away from the substrate 1 may be planarized by adjusting parameters such as pressure.
  • the selection ratio of the two may be different to achieve planarization of the dielectric bonding layer 3.
  • the surface of the composite layer 3 which is away from the substrate 1 is planarized.
  • a metal passivation film 42a is formed on the conductive part 41 and the dielectric bonding layer 3, including: using an ionized physical vapor deposition (iPVD) process to deposit a metal passivation material on the conductive part 41 and the dielectric bonding layer 3 to form a metal passivation film 42a.
  • iPVD ionized physical vapor deposition
  • the integrated circuit to be formed can be placed in a PVD (physical vapor deposition) device, and the energy, time and other parameters can be adjusted through iPVD technology to deposit a metal passivation film 42a with a certain thickness on the conductive part 41 and the dielectric bonding layer 3.
  • PVD physical vapor deposition
  • FIG. 14 schematically shows a structure in which a metal film layer is deposited in a groove by a PVD process
  • FIG. 15 schematically shows a structure in which a metal film layer is deposited in a groove by an iPVD process.
  • the thickness of the metal film layer formed by the PVD process is uniform, and the thickness at different positions is basically the same, while the thickness of the metal film layer formed by the iPVD process is not uniform, and the thickness of the metal film layer located in the groove is greater.
  • the metal passivation film 42a formed by the iPVD process can satisfy the thickness of the part located on the conductive part 41, which is greater than the thickness of the part located on the dielectric bonding layer 3, so that after the metal passivation film 42a is subjected to the third grinding treatment, the part of the metal passivation film 42a located on the conductive part 41 can be retained, and the selective deposition of heterogeneous metals can be achieved.
  • FIG. 16 schematically shows a process of performing a third grinding treatment on the metal passivation film 42a.
  • the surface of the portion of the metal passivation film 42a located on the conductive portion 41 is basically completely covered by the positive and negative charges attracted by it, thereby making it difficult for the abrasive particles (abrasive) 5 in the CMP grinding liquid to reach the surface of the metal portion.
  • the grinding amount of the portion of the metal passivation film 42a located on the conductive portion 41 can be reduced, so that the grinding amount of the portion of the metal passivation film 42a located on the conductive portion 41 is less than the grinding amount of the portion of the metal passivation film 42a located on the dielectric bonding layer 3, so that after the portion of the metal passivation film 42a located on the dielectric bonding layer 3 is ground and removed, the thickness of the metal passivation layer 42 retained is larger, and the thickness of the metal passivation layer 42 is ensured on the basis of achieving selective deposition of heterogeneous metals.
  • the preparation method before the above S231, that is, before forming the conductive film 41a in the hybrid bonding via G and on the dielectric bonding layer 3, as shown in FIG13b and FIG13c, the preparation method further includes: sequentially forming a barrier film 44a and a seed crystal film 43a in the hybrid bonding via G and on the dielectric bonding layer 3.
  • the conductive film 41a formed in S121 is located on the seed crystal film 43a.
  • the embodiment of the present application may adopt a deposition process (including but not limited to physical vapor deposition, chemical vapor deposition, etc.) to form the barrier film 44a and the seed film 43a.
  • a deposition process including but not limited to physical vapor deposition, chemical vapor deposition, etc.
  • the structure after the barrier film 44a is deposited (barrier layer deposition) is shown in FIG13b
  • the structure after the seed film 43a is deposited is shown in FIG13c.
  • the material of the barrier film 44a may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, etc.
  • the material of the seed film 43a may include, for example, one or more of titanium, copper, nickel, cobalt, tungsten or related alloys.
  • the formed barrier film 44a can prevent the metal in the seed crystal film 43a and the conductive film 41a from diffusing into the dielectric bonding layer 3.
  • the formed seed crystal film 43a can facilitate the subsequent formation of the conductive film 41a using the ECP process.
  • the seed crystal film 43a and the barrier film 44a are also subjected to the first grinding process, and the portions of the seed crystal film 43a and the barrier film 44a located on the dielectric bonding layer 3 are removed, and the portions of the seed crystal film 43a and the barrier film 44a located in the hybrid bonding through hole G are retained to obtain the seed crystal layer 43 and the barrier layer 44.
  • the seed crystal layer 43 surrounds the conductive portion 41, and the barrier layer 44 surrounds the seed crystal layer 43.
  • the morphologies of the conductive part 41, the seed crystal layer 43 and the barrier layer 44 are, for example, as shown in FIG. 13e.
  • the top of the barrier layer 44 is, for example, flush with the surface of the side of the dielectric bonding layer 3 away from the substrate 1.
  • the surfaces of the side of the conductive part 41 and the seed crystal layer 43 away from the substrate 1 are curved and concave toward the substrate 1.
  • the metal passivation layer 42 subsequently formed in the concave for example, also covers the seed crystal layer 43.
  • Some embodiments of the present application further provide a three-dimensional integrated circuit.
  • Figures 17 to 19 respectively illustrate the structure of a three-dimensional integrated circuit.
  • the three-dimensional integrated circuit 16 includes: a first integrated circuit 100a and a second integrated circuit 100b arranged opposite to each other.
  • the first integrated circuit 100a and the second integrated circuit 100b are the integrated circuits 100 described in any of the above embodiments.
  • the bonding pattern 4 in the first integrated circuit 100a is bonded to the bonding pattern 4 in the second integrated circuit 100b.
  • the dielectric bonding layer 3 of the first integrated circuit 100a is bonded to the dielectric bonding layer 3 of the second integrated circuit 100b to achieve bonding between the first integrated circuit 100a and the second integrated circuit 100b.
  • the bonding pattern 4 includes a conductive portion 41 and a metal passivation layer 42 located on the conductive portion 41.
  • the dielectric bonding layer 3 of the two integrated circuits can generate a strong physical bond, and the materials of the conductive portions 41 of the two integrated circuits will diffuse into the corresponding metal passivation layer 42 under the action of heat to form an alloy layer, and the alloy layers are mutually melted and bonded together.
  • beneficial effects that can be achieved by the three-dimensional integrated circuit 16 provided in the embodiment of the present application are the same as the beneficial effects that can be achieved by the integrated circuit 100 provided in some of the above embodiments, and will not be repeated here.
  • silicon nitride or silicon carbide has a higher blocking ability to the material of the conductive part 41, and can prevent the material of the conductive part 41 from diffusing into the dielectric bonding layer 3; while silicon oxide has a lower blocking ability to the material of the conductive part 41, and it is difficult to prevent the material of the conductive part 41 from diffusing into the dielectric bonding layer 3.
  • the three-dimensional integrated circuit 16 has a reference plane, which is a surface of a side of the substrate 1 of the first integrated circuit 100 a away from the second integrated circuit 100 b .
  • the material of either the dielectric bonding layer 3 of the first integrated circuit 100a or the dielectric bonding layer 3 of the second integrated circuit 100b includes silicon nitride or silicon carbide. As shown in FIGS. 17 and 18 , the orthographic projections of the bonding pattern 4 of the first integrated circuit 100a and the bonding pattern 4 of the second integrated circuit 100b on the reference plane overlap or partially overlap.
  • the bonding pattern 4 of the first integrated circuit 100a and the bonding pattern 4 of the second integrated circuit 100b have orthographic projections on the reference plane that overlap.
  • the size of the bonding pattern 4 of the first integrated circuit 100a is the same as the size of the bonding pattern 4 of the second integrated circuit 100b.
  • the bonding pattern 4 of the first integrated circuit 100a and the bonding pattern 4 of the second integrated circuit 100b partially overlap in their orthographic projection on the reference plane.
  • the size of the bonding pattern 4 of the first integrated circuit 100a and the size of the bonding pattern 4 of the second integrated circuit 100b can be the same or different.
  • the bonding pattern 4 of one is in contact with the dielectric bonding layer 3 of the other.
  • silicon nitride or silicon carbide can block the diffusion of the material of the conductive part 41 into the dielectric bonding layer 3 under high temperature environment, it can effectively avoid the electrical problems and reliability reduction problems caused by blocking the diffusion of the material of the conductive part 41 into the dielectric bonding layer 3.
  • the alignment accuracy of the first integrated circuit 100a and the second integrated circuit 100b can be effectively reduced, and the difficulty of bonding the first integrated circuit 100a and the second integrated circuit 100b can be reduced.
  • the material of the dielectric bonding layer 3 of the first integrated circuit 100a includes silicon nitride or silicon carbide
  • the material of the dielectric bonding layer 3 of the second integrated circuit 100b includes silicon oxide.
  • the orthographic projection of the bonding pattern 4 of the first integrated circuit 100a on the reference plane is within the orthographic projection range of the bonding pattern 4 of the second integrated circuit 100b on the reference plane.
  • a portion of the boundary of the orthographic projection of the bonding pattern 4 of the first integrated circuit 100a on the reference plane coincides with a portion of the boundary of the orthographic projection of the bonding pattern 4 of the second integrated circuit 100b on the reference plane; another portion of the boundary of the orthographic projection of the bonding pattern 4 of the first integrated circuit 100a on the reference plane and another portion of the boundary of the orthographic projection of the bonding pattern 4 of the second integrated circuit 100b on the reference plane have a spacing therebetween.
  • a boundary of the orthographic projection of the bonding pattern 4 of the first integrated circuit 100a on the reference plane and a boundary of the orthographic projection of the bonding pattern 4 of the second integrated circuit 100b on the reference plane both have a spacing therebetween.
  • the size of the bonding pattern 4 of the first integrated circuit 100a is smaller than the size of the bonding pattern 4 of the second integrated circuit 100b. There is no contact between the bonding pattern 4 of the first integrated circuit 100a and the dielectric bonding layer 3 of the second integrated circuit 100b, while the bonding pattern 4 of the second integrated circuit 100b is in contact with the dielectric bonding layer 3 of the first integrated circuit 100a.
  • the dielectric bonding layer 3 of the first integrated circuit 100a can be used to effectively block the diffusion of the material of the conductive part 41 in the bonding pattern 4 of the second integrated circuit 100b, and effectively avoid electrical problems and reliability reduction problems caused by blocking the diffusion of the material of the conductive part 41 into the dielectric bonding layer 3.
  • Some embodiments of the present application also provide a method for preparing a three-dimensional integrated circuit.
  • the preparation method is used, for example, to prepare a A three-dimensional integrated circuit as described in any of the above embodiments.
  • Figure 20 is a flow chart of manufacturing an integrated circuit in some embodiments;
  • Figures 21a to 21b are diagrams of various steps of manufacturing a three-dimensional integrated circuit in some embodiments.
  • the above-mentioned preparation method includes: S310 to S330.
  • S310 provides a first integrated circuit 100a and a second integrated circuit 100b, wherein the first integrated circuit 100a and the second integrated circuit 100b are the integrated circuits 100 described in any of the above embodiments.
  • alignment marks may be prepared on the surfaces of the two.
  • the alignment marks of the two are respectively captured to collect the position information of the two until the two are aligned. Then, the first integrated circuit 100a is bonded to the second integrated circuit 100b.
  • heat treatment is performed on the bonded first integrated circuit 100a and the second integrated circuit 100b, and the temperature range of the heat treatment is 120°C to 400°C.
  • the temperature of the heat treatment is 120° C., 150° C., 300° C., 350° C. or 400° C.
  • the material of the conductive portion 41 expands under the action of heat, so that the bonding patterns 4 in the first integrated circuit 100 a and the second integrated circuit 100 b come into contact.
  • the embodiment of the present application can use in-situ heating and pressurization to perform heat treatment on the bonded first integrated circuit 100a and the second integrated circuit 100b, so that the material of the conductive portion 41 of the bonding pattern 4 in the first integrated circuit 100a diffuses into the metal passivation layer 42, and forms an alloy layer on the side of the bonding pattern 4 away from the substrate 1.
  • the material of the conductive portion 41 of the bonding pattern 4 in the second integrated circuit 100b diffuses into the metal passivation layer 42, and forms an alloy layer on the side of the bonding pattern 4 away from the substrate 1.
  • the alloy layer in the first integrated circuit 100a and the alloy layer in the second integrated circuit 100b are mutually melted, so that the first integrated circuit 100a and the second integrated circuit 100b are interconnected.
  • the embodiment of the present application can perform an annealing treatment on the bonded first integrated circuit 100a and the second integrated circuit 100b in a vacuum atmosphere, so that the material of the conductive portion 41 of the bonding pattern 4 in the first integrated circuit 100a diffuses into the metal passivation layer 42, and forms an alloy layer on the side of the bonding pattern 4 away from the substrate 1.
  • the material of the conductive portion 41 of the bonding pattern 4 in the second integrated circuit 100b diffuses into the metal passivation layer 42, and forms an alloy layer on the side of the bonding pattern 4 away from the substrate 1.
  • the alloy layer in the first integrated circuit 100a and the alloy layer in the second integrated circuit 100b are mutually melted, so that the first integrated circuit 100a and the second integrated circuit 100b are interconnected.
  • the temperature of the heat treatment of the hybrid bonding is very high, and the temperature of the heat treatment is basically above 400°C.
  • the embodiment of the present application can reduce the temperature of the heat treatment of the hybrid bonding to 400°C or below by providing a metal passivation layer 42 on the conductive portion 41 in the bonding pattern 4. In other words, the embodiment of the present application effectively reduces the temperature of the heat treatment of the hybrid bonding.
  • the metal passivation layer 42 can be used to provide anti-oxidation protection for the surface of the conductive part 41, reduce the impact of heat treatment on the conductive part 41, and reduce the impact of heat treatment on stress, thermal balance and structural reliability in the wafer, thereby improving the oxidation of the conductive part 41 in the bonding pattern 4, wafer warping, and destruction of the thermal balance and structural reliability of the wafer, and further ensuring the electrical performance and reliability of the three-dimensional integrated circuit formed by interconnection.

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Abstract

本申请实施例公开一种集成电路及其制备方法、三维集成电路、电子设备，涉及半导体技术领域，用于降低不同集成电路混合键合时的热处理的温度。集成电路包括：衬底，位于衬底上的功能层，位于功能层上的介质键合层，位于介质键合层内的多个键合图案。键合图案与功能层电连接。键合图案包括与功能层电连接的导电部，及位于导电部上的金属钝化层。其中，导电部的材料和金属钝化层的材料形成的合金的熔点，低于导电部的材料的熔点。

Description

集成电路及其制备方法、三维集成电路、电子设备
本申请要求于2022年11月03日提交国家知识产权局、申请号为202211371686.6、申请名称为“集成电路及其制备方法、三维集成电路、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种集成电路及其制备方法、三维集成电路及其制备方法、电子设备。
背景技术
随着半导体制造工艺进入深亚微米阶段后，晶体管的尺寸需要大大减小，晶圆的集成度不断提高，平面(2D)集成电路(integrated circuit，IC)的发展面临挑战。例如，晶体管的小型化迅速增加了互连布局的复杂性；当特征尺寸为10nm以下节点时，会出现严重的RC延迟，挑战IC的性能。为了降低IC互连长度、功耗和RC延迟等，通常将不同晶圆堆叠、键合在一起，以形成三维集成电路(three-dimensional integrated circuit，3D IC)。3D IC技术可以应用于高带宽存储器(high bandwidth memory，HBM)、量子计算、第五或第六代移动网络(5/6G)和人工智能(artificial intelligence，AI)芯片等。
目前，金属/介质混合键合(hybrid bonding，HB)的方式，被认为是实现高互连密度和高性能集成电路的很有发展前途技术。在将不同的晶圆(以两个晶圆为例)进行混合键合的过程中，需要在该两个晶圆的表面制备介质键合层和导电部，然后将两个晶圆对位、键合，并对键合后的两个晶圆进行高温的热处理(例如退火处理)，实现两个晶圆的导电部的互熔。
但是，在高温的热处理中，容易出现导电部氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题。因此，如何降低两个晶圆的热处理的温度，成为本领域内亟待解决的问题。
发明内容
本申请实施例提供一种集成电路及其制备方法、三维集成电路及其制备方法、电子设备，用于降低不同集成电路混合键合时的热处理的温度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种集成电路，该集成电路包括：衬底，位于衬底上的功能层，位于功能层上的介质键合层，位于介质键合层内的多个键合图案。键合图案与功能层电连接。键合图案包括与功能层电连接的导电部，及位于导电部上的金属钝化层。其中，导电部的材料和金属钝化层的材料形成的合金的熔点，低于导电部的材料的熔点。
本申请的一些实施例提供的集成电路，通过在功能层上设置介质键合层，并设置位于介质键合层内、且与功能层电连接的多个键合图案，可以使得集成电路能够采用混合键合的方式与其他的集成电路形成互连，提高互连形成的三维集成电路的可靠性。
而且，本申请实施例通过在键合图案中设置导电部，并设置覆盖导电部的至少一部分的金属钝化层，可以利用导电部和金属钝化层所形成的合金层的物理性质，也即，该合金层的熔点低于导电部的材料的熔点的性质，降低键合图案的键合温度，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层对导电部的表面进行抗氧化保护，降低热处理对导电部的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案中导电部的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
在第一方面可能的实现方式中，导电部的材料在金属钝化层中的晶界扩散系数，大于金属钝化层的材料在导电部中的晶界扩散系数。这样可以使得导电部和金属钝化层所形成的合金层主要位于键合图案的顶端(也即远离衬底的一端)，既能够利用该合金层降低混合键合过程中热处理的温度，又能够利用导电部的良好电学性能(例如较小的电阻和较好的抗电迁移和导热性能)，保障互连形成的三维集成电路的电学性能，降低合金层对三维集成电路的电学性能的影响。
在第一方面可能的实现方式中，相比于衬底，金属钝化层远离衬底的一侧表面的至少一部分，低于介质键合层远离衬底的一侧表面。这样在进行混合键合、且集成电路处于热处理的过程中，可以为导电部的受热膨胀提供一定的缓冲，既可以避免顶裂晶圆，还可以避免已键合的介质键合层分离，提高互连形成的三维集成电路的结构可靠性。
在第一方面可能的实现方式中，金属钝化层远离衬底的一侧表面呈弧面状，且向靠近衬底的方向凹陷。金属钝化层远离衬底1的一侧表面呈碗装、盘状或凹槽状。这样便于制备形成金属钝化层。
在第一方面可能的实现方式中，相比于衬底，导电部远离衬底的一侧表面，低于介质键合层远离衬底的一侧表面。这样可以为位于导电部上的金属钝化层预留设置空间，确保金属钝化层整体能够相对于衬底，低于介质键合层远离衬底1的一侧表面，进而为导电部的受热膨胀提供缓冲空间。
在第一方面可能的实现方式中，导电部远离衬底的一侧表面呈弧面状，且向靠近衬底的方向凹陷。导电部远离衬底的一侧表面呈碗装、盘状或凹槽状。这样便于制备形成导电部。
在第一方面可能的实现方式中，导电部的材料包括铜，金属钝化层的材料包括镍、钛、锡、银、金或钯。这样可以确保键合图案的键合的温度的降低，或混合键合热处理温度的降低，进而能够有效改善键合图案中导电部的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题。
在第一方面可能的实现方式中，介质键合层的材料包括氮化硅、氮碳化硅、氧化硅。
在第一方面可能的实现方式中，键合图案还包括：籽晶层和阻挡层。籽晶层环绕导电部，且位于导电部和介质键合层之间。阻挡层环绕籽晶层，且位于籽晶层和介质键合层之间。阻挡层可将籽晶层与介质键合层隔开，可避免籽晶层与介质键合层直接接触而发生铜扩散，从而提高集成电路的产品可靠性。
第二方面，提供了一种集成电路的制备方法，该制备方法包括：在衬底上依次形成功能层和介质键合层，介质键合层具有多个混合键合通孔，混合键合通孔暴露功能层的部分表面；在混合键合通孔内形成导电部，导电部与功能层电连接，得到初始集成电路；将初始集成电路置于处理气体中，处理气体包括金属羰基有机化合物前驱体蒸汽，以在导电部上选择性沉积金属钝化层。其中，导电部的材料和金属钝化层的材料构成的合金的熔点，低于导电部的材料的熔点。
本申请的一些实施例提供的集成电路的制备方法，通过将上述处置集成电路置于包括金属羰基有机化合物前驱体蒸汽中，可以利用金属羰基有机化合物前驱体对导电部和介质键合层的高选择比，实现异质金属高选择性沉积，进而可以利用导电部和金属钝化层所形成的合金层的物理性质，也即，该合金层的熔点低于导电部的材料的熔点的性质，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层对导电部的表面进行抗氧化保护，降低热处理对导电部的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案中导电部的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
另外，上述制备方法未引入有机物质和溶剂，不仅在选择性沉积形成金属钝化层之后，无需涉及复杂的后处理去除有机物过程，避免影响3D IC的制备效率，还可以避免在混合键合的界面产生碳残留和杂质污染，避免影响键合的效果。
在第二方面可能的实现方式中，金属钝化层的厚度的范围为10nm～30nm。采用上述厚度范围，可以在不同集成电路的混合键合的热处理过程中，使得导电部的材料在金属钝化层中具有较好的扩散效果，进而使得导电部和金属钝化层所形成的合金层，能够有效降低热处理的温度。
在第二方面可能的实现方式中，导电部的材料包括铜，金属羰基有机化合物前驱体包括Ni(CO)4。Ni(CO)4发生热分解后可以在导电部上析出镍。铜镍二元合金的熔点低于铜的熔点，且铜在镍中的晶界扩散系数，大于镍在铜中的晶界扩散系数。采用铜形成导电部，并采用镍形成金属钝化层，可以使得导电部和金属钝化层形成的合金层位于键合图案的顶端，进而能够利用位于键合图案顶端的合金层降低热处理的温度。
在第二方面可能的实现方式中，在混合键合通孔内形成导电部，包括：在混合键合通孔内和介质键合层上形成导电薄膜；对导电薄膜进行第一研磨处理，去除导电薄膜中位于介质键合层上 的部分，保留导电薄膜中位于混合键合通孔内的部分，得到导电部。相比于衬底，导电部远离衬底的一侧表面，低述介质键合层远离衬底的一侧表面。第一研磨处理中采用的研磨液对介质键合层和导电薄膜具有超高选择比，利用该性质，可以实现蝶形凹陷结构的构建，进而可以为后续沉积于导电部上的金属钝化层预留空间，确保金属钝化层整体能够相对于衬底，低于介质键合层远离衬底的一侧表面，进而为导电部的受热膨胀提供缓冲空间。
在第二方面可能的实现方式中，上述制备方法还包括：对介质键合层远离衬底的一侧表面进行平坦化处理。这样在将不同集成电路进行混合键合的过程中，可以满足对于键合界面的平坦化需求，避免键合形成的三维集成电路的键合界面出现大量的弥散气泡，提高键合效果。
在第二方面可能的实现方式中，在垂直于衬底的方向上，导电部远离衬底的一侧表面，与介质键合层远离衬底的一侧表面之间的最大间距的范围为10nm～30nm。可选地，该最大间距可以为10nm、13nm、15nm、21nm、25nm或30nm等。
在第二方面可能的实现方式中，上述制备方法还包括：对金属钝化层和介质键合层远离衬底的一侧表面进行第二研磨处理。相比于衬底，金属钝化层远离衬底的一侧表面的至少一部分，低于介质键合层远离衬底的一侧表面。这样在将不同的集成电路进行混合键合时，可以为导电部的受热膨胀提供一定的缓冲，既可以避免顶裂晶圆，还可以避免已键合的介质键合层3分离，提高互连形成的三维集成电路的结构可靠性。
在第二方面可能的实现方式中，在混合键合通孔内和介质键合层上形成导电薄膜之前，制备方法还包括：在混合键合通孔内和介质键合层上，依次形成阻挡薄膜和籽晶薄膜。其中，在对导电薄膜进行第一研磨处理的过程中，还对籽晶薄膜和阻挡薄膜进行第一研磨处理，去除籽晶薄膜和阻挡薄膜位于介质键合层上的部分，保留籽晶薄膜和阻挡薄膜位于混合键合通孔内的部分，得到籽晶层和阻挡层；籽晶层环绕导电部，阻挡层环绕籽晶层。形成的阻挡薄膜可以避免籽晶薄膜和导电薄膜中的金属扩散到介质键合层中。形成的籽晶薄膜可以便于后续采用电镀工艺形成导电薄膜。
第三方面，提供了一种集成电路的制备方法，该制备方法包括：在衬底上依次形成功能层和介质键合层，介质键合层具有多个混合键合通孔，混合键合通孔暴露功能层的部分表面；在混合键合通孔内形成导电部，导电部与功能层电连接，相比于衬底，导电部远离衬底的一侧表面，低于介质键合层远离衬底的一侧表面；在导电部上和介质键合层上形成金属钝化薄膜，金属钝化薄膜中位于导电部上的部分的厚度，大于金属钝化薄膜中位于介质键合层上的部分的厚度；对金属钝化薄膜进行第三研磨处理，去除金属钝化薄膜位于介质键合层上的部分，保留金属钝化薄膜位于导电部上的部分，得到金属钝化层。其中，导电部的材料和金属钝化层的材料构成的合金的熔点，低于导电部的材料的熔点。
本申请的一些实施例提供的集成电路的制备方法，通过在介质键合层中形成导电部，并使得导电部远离衬底的一侧表面，相比于衬底低于介质键合层远离衬底的一侧表面，并在后续形成的金属钝化薄膜中位于导电部上的部分的厚度，大于金属钝化薄膜中位于介质键合层上的部分的厚度，可以在对金属钝化薄膜进行第三研磨处理之后，保留金属钝化薄膜位于导电部上的部分，得到金属钝化层，实现异质金属的选择性沉积，进而可以利用导电部和金属钝化层所形成的合金层的物理性质，也即，该合金层的熔点低于导电部的材料的熔点的性质，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层对导电部的表面进行抗氧化保护，降低热处理对导电部的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案中导电部的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
另外，上述制备方法未引入有机物质和溶剂，不仅在选择性沉积形成金属钝化层之后，无需涉及复杂的后处理去除有机物过程，避免影响3D IC的制备效率，还可以避免在混合键合的界面产生碳残留和杂质污染，避免影响键合的效果。
在第三方面可能的实现方式中，导电部的材料包括铜，金属钝化层材料包括钛、锡、银、金或钯。采用铜形成导电部，并采用钛、锡、银、金或钯等形成金属钝化层，可以使得导电部和金 属钝化层形成的合金层位于键合图案的顶端，进而能够利用位于键合图案顶端的合金层降低热处理的温度。
在第三方面可能的实现方式中，金属钝化薄膜中位于导电部上的一部分的厚度的范围为10nm～60nm。采用上述厚度范围，可以在对金属钝化薄膜进行第三研磨处理后，保留在导电部上的一部分仍具有一定的厚度，进而在不同集成电路的混合键合的热处理过程中，使得导电部的材料在金属钝化层中具有较好的扩散效果，进而使得导电部和金属钝化层所形成的合金层，能够有效降低热处理的温度。
在第三方面可能的实现方式中，在混合键合通孔内形成导电部，包括：在混合键合通孔内和介质键合层上形成导电薄膜；对导电薄膜进行第一研磨处理，去除导电薄膜位于介质键合层上的部分，保留导电薄膜位于混合键合通孔内的部分，得到导电部。第一研磨处理中采用的研磨液对介质键合层和导电薄膜具有超高选择比，利用该性质，可以实现蝶形凹陷结构的构建，进而可以为后续沉积于导电部上的金属钝化层预留空间，确保金属钝化层整体能够相对于衬底，低于介质键合层远离衬底的一侧表面，进而为导电部的受热膨胀提供缓冲空间。
在第三方面可能的实现方式中，上述制备方法还包括：对介质键合层远离衬底的一侧表面进行平坦化处理。这样在将不同集成电路进行混合键合的过程中，可以满足对于键合界面的平坦化需求，避免键合形成的三维集成电路的键合界面出现大量的弥散气泡，提高键合效果。
在第三方面可能的实现方式中，在垂直于衬底的方向上，导电部远离衬底的一侧表面，与介质键合层远离衬底的一侧表面之间的最大间距的范围为20nm～70nm。可选地，该最大间距可以为20nm、30nm、35nm、43nm、59nm或70nm等。
在第三方面可能的实现方式中，在导电部上和介质键合层上形成金属钝化薄膜，包括：采用离子化物理气相沉积工艺，在导电部上和介质键合层上沉积金属钝化材料，形成金属钝化薄膜。采用离子化物理气相沉积工艺形成的金属钝化薄膜，能够满足其位于导电部上的部分的厚度，大于其位于介质键合层上的部分的厚度，这样在对金属钝化薄膜进行第三研磨处理之后，则能够保留金属钝化薄膜位于导电部上的部分，实现异质金属的选择性沉积。
在第三方面可能的实现方式中，在混合键合通孔内和介质键合层上形成第一导电薄膜之前，制备方法还包括：在混合键合通孔内和介质键合层上，依次形成阻挡薄膜和籽晶薄膜。其中，在对导电薄膜进行第一研磨处理的过程中，还对籽晶薄膜和阻挡薄膜进行第一研磨处理，去除籽晶薄膜和阻挡薄膜位于介质键合层上的部分，保留籽晶薄膜和阻挡薄膜位于混合键合通孔内的部分，得到籽晶层和阻挡层。籽晶层环绕导电部和金属钝化层，阻挡层环绕籽晶层。形成的阻挡薄膜可以避免籽晶薄膜和导电薄膜中的金属扩散到介质键合层中。形成的籽晶薄膜可以便于后续采用电镀工艺形成导电薄膜。
第四方面，提供了一种三维集成电路，该三维集成电路包括：相对设置的第一集成电路和第二集成电路。第一集成电路和第二集成电路为如第一方面中任一实施方式中所述的集成电路。其中，第一集成电路中的键合图案与第二集成电路中的键合图案相键合，第一集成电路的介质键合层与第二集成电路的介质键合层相键合。
在第四方面可能的实现方式中，第一集成电路的介质键合层与第二集成电路的介质键合层中，任一者的材料包括氮化硅或氮碳化硅。第一集成电路的键合图案与第二集成电路的键合图案，在参考平面上的正投影重合或部分交叠。参考平面为第一集成电路的衬底远离第二集成电路的一侧表面。这样可以有效降低第一集成电路和第二集成电路的对位精度，降低第一集成电路和第二集成电路键合的难度。
在第四方面可能的实现方式中，第一集成电路的介质键合层的材料包括氮化硅或氮碳化硅，第二集成电路的介质键合层的材料包括氧化硅。第一集成电路的键合图案在参考平面上的正投影，位于第二集成电路的键合图案在参考平面上的正投影范围内。参考平面为第一集成电路的衬底远离第二集成电路的一侧表面。这样可以利用第一集成电路的介质键合层，有效阻挡第二集成电路的键合图案中导电部的材料的扩散，有效避免出现因阻挡导电部的材料向介质键合层的扩散，而引起的电性问题、可靠性降低问题。
第五方面，提供了一种三维集成电路的制备方法，该制备方法包括：提供第一集成电路和第 二集成电路，第一集成电路和第二集成电路为如第一方面中任一实施方式中所述的集成电路；将第一集成电路和第二集成电路对位并键合；对键合后的第一集成电路和第二集成电路进行热处理，热处理的温度的范围为120℃～400℃。
第六方面，提供了一种电子设备，该电子设备包括如第四方面中任一实施方式中所述的三维集成电路。
第四方面至第六方面中任一种设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构图；
图2为本申请实施例提供的一种电子设备的局部结构图；
图3为本申请实施例提供的一种三维集成电路的结构图；
图4为本申请实施例提供的一种固液扩散键合的示意图；
图5为本申请实施例提供的一种各向异性导电膜/膏键合的示意图；
图6为本申请实施例提供的一种混合键合的示意图；
图7为本申请实施例提供的一种集成电路的结构图；
图8为本申请实施例提供的另一种集成电路的结构图；
图9为本申请实施例提供的一种集成电路的制备方法的流程图；
图10a～图10f为本申请实施例提供的一种制备集成电路的步骤图；
图11a～图11e为本申请实施例提供的另一种制备集成电路的步骤图；
图12为本申请实施例提供的另一种集成电路的制备方法的流程图；
图13a～图13g为本申请实施例提供的又一种制备集成电路的步骤图；
图14为本申请实施例提供的一种采用物理气相沉积工艺形成的膜层的结构图；
图15为本申请实施例提供的一种采用离子化物理气相沉积工艺形成的膜层的结构图；
图16为本申请实施例提供的一种对金属钝化薄膜进行第三研磨处理的示意图；
图17为本申请实施例提供的一种三维集成电路的结构图；
图18为本申请实施例提供的另一种三维集成电路的结构图；
图19为本申请实施例提供的又一种三维集成电路的结构图；
图20为本申请实施例提供的一种三维集成电路的制备方法的流程图；
图21a～图21b为本申请实施例提供的一种制备三维集成电路的步骤图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
其中，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
本申请实施例中，“上”、“下”、“左”以及“右”不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。在附图中，为了清楚起见，夸大了层和区域的厚度，图示中的各部分之间的尺寸比例关系并不反映实际的尺寸比例关系。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
此外，本申请实施例描述的架构以及场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着架构的演变和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请实施例提供一种电子设备。该电子设备可以是手机(mobile phone)、平板电脑(pad)、电视、桌面型计算机、膝上型计算机、手持计算机、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本，以及蜂窝电话、个人数字助理(personal digital assistant，PDA)、增强现实(augmented reality，AR)设备、虚拟现实(virtual reality，VR)设备、人工智能(artificial intelligence，AI)设备、智能穿戴设备(例如，智能手表、智能手环)、车载设备、智能家居设备和/或智慧城市设备，本申请实施例对该电子设备的具体类型不作特殊限制。
以下为了方便说明，以电子设备为手机为例进行举例说明，这不能认为是对电子设备的结构形式构成的具体限定。图1为一些实施例中的电子设备的结构图。
如图1所示，电子设备1000主要包括盖板11、显示屏12、中框13以及后壳14。后壳14和显示屏12分别位于中框13的两侧，且中框13和显示屏12设置于后壳14内，盖板11设置在显示屏12远离中框13的一侧，显示屏12的显示面朝向盖板11。
其中，显示屏12可以是液晶显示屏(liquid crystal display，LCD)，在此情况下，液晶显示屏包括液晶显示面板和背光模组，液晶显示面板设置在盖板11和背光模组之间，背光模组用于为液晶显示面板提供光源。上述显示屏12也可以为有机发光二极管(organic light emitting diode，OLED)显示屏、量子点发光二极管(quantum dot light emitting diodes，QLED)显示屏、迷你发光二极管(mini light emitting diode，Mini LED)显示屏或微型发光二极管(micro light emitting diode，Micro LED)显示屏等。由于OLED显示屏、QLED显示屏、Mini LED显示屏、Micro LED显示屏等均为自发光显示屏，因而无需设置背光模组。
上述中框13包括承载板131以及绕承载板131一周的边框132。电子设备1000中还包括设置于承载板131上的电路板15、电池、摄像头等电子元器件。
如图1所示，上述电子设备1000还可以包括设置于电路板15上的三维集成电路16，该三维集成电路16与电路板15电连接。
如图2所示，上述电子设备1000还包括设置在电路板15和三维集成电路16之间的第一连接件17，三维集成电路16通过第一连接件17与电路板15电连接。第一连接件17例如可以为球栅阵列(ball grid array，BGA)。
三维集成电路16包括依次堆叠的多个集成电路100、封装基板18、及设置在该多个集成电路100和封装基板18之间的第二连接件19，该多个集成电路100通过第二连接件19与封装基板18电连接。第二连接件19例如可以为可控塌陷芯片连接凸块(controlled collapse chip connection bump，C4 bump)。其中，集成电路100的数量可以为两个、三个、四个甚至更多个。图2示意出了两个集成电路100。
可以理解的是，多个集成电路100依次堆叠相对于多个集成电路单独设置具有较多优势，例如能够获得更高的带宽，从而获得更高的存储或计算密度等，还可以减小封装尺寸，提升芯片的集成度等。
如图3所示，在三维集成电路16中，每个集成电路100都包括衬底(substrate)1以及设置 在衬底1上的功能层2，功能层2在工作过程中可以使得集成电路100实现其自身的功能，例如逻辑计算功能或者存储功能等。其中，功能层2包括但不限于功能器件、电路结构、互连金属线以及电介质层等。
例如，三维集成电路16包括相键合并形成电连接的两个集成电路100，其中一个集成电路100的功能层2能够使得集成电路100实现存储功能，相应的，该集成电路100为存储器芯片，另一个集成电路100的功能层2能够使得集成电路100实现逻辑计算功能，相应的，该集成电路100为处理器芯片。
示例性的，上述集成电路100的衬底1的材料例如可以包括硅(Si)、锗(Ge)、氮化镓(GaN)、砷化镓(GaAs)或其它半导体材料中的一种或多种。此外，衬底1的材料例如还可以为玻璃(glass)、有机材料等。
在本申请的一些实施例中，三维集成电路16中的集成电路100可以是指形成有功能层2的晶圆(wafer)，也可以是指将形成有功能层2的晶圆切割后得到的裸芯片(die)，裸芯片也可以称为晶粒或颗粒。在某些场合下，集成电路100也可以是将裸芯片进行封装后得到的封装后的芯片。基于此，在一些实施例中，上述三维集成电路16中的多个集成电路100可以均为裸芯片或者均为将裸芯片封装后得到的芯片。在另一些实施例中，上述三维集成电路16中的多个集成电路100可以均为晶圆。在又一些实施例中，上述三维集成电路16中的多个集成电路100可以是部分集成电路100为晶圆，部分集成电路100为裸芯片和/或将裸芯片封装后得到的芯片。
在上述三维集成电路16中，为了实现相邻两个集成电路100之间的互连，且满足更细间距互连的要求，主要有三种键合的方式，也即，如图4所示的固液扩散(或称为滑动)(solid-liquid inter diffuse，SLID)键合(bonding)、如图5所示的各向异性导电膜/膏(anisotropic conductive film/pastes，ACF/ACP)键合和如图6所示的金属/介质混合键合。
图4中的(a)示意出了采用固液扩散键合(SLID Bonding)的方式进行互连的集成电路的一种结构，功能层上设置有重新布线层(redistribution layer，RDL)1’和焊料(solder)。图4中的(b)示意出了两个集成电路键合后的理想的键合结果(ideal bonding result)，重新布线层1’中的导电部和焊料2’之间均填充(underfill)有介质。图4中的(c)示意出了更细间距键合情况下出现的问题(finer pitch bonding concern)，例如，重新布线层1’中部分导电部之间的狭窄缝隙(narrow gap)内未填充介质，部分焊料2’之间相互挤压(squeeze)。
图5中的(a)示意出了采用各向异性导电膜键合(ACF Bonding)的方式进行互连的集成电路的一种结构，功能层上设置有重新布线层1’和各向异性导电膜3’。图5中的(b)示意出了两个集成电路键合后的理想的键合结果，各向异性导电膜3’中的导电颗粒(conductive particles，CPs)弥散分布，且两个集成电路中的重新布线层1’之间均填充有导电颗粒。其中，图5中的(a)示意出了导电颗粒的放大图，导电颗粒包括聚合物(polymer)及包裹该聚合物的导电层(conductive layer)。图5中的(c)示意出了更细间距键合情况下出现的问题，例如，重新布线层1’中部分导电部之间键合填充(Bonding filled)失效，没有填充导电颗粒从而未形成电连接；或者，导电颗粒发生聚集，重新布线层1’中相邻的导电部通过聚集的导电颗粒形成短路(leakage)。
图6中的(a)示意出了采用混合键合的方式进行互连的集成电路的一种结构，功能层上设置有重新布线层1’和介质键合层4’。图6中的(b)示意出了两个集成电路键合后的理想的键合结果，两个集成电路中，重新布线层1’和重新布线层1’相键合，介质键合层4’和介质键合层4’相键合。
由上可知，在更细间距互连的要求下，相比于固液扩散键合和各向异性导电膜键合，混合键合的方式能够使得三维集成电路具有更好的互连效果。
但是，采用混合键合的方式实现三维集成电路的互连时，需要经过高温的热处理，这样容易出现导电部氧化、晶圆(也即集成电路)翘曲、晶圆的热平衡和结构可靠性被破坏等问题。
基于此，本申请的一些实施例提供了一种集成电路。图7和图8分别示意出了一种集成电路的结构。图7和图8均以功能层2包括电子器件21及位于电子器件远离衬底1一侧的互连层22为例进行说明。电子器件21与互连层22之间电连接。
示例性的，电子器件21包括但不限于晶体管、电容器、电感器等。图7和图8中以晶体管代 表电子器件21为例，该晶体管包括栅极、源极和漏极。
示例性的，互连层22包括多个导电层。例如，图7和图8示意出了四个导电层。部分导电层中设置有金属走线，部分导电层中设置有导电图案，该导电图案用于连接电子器件和相应的金属走线，或用于连接不同导电层中的走线。
在一些示例中，如图7和图8所示，集成电路100还包括：介质键合层3和多个键合图案4。该介质键合层3位于功能层2上。在功能层2包括电子器件21和互连层22的情况下，介质键合层3位于互连层22远离电子器件21的一侧。上述多个键合图案4位于介质键合层3内，基本未凸出于介质键合层3远离衬底1的一侧表面。该多个键合图案4中的至少部分键合图案4会贯穿介质键合层3，并延伸至功能层2，与功能层2电连接。例如，键合图案4与互连层22中的金属走线或导电图案相接触，形成电连接。
上述多个键合图案4的排列方式可以根据实际需要选择设置。可选地，该多个键合图案4呈阵列状排布，相邻两个键合图案4之间具有较小的间距，以实现更细间距的互连。
示例性的，如图7和图8所示，键合图案4包括导电部41，导电部41与功能层2电连接。导电部41的材料包括金属材料，且性质较为活泼，具有较小的电阻和较好的抗电迁移和导热性能。
示例性的，如图7和图8所示，键合图案4还包括金属钝化层42，该金属钝化层42位于导电部41上，也即，金属钝化层42位于导电部41远离衬底1的一侧表面上。同一键合图案4中，金属钝化层42覆盖导电部41或覆盖导电部41的一部分，且与导电部41相接触。也即，导电部41和金属钝化层42沿垂直且远离衬底1的方向依次排列，导电部41在衬底1上的正投影与金属钝化层42在衬底1上的正投影至少部分重合。
可选地，在垂直于衬底1的方向上，导电部41的厚度(或称高度)大于金属钝化层42的厚度。
上述导电部41的材料和金属钝化层42的材料构成的合金的熔点，低于导电部41的材料的熔点。
可以理解的是，导电部41和金属钝化层42相接触。在热的作用下，导电部41的材料会向金属钝化层42中扩散，金属钝化层42的材料会向导电部41中扩散，这样便可以在键合图案4远离衬底1的一侧形成合金层。由于导电部41的材料和金属钝化层42的材料构成的合金的熔点，低于导电部41的材料的熔点，这样在将不同(例如两个)集成电路100进行混合键合的过程中，便可以利用该合金层的更低熔点，在较低的热处理温度中，实现键合图案4的互熔、键合。在此基础上，还可以改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题。
由此，本申请的一些实施例提供的集成电路100，通过在功能层2上设置介质键合层3，并设置位于介质键合层3内、且与功能层2电连接的多个键合图案4，可以使得集成电路100能够采用混合键合的方式与其他的集成电路100形成互连，提高互连形成的三维集成电路的可靠性。
而且，本申请实施例通过在键合图案4中设置导电部41，并设置覆盖导电部41的至少一部分的金属钝化层42，可以利用导电部41和金属钝化层42所形成的合金层的物理性质，也即，该合金层的熔点低于导电部41的材料的熔点的性质，降低键合图案4的键合温度，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层42对导电部41的表面进行抗氧化保护，降低热处理对导电部41的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
在一些实施例中，导电部41的材料在金属钝化层42中的晶界扩散系数，大于金属钝化层42的材料在导电部41中的晶界扩散系数。也即，导电部41的材料在金属钝化层42的体相中扩散得较快，金属钝化层42的材料在导电部41的体相中扩散得较慢。
这样可以使得导电部41和金属钝化层42所形成的合金层主要位于键合图案4的顶端(也即远离衬底1的一端)，金属钝化层42的材料仅扩散至导电部41的顶端。
例如，对相键合的两个集成电路100的键合界面进行切片，从其切面的TEM(transmission  electron microscope，透射电子显微镜)图像或者其对应的EDX(energy dispersive X-Ray spectroscopy，能量色散X射线光谱仪)结果表征中可以看出，导电部41的材料会扩散至金属钝化层42整体，甚至会扩散至金属钝化层42远离衬底1的一侧表面上，而金属钝化层42的材料仅扩散至导电部41的顶端。
这样既能够利用该合金层降低混合键合过程中热处理的温度，又能够利用导电部41的良好电学性能(例如较小的电阻和较好的抗电迁移和导热性能)，保障互连形成的三维集成电路的电学性能，降低合金层对三维集成电路的电学性能的影响。
在一些实施例中，如图7和图8所示，介质键合层3远离衬底1的一侧表面为平整的表面或大致平整的表面。相比于衬底1，金属钝化层42远离衬底1的一侧表面的至少一部分，低于介质键合层3远离衬底1的一侧表面。也即，金属钝化层42远离衬底1的一侧表面整体，低于介质键合层3远离衬底1的一侧表面；或者，金属钝化层42远离衬底1的一侧表面的边界与介质键合层3远离衬底1的一侧表面齐平，金属钝化层42远离衬底1的一侧表面其余部分，低于介质键合层3远离衬底1的一侧表面。
金属钝化层42远离衬底1的一侧表面，与介质键合层3远离衬底1的一侧表面所在水平面之间形成一定的空间。这样在进行混合键合、且集成电路100处于热处理的过程中，可以利用上述空间，为导电部41的受热膨胀提供一定的缓冲，既可以避免顶裂晶圆，还可以避免已键合的介质键合层3分离，提高互连形成的三维集成电路的结构可靠性。
在一些示例中，如图7和图8所示，金属钝化层42远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。
示例性的，金属钝化层42远离衬底1的一侧表面呈碗装、盘状或凹槽状。这样便于制备形成金属钝化层42。
在一些实施例中，如图7和图8所示，相比于衬底1，导电部41远离衬底1的一侧表面，低于介质键合层3远离衬底1的一侧表面。
在垂直于衬底1的方向上，导电部41远离衬底1的一侧表面，与介质键合层3远离衬底1的一侧表面之间具有一定的间距。
这样可以为位于导电部41上的金属钝化层42预留设置空间，确保金属钝化层42整体能够相对于衬底1，低于介质键合层3远离衬底1的一侧表面，进而为导电部41的受热膨胀提供缓冲空间。
在一些示例中，如图7和图8所示，导电部41远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。
示例性的，导电部41远离衬底1的一侧表面呈碗装、盘状或凹槽状。这样便于制备形成导电部41。
在一些实施例中，导电部41的材料包括铜，金属钝化层42的材料包括镍、钛、锡、银、金或钯。
导电部41和金属钝化层42，能够在键合图案4的顶端扩散形成铜镍二元合金、铜钛二元合金、铜锡二元合金、铜银二元合金、铜金二元合金或铜钯二元合金等，该多种二元合金的熔点均低于导电部41的熔点。这样可以确保键合图案4的键合的温度的降低，或混合键合热处理温度的降低，进而能够有效改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题。
在一些实施例中，介质键合层3的材料包括但不限于氮化硅(SiNX)、氮碳化硅(SiCN)、氧化硅(SiO2)。
在一些实施例中，如图8所示，键合图案4还包括：籽晶层43和阻挡层44。籽晶层43环绕导电部41，且位于导电部41和介质键合层3之间。阻挡层44环绕籽晶层43，且位于籽晶层43和介质键合层3之间。
在一些示例中，籽晶层43围绕导电部41的侧面，并与导电部41的底部相接触。阻挡层44围绕籽晶层43的侧面，并与籽晶层43的底部相接触。导电部41依次通过籽晶层43和阻挡层44与功能层2电连接。
示例性的，上述籽晶层43的材料包括铜，可作为被镀基体金属，在电镀的过程中，在籽晶层43表面生长铜，以形成导电部41。通常，籽晶层43中的铜的晶粒的平均直径，要小于导电部41中的铜的晶粒的平均直径。
示例性的，阻挡层44可将籽晶层43粘附在介质键合层3上，从而保证籽晶层43和导电部41与介质键合层3的稳定连接。并且，阻挡层44可将籽晶层43与介质键合层3隔开，可避免籽晶层43与介质键合层3直接接触而发生铜扩散，从而提高集成电路100的产品可靠性。
可选地，阻挡层44的材料包括钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)中的至少一种，使其具有阻挡力。
本申请的发明人经研究发现，目前部分领域实现了在面铜上沉积异质金属的方案，但受限于制备工艺，难以实现异质金属的选择性构建，从而难以应用于混合键合中。而且，目前特定区域选择性沉积异质金属的技术方案主要是采用选区原子层沉积(area-selective atomic layer deposition，AS-ALD)工艺，也即，主要通过自组装单层膜法(self-assembly monolayers，SAMs)和聚合物法的方式去钝化或者活化特定区域，然后使得前驱体与这些区域有不同于原表面的反应活性。该选择性沉积过程涉及到使用二乙烯三胺基丙基三甲氧基硅烷(trimethoxysilyl propyl diethylenetriamine，DETA)作为SAMs前驱体，使用二甲胺硼烷(p-dimethylaminobenzaldehyde，DMAB)、氯化铵作为金属钯还原剂，使用乙二胺(ethylenediamine，EDA)作为络合剂。但是，目前上述特定区域选择性沉积异质金属的技术方案，尚未应用于3D IC领域，也未应用于3D IC的混合键合中。因为该特定区域选择性沉积异质金属的技术方案，会引入大量的有机物质和溶剂，因此会涉及到复杂的后处理去除有机物过程，严重影响3D IC的制备效率，成为量产3D IC的严重阻碍。而且，上述特定区域选择性沉积异质金属的技术方案，将对混合键合的界面产生巨大的碳残留和杂质污染，进而会严重影响键合的效果。
基于此，本申请的一些实施例提供了一种集成电路的制备方法。该制备方法例如用于制备形成如上述一些实施例中任一项所述的集成电路。图9为一些实施例中的制备一种集成电路的流程图；图10a～图10f为一些实施例的制备一种集成电路的各步骤图。
如图9所示，上述制备方法包括：S110～S130。
S110，如图10a所示，在衬底1上依次形成功能层2和介质键合层3，介质键合层3具有多个混合键合通孔G，混合键合通孔G暴露功能层2的部分表面。
上述衬底1的材料，功能层2的结构，及介质键合层3的结构、材料等，可以参见上文中的说明，此处不再赘述。
示例性的，在上述S100a中，在衬底1上依次形成功能层2和介质键合层3包括：如图11a所示，提供衬底1，并采用RCA标准清洗法(RCA clean)对衬底1进行清洗；如图11b所示，采用包括但不限于沉积工艺、光刻工艺、干刻工艺等在衬底1上形成功能层2；如图11c所示，采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积)工艺在功能层2上沉积一层介质薄膜3a；如图11d所示，在该介质薄膜3a上涂覆形成一光刻胶层，然后采用光刻工艺(lithography)对该光刻胶层进行曝光、显影，形成具有多个开口的光刻胶层PR；如图11e所示，以具有多个开口的光刻胶层PR为掩膜，对介质薄膜进行刻蚀(etching)，形成暴露功能层2的部分表面的多个混合键合通孔G，得到介质键合层3。例如，至少部分混合键合通孔G贯穿介质键合层3。
可选地，本申请实施例还可以采用双大马士革工艺形成上述混合键合通孔G，其中，如图10a所示，混合键合通孔G包括靠近功能层2一侧的通孔，及与该通孔连通、且位于通孔远离功能层2一侧的沟槽。本申请实施例以图10a所示的混合键合通孔G为例进行示意性说明。
S120，如图10e所示，在混合键合通孔G内形成导电部41，导电部41与功能层2电连接，得到初始集成电路。
示例性的，本申请实施例可以采用包括但不限于电化学沉积(electro-chemical plating，ECP)工艺、化学机械研磨(chemical-mechanical polishing，CMP)工艺形成导电部41。
S130，如图10f所示，将初始集成电路置于处理气体中，该处理气体包括金属羰基有机化合物前驱体蒸汽，以在导电部41上选择性沉积金属钝化层42。其中，导电部41的材料和金属钝化 层42的材料构成的合金的熔点，低于导电部41的材料的熔点。
示例性的，本申请实施例可以将上述处理气体置于相关设备的处理室中，该相关设备例如为化学气相沉积(chemical vapor deposition，CVD)设备，上述金属羰基有机化合物前驱体可以称为CVD反应前驱体。
导电部41对羰基的吸附能力，大于介质键合层3对羰基的吸附能力。在将初始集成电路置于处理气体中后，也即，将初始集成电路置于充满处理气体的CVD设备后，基于金属羰基有机化合物前驱体中的羰基和导电部41表面的强吸附能力，金属羰基有机化合物前驱体主要会沉积在导电部41远离衬底1的一侧表面上，表现出选择性沉积金属羰基有机化合物前驱体对导电部41远离衬底1的一侧表面和介质键合层3远离衬底1的一侧表面的高选择比。在高温环境下，上述金属羰基有机化合物前驱体会发生热分解(或可以理解为发生氧化还原反应)，并在导电部41远离衬底1的一侧表面上析出金属羰基有机化合物前驱体中的金属，从而实现异质金属高选择性沉积。在导电部41远离衬底1的一侧表面上沉积的金属构成金属钝化层42。
可以理解的是，在将不同(例如两个)集成电路100进行混合键合的过程中，会经过热处理(例如退火处理)。导电部41的材料会在热的作用下向金属钝化层42中扩散，从而使得键合图案4远离衬底1的一侧形成合金层。由于导电部41的材料和金属钝化层42的材料构成的合金的熔点，低于导电部41的材料的熔点，这样便可以在较低的热处理温度中，实现键合图案4的互熔、键合。
由此，本申请的一些实施例提供的集成电路的制备方法，通过将上述处置集成电路置于包括金属羰基有机化合物前驱体蒸汽中，可以采用金属羰基有机化合物前驱体作为CVD反应前驱体，并利用金属羰基有机化合物前驱体对导电部41和介质键合层3的高选择比，实现异质金属高选择性沉积，进而可以利用导电部41和金属钝化层42所形成的合金层的物理性质，也即，该合金层的熔点低于导电部41的材料的熔点的性质，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层42对导电部41的表面进行抗氧化保护，降低热处理对导电部41的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
另外，上述制备方法未引入有机物质和溶剂，不仅在选择性沉积形成金属钝化层42之后，无需涉及复杂的后处理去除有机物过程，避免影响3D IC的制备效率，还可以避免在混合键合的界面产生碳残留和杂质污染，避免影响键合的效果。
上述制备方法可实现全程后道工艺(back end of line，BEOL)，且上述制备方法所采用的工艺成本较低，效率较高。
在一些实施例中，上述金属钝化层42的厚度的范围为10nm～30nm。该厚度指的是在垂直衬底1的方向上，金属钝化层42的最大尺寸或平均尺寸。
可选地，金属钝化层42的厚度为10nm、12nm、16nm、21nm、25nm或30nm等。
采用上述厚度范围，可以在不同集成电路的混合键合的热处理过程中，使得导电部41的材料在金属钝化层42中具有较好的扩散效果，进而使得导电部41和金属钝化层42所形成的合金层，能够有效降低热处理的温度。
示例性的，通过调节CVD工艺的能量、时间等参数，可以调节选择性沉积在导电部41上的金属钝化层42的厚度。可以理解的是，上述导电部41的材料，在不同金属中的晶界扩散系数不同。相应的，金属羰基有机化合物前驱体中金属的不同，选择性沉积形成的金属钝化层42的厚度可以相同，也可以不同，具体可以根据需要选择设置。
在一些实施例中，导电部41的材料包括铜，金属羰基有机化合物前驱体包括但不限于Ni(CO)4(四羰基镍)。
铜和羰基之间的吸附能力，大于介质键合层3和羰基之间的吸附能力。在上述S130中，Ni(CO)4基本上沉积在铜上，并在高温环境下发生热分解，进而在导电部41远离衬底1的一侧表面上析出Ni(镍)，实现异质金属镍的高选择性沉积。其中，Ni(CO)4发生热分解的方程式为：
Ni(CO)4→Ni+4CO。
铜镍二元合金的熔点低于铜的熔点，且铜在镍中的晶界扩散系数，大于镍在铜中的晶界扩散系数。采用铜形成导电部41，并采用镍形成金属钝化层42，可以使得导电部41和金属钝化层42形成的合金层位于键合图案4的顶端，进而能够利用位于键合图案4顶端的合金层降低热处理的温度。
可以理解的是，金属羰基有机化合物前驱体并不局限于Ni(CO)4，任何金属羰基有机化合物前驱体和适用于PVD设备或CVD设备的金属靶材均可应用于上述制备方法。
在一些实施例中，在上述S120中，在混合键合通孔G内形成导电部41，包括：S121～S122。
S121，如图10d所示，在混合键合通孔G内和介质键合层3上形成导电薄膜41a。
上述“介质键合层3上”指的是，介质键合层3远离衬底1的一侧表面上。
本申请实施例可以采用包括但不限于ECP工艺形成导电薄膜41a。导电薄膜41a远离衬底1的一侧表面例如为较为平整的表面。
S122，如图10e所示，对导电薄膜41a进行第一研磨处理，去除导电薄膜41a中位于介质键合层3上的部分，保留导电薄膜41a中位于混合键合通孔G内的部分，得到导电部41。相比于衬底1，导电部41远离衬底1的一侧表面，低于介质键合层3远离衬底1的一侧表面。
示例性的，本申请实施例可以采用CMP工艺对导电薄膜41a进行第一研磨处理，所采用的CMP研磨液对介质键合层3和导电薄膜41a，具有超高选择比。在对导电薄膜41a进行研磨的过程中，是会对导电薄膜41a整个表面进行研磨的，因此，还会去除导电薄膜41a中位于混合键合通孔G上的部分，并使得保留于混合键合通孔G内的部分，相比于衬底1低于介质键合层3。
对导电薄膜41a进行研磨后，导电部41的形貌例如如图10e所示，导电部41远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。该凹陷又可以称为蝶形凹陷。
利用对介质键合层3和导电薄膜41a具有超高选择比的CMP研磨液，可以实现蝶形凹陷结构的构建，进而可以为后续沉积于导电部41上的金属钝化层42预留空间，确保金属钝化层42整体能够相对于衬底1，低于介质键合层3远离衬底1的一侧表面，进而为导电部41的受热膨胀提供缓冲空间。
在一些示例中，在垂直于衬底1的方向上，导电部41远离衬底1的一侧表面，与介质键合层3远离衬底1的一侧表面之间的最大间距的范围为10nm～30nm。
可选地，上述最大间距可以为10nm、13nm、15nm、21nm、25nm或30nm等。
在一些示例中，在上述S122之后，制备方法还包括：S123。
S123，对介质键合层3远离衬底1的一侧表面进行平坦化处理。
示例性的，本申请实施例可以采用CMP工艺对介质键合层3远离衬底1的一侧表面进行研磨抛光。在上述S122中，对导电薄膜41a进行第一研磨处理时，可能会增大介质键合层3的表面粗糙度。通过对介质键合层3远离衬底1的一侧表面进行平坦化处理，可以减小介质键合层3的表面粗糙度，提高介质键合层3远离衬底1的一侧表面的平整度。
这样在将不同集成电路进行混合键合的过程中，可以满足对于键合界面的平坦化需求，避免键合形成的三维集成电路的键合界面出现大量的弥散气泡，提高键合效果。
例如，对相键合的两个集成电路100，从其CSAM(confocal scanning acoustic microscopy，共焦扫描声学显微镜)表征结果中可以看出，键合界面基本没有弥散起泡。也就是说，对介质键合层3远离衬底1的一侧表面进行平坦化处理之后，可以有效提高不同集成电路100的键合效果。
可选地，上述S123中所采用的CMP研磨液与上述S122中采用的CMP研磨液可以相同，也可以不同。在两者相同的情况下，可以通过调节压力等参数，实现对介质键合层3远离衬底1的一侧表面进行平坦化处理。在两者不同的情况下，可以两者的选择比可以不同，以实现对介质键合层3远离衬底1的一侧表面进行平坦化处理。
在一些实施例中，在上述S130之后，制备方法还包括：S140。
S140，对金属钝化层42和介质键合层3远离衬底1的一侧表面进行第二研磨处理。相比于衬底1，金属钝化层42远离衬底1的一侧表面的至少一部分，低于介质键合层3远离衬底1的一侧表面。
示例性的，本申请实施例可以采用CMP工艺对金属钝化层42和介质键合层3进行第二研磨 处理，第二研磨处理中采用的研磨垫例如为硬质研磨垫。第二研磨处理又可以称为轻抛光处理。
对金属钝化层42和介质键合层3进行第二研磨处理后，金属钝化层42的表面粗糙度有所降低。金属钝化层42的形貌例如图10f所示，金属钝化层42远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。该凹陷又可以称为蝶形凹陷。
这样在将不同的集成电路进行混合键合时，可以利用上述凹陷，为导电部41的受热膨胀提供一定的缓冲，既可以避免顶裂晶圆，还可以避免已键合的介质键合层3分离，提高互连形成的三维集成电路的结构可靠性。
可选地，在上述S130中，例如可以通过调节CVD工艺的能量、时间等参数，使得选择形成的金属钝化层42远离衬底1的一侧表面，相对于衬底1低于介质键合层3远离衬底1的一侧表面，使得金属钝化层42呈凹陷状态。在上述S140中，经过轻抛光处理后，可以加深该凹陷的深度，从而能够进一步地为不同集成电路混合键合时，导电部41的受热膨胀提供缓冲空间。
在一些实施例中，在上述S121之前，也即，在混合键合通孔G内和介质键合层3上形成导电薄膜41a之前，如图10b和图10c所示，制备方法还包括：在混合键合通孔G内和介质键合层3上，依次形成阻挡薄膜44a和籽晶薄膜43a。在S121中形成的导电薄膜41a则位于籽晶薄膜43a上。
示例性的，本申请实施例可以采用沉积工艺(包括但不限于物理气相沉积、化学气相沉积等)形成阻挡薄膜44a和籽晶薄膜43a。沉积形成阻挡薄膜44a(barrier layer deposition)后的结构如图10b所示，沉积形成籽晶薄膜43a(seed layer deposition)后的结构如图10c所示。
阻挡薄膜44a的材料例如可以包括钛、氮化钛、钽、氮化钽等。籽晶薄膜43a的材料例如可以包括钛、铜、镍、钴、钨或相关合金中的一种或多种。
形成的阻挡薄膜44a可以避免籽晶薄膜43a和导电薄膜41a中的金属扩散到介质键合层3中。形成的籽晶薄膜43a可以便于后续采用ECP工艺形成导电薄膜41a。
在一些示例中，如图10e所示，在上述S122中，也即，在对导电薄膜41a进行第一研磨处理的过程中，还对籽晶薄膜43a和阻挡薄膜44a进行第一研磨处理，去除籽晶薄膜43a和阻挡薄膜44a位于介质键合层3上的部分，保留籽晶薄膜43a和阻挡薄膜44a位于混合键合通孔内G的部分，得到籽晶层43和阻挡层44。籽晶层43环绕导电部41，阻挡层44环绕籽晶层43。
对导电薄膜41a、籽晶薄膜43a和阻挡薄膜44a进行研磨后，导电部41、籽晶层43和阻挡层44的形貌例如如图10e所示，阻挡层44远离的顶端例如与介质键合层3远离衬底1的一侧表面齐平，导电部41和籽晶层43两者远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。后续在该凹陷内形成的金属钝化层42，例如还覆盖籽晶层43。
本申请的一些实施例还提供了一种集成电路的制备方法。该制备方法例如用于制备形成如上述一些实施例中任一项所述的集成电路100。图12为一些实施例中的制备一种集成电路的流程图；图13a～图13g为一些实施例的制备一种集成电路的各步骤图。
如图12所示，上述制备方法包括：S210～S240。
S210，如图13a所示，在衬底1上依次形成功能层2和介质键合层3，介质键合层3具有多个混合键合通孔G，混合键合通孔G暴露功能层2的部分表面。
上述衬底1的材料，功能层2的结构，及介质键合层3的结构、材料等，可以参见上文中的说明，此处不再赘述。
示例性的，关于功能层2和介质键合层3的形成方法，可以参见上述S110中的说明，此处不再赘述。
示例性的，上述介质键合层3的材料包括但不限于氮化硅、氮碳化硅、氧化硅。
S220，如图13e所示，在混合键合通孔G内形成导电部41，导电部41与功能层2电连接。相比于衬底1，导电部41远离衬底1的一侧表面，低于介质键合层3远离衬底1的一侧表面。
示例性的，本申请实施例可以采用包括但不限于电化学沉积(electro-chemical plating，ECP)工艺、化学机械研磨(chemical-mechanical polishing，CMP)工艺形成导电部41。
通过使得导电部41远离衬底1的一侧表面，相比于衬底1低于介质键合层3远离衬底1的一侧表面，可以使得在S240中形成的金属钝化薄膜42a中位于导电部41上的部分具有一定的厚度。
S230，如图13f所示，在导电部41上和介质键合层3上形成金属钝化薄膜42a。金属钝化薄膜42a中位于导电部41上的部分的厚度，大于金属钝化薄膜42a中位于介质键合层3上的部分的厚度。
示例性的，本申请实施例可以采用沉积工艺形成金属钝化薄膜42a。金属钝化薄膜42a呈面状，既覆盖导电部41，又覆盖介质键合层3。
由于导电部41远离衬底1的一侧表面，相比于衬底1低于介质键合层3远离衬底1的一侧表面，因此，可以在导电部41上沉积更多的金属材料，使得金属钝化薄膜42a为厚度不均一的膜层，且相比于金属钝化薄膜42a中位于介质键合层3上的部分，金属钝化薄膜42a中位于导电部41上的部分更厚。
S240，如图13g所示，对金属钝化薄膜42a进行第三研磨处理，去除金属钝化薄膜42a位于介质键合层3上的部分，保留金属钝化薄膜42a位于导电部41上的部分，得到金属钝化层42。其中，导电部41的材料和金属钝化层42的材料构成的合金的熔点，低于导电部41的材料的熔点。
示例性的，本申请实施例可以采用CMP工艺对金属钝化薄膜42a进行第三研磨处理，第三研磨处理中采用的研磨垫例如为硬质研磨垫，对金属钝化薄膜42a的不同位置的去除例如为等量去除。
在对金属钝化薄膜42a进行研磨的过程中，可以控制研磨的压力，并通过抓取截止信号的方式，完成对金属钝化薄膜42a的第三研磨处理。该截止信号例如来自研磨设备的参数，具体可以表现为研磨至介质键合层3远离衬底1的一侧表面，去除位于介质键合层3远离衬底1的一侧表面上的金属则停止研磨。由于金属钝化薄膜42a中位于导电部41上的部分的厚度，大于金属钝化薄膜42a中位于介质键合层3上的部分的厚度，因此，在去除金属钝化薄膜42a位于介质键合层3上的部分之后，可以仅保留位于金属钝化薄膜42a位于导电部41上的部分，该部分构成金属钝化层42。
示例性的，对金属钝化薄膜42a进行第三研磨处理后，金属钝化层42的形貌例如图13f所示，金属钝化层42远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。该凹陷又可以称为蝶形凹陷。该蝶形凹陷的量(dishing量)小于或等于5nm，以确保后续不同集成电路进行混合键合时，键合图案4能够互熔，避免出现因未互熔而断路的情况。
可以理解的是，在将不同(例如两个)集成电路100进行混合键合的过程中，会经过热处理(例如退火处理)。导电部41的材料会在热的作用下向金属钝化层42中扩散，从而使得键合图案4远离衬底1的一侧形成合金层。由于导电部41的材料和金属钝化层42的材料构成的合金的熔点，低于导电部41的材料的熔点，这样便可以在较低的热处理温度中，实现键合图案4的互熔、键合。
由此，本申请的一些实施例提供的集成电路的制备方法，通过在介质键合层3中形成导电部41，并使得导电部41远离衬底1的一侧表面，相比于衬底1低于介质键合层3远离衬底1的一侧表面，并在后续形成的金属钝化薄膜42a中位于导电部41上的部分的厚度，大于金属钝化薄膜42a中位于介质键合层3上的部分的厚度，可以在对金属钝化薄膜42a进行第三研磨处理之后，保留金属钝化薄膜42a位于导电部41上的部分，得到金属钝化层42，实现异质金属的选择性沉积，进而可以利用导电部41和金属钝化层42所形成的合金层的物理性质，也即，该合金层的熔点低于导电部41的材料的熔点的性质，降低混合键合过程中热处理的温度。
在此基础上，可以利用金属钝化层42对导电部41的表面进行抗氧化保护，降低热处理对导电部41的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
另外，上述制备方法未引入有机物质和溶剂，不仅在选择性沉积形成金属钝化层42之后，无需涉及复杂的后处理去除有机物过程，避免影响3D IC的制备效率，还可以避免在混合键合的界面产生碳残留和杂质污染，避免影响键合的效果。
上述制备方法可实现全程后道工艺(back end of line，BEOL)，且上述制备方法所采用的工艺成本较低，效率较高。
在一些实施例中，金属钝化薄膜42a中位于导电部41上的一部分的厚度的范围为10nm～60nm。
可选地，金属钝化薄膜42a中位于导电部41上的一部分的厚度为10nm、19nm、25nm、38nm、55nm或60nm等。
采用上述厚度范围，可以在对金属钝化薄膜42a进行第三研磨处理后，保留在导电部41上的一部分仍具有一定的厚度，进而在不同集成电路的混合键合的热处理过程中，使得导电部41的材料在金属钝化层42中具有较好的扩散效果，进而使得导电部41和金属钝化层42所形成的合金层，能够有效降低热处理的温度。
在一些实施例中，导电部41的材料包括铜，金属钝化层42材料包括钛、锡、银、金或钯。
铜钛二元合金的熔点低于铜的熔点，且铜在钛中的晶界扩散系数，大于钛在铜中的晶界扩散系数；铜锡二元合金的熔点低于铜的熔点，且铜在锡中的晶界扩散系数，大于锡在铜中的晶界扩散系数；铜银二元合金的熔点低于铜的熔点，且铜在银中的晶界扩散系数，大于银在铜中的晶界扩散系数；铜金二元合金的熔点低于铜的熔点，且铜在金中的晶界扩散系数，大于金在铜中的晶界扩散系数；铜钯二元合金的熔点低于铜的熔点，且铜在钯中的晶界扩散系数，大于钯在铜中的晶界扩散系数。
采用铜形成导电部41，并采用钛、锡、银、金或钯等形成金属钝化层42，可以使得导电部41和金属钝化层42形成的合金层位于键合图案4的顶端，进而能够利用位于键合图案4顶端的合金层降低热处理的温度。
在一些实施例中，在上述S220中，在混合键合通孔G内形成导电部41，包括：S221～S222。
S221，如图13d所示，在混合键合通孔G内和介质键合层3上形成导电薄膜41a。
本申请实施例可以采用包括但不限于ECP工艺形成导电薄膜41a。导电薄膜41a远离衬底1的一侧表面例如为较为平整的表面。
S222，如图13e所示，对导电薄膜41a进行第一研磨处理，去除导电薄膜41a中位于介质键合层3上的部分，保留导电薄膜41a中位于混合键合通孔G内的部分，得到导电部41。
示例性的，本申请实施例可以采用CMP工艺对导电薄膜41a进行第一研磨处理，所采用的CMP研磨液对介质键合层3和导电薄膜41a，具有超高选择比。在对导电薄膜41a进行研磨的过程中，是会对导电薄膜41a整个表面进行研磨的，因此，还会去除导电薄膜41a中位于混合键合通孔G上的部分，并使得保留于混合键合通孔G内的部分，相比于衬底1低于介质键合层3。
对导电薄膜41a进行研磨后，导电部41的形貌例如如图13e所示，导电部41远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。该凹陷又可以称为蝶形凹陷。
利用对介质键合层3和导电薄膜41a具有超高选择比的CMP研磨液，可以实现蝶形凹陷结构的构建，进而可以为后续沉积于导电部41上的金属钝化薄膜42a预留空间，确保金属钝化薄膜42a中位于导电部41上的部分的厚度，大于金属钝化薄膜42a中位于介质键合层3上的部分的厚度。
在一些示例中，在垂直于衬底1的方向上，导电部41远离衬底1的一侧表面，与介质键合层3远离衬底1的一侧表面之间的最大间距的范围为20nm～70nm。
可选地，上述最大间距可以为20nm、30nm、35nm、43nm、59nm或70nm等。
在一些示例中，在上述S222之后，制备方法还包括：S223。
S223，对介质键合层3远离衬底1的一侧表面进行平坦化处理。
示例性的，本申请实施例可以采用CMP工艺对介质键合层3远离衬底1的一侧表面进行研磨抛光。在上述S222中，对导电薄膜41a进行第一研磨处理时，可能会增大介质键合层3的表面粗糙度。通过对介质键合层3远离衬底1的一侧表面进行平坦化处理，可以减小介质键合层3的表面粗糙度，提高介质键合层3远离衬底1的一侧表面的平整度。
这样在将不同集成电路进行混合键合的过程中，可以满足对于键合界面的平坦化需求，避免键合形成的三维集成电路的键合界面出现大量的弥散气泡，提高键合效果。
可选地，上述S223中所采用的CMP研磨液与上述S222中采用的CMP研磨液可以相同，也可以不同。在两者相同的情况下，可以通过调节压力等参数，实现对介质键合层3远离衬底1的一侧表面进行平坦化处理。在两者不同的情况下，可以两者的选择比可以不同，以实现对介质键 合层3远离衬底1的一侧表面进行平坦化处理。
在一些实施例中，在上述S230中，在导电部41上和介质键合层3上形成金属钝化薄膜42a，包括：采用离子化物理气相沉积(ionized physical vapor deposition，iPVD)工艺，在导电部41上和介质键合层3上沉积金属钝化材料，形成金属钝化薄膜42a。
示例性的，在形成金属钝化薄膜42a时，可以将待形成的集成电路置于PVD(physical vapor deposition，物理气相沉积)设备中，通过iPVD技术调节能量、时间等参数，在导电部41上和介质键合层3上沉积形成具有一定厚度的金属钝化薄膜42a。
图14示意出了采用PVD工艺在凹槽内沉积形成金属膜层的一种结构，图15示意出了采用iPVD工艺在凹槽内沉积形成金属膜层的一种结构。由图14和图15可知，采用PVD工艺形成的金属膜层的厚度均一，不同位置处的厚度基本一致，采用iPVD工艺形成的金属膜层的厚度不均一，该金属膜层位于凹槽内的部分的厚度更大。这也就意味着，如果采用PVD工艺形成金属钝化薄膜42a，那么在对金属钝化薄膜42a进行第三研磨处理之后，难以保留金属钝化薄膜42a位于导电部41上的部分，也就难以得到金属钝化层42。而采用iPVD工艺形成的金属钝化薄膜42a，能够满足其位于导电部41上的部分的厚度，大于其位于介质键合层3上的部分的厚度，这样在对金属钝化薄膜42a进行第三研磨处理之后，则能够保留金属钝化薄膜42a位于导电部41上的部分，实现异质金属的选择性沉积。
另外，图16示意出了对金属钝化薄膜42a进行第三研磨处理的一种过程，通过控制CMP工艺的不同参数，使得金属钝化薄膜42a中位于导电部41上的部分的表面，基本完全被其吸引的正电荷和负电荷覆盖，进而使得CMP研磨液中的研磨颗粒(abrasive)5难以到达该部分金属的表面。这样可以减小金属钝化薄膜42a中位于导电部41上的部分的研磨量，使得金属钝化薄膜42a中位于导电部41上的部分的研磨量，小于金属钝化薄膜42a中位于介质键合层3上的部分的研磨量，从而在研磨去除金属钝化薄膜42a中位于介质键合层3上的部分后，保留下来金属钝化层42的厚度更大，在实现异质金属的选择性沉积的基础上，确保金属钝化层42的厚度。
在一些实施例中，在上述S231之前，也即，在混合键合通孔G内和介质键合层3上形成导电薄膜41a之前，如图13b和图13c所示，制备方法还包括：在混合键合通孔G内和介质键合层3上，依次形成阻挡薄膜44a和籽晶薄膜43a。在S121中形成的导电薄膜41a则位于籽晶薄膜43a上。
示例性的，本申请实施例可以采用沉积工艺(包括但不限于物理气相沉积、化学气相沉积等)形成阻挡薄膜44a和籽晶薄膜43a。沉积形成阻挡薄膜44a(barrier layer deposition)后的结构如图13b所示，沉积形成籽晶薄膜43a(seed layer deposition)后的结构如图13c所示。
阻挡薄膜44a的材料例如可以包括钛、氮化钛、钽、氮化钽等。籽晶薄膜43a的材料例如可以包括钛、铜、镍、钴、钨或相关合金中的一种或多种。
形成的阻挡薄膜44a可以避免籽晶薄膜43a和导电薄膜41a中的金属扩散到介质键合层3中。形成的籽晶薄膜43a可以便于后续采用ECP工艺形成导电薄膜41a。
在一些示例中，如图13d和图13e所示，在上述S232中，也即，在对导电薄膜41a进行第一研磨处理的过程中，还对籽晶薄膜43a和阻挡薄膜44a进行第一研磨处理，去除籽晶薄膜43a和阻挡薄膜44a位于介质键合层3上的部分，保留籽晶薄膜43a和阻挡薄膜44a位于混合键合通孔内G的部分，得到籽晶层43和阻挡层44。籽晶层43环绕导电部41，阻挡层44环绕籽晶层43。
对导电薄膜41a、籽晶薄膜43a和阻挡薄膜44a进行研磨后，导电部41、籽晶层43和阻挡层44的形貌例如如图13e所示，阻挡层44远离的顶端例如与介质键合层3远离衬底1的一侧表面齐平，导电部41和籽晶层43两者远离衬底1的一侧表面呈弧面状，且向靠近衬底1的方向凹陷。后续在该凹陷内形成的金属钝化层42，例如还覆盖籽晶层43。
本申请的一些实施例还提供了一种三维集成电路。图17～图19分别示意出了一种三维集成电路的结构。
如图17～图19所示，三维集成电路16包括：相对设置的第一集成电路100a和第二集成电路100b。其中，第一集成电路100a和第二集成电路100b为上述任一实施例所述的集成电路100。
示例性的，第一集成电路100a中的键合图案4与第二集成电路100b中的键合图案4相键合， 第一集成电路100a的介质键合层3与第二集成电路100b的介质键合层3相键合，以实现第一集成电路100a和第二集成电路100b的键合。
由上述任一实施例，键合图案4包括导电部41和位于导电部41上的金属钝化层42。在将上述第一集成电路100a和第二集成电路100b进行混合键合的过程中，两者的介质键合层3可以产生较强的物理键合，两者的导电部41的材料会在热的作用下向相应的金属钝化层42中扩散，形成合金层，并通过合金层的互熔键合在一起。
本申请实施例所提供的三维集成电路16所能实现的有益效果与上述一些实施例中提供的集成电路100所能实现的有益效果相同，此处不再赘述。
可以理解的是，在高温环境下，氮化硅或氮碳化硅对导电部41的材料具有较高的阻挡能力，能够阻挡导电部41的材料向介质键合层3的扩散；而氧化硅对导电部41的材料的阻挡能力较低，难以阻挡导电部41的材料向介质键合层3的扩散。
示例性的，三维集成电路16具有参考平面，该参考平面为第一集成电路100a的衬底1远离第二集成电路100b的一侧表面。
在一些实施例中，第一集成电路100a的介质键合层3与第二集成电路100b的介质键合层3中，任一者的材料包括氮化硅或氮碳化硅。如图17和图18所示，第一集成电路100a的键合图案4与第二集成电路100b的键合图案4，在参考平面上的正投影重合或部分交叠。
示例性的，第一集成电路100a的键合图案4与第二集成电路100b的键合图案4，在参考平面上的正投影重合。此时，在平行于参考平面的方向上，第一集成电路100a的键合图案4的尺寸，和第二集成电路100b的键合图案4的尺寸相同。第一集成电路100a的键合图案4与第二集成电路100b的介质键合层3之间无接触，第二集成电路100b的键合图案4与第一集成电路100a的介质键合层3之间无接触。
示例性的，第一集成电路100a的键合图案4与第二集成电路100b的键合图案4，在参考平面上的正投影部分交叠。此时，在平行于参考平面的方向上，第一集成电路100a的键合图案4的尺寸，和第二集成电路100b的键合图案4的尺寸可以相同，也可以不同。第一集成电路100a和第二集成电路100b中，一者的键合图案4，与另一者的介质键合层3相接触。由于氮化硅或氮碳化硅能够在高温环境下，阻挡导电部41的材料向介质键合层3的扩散，因此，可以有效避免出现因阻挡导电部41的材料向介质键合层3的扩散，而引起的电性问题、可靠性降低问题。
在上述实施例中，可以有效降低第一集成电路100a和第二集成电路100b的对位精度，降低第一集成电路100a和第二集成电路100b键合的难度。
在另一些实施例中，第一集成电路100a的介质键合层3的材料包括氮化硅或氮碳化硅，第二集成电路100b的介质键合层3的材料包括氧化硅。如图19所示，第一集成电路100a的键合图案4在参考平面上的正投影，位于第二集成电路100b的键合图案4在参考平面上的正投影范围内。
示例性的，第一集成电路100a的键合图案4在参考平面上的正投影的一部分边界，与第二集成电路100b的键合图案4在参考平面上的正投影的一部分边界重合；第一集成电路100a的键合图案4在参考平面上的正投影的另一部分边界，与第二集成电路100b的键合图案4在参考平面上的正投影的另一部分边界之间具有间距。或者，第一集成电路100a的键合图案4在参考平面上的正投影边界，和第二集成电路100b的键合图案4在参考平面上的正投影边界之间，均具有间距。
在平行于参考平面的方向上，第一集成电路100a的键合图案4的尺寸，小于第二集成电路100b的键合图案4的尺寸。第一集成电路100a的键合图案4与第二集成电路100b的介质键合层3之间无接触，第二集成电路100b的键合图案4与第一集成电路100a的介质键合层3之间相接触。
由于氮化硅或氮碳化硅能够在高温环境下阻挡导电部41的材料向介质键合层3的扩散，而氧化硅难以在高温环境下阻挡导电部41的材料向介质键合层3的扩散，因此，采用上述设置方式，可以利用第一集成电路100a的介质键合层3，有效阻挡第二集成电路100b的键合图案4中导电部41的材料的扩散，有效避免出现因阻挡导电部41的材料向介质键合层3的扩散，而引起的电性问题、可靠性降低问题。
本申请的一些实施例还提供了一种三维集成电路的制备方法。该制备方法例如用于制备形成 如上述一些实施例中任一项所述的三维集成电路。图20为一些实施例中的制备一种集成电路的流程图；图21a～图21b为一些实施例的制备一种三维集成电路的各步骤图。
如图20所示，上述制备方法包括：S310～S330。
S310，如图21a所示，提供第一集成电路100a和第二集成电路100b，该第一集成电路100a和第二集成电路100b为上述任一实施例所述的集成电路100。
S320，将第一集成电路100a和第二集成电路100b对位并键合。
示例性地，在制备第一集成电路100a和第二集成电路100b的过程中，可以在两者的表面制备对位标记。在混合键合的过程中，分别抓取两者的对位标记以采集两者的位置信息，直至两者对准。然后，将第一集成电路100a与第二集成电路100b键合。
S330，如图21b所示，对键合后的第一集成电路100a和第二集成电路100b进行热处理，该热处理的温度的范围为120℃～400℃。
可选地，上述热处理的温度为120℃、150℃、300℃、350℃或400℃等。导电部41的材料在热的作用下膨胀，使得第一集成电路100a和第二集成电路100b中的键合图案4相接触。
示例性的，对键合后的第一集成电路100a和第二集成电路100b进行热处理的方式包括多种，可以根据实际需要选择设置。
可选地，本申请实施例可以采用原位加热加压的方式对键合后的第一集成电路100a和第二集成电路100b进行热处理，使得第一集成电路100a中键合图案4的导电部41的材料向金属钝化层42中扩散，并在该键合图案4远离衬底1的一侧形成合金层，同时，还使得第二集成电路100b中键合图案4的导电部41的材料向金属钝化层42中扩散，并在该键合图案4远离衬底1的一侧形成合金层，第一集成电路100a中的合金层和第二集成电路100b中的合金层产生互熔，从而使得第一集成电路100a和第二集成电路100b互联在一起。
可选地，本申请实施例可以在真空大气氛围中对键合后的第一集成电路100a和第二集成电路100b进行退火处理，使得第一集成电路100a中键合图案4的导电部41的材料向金属钝化层42中扩散，并在该键合图案4远离衬底1的一侧形成合金层，同时，还使得第二集成电路100b中键合图案4的导电部41的材料向金属钝化层42中扩散，并在该键合图案4远离衬底1的一侧形成合金层，第一集成电路100a中的合金层和第二集成电路100b中的合金层产生互熔，从而使得第一集成电路100a和第二集成电路100b互联在一起。
此处，在相关技术中，混合键合的热处理的温度很高，且热处理的温度基本均在400℃以上。而本申请实施例通过在键合图案4中导电部41上设置金属钝化层42，可以将混合键合的热处理的温度降低至400℃及以下。也就是说，本申请实施例有效降低了混合键合的热处理的温度。
在此基础上，可以利用金属钝化层42对导电部41的表面进行抗氧化保护，降低热处理对导电部41的影响，降低热处理对晶圆中应力、热平衡和结构可靠性的影响，从而能够改善键合图案4中导电部41的氧化、晶圆翘曲、晶圆的热平衡和结构可靠性被破坏等问题，进一步保障互连形成的三维集成电路的电学性能和可靠性。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (30)

  1. 一种集成电路，其特征在于，所述集成电路包括：
    衬底；
    位于所述衬底上的功能层；
    位于所述功能层上的介质键合层；
    位于所述介质键合层内的多个键合图案，所述键合图案与所述功能层电连接；所述键合图案包括与所述功能层电连接的导电部，及位于所述导电部上的金属钝化层；
    其中，所述导电部的材料和所述金属钝化层的材料形成的合金的熔点，低于所述导电部的材料的熔点。
  2. 根据权利要求1所述的集成电路，其特征在于，所述导电部的材料在所述金属钝化层中的晶界扩散系数，大于所述金属钝化层的材料在所述导电部中的晶界扩散系数。
  3. 根据权利要求1所述的集成电路，其特征在于，相比于所述衬底，所述金属钝化层远离所述衬底的一侧表面的至少一部分，低于所述介质键合层远离所述衬底的一侧表面。
  4. 根据权利要求3所述的集成电路，其特征在于，所述金属钝化层远离所述衬底的一侧表面呈弧面状，且向靠近所述衬底的方向凹陷。
  5. 根据权利要求1所述的集成电路，其特征在于，相比于所述衬底，所述导电部远离所述衬底的一侧表面，低于所述介质键合层远离所述衬底的一侧表面。
  6. 根据权利要求5所述的集成电路，其特征在于，所述导电部远离所述衬底的一侧表面呈弧面状，且向靠近所述衬底的方向凹陷。
  7. 根据权利要求1～6中任一项所述的集成电路，其特征在于，所述导电部的材料包括铜，所述金属钝化层的材料包括镍、钛、锡、银、金或钯。
  8. 根据权利要求1～6中任一项所述的集成电路，其特征在于，所述介质键合层的材料包括氮化硅、氮碳化硅、氧化硅。
  9. 根据权利要求1～6中任一项所述的集成电路，其特征在于，所述键合图案还包括：
    环绕所述导电部，且位于所述导电部和所述介质键合层之间的籽晶层；
    环绕所述籽晶层，且位于所述籽晶层和所述介质键合层之间的阻挡层。
  10. 一种集成电路的制备方法，其特征在于，所述制备方法包括：
    在衬底上依次形成功能层和介质键合层，所述介质键合层具有多个混合键合通孔，所述混合键合通孔暴露所述功能层的部分表面；
    在所述混合键合通孔内形成导电部，所述导电部与所述功能层电连接，得到初始集成电路；
    将所述初始集成电路置于处理气体中，所述处理气体包括金属羰基有机化合物前驱体蒸汽，以在所述导电部上选择性沉积金属钝化层；其中，所述导电部的材料和所述金属钝化层的材料构成的合金的熔点，低于所述导电部的材料的熔点。
  11. 根据权利要求10所述的制备方法，其特征在于，所述金属钝化层的厚度的范围为10nm～30nm。
  12. 根据权利要求10所述的制备方法，其特征在于，所述导电部的材料包括铜，所述金属羰基有机化合物前驱体包括Ni(CO)4。
  13. 根据权利要求10所述的制备方法，其特征在于，所述在所述混合键合通孔内形成导电部，包括：
    在所述混合键合通孔内和所述介质键合层上形成导电薄膜；
    对所述导电薄膜进行第一研磨处理，去除所述导电薄膜中位于所述介质键合层上的部分，保留所述导电薄膜中位于所述混合键合通孔内的部分，得到所述导电部；相比于所述衬底，所述导电部远离所述衬底的一侧表面，低于所述介质键合层远离所述衬底的一侧表面。
  14. 根据权利要求13所述的制备方法，其特征在于，所述制备方法还包括：
    对所述介质键合层远离所述衬底的一侧表面进行平坦化处理。
  15. 根据权利要求13所述的制备方法，其特征在于，在垂直于所述衬底的方向上，所述导电部远离所述衬底的一侧表面，与所述介质键合层远离所述衬底的一侧表面之间的最大间距的范围 为10nm～30nm。
  16. 根据权利要求13所述的制备方法，其特征在于，所述制备方法还包括：
    对所述金属钝化层和所述介质键合层远离所述衬底的一侧表面进行第二研磨处理；相比于所述衬底，所述金属钝化层远离所述衬底的一侧表面的至少一部分，低于所述介质键合层远离所述衬底的一侧表面。
  17. 根据权利要求13所述的制备方法，其特征在于，所述在所述混合键合通孔内和所述介质键合层上形成导电薄膜之前，所述制备方法还包括：
    在所述混合键合通孔内和所述介质键合层上，依次形成阻挡薄膜和籽晶薄膜；
    其中，在对所述导电薄膜进行第一研磨处理的过程中，还对所述籽晶薄膜和所述阻挡薄膜进行第一研磨处理，去除所述籽晶薄膜和所述阻挡薄膜位于所述介质键合层上的部分，保留所述籽晶薄膜和所述阻挡薄膜位于所述混合键合通孔内的部分，得到籽晶层和阻挡层；所述籽晶层环绕所述导电部，所述阻挡层环绕所述籽晶层。
  18. 一种集成电路的制备方法，其特征在于，所述制备方法包括：
    在衬底上依次形成功能层和介质键合层，所述介质键合层具有多个混合键合通孔，所述混合键合通孔暴露所述功能层的部分表面；
    在所述混合键合通孔内形成导电部，所述导电部与所述功能层电连接；相比于所述衬底，所述导电部远离所述衬底的一侧表面，低于所述介质键合层远离所述衬底的一侧表面；
    在所述导电部上和所述介质键合层上形成金属钝化薄膜；所述金属钝化薄膜中位于所述导电部上的部分的厚度，大于所述金属钝化薄膜中位于所述介质键合层上的部分的厚度；
    对所述金属钝化薄膜进行第三研磨处理，去除所述金属钝化薄膜位于所述介质键合层上的部分，保留所述金属钝化薄膜位于所述导电部上的部分，得到金属钝化层；其中，所述导电部的材料和所述金属钝化层的材料构成的合金的熔点，低于所述导电部的材料的熔点。
  19. 根据权利要求18所述的制备方法，其特征在于，所述导电部的材料包括铜，所述金属钝化层材料包括钛、锡、银、金或钯。
  20. 根据权利要求18所述的制备方法，其特征在于，所述金属钝化薄膜中位于所述导电部上的一部分的厚度的范围为10nm～60nm。
  21. 根据权利要求18所述的制备方法，其特征在于，所述在所述混合键合通孔内形成导电部，包括：
    在所述混合键合通孔内和所述介质键合层上形成导电薄膜；
    对所述导电薄膜进行第一研磨处理，去除所述导电薄膜位于所述介质键合层上的部分，保留所述导电薄膜位于所述混合键合通孔内的部分，得到所述导电部。
  22. 根据权利要求21所述的制备方法，其特征在于，所述制备方法还包括：
    对所述介质键合层远离所述衬底的一侧表面进行平坦化处理。
  23. 根据权利要求21所述的制备方法，其特征在于，在垂直于所述衬底的方向上，所述导电部远离所述衬底的一侧表面，与所述介质键合层远离所述衬底的一侧表面之间的最大间距的范围为20nm～70nm。
  24. 根据权利要求21所述的制备方法，其特征在于，所述在所述导电部上和所述介质键合层上形成金属钝化薄膜，包括：
    采用离子化物理气相沉积工艺，在所述导电部上和所述介质键合层上沉积金属钝化材料，形成所述金属钝化薄膜。
  25. 根据权利要求21所述的制备方法，其特征在于，所述在所述混合键合通孔内和所述介质键合层上形成第一导电薄膜之前，所述制备方法还包括：
    在所述混合键合通孔内和所述介质键合层上，依次形成阻挡薄膜和籽晶薄膜；
    其中，在对所述导电薄膜进行第一研磨处理的过程中，还对所述籽晶薄膜和所述阻挡薄膜进行第一研磨处理，去除所述籽晶薄膜和所述阻挡薄膜位于所述介质键合层上的部分，保留所述籽晶薄膜和所述阻挡薄膜位于所述混合键合通孔内的部分，得到籽晶层和阻挡层；所述籽晶层环绕所述导电部和所述金属钝化层，所述阻挡层环绕所述籽晶层。
  26. 一种三维集成电路，其特征在于，所述三维集成电路包括：相对设置的第一集成电路和第二集成电路，所述第一集成电路和所述第二集成电路为如权利要求1～9中任一项所述的集成电路；
    其中，所述第一集成电路中的键合图案与所述第二集成电路中的键合图案相键合，所述第一集成电路的介质键合层与所述第二集成电路的介质键合层相键合。
  27. 根据权利要求26所述的三维集成电路，其特征在于，所述第一集成电路的介质键合层与所述第二集成电路的介质键合层中，任一者的材料包括氮化硅或氮碳化硅；
    所述第一集成电路的键合图案与所述第二集成电路的键合图案，在参考平面上的正投影重合或部分交叠；
    所述参考平面为所述第一集成电路的衬底远离所述第二集成电路的一侧表面。
  28. 根据权利要求26所述的三维集成电路，其特征在于，所述第一集成电路的介质键合层的材料包括氮化硅或氮碳化硅，所述第二集成电路的介质键合层的材料包括氧化硅；
    所述第一集成电路的键合图案在参考平面上的正投影，位于所述第二集成电路的键合图案在所述参考平面上的正投影范围内；
    所述参考平面为所述第一集成电路的衬底远离所述第二集成电路的一侧表面。
  29. 一种三维集成电路的制备方法，其特征在于，所述制备方法包括：
    提供第一集成电路和第二集成电路，所述第一集成电路和所述第二集成电路为如权利要求1～9中任一项所述的集成电路；
    将所述第一集成电路和所述第二集成电路对位并键合；
    对键合后的所述第一集成电路和所述第二集成电路进行热处理，所述热处理的温度的范围为120℃～400℃。
  30. 一种电子设备，其特征在于，所述电子设备包括如权利要求26～28中任一项所述的三维集成电路。
PCT/CN2023/102965 2022-11-03 2023-06-27 集成电路及其制备方法、三维集成电路、电子设备 WO2024093281A1 (zh)

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