WO2024093045A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2024093045A1
WO2024093045A1 PCT/CN2023/076133 CN2023076133W WO2024093045A1 WO 2024093045 A1 WO2024093045 A1 WO 2024093045A1 CN 2023076133 W CN2023076133 W CN 2023076133W WO 2024093045 A1 WO2024093045 A1 WO 2024093045A1
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WIPO (PCT)
Prior art keywords
data
selection circuit
array
storage array
storage
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PCT/CN2023/076133
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English (en)
French (fr)
Inventor
鲁耀华
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication of WO2024093045A1 publication Critical patent/WO2024093045A1/zh
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Definitions

  • the present disclosure relates to memory technology, and more particularly to a memory.
  • DRAM dynamic random access memory
  • the memory unit may fail, and the failed memory unit cannot work normally and needs to be replaced and repaired. Therefore, considering the possible replacement and repair, how to ensure that the memory can achieve accurate data processing becomes a problem that needs to be considered.
  • An embodiment of the present disclosure provides a memory.
  • the first aspect of the present disclosure provides a memory, comprising: N storage arrays arranged in sequence, the N storage arrays are respectively recorded as the first storage array, the second storage array, ..., the i-th storage array, ..., the N-th storage array, wherein at least one of the storage arrays is a redundant array, and at least one of the storage arrays is a main storage array, the redundant array is used to replace a faulty storage unit in the main storage array, 1 ⁇ i ⁇ N, 2 ⁇ N and i and N are positive integers; N selection circuits, respectively recorded as the first selection circuit, the second selection circuit, ..., the i-th selection circuit, ..., the N-th selection circuit, the N selection circuits Receive N-1 groups of data, which are recorded as the first data, the second data, ..., the i-th data, ..., the N-1-th data; wherein the first selection circuit receives the first data, and is used to output or not output the first data to the first storage array according to the first
  • the storage array and the redundant array each include M columns, respectively recorded as the 1st column, the 2nd column, ..., the jth column, ..., the Mth column, the jth column of the redundant array is used to replace the jth column of any one of the main storage arrays, 1 ⁇ j ⁇ M, and j and M are positive integers.
  • the selection circuit includes: a plurality of sub-selection circuits, each of the sub-selection circuits of the first selection circuit 1 bit of the 1st data is received, each of the sub-selection circuits of the i-th selection circuit receives the i-1th data and 1 bit of the i-th data respectively, and each of the sub-selection circuits of the N-th selection circuit receives 1 bit of the N-1th data.
  • the sub-selection circuit includes a data selector, the first data input terminal of the data selector of the first selection circuit receives 1 bit of data in the first data, the selection terminal of the data selector of the first selection circuit receives the first selection signal, the first data input terminal of the data selector of the i-1th selection circuit receives 1 bit of data in the i-1th data, the second data input terminal of the data selector of the i-th selection circuit receives 1 bit of data in the i-th data, the selection terminal of the data selector of the i-th selection circuit receives the i-th selection signal, the first data input terminal of the data selector of the N-1th selection circuit receives 1 bit of data in the N-1th data, and the selection terminal of the data selector of the N-th selection circuit receives the N-selection signal.
  • the number of the redundant array is one.
  • the first storage array is the redundant array.
  • the first selection circuit when there is no faulty storage unit, the first selection circuit does not output data, the Nth selection circuit outputs the N-1th data, and the i-th selection circuit outputs the i-1th data; when the faulty storage unit in the nth storage array is replaced by the redundant array, the first selection circuit outputs the first data, the Nth selection circuit outputs the N-1th data, in the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the i-th data, in the range of n ⁇ i ⁇ N, the i-th selection circuit outputs the i-1th data, and n is a positive integer; when the faulty storage unit in the Nth storage array is replaced by the redundant array, the first selection circuit outputs the first data, the i-th selection circuit outputs the i-th data, and the N-th selection circuit does not output data.
  • the Nth storage array is the redundant array.
  • the first selection circuit when there is no faulty storage unit, the first selection circuit outputs the first data, the Nth selection circuit does not output data, and the i-th selection circuit outputs the i-th data; when the faulty storage unit in the n-th storage array is replaced by the redundant array, the first selection circuit outputs the first data, the N-th selection circuit outputs the N-1-th data, in the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the i-th data, in the range of n ⁇ i ⁇ N, the i-th selection circuit outputs the i-1-th data, and n is a positive integer; when the faulty storage unit in the first storage array is replaced by the redundant array, the first selection circuit does not output data, the i-th selection circuit outputs the i-1-th data, and the N-th selection circuit outputs the N-1-th data.
  • the mth storage array is the redundant array, 1 ⁇ m ⁇ N and m is a positive integer.
  • the first selection circuit when there is no faulty storage unit, the first selection circuit outputs the first data, the Nth selection circuit outputs the N-1th data, the mth selection circuit does not output data, and in the range of 1 ⁇ i ⁇ m, the i-th selection circuit outputs the i-th data, and in the range of m ⁇ i ⁇ N, the i-th selection circuit outputs the i-1th data; when the faulty storage unit in the nth storage array is replaced by the redundant array, the first selection circuit outputs the first data, the Nth selection circuit outputs the N-1th data, the nth selection circuit does not output data, in the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the i-th data, and in the range of n ⁇ i ⁇ N, the i-th selection circuit outputs the i-1th data, n ⁇ m and n is a positive integer; when the faulty storage unit in the kth storage array is replaced by the redundant array, the first selection circuit outputs the first data, the
  • the number of the redundant arrays is plural and the redundant arrays are not adjacent.
  • At least one of the main storage arrays is a check code storage array, and the check code storage array is used to store check code data.
  • the memory further includes: a verification module; the verification module is connected to the N selection circuits, the data received by the N selection circuits include data to be written and verification code data, and the verification module is used to generate the verification code data based on the data to be written.
  • the memory provided by the embodiment of the present disclosure includes N memory arrays arranged in sequence, including at least one main memory array and at least one redundant array, the redundant array is used to provide faulty unit replacement of the main memory array, and N selection circuits, each selection circuit receives data corresponding to the bit sequence and the previous adjacent data, each selection circuit responds to its own selection signal, and outputs a corresponding signal by selection to achieve data processing in a fault replacement scenario.
  • the memory of this solution sets multiple selection circuits, and controls the selection circuit to output corresponding data according to the faulty unit replacement situation of the memory, thereby achieving data processing under fault replacement and ensuring the accuracy and reliability of data processing.
  • FIG1 is a diagram showing an example of a memory architecture according to an embodiment
  • FIG2 is a structural diagram of a storage unit according to an embodiment
  • FIG3 and FIG4 are respectively diagrams of an exemplary replacement solution architecture
  • FIG5 is a diagram showing an example structure of a memory provided by an embodiment
  • FIG6 and FIG7 are state example diagrams under different situations respectively.
  • FIG8 is a diagram showing an example of a storage array architecture
  • FIG9 is a structural diagram of an exemplary memory
  • Figures 10 to 12 are example diagrams of states under different situations
  • FIG13 is a structural diagram of an exemplary memory
  • Figures 14 to 16 are example diagrams of states under different situations
  • FIG17 is a diagram showing an exemplary structure of a memory device
  • 18 to 21 are diagrams showing examples of states under different circumstances.
  • FIG1 is an example diagram of the architecture of a memory device according to an embodiment.
  • DRAM taking DRAM as an example, it includes a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a storage array.
  • the data input/output buffer belongs to the peripheral area circuit
  • the sense amplifier, the row decoder, the column decoder, and the storage array belong to the array area circuit.
  • the storage array is mainly composed of word lines, bit lines, and storage cells.
  • the word lines in the storage array extend in the row direction
  • the bit lines in the storage array extend in the column direction.
  • the intersection of the word lines and the bit lines is the storage cell of the storage array.
  • FIG2 is a structural example diagram of a storage unit shown in an embodiment, and the storage unit is mainly composed of a transistor switch M and a capacitor C.
  • the capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.
  • a certain storage cell can be activated by controlling the word line and the bit line to access the storage cell.
  • the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder. Correspondingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa.
  • the write scenario as an example: when bit data needs to be written to a certain storage cell, such as writing 1.
  • the word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on.
  • the logic level of the bit line By setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.
  • faulty storage cells may be generated in the storage array.
  • These faulty storage cells cannot work properly, so in order to prevent the faulty storage cells from affecting the normal operation of the memory, in addition to planning the main storage array containing regular storage cells, a redundant array is also planned during the design.
  • the storage cells in the redundant array are used as redundant parts to replace the faulty storage cells in the main storage array.
  • replacement in this article refers to the replacement of storage function, that is, ensuring the number of storage units that can be used to store data normally after replacement.
  • Specific replacement methods include but are not limited to using redundant storage units to store the bit data that the failed storage unit originally needed to store, or ensuring that after adding redundant storage units, the number of storage units that can work normally can ensure the storage of complete data, and there is no restriction on which storage unit stores which bit of data.
  • a storage column containing regular storage cells and a redundant column containing redundant storage cells are designed in the storage array.
  • the redundant column and the storage column share the data line of the storage array, and the data line is used to transmit read or write data.
  • CCR Central Column Repair
  • all redundant storage cells are set in an independent redundant array, and the redundant array and the regular storage array are set independently, each with an independent data line. Therefore, it is necessary to provide an effective solution to support data processing when a fault replacement occurs under this architecture, such as the normal writing of data.
  • FIG3 and FIG4 are respectively an example of a replacement scheme architecture diagram, taking a memory including N storage arrays as an example, namely the first storage array, the second storage array, ... the Nth storage array.
  • the fault replacement scheme adopted in FIG3 is the LCR scheme, the columns filled with shades in the figure are redundant columns, and the unfilled shaded parts are conventional storage columns. It can be seen that in the LCR scheme, each redundant column is integrated in each storage array, and the storage columns and redundant columns under each storage array share data lines.
  • the fault replacement scheme adopted in FIG4 is the CCR scheme, the array filled with shades in the figure is a redundant array, and the unfilled shaded parts are conventional main storage arrays.
  • a redundant array is independently set, and the storage cells in the redundant array are used to replace the faulty storage cells in the main storage array, and each array is configured with an independent data line. It should be noted that the figure is only an example, and the specific array architecture can be adjusted according to actual needs, and is not limited to the example in the figure.
  • FIG5 is a structural example diagram of a memory provided by an embodiment. As shown in FIG5, the memory includes:
  • N storage arrays 11 are arranged in sequence, the N storage arrays are respectively recorded as the first storage array, the second storage array, ..., the i-th storage array, ..., the N-th storage array, wherein at least one storage array is a redundant array, and at least one storage array is a primary storage array, the redundant array is used to replace a faulty storage unit in the primary storage array, 1 ⁇ i ⁇ N, 2 ⁇ N, and i and N are positive integers;
  • N selection circuits 12 are respectively recorded as the first selection circuit, the second selection circuit, ..., the i-th selection circuit, ..., the N-th selection circuit.
  • the N selection circuits receive N-1 groups of data, which are respectively recorded as the first data, the second data, ..., the i-th data, ..., the N-1-th data;
  • the first selection circuit receives the first data and is used to output or not output the first data to the first storage array according to the first selection signal;
  • the Nth selection circuit receives the N-1th data and is used to output or not output the N-1th data to the Nth storage array according to the Nth selection signal;
  • the i-th selection circuit receives the N-1th data and is used to output or not output the N-1th data to the Nth storage array according to the Nth selection signal;
  • the selection circuit receives the i-1th data and the i-th data, and the i-th selection circuit is used to output the i-1th data or the i-th data to the i-th storage array according to the i-th selection signal, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • the number of data groups received by the selection circuit can be determined according to the amount of data actually required to be written into the memory.
  • the type of memory provided in this embodiment is not limited, and as an example, it can be applied to, including but not limited to, double data rate synchronous dynamic random access memory (DDR for short).
  • DDR double data rate synchronous dynamic random access memory
  • the main storage array in the storage array is used to store the written data when there is no faulty storage unit.
  • the read data can be verified. Therefore, in one example, at least one main storage array is a check code storage array, and the check code storage array is used to store the check code data. Therefore, the data finally written into the N storage arrays will include the data to be written Data_CP, and the check code data Data_ECC.
  • the check code storage array is used to store the check code data, which can be interpreted as the check code storage array normally storing the check code data when there is no faulty storage unit.
  • the faulty storage unit in the check code storage array can also be replaced by a redundant array.
  • the check code data corresponding to the faulty storage unit will be written into a certain storage unit after the replacement.
  • the data verification method may include but is not limited to parity check, cyclic redundancy check, etc.
  • the verification scheme verification is required based on the verification code data. Therefore, when writing data to the storage array, the verification code data will be generated and written at the same time, so that when the data is read, the read storage data is verified according to the read verification code data.
  • the memory also includes: a verification module 13; the verification module 13 is connected to N selection circuits 12, and the data received by the N selection circuits 12 includes the data to be written and the verification code data.
  • the verification module 13 is used to generate the verification code data according to the data to be written. This example can generate corresponding verification code data when the data is written and store it in the storage array by setting the verification code module, so that the read data can be verified when the data is read, thereby further improving the accuracy and reliability of data processing.
  • the circuit working principle of this embodiment is illustrated below: Take the complete data written at one time as 34 groups of data as an example, recorded as the first data Data_1 to the 34th data Data_34, and the 18th storage array is a redundant array.
  • the length and content of the data written at one time can be determined according to the type and working parameters of the memory.
  • the first data Data_1 represents the data that should be written to the first main storage array under normal circumstances among the complete 34 groups of data
  • the second data Data_2 represents the data that should be written to the second main storage array under normal circumstances among the complete 34 groups of data; and so on.
  • the redundant array may not store data, that is, empty data; or, when the column where the faulty storage unit in the main storage array is located is replaced by the redundant array, the data in the redundant array is specifically the data stored after the faulty storage unit is replaced, and the data may be one of the 34 groups of data. Which group of data is specifically determined according to the actual situation, and an example will be given later.
  • FIG6 is a state example diagram under a situation where there is no faulty storage unit in the main storage array.
  • the 34 sets of data written should be stored in the corresponding main storage array.
  • the 19th to 35th storage arrays are all main storage arrays.
  • the first data Data_1 in the written data needs to be stored in the first storage array (the first main storage array), the second data Data_2 needs to be stored in the second storage array (the second main storage array), and so on, until the 17th data Data_17 needs to be stored in the 17th storage array (the 17th main storage array), and then the 18th storage array is a redundant array, so no data is stored, and then the 18th data Data_18 needs to be stored in the 19th storage array (the 18th main storage array), the 19th data Data_19 needs to be stored in the 20th storage array (the 19th main storage array), and so on, until the 34th data Data_34 needs to be stored in the 35th storage array (the 34th main storage array).
  • the 1st selection circuit receives the 1st data
  • the Nth selection circuit receives the N-1th data
  • the i-th selection circuit receives the i-1th data and the i-th data.
  • the 1st selection circuit receives the 1st data Data_1, the 2nd selection circuit receives the 1st data Data_1 and the 2nd data Data_2, ... the 17th selection circuit receives the 16th data Data_16 and the 17th data Data_17
  • the 18th selection circuit receives the 17th data Data_17 and the 18th data Data_18
  • the 19th selection circuit receives the 18th data Data_18 and the 19th data Data_19
  • the 34th selection circuit receives the 33rd data Data_33 and the 35th data Data_34
  • the 35th selection circuit receives the 34th data Data_34.
  • the first selection circuit outputs the first data to write the first data Data_1 into the first storage array.
  • the i-th selection circuit selects to output the i-th data to write the i-th data into the i-th storage array.
  • the i-th selection circuit selects to output the i-1-th data Data_i-1 to write the i-1-th data Data_i-1 into the i-th storage array.
  • the 35th selection circuit outputs the 34th data Data_34 to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate writing of data.
  • FIG. 7 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array. Still in combination with the architecture shown in FIG. 6, taking the situation where there is a faulty storage unit in the first storage array as an example, in FIG. 7, the redundant array (the 18th storage array) is used to replace the faulty storage unit in the first storage array.
  • the first data Data_1 that originally needs to be written to the first storage array needs to be written to the second storage array
  • the second data Data_2 that originally needs to be written to the second storage array needs to be written to the third storage array, until the 17th data Data_17 that originally needs to be written to the 17th storage array needs to be written to the redundant array (in the 18th storage array), thereby replacing the faulty storage unit in the first storage array.
  • the column where the faulty storage unit in the first storage array is located may not store data, so the first selection circuit does not output the first data Data_18, and the 19th to 35th selection circuits output the 18th data Data_18 to the 34th data Data_34 respectively, and then write the 18th data Data_18 to the 34th data Data_34 to the 19th to 35th storage arrays respectively, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • N selection circuits are set for N storage arrays, and the corresponding data can be output by controlling the selection circuits regardless of whether a failed storage unit is replaced, so as to achieve accurate writing of complete data and ensure the accuracy and reliability of data processing.
  • the solution of this embodiment is convenient for circuit design and preparation, and can be applied to high-integration scenarios such as memory.
  • FIG8 is an example diagram of the architecture of a storage array.
  • the main storage array and the redundant array both include multiple columns, for example, M columns, which are respectively recorded as the first column, the second column, ..., The jth column, ..., the Mth column.
  • the jth column of the redundant array is used to replace the jth column of the main storage array, where 1 ⁇ j ⁇ M, and j and M are positive integers.
  • the single "column” here refers to the control object of a single column selection signal.
  • the storage array includes multiple physical rows (for example, understood as word lines) and multiple physical columns (for example, understood as bit lines) in physical structure.
  • multiple physical columns in a storage array are divided into multiple groups of columns, and all physical columns in each group of columns are controlled by the same column selection signal, and columns in different groups are controlled by different column selection signals.
  • a storage array includes 16 physical columns, it will be divided into 4 columns (column_1 to column_4) according to every 4 physical columns, and column_1 to column_4 correspond to column selection signals 1 to column selection signals 4 respectively.
  • the 4 physical columns in each column correspond to the same column selection signal, and each column can be regarded as a "column” described in this example.
  • the same column selection signal is used to select the same column in different storage arrays.
  • the same column here refers to the column with the same position in different storage arrays, for example, column selection signal 1 is used to select column_1 in all storage arrays.
  • a single "column” in this example is a single physical column.
  • a storage array includes 8 physical columns, which are respectively controlled by 8 column selection signals. Then, each physical column at this time can be regarded as a "column” described in this example. This embodiment does not limit this.
  • the selection circuit 12 includes: multiple sub-selection circuits 121, each sub-selection circuit of the 1st selection circuit receives 1 bit of data in the 1st data, each sub-selection circuit of the i-th selection circuit receives 1 bit of data in the i-1th data and the i-th data respectively, and each sub-selection circuit of the N-th selection circuit receives 1 bit of data in the N-1th data.
  • each storage array 11 includes multiple columns 21, and an enlarged view of one of the storage arrays is used as an example in the figure, and each column 21 is further composed of multiple physical columns (such as 4 bits).
  • the column decoder will parse the column selection signal from the write instruction, for example, the column selection signal represents the address of the first column. In response to the column selection signal, the first column of the multiple storage arrays 11 is selected.
  • the i-th data includes 4-bit data that needs to be written to the first column of a certain storage array, that is, the first data includes 4-bit data that needs to be written to the first column of a certain storage array, and the second data includes 4-bit data that needs to be written to the first column of another storage array, and so on. Therefore, each selection circuit includes 4 sub-selection circuits, each corresponding to 1-bit data in the 4-bit data, and the output end of each selection circuit is connected to the data line of the corresponding storage array, and the data output by the selection circuit is written to the corresponding storage array through the data line.
  • each sub-selection circuit in the i-th selection circuit receives 1 bit of data in the i-1th data (including 4 bits of data) and 1 bit of data in the i-th data (including 4 bits of data), and each sub-selection circuit in the N-th selection circuit receives 1 bit of data in the N-1th data.
  • the column selection signal has the same position in the columns selected by different storage arrays, and the physical columns to be written by the two bits of data received by the sub-selection circuits are distributed in the same columns of the two different storage arrays, and have the same position in their respective columns.
  • the two bits of data received by the first sub-selection circuit of the second selection circuit come from the first bit of the 4 bits of the first data and the first bit of the 4 bits of the second data, respectively.
  • the selection circuit may include one or more sub-selection circuits, and the selection signals of the sub-selection circuits in the same selection circuit are the same. Therefore, in one example, the sub-selection circuits in the same selection circuit may share a selection signal, and different selection circuits may have the same selection signal.
  • the channels receive their own independent selection signals.
  • the sub-selection circuit is used to select a data output from the received data in response to the selection signal.
  • the implementation of the sub-selection circuit is not limited.
  • the sub-selection circuit includes a data selector MUX, the first data input end of the data selector of the first selection circuit receives 1 bit of data in the first data, the selection end of the data selector of the first selection circuit receives the first selection signal, the first data input end of the data selector of the i-th selection circuit receives 1 bit of data in the i-th data, the second data input end of the data selector of the i-th selection circuit receives 1 bit of data in the i-th data, the selection end of the data selector of the i-th selection circuit receives the i-th selection signal, the first data input end of the data selector of the N-th selection circuit receives 1 bit of data in the N-1th data, and the selection end of the data selector of the N-th selection circuit receives
  • how the data selector outputs data according to the level of the selection signal can be set according to actual needs. For example, when the first selection signal is at a high level, the output end of the data selector of the first selection circuit outputs 1 bit of the first data. When the first selection signal is at a low level, the output end of the data selector of the first selection circuit does not output data. When the i-th selection signal is at a high level, the output end of the data selector of the i-th selection circuit outputs 1 bit of the i-th data. When the i-th selection signal is at a low level, the output end of the data selector of the i-th selection circuit outputs 1 bit of the i-1-th data.
  • the output end of the data selector of the N-th selection circuit When the N-th selection signal is at a high level, the output end of the data selector of the N-th selection circuit outputs 1 bit of the N-1-th data. When the N-th selection signal is at a low level, the output end of the data selector of the N-th selection circuit does not output the N-1-th data. When the selection end of the data selector does not receive a signal, that is, the selection end of the data selector is in a floating state, the data selector does not output any data at this time, thereby realizing the selection and output of corresponding data according to the selection signal, and realizing the sub-selection circuit by conventional devices, which can simplify the circuit structure and reduce costs.
  • the sub-selection circuit in the 1st selection circuit includes a first switch tube, the first end of the first switch tube receives 1 bit in the 1st data, the second end of the first switch tube is the output end of the sub-selection circuit, and the first switch tube is closed or opened according to the 1st selection signal.
  • the sub-selection circuit in the i-th selection circuit includes a second switch tube and a third switch tube, the first end of the second switch tube receives 1 bit in the i-1th data, the first end of the third switch tube receives 1 bit in the i-th data, the second end of the second switch tube and the second end of the third switch tube serve as the output end of the sub-selection circuit, wherein the second switch tube or the third switch tube is closed according to the i-th selection signal, or the second switch tube and the third switch tube are both opened according to the i-th selection signal.
  • the sub-selection circuit in the N-th selection circuit includes a fourth switch tube, the first end of the fourth switch tube receives 1 bit in the N-1th data, the second end of the fourth switch tube is the output end of the sub-selection circuit, and the fourth switch tube is closed or opened according to the N-th selection signal.
  • the arrangement of each storage array can be designed as needed.
  • the number of redundant arrays can be one or more. Taking the number of redundant arrays as one as an example, there are also many arrangements of redundant arrays.
  • the redundant array can be located at the edge of the entire storage array, for example, the 1st storage array or the Nth storage array is a redundant array.
  • the redundant array can be located between storage arrays, for example, the mth storage array is a redundant array, 1 ⁇ m ⁇ N and m is a positive integer.
  • the number of redundant arrays is one.
  • each column in the redundant array can be used to replace the column in the same position in any main storage array.
  • the first column in the redundant array can be used to replace the first column in any main storage array.
  • the second column in the redundant array can be used as the second column of any main storage array.
  • both columns of a main storage array have faulty storage units, they can be replaced with two columns at the same position in the redundant array. The replacement of faulty storage units can be achieved by setting up redundant arrays.
  • FIG9 is a structural example diagram of an example memory.
  • the first storage array is a redundant array
  • the storage array filled with shades in the figure is a redundant array
  • the storage array not filled with shades is a main storage array.
  • FIG. 10 is a state example diagram under a situation where there is no faulty storage unit in the main storage array. Specifically, when there is no faulty storage unit, the first selection circuit does not output the first data Data_1, the 35th selection circuit outputs the 34th data Data_34, and the i-th selection circuit outputs the i-1th data.
  • the first storage array is a redundant array
  • the second to third storage arrays are all main storage arrays.
  • the first storage array is a redundant array, so when the main storage array does not fail, the column where the failed storage unit in the first storage array is located does not store data, and at this time, the first selection circuit does not output the first data Data_1, and the second to third selection circuits respectively output the first data Data_1 to the third data Data_34, so as to write the first data Data_1 to the third data Data_34 into the second to third storage arrays (34 main storage arrays) respectively.
  • the first selection circuit does not output the first data Data_1
  • the i-th selection circuit outputs the i-1th data
  • the third selection circuit outputs the third data Data_34, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, and realize accurate data writing.
  • FIG11 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array.
  • the first selection circuit outputs the first data
  • the Nth selection circuit outputs the N-1th data, within the range of 1 ⁇ i ⁇ n
  • the i-th selection circuit outputs the i-th data, within the range of n ⁇ i ⁇ N
  • the i-th selection circuit outputs the i-1th data
  • n is a positive integer
  • the n-th selection circuit may not output data, which can save power consumption, or may output any one of the n-1th data and the nth data, because whether the column where the faulty storage unit is located stores data does not affect the storage of the overall data, and it is only necessary not to read data from the column where the faulty storage unit is located when reading data.
  • a main storage array has a faulty storage unit, and the main storage array is not the last storage array.
  • the 16th data Data_16 originally to be written into the 17th storage array needs to be written into the 16th storage array
  • the 15th data Data_15 originally to be written into the 16th storage array needs to be written into the 15th storage array, ...
  • the first selection circuit outputs the first data Data_1 to write the first data Data_1 into the first storage array; within the range of 1 ⁇ i ⁇ 17, the i-th selection circuit outputs the i-th data, that is, the 2nd to 16th selection circuits respectively output the second data Data_2 to the 16th data Data_16, and then the second data Data_2 to the 16th data Data_16 are respectively written into the 2nd to 16th storage arrays.
  • the 17th selection circuit does not output data to avoid writing data to the column where the faulty storage unit is located; in the range of 17 ⁇ i ⁇ 35, the i-th selection circuit outputs the i-1th data, that is, the 18th to 34th selection circuits output the 17th data Data_17 to the 33rd data Data_33, so as to write the 17th data Data_17 to the 33rd data Data_33 into the 18th to 34th storage arrays respectively; at this time, the 35th selection circuit outputs the 34th data Data_34 to write the 34th data Data_34 to the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, and realize accurate writing of data.
  • the first selection circuit when the faulty storage unit in the Nth storage array is replaced by the redundant array, the first selection circuit outputs the first data, the i-th selection circuit outputs the i-th data, and the N-th selection circuit does not output data. That is, when the redundant array is the first storage array and the storage array with a fault and replaced is the last storage array, all selection circuits choose to output the i-th data to the i-th storage array.
  • a main storage array has a faulty storage unit, and the main storage array is the last storage array.
  • the 35th storage array in Figure 12 has a faulty storage unit.
  • the column where the faulty storage unit is located in the 35th storage array does not store data, and the 34th data Data_34 originally to be written into the 35th storage array needs to be written into the 34th storage array, and the 33rd data Data_33 originally to be written into the 34th storage array needs to be written into the 33rd storage array, ...
  • the first selection circuit outputs the first data Data_1 to write the first data Data_1 into the first storage array; the i-th selection circuit outputs the i-th data, that is, the 2nd to 34th selection circuits respectively output the second data Data_2 to the 34th data Data_34 to write the second data Data_2 to the 34th data Data_34 into the 2nd to 34th storage arrays respectively; at this time, the 35th selection circuit does not output the 34th data Data_34 to avoid writing data to the column where the faulty storage unit is located, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • FIG. 13 is a structural example diagram of an example memory, as shown in FIG. 13, the Nth storage array is a redundant array. That is, the redundant array is set at the last storage array.
  • the storage array filled with shades in the figure is a redundant array, and the storage array not filled with shades is a main storage array.
  • FIG. 14 is a state example diagram under a situation where there is no faulty storage unit in the main storage array. Specifically, when there is no faulty storage unit, the first selection circuit outputs the first data Data_1, the 35th selection circuit does not output the 34th data Data_34, and the i-th selection circuit outputs the i-th data.
  • the 35th storage array is a redundant array, and the 1st to 34th storage arrays are all main storage arrays.
  • the 35th storage array is a redundant array, so the 35th storage array does not write data when the main storage array is not faulty, and the 1st data Data_1 to the 34th data Data_34 need to be written into the 1st to 34th storage arrays (34 main storage arrays) respectively.
  • the 1st selection circuit outputs the 1st data Data_1 to write the 1st data Data_1 into the 1st storage array
  • the 2nd to 34th selection circuits output the 2nd data Data_2 to the 34th data Data_34 respectively to write the 2nd data Data_2 to the 34th data Data_34 into the 2nd to 34th storage arrays respectively; at this time, the 35th selection circuit does not output the 34th data Data_34.
  • the 1st selection circuit outputs the 1st data Data_1, the i-th selection circuit outputs the i-th data Data_i, and the 35th selection circuit does not output the 34th data, so that the selection circuit outputs complete data, and then the storage array It can accurately store the data output by the selection circuit and realize accurate writing of data.
  • Fig. 15 is a state example diagram under another situation, in which there is a faulty storage unit in the main storage array. Specifically, when the column where the faulty storage unit in the nth storage array is located is replaced by the redundant array, the 1st selection circuit outputs the 1st data, the Nth selection circuit outputs the N-1th data, within the range of 1 ⁇ i ⁇ n, the i-th selection circuit outputs the i-th data, within the range of n ⁇ i ⁇ N, the i-th selection circuit outputs the i-1th data, and n is a positive integer.
  • the first selection circuit outputs the first data Data_1 to write the first data Data_1 into the first storage array; in the range of 1 ⁇ i ⁇ 17, the i-th selection circuit outputs the i-th data, that is, the 2nd to 16th selection circuits respectively output the second data Data_2 to the 16th data Data_16 to write the second data Data_2 to the 16th data Data_16 into the 2nd to 16th storage arrays respectively; the 17th selection circuit does not output data to avoid writing data to the column where the faulty storage unit is located; in the range of 17 ⁇ i ⁇ 35 Within the range, the i-th selection circuit outputs the i-1th data, that is, the 18th to 34th selection circuits output the 17th data Data_17 to the 33rd data Data_33 respectively, so as to write the
  • the first selection circuit does not output the first data
  • the i-th selection circuit outputs the i-1th data
  • the N-th selection circuit outputs the N-1th data. That is, when the redundant array is the last storage array and the storage array that has a fault and is replaced is the first storage array, all selection circuits select to output the i-1th data.
  • the redundant array is the last storage array and the storage array that has a fault and is replaced is the first storage array
  • all selection circuits select to output the i-1th data.
  • there is a faulty storage unit in the first storage array for example, there is a faulty storage unit in the first storage array in FIG16. In conjunction with the example of FIG16, it is necessary to perform a replacement of the faulty storage unit.
  • the first selection circuit does not output the first data Data_1.
  • the first data Data_1 originally to be written to the first storage array needs to be written to the second storage array, and the second data Data_2 originally to be written to the second storage array needs to be written to the third storage array, ... and so on, until the 34th data Data_34 originally to be written to the 34th storage array needs to be written to the 35th storage array (redundant array), thereby achieving a replacement of the faulty unit.
  • the first selection circuit does not output the first data Data_1 to avoid writing data to the column where the faulty storage unit is located; the i-th selection circuit outputs the i-1-th data, that is, the 2nd to 34th selection circuits output the first data Data_1 to the 33rd data Data_33 respectively, to write the first data Data_1 to the 33rd data Data_33 into the 2nd to 34th storage arrays respectively; the 35th selection circuit outputs the 34th data Data_34 to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • FIG. 17 is a structure of an example memory.
  • the mth storage array is a redundant array, 1 ⁇ m ⁇ N and m is a positive integer. That is, the redundant array is set in a storage array that is not the first or the last.
  • the circuit working principle when the redundant array is the mth storage array is exemplified below: still taking the complete data read once as 34 groups of data as an example, the example can be combined with the aforementioned Figure 6.
  • the state when the main storage array has no faulty storage unit is as shown in Figure 6.
  • the 1st selection circuit When there is no faulty storage unit, the 1st selection circuit outputs the 1st data, the Nth selection circuit outputs the N-1th data, the mth selection circuit does not output data, and in the range of 1 ⁇ i ⁇ m, the i-th selection circuit outputs the i-th data, and in the range of m ⁇ i ⁇ N, the i-th selection circuit outputs the i-th data.
  • the first selection circuit outputs the first data Data_1 to write the first data Data_1 into the first storage array.
  • the i-th selection circuit selects to output the i-th data, that is, the second to the seventeenth selection circuits output the second data Data_2 to the seventeenth data Data_17 to write the second data Data_2 to the seventeenth data Data_17 into the second to the seventeenth storage arrays, respectively. Since the redundant array (the eighteenth storage array) does not need to store data when the main storage array is normal, the eighteenth selection circuit does not output data.
  • the i-th selection circuit selects to output the i-1th data, that is, the 19th to 34th selection circuits output the 18th data Data_18 to the 33rd data Data_33 respectively, so as to write the 18th data Data_18 to the 33rd data Data_33 into the 19th to 34th storage arrays respectively; at this time, the 35th selection circuit outputs the 34th data Data_34, so as to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate writing of data.
  • Figures 18 to 21 are state example diagrams under different situations.
  • the 1st selection circuit outputs the 1st data
  • the Nth selection circuit outputs the N-1th data
  • the nth selection circuit does not output data, within the range of 1 ⁇ i ⁇ n
  • the i-th selection circuit outputs the i-th data, within the range of n ⁇ i ⁇ N
  • the i-th selection circuit outputs the i-1th data
  • n ⁇ m and n is a positive integer.
  • the column where the failed storage unit of the 15th storage array is located no longer stores data
  • the 15th data Data_15 originally to be written into the 15th storage array needs to be written into the 16th storage array
  • the 16th data Data_16 originally to be written into the 16th storage array needs to be written into the 17th storage array
  • the 17th data Data_17 originally to be written into the 17th storage array needs to be written into the 18th storage array (redundant array), and the failure replacement is completed.
  • the first selection circuit outputs the first data Data_1, and writes Data_1 into the first storage array with the first data; within the range of 1 ⁇ i ⁇ 15, the i-th selection circuit outputs the i-th data, that is, the 2nd to 14th selection circuits respectively output the second data Data_2 to the 14th data Data_14, so as to write the second data Data_2 to the 14th data Data_14 into the 2nd to 14th storage arrays respectively; the 15th selection circuit does not output data to avoid writing data to the column where the faulty storage unit is located; within the range of 15 ⁇ i ⁇ 35, the i-th selection circuit outputs the i-th data, that is, the 2nd to 14th selection circuits respectively output the second data Data_2 to the 14th data Data_14, so as to write the second data Data_2 to the 14th data Data_14 into the 2nd to 14th storage arrays respectively.
  • the i selection circuit outputs the i-1th data, that is, the 16th to 34th selection circuits output the 15th data Data_15 to the 33rd data Data_33 respectively, so as to write the 15th data Data_15 to the 33rd data Data_33 into the 16th to 34th storage arrays respectively; at this time, the 35th selection circuit outputs the 34th data Data_34, so as to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate writing of data.
  • the first selection circuit when a failed storage unit in the kth storage array is replaced by a redundant array, the first selection circuit outputs the first data.
  • the Nth selection circuit outputs the N-1th data
  • the kth selection circuit does not output data, within the range of 1 ⁇ i ⁇ k
  • the ith selection circuit outputs the ith data, within the range of k ⁇ i ⁇ N
  • the ith selection circuit outputs the i-1th data, m ⁇ k ⁇ N and k is a positive integer.
  • the 21st storage array no longer stores data
  • the 20th data Data_20 originally to be written into the 21st storage array needs to be written into the 20th storage array
  • the 19th data Data_19 originally to be written into the 20th storage array needs to be written into the 19th storage array
  • the 18th data Data_18 originally to be written into the 19th storage array needs to be written into the 18th storage array (redundant array), and the failure replacement is completed.
  • the first selection circuit outputs the first data Data_1 to write the first data Data_1 into the first storage array; within the range of 1 ⁇ i ⁇ 21, the i-th selection circuit outputs the i-th data, that is, the 2nd to 20th selection circuits respectively output the second data Data_2 to the 20th data Data_20 to write the second data Data_2 to the 20th data Data_20 into the 2nd to 20th storage arrays respectively; the 21st selection circuit does not output data to avoid writing data to the column where the faulty storage array is located; within the range of 21 ⁇ i ⁇ 35, the i-th selection circuit outputs the i-th data, that is, the 2nd to 20th selection circuits respectively output the second data Data_2 to the 20th data Data_20 to write the second data Data_2 to the 20th data Data_20 into the 2nd to 20th storage arrays respectively.
  • the i selection circuit outputs the i-1th data, that is, the 22nd to 34th selection circuits output the 21st data Data_21 to the 33rd data Data_33 respectively, so as to write the 21st data Data_21 to the 33rd data Data_33 into the 22nd to 34th storage arrays respectively; the 35th selection circuit outputs the 34th data Data_34, so as to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate writing of data.
  • the first selection circuit when a failed storage cell in the first storage array is replaced by a redundant array, the first selection circuit does not output the first data, the Nth selection circuit outputs the N-1th data, and the i-th selection circuit outputs the i-1th data.
  • the storage array that fails is the first storage array.
  • the column where the failed storage unit in the first storage array is located no longer stores data, and the first data Data_1 originally to be written into the first storage array needs to be written into the second storage array, and the second data Data_2 originally to be written into the second storage array needs to be written into the third storage array, and so on, until the 17th data Data_17 originally to be written into the 17th storage array needs to be written into the 18th storage array (redundant array), and the failure replacement is completed.
  • the first selection circuit does not output the first data Data_1 to avoid writing data to the column where the faulty storage unit is located; the i-th selection circuit outputs the i-1-th data, that is, the 2nd to 34th selection circuits output the first data Data_1 to the 33rd data Data_33 respectively, to write the first data Data_1 to the 33rd data Data_33 into the 2nd to 34th storage arrays respectively; the 35th selection circuit outputs the 34th data Data_34 to write the 34th data Data_34 into the 35th storage array, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • the 1st selection circuit when a failed memory cell in the Nth memory array is replaced by a redundant array, the 1st selection circuit outputs the 1st data, the Nth selection circuit outputs no data, and the i-th selection circuit outputs the i-th data.
  • the storage array that fails is the 35th storage array.
  • the column where the failed storage unit of the 35th storage array is located no longer stores data.
  • the 34th data Data_34 that was originally to be written into the 35th storage array needs to be written into the 34th storage array
  • the 33rd data Data_33 that was originally to be written into the 34th storage array needs to be written into the 33rd storage array, and so on, until the 18th data Data_18 that was originally to be written into the 19th storage array needs to be written into the 18th storage array (redundant array), and the failure replacement is completed.
  • the 1st selection circuit outputs the 1st data Data_1 to write the 1st data Data_1 into the 1st storage array; the i-th selection circuit outputs the i-th data, i.e., the 2nd to 34th data.
  • the selection circuits output the second data Data_2 to the 34th data Data_34 respectively to write the second data Data_2 to the 34th data Data_34 into the second to the 34th storage arrays; the 35th selection circuit does not output the 34th data Data_34 to avoid writing data into the column where the faulty storage unit is located, so that the selection circuit outputs complete data, and then the storage array can accurately store the data output by the selection circuit, thereby realizing accurate data writing.
  • the number of redundant arrays is multiple and the redundant arrays are not adjacent.
  • the redundant columns in the 7th storage array can be used to replace the columns where the faulty storage units in the 1st storage array to the 6th storage array are located, and the redundant columns in the 15th storage array can be used to replace the columns where the faulty storage units in the 16th storage array to the 35th storage array are located.
  • the main storage array between two adjacent redundant arrays for example, the 8th storage array to the 14th storage array
  • they can be divided during design, for example, the 8th storage array to the 9th storage array are divided into the 7th storage array responsible for fault replacement, and the 10th storage array to the 14th storage array are divided into the 15th storage array responsible for fault replacement.
  • the control mechanism for executing fault replacement and selecting circuits is similar to the aforementioned scheme.
  • the memory provided by the embodiment of the present disclosure includes N memory arrays arranged in sequence, including at least one main memory array and at least one redundant array, the redundant array is used to provide faulty unit replacement of the main memory array, and N selection circuits, each selection circuit receives data corresponding to the bit sequence and the previous adjacent data, each selection circuit responds to its own selection signal, and outputs a corresponding signal by selection to achieve data processing in a fault replacement scenario.
  • the memory of this solution sets multiple selection circuits, and controls the selection circuit to output corresponding data according to the faulty unit replacement situation of the memory, thereby achieving data processing under fault replacement and ensuring the accuracy and reliability of data processing.

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Abstract

一种存储器，包括：依次排列的N个存储阵列，其中至少一个存储阵列为冗余阵列，且至少一个存储阵列为主存储阵列，冗余阵列用于替换主存储阵列中的故障存储单元；N个选择电路，接收N-1组数据；其中，第1选择电路接收第1数据，用于根据第1选择信号向第1存储阵列输出或不输出第1数据；第N选择电路接收第N-1数据，用于根据第N选择信号向第N存储阵列输出或不输出第N-1数据；第i选择电路接收第i-1数据和第i数据，且第i选择电路用于根据第i选择信号向第i存储阵列输出第i-1数据或第i数据。本方案通过设置多个选择电路，根据存储器的故障单元替换情况，控制选择电路输出相应的数据，从而实现故障替换下的数据处理，保证数据处理的准确性和可靠性。

Description

存储器
本公开要求于2022年11月02日提交中国专利局、申请号为202211361069.8、申请名称为“存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储器技术，尤其涉及一种存储器。
背景技术
伴随存储器技术的发展，存储器被广泛应用在多种领域，比如，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的使用非常广泛。
实际应用中，在存储器的生产和使用过程中，存储单元可能会产生故障，故障存储单元不能正常工作，需要进行替换修复。因此，结合考虑可能进行替换修复的情况，如何保证存储器实现准确的数据处理，成为需要考虑的问题。
发明内容
本公开的实施例提供一种存储器。
根据一些实施例，本公开第一方面提供一种存储器，包括：依次排列的N个存储阵列，所述N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个所述存储阵列为冗余阵列，且至少一个所述存储阵列为主存储阵列，所述冗余阵列用于替换所述主存储阵列中的故障存储单元，1＜i＜N，2≤N且i和N为正整数；N个选择电路，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N选择电路，所述N个选择电路接收N-1组数据，分别记为第1数据，第2数据，…，第i数据，…，第N-1数据；其中，所述第1选择电路接收所述第1数据，用于根据第1选择信号向所述第1存储阵列输出或不输出所述第1数据；所述第N选择电路接收所述第N-1数据，用于根据第N选择信号向所述第N存储阵列输出或不输出所述第N-1数据；第i选择电路接收所述第i-1数据和所述第i数据，且所述第i选择电路用于根据第i选择信号向所述第i存储阵列输出所述第i-1数据或所述第i数据。
在一些实施例中，所述存储阵列和所述冗余阵列均包括M个列，分别记为第1列，第2列，…，第j列，…，第M列，所述冗余阵列的第j列用于替换任意一个所述主存储阵列的第j列，1≤j≤M，且j和M为正整数。
在一些实施例中，所述选择电路包括：多个子选择电路，所述第1选择电路的每一所述子选择电路 接收第1数据中的1bit数据，所述第i选择电路的每一所述子选择电路分别接收所述第i-1数据和所述第i数据中的1bit数据，所述第N选择电路的每一所述子选择电路接收第N-1数据中的1bit数据。
在一些实施例中，所述子选择电路包括数据选择器，所述第1选择电路的所述数据选择器的第一数据输入端接收所述第1数据中的1bit数据，所述第1选择电路的所述数据选择器的选择端接收所述第1选择信号，所述第i选择电路的所述数据选择器的第一数据输入端接收所述第i-1数据中的1bit数据，所述第i选择电路的所述数据选择器的第二数据输入端接收所述第i数据中的1bit数据，所述第i选择电路的所述数据选择器的选择端接收所述第i选择信号，所述第N选择电路的所述数据选择器的第一数据输入端接收所述第N-1数据中的1bit数据，所述第N选择电路的所述数据选择器的选择端接收所述第N选择信号。
在一些实施例中，所述冗余阵列的数量为一个。
在一些实施例中，所述第1存储阵列为所述冗余阵列。
在一些实施例中，当不存在故障存储单元时，所述第1选择电路不输出数据，所述第N选择电路输出所述第N-1数据，所述第i选择电路输出所述第i-1数据；当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n为正整数；当所述第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第i选择电路输出所述第i数据，所述第N选择电路不输出数据。
在一些实施例中，所述第N存储阵列为所述冗余阵列。
在一些实施例中，当不存在故障存储单元时，所述第1选择电路输出所述第1数据，所述第N选择电路不输出数据，所述第i选择电路输出所述第i数据；当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出所述第i-1数据，n为正整数；当所述第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路不输出数据，所述第i选择电路输出所述第i-1数据，所述第N选择电路输出所述第N-1数据。
在一些实施例中，第m存储阵列为所述冗余阵列，1＜m＜N且m为正整数。
在一些实施例中，当不存在故障存储单元时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，第m选择电路不输出数据，且在1＜i＜m的范围内，所述第i选择电路输出所述第i数据，在m＜i＜N的范围内，所述第i选择电路输出所述第i-1数据；当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，第n选择电路不输出数据，在1＜i＜n的范围内，所述第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n＜m且n为正整数；当第k存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数 据，第k选择电路不输出数据，在1＜i＜k的范围内，所述第i选择电路输出所述第i数据，在k＜i＜N的范围内，第i选择电路输出第i-1数据，m＜k＜N且k为正整数；当第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路不输出数据，所述第N选择电路输出所述第N-1数据，所述第i选择电路输出所述第i-1数据；当第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路不输出数据，所述第i选择电路输出所述第i数据。
在一些实施例中，所述冗余阵列的数量为多个且所述冗余阵列不相邻。
在一些实施例中，至少一个所述主存储阵列为校验码存储阵列，所述校验码存储阵列用于存储校验码数据。
在一些实施例中，所述存储器还包括：校验模块；所述校验模块与所述N个选择电路连接，所述N个选择电路接收的数据包括待写入数据和校验码数据，所述校验模块用于根据所述待写入数据，生成所述校验码数据。
本公开实施例提供的存储器，包括依次排列的N个存储阵列，其中包含至少一个主存储阵列和至少一个冗余阵列，冗余阵列用于提供主存储阵列的故障单元替换，以及N个选择电路，每个选择电路接收位序对应的数据以及上一相邻数据，每个选择电路响应于自身的选择信号，通过选择输出相应的信号，实现故障替换场景下的数据处理。本方案的存储器通过设置多个选择电路，根据存储器的故障单元替换情况，控制选择电路输出相应的数据，从而实现故障替换下的数据处理，保证数据处理的准确性和可靠性。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开实施例的原理。
图1为一实施例示出的存储器的架构示例图；
图2为一实施例示出的存储单元的结构示例图；
图3和图4分别为一种示例的替换方案架构图；
图5为一实施例提供的存储器的结构示例图；
图6和图7分别为不同情形下的状态示例图；
图8为存储阵列的架构示例图；
图9为一示例的存储器的结构示例图；
图10～图12分别为不同情形下的状态示例图；
图13为一示例的存储器的结构示例图；
图14～图16分别为不同情形下的状态示例图；
图17为一示例的存储器的结构示例图；
图18～图21分别为不同情形下的状态示例图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开中的用语“包括”和“具有”用以表示开放式的包括在内的意思，并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记或区分使用，不是对其对象的先后顺序或数量限制。此外，附图中的不同元件和区域只是示意性示出，因此不限于附图中示出的尺寸或距离。
下面以具体的实施例对技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为一实施例示出的存储器的架构示例图，如图1所示，以DRAM作为示例，包括数据输入/输出缓冲、行解码器、列解码器、感测放大器以及存储阵列。其中，数据输入/输出缓冲属于外围区电路，感测放大器、行解码器、列解码器以及存储阵列属于阵列区电路。存储阵列主要由字线、位线和存储单元组成。存储阵列中的字线沿行方向延伸，存储阵列中的位线沿列方向延伸，字线与位线的交叉处为存储阵列的存储单元。
其中，每个存储单元用于存储一个位(bit)的数据。如图2所示，图2为一实施例示出的存储单元的结构示例图，存储单元主要由晶体管开关M和电容C组成。其中，电容用于存储数据，晶体管开关用于根据选中状态，关断或导通。
可以通过控制字线和位线来激活某个存储单元，以实现对该存储单元的访问。结合读取场景作为示例：需要读取存储单元中的数据时，可以通过行解码器选中该存储单元所在行的字线，相应的，图示中的晶体管M导通，通过对位线信号的感测放大就可以感知到此时电容C上的状态。例如，如果存储单元中存储的bit数据为1，那么晶体管M导通后就会从存储单元的位线上读到1，反之也是同样的道理。另外，结合写入场景作为示例：需要向某存储单元中写入bit数据时，比如写入1。可以通过行解码器选中该存储单元所在行的字线，相应的图示中的晶体管M导通，通过将位线的逻辑电平设为1，使得电容C充电，即向存储单元写入1。反之，如果要写入0，那么位线的逻辑电平设为0，使得电容C放电，即向存储单元写入0。
实际应用中，DRAM在生产过程中有一定概率会产生故障的存储单元，或者，伴随着设备的老化损坏，尤其是运行环境存在挑战(高温环境)，并且需要频繁运行的存储器，在存储阵列中可能产生故障存储单元。这些故障存储单元不能正常工作，因此为了避免故障存储单元影响存储器的正常工作，在设计时除了规划包含常规存储单元的主存储阵列以外，还会规划冗余阵列，冗余阵列中的存储单元作为冗余部分，用于实现对主存储阵列中故障存储单元的替换。
本文中的“替换”指存储功能上的替换，即保证替换后能正常用于存储数据的存储单元的数量即可，具体的替换方式包括但不限于，用冗余存储单元存储故障存储单元原本需要存储的bit数据，或者，只需保证加入冗余存储单元后，能够正常工作的存储单元的数量可以保证完整数据的储存即可，至于哪个存储单元存储哪个bit数据则不做限制。
在一些替换方案中，比如LCR(Local Column Repair)方案，会在存储阵列中设计包含常规存储单元的存储列，以及包含冗余存储单元的冗余列，冗余列和存储列共享该存储阵列的数据线，数据线用于传输读取或写入的数据。为了进一步便于设计，在一些替换方案里，比如CCR(Central Column Repair)方案中，所有冗余存储单元设置在独立的冗余阵列中，冗余阵列和常规的存储阵列分别独立设置，各自具有独立的数据线，故需要提供一种有效方案支持该架构下，发生故障替换时的数据处理，比如，数据的正常写入。
为便于理解，如图3和图4所示，图3和图4分别为一种示例的替换方案架构图，以存储器包括N个存储阵列作为示例，分别为第1存储阵列、第2存储阵列，…第N存储阵列。图3采用的故障替换方案为LCR方案，图中填充阴影的列为冗余列，未填充阴影的部分为常规的存储列，可知LCR方案中，各冗余列集成于每个存储阵列中，每个存储阵列下的存储列和冗余列共享数据线。图4采用的故障替换方案为CCR方案，图中填充阴影的阵列为冗余阵列，未填充阴影的部分为常规的主存储阵列，可知CCR方案中，独立设置冗余阵列，冗余阵列中的存储单元用于替换主存储阵列中故障的存储单元，每个阵列配置有独立的数据线。需要说明的是，图中只是一种示例，具体的阵列架构可以根据实际需要调整，而不限于图中的示例。
本公开实施例的一些方面涉及上述考虑。以下结合本公开的一些实施例对方案进行示例介绍。图5为一实施例提供的存储器的结构示例图，如图5所示，该存储器包括：
依次排列的N个存储阵列11，N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个存储阵列为冗余阵列，且至少一个存储阵列为主存储阵列，冗余阵列用于替换主存储阵列中的故障存储单元，1＜i＜N，2≤N且i和N为正整数；
N个选择电路12，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N选择电路，N个选择电路接收N-1组数据，分别记为第1数据，第2数据，…，第i数据，…，第N-1数据；
其中，第1选择电路接收第1数据，用于根据第1选择信号向第1存储阵列输出或不输出第1数据；第N选择电路接收第N-1数据，用于根据第N选择信号向第N存储阵列输出或不输出第N-1数据；第i 选择电路接收第i-1数据和第i数据，且第i选择电路用于根据第i选择信号向第i存储阵列输出第i-1数据或第i数据，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
其中，选择电路接收的数据组数量可以根据实际需要写入存储器的数据量确定。实际应用中，本实施例提供的存储器的类型不限，作为示例，可以应用在包括但不限于双倍速率同步动态随机存储器(简称DDR)等。
其中，存储阵列中的主存储阵列用于在未存在故障存储单元的情况下存储写入的数据。实际应用中，为了在后续进行数据读取时，验证数据读取的准确性，可以对读取的数据进行数据校验。故在一个示例中，至少一个主存储阵列为校验码存储阵列，校验码存储阵列用于存储校验码数据。故最终写入N个存储阵列的数据将包含待写入数据Data_CP，以及校验码数据Data_ECC。其中，校验码存储阵列用于存储校验码数据可解释为，校验码存储阵列在不存在故障存储单元时，正常存储校验码数据，可以理解，如果校验码存储阵列中存在故障存储单元，也可用冗余阵列对校验码存储阵列中的故障存储单元进行替换，相应的，故障存储单元对应的校验码数据将被写入在进行替换之后的某个存储单元中。
实际应用中，在数据写入、读取和传输的过程中可能产生错误，故为了避免和及时发现这种错误，可以采用数据校验方法对读取出的数据进行校验。作为示例，数据校验方法可以包括但不限于奇偶校验、循环冗余校验等，在校验方案中，需要基于校验码数据进行校验，故在向存储阵列中写入数据时，会一并生成并写入校验码数据，以便在数据读取时，根据读出的校验码数据对读出的存储数据进行数据校验。相应的，在一个示例中，存储器还包括：校验模块13；校验模块13与N个选择电路12连接，N个选择电路12接收的数据包括待写入数据和校验码数据，校验模块13用于根据所述待写入数据，生成所述校验码数据。本示例通过设置校验码模块，能够在数据写入时生成相应的校验码数据存至存储阵列中，以便在读取数据时对读取的数据进行数据校验，从而进一步提高数据处理的准确性和可靠性。
下面结合附图，对本实施例的电路工作原理进行示例：以一次写入的完整数据为34组数据进行举例，记为第1数据Data_1～第34数据Data_34，第18存储阵列为冗余阵列。实际应用中，一次写入的数据长度和内容可以根据存储器的类型和工作参数确定。其中，第1数据Data_1表示完整的34组数据中，在正常情况下应写入至第1个主存储阵列中的数据；第2数据Data_2表示完整的34组数据中，正常情况下应写入第2个主存储阵列中的数据；以此类推。可以理解，当主存储阵列不存在故障时，冗余阵列中可以不存储数据，即为空数据；或者，当主存储阵列中的故障存储单元所在的列被冗余阵列替换后，冗余阵列中的数据具体为替换故障存储单元后存储的数据，该数据可能是34组数据中的其中一组，具体为哪组数据可根据实际情况确定，后述会进行举例说明。
首先，图6为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。当主存储阵列中没有故障存储单元时，写入的34组数据应存储在对应的主存储阵列中。结合图中的示例，假设存储器包含35个存储阵列，即N＝35，其中冗余阵列为第18存储阵列，其余的第1存储阵列至第17存储阵 列以及第19存储阵列至第35存储阵列均为主存储阵列。具体的，写入数据中的第1数据Data_1需存储于第1存储阵列(第1个主存储阵列)，第2数据Data_2需存储于第2存储阵列(第2个主存储阵列)，以此类推，直至第17数据Data_17需存储于第17存储阵列(第17个主存储阵列)，之后第18存储阵列为冗余阵列，故不存储数据，再之后，第18数据Data_18需存储于第19存储阵列(第18个主存储阵列)，第19数据Data_19需存储于第20存储阵列(第19个主存储阵列)，以此类推，直至第34数据Data_34需存储于第35存储阵列(第34个主存储阵列)。
相应的，第1选择电路接收第1数据，第N选择电路接收第N-1数据，第i选择电路接收第i-1数据以及第i数据。结合图6所示，第1选择电路接收第1数据Data_1，第2选择电路接收第1数据Data_1和第2数据Data_2，…第17选择电路接收第16数据Data_16和第17数据Data_17，第18选择电路接收第17数据Data_17和第18数据Data_18，第19选择电路接收第18数据Data_18和第19数据Data_19，…第34选择电路接收第33数据Data_33和第35数据Data_34，第35选择电路接收第34数据Data_34。基于上述情形，当不存在故障存储单元时，第1选择电路输出第1数据，以将第1数据Data_1写入第1存储阵列，N个选择电路中，在1＜i＜18的范围内，第i选择电路选择输出第i数据，以将第i数据写入第i存储阵列，在18＜i＜35的范围内，第i选择电路选择输出第i-1数据Data_i-1，以将第i-1数据Data_i-1写入第i存储阵列，所述第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
以上为不存在故障存储单元的情形。作为示例，图7为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。仍结合图6所示的架构，以第1存储阵列存在故障存储单元为例，在图7中，冗余阵列(第18存储阵列)用于替换第1存储阵列中的故障存储单元。在一个示例中，原本需要写入第1存储阵列的第1数据Data_1需写入第2存储阵列，原本需写入第2存储阵列的第2数据Data_2需写入第3存储阵列，直至原本需写入第17存储阵列中的第17数据Data_17需写入冗余阵列(第18存储阵列中)，实现对第1存储阵列中故障存储单元的替换。此时，第1存储阵列中的故障存储单元所在的列可以不存储储据，故第1选择电路不输出第1数据Data_18，第19～35选择电路分别输出第18数据Data_18～第34数据Data_34，进而将第18数据Data_18～第34数据Data_34分别写入至第19～第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
本实施例中，针对N个存储阵列设置N个选择电路，能够在无论是否发生故障存储单元替换的情形下，通过控制选择电路选择输出相应的数据，来实现完整数据的准确写入，保证数据处理的准确性和可靠性。并且本实施例的方案，便于电路设计和制备，可以适用于存储器等集成度高的场景。
其中，选择电路12的具体实现电路可以根据实际情况设计。作为示例，图8为存储阵列的架构示例图，如图8所示，主存储阵列和所述冗余阵列均包括多个列，例如M个列，分别记为第1列，第2列，…， 第j列，…，第M列。
具体的，冗余阵列的第j列用于替换所述主存储阵列的第j列，其中1≤j≤M，且j和M为正整数。需要说明的是，这里的单个“列”指单个列选择信号的控制对象。举例来说，存储阵列在物理结构上包括多个物理行(例如理解为字线wordline)和多个物理列(例如理解为位线bitline)。在一些存储器设计方案中，将一个存储阵列中的多个物理列划分为多组列，每组列中的所有物理列受控于同一个列选择信号，不同组的列受控的列选择信号不同。举例来说，假设某存储阵列包含16个物理列，按照每4个物理列进行划分，将得到4列(column_1～column_4)，column_1～column_4分别对应列选择信号1～列选择信号4，每个column中的4个物理列对应同一列选择信号，每个column可视为本示例所述的一个“列”。需要说明的是，在多个存储阵列的情形下，同一列选择信号用于选中不同存储阵列中的相同列，这里的相同列指在不同存储阵列中位置相同的列，比如列选择信号1用于选中所有存储阵列中的column_1。在另一些存储器设计方案中，本示例中的单个“列”即单个物理列，比如，某存储阵列包含8个物理列，分别受控于8个列选择信号，则此时的每一物理列可视为本示例所述的一个“列”。本实施例在此不对此进行限制。
以匹配前一种设计方案作为示例，在一个示例中，选择电路12包括：多个子选择电路121，第1选择电路的每一子选择电路接收第1数据中的1bit数据，第i选择电路的每一子选择电路分别接收第i-1数据和第i数据中的1bit数据，第N选择电路的每一子选择电路接收第N-1数据中的1bit数据。
结合图8所示，结合第一种设计方案，存储器的数据写入过程示例如下：如图8所示，示出了多个存储阵列11，每个存储阵列11包括多个列21，图中以其中一个存储阵列的放大图作为示例，每个列21进一步由多个物理列(比如4bit)构成。当进行数据写入时，列解码器会从写入指令中解析出列选择信号，比如，列选择信号表征第1列的地址。响应于该列选择信号，多个存储阵列11的第1列被选中。故结合前述图6的示例，第i数据包括需要写入某存储阵列的第1列的4bit数据，即第1数据包括需写入某存储阵列的第1列的4bit数据，第2数据包括需写入另一存储阵列的第1列的4bit数据，以此类推。故每一选择电路对应包括4个子选择电路，分别对应4bit数据中的1bit数据，且每一选择电路的输出端均连接对应存储阵列的数据线，选择电路输出的数据通过数据线写入至对应的存储阵列。
具体的，第i选择电路中的每一子选择电路接收第i-1数据(包括4bit数据)中的1个bit数据，以及第i数据(包括4bit数据)中的1个bit数据，第N选择电路的每一子选择电路接收第N-1数据中的1bit数据。其中，该列选择信号在不同存储阵列选中的列的位置相同，这里子选择电路接收的两个bit数据需写入的物理列，分布在不同的两个存储阵列的位置相同的列，且在各自列中的位置相同。比如，假设列选择信号为第1列的地址，则第2选择电路的第1子选择电路接收的两个bit数据，分别来自第1数据的4bit中的第1个bit，以及第2数据的4bit中的第1个bit。
故可以理解，实际应用中，选择电路可以包括一个或多个子选择电路，同一选择电路中子选择电路的选择信号相同。故在一个示例中，同一选择电路中的子选择电路可以共享一个选择信号，不同选择电 路接收各自独立的选择信号。
结合前述，子选择电路用于响应于选择信号从接收的数据中选择一个数据输出。实际应用中，子选择电路的实现方式不限，在一个示例中，子选择电路包括数据选择器MUX，第1选择电路的数据选择器的第一数据输入端接收第1数据中的1bit数据，第1选择电路的数据选择器的选择端接收第1选择信号，第i选择电路的数据选择器的第一数据输入端接收第i-1数据中的1bit数据，第i选择电路的数据选择器的第二数据输入端接收第i数据中的1bit数据，第i选择电路的数据选择器的选择端接收第i选择信号，第N选择电路的数据选择器的第一数据输入端接收第N-1数据中的1bit数据，第N选择电路的数据选择器的选择端接收所述第N选择信号，其中第1选择电路的的数据选择器的第二数据输入端和第N选择电路的数据选择器的第一数据输入端可以不接收任何数据，例如为浮置端，或者接收固定电平信号，例如接地或电源电压VDD。
本示例中，数据选择器如何根据选择信号的电平高低来输出数据可以根据实际需求设置，例如当第1选择信号为高电平的时候，第1选择电路的数据选择器的输出端输出第1数据中的1bit数据，第1选择信号为低电平的时候，第1选择电路的数据选择器的输出端不输出数据，当第i选择信号为高电平的时候，第i选择电路的数据选择器的输出端输出第i数据中的1bit数据，当第i选择信号为低电平的时候，第i选择电路的数据选择器的输出端输出第i-1数据中的1bit数据，当第N选择信号为高电平的时候，第N选择电路的数据选择器的输出端输出第N-1数据中的1bit数据，第N选择信号为低电平的时候，第N选择电路的数据选择器的输出端不输出第N-1数据，其中当数据选择器的选择端不接收信号的时候，即数据选择器的选择端为浮置状态，此时数据选择器不输出任何数据，从而实现根据选择信号选择输出相应的数据，并且通过常规器件实现子选择电路，能够简化电路结构，降低成本。
在一个示例中，第1选择电路中的子选择电路包括一个第一开关管，第一开关管的第一端接收第1数据中的1bit，第一开关管的第二端为子选择电路的输出端，第一开关管根据第1选择信号闭合或断开，第i选择电路中的子选择电路包括第二开关管和第三开关管，第二开关管的第一端接收第i-1数据中的1bit，第三开关管的第一端接收第i数据中的1bit，第二开关管的第二端和第三开关管的第二端作为子选择电路的输出端，其中第二开关管或第三开关管根据第i选择信号闭合，或第二开关管和第三开关管根据第i选择信号都断开，第N选择电路中的子选择电路包括第四开关管，第四开关管的第一端接收第N-1数据中的1bit，第四开关管的第二端为子选择电路输出端，第四开关管根据第N选择信号闭合或断开。
实际应用中，各存储阵列的排布可以根据需要设计。作为示例，冗余阵列的数量可以为一个或多个。以冗余阵列的数量为一个作为示例，冗余阵列的排布情形也有多种。比如，冗余阵列可以位于整个存储阵列的边缘，例如第1存储阵列或者第N存储阵列为冗余阵列。再比如，冗余阵列可以位于存储阵列之间，例如，第m存储阵列为冗余阵列，1<m<N且m为正整数。
在一个示例中，冗余阵列的数量为一个。具体的，冗余阵列中的每列可以用于替换任一主存储阵列中位置相同的列，比如，冗余阵列中的第1列可以用于替换任意一个主存储阵列的第1列，该冗余阵列 中的第2列可以用于任意一个主存储阵列的第2列。或者，当某一主存储阵列的两个列都存在故障存储单元时，也可用冗余阵列中位置相同的两个列进行替换。通过设置冗余阵列能够实现故障存储单元的替换。
结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图9为一示例的存储器的结构示例图，如图9所示，第1存储阵列为冗余阵列，图中填充阴影的存储阵列为冗余阵列，未填充阴影的存储阵列为主存储阵列。
下面结合附图，对冗余阵列为第1存储阵列时的电路工作原理进行示例：仍以一次写入的完整数据为34组数据进行举例。图10为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。具体的，当不存在故障存储单元时，所述第1选择电路不输出第1数据Data_1，所述第35选择电路输出所述第34数据Data_34，所述第i选择电路输出所述第i-1数据。
结合图10的示例，第1存储阵列为冗余阵列，第2～35存储阵列均为主存储阵列。第1存储阵列为冗余阵列，故在主存储阵列没有发生故障时，第1存储阵列中故障存储存储单元所在的列不存储数据，此时第1选择电路不输出第1数据Data_1，第2选择电路～第35选择电路分别输出第1数据Data_1～第34数据Data_34，以将第1数据Data_1～第34数据Data_34分别写入第2～35存储阵列(34个主存储阵列)。基于上述情形，N个选择电路中，第1选择电路不输出第1数据Data_1，所述第i选择电路输出所述第i-1数据，第35选择电路输出所述第34数据Data_34，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
图11为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。具体的，当第n存储阵列中的故障存储单元所在的列被所述冗余阵列替换时，当根据故障存储单元所在的列的列地址向存储阵列写入数据时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n为正整数，第n选择电路可以不输出数据，能够节约功耗，也可以输出第n-1数据和第n数据中的任一个，因为故障存储单元所在的列是否存储数据不影响整体数据的存储，只需要在数据读出的时候不从故障存储单元所在的列读出数据即可。
结合图11举例来说，某个主存储阵列存在故障存储单元，且该主存储阵列并非最后一个存储阵列，比如，假设图11中第17存储阵列存在故障存储单元，即n＝17为例，结合图中的示例，不向第17存储阵列的故障存储单元所在的列写入数据，原本需写入第17存储阵列的第16数据Data_16需写入第16存储阵列，原本需写入第16存储阵列的第15数据Data_15需写入第15存储阵列，...以此类推，直至原本需写入第2存储阵列的第1数据Data_1需写入第1存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了按照上述故障修复方案准确写入数据，第1选择电路输出第1数据Data_1，以将第1数据Data_1写入第1存储阵列；在1＜i＜17的范围内，第i选择电路输出第i数据，即第2～16选择电路分别输出第2数据Data_2～第16数据Data_16，进而将第2数据Data_2～第16数据Data_16分别写入至第2～16存储 阵列；第17选择电路不输出数据，以避免向故障存储单元所在的列写入数据；在17＜i＜35的范围内，第i选择电路输出第i-1数据，即第18～34选择电路输出第17数据Data_17～第33数据Data_33，以将第17数据Data_17～第33数据Data_33分别写入第18～34存储阵列；此时第35选择电路输出第34数据Data_34，以向第35存储阵列写入第34数据Data_34，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
再具体的，当第N存储阵列中的故障存储单元被冗余阵列替换时，第1选择电路输出第1数据，第i选择电路输出第i数据，第N选择电路不输出数据。即在冗余阵列为首个存储阵列，存在故障被替换的存储阵列为最后一个存储阵列时，所有选择电路均选择向第i存储阵列输出第i数据。
结合图12举例来说，某个主存储阵列存在故障存储单元，且该主存储阵列为最后一个存储阵列，比如，图12中第35存储阵列存在故障存储单元，结合图10的示例，为了执行故障存储单元替换，第35存储阵列中故障存储单元所在的列不存储数据，原本需写入第35存储阵列的第34数据Data_34需写入第34存储阵列，原本需写入第34存储阵列的第33数据Data_33需写入第33存储阵列，...以此类推，直至原本需写入第2存储阵列的第1数据Data_1需写入第1存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了实现上述替换策略以准确写入数据，第1选择电路输出第1数据Data_1，以将第1数据Data_1写入第1存储阵列；第i选择电路输出从第i数据，即第2～34选择电路分别输出第2数据Data_2～第34数据Data_34，以将第2数据Data_2～第34数据Data_34分别写入至第2～34存储阵列；此时第35选择电路不输出第34数据Data_34，以避免向故障存储单元所在的列写入数据，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
仍结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图13为一示例的存储器的结构示例图，如图13所示，第N存储阵列为冗余阵列。也就是说，冗余阵列设置在最后一个存储阵列。图中填充阴影的存储阵列为冗余阵列，未填充阴影的存储阵列为主存储阵列。
下面结合附图，对冗余阵列为第N存储阵列时的电路工作原理进行示例：仍以一次读取的完整数据为34组数据进行举例。图14为一种情形下的状态示例图，该情形为主存储阵列中未存在故障存储单元。具体的，当不存在故障存储单元时，第1选择电路输出第1数据Data_1，第35选择电路不输出第34数据Data_34，第i选择电路输出第i数据。
结合图14的示例，第35存储阵列为冗余阵列，第1～34存储阵列均为主存储阵列。第35存储阵列为冗余阵列，故第35存储阵列在主存储阵列没有故障时不写入数据，第1数据Data_1～第34数据Data_34分别需写入第1～34存储阵列(34个主存储阵列)。相应的，结合图所示，第1选择电路输出所述第1数据Data_1，以将第1数据Data_1写入第1存储阵列，第2～34选择电路分别输出第2数据Data_2～第34数据Data_34，以将第2数据Data_2～第34数据Data_34分别写入至第2～34存储阵列；此时第35选择电路不输出第34数据Data_34。基于上述情形，第1选择电路输出第1数据Data_1，第i选择电路输出第i数据Data_i，第35选择电路不输出第34数据，从而使得选择电路输出完整的数据，进而存储阵列 能够准确存储选择电路输出的数据，实现数据的准确写入。
图15为另一种情形下的状态示例图，该情形为主存储阵列中存在故障存储单元。具体的，当第n存储阵列中的故障存储单元所在的列被冗余阵列替换时，第1选择电路输出第1数据，第N选择电路输出第N-1数据，在1＜i＜n的范围内，第i选择电路输出第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n为正整数。
结合图15举例来说，假设某个主存储阵列存在故障存储单元，且该主存储阵列并非首个存储阵列，比如，假设图15中第17存储阵列存在故障存储单元，即n＝17为例，结合图14的示例，需执行故障存储单元替换，故不向第17存储阵列的故障存储单元所在的列写入数据，原本需写入至第17存储阵列的第17数据Data_17需写入至第18存储阵列，原本需写入至第18存储阵列的第18数据Data_18需写入至第19存储阵列，...以此类推，直至原本需写入至第34存储阵列的第34数据Data_34需写入至第35存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了准确写入数据，第1选择电路输出所述第1数据Data_1，以将第1数据Data_1写入第1存储阵列；在1＜i＜17的范围内，第i选择电路输出第i数据，即第2～16选择电路分别输出第2数据Data_2～第16数据Data_16，以将第2数据Data_2～第16数据Data_16分别写入第2～16存储阵列；第17选择电路不输出数据，以避免向故障存储单元所在的列写入数据；在17＜i＜35的范围内，第i选择电路输出第i-1数据，即第18～34选择电路分别输出第17数据Data_17～第33数据Data_33，以将第17数据Data_17～第33数据Data_33分别写入第18～34存储阵列；此时第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
再具体的，当第1存储阵列中的故障存储单元所在的列被冗余阵列替换时，第1选择电路不输出第1数据，第i选择电路输出第i-1数据，第N选择电路输出第N-1数据。即在冗余阵列为最后一个存储阵列，存在故障被替换的存储阵列为首个存储阵列时，所有选择电路均选择输出第i-1数据。结合图16举例来说，首个存储阵列存在故障存储单元，比如，图16中第1存储阵列存在故障存储单元，结合图16的示例，需执行故障存储单元替换，由于第1存储阵列发生故障，故不向第1存储阵列中故障存储单元所在的列写入数据，第1选择电路不输出第1数据Data_1，原本需写入第1存储阵列的第1数据Data_1需写入第2存储阵列，原本需写入第2存储阵列的第2数据Data_2需写入第3存储阵列，...以此类推，直至原本需写入第34存储阵列的第34数据Data_34需写入第35存储阵列(冗余阵列)，从而实现故障单元替换。相应的，为了准确写入数据，第1选择电路不输出第1数据Data_1，以避免向故障存储单元所在的列写入数据；第i选择电路输出第i-1数据，即第2～34选择电路分别输出第1数据Data_1～第33数据Data_33，以将第1数据Data_1～第33数据Data_33分别写入第2～34存储阵列；第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
继续结合一个冗余阵列的不同位置，作为上述示例的一种可能的方式，图17为一示例的存储器的结 构示例图，如图17所示，第m存储阵列为冗余阵列，1<m<N且m为正整数。也就是说，冗余阵列设置在并非首个或最后一个存储阵列。
下面结合附图，对冗余阵列为第m存储阵列时的电路工作原理进行示例：仍以一次读取的完整数据为34组数据进行举例，可结合前述的图6进行示例。图6中示例的冗余阵列为第18存储阵列，即m＝18。当主存储阵列没有故障存储单元时的状态，如图6所示。当不存在故障存储单元时，第1选择电路输出所述第1数据，第N选择电路输出所述第N-1数据，第m选择电路不输出数据，且在1＜i＜m的范围内，第i选择电路输出所述第i数据，在m＜i＜N的范围内，第i选择电路输出所述第i-1数据。结合图6所示，当不存在故障存储单元时，第1选择电路输出第1数据Data_1，以将第1数据Data_1写入第1存储阵列，在1＜i＜18的范围内，第i选择电路选择输出第i数据，即第2～17选择电路输出第2数据Data_2～第17数据Data_17，以将第2数据Data_2～第17数据Data_17分别写入第2～17存储阵列；由于冗余阵列(第18存储阵列)在主存储阵列正常时无需存储数据，故第18选择电路不输出数据；在18＜i＜35的范围内，第i选择电路选择输出第i-1数据，即第19～34选择电路分别输出第18数据Data_18～第33数据Data_33，以将第18数据Data_18～第33数据Data_33分别写入第19～34存储阵列；此时第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
当主存储阵列中存在故障存储单元时，图18～图21分别为不同情形下的状态示例图。在一个示例中，当第n存储阵列中的故障存储单元被冗余阵列替换时，第1选择电路输出第1数据，第N选择电路输出第N-1数据，第n选择电路不输出数据，在1＜i＜n的范围内，第i选择电路输出第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n＜m且n为正整数。
结合图18所示，假设发生故障的存储阵列为第1～17存储阵列中的某个存储阵列，比如，为第15存储阵列，即n＝15。在一个示例中，第15存储阵列的故障存储单元所在的列不再存储数据，原本需写入第15存储阵列的第15数据Data_15需写入第16存储阵列，原本需写入第16存储阵列的第16数据Data_16需写入第17存储阵列，原本需写入第17存储阵列的第17数据Data_17需写入第18存储阵列(冗余阵列)，完成故障替换。相应的，第1选择电路输出第1数据Data_1，以第1数据将Data_1写入第1存储阵列；在1＜i＜15的范围内，第i选择电路输出第i数据，即第2～14选择电路分别输出第2数据Data_2～第14数据Data_14，以将第2数据Data_2～第14数据Data_14分别写入第2～14存储阵列；第15选择电路不输出数据，以避免向故障存储单元所在的列写入数据；在15＜i＜35的范围内，第i选择电路输出第i-1数据，即第16～34选择电路分别输出第15数据Data_15～第33数据Data_33，以将第15数据Data_15～第33数据Data_33分别写入第16～34存储阵列；此时第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
在一个示例中，当第k存储阵列中的故障存储单元被冗余阵列替换时，第1选择电路输出第1数据， 第N选择电路输出第N-1数据，第k选择电路不输出数据，在1＜i＜k的范围内，第i选择电路输出第i数据，在k＜i＜N的范围内，第i选择电路输出第i-1数据，m＜k＜N且k为正整数。
结合图19所示，假设发生故障的存储阵列为第19～35存储阵列中的某个存储阵列，比如，为第21存储阵列，即k＝21。在一个示例中，第21存储阵列不再存储数据，原本需写入第21存储阵列的第20数据Data_20需写入第20存储阵列，原本需写入第20存储阵列的第19数据Data_19需写入第19存储阵列，原本需写入第19存储阵列的第18数据Data_18需写入第18存储阵列(冗余阵列)，完成故障替换。相应的，第1选择电路输出第1数据Data_1，以将第1数据Data_1写入第1存储阵列；1＜i＜21的范围内，第i选择电路输出第i数据，即第2～20选择电路分别输出第2数据Data_2～第20数据Data_20，以将第2数据Data_2～第20数据Data_20分别写入第2～20存储阵列；第21选择电路不输出数据，以避免向故障存储阵列所在的列写入数据；在21＜i＜35的范围内，第i选择电路输出第i-1数据，即第22～34选择电路分别输出第21数据Data_21～第33数据Data_33，以将第21数据Data_21～第33数据Data_33分别写入第22～34存储阵列；第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
在一个示例中，当第1存储阵列中的故障存储单元被冗余阵列替换时，第1选择电路不输出第1数据，第N选择电路输出第N-1数据，第i选择电路输出第i-1数据。
结合图20所示，假设发生故障的存储阵列为第1存储阵列。在一个示例中，第1存储阵列中故障的存储单元所在的列不再存储数据，原本需写入第1存储阵列的第1数据Data_1需写入第2存储阵列，原本需写入第2存储阵列的第2数据Data_2需写入第3存储阵列，以此类推，直至原本需写入第17存储阵列的第17数据Data_17需写入第18存储阵列(冗余阵列)，完成故障替换。相应的，第1选择电路不输出第1数据Data_1，以避免向故障存储单元所在的列写入数据；第i选择电路输出第i-1数据，即第2～34选择电路分别输出第1数据Data_1～第33数据Data_33，以将第1数据Data_1～第33数据Data_33分别写入第2～34存储阵列；第35选择电路输出第34数据Data_34，以将第34数据Data_34写入第35存储阵列，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
在一个示例中，当第N存储阵列中的故障存储单元被冗余阵列替换时，第1选择电路输出第1数据，第N选择电路不输出数据，第i选择电路输出第i数据。
结合图21所示，假设发生故障的存储阵列为第35存储阵列。在一个示例中，第35存储阵列故障存储单元所在的列不再存储数据，原本需写入第35存储阵列的第34数据Data_34需写入第34存储阵列，原本需写入第34存储阵列的第33数据Data_33需写入第33存储阵列，以此类推，直至原本需写入第19存储阵列的第18数据Data_18需写入第18存储阵列(冗余阵列)，完成故障替换。相应的，第1选择电路输出第1数据Data_1，以将第1数据Data_1写入第1存储阵列；第i选择电路输出第i数据，即第2～34 选择电路分别输出第2数据Data_2～第34数据Data_34，以将第2数据Data_2～第34数据Data_34写入第2～34存储阵列；第35选择电路不输出第34数据Data_34，以避免向故障存储单元所在的列写入数据，从而使得选择电路输出完整的数据，进而存储阵列能够准确存储选择电路输出的数据，实现数据的准确写入。
上述示例结合冗余阵列的数量为一个的情况，针对冗余阵列设置在不同位置下，未存在和存在故障存储单元的不同情形进行了示例说明，可以理解，通过控制选择电路选择输出相应的数据，能够在不同示例的情形下均可实现数据的准确写入。
此外，在另一个示例中，冗余阵列的数量为多个且所述冗余阵列不相邻。具体的，当设置有多个冗余阵列时，可以支持对多个主存储阵列中位置相同的列同时故障时的替换。举例来说，假设第7存储阵列和第15存储阵列为冗余阵列，则可使用第7存储阵列中的冗余列替换第1存储阵列至第6存储阵列中的故障存储单元所在的列，使用第15存储阵列中的冗余列替换第16存储阵列至第35存储阵列中的故障存储单元所在的列。针对相邻两个冗余阵列之间的主存储阵列，比如，第8存储阵列至第14存储阵列，可以在设计时进行划分，例如，将第8存储阵列至第9存储阵列划分至第7存储阵列负责故障替换，将第10存储阵列至第14存储阵列划分至第15存储阵列负责故障替换。执行故障替换和选择电路的控制机制与前述方案类似。通过设置多个冗余阵列，可以支持多个主存储阵列中位置相同的列同时故障的场景，提高故障修复的可靠性。
本公开实施例提供的存储器，包括依次排列的N个存储阵列，其中包含至少一个主存储阵列和至少一个冗余阵列，冗余阵列用于提供主存储阵列的故障单元替换，以及N个选择电路，每个选择电路接收位序对应的数据以及上一相邻数据，每个选择电路响应于自身的选择信号，通过选择输出相应的信号，实现故障替换场景下的数据处理。本方案的存储器通过设置多个选择电路，根据存储器的故障单元替换情况，控制选择电路输出相应的数据，从而实现故障替换下的数据处理，保证数据处理的准确性和可靠性。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (14)

  1. 一种存储器，包括：
    依次排列的N个存储阵列，所述N个存储阵列分别记为第1存储阵列，第2存储阵列，…，第i存储阵列，…，第N存储阵列，其中至少一个所述存储阵列为冗余阵列，且至少一个所述存储阵列为主存储阵列，所述冗余阵列用于替换所述主存储阵列中的故障存储单元，1＜i＜N，2≤N且i和N为正整数；
    N个选择电路，分别记为第1选择电路，第2选择电路，…，第i选择电路，…，第N选择电路，所述N个选择电路接收N-1组数据，分别记为第1数据，第2数据，…，第i数据，…，第N-1数据；
    其中，所述第1选择电路接收所述第1数据，用于根据第1选择信号向所述第1存储阵列输出或不输出所述第1数据；所述第N选择电路接收所述第N-1数据，用于根据第N选择信号向所述第N存储阵列输出或不输出所述第N-1数据；第i选择电路接收所述第i-1数据和所述第i数据，且所述第i选择电路用于根据第i选择信号向所述第i存储阵列输出所述第i-1数据或所述第i数据。
  2. 根据权利要求1所述的存储器，其中，所述存储阵列和所述冗余阵列均包括M个列，分别记为第1列，第2列，…，第j列，…，第M列，所述冗余阵列的第j列用于替换任意一个所述主存储阵列的第j列，1≤j≤M，且j和M为正整数。
  3. 根据权利要求2所述的存储器，其中，所述选择电路包括：
    多个子选择电路，所述第1选择电路的每一所述子选择电路接收第1数据中的1bit数据，所述第i选择电路的每一所述子选择电路分别接收所述第i-1数据和所述第i数据中的1bit数据，所述第N选择电路的每一所述子选择电路接收第N-1数据中的1bit数据。
  4. 根据权利要求3所述的存储器，其中，所述子选择电路包括数据选择器，所述第1选择电路的所述数据选择器的第一数据输入端接收所述第1数据中的1bit数据，所述第1选择电路的所述数据选择器的选择端接收所述第1选择信号，所述第i选择电路的所述数据选择器的第一数据输入端接收所述第i-1数据中的1bit数据，所述第i选择电路的所述数据选择器的第二数据输入端接收所述第i数据中的1bit数据，所述第i选择电路的所述数据选择器的选择端接收所述第i选择信号，所述第N选择电路的所述数据选择器的第一数据输入端接收所述第N-1数据中的1bit数据，所述第N选择电路的所述数据选择器的选择端接收所述第N选择信号。
  5. 根据权利要求1所述的存储器，其中，所述冗余阵列的数量为一个。
  6. 根据权利要求5所述的存储器，其中，所述第1存储阵列为所述冗余阵列。
  7. 根据权利要求6所述的存储器，其中，当不存在故障存储单元时，所述第1选择电路不输出第1数据，所述第N选择电路输出所述第N-1数据，所述第i选择电路输出所述第i-1数据；
    当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n为正整数；
    当所述第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第i选择电路输出所述第i数据，所述第N选择电路不输出第N-1数据。
  8. 根据权利要求5所述的存储器，其中，所述第N存储阵列为所述冗余阵列。
  9. 根据权利要求8所述的存储器，其中，当不存在故障存储单元时，所述第1选择电路输出所述第1数据，所述第N选择电路不输出第N-1数据，所述第i选择电路输出所述第i数据；
    当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出所述第i-1数据，n为正整数；
    当所述第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路不输出第1数据，所述第i选择电路输出所述第i-1数据，所述第N选择电路输出所述第N-1数据。
  10. 根据权利要求5所述的存储器，其中，第m存储阵列为所述冗余阵列，1＜m＜N且m为正整数。
  11. 根据权利要求10所述的存储器，其中，当不存在故障存储单元时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，且在1＜i＜m的范围内，所述第i选择电路输出所述第i数据，在m＜i＜N的范围内，所述第i选择电路输出所述第i-1数据；
    当第n存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜n的范围内，所述第i选择电路输出所述第i数据，在n＜i＜N的范围内，第i选择电路输出第i-1数据，n＜m且n为正整数；
    当第k存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路输出所述第N-1数据，在1＜i＜k的范围内，所述第i选择电路输出所述第i数据，在k＜i＜N的范围内，第i选择电路输出第i-1数据，m＜k＜N且k为正整数；
    当第1存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路不输出第1数据，所述第N选择电路输出所述第N-1数据，所述第i选择电路输出所述第i-1数据；
    当第N存储阵列中的故障存储单元被所述冗余阵列替换时，所述第1选择电路输出所述第1数据，所述第N选择电路不输出第N-1数据，所述第i选择电路输出所述第i数据。
  12. 根据权利要求1所述的存储器，其中，所述冗余阵列的数量为多个且所述冗余阵列不相邻。
  13. 根据权利要求1-12任一项所述的存储器，其中，至少一个所述主存储阵列为校验码存储阵列，所述校验码存储阵列用于存储校验码数据。
  14. 根据权利要求13所述的存储器，其中，所述存储器还包括：校验模块；
    所述校验模块与所述N个选择电路连接，所述N个选择电路接收的数据包括待写入数据和校验码数据，所述校验模块用于根据所述待写入数据，生成所述校验码数据。
PCT/CN2023/076133 2022-11-02 2023-02-15 存储器 Ceased WO2024093045A1 (zh)

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