WO2024088320A1 - 一种驱动电路以及显示装置 - Google Patents

一种驱动电路以及显示装置 Download PDF

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Publication number
WO2024088320A1
WO2024088320A1 PCT/CN2023/126581 CN2023126581W WO2024088320A1 WO 2024088320 A1 WO2024088320 A1 WO 2024088320A1 CN 2023126581 W CN2023126581 W CN 2023126581W WO 2024088320 A1 WO2024088320 A1 WO 2024088320A1
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WIPO (PCT)
Prior art keywords
signal
data recovery
recovery unit
bandwidth
clock data
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PCT/CN2023/126581
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English (en)
French (fr)
Inventor
林坤和
何长安
王建国
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摩星半导体(广东)有限公司
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Publication of WO2024088320A1 publication Critical patent/WO2024088320A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, and in particular to a driving circuit and a display device.
  • Display devices generally include a motherboard, a timing controller (TCON) board, a drive circuit, and a display panel.
  • the drive circuit is integrated into the display panel.
  • the drive circuit is divided into a gate drive circuit and a source drive circuit.
  • the motherboard inputs the display data to the timing control board
  • the timing control board converts the display data, and then inputs the signal related to the gate drive to the gate drive circuit, and the signal related to the source drive to the source drive circuit.
  • the gate drive circuit outputs the gate drive signal
  • the source drive circuit outputs the source signal to drive the display panel.
  • the driving circuit is easily affected by signal interference.
  • the processing of internal data signals will be affected, thereby affecting the display effect of the display device.
  • the embodiments of the present application provide a driving circuit and a display device, which are intended to improve/solve the problem in the related art that the driving circuit is affected by signal interference and thus affects the display effect.
  • the present application provides a driving circuit, which includes: a clock data recovery unit, used to receive a first signal sent by a timing control circuit; an output unit, connected to the clock data recovery unit, and used to output a second signal; wherein the clock data recovery unit is configured to adjust the bandwidth of the clock data recovery unit according to the second signal.
  • the clock-data recovery unit is configured to adjust a bandwidth of the clock-data recovery unit when the second signal generates signal interference to the clock-data recovery unit.
  • the clock-data recovery unit is configured to adjust the bandwidth of the clock-data recovery unit in a signal conversion interval of the second signal; the signal conversion interval is a level conversion time interval of the second signal.
  • the clock data recovery unit is configured to adjust the bandwidth of the clock data recovery unit from a first bandwidth to a second bandwidth at the beginning of a signal conversion interval of the second signal, and to adjust the bandwidth of the clock data recovery unit from the second bandwidth to the first bandwidth at the end of the signal conversion interval of the second signal; wherein the second bandwidth is greater than the first bandwidth.
  • the clock data recovery unit includes: a first frequency divider, wherein the input end of the first frequency divider is used to input the first signal; a frequency detector, wherein the first input end of the frequency detector is connected to the output end of the first frequency divider; a charge pump, wherein the input end of the charge pump is connected to the output end of the frequency detector; a filter, wherein the input end of the filter is connected to the output end of the charge pump; a voltage-controlled oscillator, wherein the input end of the voltage-controlled oscillator is connected to the output end of the filter; and a second frequency divider, wherein the input end of the second frequency divider is connected to the output end of the voltage-controlled oscillator, and the output end of the second frequency divider is connected to the second input end of the frequency detector.
  • the charge pump is configured to adjust an output current of the charge pump according to the second signal to adjust a bandwidth of the clock data recovery unit.
  • the filter includes: a resistor, a first end of the resistor is connected to the output end of the charge pump; a first capacitor, a first end of the first capacitor is connected to the second end of the resistor, and the second end of the first capacitor is grounded; a second capacitor, a first end of the second capacitor is connected to the output end of the charge pump, and the second end of the second capacitor is grounded.
  • the resistor is configured to adjust a resistance value of the resistor according to the second signal to adjust a bandwidth of the clock data recovery unit.
  • the first capacitor is configured to adjust a capacitance value of the first capacitor according to the second signal to adjust a bandwidth of the clock data recovery unit.
  • the present application also provides a display device, which includes a driving circuit, and the driving circuit is the driving circuit as described above.
  • the driving circuit provided in the embodiment of the present application includes: a clock data recovery unit, which is used to receive a first signal sent by a timing control circuit; an output unit, which is connected to the clock data recovery unit, and the output unit is used to output a second signal; wherein the clock data recovery unit is configured to adjust the bandwidth of the clock data recovery unit according to the second signal.
  • the above manner adjusts the bandwidth of the clock data recovery unit according to the second signal, and can reduce the influence of the interference signal on the clock data recovery unit by adjusting the bandwidth when the second signal interferes, thereby ensuring the working performance of the clock data recovery unit, and further ensuring the normal display screen of the display device.
  • FIG1 is a schematic structural diagram of an embodiment of a display device provided by the present application.
  • FIG2 is a schematic diagram of the structure of the TCON board and the driving circuit in FIG1 ;
  • FIG3 is a schematic structural diagram of an embodiment of a driving circuit provided by the present application.
  • FIG4 is a schematic diagram showing the relationship between CDR bandwidth and interference signal
  • FIG5 is a schematic diagram of a bandwidth of a second signal and a clock data recovery unit provided by the present application
  • FIG6 is a schematic structural diagram of an embodiment of a clock data recovery unit in FIG3 ;
  • FIG7 is a schematic diagram of the structure of the charge pump and filter in FIG6 ;
  • FIG. 8 is a schematic structural diagram of another embodiment of a driving circuit provided in the present application.
  • first and second are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise clearly and specifically defined.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • FIG. 1 is a schematic structural diagram of an embodiment of a display device provided in the present application.
  • the display device 100 includes a main board 10 , a TCON board 20 , a driving circuit 30 and a display panel 40 .
  • the driving circuit 30 can be integrated into the display panel 40 or independent of the display panel 40.
  • the driving circuit 30 includes a gate driving circuit 31 and a source driving circuit 32 (the number of the gate driving circuit 31 and the source driving circuit 32 can be multiple), and the display panel 40 includes a TFT (Thin Film Transistor) array 41.
  • TFT Thin Film Transistor
  • FIG. 2 is a schematic diagram of the structure of the TCON board and the driving circuit in FIG. 1 .
  • the TCON board 20 includes a power supply circuit 21 , a Gamma circuit 22 and a timing control circuit 23 .
  • the power supply circuit 21 is used to provide power supply voltage to the Gamma circuit 22 and the timing control circuit 23. In addition, the power supply circuit 21 also provides power supply voltage to the gate drive circuit 31, the source drive circuit 32, the TFT array 41, the common electrode (not shown), etc.
  • the Gamma circuit 22 is used to provide a Gamma signal for the source driving circuit 32 , and the timing control circuit 23 provides a signal required for gate driving for the gate driving circuit 31 and provides a signal required for source driving for the source driving circuit 32 .
  • the input signals of the timing control circuit 23 include:
  • the signal input from the timing control circuit 23 to the gate drive circuit 31 includes:
  • STV start vertical
  • start vertical is the column start signal and also the start signal of a frame.
  • the signals input from the timing control circuit 23 to the source driving circuit 32 include:
  • mini-LVDS mini-LVDS Low Voltage Differential Signaling
  • the timing control circuit 23 converts the LVDS signal into a mini-LVDS or RSDS signal according to the requirements.
  • the display device 100 provided in this embodiment is mainly a liquid crystal display, and the display panel of the liquid crystal display may also include an array substrate (including a TFT array), a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate.
  • the timing control circuit and the drive circuit are introduced separately below.
  • FIG. 3 is a schematic diagram of the structure of an embodiment of a driving circuit provided in the present application.
  • the driving circuit in this embodiment is mainly a source driving circuit 32 , and the source driving circuit 32 includes a clock data recovery unit 321 and an output unit 322 .
  • the clock data recovery unit 321 is used to receive the first signal D1 (data signal data) sent by the timing control circuit 23; the output unit 322 is connected to the clock data recovery unit 321, and the output unit 322 is used to output the second signal D2; wherein the clock data recovery unit 321 is configured to adjust the bandwidth of the clock data recovery unit 321 according to the second signal D2.
  • the bandwidth of the clock data recovery unit 321 is adjusted, mainly the loop bandwidth of the filter loop therein is adjusted.
  • the second signal D2 here is a data signal input to any one of the multiple data lines (data lines) in the TFT array 41.
  • the source driver circuit 32 outputs, a large current may be generated, which will interfere with the source driver circuit 32, especially the CDR (clock data recovery) unit.
  • the CDR unit can parse the clock and data from the first signal D1 provided by the timing control circuit 23.
  • the CDR circuit in the source driver circuit 32 can correctly lock the first signal D1 provided by the timing control circuit 23 .
  • the CDR unit in the source driver circuit 32 may not be able to correctly lock the first signal D1 provided by the timing control circuit 23.
  • the source driver circuit 32 cannot correctly lock the first signal D1, the display panel 40 of the display device 100 cannot display a correct image.
  • the source driving circuit 32 adjusts the bandwidth of the clock data recovery unit 321 according to the second signal D2 .
  • the source driving circuit 32 determines the timing when the second signal D2 interferes with the clock data recovery unit 321 according to the second signal D2, and adjusts the bandwidth of the clock data recovery unit 321 based on the timing when the second signal D2 interferes. For example, when the output current of the second signal D2 is too large, the interference generated by the clock data recovery unit 321 is particularly obvious, then the current detection of the second signal D2 can be performed, and when the current of the second signal D2 is too large, the bandwidth of the clock data recovery unit 321 is adjusted.
  • the present embodiment mainly analyzes the timing when the second signal D2 interferes with the CDR circuit, so that the source driver circuit 32 adjusts the bandwidth of the clock data recovery unit 321 according to the second signal D2.
  • FIG4 which is a schematic diagram of the relationship between the CDR bandwidth and the interference signal
  • the performance of the clock data recovery unit 321 is determined by three indicators: circuit jitter generation, jitter transmission, and jitter tolerance, and these indicators are determined by the bandwidth of the clock data recovery unit 321.
  • the clock data recovery unit 321 is configured to increase the bandwidth of the clock data recovery unit 321 according to the second signal when the second signal interferes with the clock data recovery unit 321, thereby increasing the anti-interference capability of the clock data recovery unit 321.
  • the driving circuit provided in this embodiment includes: a clock data recovery unit, which is used to receive a first signal sent by a timing control circuit; an output unit, which is connected to the clock data recovery unit, and the output unit is used to output a second signal; wherein the clock data recovery unit is configured to adjust the bandwidth of the clock data recovery unit according to the second signal.
  • the above manner since the second signal will interfere with the clock data recovery unit when it is output, affecting the performance of the clock data recovery unit, the above manner adjusts the bandwidth of the clock data recovery unit according to the second signal, and can reduce the influence of the interference signal on the clock data recovery unit by adjusting the bandwidth when the second signal interferes, thereby ensuring the working performance of the clock data recovery unit and further ensuring the normal display screen of the display device.
  • the clock-data recovery unit 321 is configured to adjust the bandwidth of the clock-data recovery unit 321 when the second signal D2 generates signal interference to the clock-data recovery unit 321 .
  • the current value of the second signal D2 can be detected and compared with the reference current in real time.
  • the detected current value is greater than the reference current, it is determined that the noise generated by the second signal D2 is large and the interference to the clock data recovery unit 321 is also large.
  • the bandwidth of the clock data recovery unit 321 is adjusted to reduce the interference of noise.
  • the clock data recovery unit 321 is configured to adjust the bandwidth (bandwith, BW) of the clock data recovery unit 321 in the signal conversion interval of the second signal D2; the signal conversion interval is the level conversion time interval of the second signal D2, that is, the time interval from low level to high level, or the time interval from high level to low level.
  • the clock data recovery unit 321 is configured to adjust the bandwidth of the clock data recovery unit 321 from the first bandwidth to the second bandwidth at the beginning of the signal conversion interval of the second signal D2, and to adjust the bandwidth of the clock data recovery unit from the second bandwidth to the first bandwidth at the end of the signal conversion interval of the second signal; wherein the second bandwidth is greater than the first bandwidth.
  • the first bandwidth is the bandwidth under normal conditions, and the second bandwidth can be set based on experience. For example, a bandwidth change curve can be established in the signal conversion interval of the second signal D2, and the bandwidth adjustment range can be adjusted according to the change situation.
  • the clock data recovery unit 321 includes a first frequency divider 3211, a frequency detector 3212, a charge pump 3213, a filter 3214, a voltage controlled oscillator (VCO) 3215 and a second frequency divider 3216.
  • VCO voltage controlled oscillator
  • the input end of the first frequency divider 3211 is used to input the first signal D1; the first input end of the frequency detector 3212 is connected to the output end of the first frequency divider 3211; the input end of the charge pump 3213 is connected to the output end of the frequency detector 3212; the input end of the filter 3214 is connected to the output end of the charge pump 3213; the input end of the voltage-controlled oscillator 3215 is connected to the output end of the filter 3214; the input end of the second frequency divider 3216 is connected to the output end of the voltage-controlled oscillator 3215, and the output end of the second frequency divider 3216 is connected to the second input end of the frequency detector 3212.
  • the first frequency divider 3211 is used to divide the input first signal D1 to obtain a reference clock signal CKref which is input to the first input end of the frequency detector 3212.
  • the frequency detector 3212, the charge pump 3213, the filter 3214, the voltage-controlled oscillator 3215 and the second frequency divider 3216 constitute a phase-locked loop, and the feedback clock signal CKfb is input to the second input end of the frequency detector 3212.
  • the frequency difference (or phase difference) is integrated by the filter 3214, and the output frequency of the voltage-controlled oscillator 3215 is controlled in the form of voltage.
  • the voltage-controlled oscillator 3215 is a device that controls the frequency output by voltage. In essence, this process is a voltage feedback loop:
  • the charge pump 3213 is configured to adjust the output current of the charge pump 3213 according to the second signal D2 , so as to adjust the bandwidth of the clock data recovery unit 321 .
  • the change in the output current of the charge pump 3213 causes the change in the bandwidth of the clock data recovery unit 321 .
  • the change in the bandwidth of the clock data recovery unit 321 can improve the signal interference of the second signal D2 on the clock data recovery unit 321 .
  • the charge pump 3213 is configured to adjust the current value of the output current from a first current value to a second current value at the beginning of the signal conversion interval of the second signal D2, and to adjust the current value of the output current from the second current value to the first current value at the end of the signal conversion interval of the second signal D2; wherein the second current value is greater than the first current value, and the first current value is the output current under normal circumstances.
  • the filter 3214 includes a resistor R, a first capacitor C1 and a second capacitor C2.
  • the first end of the resistor R is connected to the output end of the charge pump 3213; the first end of the first capacitor C1 is connected to the second end of the resistor R, and the second end of the first capacitor C1 is grounded GND; the first end of the second capacitor C2 is connected to the output end of the charge pump 3213, and the second end of the second capacitor C2 is grounded.
  • the resistor R is configured to adjust the resistance value of the resistor R according to the second signal D2 to adjust the bandwidth of the clock data recovery unit 321 .
  • the change in the resistance value of the resistor R causes the change in the bandwidth of the clock data recovery unit 321 .
  • the change in the bandwidth of the clock data recovery unit 321 improves the signal interference of the second signal D2 on the clock data recovery unit 321 .
  • the resistor R is configured to adjust the resistance value of the resistor R from a first resistance value to a second resistance value at the beginning of the signal conversion interval of the second signal D2, and to adjust the resistance value of the resistor R from the second resistance value to the first resistance value at the end of the signal conversion interval of the second signal D2; wherein the second resistance value is greater than the first resistance value, and the first resistance value is the resistance value under normal circumstances.
  • the resistor R can be an adjustable resistor, and its resistance value can be adjusted by a controller.
  • the first capacitor C1 is configured to adjust the capacitance value of the first capacitor C1 according to the second signal D2 to adjust the bandwidth of the clock data recovery unit 321 .
  • the change in the capacitance of the first capacitor C1 causes the change in the bandwidth of the clock data recovery unit 321 .
  • the change in the bandwidth of the clock data recovery unit 321 can improve the signal interference of the second signal D2 on the clock data recovery unit 321 .
  • the first capacitor C1 is configured to adjust the capacitance value of the first capacitor C1 from the first capacitance value to the second capacitance value at the beginning of the signal conversion interval of the second signal D2, and to adjust the capacitance value of the first capacitor C1 from the second capacitance value to the first capacitance value at the end of the signal conversion interval of the second signal D2; wherein the second capacitance value is less than the first capacitance value, and the first capacitance value is the capacitance value under normal circumstances.
  • the first capacitor C1 can be an adjustable capacitor, and its capacitance value can be adjusted by a controller.
  • the driving circuit in this embodiment is mainly a source driving circuit 32, and the source driving circuit 32 includes a clock data recovery unit 321, an output unit 322 and a control unit 323.
  • the clock data recovery unit 321 is used to receive the first signal D1 (data signal data) sent by the timing control circuit 23; the output unit 322 is connected to the clock data recovery unit 321, and the output unit 322 is used to output the second signal D2; the control unit 323 is connected to the clock data recovery unit 321 and the output unit 322, and is configured to adjust the bandwidth of the clock data recovery unit 321 according to the second signal D2.
  • control unit 323 may adjust the bandwidth of the clock data recovery unit 321 in the following manner:
  • the resistance value of the resistor R in the filter 3214 in the clock data recovery unit 321 is increased.
  • the capacitance value of the first capacitor C1 in the filter 3214 in the clock data recovery unit 321 is adjusted to be small.
  • control unit 323 may be a MCU (microprocessor).
  • the driving circuit provided in this embodiment includes: a clock data recovery unit, which is used to receive a first signal sent by a timing control circuit; an output unit, which is connected to the clock data recovery unit, and the output unit is used to output a second signal; wherein the clock data recovery unit is configured to adjust the bandwidth of the clock data recovery unit according to the second signal.
  • the bandwidth of the clock data recovery unit is adjusted by adjusting the output current of the charge pump in the CDR, the resistance in the filter circuit, the capacitor in the filter circuit, etc., so that when the second signal generates interference, the influence of the interference signal on the clock data recovery unit can be reduced by adjusting the bandwidth, thereby ensuring the working performance of the clock data recovery unit, and further ensuring the normal display screen of the display device.

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Abstract

一种驱动电路（30）以及显示装置（100），驱动电路（30）包括：时钟数据恢复单元（321），用于接收时序控制电路（23）发送的第一信号（D1）；输出单元（322），连接时钟数据恢复单元（321），输出单元（322）用于输出第二信号（D2）；时钟数据恢复单元（321）被配置为根据第二信号（D2），对时钟数据恢复单元（321）的带宽进行调节。可以减小第二信号（D2）对时钟数据恢复单元（321）的噪声影响。

Description

一种驱动电路以及显示装置
本申请要求于2022年10月25日提交中国专利局、申请号为202211312954.7、申请名称为“一种驱动电路以及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种驱动电路以及显示装置。
背景技术
显示装置一般包括主板、时序控制(timing controller，TCON)板、驱动电路和显示面板，有的显示装置驱动电路集成于显示面板中。驱动电路分为栅极驱动电路和源极驱动电路，当主板把显示数据输入至时序控制板后，时序控制板会对显示数据进行转化处理，然后将跟栅极驱动相关的信号输入至栅极驱动电路，将跟源极驱动相关的信号输入至源极驱动电路。栅极驱动电路输出栅极驱动信号、源极驱动电路输出源极信号以对显示面板进行驱动。
技术问题
驱动电路很容易受到信号干扰，在驱动电路受到信号干扰时，内部数据信号的处理会受到影响，从而影响显示装置的显示效果。
技术解决方案
本申请实施例提供一种驱动电路以及显示装置，用意改善/解决相关技术中驱动电路受到信号干扰而影响显示效果的问题。
本申请提供一种驱动电路，该驱动电路包括：时钟数据恢复单元，用于接收时序控制电路发送的第一信号；输出单元，连接时钟数据恢复单元，输出单元用于输出第二信号；其中，时钟数据恢复单元被配置为根据第二信号，对时钟数据恢复单元的带宽进行调节。
在一些实施例中，时钟数据恢复单元被配置为在第二信号对时钟数据恢复单元产生信号干扰时，对时钟数据恢复单元的带宽进行调节。
在一些实施例中，时钟数据恢复单元被配置为在第二信号的信号转换区间，对时钟数据恢复单元的带宽进行调节；信号转换区间为第二信号的电平转换时间区间。
在一些实施例中，时钟数据恢复单元被配置为在第二信号的信号转换区间开始时，将时钟数据恢复单元的带宽从第一带宽调节至第二带宽，以及在第二信号的信号转换区间结束时，将时钟数据恢复单元的带宽从第二带宽调节至第一带宽；其中，第二带宽大于第一带宽。
在一些实施例中，时钟数据恢复单元包括：第一分频器，第一分频器的输入端用于输入第一信号；鉴频鉴相器，鉴频鉴相器的第一输入端连接第一分频器的输出端；电荷泵，电荷泵的输入端连接鉴频鉴相器的输出端；滤波器，滤波器的输入端连接电荷泵的输出端；压控振荡器，压控振荡器的输入端连接滤波器的输出端；第二分频器，第二分频器的输入端连接压控振荡器的输出端，第二分频器的输出端连接鉴频鉴相器的第二输入端。
在一些实施例中，电荷泵被配置为根据第二信号，对电荷泵的输出电流进行调节，以对时钟数据恢复单元的带宽进行调节。
在一些实施例中，滤波器包括：电阻，电阻的第一端连接电荷泵的输出端；第一电容，第一电容的第一端连接电阻的第二端，第一电容的第二端接地；第二电容，第二电容的第一端连接电荷泵的输出端，第二电容的第二端接地。
在一些实施例中，电阻被配置为根据第二信号，对电阻的电阻值进行调节，以对时钟数据恢复单元的带宽进行调节。
在一些实施例中，第一电容被配置为根据第二信号，对第一电容的电容值进行调节，以对时钟数据恢复单元的带宽进行调节。
本申请还提供一种显示装置，该显示装置包括驱动电路，该驱动电路是如上述的驱动电路。
有益效果
本申请实施例提供的驱动电路包括：时钟数据恢复单元，用于接收时序控制电路发送的第一信号；输出单元，连接时钟数据恢复单元，输出单元用于输出第二信号；其中，时钟数据恢复单元被配置为根据第二信号，对时钟数据恢复单元的带宽进行调节。通过上述方式，由于第二信号来输出时会对时钟数据恢复单元产生干扰，影响时钟数据恢复单元的性能，上述方式通过根据第二信号来对时钟数据恢复单元的带宽进行调节，能够在第二信号产生干扰时，通过调节带宽来减少干扰信号对时钟数据恢复单元的影响，从而保证了时钟数据恢复单元的工作性能，也进一步保证了显示装置的显示画面的正常。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的显示装置一实施例的结构示意图；
图2是图1中TCON板和驱动电路的结构示意图；
图3是本申请提供的驱动电路一实施例的结构示意图；
图4是CDR带宽与干扰信号的关系示意图；
图5是本申请提供的第二信号和时钟数据恢复单元的带宽的示意图；
图6是图3中时钟数据恢复单元一实施例的结构示意图；
图7是图6中电荷泵和滤波器的结构示意图；
图8是本申请提供的驱动电路另一实施例的结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本申请中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
参阅图1，图1是本申请提供的显示装置一实施例的结构示意图，该显示装置100包括主板10、TCON板20、驱动电路30和显示面板40。
其中，驱动电路30可以集成于显示面板40中，也可以独立于显示面板40，驱动电路30包括栅极驱动电路31和源极驱动电路32(栅极驱动电路31和源极驱动电路32的数量可以为多个)，显示面板40包括TFT(Thin Film Transistor，薄膜场效应晶体管)阵列41。
具体地，如图2所示，图2是图1中TCON板和驱动电路的结构示意图，该TCON板20上包括电源电路21、Gamma电路22和时序控制电路23。
其中，电源电路21用于对Gamma电路22和时序控制电路23提供电源电压，另外，电源电路21还对栅极驱动电路31、源极驱动电路32、TFT阵列41、公共电极(图未示)等提供电源电压。
其中，Gamma电路22用于为源极驱动电路32提供Gamma信号，时序控制电路23为栅极驱动电路31提供栅极驱动需要的信号，为源极驱动电路32提供源极驱动需要的信号。
具体如下：
时序控制电路23的输入信号包括：
LVDS，Low Voltage Differential Signaling，低电压差分信号。
Data，数据信号。
时序控制电路23输入至栅极驱动电路31的信号包括：
STV，start vertical，列开始信号，同样也是一帧的开始信号。
CPV/CKV，clock pulse vertical，列时钟信号。
时序控制电路23输入至源极驱动电路32的信号包括：
STH，start horizontal，行开始的信号。
CPH/CKH，clock pulse horizontal，行的时钟信号。
mini-LVDS，mini-LVDS Low Voltage Differential Signaling；或
RSDS，reduced swing differential signal，低摆幅差分信号。
Data，数据信号。
其中，时序控制电路23根据需求将LVDS信号转化为mini-LVDS或者RSDS信号。
本实施例提供的显示装置100主要为液晶显示器，液晶显示器的显示面板还可以包括阵列基板(包括TFT阵列)、彩膜基板以及阵列基板和彩膜基板之间的液晶层。下面再对时序控制电路和驱动电路分别进行介绍。
参阅图3，图3是本申请提供的驱动电路一实施例的结构示意图，本实施例中的驱动电路主要是源极驱动电路32，该源极驱动电路32包括时钟数据恢复单元321和输出单元322。
其中，时钟数据恢复单元321用于接收时序控制电路23发送的第一信号D1(数据信号data)；输出单元322连接时钟数据恢复单元321，输出单元322用于输出第二信号D2；其中，时钟数据恢复单元321被配置为根据第二信号D2，对时钟数据恢复单元321的带宽进行调节。
可选地，对时钟数据恢复单元321的带宽进行调节，主要是对其中的滤波回路的回路带宽进行调节。
可以理解地，这里的第二信号D2为输入至TFT阵列41中的多个数据线(data line)中任意一条数据线的数据信号。其中，在源极驱动电路32进行输出时，有可能会产生较大的电流，较大的电流会对源极驱动电路32产生干扰，特别是对其中的CDR(clock data recovery，时钟数据恢复)单元产生干扰。CDR单元可以从时序控制电路23所提供的第一信号D1解析出时钟以及数据。
在第二信号D2未对其产生干扰时，或者第二信号D2未尚不足以对其产生干扰时，源极驱动电路32内部的CDR电路可以正确锁定(lock)时序控制电路23所提供的第一信号D1。
在第二信号D2对其产生干扰时，源极驱动电路32内部的CDR单元可能无法正确锁定时序控制电路23所提供的第一信号D1。当源极驱动电路32无法正确锁定第一信号D1时，显示装置100的显示面板40无法显示正确图像。
因此，在本实施例中，在源极驱动电路32内部的CDR单元受到信号干扰时，源极驱动电路32根据第二信号D2，对时钟数据恢复单元321的带宽进行调节。
在一可选的实施例中，源极驱动电路32根据第二信号D2来确定第二信号D2对时钟数据恢复单元321产生干扰的时机，并基于第二信号D2产生干扰的时机，对时钟数据恢复单元321的带宽进行调节。比如，第二信号D2在输出电流过大时，对时钟数据恢复单元321产生的干扰特别明显，则可以对第二信号D2进行电流检测，在第二信号D2的电流过大时，对时钟数据恢复单元321的带宽进行调节。
可以理解地，由于源极驱动电路32内部的CDR电路受到的信号干扰主要来源于第二信号D2，所以本实施例中主要是分析第二信号D2对CDR电路产生干扰的时机，以使源极驱动电路32根据第二信号D2，对时钟数据恢复单元321的带宽进行调节。
进一步，如图4所示，图4是CDR带宽与干扰信号的关系示意图，时钟数据恢复单元321的性能由电路抖动产生、抖动传输以及抖动容忍三个指标决定，而这些指标与时钟数据恢复单元321的带宽决定。经过多次实验发现，其噪声幅度越大，时钟数据恢复单元321的带宽越小，反之，其噪声幅度越小，时钟数据恢复单元321的带宽则越大。
因此，在一实施例中，时钟数据恢复单元321被配置为根据第二信号，在第二信号对时钟数据恢复单元321产生干扰时，增大时钟数据恢复单元321的带宽，从而增大时钟数据恢复单元321的抗干扰能力。
本实施例提供的驱动电路包括：时钟数据恢复单元，用于接收时序控制电路发送的第一信号；输出单元，连接时钟数据恢复单元，输出单元用于输出第二信号；其中，时钟数据恢复单元被配置为根据第二信号，对时钟数据恢复单元的带宽进行调节。通过上述方式，由于第二信号来输出时会对时钟数据恢复单元产生干扰，影响时钟数据恢复单元的性能，上述方式通过根据第二信号来对时钟数据恢复单元的带宽进行调节，能够在第二信号产生干扰时，通过调节带宽来减少干扰信号对时钟数据恢复单元的影响，从而保证了时钟数据恢复单元的工作性能，也进一步保证了显示装置的显示画面的正常。
可选地，在一实施例中，时钟数据恢复单元321被配置为在第二信号D2对时钟数据恢复单元321产生信号干扰时，对时钟数据恢复单元321的带宽进行调节。
其中，第二信号D2对时钟数据恢复单元321产生信号干扰时可以通过以下具体方式来进行检测：
例如，可以通过检测第二信号D2的电流值，并实时将检测的电流值与参考电流进行比较，当检测的电流值大于该参考电流时，认定为第二信号D2产生的噪声较大，对时钟数据恢复单元321产生的干扰也较大，此时，通过对时钟数据恢复单元321的带宽进行调节，来减少噪声对其干扰。
例如，可以通过检测第二信号D2的信号转换区间来确定，如图5所示，图5是本申请提供的第二信号和时钟数据恢复单元的带宽的示意图，时钟数据恢复单元321被配置为在第二信号D2的信号转换区间，对时钟数据恢复单元321的带宽(bandwith，BW)进行调节；信号转换区间为第二信号D2的电平转换时间区间，即由低电平转换为高电平的时间区间，或者由高电平转换为低电平的时间区间。
可以理解地，在第二信号D2的时钟变换区间(transition)会产生较大的电流，造成接地噪声(ground bounce noise)，接地噪声会对源极驱动电路32中的CDR电路产生影响。
因此，在本实施例中，时钟数据恢复单元321被配置为在第二信号D2的信号转换区间开始时，将时钟数据恢复单元321的带宽从第一带宽调节至第二带宽，以及在第二信号的信号转换区间结束时，将时钟数据恢复单元的带宽从第二带宽调节至第一带宽；其中，第二带宽大于第一带宽。
其中，第一带宽为正常情况下的带宽，而第二带宽可以根据经验来设定。例如，可以建立在第二信号D2的信号转换区间，带宽的变化曲线，再根据变化情况来调节带宽的调节幅度。
参阅图6，图6是图3中时钟数据恢复单元一实施例的结构示意图，该时钟数据恢复单元321包括第一分频器3211、鉴频鉴相器3212、电荷泵3213、滤波器3214、压控振荡器(VCO)3215和第二分频器3216。
其中，第一分频器3211的输入端用于输入第一信号D1；鉴频鉴相器3212的第一输入端连接第一分频器3211的输出端；电荷泵3213的输入端连接鉴频鉴相器3212的输出端；滤波器3214的输入端连接电荷泵3213的输出端；压控振荡器3215的输入端连接滤波器3214的输出端；第二分频器3216的输入端连接压控振荡器3215的输出端，第二分频器3216的输出端连接鉴频鉴相器3212的第二输入端。
其中，第一分频器3211用于对输入的第一信号D1进行分频，得到一个参考时钟信号CKref输入至鉴频鉴相器3212的第一输入端，鉴频鉴相器3212、电荷泵3213、滤波器3214、压控振荡器3215和第二分频器3216构成一个锁相环，反馈的时钟信号CKfb输入至鉴频鉴相器3212的第二输入端。
具体地，经过鉴频鉴相器3212以后，频差(或者相差)再经过滤波器3214的积分，就以电压的形式控制压控振荡器3215的输出频率。压控振荡器3215是一个电压控制频率输出的器件。实质上这个过程就是一个电压反馈回路：
1)当时钟信号CKfb频率低于参考时钟CKref频率时，电压越来越大(PWM占空比增大，高电平占比增多)，VCO输出频率提高，时钟加快；
2)当时钟信号CKfb频率高于参考时钟CKref频率时，电压越来越小(PWM占空比减小，低电平占比增多)，VCO输出频率减小，时钟减慢；
通过以上两个过程，实现动态平衡，最终VCO输出的频率锁定(等于)参考信号CKref的频率。
在本实施例中中，电荷泵3213被配置为根据第二信号D2，对电荷泵3213的输出电流进行调节，以对时钟数据恢复单元321的带宽进行调节。
其中，电荷泵3213的输出电流的变化导致时钟数据恢复单元321的带宽的变化，再结合上述图4的关系，时钟数据恢复单元321的带宽的变化会改善第二信号D2对时钟数据恢复单元321的信号干扰。
具体地，电荷泵3213被配置为在第二信号D2的信号转换区间开始时，将输出电流的电流值从第一电流值调节至第二电流值，以及在第二信号D2的信号转换区间结束时，将输出电流的电流值从第二电流值调节至第一电流值；其中，第二电流值大于第一电流值，第一电流值为正常情况下的输出电流。
参阅图7，图7是图6中电荷泵和滤波器的结构示意图，滤波器3214包括电阻R、第一电容C1和第二电容C2，电阻R的第一端连接电荷泵3213的输出端；第一电容C1的第一端连接电阻R的第二端，第一电容C1的第二端接地GND；第二电容C2的第一端连接电荷泵3213的输出端，第二电容C2的第二端接地。
在一可选的实施例中，电阻R被配置为根据第二信号D2，对电阻R的电阻值进行调节，以对时钟数据恢复单元321的带宽进行调节。
其中，电阻R的电阻值的变化导致时钟数据恢复单元321的带宽的变化，再结合上述图4的关系，时钟数据恢复单元321的带宽的变化会改善第二信号D2对时钟数据恢复单元321的信号干扰。
具体地，电阻R被配置为在第二信号D2的信号转换区间开始时，将电阻R的电阻值从第一电阻值调节至第二电阻值，以及在第二信号D2的信号转换区间结束时，将电阻R的电阻值从第二电阻值调节至第一电阻值；其中，第二电阻值大于第一电阻值，第一电阻值为正常情况下的电阻值。
可以理解地，电阻R可以是可调电阻，具体可以通过一控制器来对其的电阻值进行调节。
在一可选的实施例中，第一电容C1被配置为根据第二信号D2，对第一电容C1的电容值进行调节，以对时钟数据恢复单元321的带宽进行调节。
其中，第一电容C1的电容值的变化导致时钟数据恢复单元321的带宽的变化，再结合上述图4的关系，时钟数据恢复单元321的带宽的变化会改善第二信号D2对时钟数据恢复单元321的信号干扰。
具体地，第一电容C1被配置为在第二信号D2的信号转换区间开始时，将第一电容C1的电容值从第一电容值调节至第二电容值，以及在第二信号D2的信号转换区间结束时，将第一电容C1的电容值从第二电容值调节至第一电容值；其中，第二电容值小于第一电容值，第一电容值为正常情况下的电容值。
可以理解地，第一电容C1可以是可调电容，具体可以通过一控制器来对其的电容值进行调节。
参阅图8，图8是本申请提供的驱动电路另一实施例的结构示意图，本实施例中的驱动电路主要是源极驱动电路32，该源极驱动电路32包括时钟数据恢复单元321、输出单元322和控制单元323。
其中，时钟数据恢复单元321用于接收时序控制电路23发送的第一信号D1(数据信号data)；输出单元322连接时钟数据恢复单元321，输出单元322用于输出第二信号D2；控制单元323连接时钟数据恢复单元321和输出单元322，被配置为根据第二信号D2，对时钟数据恢复单元321的带宽进行调节。
结合上述图6和图7实施例，控制单元323对时钟数据恢复单元321的带宽进行调节方式可以包括：
在第二信号D2的信号转换区间，调大时钟数据恢复单元321中电荷泵3213的输出电 流。
在第二信号D2的信号转换区间，调大时钟数据恢复单元321中滤波器3214中电阻R的电阻值。
在第二信号D2的信号转换区间，调小时钟数据恢复单元321中滤波器3214中第一电容C1的电容值。
可选地，该控制单元323可以是MCU(微处理器)。
本实施例提供的驱动电路包括：时钟数据恢复单元，用于接收时序控制电路发送的第一信号；输出单元，连接时钟数据恢复单元，输出单元用于输出第二信号；其中，时钟数据恢复单元被配置为根据第二信号，对时钟数据恢复单元的带宽进行调节。通过上述方式，具体采用调节CDR中电荷泵的输出电流、滤波回路中的电阻、滤波回路中的电容等方式来调节时钟数据恢复单元的带宽，能够在第二信号产生干扰时，通过调节带宽来减少干扰信号对时钟数据恢复单元的影响，从而保证了时钟数据恢复单元的工作性能，也进一步保证了显示装置的显示画面的正常。
以上对本申请实施例所提供的显示屏进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种驱动电路，其特征在于，所述驱动电路包括：
    时钟数据恢复单元，用于接收时序控制电路发送的第一信号；
    输出单元，连接所述时钟数据恢复单元，所述输出单元用于输出第二信号；
    其中，所述时钟数据恢复单元被配置为根据所述第二信号，对所述时钟数据恢复单元的带宽进行调节。
  2. 根据权利要求1所述的驱动电路，其特征在于，
    所述时钟数据恢复单元被配置为在所述第二信号对所述时钟数据恢复单元产生信号干扰时，对所述时钟数据恢复单元的带宽进行调节。
  3. 根据权利要求2所述的驱动电路，其特征在于，
    所述时钟数据恢复单元被配置为在所述第二信号的信号转换区间，对所述时钟数据恢复单元的带宽进行调节；
    所述信号转换区间为所述第二信号的电平转换时间区间。
  4. 根据权利要求3所述的驱动电路，其特征在于，
    所述时钟数据恢复单元被配置为在所述第二信号的信号转换区间开始时，将所述时钟数据恢复单元的带宽从第一带宽调节至第二带宽，以及在所述第二信号的信号转换区间结束时，将所述时钟数据恢复单元的带宽从所述第二带宽调节至所述第一带宽；
    其中，所述第二带宽大于所述第一带宽。
  5. 根据权利要求1所述的驱动电路，其特征在于，
    所述时钟数据恢复单元包括：
    第一分频器，所述第一分频器的输入端用于输入所述第一信号；
    鉴频鉴相器，所述鉴频鉴相器的第一输入端连接所述第一分频器的输出端；
    电荷泵，所述电荷泵的输入端连接所述鉴频鉴相器的输出端；
    滤波器，所述滤波器的输入端连接所述电荷泵的输出端；
    压控振荡器，所述压控振荡器的输入端连接所述滤波器的输出端；
    第二分频器，所述第二分频器的输入端连接所述压控振荡器的输出端，所述第二分频器的输出端连接所述鉴频鉴相器的第二输入端。
  6. 根据权利要求5所述的驱动电路，其特征在于，
    所述电荷泵被配置为根据所述第二信号，对所述电荷泵的输出电流进行调节，以对所述时钟数据恢复单元的带宽进行调节。
  7. 根据权利要求5所述的驱动电路，其特征在于，
    所述滤波器包括：
    电阻，所述电阻的第一端连接所述电荷泵的输出端；
    第一电容，所述第一电容的第一端连接所述电阻的第二端，所述第一电容的第二端接地；
    第二电容，所述第二电容的第一端连接所述电荷泵的输出端，所述第二电容的第二端接地。
  8. 根据权利要求7所述的驱动电路，其特征在于，
    所述电阻被配置为根据所述第二信号，对所述电阻的电阻值进行调节，以对所述时钟数据恢复单元的带宽进行调节。
  9. 根据权利要求7所述的驱动电路，其特征在于，
    所述第一电容被配置为根据所述第二信号，对所述第一电容的电容值进行调节，以对所述时钟数据恢复单元的带宽进行调节。
  10. 一种显示装置，其特征在于，所述显示装置包括驱动电路，所述驱动电路是如权利要求1-9任一项所述的驱动电路。
PCT/CN2023/126581 2022-10-25 2023-10-25 一种驱动电路以及显示装置 WO2024088320A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102064825A (zh) * 2010-12-15 2011-05-18 硅谷数模半导体（北京）有限公司 时钟与数据恢复电路以及具有该电路的集成芯片
CN106656168A (zh) * 2016-12-30 2017-05-10 北京集创北方科技股份有限公司 时钟数据恢复装置及方法
CN107911113A (zh) * 2017-10-31 2018-04-13 北京集创北方科技股份有限公司 时钟数据恢复电路及其环路带宽调节方法、处理器
CN109787925A (zh) * 2019-03-08 2019-05-21 北京集创北方科技股份有限公司 检测电路、时钟数据恢复电路和信号检测方法
CN110444139A (zh) * 2018-05-03 2019-11-12 联咏科技股份有限公司 集成电路及其抗干扰方法
KR20210028057A (ko) * 2019-09-03 2021-03-11 삼성전자주식회사 클락 데이터 복원 회로와 이를 포함하는 디스플레이 장치
CN112713906A (zh) * 2020-12-22 2021-04-27 北京奕斯伟计算技术有限公司 噪声滤除电路以及噪声滤除方法
CN115001484A (zh) * 2022-05-25 2022-09-02 Tcl华星光电技术有限公司 时钟数据恢复电路及方法、显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102064825A (zh) * 2010-12-15 2011-05-18 硅谷数模半导体（北京）有限公司 时钟与数据恢复电路以及具有该电路的集成芯片
CN106656168A (zh) * 2016-12-30 2017-05-10 北京集创北方科技股份有限公司 时钟数据恢复装置及方法
CN107911113A (zh) * 2017-10-31 2018-04-13 北京集创北方科技股份有限公司 时钟数据恢复电路及其环路带宽调节方法、处理器
CN110444139A (zh) * 2018-05-03 2019-11-12 联咏科技股份有限公司 集成电路及其抗干扰方法
CN109787925A (zh) * 2019-03-08 2019-05-21 北京集创北方科技股份有限公司 检测电路、时钟数据恢复电路和信号检测方法
KR20210028057A (ko) * 2019-09-03 2021-03-11 삼성전자주식회사 클락 데이터 복원 회로와 이를 포함하는 디스플레이 장치
CN112713906A (zh) * 2020-12-22 2021-04-27 北京奕斯伟计算技术有限公司 噪声滤除电路以及噪声滤除方法
CN115001484A (zh) * 2022-05-25 2022-09-02 Tcl华星光电技术有限公司 时钟数据恢复电路及方法、显示面板

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