WO2024088076A1 - 一种基于单总线信息传输的数据流控方法、装置及通信系统 - Google Patents

一种基于单总线信息传输的数据流控方法、装置及通信系统 Download PDF

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Publication number
WO2024088076A1
WO2024088076A1 PCT/CN2023/124378 CN2023124378W WO2024088076A1 WO 2024088076 A1 WO2024088076 A1 WO 2024088076A1 CN 2023124378 W CN2023124378 W CN 2023124378W WO 2024088076 A1 WO2024088076 A1 WO 2024088076A1
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Prior art keywords
data
flow control
state
signal
data buffer
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PCT/CN2023/124378
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English (en)
French (fr)
Inventor
周超
赵东艳
李德建
杨立新
牛彬
代胜林
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北京智芯微电子科技有限公司
国网江苏省电力有限公司
国家电网有限公司
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Publication of WO2024088076A1 publication Critical patent/WO2024088076A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node

Definitions

  • the present invention relates to the field of communication technology, and in particular to a data flow control method, device and communication system based on single bus information transmission.
  • Hardware flow control means that when the receiving buffer is about to be full, the receiving end prompts the sending end to stop sending data through the level change of the preset pin;
  • software flow control means that when the receiving buffer is about to be full, the receiving end actively sends a specified character indicating that the receiving buffer is about to be full to the sending end, and the sending end stops sending data when it receives the specified character.
  • Software flow control has a certain bit error rate during data transmission, or the agreed characters sent by the receiving end are mixed into the binary data stream, which will cause the agreed characters to be lost during the transmission process and unable to reach the sending end, or fail to be recognized after reaching the sending end or be misjudged by the sending end, causing erroneous operation.
  • the purpose of the embodiments of the present invention is to provide a data flow control method, device and communication system based on single bus information transmission, which can solve or partially solve the problems existing in the data transmission process.
  • an embodiment of the present invention provides a data flow control method based on single bus information transmission, based on a data receiving end, the method includes:
  • Detecting a state of a data buffer at a data receiving end wherein the state includes that the data buffer is idle and the data buffer is saturated;
  • an initialization signal is sent to the data sending end; when no initialization response signal from the data sending end is received within a preset time, the initialization signal is repeatedly sent;
  • the initialization signal, the data writing preparation signal and the state of the data buffer are sent through a single flow control bus.
  • the data buffer being saturated includes that a storage space occupancy ratio of the data buffer is greater than a first limit value; and the data buffer being idle includes that a storage space occupancy ratio of the data buffer is not greater than a second limit value.
  • the method when the state of the data buffer changes, before sending an initialization signal to the data sending end, the method also includes: detecting the state of the flow control bus, the state of the flow control bus including an idle state and a busy state; when it is determined that the flow control bus is in the idle state, sending the initialization signal to the data sending end.
  • detecting the state of the flow control bus includes:
  • sending the initialization signal to the data sending end includes: pulling down the level of the flow control bus and maintaining it for a second time.
  • sending a write data preparation signal to the data sending end includes: pulling down a level of a flow control bus and maintaining it for a fifth time.
  • sending the status of the data buffer to the data sending end includes: when the status of the data buffer is that the data buffer is idle, completing a signal operation of writing 0 within a sixth time; when the status of the data buffer is that the data buffer is saturated, completing a signal operation of writing 1 within a sixth time.
  • an embodiment of the present invention further provides a data flow control method based on single bus information transmission, based on a data sending end, the method includes:
  • the initialization response signal is sent through a single flow control bus; and the data transmission is performed through a data bus.
  • sending the initialization response signal includes: pulling down the level of the flow control bus and maintaining it for a fourth time.
  • the method before sending the initialization response signal, the method further includes:
  • the state of the flow control bus is detected, and when it is determined that the flow control bus is in an idle state, the initialization response signal is sent.
  • the state of the data buffer sent by the receiving data receiving end includes: completing the reading of the 0 or 1 signal within a sixth time.
  • the present invention also provides a data flow control device based on single bus information transmission, and the device is configured to execute the data flow control method based on the data receiving end.
  • the present invention also provides a data flow control device based on single bus information transmission, and the device is configured to execute the data flow control method based on the data sending end.
  • the present invention also provides a communication system, which includes a data receiving end, a data sending end, a flow control bus, a data bus, a data flow control device based on the data receiving end, and a data flow control device based on the data sending end, wherein the data bus is used for data transmission between the data sending end and the data receiving end; the flow control bus is used for transmission of initialization signals, initialization response signals, write data preparation signals and data buffer status between the data sending end and the data receiving end.
  • the embodiment of the present invention proposes a flow control method for data transmission under a single bus state, which can realize the transmission of flow control state between devices through a single flow control bus.
  • the hardware interface is reduced from the original two flow control buses to one, and the peripheral hardware resources are saved through the single bus communication mode, and the wiring mode is optimized.
  • it solves the problem that in the original software flow control scheme, the data packet and the control symbol (flow control state) share the bus, which easily causes data string, low communication reliability, and misidentification, reduces the difficulty of disassembling and unpacking, improves the control efficiency, and can effectively prevent data loss.
  • FIG1 is a diagram of a serial port flow control hardware interface in the prior art
  • FIG. 2 is a serial port hardware flow control wiring diagram in the prior art
  • FIG3 is a serial port software flow control wiring diagram in the prior art
  • FIG. 4 is a flow chart of a data flow control method based on a data receiving end provided by an embodiment of the present invention
  • FIG5 is a state switching diagram of a data buffer provided by an embodiment of the present invention.
  • FIG. 7 is a timing diagram of an initialization response signal provided in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a flow control bus state of data transmission flow control provided by an embodiment of the present invention.
  • 10 is a flow control bus timing diagram of data transmission flow control provided in an embodiment of the present invention.
  • FIG. 11 is a flow chart of a data flow control method based on a data sending end provided in an embodiment of the present invention.
  • FIG. 12 is a communication system provided by an embodiment of the present invention.
  • the inventor of the present invention has found that, in the communication process, two data flow control modes, hardware flow control and software flow control, are currently generally used to solve the data loss problem caused by the mismatch of the data processing rate of the two communication parties.
  • serial port data communication for the USART serial port module of the universal control chip, as shown in Figure 1, it generally includes four pins for receiving data RXD, sending data TXD, requesting to send RTS and clearing to send CTS.
  • RXD and TXD are used for receiving and sending data
  • RTS and CTS are used for hardware data flow control.
  • the control chip determines whether the processor is saturated by detecting the receiving end FIFO, thereby controlling the RTS and CTS pin signals.
  • the hardware flow control of the USART serial port includes: in addition to the two data buses TXD and RXD, it also includes two flow control buses RTS and CTS.
  • RTS flow control buses
  • the USART serial port module also provides a software flow control method. As shown in Figure 3, when the data receiving end is saturated, it sends "XOFF" to the data sending end through TXD. Character, the data sending end stops sending data immediately after receiving the "XOFF"character; when the processing power of the data receiving end is released, it sends an "XON" character to the data sending end, and the data sending end starts sending data immediately after receiving the "XON” character.
  • the hardware resources need to control the reception and transmission of data through two flow control buses, RTS and CTS, which wastes the hardware resources of the chip.
  • RTS and CTS lines of the communicating parties must be cross-connected, which may cause functional failure due to wiring errors.
  • FIG4 is a flow chart of a data flow control method based on single bus information transmission provided in an embodiment of the present application.
  • an embodiment of the present invention provides a data flow control method based on single bus information transmission, based on a data receiving end, the method includes:
  • Step 400 Detecting the state of a data buffer at the data receiving end, wherein the state includes the data buffer being idle and the data buffer being saturated;
  • the "data sending end” refers to the serial communication end when the device with serial communication function acts as the sending end
  • the "data receiving end” refers to the serial communication end when the device with serial communication function acts as the receiving end, that is, the same device can act as both a data sending end and a data receiving end.
  • the "data buffer is free” refers to a state in which the data buffer storage space of the other end (data receiving end) is not full and can continue to receive data sent by the data sending end.
  • the data buffer being free includes the total storage space occupancy ratio of the data buffer being no greater than the first limit value; for example, the first limit value may be 0%, that is, when the data buffer of the data receiving end does not store data, it is deemed that the data buffer is free and can receive data sent by the data sending end. More preferably, the first limit value may be 75%, that is, the state in which the data buffer is not completely cleared is set as data buffer free.
  • the data sending end can continue to send data when the data buffer is not cleared (such as the first limit value is 75%), which can improve the efficiency of data transmission and save data transmission time.
  • the chip can be powered on by default.
  • the data buffer is idle, that is, the device can directly receive data sent by the data sender after power-on without detecting the status of the data buffer.
  • the “data buffer saturation” refers to the state that the data buffer storage space of the opposite end (data receiving end) is full or nearly full, and the data sent by the data sending end cannot be received.
  • the data buffer saturation includes that the storage space occupancy ratio of the data buffer is greater than or equal to the second limit value; for example, the second limit value can be set to 100%.
  • the second limit value is 75%.
  • the data sending end is not allowed to send data when the data buffer is not fully occupied, which can effectively prevent data loss caused by signal time delay.
  • the data receiving end sends a data buffer saturation state to the data sending end to prevent it from continuing to send data.
  • the data sending end may continue to send data, and at this time, the data buffer of the data receiving end is full and cannot continue to receive data from the data sending end. At this time, the transmitted data cannot be stored in the data buffer, resulting in data loss.
  • the data receiving end When the data buffer is not fully occupied, the data receiving end sends a data buffer saturation status to the data sending end to prevent it from continuing to send data. Before the data sending end receives the data buffer saturation status, the data sending end will continue to send data. At this time, the data buffer of the data receiving end is not full and can continue to store data, so there will be no data loss, which improves the reliability of data transmission.
  • the first limit value and the second limit value can be in the form of a percentage of the existing data in the data buffer storage space, or in other forms. For example, if the size of the data buffer is 100 BYTE, the first limit value is 95 BYTE, and the second limit value is 80 BYTE. There is no restriction on the size of the first limit value and the second limit value.
  • the device can determine the first limit value and the second limit value of the data buffer in advance based on the total storage space size of its own receiving buffer, and store the limit values in a predetermined register.
  • Step 410 When the state of the data buffer changes, an initialization signal is sent to the data sending end; when no initialization response signal from the data sending end is received within a preset time, the initialization signal is repeatedly sent;
  • FIG5 is a state switching diagram of the data buffer.
  • the data receiving end can detect the state change of its own data buffer at any time. No matter whether the data buffer changes from data buffer idle to data buffer saturated or from data buffer saturated to data buffer idle, it will trigger the data receiving end to send an initialization signal to the data sending end.
  • the initialization signal sent by the data receiving end is used to confirm whether the data sending end can communicate now. When it is confirmed that the data sending end can communicate, When communicating, the data receiving end can send the state of the data buffer to the data sending end, so as to control whether the sending end sends data or pauses sending data, thereby realizing data flow control.
  • the data receiving end detects that the state of the data buffer changes from data buffer idle to data buffer saturated. After the data receiving end sends an initialization signal to the data sending end to confirm whether communication is possible, it sends a data buffer saturation signal to inform the data sending end that it cannot continue to send data; when the data buffer changes from data buffer saturated to data buffer idle, the data receiving end sends an initialization signal to the data sending end to confirm whether communication is possible, and then sends a data buffer idle signal to inform the data sending end that it can continue to send data, thereby realizing safe and reliable data transmission.
  • the level of the flow control bus can be pulled down at any time and maintained for more than a second time, indicating that the data receiving end sends an initialization signal to the data sending end.
  • the data receiving end can detect whether the flow control bus is in an idle state. When the flow control bus is in an idle state, the data receiving end and the data sending end can send signals to each other. Relatively, when the flow control bus is in a busy state, the data receiving end and the data sending end cannot send signals to each other.
  • FIG. 6 is a timing diagram of the flow control bus idle signal, in which T1 is used to represent the first time for the convenience of description.
  • Step 420 In response to the initialization response signal of the data sending end, send a write data ready signal and the status of the data buffer to the data sending end in sequence; wherein the initialization signal, the write data ready signal and the status of the data buffer are sent through a single flow control bus.
  • the data transmitting end When the data transmitting end detects that the flow control bus is pulled down for the second time, it indicates that the initialization signal sent by the data receiving end is received. When the data transmitting end can communicate with the data receiving end, the data transmitting end can send an initialization response signal to the data transmitting end. When the data transmitting end cannot communicate with the data receiving end at this time, the data transmitting end refuses to send an initialization response signal to the receiving end.
  • the level of the flow control bus can be pulled down and maintained for more than a fourth time, indicating that the data transmitting end sends an initialization response signal to the data receiving end. It should be noted that after the data receiving end sends the initialization signal to the data transmitting end, the flow control bus will be released and maintained for a third time.
  • FIG. 7 is a timing diagram of the initialization response signal.
  • T2 is used to represent the second time
  • T3 is used to represent the third time
  • T4 is used to represent the fourth time.
  • the data receiving end may repeatedly send the initialization signal, thereby achieving sustainability of data flow control and reliability of data transmission.
  • the data receiving end may send a write data ready signal before sending the state of the data buffer after receiving the initialization response signal from the data sending end.
  • the level of the flow control bus may be pulled down and maintained for a fifth time to indicate a write data ready signal, and the write data ready signal is used to prompt the data sending end to receive data.
  • FIG8 is a timing diagram of the read and write data signal provided by an embodiment of the present invention.
  • T5 is used to represent the fifth time
  • T6 is used to represent the sixth time for the convenience of description.
  • FIG9 is a state diagram of the flow control bus of the data transmission flow control provided by an embodiment of the present invention.
  • bus data 1 when bus data 1 is received, the data sending end is prohibited from sending data; when bus data 0 is received, it indicates that the data sending end is allowed to send data.
  • the data buffer of the data receiving end When the data buffer of the data receiving end is full (saturated), data 1 is sent to the flow control bus.
  • the data buffer of the data receiving end When the data buffer of the data receiving end is idle, data 0 is sent to the flow control bus.
  • first time, the second time, the third time, the fourth time, the fifth time and the sixth time can be set to different values for distinction.
  • first time can be 1000 to 1200 us
  • second time can be 480 to 960 us
  • third time can be 100 to 400 us
  • fourth time can be 480 to 960 us
  • fifth time can be 100 to 400 us
  • sixth time can be 600 to 960 us.
  • FIG10 is a flow control bus timing diagram of data transmission flow control provided by an embodiment of the present invention.
  • the master-slave mode of the original single bus communication protocol is cancelled, that is, the master-slave is not specified, that is, any device on the flow control bus can be used as a communication host, thereby realizing bidirectional data transmission.
  • the data receiving end sends an initialization signal, and then waits for the data sending end device to respond.
  • the master-slave status is confirmed (the communication initiator is the host, and the responder is the slave).
  • the host (data receiving end) waits for the slave (data sending end) to release the flow control bus, and then starts writing data, thereby realizing data flow control.
  • FIG11 is a data flow control method based on single bus information transmission provided by an embodiment of the present invention, based on a data sending end, the method includes:
  • Step S1100 sending an initialization response signal in response to the initialization signal sent by the data receiving end;
  • Step S1110 receiving a write data preparation signal and a data buffer status sent by the data receiving end; when the data buffer status is that the data buffer is idle, starting data transmission;
  • Step S1120 When the state of the data buffer is that the data buffer is saturated, stop data transmission; wherein the initialization response signal is sent through a single flow control bus; and the data transmission is performed through the data bus.
  • data flow control method provided in the embodiment of the present invention can be used not only for serial communication, but also in other communication modes, such as SPI communication and I2C communication, and any communication interface that requires data flow control or status transmission, without limitation here.
  • the embodiment of the present invention proposes a flow control method for data transmission under a single bus state, wherein the initialization signal, data write preparation signal, initialization response signal and data buffer status are all sent through a single flow control bus.
  • the hardware interface is reduced from the original two flow control bus lines to one, saving peripheral hardware resources and optimizing the wiring method.
  • it solves the problem that in the original software flow control scheme, data packets and control symbols share the bus, which easily causes data string, low communication reliability and misidentification, reduces the difficulty of disassembling and unpacking, improves control efficiency, and can effectively prevent data loss.
  • the present invention also provides a flow control device for data transmission, which is configured to execute the flow control method for data transmission based on the data receiving end.
  • the present invention also provides a data flow control device based on single bus information transmission, and the device is configured to execute the data flow control method based on the data sending end.
  • the present invention also provides a data flow control device based on single bus information transmission, and the device is configured to execute the data flow control method based on the data receiving end.
  • Figure 12 is a communication system provided by an embodiment of the present invention, wherein the system includes a data receiving end, a data sending end, a flow control bus, a data bus, a data flow control device based on the data receiving end, and a data flow control device based on the data sending end, wherein the data bus is used for data transmission between the data sending end and the data receiving end; the flow control bus is used for transmission of initialization signals, initialization response signals, write data preparation signals, and data buffer status between the data sending end and the data receiving end.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • a computing device includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
  • processors CPU
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and/or non-volatile memory in the form of read-only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information.
  • Information can be computer readable instructions, data structures, program modules or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
  • computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

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Abstract

本发明实施例提供一种基于单总线信息传输的数据流控方法、装置及通信系统，属于通信技术领域。所述数据流控方法基于数据接收端，包括：检测数据接收端的数据缓冲区的状态，所述状态包括数据缓冲区空闲和数据缓冲区饱和；当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号；当超过预设时间未接收到所述数据发送端的初始化应答信号时，重复发送所述初始化信号；响应于所述数据发送端的所述初始化应答信号，依次向所述数据发送端发送写数据准备信号和所述数据缓冲区的状态；其中，所述初始化信号、写数据准备信号和数据缓冲区的状态通过单根流控总线发送。通过本发明实施例，可以实现总线设备间的通信状态传输，可以有效防止通信数据丢失。

Description

一种基于单总线信息传输的数据流控方法、装置及通信系统 技术领域
本发明涉及通信技术领域，具体地涉及一种基于单总线信息传输的数据流控方法、装置及通信系统。
背景技术
数据在两个串口之间进行高速通信的时候常常会出现丢失数据的现象，比如两台计算机或者是一台计算机和一个单片机之间进行通讯，当接收端的接收缓冲区已满，这时如果还有数据发送过来，因为接收端没有时间进行处理，就有可能出现数据丢失。
目前解决这种问题有硬件流控和软件流控两种处理方法。硬件流控即接收端在接收缓冲区将满时，通过预设引脚的电平变化提示发送端停止发送数据；软件流控则是接收端在接收缓冲区将满时，主动向发送端发送一个表示接收缓冲区将满的约定字符，发送端接收到该约定字符时停止发送数据。
然而，硬件流控在硬件资源上需要通过RTS(请求发送，Request To Send)和CTS(清除发送，Clear To Send)两根线来控制数据的接收及发送，在芯片硬件资源比较紧张的情况下，这种方式会浪费硬件资源。同时，通信双方的RTS和CTS线必须交叉连接，存在接线错误导致功能失效的风险。
软件流控在数据传输时存在一定的误码率，或是接收端发送的约定字符混入二进制数据流中，会造成约定字符在传输过程中丢失、无法到达发送端，或者在到达发送端后未能被识别或是被发送端误判而引起误操作的问题。
发明内容
本发明实施例的目的是提供一种基于单总线信息传输的数据流控方法、装置及通信系统，可以解决或部分解决数据传输过程中存在的问题。
为了实现上述目的，本发明实施例提供一种基于单总线信息传输的数据流控方法，基于数据接收端，所述方法包括：
检测数据接收端的数据缓冲区的状态，所述状态包括数据缓冲区空闲和数据缓冲区饱和；
当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号；当超过预设时间未接收到所述数据发送端的初始化应答信号时，重复发送所述初始化信号；
响应于所述数据发送端的所述初始化应答信号，依次向所述数据发送端发送写数据准备信号和所述数据缓冲区的状态；
其中，所述初始化信号、写数据准备信号和数据缓冲区的状态通过单根流控总线发送。
可选的，所述数据缓冲区饱和包括所述数据缓冲区的存储空间占用比例大于第一限位值；所述数据缓冲区空闲包括所述数据缓冲区的存储空间占用比例不大于第二限位值。
可选的，在当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号之前，所述方法还包括：检测流控总线的状态，所述流控总线的状态包括空闲状态和繁忙状态；当判定所述流控总线处于空闲状态时，向数据发送端发送所述初始化信号。
可选的，所述检测流控总线的状态包括：
当检测到流控总线的电平维持高电平超过第一时间时，判定所述流控总线处于空闲状态；
当检测到流控总线处于高低电平切换状态时或流控总线处于低电平状态时，判定所述流控总线处于繁忙状态。
可选的，所述向数据发送端发送初始化信号包括：将流控总线的电平拉低并维持第二时间。
可选的，所述向所述数据发送端发送写数据准备信号包括：将流控总线的电平拉低并维持第五时间。
可选的，所述向所述数据发送端发送所述数据缓冲区的状态包括：当所述数据缓冲区的状态为所述数据缓冲区空闲时，在第六时间内完成写0的信号操作；当所述数据缓冲区的状态为所述数据缓冲区饱和时，在第六时间内完成写1的信号操作。
另一方面，本发明实施例还提供一种基于单总线信息传输的数据流控方法，基于数据发送端，所述方法包括：
响应于数据接收端发送的初始化信号，发送初始化应答信号；
接收所述数据接收端发送的写数据准备信号和数据缓冲区的状态；当所述数据缓冲区的状态为空闲时，开始数据传输；
当所述数据缓冲区的状态为饱和时，停止数据传输；
其中，所述初始化应答信号通过单根流控总线发送；所述数据传输通过数据总线进行。
可选的，所述发送初始化应答信号包括：将流控总线的电平拉低并维持第四时间。
可选的，在发送初始化应答信号之前，所述方法还包括：
检测流控总线的状态，当判定所述流控总线处于空闲状态时，发送所述初始化应答信号。
可选的，所述接收数据接收端发送的数据缓冲区的状态包括：在第六时间内，完成0或1信号的读取。
另一方面，本发明还提供一种基于单总线信息传输的数据流控装置，所述装置被配置为执行基于数据接收端的所述数据流控方法。
另一方面，本发明还提供一种基于单总线信息传输的数据流控装置，所述装置被配置为执行基于数据发送端的所述数据流控方法。
另一方面，本发明还提供一种通信系统，所述系统包括数据接收端、数据发送端、流控总线、数据总线、基于数据接收端的数据流控装置以及基于数据发送端的数据流控装置，所述数据总线用于所述数据发送端和数据接收端之间的数据传输；所述流控总线用于所述数据发送端和数据接收端之间初始化信号、初始化应答信号、写数据准备信号和数据缓冲区的状态的传输。
本发明实施例提出了一种单总线状态下的数据传输的流控方法，可以通过单根流控总线实现设备间的流控状态的传输，在不改变原硬件流控功能的基础上，硬件接口由原来的两根流控总线缩减为了一根，通过单总线通信方式节约了外围硬件资源，优化了接线方式。同时解决了原软件流控方案中，数据包和控制符(流控状态)共用总线，容易造成数据串包，通信可靠性低、误识别的问题，降低了拆、解包难度，提升了控制效率，可以有效防止数据丢失。
本发明实施例的其它特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明实施例，但并不构成对本发明实施例的限制。在附图中：
图1是现有技术中的串口流控硬件接口图；
图2是现有技术中的串口硬件流控接线图；
图3是现有技术中的串口软件流控接线图；
图4是本发明实施例提供的一种基于数据接收端的数据流控方法的流程图；
图5是本发明实施例提供的数据缓冲区的状态切换图；
图6是本发明实施例提供的流控总线空闲时序图；
图7是本发明实施例提供的初始化应答信号时序图；
图8是本发明实施例提供的读写数据信号时序图；
图9是本发明实施例提供的数据传输流控的流控总线状态示意图；
图10是本发明实施例提供的数据传输流控的流控总线时序图；
图11是本发明实施例提供的一种基于数据发送端的数据流控方法的流程图；
图12是本发明实施例提供的一种通信系统。
具体实施方式
以下结合附图对本发明实施例的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明实施例，并不用于限制本发明实施例。
本发明的发明人发现，在通信过程中，目前通常采用硬件流控和软件流控两种数据流控制方式以解决由于通信双方数据处理速率不匹配而导致的数据丢失问题。例如，在串口数据通信中，对于通用控制芯片的USART串口模块，如图1所示，一般包含接收数据RXD、发送数据TXD、请求发送RTS和清除发送CTS四个引脚。其中，RXD和TXD用于数据的接收与发送，而RTS和CTS则用于硬件数据流控。控制芯片通过检测接收端FIFO来判断处理器是否饱和，从而控制RTS和CTS引脚信号。
如图2硬件流控接线图所示，USART串口硬件流控包括：除TXD和RXD两根数据总线外，还包括RTS和CTS两根流控总线。当数据接收端处理能力饱和，即FIFO满时，就通过RTS引脚发出“清除接收/停止发送”的信号，数据发送端读取CTS引脚识别到此信号后就会停止数据发送，直到数据接收端的处理能力释放，通过RTS发出“可以接收/请求接收”的信号，数据发送端才继续发送数据。
考虑到线缆数量限制，除硬件流控外，USART串口模块还提供了一种软件流控的方式。如图3所示，当数据接收端处理饱和时，就通过TXD向数据发送端发出“XOFF” 字符，数据发送端收到“XOFF”字符后当即中止发送数据；当数据接收端的处理能力释放时，就向数据发送端发出“XON”字符，数据发送端收到“XON”字符后当即开始发送数据。
对于硬件流控，硬件资源上需要通过RTS和CTS两根流控总线控制数据的接收及发送，比较浪费芯片的硬件资源。另外，通信双方的RTS和CTS线必须交叉连接，存在接线错误导致功能失效的风险。
其次是软件流控，虽然软件方式规避了RTS和CTS引脚的使用，但是将软件流控的控制字符穿插在正常通信数据包中，不仅增加了拆包、解包难度，而且很容易引起误识别，尤其传输的数据是二进制时，标志字符也有可能在数据流中出现。基于此，本发明的发明人提出了一种基于单总线的数据传输的流控方法，只需要一根流控总线就可以完成数据流控，不仅节约了硬件资源，优化接线方式，同时避免了现有软件流控存在的数据串包问题。
图4是本申请实施例提供的一种基于单总线信息传输的数据流控方法的流程图。
如图4所示，本发明实施例提供一种基于单总线信息传输的数据流控方法，基于数据接收端，所述方法包括：
步骤400：检测数据接收端的数据缓冲区的状态，所述状态包括数据缓冲区空闲和数据缓冲区饱和；
需要说明的是，本申请实施例中“数据发送端”指具有串口通信功能的设备作为发送端角色时的串口通信端，“数据接收端”指具有串口通信功能的设备作为接收端角色时的串口通信端，即同一设备既可以作为数据发送端又可以作为数据接收端。
所述“数据缓冲区空闲”指对端(数据接收端)的数据缓冲区存储空间未满，可以继续接收数据发送端发送数据的状态。优选的，所述数据缓冲区空闲包括所述数据缓冲区的总存储空间占用比例不大于第一限位值；例如，所述第一限位值可以为0％，即当数据接收端的数据缓冲区未存储数据时，认定为数据缓冲区空闲，可以接收数据发送端发送数据。更优选的，所述第一限位值可以为75％，即将数据缓冲区未完全清空的状态设置为数据缓冲区空闲。相比于数据缓冲区清空(第一限位值为0％)之后数据发送端再发送数据，数据缓冲区未清空(如第一限位值为75％)时，数据发送端即可继续发送数据的方式可以提高数据传输的效率，节省数据传输的时间。可选的，芯片上电可以默认为 数据缓冲区空闲，即设备上电可以直接接收数据发送端发送的数据，无需检测数据缓冲区的状态。
所述“数据缓冲区饱和”指对端(数据接收端)的数据缓冲区存储空间已满或接近已满，无法继续接收数据发送端发送数据的状态。优选的，所述数据缓冲区饱和包括所述数据缓冲区的存储空间占用比例大于或等于第二限位值；例如，可以设置所述第二限位值为100％，当数据缓冲区的数据占总存储空间的100％时，即达到第二限位值时，认定为数据缓冲区饱和，无法接收数据发送端发送数据的状态。更优选的，所述第二限位值为75％，相比于将数据缓冲区存储空间完全占用时定义为数据缓冲区饱和状态，数据缓冲区未完全占用时不允许数据发送端发送数据的方式，可以有效预防由于信号的时间延迟造成的数据丢失。例如，当检测到数据缓冲区存储空间完全被占用后，数据接收端发送数据缓冲区饱和状态给数据发送端，阻止其继续发送数据，在数据发送端接收到数据缓冲区饱和状态之前，数据发送端可能会继续发送数据，而此时数据接收端数据缓冲区已满，无法继续接收数据发送端的数据，此时传输的数据无法存储在数据缓冲区，造成数据丢失。当数据缓冲区未完全占用时，数据接收端发送数据缓冲区饱和状态给数据发送端，阻止其继续发送数据，数据发送端接收到数据缓冲区饱和状态之前，数据发送端会继续发送数据，而此时数据接收端数据缓冲区未满，可以继续存储数据，因此不会造成数据的丢失，提高了数据传输的可靠性。
需要说明的，所述第一限位值和第二限位值可以是现有数据占数据缓冲区存储空间的百分比的形式，也可以是其他形式，如数据缓冲区的大小是100BYTE，第一限位值是95BYTE，第二限位值是80BYTE，此处对第一限位值和第二限位值的大小不加以限制，在具体实施中，设备可以预先根据自身接收缓冲区的总存储空间大小确定数据缓冲区的第一限位值和第二限位值，并将所述限位值存于一个预定的寄存器中。
步骤410：当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号；当超过预设时间未接收到所述数据发送端的初始化应答信号时，重复发送所述初始化信号；
图5是数据缓冲区的状态切换图，数据接收端可以随时检测自身数据缓冲区的状态变化，无论数据缓冲区由数据缓冲区空闲转为数据缓冲区饱和还是由数据缓冲区饱和转为数据缓冲区空闲，都会触发数据接收端向数据发送端发送初始化信号。所述数据接收端发送的初始化信号用于确认数据发送端现在是否可以通信。当确认所述数据发送端可 以通信时，数据接收端能够将数据缓冲区的状态发送给数据发送端，以此控制发送端发送数据还是暂停发送数据，实现数据的流控。具体的，数据接收端和发送端在传输数据的过程中，数据接收端检测到数据缓冲区的状态由数据缓冲区空闲转为数据缓冲区饱和，数据接收端向数据发送端发送初始化信号确认是否可以通信后，发送数据缓冲区饱和信号，告知数据发送端不能继续发送数据；当数据缓冲区由数据缓冲区饱和转为数据缓冲区空闲时，数据接收端向数据发送端发送初始化信号确认是否可以通信后，发送数据缓冲区空闲的信号，告知数据发送端可以继续发送数据，以此实现数据的安全可靠的传输。
优选的，可以通过任意时刻将流控总线的电平拉低并维持超过第二时间，表示数据接收端向数据发送端发送初始化信号。需要说明的是，在发送所述初始换信号之前，数据接收端可以检测流控总线是否处于空闲状态，流控总线处于空闲状态时，数据接收端和数据发送端才可以相互发送信号。相对的，流控总线处于繁忙状态时，数据接收端和数据发送端不可以相互发送信号。具体的，可以通过检测流控总线的电平维持高电平的时间是否超过第一时间，当检测到流控总线的电平维持高电平的时间超过第一时间时，可以判定流控总线处于空闲状态，可以利用流控总线收发信号；当检测到流控总线处于高低电平切换状态时或流控总线处于低电平状态时，可以将流控总线示为繁忙状态，不可以相互发送信号。图6是流控总线空闲信号时序图，图中为了方便描述用T1表示第一时间。
步骤420：响应于所述数据发送端的所述初始化应答信号，依次向所述数据发送端发送写数据准备信号和所述数据缓冲区的状态；其中，所述初始化信号、写数据准备信号和数据缓冲区的状态通过单根流控总线发送。
数据发送端检测到流控总线被拉低第二时间时，表示收到数据接收端发送的初始化信号，当数据发送端可以和数据接收端进行通信时，可以向数据发送端发送初始化应答信号，当数据发送端此时不可以和数据接收端通信时，拒绝向接收端发送初始化应答信号。优选的，可以通过将流控总线的电平拉低并维持超过第四时间，表示数据发送端向数据接收端发送初始化应答信号。需要说明的是，数据接收端向数据发送端发送初始化信号后，会释放流控总线并维持第三时间，在数据发送端发送初始化应答信号之前，数据发送端会检测流控总线是否处于空闲状态，当检测到流控总线处于空闲状态时，发送初始化应答信号，表示可以通信，图7是初始化应答信号时序图，图中为了方便描述用T2表示第二时间，用T3表示第三时间，T4表示第四时间。
本发明提供的一个实施例中，数据接收端发送初始化信号后，在当超过预设时间未接收到所述初始化应答信号时，数据接收端可以重复发送所述初始化信号，以此实现数据流控的可持续性和数据传输的可靠性。
优选的，为了保证数据传输的可靠性，数据接收端在收到数据发送端的初始化应答信号之后，可以发送所述数据缓冲区的状态之前可以发送写数据准备信号。具体的，可以将流控总线的电平拉低并维持第五时间表示写数据准备信号，所述写数据准备信号用于提示数据发送端接收数据。
当数据接收端发送写数据准备信号之后，在第六时间内完成写0或写1的信号操作，图8是本发明实施例提供的读写数据信号时序图，图中为了方便描述用T5表示第五时间，用T6表示第六时间。当所述数据缓冲区空闲时，在第六时间内完成写0的信号操作；当所述数据缓冲区饱和时，在第六时间内完成写1的信号操作。图9是本发明实施例提供的数据传输流控的流控总线的状态示意图，在第六时间内，当收到总线数据1时，禁止数据发送端发送数据；收到总线数据0时，表示允许数据发送端发送数据，当数据接收端数据缓冲区存满(饱和)时，向流控总线发送数据1，当数据接收端数据缓冲区空闲时，向流控总线发送数据0。
需要说明的是，所述第一时间、第二时间、第三时间、第四时间、第五时间以及第六时间可以设置为不同数值，从而进行区分。例如，第一时间可以为1000至1200us，第二时间可以为480至960us，第三时间可以为100至400us，第四时间可以为480至960us，第五时间可以为100至400us，第六时间可以为600至960us。
图10是本发明实施例提供的数据传输流控的流控总线时序图。本发明提供的一个实施例中，为了使单总线通信协议适用于数据流控，取消了原有的单总线通信协议的主从机模式，即不指定主从机，也就是说流控总线上任意设备都可以作为通信主机，以此实现数据的双向传输。具体的，当监测到流控总线空闲时，数据接收端发送一个初始化信号，随后等待数据发送端设备应答，应答成功后，主从机状态确认(通信发起方作为主机，应答方作为从机)，之后，主机(数据接收端)等待从机(数据发送端)将流控总线释放后，开始写数据，以此实现数据流控。
图11是本发明实施例提供的一种基于单总线信息传输的数据流控方法，基于数据发送端，所述方法包括：
步骤S1100：响应于数据接收端发送的初始化信号，发送初始化应答信号；
步骤S1110：接收所述数据接收端发送的写数据准备信号和数据缓冲区的状态；当所述数据缓冲区的状态为数据缓冲区空闲时，开始数据传输；
步骤S1120：当所述数据缓冲区的状态为数据缓冲区饱和时，停止数据传输；其中，所述初始化应答信号通过单根流控总线发送；所述数据传输通过数据总线进行。
需要说明的是，本发明实施例提供的数据流控方法不仅可以用于串口通信，还可以应用于其它通信方式中，如SPI通信以及I2C通信等任何需要进行数据流控或者状态传输的通信接口中，此处不加以限制。
本发明实施例提出了一种单总线状态下的数据传输的流控方法，其中所述初始化信号、写数据准备信号、初始化应答信号和数据缓冲区的状态都是通过单跟流控总线发送，在不改变原硬件流控功能的基础上，硬件接口由原来的两根流控总线线缩减为了一根，节约了外围硬件资源，优化了接线方式。同时解决了原软件流控方案中，数据包和控制符共用总线，容易造成数据串包，通信可靠性低、误识别的问题，降低了拆、解包难度，提升了控制效率，可以有效防止数据丢失。相应的，本发明还提供一种数据传输的流控装置，所述装置被配置为执行基于数据接收端的所述数据传输的流控方法。
相应的，本发明还提供一种基于单总线信息传输的数据流控装置，所述装置被配置为执行基于数据发送端的所述数据流控方法。
相应的，本发明还提供一种基于单总线信息传输的数据流控装置，所述装置被配置为执行基于数据接收端的所述数据流控方法。
图12是本发明实施例提供的一种通信系统，所述系统包括数据接收端、数据发送端、流控总线、数据总线、基于数据接收端的数据流控装置以及基于数据发送端的的数据流控装置，所述数据总线用于所述数据发送端和数据接收端之间的数据传输；所述流控总线用于所述数据发送端和数据接收端之间初始化信号、初始化应答信号、写数据准备信号和数据缓冲区的状态的传输。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程 图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
存储器可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。存储器是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性 的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (14)

  1. 一种基于单总线信息传输的数据流控方法，其特征在于，基于数据接收端，所述方法包括：
    检测数据接收端的数据缓冲区的状态，所述状态包括数据缓冲区空闲和数据缓冲区饱和；
    当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号；当超过预设时间未接收到所述数据发送端的初始化应答信号时，重复发送所述初始化信号；
    响应于所述数据发送端的所述初始化应答信号，依次向所述数据发送端发送写数据准备信号和所述数据缓冲区的状态；
    其中，所述初始化信号、写数据准备信号和数据缓冲区的状态通过单根流控总线发送。
  2. 根据权利要求1所述的数据流控方法，其特征在于，所述数据缓冲区饱和包括所述数据缓冲区的存储空间占用比例大于第一限位值；所述数据缓冲区空闲包括所述数据缓冲区的存储空间占用比例不大于第二限位值。
  3. 根据权利要求1所述的数据流控方法，其特征在于，在当所述数据缓冲区的状态发生改变时，向数据发送端发送初始化信号之前，所述方法还包括：检测流控总线的状态，所述流控总线的状态包括空闲状态和繁忙状态；当判定所述流控总线处于所述空闲状态时，向数据发送端发送所述初始化信号。
  4. 根据权利要求3所述的数据流控方法，其特征在于，所述检测流控总线的状态包括：
    当检测到流控总线的电平维持高电平超过第一时间时，判定所述流控总线处于空闲状态；
    当检测到所述流控总线处于高低电平切换状态时或所述流控总线处于低电平状态时，判定所述流控总线处于繁忙状态。
  5. 根据权利要求1所述的数据流控方法，其特征在于，所述向数据发送端发送初始化信号包括：将流控总线的电平拉低并维持第二时间。
  6. 根据权利要求1所述的数据流控方法，其特征在于，所述向所述数据发送端发送写数据准备信号包括：将流控总线的电平拉低并维持第五时间。
  7. 根据权利要求1所述的数据流控方法，其特征在于，所述向所述数据发送端发送所述数据缓冲区的状态包括：当所述数据缓冲区的状态为所述数据缓冲区空闲时，在 第六时间内完成写0的信号操作；当所述数据缓冲区的状态为所述数据缓冲区饱和时，在第六时间内完成写1的信号操作。
  8. 一种基于单总线信息传输的数据流控方法，基于数据发送端，其特征在于，所述方法包括：
    响应于数据接收端发送的初始化信号，发送初始化应答信号；
    接收所述数据接收端发送的写数据准备信号和数据缓冲区的状态；当所述数据缓冲区的状态为数据缓冲区空闲时，开始数据传输；
    当所述数据缓冲区的状态为数据缓冲区饱和时，停止数据传输；
    其中，所述初始化应答信号通过单根流控总线发送；所述数据传输通过数据总线进行。
  9. 根据权利要求8所述的数据流控方法，其特征在于，所述发送初始化应答信号包括：将流控总线的电平拉低并维持第四时间。
  10. 根据权利要求8或9所述的数据流控方法，其特征在于，在发送初始化应答信号之前，所述方法还包括：
    检测流控总线的状态，当判定所述流控总线处于空闲状态时，发送初始化应答信号。
  11. 根据权利要求8所述的数据流控方法，其特征在于，所述接收所述数据接收端发送的数据缓冲区的状态包括：在第六时间内，完成0或1信号的读取。
  12. 一种基于单总线信息传输的数据流控装置，其特征在于，基于数据接收端，所述装置被配置为执行权利要求1-7任一项所述的基于单总线信息传输的数据流控方法。
  13. 一种基于单总线信息传输的数据流控装置，其特征在于，基于数据发送端，所述装置被配置为执行权利要求8-11任一项所述的基于单总线信息传输的数据流控方法。
  14. 一种通信系统，其特征在于，所述系统包括数据接收端、数据发送端、流控总线、数据总线、权利要求12所述的数据流控装置以及权利要求13所述的数据流控装置，所述数据总线用于所述数据发送端和所述数据接收端之间的数据传输；所述流控总线用于所述数据发送端和所述数据接收端之间初始化信号、初始化应答信号、写数据准备信号和数据缓冲区的状态的传输。
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