WO2024087697A1 - 数据传输走线的布局方案、主板及电子设备 - Google Patents

数据传输走线的布局方案、主板及电子设备 Download PDF

Info

Publication number
WO2024087697A1
WO2024087697A1 PCT/CN2023/103272 CN2023103272W WO2024087697A1 WO 2024087697 A1 WO2024087697 A1 WO 2024087697A1 CN 2023103272 W CN2023103272 W CN 2023103272W WO 2024087697 A1 WO2024087697 A1 WO 2024087697A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
signal line
data
pair
matching
Prior art date
Application number
PCT/CN2023/103272
Other languages
English (en)
French (fr)
Inventor
许泷潇
彭相杰
江浙
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024087697A1 publication Critical patent/WO2024087697A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H01R13/6471—Means for preventing cross-talk by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding  
    • H01R13/658—High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields

Definitions

  • the present application relates to the technical field of data transmission, and in particular to a layout scheme for data transmission routing, a mainboard and an electronic device.
  • High definition multimedia interface HDMI
  • other video transmission interfaces with clock pairs are widely used in electronic devices due to their high audio/video transmission speed.
  • video transmission interfaces with clock pairs are prone to excessive electromagnetic interference (EMI).
  • EMI electromagnetic interference
  • the embodiments of the present application provide a data transmission line layout solution, a mainboard, and an electronic device for solving the problem of how to reduce electromagnetic interference in electronic devices.
  • a layout scheme for data transmission routing is provided, which can be applied to the routing layout of a high-definition multimedia interface, for example.
  • the data transmission routing includes a first clock pair signal line, a first data pair signal line, and a first matching line.
  • the first clock pair signal line includes a first clock signal line and a second clock signal line; the first clock pair signal line is used to transmit a clock signal.
  • the first data pair signal line includes a first data signal line and a second data signal line; the first data pair signal line is used to transmit a data signal.
  • the first clock pair signal line is located between the first matching line and the first data pair signal line; the first clock signal line is adjacent to the second data signal line, and the second clock signal line is adjacent to the first matching line; the first matching line includes a matching segment, and the first pair of inter-line spacing between the matching segment and the second clock signal line is equal to the second pair of inter-line spacing between the second data signal line and the first clock signal line.
  • the first side of the first clock pair signal line is arranged with the first data pair signal line
  • the second side opposite to the first clock pair signal line is arranged with the first matching line.
  • the existence of the first matching line can change the parasitic parameters (such as the size of the parasitic capacitance) on the second side of the first clock pair signal line.
  • EMI is reduced by improving the consistency of the parasitic parameters on both sides of the first clock pair signal line. Therefore, the length change of the first clock pair signal line will hardly affect the suppression effect of EMI. Therefore, the layout scheme of the data transmission line of the present application can significantly reduce the EMI caused by the increase of the long time difference common mode conversion of the first clock pair signal line. And the cost of forming the first matching line is extremely low, and does not affect the signal quality and the compatibility of docking with other devices.
  • the first matching line also includes a avoidance segment, the avoidance segment is connected to the matching segment, and the third pair of line spacing between the avoidance segment and the second clock signal line is greater than or less than the first pair of line spacing.
  • the layout scheme of the data transmission line also includes a second matching line, and the second matching line is located on the side of the first matching line away from the second clock signal line.
  • the second matching line By setting the second matching line on the side of the second clock signal line away from the first clock signal line, the parasitic parameters of the second clock signal line away from the first clock signal line can be adjusted, and the consistency of the parasitic parameters on both sides of the first clock pair signal line can be further improved. This can further reduce the differential common mode conversion in the first clock pair signal line and improve the EMI resistance. Inhibitory effect.
  • the first pair of inner line spacing between the matching section and the second matching line is equal to the second pair of inner line spacing between the first data signal line and the second data signal line.
  • the line width of the matching segment is equal to the line width of the second data signal line.
  • the first clock signal line and the second clock signal line are arranged in arc routing when they turn.
  • the arc routing does not increase the line width at the corner, and the arc routing at the turning point can be made equal or approximately equal to the width of the routing at the non-turning point, so that the impedance at each position of the first clock signal line and the second clock signal line is equal. In this way, the signal reflection caused by impedance change can be reduced.
  • the differential common mode conversion is further reduced, thereby reducing EMI.
  • the arc angles between the first clock signal line, the second clock signal line, the first data signal line, the second data signal line, and the first matching line are concentric arc angles.
  • the arc turning angles ⁇ between the first clock signal line 21, the second clock signal line 22, the first data signal line 31, the second data signal line 32, and the first matching line 41 are concentric arc angles ⁇ , which can make the first pair of line spacing S1 and the second pair of line spacing S2 at the corners equal, further improving the consistency of parasitic parameters on both sides of the first clock pair signal line 20.
  • two ends of the first matching line are aligned with two ends of the second data signal line.
  • the symmetry of the first matching line and the second data signal line on both sides of the first clock pair signal line can be further improved to improve the consistency of parasitic parameters on both sides of the first clock pair signal line.
  • the differential common mode conversion in the first clock pair signal line is further reduced, and the EMI suppression effect is improved.
  • At least one end of the first matching line is coupled to a reference ground voltage terminal.
  • a passive device is coupled between at least one end of the first matching line and the reference ground voltage terminal.
  • the passive device By coupling the passive device to at least one end of the first matching line, the symmetry of the first matching line and the second data signal line on both sides of the first clock pair signal line can be further improved by adjusting the passive device, so as to improve the consistency of parasitic parameters on both sides of the first clock pair signal line.
  • the differential common mode conversion in the first clock pair signal line is further reduced, and the EMI suppression effect is improved.
  • the passive device includes at least one of a resistor, a capacitor, an inductor, or a magnetic bead. This is an implementation with a simple structure.
  • the first matching line and the second matching line constitute a set of second data pair signal lines for transmitting data signals;
  • the layout scheme of the data transmission line also includes a second clock pair signal line;
  • the second clock pair signal line is arranged on the side of the second matching line away from the first matching line.
  • the first matching line is used to transmit a low-speed signal.
  • the existing two-wire serial bus can be used as the first matching line and the second matching line in the layout solution provided in the embodiment of the present application.
  • EMI can be reduced without increasing the number of routing lines.
  • the layout scheme of the data transmission line includes multiple pairs of first data pair signal lines, and the multiple pairs of first data pair signal lines are located on the same side of the first clock pair signal line.
  • the structure of multiple pairs of data pair signal lines can also use the layout scheme of the present application to suppress EMI.
  • the first clock pair signal line and the first data pair signal line are both used to couple between the processor and the output transmission interface connector. This is a possible application.
  • both the first clock pair signal line and the first data pair signal line are used to couple with a high-definition multimedia interface connector. This is a possible application.
  • the length of the first clock pair signal line is greater than 10 cm.
  • the EMI intensity is reduced by adopting the layout scheme of the data transmission line provided in the embodiment of the present application.
  • the EMI intensity is reduced by an average of 5 dB at a low cost.
  • a second aspect of an embodiment of the present application provides a mainboard, including a circuit board, a processor and an output transmission interface connector, the circuit board including a data transmission line, the data transmission line being laid out using the layout scheme of the data transmission line of any one of the first aspects; the first clock pair signal line and the first data pair signal line in the data transmission line are both coupled between the processor and the output transmission interface connector.
  • the mainboard provided in the embodiment of the present application includes the layout scheme of the data transmission lines of the first aspect, and its beneficial effects are the same as the beneficial effects of the layout scheme of the data transmission lines of the first aspect, which will not be repeated here.
  • an electronic device including a shielding shell and a main board, wherein the main board is located in the shielding shell, and the main board is the main board of the second aspect.
  • the electronic device provided in the embodiment of the present application includes the main board of the second aspect, and its beneficial effects are the same as the beneficial effects of the main board of the second aspect, which will not be repeated here.
  • FIG1A is a schematic diagram of an application scenario of an electronic device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of a framework of an electronic device provided in an embodiment of the present application.
  • FIG1C is a schematic diagram of the structure of a mainboard in an electronic device provided in an embodiment of the present application.
  • FIG1D is a schematic diagram of the structure of an HDMI connector provided in an embodiment of the present application.
  • FIG. 1E is a schematic diagram of a layout of wiring between an HDMI connector and a processor provided in an embodiment of the present application;
  • FIG2 is a schematic diagram of a layout of a data pair signal line and a clock pair signal line according to an embodiment of the present application
  • FIG3 is a schematic diagram of a layout of a data transmission line provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another layout of data transmission lines provided in an embodiment of the present application.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • the present application provides an electronic device having an audio/video transmission function.
  • the electronic device may include, for example, a network video recorder (NVR), a digital video recorder (DVR), a digital video recorder (XVR), an encoder (DVS), an all-in-one machine, an industrial computer, a gateway, an industry host, etc.
  • NVR network video recorder
  • DVR digital video recorder
  • XVR digital video recorder
  • DVD digital video recorder
  • the electronic device may also be an electronic device such as a set-top box that has audio/video transmission requirements.
  • the front-end camera device transmits the collected images, audio and other information to the electronic device, and the electronic device transmits multiple groups of images to the display device for display.
  • the display device can, for example, simultaneously display 9-grid or 12-grid monitoring images.
  • the network video recorder NVR includes a processor, and the processor may be, for example, a central processing unit (CPU).
  • the network video recorder NVR also includes a memory coupled to the central processing unit CPU, a flash memory, a hard disk data interface, an input and output (I/O) interface, an Ethernet interface, a video graphics array (VGA) interface, and a high definition multimedia interface (HDMI).
  • the processor, memory, flash memory, hard disk data interface, input and output (I/O) interface, Ethernet interface and high-definition multimedia interface HDMI can be set on a printed circuit board (PCB) as the main board of a network video recorder NVR.
  • PCB printed circuit board
  • the network video recorder NVR may further include a shielding shell, in which the mainboard is disposed.
  • the shielding shell may, for example, shield electromagnetic interference (EMI), and the material of the shielding shell may, for example, be metal.
  • EMI shield electromagnetic interference
  • the central processing unit CPU is used to process video data compression encoding, data reception and transmission and other network video recorder NVR services
  • the memory is used to provide temporary data storage space required by the central processing unit CPU during operation
  • the flash memory is used to provide permanent storage space for the network video recorder NVR firmware and system configuration information
  • the hard disk data interface is used to connect to the hard disk and transfer the video data to the hard disk for storage
  • the input and output interface is used to provide I/O triggered input and output
  • the Ethernet interface is used to connect to Ethernet
  • the VGA interface is used to connect to a VGA monitor and display video images through the VGA monitor
  • the high-definition multimedia interface HDMI is used to connect to a display device and display video images through the display device.
  • a high-definition multimedia interface connector at the high-definition multimedia interface HDMI is coupled to the processor through a clock pair signal line and a data pair signal line.
  • the main board of the electronic device includes a PCB, a data transmission port connector and a processor.
  • the data transmission port connector and the processor are arranged on the PCB.
  • the data transmission port connector is, for example, an HDMI connector, a mobile industry processor interface (MIPI) connector, etc.
  • the data transmission interface can be used to transmit data signals such as audio, video, and files.
  • 1C is illustrated by taking the data transmission port connector as an HDMI connector as an example.
  • the HDMI connector and the processor are coupled via wiring to complete signal transmission.
  • the wiring coupled between the HDMI connector and the processor can be integrated on a PCB.
  • the HDMI connector has multiple terminals
  • FIG. 1D illustrates an example in which the HDMI connector has 19 terminals.
  • Terminals 1 and 3 are used to transmit data pair signals (data 2+ and data 2-), and terminal 2 is used to couple with the shield layer of the data pair.
  • Terminals 4 and 6 are used to transmit data pair signals (data 1+ and data 1-), and terminal 5 is used to couple with the shield layer of the data pair.
  • Terminals 7 and 9 are used to transmit data pair signals (data 0+ and data 0-), and terminal 8 is used to couple with the shield layer of the data pair.
  • Terminals 10 and 12 are used to transmit clock pair signals (clock+ and clock-), and terminal 11 is used to couple with the shield layer of the clock pair.
  • Terminal 13 serves as the controller terminal CEC.
  • Terminal 14 serves as a reserved terminal.
  • Terminals 15 and 16 serve as connection terminals for a two-wire serial bus (inter-integrated circuit, I2C), terminal 15 serves as a bidirectional data line terminal SDA of the two-wire serial bus, and terminal 16 serves as a clock line terminal SCL of the two-wire serial bus.
  • Terminal 17 serves as a ground terminal.
  • Terminal 18 serves as a power supply terminal.
  • Terminal 19 serves as a hot-swap identification terminal.
  • Each terminal is coupled to a trace respectively, but only some of the terminals are coupled to the processor through the trace.
  • terminal 7 and terminal 9 are coupled to the processor via data pair signal line
  • terminal 4 and terminal 6 are coupled to the processor via data pair signal line 1
  • terminal 1 and terminal 3 are coupled to the processor via data pair signal line 2
  • terminal 10 and terminal 12 are coupled to the processor via clock pair signal line.
  • Terminal 2, terminal 5, terminal 8, and terminal 1 are used as shielding terminals, coupled to the shielding line, and the shielding line is not coupled to the processor.
  • terminal 1 to 19 in the HDMI connector terminal 1, terminal 3, terminal 4, terminal 6, terminal 7, terminal 9, terminal 10 and terminal 12 are coupled to the processor through wiring.
  • EMI electromagnetic interference
  • the location where the clock generates electromagnetic interference to the signal can be divided into two parts.
  • One part is the electromagnetic interference emitted from the PCB inside the electronic device, and the other part is the electromagnetic interference emitted by the connecting cables outside the electronic device.
  • the main reason for excessive electromagnetic interference is the asymmetry of the wiring of the clock pair on the PCB, which causes the differential common-mode conversion of the clock signal and generates a common-mode signal.
  • the common-mode signal has a large interference amplitude and high frequency, and can also radiate through the wiring, causing greater electromagnetic interference. Since the wiring length of the clock pair on the PCB is often much smaller than the length of the cable outside the electronic device, and the PCB is usually constrained in a metal shielding shell, the electromagnetic interference generated by the common-mode signal on the PCB is not the main reason for the excessive electromagnetic interference.
  • the electromagnetic interference generated by the common-mode signal carried out of the electronic device through the cable outside the electronic device is the main reason for the excessive electromagnetic interference.
  • the essence of the excessive electromagnetic interference is the asymmetry of the wiring of the clock pair on the PCB.
  • a clock pair signal line and a data pair signal line are included on a PCB, and the clock pair signal line and the data pair signal line are used to transmit signals such as audio, video, and documents.
  • the clock pair signal line and the data pair signal line are used to transmit signals such as audio, video, and documents.
  • the serpentine wire By winding the serpentine wire to keep the clock pair signal lines of equal length, the two signals with opposite polarities in the clock pair can be delivered at the same time, reducing the generation of common-mode signals and thus reducing EMI.
  • the clock pair signal lines of equal length inside the pair can improve the symmetry of the clock pair wiring, but the data pair signal lines are always located on one side of the clock pair signal lines. Therefore, even if the clock pair signal lines are of equal length inside the pair, there will be parasitic capacitance on both sides of the clock pair signal lines. This leads to a large differential common mode conversion when the routing is long (such as a high-definition multimedia interface HDMI routing of more than 10cm), due to the accumulation of small asymmetries in the environment around the clock pair signal lines, it will cause EMI problems.
  • EMI is reduced by adjusting relevant parameters of the motherboard.
  • EMI is reduced by adding radiation-suppressing components or materials.
  • Common-mode suppression inductors can convert common-mode signals generated by the asymmetry of the PCB routing into heat loss, reduce the common-mode signals transmitted to the external cables, and thus reduce EMI.
  • Using cables with higher shielding effects can effectively prevent EMI leakage, thereby reducing EMI.
  • Common-mode suppression inductors and better shielded cables can reduce EMI, but they also increase costs.
  • an embodiment of the present application provides a layout solution for data transmission lines, which is used to reduce the EMI caused by the clock to the signal line by adjusting the layout of the lines.
  • the data transmission line includes a first clock pair signal line 20 , a first data pair signal line 30 and a first matching line 41 .
  • the first clock pair signal line 20 includes a first clock signal line 21 and a second clock signal line 22 .
  • the first clock pair signal line 20 is used to transmit a clock signal.
  • the first data pair signal line 30 includes a first data signal line 31 and a second data signal line 32.
  • the first data pair signal line 30 is used to transmit a data signal.
  • the data transmission line may include a pair of first data pair signal lines 30, and the data transmission line may also include multiple pairs of first data pair signal lines 30.
  • the data transmission line includes multiple pairs of first data pair signal lines 30, the multiple pairs of first data pair signal lines 30 are located on the same side of the first clock pair signal line 20.
  • FIG3 is taken as an example in which the data transmission line includes multiple pairs of first data pair signal lines 30.
  • the first clock pair signal line 20 and the first data pair signal line 30 are both used to couple with an HDMI connector.
  • the first clock pair signal line 20 is used as the clock pair signal line in FIG. 1E , and is coupled to the terminal in the HDMI connector. 10 and terminal 12, and between the processor.
  • the plurality of pairs of first data pair signal lines 30 are three pairs of first data pair signal lines 30.
  • One pair of first data pair signal lines 30 is coupled between terminals 1 and 3 in the HDMI connector and the processor as data pair signal line 2 in FIG. 1E.
  • One pair of first data pair signal lines 30 is coupled between terminals 4 and 6 in the HDMI connector and the processor as data pair signal line 1 in FIG. 1E.
  • One pair of first data pair signal lines 30 is coupled between terminals 7 and 9 in the HDMI connector and the processor as data pair signal line 0 in FIG. 1E.
  • the first matching line 41 is used to adjust parasitic parameters around the first clock pair signal line 20 .
  • the first matching line 41 may be coupled to the HDMI connector, or the first matching line 41 may not be coupled to the HDMI connector.
  • the layout scheme of the data transmission line includes the first matching line 41 and the first data pair signal line 30 being located on opposite sides of the first clock pair signal line 20 , or it can be understood that the first clock pair signal line 20 is located between the first matching line 41 and the first data pair signal line 30 .
  • the first clock signal line 21 is disposed adjacent to the second data signal line 32
  • the second clock signal line 22 is disposed adjacent to the first matching line 41 .
  • the first matching line 41 includes a matching section 411 and a avoiding section 412 , and the avoiding section 412 is connected to the matching section 411 .
  • the position, number of times the avoidance section 412 appears in the first matching line 41, and the shape of the avoidance section 412 depend on the layout of the devices and pins around the data transmission line.
  • the avoidance section 412 is used to avoid the above-mentioned devices, pins and other components during the extension process of the first matching line 41.
  • the layout solution of the data transmission line provided in the embodiment of the present application can be applicable to any wiring scenario. No requirements are made on the layout of components such as devices and pins in the application scenario.
  • the avoidance section 412 can be used to avoid the devices and pins, thereby improving the scope of application.
  • the first pair of inter-line spacing S1 is equal to the second pair of inter-line spacing S2, and the first pair of inter-line spacing S1 is not equal to the third pair of inter-line spacing S3.
  • each third pair of inter-line spacing S3 is not equal to the first pair of inter-line spacing S1, and multiple different third pair of inter-line spacings S3 may be equal or unequal.
  • the equality in the embodiment of the present application is not absolute equality, and approximate equality also belongs to the equality in the embodiment of the present application.
  • the process error of the width of the first data signal line 31, the second data signal line 32, the first clock signal line 21, the second clock signal line 22 and the first matching line 41 itself is ⁇ 30%
  • the difference between the second pair of line spacing S2 and the first pair of line spacing S1 is ⁇ 60% of the first pair of line spacing S1, which also belongs to the embodiment of the present application that the first pair of line spacing S1 is equal to the second pair of line spacing S2.
  • first pair of inter-line spacing S1 may be larger than the third pair of inter-line spacing S3, and the first pair of inter-line spacing S1 may also be smaller than the third pair of inter-line spacing S3.
  • FIG. 4 is only a schematic diagram.
  • the first matching line 41 only includes the matching segment 411 .
  • the first matching line 41 is composed of a matching segment 411 .
  • first inter-line spacing S1 between the matching section 411 and the second clock signal line 22, and there is a second inter-line spacing S2 between the second data signal line 32 and the first clock signal line 21.
  • the first inter-line spacing S1 is equal to the second inter-line spacing S2.
  • the first matching line 41 and the second data signal line 32 can be symmetrically arranged on both sides of the first clock pair signal line 20.
  • the first matching line 41 includes a plurality of matching segments 411 that are spaced apart from each other.
  • the first matching line 41 encounters components such as devices and pins during its extension, the first matching line 41 is disconnected and skips over the components such as devices and pins to avoid the components such as devices and pins.
  • first inter-line spacing S1 between each matching section 411 and the second clock signal line 22, and a second inter-line spacing S2 between the second data signal line 32 and the first clock signal line 21.
  • the first inter-line spacing S1 and the second inter-line spacing S2 are all equal.
  • the layout solution of the data transmission lines provided in the embodiment of the present application can be applicable to any wiring scenario, and the layout of the first matching lines 41 can be simplified.
  • the first side of the first clock pair signal line 20 is arranged with the first data pair signal line 30, and the second side opposite to the first clock pair signal line 20 is arranged with the first matching line 41.
  • the existence of the first matching line 41 can change the parasitic parameters (such as the size of the parasitic capacitance) on the second side of the first clock pair signal line 20.
  • EMI is reduced by improving the consistency of parasitic parameters on both sides of the first clock pair signal line 20. Therefore, the change in the length of the first clock pair signal line 20 will hardly affect the EMI suppression effect. Therefore, the layout scheme of the data transmission line of the present application can significantly reduce the EMI caused by the larger common mode conversion of the longer time difference of the first clock pair signal line 20. And the cost of forming the first matching line 41 is extremely low, and does not affect the signal quality and the compatibility of docking with other devices.
  • the length (dimension in the extension direction) of the first clock pair signal line 20 is greater than 10 cm.
  • the EMI intensity of the data transmission line layout scheme provided by the embodiment of the present application is reduced compared with the layout scheme shown in FIG2 (for example, the EMI intensity is reduced by 5 dB on average). Compared with the scheme of using cables with better shielding effect, it can save costs.
  • the line widths of the first data signal line 31 , the second data signal line 32 , the first clock signal line 21 , and the second clock signal line 22 are equal.
  • the line width of the line refers to the line width at the non-turning part.
  • the first clock pair signal line 20 is a thicker line than the first data pair signal line 30. This is only to facilitate the determination of the position of the first clock signal line 20 in the layout scheme, and does not mean that the first clock pair signal line 20 is wider than the first data pair signal line 30.
  • the line width of the matching segment 411 in the first matching line 41 is equal to the line width of the second data signal line 32 .
  • the equality in the embodiment of the present application is not absolute equality, and approximate equality also belongs to the equality in the embodiment of the present application.
  • the process error of the width of the first data signal line 31, the second data signal line 32, the first clock signal line 21, the second clock signal line 22 and the first matching line 41 is ⁇ 30%.
  • the width of the first data signal line 31, the second data signal line 32, the first clock signal line 21, the second clock signal line 22 and the first matching line 41 differs by ⁇ 60% of the width of the second data signal line 32, which also belongs to the equal line width in the embodiment of the present application.
  • the line width of the avoidance section 412 may be equal to or different from the line width of the second data signal line 32 .
  • the line width of the matching segment 411 is equal to that of the second data signal line 32, the consistency of parasitic parameters on both sides of the first clock pair signal line 20 can be improved, so as to further reduce the differential common mode conversion in the first clock pair signal line 20 and improve the EMI suppression effect.
  • the first clock signal line 21 and the second clock signal line 22 have an arc angle ⁇ .
  • the first clock signal line 21 , the second clock signal line 22 , the first data signal line 31 , the second data signal line 32 , and the first matching line 41 have concentric arc angles ⁇ therebetween.
  • arc routing is used for turning transition.
  • the arc turning angle ⁇ between the first clock signal line 21, the second clock signal line 22, the first data signal line 31, the second data signal line 32 and the first matching line 41 is a concentric arc turning angle.
  • the first clock signal line 21 in the extension track of the first clock signal line 21, may have one or more turns, and the turns of the first clock signal line 21 may be circular arc turns.
  • the sizes of the circular arc angles ⁇ at the multiple turns may be equal, or the sizes of the circular arc angles ⁇ at the multiple turns may be unequal, and they may be reasonably set according to needs.
  • the first clock signal line 21 and the second clock signal line 22 are arranged in an arc when they turn.
  • the arc does not increase the line width at the corner when the arc turns, and the width of the arc at the turning and the line at the non-turning can be made equal or approximately equal, so that the impedance at each position of the first clock signal line 21 and the second clock signal line 22 is equal. In this way, the signal reflection caused by the impedance change can be reduced, and the differential common mode conversion is further reduced, thereby reducing EMI.
  • the arc corner ⁇ between the first clock signal line 21, the second clock signal line 22, the first data signal line 31, the second data signal line 32 and the first matching line 41 is a concentric arc angle ⁇ , which can make the first pair of line spacing S1 and the second pair of line spacing S2 at the corner equal, further improving the consistency of the parasitic parameters on both sides of the first clock pair signal line 20.
  • an angled routing can also be used for turning transition, and the embodiments of the present application do not limit this.
  • the routing turning point adopts an angled routing for turning transition, at the same turning point, the turning angles of the first clock signal line 21, the second clock signal line 22, the first data signal line 31, the second data signal line 32, and the first matching line 41 are equal.
  • two ends of the first matching line 41 are aligned with two ends of the second data signal line 32 .
  • connection line between the first end of the first match line 41 and the first end of the second data signal line 32 is perpendicular to the first match line 41 and the second data signal line 32.
  • connection line between the second end of the first match line 41 and the second end of the second data signal line 32 is perpendicular to the first match line 41 and the second data signal line 32.
  • the symmetry of the first matching line 41 and the second data signal line 32 on both sides of the first clock pair signal line 20 can be further improved to improve the consistency of the parasitic parameters on both sides of the first clock pair signal line 20.
  • the differential common mode conversion in the first clock pair signal line 20 is further reduced, and the EMI suppression effect is improved.
  • At least one end of the first matching line 41 is coupled to the reference ground voltage terminal GND.
  • Fig. 6 takes the example that both ends of the first matching line 41 are coupled to the reference ground voltage terminal GND.
  • the first matching line 41 By coupling at least one end of the first matching line 41 to the reference ground voltage terminal GND, the first matching line 41 can play a shielding role on the basis of adjusting the parasitic parameters.
  • a passive device 50 is coupled between at least one end of the first matching line 41 and the reference ground voltage terminal GND.
  • Fig. 7 takes the example that both ends of the first matching line 41 are coupled with the passive device 50 as an example.
  • the passive device 50 may include, for example, at least one of a resistor, a capacitor, an inductor, or a magnetic bead.
  • the passive devices 50 at both ends of the first matching line 41 may be the same, or they may be different.
  • the passive device 50 By coupling the passive device 50 to at least one end of the first matching line 41, the symmetry of the first matching line 41 and the second data signal line 32 on both sides of the first clock pair signal line 20 can be further improved by adjusting the passive device 50, so as to improve the consistency of the parasitic parameters on both sides of the first clock pair signal line 20.
  • the differential common mode conversion in the first clock pair signal line 20 is further reduced, and the EMI suppression effect is improved.
  • the layout scheme of the data transmission line further includes a second matching line 42 , and the second matching line 42 is located on a side of the first matching line 41 away from the second clock signal line 22 .
  • the first matching line 41 is located between the second matching line 42 and the second clock signal line 22 .
  • the structure of the second matching line 42 may refer to the above description of the structure of the first matching line 41 .
  • the second matching line 42 may include only a matching section, or may include a matching section and an avoidance section.
  • the first matching line 41 and the second matching line 42 may have the same structure, or may have different structures, which is not limited in the present embodiment.
  • Both ends of the second matching line 42 may be coupled to the reference ground voltage terminal GND, or both ends of the second matching line 42 may not be coupled to the reference ground voltage terminal GND.
  • Both ends of the second matching line 42 may be coupled to the passive device 50 , or both ends of the second matching line 42 may not be coupled to the passive device 50 .
  • the width of the second match line 42 is equal to the width of the first match line 41 .
  • the equality in the embodiment of the present application is not absolute equality, and approximate equality also belongs to the equality in the embodiment of the present application.
  • the process error of the width of the second matching line 42 and the first matching line 41 is ⁇ 30%, then the difference between the second matching line 42 and the first matching line 41 is ⁇ 60% of the width of the first matching line 41, which also belongs to the embodiment of the present application that the width of the second matching line 42 is equal to that of the first matching line 41.
  • the second matching line 42 and the first matching line 41 have a concentric arc angle ⁇ .
  • the layout scheme of the data transmission line may also include a third matching line, a fourth matching line and other multiple matching lines, which is not limited in the embodiment of the present application.
  • the parasitic parameters on the side of the second clock signal line 22 away from the first clock signal line 21 can be adjusted, and the consistency of the parasitic parameters on both sides of the first clock pair signal line 20 can be further improved. This can further reduce the differential common mode conversion in the first clock pair signal line 20 and improve the EMI suppression effect.
  • a first pair of inner line spacing M1 between the matching segment 411 and the second matching line 42 is equal to a second pair of inner line spacing M2 between the first data signal line 31 and the second data signal line 32 .
  • the equality in the embodiment of the present application is not absolute equality, and approximate equality also belongs to the equality in the embodiment of the present application.
  • the process error of the width of the first data signal line 31, the second data signal line 32, the first clock signal line 21, the second clock signal line 22 and the first matching line 41 itself is ⁇ 30%
  • the difference between the first pair of inner line spacing M1 and the second pair of inner line spacing M2 is ⁇ 60% of the first pair of inner line spacing M1, which also belongs to the embodiment of the present application that the first pair of inner line spacing M1 and the second pair of inner line spacing M2 are equal.
  • the consistency of parasitic parameters on both sides of the first clock pair signal line 20 can be further improved, so as to further reduce the differential common mode conversion in the first clock pair signal line 20 and improve the EMI suppression effect.
  • the third pair of inner line spacing M3 , the first pair of inner line spacing M1 , and the second pair of inner line spacing M2 between the first clock signal line 21 and the second clock signal line 22 are equal.
  • the consistency of parasitic parameters on both sides of the first clock pair signal line 20 can be further improved, so as to further reduce the differential common mode conversion in the first clock pair signal line 20 and improve the EMI suppression effect.
  • both ends of the first match line 41 and the second match line 42 are not coupled to the reference ground voltage terminal GND.
  • the first match line 41 and the second match line 42 form a set of second data pair signal lines for transmitting data signals.
  • the layout scheme of the data transmission line also includes a second clock pair signal line; the second clock pair signal line is arranged on the side of the second match line 42 away from the first match line 41.
  • both ends of the first matching line 41 and the second matching line 42 are not coupled to the reference ground voltage terminal GND, but are coupled to the HDMI connector and the processor.
  • the HDMI connector coupled to the second data pair signal line and the second clock pair signal line, and the HDMI connector coupled to the first data pair signal line 30 and the first clock pair signal line 20 are different HDMI connectors.
  • the electronic device to which the layout scheme provided by the embodiment of the present application is applied includes multiple HDMI interfaces.
  • the existing second data pair signal lines can be used as the first matching line 41 and the second matching line 42 in the layout solution provided in the embodiment of the present application.
  • EMI can be reduced without increasing the number of routing lines.
  • the first matching line 41 and the second matching line 42 are coupled to the first clock pair signal line 20 at the same HDMI connector.
  • the first matching line 41 and the second matching line 42 form a differential pair for transmitting low-speed signals.
  • the low-speed signal in the embodiment of the present application is, for example, a signal with a transmission speed below 50 Mbps.
  • the first matching line 41 and the second matching line 42 are used as a two-wire serial bus, coupled to the terminal 15 and the terminal 16 in the HDMI connector shown in FIG. 1D , for transmitting low-speed signals.
  • the existing two-wire serial bus can be used as the first matching line 41 and the second matching line 42 in the layout solution provided in the embodiment of the present application.
  • EMI can be reduced without increasing the number of wiring.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Dc Digital Transmission (AREA)

Abstract

一种数据传输走线的布局方案、主板及电子设备，数据传输走线包括第一时钟对信号线（20）、第一数据对信号线（30）以及第一匹配线（41）。第一时钟对信号线包括第一时钟信号线（21）和第二时钟信号线（22）；第一时钟对信号线用于传输时钟信号。第一数据对信号线包括第一数据信号线（31）和第二数据信号线（32）；第一数据对信号线用于传输数据信号。第一时钟对信号线位于第一匹配线和第一数据对信号线之间；第一时钟信号线与第二数据信号线相邻设置，第二时钟信号线与第一匹配线相邻设置；第一匹配线与第二时钟信号线之间的第一对间线间距与第二数据信号线和第一时钟信号线之间的第二对间线间距相等。该技术方案可以解决降低电子设备中的电磁干扰的问题。

Description

数据传输走线的布局方案、主板及电子设备
本申请要求于2022年10月25日提交国家知识产权局、申请号为202211312966.X、发明名称为“数据传输走线的布局方案、主板及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据传输技术领域，尤其涉及一种数据传输走线的布局方案、主板及电子设备。
背景技术
随着信息世界的发展，信号传输的速率越来越高，高清多媒体接口(high definition multimedia interface，HDMI)等带有时钟对的视频传输接口，因具有较高的音频/视频传输速度而被广泛的应用于电子设备中。而带有时钟对的视频传输接口中容易遇到电磁干扰(electromagnetic interference，EMI)超标的问题。
电磁干扰超标会导致电子设备被定性为不合格产品，因此，如何降低电子设备中的电磁干扰，是本领域技术人员持续关注的热点问题。
发明内容
本申请实施例提供一种数据传输走线的布局方案、主板及电子设备，用于解决如何降低电子设备中的电磁干扰的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种数据传输走线的布局方案，该布局方案例如可以应用于高清多媒体接口的走线布局中。数据传输走线包括第一时钟对信号线、第一数据对信号线以及第一匹配线。第一时钟对信号线包括第一时钟信号线和第二时钟信号线；第一时钟对信号线用于传输时钟信号。第一数据对信号线包括第一数据信号线和第二数据信号线；第一数据对信号线用于传输数据信号。本申请提供的数据传输走线的布局方案中，第一时钟对信号线位于第一匹配线和第一数据对信号线之间；第一时钟信号线与第二数据信号线相邻设置，第二时钟信号线与第一匹配线相邻设置；第一匹配线包括匹配段，匹配段与第二时钟信号线之间的第一对间线间距，与，第二数据信号线和第一时钟信号线之间的第二对间线间距相等。
本申请实施例提供的数据传输走线的布局方案中，第一时钟对信号线的第一侧排布有第一数据对信号线，第一时钟对信号线相对的第二侧排布有第一匹配线，第一匹配线的存在，可以改变第一时钟对信号线第二侧的寄生参数(例如寄生电容的大小)。而通过使匹配段到第二时钟信号线的第一对间线间距与第二数据信号线到第一时钟信号线的第二对间线间距相等，可以使第一时钟对信号线两侧的寄生参数的一致性提高。以减小第一时钟对信号线中的差共模转换，提高对EMI的抑制效果。另外，本申请实施例中，是通过提高第一时钟对信号线两侧的寄生参数的一致性来降低EMI的。因此，第一时钟对信号线的长度变化几乎不会影响EMI的抑制效果。所以，本申请的数据传输走线的布局方案能够明显降低第一时钟对信号线较长时差共模转换变大而引起的EMI。且形成第一匹配线的成本极低，不影响信号质量和其他设备对接的兼容性。
在一种可能的实现方式中，第一匹配线还包括避让段，避让段与匹配段连接，避让段与第二时钟信号线之间的第三对间线间距大于或者小于第一对间线间距。通过使第一匹配线在包括匹配段的基础上，还包括避让段，可使本申请实施例提供的数据传输走线的布局方案适用于任意布线场景中，对应用场景中器件和管脚等部件布局不做要求，在器件和管脚位置处通过避让段避开即可，可提高适用范围。
在一种可能的实现方式中，数据传输走线的布局方案还包括第二匹配线，第二匹配线位于第一匹配线远离第二时钟信号线一侧。通过在第二时钟信号线远离第一时钟信号线一侧设置第二匹配线，可以调整第二时钟信号线远离第一时钟信号线一侧的寄生参数，进一步提高第一时钟对信号线两侧的寄生参数的一致性。以进一步减小第一时钟对信号线中的差共模转换，提高对EMI的 抑制效果。
在一种可能的实现方式中，匹配段与第二匹配线之间的第一对内线间距，与，第一数据信号线和第二数据信号线之间的第二对内线间距相等。通过使第一对内线间距和第二对内线间距相等，可以进一步提高第一时钟对信号线两侧的寄生参数的一致性。以进一步减小第一时钟对信号线中的差共模转换，提高对EMI的抑制效果。
在一种可能的实现方式中，匹配段的线宽与第二数据信号线的线宽相等。通过将匹配段的线段与第二数据信号线的线宽设置为相等，可以提高第一时钟对信号线两侧的寄生参数的一致性。以进一步减小第一时钟对信号线中的差共模转换，提高对EMI的抑制效果。
在一种可能的实现方式中，第一时钟信号线、第二时钟信号线、第一数据信号线、第二数据信号线以及第一匹配线之间具有圆弧拐角。第一时钟信号线和第二时钟信号线拐弯时采用圆弧走线，圆弧走线拐弯不会增加弯角处的线宽，可以使拐弯处的圆弧走线与非拐弯处的走线的宽度相等或者近似相等，以使得第一时钟信号线和第二时钟信号线各位置处的阻抗相等。这样一来，可以减小因阻抗变化而带来的信号反射。进一步降低差共模转换，进而降低EMI。
在一种可能的实现方式中，第一时钟信号线、第二时钟信号线、第一数据信号线、第二数据信号线以及第一匹配线之间的圆弧角为同心圆弧角。第一时钟信号线21、第二时钟信号线22、第一数据信号线31、第二数据信号线32以及第一匹配线41之间的圆弧拐角θ为同心圆弧角θ，可以使得拐角处的第一对间线间距S1与第二对间线间距S2也相等，进一步提高第一时钟对信号线20两侧的寄生参数的一致性。
在一种可能的实现方式中，第一匹配线的两端与第二数据信号线的两端对齐。这样一来，可以进一步提高第一时钟对信号线两侧的第一匹配线和第二数据信号线的对称性，以提高第一时钟对信号线两侧的寄生参数的一致性。进一步减小第一时钟对信号线中的差共模转换，提高对EMI的抑制效果。
在一种可能的实现方式中，第一匹配线的至少一端与参考地电压端耦接。
在一种可能的实现方式中，第一匹配线的至少一端与参考地电压端之间耦接有无源器件。通过在第一匹配线的至少一端耦接无源器件，可以通过调整无源器件，来进一步提高第一时钟对信号线两侧的第一匹配线和第二数据信号线的对称性，以提高第一时钟对信号线两侧的寄生参数的一致性。进一步减小第一时钟对信号线中的差共模转换，提高对EMI的抑制效果。
在一种可能的实现方式中，无源器件包括电阻、电容、电感或者磁珠中的至少一种。这是一种结构简单的实现方式。
在一种可能的实现方式中，第一匹配线和第二匹配线构成一组第二数据对信号线，用于传输数据信号；数据传输走线的布局方案还包括第二时钟对信号线；第二时钟对信号线设置在第二匹配线远离第一匹配线一侧。这样一来，对于多HDMI接口的产品来讲，通过调整与不同HDMI连接器耦接的信号线的布局，可以使已有的第二数据对信号线充当本申请实施例提供的布局方案中的第一匹配线和第二匹配线。在不增加走线数量的基础上，可以降低EMI。
在一种可能的实现方式中，第一匹配线用于传输低速信号。这样一来，通过调整与HDMI连接器耦接的信号线的布局，可以使已有的两线式串行总线充当本申请实施例提供的布局方案中的第一匹配线和第二匹配线。在不增加走线数量的基础上，可以降低EMI。
在一种可能的实现方式中，数据传输走线的布局方案中包括多对第一数据对信号线，多对第一数据对信号线位于第一时钟对信号线的同一侧。多对数据对信号线的结构，也可以采用本申请的布局方案进行EMI的抑制。
在一种可能的实现方式中，第一时钟对信号线和第一数据对信号线均用于耦接于处理器和输出传输接口连接器之间。这是一种可能的应用方式。
在一种可能的实现方式中，第一时钟对信号线和第一数据对信号线均用于与高清多媒体接口连接器耦接。这是一种可能的应用方式。
在一种可能的实现方式中，第一时钟对信号线的长度大于10cm。在第一时钟对信号线的长度约为10cm的情况下，采用本申请实施例提供的数据传输走线的布局方案，EMI的强度有所下 降(例如EMI强度平均下降5dB)，且成本较低。
本申请实施例的第二方面，提供一种主板，包括线路板、处理器和输出传输接口连接器，线路板上包括数据传输走线，数据传输走线采用第一方面任一项的数据传输走线的布局方案布局；数据传输走线中的第一时钟对信号线和第一数据对信号线均耦接于处理器和输出传输接口连接器之间。
本申请实施例提供的主板包括第一方面的数据传输走线的布局方案，其有益效果与第一方面的数据传输走线的布局方案的有益效果相同，此处不再赘述。
本申请实施例的第三方面，提供一种电子设备，包括屏蔽壳和主板，主板位于屏蔽壳内，主板为第二方面的主板。
本申请实施例提供的电子设备包括第二方面的主板，其有益效果与第二方面的主板的有益效果相同，此处不再赘述。
附图说明
图1A为本申请实施例提供的一种电子设备的应用场景示意图；
图1B为本申请实施例提供的一种电子设备的框架示意图；
图1C为本申请实施例提供的一种电子设备中主板的结构示意图；
图1D为本申请实施例提供的一种HDMI连接器的结构示意图；
图1E为本申请实施例提供的一种HDMI连接器与处理器之间走线的布局示意图；
图2为本申请实施例示意的一种数据对信号线和时钟对信号线的布局方式示意图；
图3为本申请实施例提供的一种数据传输走线的布局方式示意图；
图4为本申请实施例提供的另一种数据传输走线的布局方式示意图；
图5为本申请实施例提供的又一种数据传输走线的布局方式示意图；
图6为本申请实施例提供的又一种数据传输走线的布局方式示意图；
图7为本申请实施例提供的又一种数据传输走线的布局方式示意图；
图8为本申请实施例提供的又一种数据传输走线的布局方式示意图；
图9为本申请实施例提供的又一种数据传输走线的布局方式示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请实施例提供一种电子设备，电子设备具有音频/视频传输的功能。电子设备例如可以包括网络视频录像机(network video recorder，NVR)、数字视频录像机(Digital video recorder，DVR)、数字硬盘录像机(XVR)、编码器(DVS)、一体机、工控机、网关、行业主机等后 端产品。电子设备也可以是机顶盒等具有音频/视频传输需求的电子设备。
示例的，如图1A所示，前端摄像头装置将采集到的图像、音频等信息传输至电子设备，电子设备在将多组画面传输至显示设备上进行显示，显示设备上例如可以同时显示9宫格或者12宫格监控画面。
示例的，如图1B所示，示意一种网络视频录像机NVR。网络视频录像机NVR包括处理器，处理器例如可以是中央处理器(central processing unit，CPU)。网络视频录像机NVR还包括与中央处理器CPU耦接的内存、闪存(flash)、硬盘数据接口、输入输出(I/O)接口、以太网接口、视频图形阵列(video graphics array，VGA)接口以及高清多媒体接口(high definition multimedia interface，HDMI)。
处理器、内存、闪存(flash)、硬盘数据接口、输入输出(I/O)接口、以太网接口以及高清多媒体接口HDMI例如可以设置在印刷电路板(printed circuit board，PCB)上，作为网络视频录像机NVR的主板。
网络视频录像机NVR还可以包括屏蔽壳，主板设置在屏蔽壳中。屏蔽壳例如可以对电磁干扰(electromagnetic interference，EMI)进行屏蔽，屏蔽壳的材料例如可以是金属。
例如，中央处理器CPU用于处理视频数据的压缩编码、数据接收发送等网络视频录像机NVR的业务，内存用于提供中央处理器CPU运行时所需的临时数据存放空间，闪存用于提供永久性的存放网络视频录像机NVR固件和系统配置信息的存储空间，硬盘数据接口用于连接硬盘、并将视频数据传输至硬盘进行保存，输入输出接口用于提供I/O触发的输入输出，以太网接口用于连接以太网，VGA接口用于连接VGA显示器、通过VGA显示器显示视频图像，高清多媒体接口HDMI用于连接显示设备、并通过显示设备显示视频图像。
高清多媒体接口HDMI处的高清多媒体接口连接器通过时钟对信号线及数据对信号线与处理器耦接。
示例的，如图1C所示，电子设备的主板上包括PCB、数据传输端口连接器以及处理器。数据传输端口连接器和处理器设置在PCB上。
数据传输端口连接器例如为HDMI连接器、移动产业处理器接口(mobile industry processor interface，MIPI)连接器等。数据传输接口可以用于传输音频、视频、文件等数据信号。
图1C中以数据传输端口连接器为HDMI连接器为例进行示意。HDMI连接器与处理器之间通过走线耦接，以完成信号传输。耦接于HDMI连接器与处理器之间的走线可以集成在PCB上。
示例的，HDMI连接器中具有多个端子，图1D中以HDMI连接器具有19个端子为例进行示意。
端子1和端子3用于传输数据对信号(数据2+和数据2-)，端子2用于与数据对的屏蔽层耦接。端子4和端子6用于传输数据对信号(数据1+和数据1-)，端子5用于与数据对的屏蔽层耦接。端子7和端子9用于传输数据对信号(数据0+和数据0-)，端子8用于与数据对的屏蔽层耦接。端子10和端子12用于传输时钟对信号(时钟+和时钟-)，端子11用于与时钟对屏蔽层耦接。端子13作为控制器端子CEC。端子14作为保留端子。端子15和端子16作为两线式串行总线(inter-integrated circuit，I2C)的连接端子，端子15作为两线式串行总线的双向数据线端子SDA，端子16作为两线式串行总线的时钟线端子SCL。端子17作为接地端子。端子18作为电源端子。端子19作为热插拔识别端子。
每个端子分别与走线耦接，但只有部分端子通过走线与处理器耦接。
示例的，如图1E所示，端子7与端子9通过数据对信号线0与处理器耦接，端子4和端子6通过数据对信号线1与处理器耦接，端子1和端子3通过数据对信号线2与处理器耦接，端子10和端子12通过时钟对信号线与处理器耦接。端子2、端子5、端子8以及端子1作为屏蔽端子，与屏蔽线耦接，屏蔽线不与处理器耦接。
HDMI连接器中的端子1至端子19中，端子1、端子3、端子4、端子6、端子7、端子9、端子10以及端子12通过走线与处理器耦接。
带有时钟对和数据对的数据传输接口虽然可以使电子设备具有较高的信号传输速率，但是时钟对信号传输过程中通常容易产生电磁干扰(electromagnetic interference，EMI)。
时钟对信号产生电磁干扰的位置可以分成两个部分，一部分是从电子设备内的PCB上发出的电磁干扰，另一部分是由电子设备外的连接线缆发出的电磁干扰。
电磁干扰超标的主要原因是PCB上时钟对的布线存在非对称性，从而引起时钟信号的差共模转换，生成共模信号。共模信号干扰幅度大、频率高，还可以通过走线产生辐射，所造成的电磁干扰较大。由于PCB上时钟对的走线长度往往比电子设备外的线缆的长度小得多，且PCB通常被约束在金属屏蔽壳内，因此共模信号在PCB上产生的电磁干扰并不是造成电磁干扰超标的主要原因。共模信号通过电子设备外的线缆带出电子设备所产生的电磁干扰是造成电磁干扰超标的主要原因。但造成电磁干扰超标的本质在于PCB上时钟对的布线存在非对称性。
在一些技术中，如图2所示，PCB上包括时钟对信号线和数据对信号线，时钟对信号线和数据对信号线用于传输音频、视频、文档等信号。通过在时钟对信号线和时钟对信号线上设置绕线部分，来使时钟对信号线长度对内等长、数据对信号线和时钟对信号线长度相等或者近似相等。
绕蛇形线保持时钟对信号线的对内等长，可以使时钟对中极性相反的两路信号同时达到，减小共模信号的产生，进而降低EMI。
绕蛇形线保持时钟对信号线的对内等长可以提高时钟对布线的对称性，但是数据对信号线始终位于时钟对信号线一侧。因此，即使时钟对信号线对内等长，时钟对信号线两侧也会存在寄生电容等。这就导致在走线较长时(如超过10cm的高清多媒体接口HDMI走线)，由于时钟对信号线周围环境微小的不对称性的积累，也会造成较大的差共模转换，从而引起EMI问题。
在另一些技术中，通过调整主板的相关参数来降低EMI。
例如，降低主板输出管脚的驱动能力、使用时钟展频。降低主板的驱动能力，可以使方波信号的上升沿变缓，减小信号的高频分量，从而降低EMI。使用时钟展频，能让时钟频率以工作频点为中心在一频率范围内抖动，从而降低集中在工作频点及其倍频点上的辐射能量，进而降低该频点处的EMI。
降低主板的驱动能力和时钟展频虽然能降低EMI，但同时也降低了信号质量和与其他设备对接的兼容性。
在又一些技术中，增加抑制辐射的部件或材料降低EMI。
例如，使用共模抑制电感、使用屏蔽效果更好的线缆。共模抑制电感能将PCB上因走线的不对称性而生成的共模信号转化为热量损耗掉，降低传导到外部线缆上的共模信号，进而降低EMI。使用屏蔽效果更高的线缆能有效防止EMI的泄露，进而降低EMI。
共模抑制电感和屏蔽效果更好的线缆虽然能降低EMI，但同时也会增加成本。
基于此，本申请实施例提供一种数据传输走线的布局方案，用于通过调整走线的布局，来降低时钟对信号线带来的EMI。
如图3所示，数据传输走线包括第一时钟对信号线20、第一数据对信号线30以及第一匹配线41。
第一时钟对信号线20包括第一时钟信号线21和第二时钟信号线22，第一时钟对信号线20用于传输时钟信号。
第一数据对信号线30包括第一数据信号线31和第二数据信号线32。第一数据对信号线30用于传输数据信号。
当然，数据传输走线中可以包括一对第一数据对信号线30，数据传输走线中也可以包括多对第一数据对信号线30。数据传输走线中包括多对第一数据对信号线30的情况下，多对第一数据对信号线30位于第一时钟对信号线20的同一侧。图3中以数据传输走线中包括多对第一数据对信号线30为例进行示意。
在一些实施例中，第一时钟对信号线20和第一数据对信号线30均用于与HDMI连接器耦接。
示例的，第一时钟对信号线20作为图1E中的时钟对信号线，耦接于HDMI连接器中的端子 10和端子12、与处理器之间。
多对第一数据对信号线30为三对第一数据对信号线30。一对第一数据对信号线30作为图1E中的数据对信号线2，耦接于HDMI连接器中的端子1和端子3、与处理器之间。一对第一数据对信号线30作为图1E中的数据对信号线1，耦接于HDMI连接器中的端子4和端子6、与处理器之间。一对第一数据对信号线30作为图1E中的数据对信号线0，耦接于HDMI连接器中的端子7和端子9与处理器之间。
第一匹配线41用于调整第一时钟对信号线20周围的寄生参数。
本申请实施例中，第一匹配线41可以与HDMI连接器耦接，第一匹配线41也可以不与HDMI连接器耦接。
数据传输走线的布局方案包括第一匹配线41和第一数据对信号线30位于第一时钟对信号线20相对的两侧，或者理解为，第一时钟对信号线20位于第一匹配线41和第一数据对信号线30之间。
示例的，如图3所示，沿数据传输走线的排布方向，依次排布的为第一数据信号线31、第二数据信号线32、第一数据信号线31、第二数据信号线32、第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22以及第一匹配线41。
那么，第一时钟信号线21与第二数据信号线32相邻设置，第二时钟信号线22与第一匹配线41相邻设置。
在一些实施例中，如图4所示，第一匹配线41包括匹配段411和避让段412，避让段412与匹配段411连接。
此处释明的是，避让段412在第一匹配线41中出现的位置、出现的次数、以及避让段412的形状，视数据传输走线周围的器件及管脚的布局情况而定，避让段412用于在第一匹配线41的延伸过程中，避开上述器件、管脚等部件。
通过使第一匹配线41在包括匹配段411的基础上，还包括避让段412，可使本申请实施例提供的数据传输走线的布局方案适用于任意布线场景中，对应用场景中器件和管脚等部件布局不做要求，在器件和管脚位置处通过避让段412避开即可，可提高适用范围。
在一些实施例中，如图4所示，匹配段411与第二时钟信号线22之间具有第一对间线间距S1，避让段412与第二时钟信号线22之间具有第三对间线间距S3，第二数据信号线32和第一时钟信号线21之间具有第二对间线间距S2。
第一对间线间距S1与第二对间线间距S2相等，第一对间线间距S1与第三对间线间距S3不相等。在避让段412各位置处与第二时钟信号线22之间具有多个不同的第三对间线间距S3的情况下，每个第三对间线间距S3与第一对间线间距S1均不相等，多个不同的第三对间线间距S3可以相等，也可以不相等。
本申请实施例中的相等不是绝对相等，近似相等也属于本申请实施例中的相等。示例的，本申请实施例中，第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22以及第一匹配线41自身宽度的工艺误差为±30％，那么，第二对间线间距S2与第一对间线间距S1之间相差第一对间线间距S1的±60％，也属于本申请实施例中的第一对间线间距S1与第二对间线间距S2相等。
当然，第一对间线间距S1可以大于第三对间线间距S3，第一对间线间距S1也可以小于第三对间线间距S3，图4中仅是一种示意。
在另一些实施例中，第一匹配线41只包括匹配段411。
示例的，如图3所示，第一匹配线41由一段匹配段411构成。
匹配段411与第二时钟信号线22之间具有第一对间线间距S1，第二数据信号线32和第一时钟信号线21之间具有第二对间线间距S2，第一对间线间距S1与第二对间线间距S2相等。
这样一来，可实现第一匹配线41和第二数据信号线32对称的设置在第一时钟对信号线20两侧。而第一时钟对信号线20两侧信号线的对称性越高，使得第一时钟对信号线20两侧的寄生参数的一致性越高，对差共模转换的抑制效果越好，对EMI的降低效果越好。
或者，示例的，如图5所示，第一匹配线41包括多段间隔设置的匹配段411。
那么，在第一匹配线41的延伸过程中遇到器件及管脚等部件时，第一匹配线41断开，跳过上述器件及管脚等部件，以避开上述器件、管脚等部件。
每个匹配段411与第二时钟信号线22之间具有第一对间线间距S1，第二数据信号线32和第一时钟信号线21之间具有第二对间线间距S2，各个第一对间线间距S1与第二对间线间距S2均相等。
这样一来，既可以是本申请实施例提供的数据传输走线的布局方案适用于任意布线场景中，又可以简化第一匹配线41的布局。
本申请实施例提供的数据传输走线的布局方案中，第一时钟对信号线20的第一侧排布有第一数据对信号线30，第一时钟对信号线20相对的第二侧排布有第一匹配线41，第一匹配线41的存在，可以改变第一时钟对信号线20第二侧的寄生参数(例如寄生电容的大小)。而通过使匹配段411到第二时钟信号线22的第一对间线间距S1与第二数据信号线32到第一时钟信号线21的第二对间线间距S2相等，可以使第一时钟对信号线20两侧的寄生参数的一致性提高。以减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
另外，本申请实施例中，是通过提高第一时钟对信号线20两侧的寄生参数的一致性来降低EMI的。因此，第一时钟对信号线20的长度变化几乎不会影响EMI的抑制效果。所以，本申请的数据传输走线的布局方案能够明显降低第一时钟对信号线20较长时差共模转换变大而引起的EMI。且形成第一匹配线41的成本极低，不影响信号质量和其他设备对接的兼容性。
在一些实施例中，第一时钟对信号线20的长度(延伸方向上的尺寸)大于10cm。
经实测显示，在第一时钟对信号线20的长度约为10cm的情况下，采用本申请实施例提供的数据传输走线的布局方案与采用图2所示的布局方案相比，EMI的强度有所下降(例如EMI强度平均下降5dB)。与使用屏蔽效果较好的线缆的方案相比，可节省成。
在一些实施例中，第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22的线宽相等。
可以理解的是，在走线延伸过程中，若遇走线拐弯，折角拐弯会增加折角处的线宽。因此，本申请实施例中，走线的线宽是指非拐弯处的线宽。
需要指出的是，本申请实施例提供的附图中，第一时钟对信号线20相比第一数据对信号线30为加粗线，这只是为了便于确定第一时钟信号线20在布局方案中的位置，并不代表第一时钟对信号线20比第一数据对信号线30宽。
在一些实施例中，第一匹配线41中匹配段411的线宽与第二数据信号线32的线宽相等。
本申请实施例中的相等不是绝对相等，近似相等也属于本申请实施例中的相等。示例的，本申请实施例中，第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22以及第一匹配线41自身宽度的工艺误差为±30％。那么，第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22以及第一匹配线41的宽度相差第二数据信号线32的±60％，也属于本申请实施例中的线宽相等。
在第一匹配线41还包括避让段412的情况下，避让段412的线宽与第二数据信号线32的线宽可以相等，也可以不相等。
通过将匹配段411的线段与第二数据信号线32的线宽设置为相等，可以提高第一时钟对信号线20两侧的寄生参数的一致性。以进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，如图6所示，第一时钟信号线21、第二时钟信号线22具有圆弧拐角θ。
在一些实施例中，第一时钟信号线21、第二时钟信号线22、第一数据信号线31、第二数据信号线32以及第一匹配线41之间具有同心圆弧拐角θ。
也就是说，在走线拐弯处，采用圆弧走线进行拐弯过渡。在同一个拐弯处，第一时钟信号线21、第二时钟信号线22、第一数据信号线31、第二数据信号线32以及第一匹配线41之间的圆弧拐角θ为同心圆弧拐角。
以第一时钟信号线21为例，在第一时钟信号线21延伸轨迹中，第一时钟信号线21可以有一个或多个拐弯，第一时钟信号线21的拐弯处可以采用圆弧拐弯。在第一时钟信号线21的延伸轨迹上具有多个拐弯的情况下，多个拐弯处的圆弧拐角θ的大小可以相等，多个拐弯处的圆弧拐角θ的大小也可以不相等，根据需要合理设置即可。
第一时钟信号线21和第二时钟信号线22拐弯时采用圆弧走线，圆弧走线拐弯不会增加弯角处的线宽，可以使拐弯处的圆弧走线与非拐弯处的走线的宽度相等或者近似相等，以使得第一时钟信号线21和第二时钟信号线22各位置处的阻抗相等。这样一来，可以减小因阻抗变化而带来的信号反射。进一步降低差共模转换，进而降低EMI。
而第一时钟信号线21、第二时钟信号线22、第一数据信号线31、第二数据信号线32以及第一匹配线41之间的圆弧拐角θ为同心圆弧角θ，可以使得拐角处的第一对间线间距S1与第二对间线间距S2也相等，进一步提高第一时钟对信号线20两侧的寄生参数的一致性。
当然，在走线拐弯处也可以采用折角走线进行拐弯过渡，本申请实施例对此不做限定。示例的，在走线拐弯采用折角走线进行拐弯过渡的情况下，在同一个拐弯处，第一时钟信号线21、第二时钟信号线22、第一数据信号线31、第二数据信号线32以及第一匹配线41拐弯的折角相等。
在一些实施例中，沿走线的延伸方向，第一匹配线41的两端与第二数据信号线32的两端对齐。
或者理解为，第一匹配线41的第一端与第二数据信号线32的第一端的连线垂直于第一匹配线41和第二数据信号线32。第一匹配线41的第二端与第二数据信号线32的第二端的连线垂直于第一匹配线41和第二数据信号线32。
这样一来，可以进一步提高第一时钟对信号线20两侧的第一匹配线41和第二数据信号线32的对称性，以提高第一时钟对信号线20两侧的寄生参数的一致性。进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，如图6所示，第一匹配线41的至少一端与参考地电压端GND耦接。图6中以第一匹配线41的两端均与参考地电压端GND耦接为例进行示意。
通过使第一匹配线41的至少一端与参考地电压端GND耦接，可以是第一匹配线41在调整寄生参数的基础上，起到屏蔽作用。
在一些实施例中，如图7所示，第一匹配线41的至少一端与参考地电压端GND之间耦接有无源器件50。图7中以第一匹配线41的两端均耦接有无源器件50为例进行示意。
无源器件50例如可以包括电阻、电容、电感或者磁珠中的至少一种。第一匹配线41两端的无源器件50可以相同，第一匹配线41两端的无源器件50也可以不相同。
通过在第一匹配线41的至少一端耦接无源器件50，可以通过调整无源器件50，来进一步提高第一时钟对信号线20两侧的第一匹配线41和第二数据信号线32的对称性，以提高第一时钟对信号线20两侧的寄生参数的一致性。进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，如图8所示，数据传输走线的布局方案还包括第二匹配线42，第二匹配线42位于第一匹配线41远离第二时钟信号线22一侧。
或者理解为，第一匹配线41位于第二匹配线42和第二时钟信号线22之间。
第二匹配线42的结构可以参考上述关于第一匹配线41的结构的相关描述。
第二匹配线42可以仅包括匹配段，第二匹配线42也可以包括匹配段和避让段。第一匹配线41和第二匹配线42的结构可以相同，第一匹配线41和第二匹配线42的结构也可以不相同，本申请实施例对此不做限定。
第二匹配线42的两端可以与参考地电压端GND耦接，第二匹配线42的两端也可以不与参考地电压端GND耦接。
第二匹配线42的两端可以耦接有无源器件50，第二匹配线42的两端也可以不耦接无源器件50。
在一些实施例中，第二匹配线42的宽度与第一匹配线41的宽度相等。
本申请实施例中的相等不是绝对相等，近似相等也属于本申请实施例中的相等。示例的，本申请实施例中，第二匹配线42和第一匹配线41自身宽度的工艺误差为±30％，那么，第二匹配线42和第一匹配线41之间相差第一匹配线41宽度的±60％，也属于本申请实施例中的第二匹配线42的宽度与第一匹配线41相等。
在一些实施例中，第二匹配线42与第一匹配线41具有同心圆弧拐角θ。
当然，数据传输走线的布局方案还可以包括第三匹配线、第四匹配线等多个匹配线，本申请实施例对此不做限定。
通过在第二时钟信号线22远离第一时钟信号线21一侧设置第二匹配线42或者更多的匹配线，可以调整第二时钟信号线22远离第一时钟信号线21一侧的寄生参数，进一步提高第一时钟对信号线20两侧的寄生参数的一致性。以进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，如图8所示，匹配段411与第二匹配线42之间的第一对内线间距M1，与，第一数据信号线31和第二数据信号线32之间的第二对内线间距M2相等。
本申请实施例中的相等不是绝对相等，近似相等也属于本申请实施例中的相等。示例的，本申请实施例中，第一数据信号线31、第二数据信号线32、第一时钟信号线21、第二时钟信号线22以及第一匹配线41自身宽度的工艺误差为±30％，那么，第一对内线间距M1与第二对内线间距M2之间相差第一对内线间距M1的±60％，也属于本申请实施例中的第一对内线间距M1与第二对内线间距M2相等。
通过使第一对内线间距M1和第二对内线间距M2相等，可以进一步提高第一时钟对信号线20两侧的寄生参数的一致性。以进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，继续参考图8，第一时钟信号线21和第二时钟信号线22之间的第三对内线间距M3、第一对内线间距M1以及第二对内线间距M2三者相等。
这样一来，可以进一步提高第一时钟对信号线20两侧的寄生参数的一致性。以进一步减小第一时钟对信号线20中的差共模转换，提高对EMI的抑制效果。
在一些实施例中，如图9所示，第一匹配线41和第二匹配线42的两端不与参考地电压端GND耦接。
示例的，第一匹配线41和第二匹配线42构成一组第二数据对信号线，用于传输数据信号。数据传输走线的布局方案还包括第二时钟对信号线；第二时钟对信号线设置在第二匹配线42远离第一匹配线41一侧。
在这种情况下，第一匹配线41和第二匹配线42的两端不与参考地电压端GND耦接，而是与HDMI连接器和处理器耦接。当然，与第二数据对信号线和第二时钟对信号线耦接的HDMI连接器，和与第一数据对信号线30和第一时钟对信号线20耦接的HDMI连接器，为不同的HDMI连接器。应用本申请实施例提供的布局方案的电子设备中包括多个HDMI接口。
这样一来，对于多HDMI接口的产品来讲，通过调整与不同HDMI连接器耦接的信号线的布局，可以使已有的第二数据对信号线充当本申请实施例提供的布局方案中的第一匹配线41和第二匹配线42。在不增加走线数量的基础上，可以降低EMI。
或者示例的，第一匹配线41和第二匹配线42与第一时钟对信号线20耦接于同于HDMI连接器。第一匹配线41和第二匹配线42构成差分对，用于传输低速信号。
本申请实施例中的低速信号，例如为传输速度在50兆以下的信号。
示例的，第一匹配线41和第二匹配线42作为两线式串行总线，与图1D所示的HDMI连接器中的端子15和端子16耦接，用于传输低速信号。
这样一来，通过调整与HDMI连接器耦接的信号线的布局，可以使已有的两线式串行总线充当本申请实施例提供的布局方案中的第一匹配线41和第二匹配线42。在不增加走线数量的基础上，可以降低EMI。
需要指出的是，在第一时钟对信号线20、第一数据对信号线30、第一匹配线41以及第二匹配线42的延伸轨迹中，并不要求整个延伸轨迹中都满足本申请实施例描述的上述特征，只要部分线段满足上述描述，则均属于本申请实施例的保护范围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种数据传输走线的布局方案，其特征在于，包括：
    第一时钟对信号线，包括第一时钟信号线和第二时钟信号线；所述第一时钟对信号线用于传输时钟信号；
    第一数据对信号线，包括第一数据信号线和第二数据信号线；所述第一数据对信号线用于传输数据信号；
    第一匹配线；所述第一时钟对信号线位于所述第一匹配线和所述第一数据对信号线之间；
    所述第一时钟信号线与所述第二数据信号线相邻设置，所述第二时钟信号线与所述第一匹配线相邻设置；所述第一匹配线包括匹配段，所述匹配段与所述第二时钟信号线之间的第一对间线间距，与，所述第二数据信号线和所述第一时钟信号线之间的第二对间线间距相等；
    所述第一时钟对信号线和所述第一数据对信号线均用于耦接于处理器和输出传输接口连接器之间。
  2. 根据权利要求1所述的数据传输走线的布局方案，其特征在于，所述第一匹配线还包括避让段，所述避让段与所述匹配段连接，所述避让段与所述第二时钟信号线之间的第三对间线间距大于或者小于所述第一对间线间距。
  3. 根据权利要求1或2所述的数据传输走线的布局方案，其特征在于，所述数据传输走线的布局方案还包括第二匹配线，所述第二匹配线位于所述第一匹配线远离所述第二时钟信号线一侧。
  4. 根据权利要求3所述的数据传输走线的布局方案，其特征在于，所述匹配段与第二匹配线之间的第一对内线间距，与，所述第一数据信号线和所述第二数据信号线之间的第二对内线间距相等。
  5. 根据权利要求1-4任一项所述的数据传输走线的布局方案，其特征在于，所述匹配段的线宽与所述第二数据信号线的线宽相等。
  6. 根据权利要求1-5任一项所述的数据传输走线的布局方案，其特征在于，所述第一时钟信号线、所述第二时钟信号线、所述第一数据信号线、所述第二数据信号线以及所述第一匹配线之间具有同心圆弧拐角。
  7. 根据权利要求1-6任一项所述的数据传输走线的布局方案，其特征在于，所述第一匹配线的两端与所述第二数据信号线的两端对齐。
  8. 根据权利要求1-7任一项所述的数据传输走线的布局方案，其特征在于，所述第一匹配线的至少一端与参考地电压端耦接。
  9. 根据权利要求8所述的数据传输走线的布局方案，其特征在于，所述第一匹配线的至少一端与所述参考地电压端之间耦接有无源器件。
  10. 根据权利要求9所述的数据传输走线的布局方案，其特征在于，所述无源器件包括电阻、电容、电感或者磁珠中的至少一种。
  11. 根据权利要求3-7任一项所述的数据传输走线的布局方案，其特征在于，所述第一匹配线和所述第二匹配线构成一组第二数据对信号线，用于传输数据信号；
    所述数据传输走线的布局方案还包括第二时钟对信号线；所述第二时钟对信号线设置在所述第二匹配线远离所述第一匹配线一侧。
  12. 根据权利要求1-7任一项所述的数据传输走线的布局方案，其特征在于，所述第一匹配线用于传输低速信号。
  13. 根据权利要求1-12任一项所述的数据传输走线的布局方案，其特征在于，数据传输走线的布局方案中包括多对所述第一数据对信号线，多对所述第一数据对信号线位于所述第一时钟对信号线的同一侧。
  14. 根据权利要求1-13任一项所述的数据传输走线的布局方案，其特征在于，所述第一时钟对信号线和所述第一数据对信号线均用于与高清多媒体接口连接器耦接。
  15. 根据权利要求1-14任一项所述的数据传输走线的布局方案，其特征在于，所述第一时 钟对信号线的长度大于10cm。
  16. 一种主板，其特征在于，包括线路板、处理器和输出传输接口连接器，所述线路板上包括数据传输走线，所述数据传输走线采用权利要求1-15任一项所述的数据传输走线的布局方案布局；所述数据传输走线中的第一时钟对信号线和第一数据对信号线均耦接于所述处理器和所述输出传输接口连接器之间。
  17. 一种电子设备，其特征在于，包括屏蔽壳和主板，所述主板位于所述屏蔽壳内，所述主板为权利要求16所述的主板。
PCT/CN2023/103272 2022-10-25 2023-06-28 数据传输走线的布局方案、主板及电子设备 WO2024087697A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211312966.X 2022-10-25
CN202211312966.XA CN117977301A (zh) 2022-10-25 2022-10-25 数据传输走线的布局方案、主板及电子设备

Publications (1)

Publication Number Publication Date
WO2024087697A1 true WO2024087697A1 (zh) 2024-05-02

Family

ID=90829888

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103272 WO2024087697A1 (zh) 2022-10-25 2023-06-28 数据传输走线的布局方案、主板及电子设备

Country Status (2)

Country Link
CN (1) CN117977301A (zh)
WO (1) WO2024087697A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201654774U (zh) * 2010-05-14 2010-11-24 珠海世纪鼎利通信科技股份有限公司 一种基于usb2.0的数据传输设备
CN102369581A (zh) * 2009-03-30 2012-03-07 松下电器产业株式会社 柔性线缆和传输系统
JP2015231006A (ja) * 2014-06-06 2015-12-21 株式会社Ｊｖｃケンウッド プリント配線板
CN206619376U (zh) * 2016-12-26 2017-11-07 厦门天马微电子有限公司 显示面板及包含其的装置
CN107613632A (zh) * 2017-09-11 2018-01-19 宇龙计算机通信科技(深圳)有限公司 一种电路板的布线方法、电路板及移动终端
CN111447732A (zh) * 2020-05-22 2020-07-24 浪潮电子信息产业股份有限公司 一种pcb差分对走线的阻抗匹配方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102369581A (zh) * 2009-03-30 2012-03-07 松下电器产业株式会社 柔性线缆和传输系统
CN201654774U (zh) * 2010-05-14 2010-11-24 珠海世纪鼎利通信科技股份有限公司 一种基于usb2.0的数据传输设备
JP2015231006A (ja) * 2014-06-06 2015-12-21 株式会社Ｊｖｃケンウッド プリント配線板
CN206619376U (zh) * 2016-12-26 2017-11-07 厦门天马微电子有限公司 显示面板及包含其的装置
CN107613632A (zh) * 2017-09-11 2018-01-19 宇龙计算机通信科技(深圳)有限公司 一种电路板的布线方法、电路板及移动终端
CN111447732A (zh) * 2020-05-22 2020-07-24 浪潮电子信息产业股份有限公司 一种pcb差分对走线的阻抗匹配方法

Also Published As

Publication number Publication date
CN117977301A (zh) 2024-05-03

Similar Documents

Publication Publication Date Title
US9934176B2 (en) Transceiver multiplexing over USB type-C interconnects
US9226387B2 (en) Network communication device
US8886852B2 (en) Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices
US20120033369A1 (en) Motherboard with universal series bus connector
TWI593329B (zh) 配線方法、電子裝置與連接器
US8021194B2 (en) Controlled impedance display adapter
CN202307087U (zh) 显示装置
WO2018171241A1 (zh) 双屏蔽层的usb连接器
KR20120011430A (ko) 무선 통신 장치를 위한 유에스비 연결장치
EP2876746B1 (en) High-frequency signal double-layer flat cable adapter card
CN201654774U (zh) 一种基于usb2.0的数据传输设备
WO2024087697A1 (zh) 数据传输走线的布局方案、主板及电子设备
WO2021259156A1 (zh) 一种数据线
WO2017101329A1 (zh) 一种基于ffc排线传输usb信号的方法和系统
US20210399925A1 (en) Signal transmission device capable of transmitting multiple data streams
TWI704734B (zh) 外接式電連接器及電腦系統
CN103531977A (zh) 数据传输线
TWI763001B (zh) 可傳輸複數組資料流之訊號傳輸裝置
WO2022267308A1 (zh) 母座连接器及其制作方法
TW201414103A (zh) 高速傳輸介面電路及其設計方法
TWI662748B (zh) 差動訊號電連接組件及可傳送差動訊號的電路板
US20170168982A1 (en) Method and system for transmitting usb signal based on ffc
US20060067023A1 (en) Method and system for ESD protection of balanced circuit board lines
WO2021228188A1 (zh) 数据传输电缆及相关设备
US8751695B2 (en) Hybrid storage device and electronic system using the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23881286

Country of ref document: EP

Kind code of ref document: A1