WO2024082466A1 - 存储系统及其操作方法、存储器控制器和存储器 - Google Patents

存储系统及其操作方法、存储器控制器和存储器 Download PDF

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Publication number
WO2024082466A1
WO2024082466A1 PCT/CN2023/071798 CN2023071798W WO2024082466A1 WO 2024082466 A1 WO2024082466 A1 WO 2024082466A1 CN 2023071798 W CN2023071798 W CN 2023071798W WO 2024082466 A1 WO2024082466 A1 WO 2024082466A1
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Prior art keywords
page data
data
memory
group
prefix command
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PCT/CN2023/071798
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English (en)
French (fr)
Inventor
谭华
冯宇飞
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长江存储科技有限责任公司
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Priority to US18/323,948 priority Critical patent/US20240126478A1/en
Publication of WO2024082466A1 publication Critical patent/WO2024082466A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the semiconductor field, and in particular, to a storage system and an operating method thereof, a memory controller, and a memory.
  • the storage cells in NAND memory include single-level cells that store 1 bit of data and multi-level cells that store at least 2 bits of data. Although NAND memory with single-level cells has a faster write speed and higher reliability, it has a small storage capacity and high cost; NAND memory with multi-level cells has a relatively slower write speed and relatively lower reliability, but has a large storage capacity and low cost.
  • NAND memory is required to have both the fast writing speed and high reliability of single-level cells and the large storage capacity and low cost of multi-level cells. Therefore, how to flexibly configure NAND memory to achieve multiple storage cell modes has become a technical problem that needs to be solved urgently.
  • an operating method of a storage system wherein the storage system comprises a memory, the memory comprises a storage cell array and a peripheral circuit coupled to the storage cell array, the storage cell array comprises a storage cell capable of storing m bits of information, where m is a positive integer greater than 1; the operating method comprises:
  • the peripheral circuit determines the n+1th logical page according to the received prefix command and the received n sets of logical page data.
  • Group logical page data wherein n is a positive integer, and n+1 is a positive integer less than or equal to m;
  • the n groups of logic page data and the (n+1)th group of logic page data are written into the memory cell array to generate 2 n different data states in the memory cell array.
  • a memory controller is provided, the memory controller being coupled to a memory, the memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array comprising a memory cell capable of storing m bits of information, where m is a positive integer greater than 1; the memory controller being configured as follows:
  • a prefix command and n groups of logical page data are sent to the peripheral circuit, so that the peripheral circuit determines the n+1th group of logical page data according to the prefix command and the n groups of logical page data, and generates 2n different data states in the storage cell array; wherein n is a positive integer, and n+1 is a positive integer less than or equal to m.
  • a memory including:
  • a storage cell array comprising storage cells capable of storing m bits of information
  • a peripheral circuit is coupled to the memory cell array; wherein,
  • the peripheral circuit is configured to determine the n+1th group of logical page data according to the received prefix command and the received n groups of logical page data; wherein n is a positive integer and n+1 is a positive integer less than or equal to m;
  • the peripheral circuit is further configured to write the n groups of logic page data and the (n+1)th group of logic page data into the memory cell array to generate 2 n different data states in the memory cell array.
  • a storage system including:
  • the memory controller as described in the second aspect of the embodiment of the present disclosure is coupled to the memory and is configured to control the memory.
  • the peripheral circuit can determine the n+1th group of logical page data according to the received prefix command and the received n groups of logical page data, and write the n groups of logical page data and the n+1th group of logical page data into the storage cell array, 2n different data states can be generated in the storage cell array, that is, part of the storage space of the memory can be used as at least one of SLC, MLC, TLC, and QLC.
  • the NAND memory can be flexibly configured to realize a variety of storage unit modes, and can simultaneously have the advantages of fast writing speed, high reliability, large storage capacity and low cost.
  • FIG1 is a schematic diagram showing different data states of a memory according to an exemplary embodiment
  • FIG2 is a flow chart showing a writing method of a storage system according to an example embodiment
  • FIG3 is a schematic diagram of a storage system according to an example embodiment
  • FIG4 is a schematic diagram showing a write state of a memory according to an example embodiment
  • FIG5 is a flow chart showing an operation method of a storage system according to an embodiment of the present disclosure
  • FIG6 is a schematic diagram showing a memory executing a write command according to an embodiment of the present disclosure
  • FIG7 is a timing diagram of a memory performing a write operation according to an embodiment of the present disclosure.
  • FIG8 is a schematic diagram showing a write state of a memory according to an embodiment of the present disclosure.
  • FIG9 is a partial schematic diagram of a peripheral circuit of a memory according to an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a memory according to an embodiment of the present disclosure.
  • FIG11 is a cross-sectional view of a NAND storage string according to an embodiment of the present disclosure.
  • FIG12 is a block diagram of a memory including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure
  • FIG13 is a schematic diagram of a storage system according to an embodiment of the present disclosure.
  • FIG14a is a schematic diagram of a memory card according to an embodiment of the present disclosure.
  • FIG. 14 b is a schematic diagram of a solid state drive (SSD) according to an embodiment of the present disclosure.
  • Fig. 1 is a schematic diagram of different data states of a memory according to an exemplary embodiment.
  • the number of bits of a memory cell increases from 1 bit to 2 bits, 3 bits, and 4 bits, and accordingly, the memory cell evolves from a single-level cell (SLC) to a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).
  • SLC single-level cell
  • MLC multi-level cell
  • TLC triple-level cell
  • QLC quad-level cell
  • the data states in the memory increase from 2 to 4, 8, and 16, thereby increasing the capacity of the memory and reducing the cost.
  • a storage cell of the SLC memory stores 1 bit of data.
  • the data states of the SLC memory include 1 erased state and 1 programmed state.
  • the erased state is denoted as E
  • the programmed state is denoted as P.
  • the threshold voltage of the programmed state P is greater than the threshold voltage of the erased state E.
  • the storage cell of the MLC memory stores 2 bits of data.
  • the data states of the MLC memory include 1 erased state and 3 programmed states.
  • the erased state is denoted as E
  • the programmed states are denoted as P1, P2, and P3 from the 1st state to the 3rd state, respectively. From the P1 state to the P3 state, the threshold voltage gradually increases.
  • the storage cell of the TLC memory stores 3 bits of data.
  • the data states of the TLC memory include 1 erased state and 7 programmed states.
  • the erased state is denoted as E
  • the programmed states are denoted as P1, P2, P3, P4, P5, P6 and P7 from the 1st state to the 7th state, respectively. From the P1 state to the P7 state, the threshold voltage gradually increases.
  • the storage unit of the QLC memory stores 4 bits of data
  • the data state of the QLC memory includes 1 erased state and 15 programmed states, wherein the erased state is denoted as E, and the programmed state is denoted as The 15th state is recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 in sequence. From the P1 state to the P15 state, the threshold voltage gradually increases.
  • the number of stacked layers in memory continues to increase. When the number of stacked layers is greater than or equal to 64 layers, there will be no MLC memory. Although the main 3D NAND product is TLC memory at present, when the number of stacked layers is greater than or equal to 300 layers, the main 3D NAND product will be QLC memory.
  • FIG2 is a flow chart of a storage system writing method according to an example embodiment
  • FIG3 is a schematic diagram of a storage system 10 according to an example embodiment.
  • the writing method includes at least the following steps:
  • the controller 11 receives lower logical page (Lower Page, LP) data and upper logical page (Upper Page, UP) data;
  • the scrambler 13 is enabled to randomize the LP data and the UP data;
  • ECC Error Correction Code
  • the central processing unit (CPU) on the host side runs the firmware (Firmware, FW) to perform an exclusive-NOR (NXOR) operation on the LP data and the UP data to generate middle logical page (Middle Page, MP) data; here, the running firmware can be stored in the memory.
  • firmware Firmware, FW
  • NXOR exclusive-NOR
  • MP middle logical page
  • S108 disable the scrambler 13 and the ECC encoder 14, and transfer the LP/MP/UP data to a memory, for example, a page buffer;
  • S109 Send a write command (eg, 10h) to start executing a write operation, for example, writing the LP/MP/UP data from the page buffer to the memory cell array 12 .
  • a write command eg, 10h
  • FIG4 is a schematic diagram of a write state of a memory according to an example embodiment.
  • 3 bits of data can be stored in the memory cell of the TLC memory, and 8 different data states, namely, the erased state E and the programmed states P1 to P7, can be generated.
  • LP/MP/UP data is written into the memory cell array 12
  • 3 bits of data can be stored in the memory cell of the TLC memory
  • 4 different data states namely, the erased state E and the programmed states P2, P4, and P6 can be generated. That is, by executing the method shown in FIG2 , at least part of the storage space in the TLC memory can be used as MLC to meet the application requirements of the MLC memory.
  • this method needs to be executed by the CPU on the host side, which makes the operation complicated, and requires running firmware to use the CPU to perform XOR operations on the original data (for example, LP data and UP data) and generate MP data, resulting in low efficiency.
  • an embodiment of the present disclosure provides a storage system and an operating method thereof.
  • FIG5 is a flow chart of an operation method of a storage system according to an embodiment of the present disclosure.
  • the storage system includes a memory, the memory includes a storage cell array and a peripheral circuit coupled to the storage cell array, the storage cell array includes a storage cell capable of storing m bits of information, m being a positive integer greater than 1; as shown in FIG5 , the operation method includes at least the following steps:
  • S201 The peripheral circuit determines the n+1th logical page according to the received prefix command and the received n sets of logical page data.
  • S202 writing n groups of logic page data and the (n+1)th group of logic page data into a memory cell array to generate 2n different data states in the memory cell array.
  • the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array.
  • the memory cell array includes multiple memory cells, each memory cell can store m bits of information.
  • the peripheral circuit includes a logic control unit, a command register, a cache register, and a data register.
  • the logic control unit in the peripheral circuit can read the prefix command stored in the command register, and determine the n+1th group of logic page data according to the read prefix command and the n groups of logic page data, and store the n+1th group of logic page data in the cache register or the data register.
  • the n groups of logic page data include: at least one of LP data, MP data, UP data, and additional page XP data.
  • the peripheral circuit can perform a logic operation on the n groups of logic page data to generate the n+1th group of logic page data.
  • step S202 after receiving the write command, n groups of logical page data and the (n+1)th group of logical page data are sequentially written into the memory cell array, and 2n different data states are generated in the memory cell array.
  • the memory is an MLC memory.
  • the peripheral circuit determines the MP data based on the received prefix command and LP data, and writes the LP data and the MP data into the memory cell array to generate two different data states in the memory cell array.
  • the memory is a TLC memory.
  • the peripheral circuit determines the UP data based on the received prefix command, LP data and MP data, and writes the LP data, MP data and UP data into the memory cell array to generate 4 different data states in the memory cell array.
  • the memory is a TLC memory.
  • the peripheral circuit determines the MP data according to the received prefix command and the LP data. At least LP data and MP data are written into the memory cell array to generate two different data states in the memory cell array.
  • the memory is a QLC memory.
  • the peripheral circuit determines the XP data based on the received prefix command, LP data, MP data, and UP data, and writes the LP data, MP data, UP data, and XP data into the memory cell array to generate 8 different data states in the memory cell array.
  • the memory is a QLC memory.
  • the peripheral circuit determines the UP data based on the received prefix command and the LP data and the MP data, and writes at least the LP data, the MP data and the UP data into the memory cell array to generate 4 different data states in the memory cell array.
  • the memory is a QLC memory.
  • the peripheral circuit determines the MP data based on the received prefix command and LP data, and writes at least the LP data and the MP data into the memory cell array to generate two different data states in the memory cell array.
  • the peripheral circuit can determine the n+1th group of logical page data based on the received prefix command and the received n groups of logical page data, and write the n groups of logical page data and the n+1th group of logical page data into the storage cell array, 2n different data states can be generated in the storage cell array, that is, part of the storage space of the memory can be used as at least one of SLC, MLC, TLC, and QLC.
  • the NAND memory can be flexibly configured to realize a variety of storage cell modes, and can simultaneously have the advantages of fast writing speed, high reliability, large storage capacity and low cost.
  • the operation method of determining the n+1th group of logical page data through the peripheral circuit inside the memory in the embodiment of the present disclosure is simple, which is beneficial to improving the operating efficiency of the memory while realizing multiple storage unit modes.
  • the operation method provided in the embodiment of the present disclosure using prefix commands is more user-friendly and compatible with the existing NAND protocol, which helps to save development costs.
  • the prefix command when n+1 is equal to m, includes: a first sub-prefix command A; wherein the first sub-prefix command A indicates to perform an XOR operation on n groups of logical page data;
  • the above step S201 includes: the peripheral circuit performs an XOR operation on n groups of logic page data according to the first sub-prefix command A to generate the mth group of logic page data;
  • the above step S202 includes: writing n groups of logic page data and the mth group of logic page data into the memory cell array to store m bits of information in the memory cells.
  • the memory controller sends a first sub-prefix command A and LP data, MP data and UP data to the peripheral circuit, and the peripheral circuit performs an exclusive OR (XOR) operation on the LP data, MP data and UP data according to the first sub-prefix command A to generate XP data;
  • a write command (for example, 80h) is sent to the peripheral circuit, and the peripheral circuit starts to write the LP data, MP data, UP data and XP data into the storage cell array to store 4 bits of information in the storage cell and generate 8 different data states, that is, part of the storage space in the QLC memory is used as TLC, as shown in 2 in Figure 6.
  • FIG. 7(b) shows a write timing diagram for using part of the storage space in the QLC memory as TLC, which includes a data type signal Cycle Type and a data signal DQx.
  • the first sub-prefix command A is sent first, and then the 80h command is sent after the XP data is determined, and then the address signals C1, C2, R1, R2 and R3 are sent in the address cycle.
  • the address signal can be used to determine the logical address of the storage unit to be written, and the LP data, MP data, UP data and XP data are written to the storage unit.
  • the logical address includes the logical unit number (lun), plane, storage block (block) and storage page (page) address.
  • the LP data is a sequence of (1111111100000000)
  • the MP data is a sequence of (1111000000001111)
  • the UP data is a sequence of (1100001111000011).
  • the peripheral circuit performs an XOR operation on the LP data, the MP data, and the UP data according to the first sub-prefix command A to generate an XP data sequence of (1100110011001100), writes the LP data, the MP data, the UP data, and the XP data into the memory cell array, and generates 8 data states in the memory cell array, as shown in FIG8(b), which are an erase state E (1111), a programming state P2 (1100), a programming state P4 (1001), Programming state P6 (1010), programming state P8 (0011), programming state P10 (0000), programming state P12 (0101) and programming state P14 (0110).
  • the LP data is a sequence of (1111111100000000)
  • the MP data is a sequence of (1111000000001111)
  • the UP data is a sequence of (1100001111000011) for illustration, so as to convey the present disclosure to those skilled in the art, but the present disclosure is not limited thereto.
  • the LP data, the MP data, and the UP data may also be other sequences composed of "1" and "0", and it is only necessary to ensure that after the XP data is generated by executing the first prefix command A on the LP data, the MP data, and the UP data, any 8 different data states from the erased state E to the programmed state P15 are generated in the QLC memory.
  • the LP data is a sequence of (1111111100000000)
  • the MP data is a sequence of (1111000000001111)
  • the UP data is a sequence of (1100001111000011).
  • the threshold voltage difference M2 between two adjacent data states is substantially the same, that is, the read margin is distributed more evenly, which is beneficial to ensuring the accuracy of the read operation when used as TLC.
  • the peripheral circuit when n+1 is equal to m, performs an XOR operation on n groups of logical page data according to the first sub-prefix command to generate the mth group of logical page data, and writes the n groups of logical page data and the mth group of logical page data into the storage cell array.
  • 2n different data states can be generated in the storage cell array.
  • the memory is QLC
  • part of the storage space of the QLC memory can be used as TLC, so that the memory has at least two storage cell modes, which is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memories.
  • the peripheral circuit can also perform an XOR operation or a copy operation on n groups of logic page data according to the prefix command to generate the mth group of logic page data.
  • the selection can be made according to the actual situation, and the present disclosure has no special limitation on this.
  • the above operation method before executing step S202, further includes: storing n groups of logic page data in a plurality of data registers respectively; wherein each data register is used to store a group of logic page data; storing the mth group of logic page data in a cache register.
  • the peripheral circuit includes a page cache, The data register or cache register may be located in the page buffer and used to cache logical page data.
  • LP data (1111111100000000) is stored in data register 1
  • MP data (1111000000001111) is stored in data register 2
  • UP data (1111000000001111) is stored in data register 3.
  • the XP data is stored in the cache register.
  • the LP data stored in data register 1 the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are written into the storage cell array in sequence.
  • the prefix command when the difference between m and n is 2, includes: a second sub-prefix command B; wherein the second sub-prefix command B indicates to perform an XOR operation on n groups of logical page data;
  • the above step S201 includes: the peripheral circuit performs an exclusive-or-not operation on n groups of logic page data according to the second sub-prefix command B to generate the n+1th group of logic page data;
  • the above operation method further includes: writing the mth group of logic page data into the memory cell array to store m bits of information in the memory cell; wherein the mth group of logic page data is an all-0 sequence or an all-1 sequence.
  • the memory controller sends the second sub-prefix command B and the LP data and the MP data to the peripheral circuit, and the peripheral circuit performs an exclusive-or-not (NXOR) operation on the LP data and the MP data according to the second sub-prefix command B to generate UP data; sends a write command (e.g., 80h) to the peripheral circuit, and the peripheral circuit starts to write the LP data, MP data, UP data, and XP data into the memory cell array to store 4 bits of information in the memory cell and generate 4 different data states, that is, part of the storage space in the QLC memory is used as MLC, as shown in 3 in FIG6.
  • the XP data is a sequence of all 0s or a sequence of all 1s.
  • FIG7(c) shows a write timing diagram of using part of the storage space in the QLC memory as MLC.
  • the second sub-prefix command B is sent first, and the 80h command is sent after the UP data is determined. Then, the address signals C1, C2, R1, R2 and R3 are sent in the address cycle.
  • the logical address of the storage unit to be written can be determined through the address signal, and the LP data, MP data, UP data and XP data are written into the storage unit.
  • the LP data is a sequence of (1111111100000000), and the MP data is a sequence of (1111000000001111).
  • the peripheral circuit performs an XOR operation on the LP data and the MP data according to the second sub-prefix command B to generate a sequence of UP data of (1111000011110000), and a sequence of XP data of (1111111111111111).
  • the LP data, MP data, UP data, and XP data are written into the memory cell array, and four data states are generated in the memory cell array, as shown in Figure 8c, namely, the erased state E (1111), the programmed state P4 (1001), the programmed state P8 (0011), and the programmed state P12 (0101).
  • the LP data is a sequence of (1111111100000000)
  • the MP data is a sequence of (1111000000001111)
  • the XP data is a sequence of (1111111111111111) for the purpose of conveying the present disclosure to those skilled in the art, but the present disclosure is not limited thereto.
  • the LP data and the MP data may also be other sequences composed of "1" and "0" or the XP data may also be a sequence of all 0s, and it is only necessary to ensure that after the second prefix command B is executed on the LP data and the MP data to generate UP data, any four different data states from the erased state E to the programmed state P15 are generated in the QLC memory.
  • LP data is a sequence of (1111111100000000)
  • MP data is a sequence of (1111000000001111)
  • XP data is a sequence of (1111111111111111) .
  • the threshold voltage difference M3 between two adjacent data states is substantially the same, that is, the read margin is distributed more evenly, which is beneficial to ensuring the accuracy of the read operation when used as MLC.
  • the peripheral circuit when the difference between m and n is 2, performs an XOR operation on n groups of logical page data according to the second sub-prefix command to generate the n+1th group of logical page data, and writes the n groups of logical page data, the n+1th group of logical page data and the mth group of logical page data into the storage cell array.
  • 2n different data states can be generated in the storage cell array.
  • the memory is QLC
  • part of the storage space of the QLC memory can be used as MLC, so that the memory has at least two storage cell modes, which is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memories.
  • the peripheral circuit when the difference between m and n is 2, can also perform an XOR operation or a copy operation on the n groups of logic page data according to the prefix command to generate the n+1th group of logic page data.
  • the selection can be made according to the actual situation, and the present disclosure has no special limitation on this.
  • the above-mentioned operation method before executing step S202, also includes: storing the n groups of logical page data and the n+1th group of logical page data in multiple data registers respectively; wherein each data register is used to store a group of logical page data; before writing the mth group of logical page data into the storage cell array, the above-mentioned operation method also includes: storing the mth group of logical page data in the cache register.
  • LP data (1111111100000000) is stored in data register 1
  • MP data (1111000000001111) is stored in data register 2
  • XP data (1111111111111111111) is stored in the cache register.
  • UP data (1111000011110000) is stored in data register 3.
  • the LP data stored in data register 1 the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are written into the storage cell array in sequence.
  • the prefix command when the difference between m and n is 3, includes: a third sub-prefix command C; wherein the third sub-prefix command C indicates that the n+1th group of logical page data is equal to the nth group of logical page data;
  • the above step S201 includes: the peripheral circuit performs a copy operation on n groups of logic page data according to the third sub-prefix command C to generate the (n+1)th group of logic page data;
  • the above operation method also includes: writing the n+2th group of logical page data and the mth group of logical page data into the storage cell array to store m bits of information in the storage cell; wherein the n+2th group of logical page data and the mth group of logical page data are all-0 sequences or all-1 sequences.
  • the memory controller sends the third sub-prefix command C and LP data to the peripheral circuit, and the peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C to generate MP data, that is, the MP data is the same as the LP data; sends a write command (for example, 80h) to the peripheral circuit, and the peripheral circuit starts to write the LP data, MP data, UP data and XP data into the memory cell array to store 4 bits of information in the memory cell and generate 2 different data states, that is, the QLC storage Part of the storage space in the memory is used as SLC, as shown in 4 in Figure 6.
  • the UP data and XP data are all 0 sequences or all 1 sequences.
  • FIG7(d) shows a write timing diagram of using part of the storage space in the QLC memory as the SLC.
  • the third sub-prefix command C is sent first, and the 80h command is sent after the MP data is determined. Then, the address signals C1, C2, R1, R2, and R3 are sent in the address cycle.
  • the logical address of the storage unit to be written can be determined through the address signal, and the LP data, MP data, UP data, and XP data are written into the storage unit.
  • the LP data is a sequence of (11111111000000000)
  • the peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C, generating MP data of a sequence of (1111111100000000) and UP data of a sequence of (1111111111111111), and XP data of a sequence of (1111111111111111), and writing the LP data, MP data, UP data, and XP data into the memory cell array generates two data states in the memory cell array, as shown in Figure 8(d), which are the erased state E (1111) and the programmed state P8 (0011), respectively.
  • the LP data is a sequence of (1111111100000000)
  • the UP data is a sequence of (1111111111111111)
  • the XP data is a sequence of (1111111111111111) for easy communication of the present disclosure to those skilled in the art, but the present disclosure is not limited thereto.
  • the LP data may also be other sequences composed of "1" and "0" or the UP data and the XP data may also be all-0 sequences, and it is only necessary to ensure that after the MP data is generated by executing the third prefix command C on the LP data, any two different data states from the erase state E to the programming state P15 are generated in the QLC memory.
  • the LP data is a sequence of (11111111100000000)
  • the UP data is a sequence of (1111111111111111)
  • the XP data is a sequence of (1111111111111111) as shown in FIG8(d).
  • the threshold voltage difference M4 between the erased state E and the programmed state P8 is large, which is beneficial to ensure the accuracy of the read operation when used as MLC.
  • the peripheral circuit when the difference between m and n is 3, performs a copy operation on n groups of logic page data according to the third sub-prefix command to generate the n+1th group of logic page data and to copy the nth group of logic page data.
  • the page data, the n+1th group of logical page data, the n+2th group of logical page data and the mth group of logical page data are written into the storage cell array. While storing m bits of information in the storage cell, 2n different data states can be generated in the storage cell array.
  • the memory is QLC
  • part of the storage space of the QLC memory can be used as SLC, so that the memory has at least two storage cell modes, which is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memories.
  • the operation method before executing step S202, the operation method further includes: storing the nth group of logical page data and the n+1th group of logical page data in a plurality of data registers respectively; wherein each data register is used to store a group of logical page data;
  • the operation method further includes: storing the n+2th group of logical page data into a data register; and storing the mth group of logical page data into a cache register.
  • LP data (111111111000000000) is stored in data register 1
  • UP data (1111111111111111) is stored in data register 3
  • XP data (1111111111111111) is stored in the cache register.
  • MP data (11111111100000000) is stored in data register 2.
  • the LP data stored in data register 1 the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are written into the storage cell array in sequence.
  • the above operation method before determining the n+1th group of logical page data, the above operation method further includes:
  • the logic control unit in the peripheral circuit can read the command register and determine whether the command register stores a prefix command (for example, the first sub-prefix command or the second sub-prefix command or the third sub-prefix command) according to the reading result.
  • a prefix command for example, the first sub-prefix command or the second sub-prefix command or the third sub-prefix command
  • the peripheral circuit determines the n+1th group of logic page data according to the prefix command and the n groups of logic page data, that is, part of the storage space of the QLC memory is used as TLC, MLC or SLC.
  • the 80h command is sent to the peripheral circuit, and the peripheral circuit writes m groups of logical page data into the memory cell array to store m bits of information in the memory cell and generate 2 m different data states in the memory cell array.
  • the storage space where the m groups of logical page data are written is used as QLC, as shown in 1 in FIG6 .
  • LP data is a sequence of (1111111100000000)
  • MP data is a sequence of (1111000000001111)
  • UP data is a sequence of (1100001111000011)
  • XP data is a sequence of (1001100110011001).
  • the peripheral circuit writes LP data, MP data, UP data, and XP data into the memory cell array according to the 80h command, and generates 16 data states in the memory cell array, as shown in FIG8(a), which are erased state, reset state, and reset state.
  • the peripheral circuit by judging whether the peripheral circuit receives a prefix command and generating a judgment result, determining whether to use part of the storage space of the QLC memory as at least one of SLC, MLC, TLC according to the judgment result, it is beneficial to accurately configure the NAND memory.
  • the above operation method further includes: when the data register is damaged, the peripheral circuit stores a set of logical page data in the n sets of logical page data to the spare data register. For example, as shown in FIG. 9 , when the data register 1 is damaged, the peripheral circuit stores the LP data to the spare data register 4; and/or, when the data register 2 is damaged, the peripheral circuit stores the MP data to the spare data register 5, etc.
  • spare data registers are illustrated in this example, and the number of spare data registers in the memory is not limited to two, but can also be one, three or even more, and the present disclosure does not limit this. In practical applications, the number of spare data registers can be reasonably set according to needs.
  • An embodiment of the present disclosure also provides a memory controller, which is coupled to a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array includes a memory cell capable of storing m bits of information, where m is a positive integer greater than 1; the memory controller is configured to: send a prefix command and n groups of logical page data to the peripheral circuit, so that the peripheral circuit determines the n+1th group of logical page data based on the prefix command and the n groups of logical page data, and generates 2n different data states in the memory cell array; wherein n is a positive integer, and n+1 is a positive integer less than or equal to m.
  • the prefix command includes: a first sub-prefix command, the first sub-prefix command being used to instruct to perform an XOR operation on n groups of logical page data;
  • the memory controller is specifically configured to: send a first sub-prefix command and n groups of logical page data to a peripheral circuit, so that the peripheral circuit performs an XOR operation on the n groups of logical page data according to the first sub-prefix command to generate the mth group of logical page data; wherein n+1 equals m.
  • the prefix command includes: a second sub-prefix command, the second sub-prefix command being used to instruct to perform an XOR operation on n groups of logical page data;
  • the memory controller is specifically configured to: send the second sub-prefix command and n groups of logic page data to the peripheral circuit, so that the peripheral circuit performs an XOR operation on the n groups of logic page data according to the second sub-prefix command to generate the n+1th group of logic page data;
  • the memory controller is further configured to: send the mth group of logic page data to the peripheral circuit; wherein the mth group of logic page data is an all-0 sequence or an all-1 sequence, and the difference between m and n is 2.
  • the prefix command includes: a third sub-prefix command, the third sub-prefix command being used to indicate that the n+1th group of logical page data is equal to the nth group of logical page data;
  • the memory controller is specifically configured to: send the third sub-prefix command and n groups of logic page data to the peripheral circuit, so that the peripheral circuit performs a copy operation on the n groups of logic page data according to the third sub-prefix command to generate the n+1th group of logic page data;
  • the memory controller is also configured to: send the n+2th group of logic page data and the mth group of logic page data to the peripheral circuit; wherein the n+2th group of logic page data and the mth group of logic page data are all-0 sequences or all-1 sequences, and the difference between m and n is 3.
  • the memory controller is further configured to: after sending the prefix command, send a write command to the peripheral circuit, so that the peripheral circuit writes at least n groups of logical page data and the n+1th group of logical page data into the memory cell array according to the write command.
  • FIG10 is a schematic diagram of a memory 100 according to an embodiment of the present disclosure.
  • the memory 100 includes:
  • a memory cell array 101 the memory cell array 101 includes a memory cell 106 capable of storing m bits of information;
  • the peripheral circuit 102 is coupled to the memory cell array 101; wherein,
  • the peripheral circuit 102 is configured to determine the n+1th group of logical page data according to the received prefix command and the received n groups of logical page data; wherein n is a positive integer and n+1 is a positive integer less than or equal to m;
  • the peripheral circuit 102 is further configured to write n groups of logical page data and the (n+1)th group of logical page data into the memory cell array 101 to generate 2 n different data states in the memory cell array 101 .
  • the memory cell array 101 may be a NAND flash memory cell array, wherein the memory cell array 101 is provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically.
  • each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically.
  • Each memory cell 106 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 106.
  • Each memory cell 106 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.
  • each memory cell 106 is a single-level cell having two possible data states and can therefore store 1 bit of data.
  • a first data state "0" may correspond to a first voltage range
  • a second data state "1" may correspond to a second voltage range.
  • each memory cell 106 is a cell capable of storing more than 1 bit of data in more than four data states.
  • 2 bits can be stored per cell (also known as a multi-level cell), 3 bits can be stored per cell (also known as a triple-level cell), or 4 bits can be stored per cell (also known as a quad-level cell).
  • Each multi-level cell can be programmed to take on a range of possible nominal storage values. In one example, if each multi-level cell stores 2 bits of data, the multi-level cell can be written to assume one of three possible data states from the erased state by writing one of three possible nominal storage values to the cell.A fourth nominal storage value can be used for the erased state.
  • each NAND memory string 108 may include a source select transistor (SST) 110 at its source terminal and a drain select transistor (DST) 112 at its drain terminal.
  • the source select transistor 110 and the drain select transistor 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and write operations.
  • sources of NAND memory strings 108 in the same memory block 104 are coupled via the same source line (Source Line, SL) 114.
  • Source Line, SL Source Line
  • all NAND memory strings 108 in the same memory block 104 have an array common source (Array Common Source, ACS).
  • the drain select transistor 112 of each NAND memory string 108 is coupled to a corresponding bit line 116 from which data may be read or written via an output bus (not shown).
  • each NAND memory string 108 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 112) or a deselect voltage (e.g., 0V) to a corresponding drain select gate via one or more drain select gate lines 111, where the selection voltage is used to turn on the drain select transistor 112 and the deselect voltage is used to turn off the drain select transistor 112.
  • a selection voltage e.g., higher than the threshold voltage of the drain select transistor 112
  • a deselect voltage e.g., 0V
  • each NAND memory string 108 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the source select transistor 110) or a deselect voltage (e.g., 0V) to a corresponding source select gate via one or more source select gate lines 115, where the selection voltage is used to turn on the source select transistor 110 and the deselect voltage is used to turn off the source select transistor 110.
  • a selection voltage e.g., higher than the threshold voltage of the source select transistor 110
  • a deselect voltage e.g., 0V
  • the NAND memory string 108 can be organized into a plurality of memory blocks 104, each of which can have a common source line 114 (e.g., coupled to ground).
  • each memory block 104 is a basic data unit for an erase operation, i.e., all memory cells 106 on the same memory block 104 are erased at the same time.
  • erase operations may be performed at the half-block level, at the quarter-block level, or at levels having any suitable number of blocks or any suitable fraction of a block.
  • Memory cells 106 of adjacent NAND memory strings 108 may be coupled by word lines 118, which select which row of memory cells 106 is affected by read and write operations.
  • each word line 118 is recorded as a memory page 120.
  • the size of a memory page 120 in bits may be related to the number of NAND memory strings 108 coupled by the word line 118 in a memory block 104.
  • Each word line 118 may include a plurality of control gates (gate electrodes) at each memory cell 106 in a corresponding memory page 120 and a gate line coupling the control gates. It is understood that a memory cell row is a plurality of memory cells 106 located in the same memory page 120.
  • FIG 11 is a cross-sectional view of a NAND memory string 108 according to an embodiment of the present disclosure.
  • the NAND memory string 108 may extend vertically through a memory stack layer 204 above a substrate 202.
  • the substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.
  • the memory stack 204 may include alternating gate conductive layers 206 and gate dielectric layers 208.
  • the number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101.
  • the gate conductive layer 206 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
  • each gate conductive layer 206 may include a metal layer, for example, a tungsten layer.
  • each gate conductive layer 206 may include a doped polysilicon layer.
  • Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, and may extend laterally at the top of the memory stack 204 as a drain select gate line 111, extend laterally at the bottom of the memory stack 204 as a source select gate line 115, or extend laterally between the drain select gate line 111 and the source select gate line 115 as a word line 118.
  • the NAND memory string 108 includes a channel structure 212 extending vertically through the memory stack layer 204.
  • the channel structure 212 includes a A channel hole of a semiconductor material (e.g., as a semiconductor channel 220) and (one or more) dielectric materials (e.g., as a storage film 218).
  • the semiconductor channel 220 includes silicon, for example, polysilicon.
  • the storage film 218 is a composite dielectric layer including a tunneling layer 226, a storage layer 224 (also referred to as a "charge trapping/storage layer"), and a barrier layer 222.
  • the channel structure 212 may have a cylindrical shape (e.g., a column shape).
  • the semiconductor channel 220, the tunneling layer 226, the storage layer 224, and the barrier layer 222 are arranged radially in this order from the center of the cylinder toward the outer surface of the cylinder.
  • the tunneling layer 226 may include silicon oxide, silicon oxynitride, or any combination thereof.
  • the storage layer 224 may include silicon nitride, silicon oxynitride, or any combination thereof.
  • the barrier layer 222 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof.
  • the memory film 218 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
  • a well 214 (e.g., a P-well and/or an N-well) is formed in the substrate 202, and the source terminal of the NAND memory string 108 contacts the well 214.
  • the NAND memory string 108 also includes a channel plug 216 at the drain terminal of the NAND memory string 108. It should be understood that although not shown in FIG11 , additional components of the memory cell array 101 may be formed, including but not limited to gate line gaps/source contacts, local contacts, interconnect layers, etc.
  • the peripheral circuit 102 may be coupled to the memory cell array 101 via the bit lines 116, the word lines 118, the source lines 114, the source select gate lines 115, and the drain select gate lines 111.
  • the peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 101 by applying a voltage signal and/or a current signal to each memory cell 106 and sensing a voltage signal and/or a current signal from each memory cell 106 via the bit lines 116, the word lines 118, the source lines 114, the source select gate lines 115, and the drain select gate lines 111.
  • the prefix command when n+1 is equal to m, includes: a first sub-prefix command; wherein the first sub-prefix command indicates to perform an XOR operation on n groups of logical page data;
  • the peripheral circuit 102 is specifically configured to: perform an XOR operation on n groups of logic page data according to the first sub-prefix command to generate an mth group of logic page data;
  • the peripheral circuit 102 is also specifically configured to: write the nth group of logic page data and the mth group of logic page data into The memory cell array is input to store m bits of information in the memory cell.
  • the peripheral circuit 102 includes:
  • a plurality of data registers used for storing n groups of logic page data; wherein each data register is used for storing a group of logic page data;
  • the cache register is used to store the mth group of logical page data.
  • the peripheral circuit 102 includes:
  • the spare data register is used to store a set of logic page data among the n sets of logic page data when the data register is damaged.
  • the prefix command when the difference between m and n is 2, includes: a second sub-prefix command; wherein the second sub-prefix command indicates to perform an XOR operation on n groups of logical page data;
  • the peripheral circuit 102 is specifically configured to: perform an XOR operation on n groups of logic page data according to the second sub-prefix command to generate an n+1th group of logic page data;
  • the peripheral circuit 102 is further configured to: write the mth group of logic page data into the memory cell array to store m bits of information in the memory cells; wherein the mth group of logic page data is an all-0 sequence or an all-1 sequence.
  • the peripheral circuit 102 includes:
  • a plurality of data registers used to store n groups of logic page data and the n+1th group of logic page data; wherein each data register is used to store a group of logic page data;
  • the cache register is used to store the mth group of logical page data.
  • the prefix command when the difference between m and n is 3, includes: a third sub-prefix command; wherein the third sub-prefix command indicates that the n+1th group of logical page data is equal to the nth group of logical page data;
  • the peripheral circuit 102 is specifically configured to: perform a copy operation on n groups of logic page data according to the third sub-prefix command to generate an n+1th group of logic page data;
  • the peripheral circuit 102 is also configured to write the n+2th group of logic page data and the mth group of logic page data into the memory cell array to store m bits of information in the memory cells; wherein the n+2th group of logic page data and the mth group of logic page data are all-0 sequences or all-1 sequences.
  • the peripheral circuit 102 includes:
  • a plurality of data registers used to store n groups of logic page data, the n+1th group of logic page data and the n+2th group of logic page data; wherein each data register is used to store a group of logic page data;
  • the cache register is used to store the mth group of logical page data.
  • the peripheral circuit 102 is further configured to:
  • the peripheral circuits 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.
  • FIG. 12 shows some exemplary peripheral circuits 102, which include page buffers/sense amplifiers 304, column decoders/bit line (BL) drivers 306, row decoders/word line (WL) drivers 308, voltage generators 310, control logic units 312, registers 314, interfaces 316, and data buses 318. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 12 may also be included.
  • the page buffer/sense amplifier 304 can be configured to read data from the memory cell array 101 and write (program) data to the memory cell array 101 according to the control signal from the control logic unit 312.
  • the page buffer/sense amplifier 304 can store a page of write data (programming data) to be programmed into one memory page 120 of the memory cell array 101.
  • the page buffer/sense amplifier 304 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell 106 coupled to the selected word line 118.
  • the page buffer/sense amplifier 304 can also sense a low-power signal from the bit line 116 representing a data bit stored in the memory cell 106, and amplify the small voltage swing to a recognizable logic level in a read operation.
  • the column decoder/bit line driver 306 can be configured to be controlled by the control logic unit 312, and by applying a voltage from The bit line voltage generated by the generator 310 is used to select one or more NAND memory strings 108 .
  • the row decoder/word line driver 308 may be configured to be controlled by the control logic unit 312, and select/deselect the memory block 104 of the memory cell array 101 and select/deselect the word line 118 of the memory block 104.
  • the row decoder/word line driver 308 may also be configured to drive the word line 118 using the word line voltage (V WL ) generated from the voltage generator 310.
  • the row decoder/word line driver 308 may also select/deselect and drive the source selection gate line 115 and the drain selection gate line 111.
  • the row decoder/word line driver 308 is configured to perform an erase operation on the memory cell 106 coupled to the (one or more) selected word lines 118.
  • the voltage generator 310 may be configured to be controlled by the control logic unit 312, and generate a word line voltage (e.g., a read voltage, a write voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 101.
  • a word line voltage e.g., a read voltage, a write voltage, a pass voltage, a local voltage, a verification voltage, etc.
  • bit line voltage e.g., a source line voltage to be supplied to the memory cell array 101.
  • the control logic unit 312 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit.
  • the register 314 may be coupled to the control logic unit 312, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.
  • the interface 316 may be coupled to the control logic unit 312, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 312, and to buffer status information received from the control logic unit 312 and relay them to the host.
  • the interface 316 may also be coupled to the column decoder/bit line driver 306 via a data bus 318, and act as a data I/O interface and a data buffer to buffer data and relay them to the memory cell array 101 or relay or buffer data from the memory cell array 101.
  • peripheral circuit 102 is configured to perform a write operation provided by the embodiment of the present disclosure on a selected memory cell row among a plurality of memory cell rows.
  • FIG13 is a schematic diagram of a storage system 400 according to an embodiment of the present disclosure.
  • the storage system 400 includes:
  • the memory controller 406 in the above embodiment is coupled to the memory 100 and is configured to control The memory 100 is controlled.
  • System 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.
  • VR virtual reality
  • AR augmented reality
  • the system 400 may include a host 408 and a storage subsystem 402, the storage subsystem 402 having one or more memories 100, and the storage subsystem further including a memory controller 406.
  • the host 408 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device.
  • SoC system on a chip
  • the host 408 may be configured to send data to the memory 100.
  • the host 408 may be configured to receive data from the memory 100.
  • the memory 100 may be any memory device disclosed in the present disclosure.
  • the memory 100 e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)
  • a drive transistor e.g., a string driver
  • the memory controller 406 is also coupled to the host 408.
  • the memory controller 406 may manage data stored in the memory 100 and communicate with the host 408.
  • the memory controller 406 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.
  • SD secure digital
  • CF compact flash
  • USB universal serial bus
  • the memory controller 406 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptops, etc., as well as enterprise storage arrays.
  • SSD solid state drive
  • eMMC embedded multimedia card
  • the memory controller 406 may be configured to control the operation of the memory 100, such as read, erase, and program operations.
  • the memory controller 406 may also be configured to manage the data stored or to be stored in the memory.
  • the memory controller 406 may include, but is not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc.
  • the memory controller 406 may also be configured to process error correction codes (ECC) on data read from or written to the memory 100.
  • ECC error correction codes
  • the memory controller 406 may also perform any other suitable functions, for example, formatting the memory 100.
  • the memory controller 406 may communicate with an external device (e.g., the host 408) according to a specific communication protocol.
  • the memory controller 406 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
  • various interface protocols such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol,
  • the memory controller 406 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the storage system 400 can be implemented and packaged into different types of terminal electronic products.
  • a universal flash storage (UFS) package or an eMMC package e.g.
  • the memory controller 406 and the single memory 100 may be integrated into a memory card 502.
  • the memory card 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.
  • the memory card 502 may also include a memory card connector 504 that couples the memory card 502 to a host (e.g., the host 408 in FIG. 13).
  • the memory controller 406 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 506.
  • the solid state drive 506 may also include a solid state drive connector 508 that couples the solid state drive 506 to a host (e.g., the host 408 in FIG. 13 ).
  • the storage capacity and/or operating speed of the solid state drive 506 is greater than the storage capacity and/or operating speed of the memory card 502.
  • memory controller 406 may perform the operations provided by any embodiment of the present disclosure. Method of operation.

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Abstract

本公开实施例公开了一种存储系统及其操作方法、存储器控制器和存储器。所述存储系统包括存储器，所述存储器包括存储单元阵列以及与所述存储单元阵列耦合的外围电路，所述存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；所述操作方法包括：所述外围电路根据接收的前缀命令和接收的n组逻辑页数据，确定第n+1组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2n个不同的数据态。

Description

存储系统及其操作方法、存储器控制器和存储器
相关申请的交叉引用
本申请基于申请号为202211275605.2、申请日为2022年10月18日、发明名称为“存储系统及其操作方法、存储器控制器和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开实施例涉及但不限于半导体领域，尤其涉及一种存储系统及其操作方法、存储器控制器和存储器。
背景技术
NAND存储器中的存储单元包括存储1比特数据的单级单元和存储至少2比特数据的多级单元。具有单级单元的NAND存储器的虽然写入速度更快、可靠性更高，但存储容量小、成本高；具有多级单元的NAND存储器虽然写入速度相对更慢、可靠性相对更低，但存储容量大、成本低。
而在一些应用中，要求NAND存储器同时兼具单级单元的写入速度快、可靠性高以及多级单元的存储容量大、成本低。因此，如何灵活配置NAND存储器，使其实现多种存储单元模式，成为亟待解决的技术问题。
发明内容
根据本公开实施例的第一方面，提供一种存储系统的操作方法，所述存储系统包括存储器，所述存储器包括存储单元阵列以及与所述存储单元阵列耦合的外围电路，所述存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；所述操作方法包括：
所述外围电路根据接收的前缀命令和接收的n组逻辑页数据，确定第n+1 组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2n个不同的数据态。
根据本公开实施例的第二方面，提供一种存储器控制器，所述存储器控制器耦合到存储器，所述存储器包括存储单元阵列以及与所述存储单元阵列耦合的外围电路，所述存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；所述存储器控制器被配置为：
将前缀命令和n组逻辑页数据发送给所述外围电路，以使所述外围电路根据所述前缀命令和所述n组逻辑页数据确定第n+1组逻辑页数据，并在所述存储单元阵列中产生2n个不同的数据态；其中，n为正整数，n+1为小于或等于m的正整数。
根据本公开实施例的第三方面，提供一种存储器，包括：
存储单元阵列，所述存储单元阵列包括能存储m个比特信息的存储单元；
外围电路，耦合到所述存储单元阵列；其中，
所述外围电路被配置为根据接收的前缀命令和接收的n组逻辑页数据确定第n+1组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
所述外围电路还被配置为将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2n个不同的数据态。
根据本公开实施例的第四方面，提供一种存储系统，包括：
如本公开实施例第三方面所述的存储器；
如本公开实施例第二方面所述的存储器控制器，耦合到所述存储器并且被配置为控制所述存储器。
本公开实施例中，由于外围电路根据接收的前缀命令和接收的n组逻辑页数据，可确定第n+1组逻辑页数据，并将n组逻辑页数据和第n+1组逻辑页数据写入存储单元阵列，可以在存储单元阵列中产生2n个不同的数据态，即可将存储器的部分存储空间用作SLC、MLC、TLC、QLC中的至少一个，如此，可 以灵活的配置NAND存储器，使其实现多种存储单元模式，并可同时兼具写入速度快、可靠性高、存储容量大以及成本低等优势。
附图说明
为了更清楚地说明本公开具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的存储器的不同数据态的示意图；
图2是根据一示例实施例示出的一种存储系统的写入方法的流程图；
图3是根据一示例实施例示出的一种存储系统的示意图；
图4是根据一示例实施例示出的一种存储器的写入状态的示意图；
图5是根据本公开实施例示出的一种存储系统的操作方法的流程图；
图6是根据本公开实施例示出的一种存储器执行写入命令的示意图；
图7是根据本公开实施例示出的一种存储器执行写入操作的时序图；
图8是根据本公开实施例示出的一种存储器的写入状态的示意图；
图9是根据本公开实施例示出的一种存储器的外围电路的局部示意图；
图10是根据本公开实施例示出的一种存储器的示意图；
图11是根据本公开实施例示出的一种NAND存储串的剖面图；
图12是根据本公开实施例示出的包括存储单元阵列和外围电路的存储器的块图；
图13是根据本公开实施例示出的一种存储系统的示意图；
图14a是根据本公开实施例示出的一种存储器卡的示意图；
图14b是根据本公开实施例示出的一种固态驱动器(SSD)的示意图。
具体实施方式
提供下述实施例是为了更好地进一步理解本公开，并不局限于所述最佳实 施方式，不对本公开的内容和保护范围构成限制，任何人在本公开的启示下或是将本公开与其他现有技术的特征进行组合而得出的任何与本公开相同或相近似的产品，均落在本公开的保护范围之内。
在本公开的描述中，需要说明的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
图1是根据一示例性实施例示出的存储器的不同数据态的示意图。参照图1所示，随着NAND存储器的发展，存储单元的比特数从1比特(bit)增加至2比特、3比特、4比特，相应地存储单元从单级单元(Single Level Cell，SLC)演变为多级单元(Multiple Level Cell，MLC)、三级单元(Triple Level Cell，TLC)、四级单元(Quad-Level Cell，QLC)，相应地存储器中的数据态从2个增加至4个、8个、16个，使得存储器的容量增大、成本降低。
参照图1(a)所示，SLC存储器的存储单元存储1比特数据，SLC存储器的数据态包括1个擦除态和1个编程态，其擦除态记为E，其编程态记为P，编程态P的阈值电压大于擦除态E的阈值电压。
参照图1(b)所示，MLC存储器的存储单元存储2比特数据，MLC存储器的数据态包括1个擦除态和3个编程态，其擦除态记为E，其编程态从第1态至第3态依次记为P1、P2和P3，从P1态至P3态，阈值电压逐渐增大。
参照图1(c)所示，TLC存储器的存储单元存储3比特数据，TLC存储器的数据态包括1个擦除态和7个编程态，其擦除态记为E，其编程态从第1态至第7态依次记为P1、P2、P3、P4、P5、P6和P7，从P1态至P7态，阈值电压逐渐增大。
参照图1(d)所示，QLC存储器的存储单元存储4比特数据，QLC存储器数据态包括1个擦除态和15个编程态，其擦除态记为E，其编程态从第1态 至第15态依次记为P1、P2、P3、P4、P5、P6、P7、P8、P9、P10、P11、P12、P13、P14和P15，从P1态至P15态，阈值电压逐渐增大。
随着3D NAND技术的发展，存储器中的堆叠层数不断增加。当堆叠层数大于或等于64层时，将不会再有MLC存储器。虽然目前主要的3D NAND产品是TLC存储器，但当堆叠层数大于或等于300层时，主要的3D NAND产品将是QLC存储器。
新的3D NAND技术节点开发成本巨大，尤其是在堆叠层数越来越多时。从客户需求来看，仍然需求低比特存储器以满足更好的可靠性的要求，例如，汽车行业。但是，这种市场规模并不大；从成本角度来看，开发专用的低比特存储器是不值得的，例如，当主流的NAND是TLC存储器时，仍然存在一些MLC存储器的应用需求；当主流的NAND是QLC存储器时，仍然存在一些TLC存储器和MLC存储器的应用需求；从应用程序的角度来看，这是不匹配的。
一种解决方案是开发通用NAND存储器，它支持所有级别单元(SLC/MLC/TLC/QLC)。但是，这种解决方案对于所有的开发团队都是巨大的负担，例如设计、验证、确认和测试等。并且这项工作成本将是SLC存储器的三倍，特别是测试和认证团队。
图2是根据一示例实施例示出的一种存储系统的写入方法的流程图，图3是根据一示例实施例示出的一种存储系统10的示意图。结合图2和图3所示，该写入方法至少包括以下步骤：
S101：控制器11接收低逻辑页(Lower Page，LP)数据和高逻辑页(Upper Page，UP)数据；
S102：扰码器13使能，将LP数据和UP数据随机化；
S103：纠错编码器(Error Correction Code，ECC)14使能，对随机化后的LP数据和UP数据进行奇偶校验；
S104：在进行奇偶校验后，将LP数据和UP数据传输到存储器，例如，页 缓存器；
S105：禁用解扰器16和ECC解码器15；
S106：从存储器传输LP数据和UP数据至控制器11；
S107：主机端的中央处理器(Central Processing Unit，CPU)运行固件(Firmware，FW)对LP数据和UP数据执行异或非(NXOR)运算，生成中逻辑页(Middle Page，MP)数据；这里，运行固件可存储在存储器中。
S108：禁用扰码器13和ECC编码器14，并将LP/MP/UP数据传输至存储器，例如，页缓存器；
S109：发送写入命令(例如，10h)，开始执行写入操作，例如，将LP/MP/UP数据从页缓存器写入存储单元阵列12。
图4是根据一示例实施例示出的一种存储器的写入状态的示意图。参照图4所示，通过正常的写入方法将LP/MP/UP数据写入存储单元阵列12，可在TLC存储器的存储单元中存储3比特数据，并产生8个不同的数据态，即擦除态E和编程态P1至P7。通过执行图2所示的方法将LP/MP/UP数据写入存储单元阵列12，可在TLC存储器的存储单元中存储3比特数据，并产生4个不同的数据态，即擦除态E和编程态P2、P4、P6。即通过执行图2所示的方法可将TLC存储器中的至少部分存储空间用作MLC，以满足MLC存储器的应用需求。
然而，该方法需要由主机端的CPU执行，导致操作方式复杂，并且需要运行固件使用CPU对原始数据(例如，LP数据和UP数据)执行异或非运算并生成MP数据，导致效率较低。
有鉴于此，本公开实施例提供一种存储系统及其操作方法。
图5是根据本公开实施例示出的一种存储系统的操作方法的流程图。存储系统包括存储器，存储器包括存储单元阵列以及与存储单元阵列耦合的外围电路，存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；参照图5所示，所述操作方法至少包括以下步骤：
S201：外围电路根据接收的前缀命令和接收的n组逻辑页数据，确定第n+1 组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
S202：将n组逻辑页数据和第n+1组逻辑页数据写入存储单元阵列，以在存储单元阵列中产生2n个不同的数据态。
存储器包括存储单元阵列以及与存储单元阵列耦合的外围电路，存储单元阵列包括多个存储单元，每个存储单元能存储m个比特信息，例如，存储器是MLC存储器，即m＝2，又例如，存储器是TLC存储器，即m＝3，再例如，存储器是QLC存储器，即m＝4；外围电路包括逻辑控制单元、命令寄存器、缓存寄存器以及数据寄存器等。
在步骤S201中，外围电路中的逻辑控制单元可读取命令寄存器存储的前缀命令，并根据读取的前缀命令以及n组逻辑页数据，确定第n+1组逻辑页数据，并将第n+1组逻辑页数据存储至缓存寄存器或数据寄存器。n组逻辑页数据包括：LP数据、MP数据、UP数据以及额外页XP数据中的至少一个。在一具体实施例中，外围电路可对n组逻辑页数据执行逻辑运算，生成第n+1组逻辑页数据。
在步骤S202中，在接收到写入命令后，将n组逻辑页数据和第n+1组逻辑页数据依次写入存储单元阵列，并在存储单元阵列中产生2n个不同的数据态。
在一示例中，存储器是MLC存储器，当需要将MLC存储器中的部分存储空间用作SLC时，外围电路根据接收的前缀命令和LP数据，确定MP数据，并将LP数据和MP数据写入存储单元阵列，以在存储单元阵列中产生2个不同的数据态。
在一示例中，存储器是TLC存储器，当需要将TLC存储器中的部分存储空间用作MLC时，外围电路根据接收的前缀命令、LP数据和MP数据，确定UP数据，并将LP数据、MP数据和UP数据写入存储单元阵列，以在存储单元阵列中产生4个不同的数据态。
在一示例中，存储器是TLC存储器，当需要将TLC存储器中的部分存储空间用作SLC时，外围电路根据接收的前缀命令和LP数据，确定MP数据， 并至少将LP数据和MP数据写入存储单元阵列，以在存储单元阵列中产生2个不同的数据态。
在一示例中，存储器是QLC存储器，当需要将QLC存储器中的部分存储空间用作TLC时，外围电路根据接收的前缀命令、LP数据、MP数据和UP数据，确定XP数据，并将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，以在存储单元阵列中产生8个不同的数据态。
在一示例中，存储器是QLC存储器，当需要将QLC存储器中的部分存储空间用作MLC时，外围电路根据接收的前缀命令和LP数据和MP数据，确定UP数据，并至少将LP数据、MP数据和UP数据写入存储单元阵列，以在存储单元阵列中产生4个不同的数据态。
在一示例中，存储器是QLC存储器，当需要将QLC存储器中的部分存储空间用作SLC时，外围电路根据接收的前缀命令和LP数据，确定MP数据，并至少将LP数据和MP数据写入存储单元阵列，以在存储单元阵列中产生2个不同的数据态。
本公开实施例中，由于外围电路根据接收的前缀命令和接收的n组逻辑页数据，可确定第n+1组逻辑页数据，并将n组逻辑页数据和第n+1组逻辑页数据写入存储单元阵列，可以在存储单元阵列中产生2n个不同的数据态，即可将存储器的部分存储空间用作SLC、MLC、TLC、QLC中的至少一个，如此，可以灵活的配置NAND存储器，使其实现多种存储单元模式，并可同时兼具写入速度快、可靠性高、存储容量大以及成本低等优势。
此外，相较于由主机端的CPU执行逻辑运算，本公开实施例中通过存储器内部的外围电路确定第n+1组逻辑页数据的操作方式简单，在实现多种存储单元模式的同时，有利于提高存储器的操作效率。
并且，相较于开发通用NAND存储器的方案，本公开实施例提供的操作方法中采用前缀命令的方式更为友好，可与现有的NAND协议兼容，有利于节约开发成本。
在一些实施例中，当n+1等于m时，前缀命令包括：第一子前缀命令A；其中，第一子前缀命令A指示对n组逻辑页数据执行异或运算；
上述步骤S201包括：外围电路根据第一子前缀命令A对n组逻辑页数据执行异或运算，生成第m组逻辑页数据；
上述步骤S202包括：将n组逻辑页数据和第m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息。
以QLC存储器为例，存储器控制器向外围电路发送第一子前缀命令A以及LP数据、MP数据和UP数据，外围电路根据第一子前缀命令A对LP数据、MP数据和UP数据执行异或(XOR)运算，生成XP数据；向外围电路发送写入命令(例如，80h)，外围电路开始将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，以在存储单元中存储4个比特信息，并产生8个不同的数据态，即将QLC存储器中的部分存储空间用作TLC，如图6中②所示。
需要说明的是，第一子前缀命令A在80h命令之前发送。具体地，图7(b)示出了将QLC存储器中的部分存储空间用作TLC的写入时序图，该时序图包括数据类型信号Cycle Type和数据信号DQx。在QLC存储器中写入TLC模式时，首先发送第一子前缀命令A，在确定XP数据后再发送80h命令，然后在地址周期发送地址信号C1、C2、R1、R2和R3，通过该地址信号可以确定待写入的存储单元所在的逻辑地址，并将LP数据、MP数据、UP数据和XP数据写入存储单元。这里，逻辑地址包括逻辑单元号(lun)、平面(plane)、存储块(block)以及存储页(page)地址。
在一具体示例中，结合图8(a)所示，LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，UP数据为(1100001111000011)序列，外围电路根据第一子前缀命令A对LP数据、MP数据和UP数据执行异或运算，生成XP数据为(1100110011001100)序列，将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，在存储单元阵列中产生8个数据态，如图8(b)所示，分别是擦除态E(1111)、编程态P2(1100)、编程态P4(1001)、 编程态P6(1010)、编程态P8(0011)、编程态P10(0000)、编程态P12(0101)和编程态P14(0110)。
需要说明的是，本示例中以LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，UP数据为(1100001111000011)序列为例进行说明，以便于向本领域技术人员传达本公开，然而本公开并不限于此。LP数据、MP数据和UP的数据还可以是由“1”和“0”组成的其它序列，仅需保证通过对LP数据、MP数据和UP数据执行第一前缀命令A生成XP数据后，在QLC存储器中产生擦除态E至编程态P15中任意8个不同的数据态即可。
优选地，LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，UP数据为(1100001111000011)序列，如图8(b)所示，当将QLC存储器中的部分存储空间用作TLC时，相邻的两个数据态之间的阈值电压差M2基本相同，即读取裕度(margin)分布较为均匀，有利于保证用作TLC时读取操作的准确性。
本公开实施例中，当n+1等于m时，外围电路根据第一子前缀命令对n组逻辑页数据执行异或运算，可生成第m组逻辑页数据，并将n组逻辑页数据和第m组逻辑页数据写入存储单元阵列，在存储单元中存储m个比特信息的同时可在存储单元阵列中产生2n个不同的数据态，例如，当存储器是QLC时，可将QLC存储器的部分存储空间用作TLC，使得存储器兼具至少两种存储单元模式，有利于增加存储器的应用场景，在与主流存储器兼容的同时可以更好的满足客户需求。
在其它实施例中，当n+1等于m时，外围电路还可根据前缀命令对n组逻辑页数据执行异或非运算或者复制操作，生成第m组逻辑页数据。这里，可根据实际情况进行选择，本公开对此并无特殊限制。
在一些实施例中，在执行步骤S202之前，上述操作方法还包括：将n组逻辑页数据分别存储至多个数据寄存器；其中，每个数据寄存器用于存储一组逻辑页数据；将第m组逻辑页数据存储至缓存寄存器。外围电路包括页缓存器， 数据寄存器或缓存寄存器可以位于页缓存器中，用于缓存逻辑页数据。
示例性地，结合图9所示，将LP数据(1111111100000000)、存储至数据寄存器1、MP数据(1111000000001111)存储至数据寄存器2以及UP数据(1100001111000011)存储至数据寄存器3，在生成XP数据(1100110011001100)后，将XP数据存储至缓存寄存器，在接收到80h命令后，依次将数据寄存器1存储的LP数据、数据寄存器2存储的MP数据、数据寄存器3存储的UP数据以及缓存寄存器存储的XP数据写入存储单元阵列。
在一些实施例中，当m和n的差值为2时，前缀命令包括：第二子前缀命令B；其中，第二子前缀命令B指示对n组逻辑页数据执行异或非运算；
上述步骤S201包括：外围电路根据第二子前缀命令B对n组逻辑页数据执行异或非运算，生成第n+1组逻辑页数据；
上述操作方法还包括：将第m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息；其中，第m组逻辑页数据为全0序列或全1序列。
仍以QLC存储器为例，存储器控制器向外围电路发送第二子前缀命令B以及LP数据和MP数据，外围电路根据第二子前缀命令B对LP数据和MP数据执行异或非(NXOR)运算，生成UP数据；向外围电路发送写入命令(例如，80h)，外围电路开始将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，以在存储单元中存储4个比特信息，并产生4个不同的数据态，即将QLC存储器中的部分存储空间用作MLC，如图6中③所示。这里，XP数据为全0序列或全1序列。
需要说明的是，第二子前缀命令B在80h命令之前发送。具体地，图7(c)示出了将QLC存储器中的部分存储空间用作MLC的写入时序图，在QLC存储器中写入MLC模式时，首先发送第二子前缀命令B，在确定UP数据后再发送80h命令，然后在地址周期发送地址信号C1、C2、R1、R2和R3，通过该地址信号可以确定待写入的存储单元所在的逻辑地址，并将LP数据、MP数据、UP数据和XP数据写入存储单元。
在一具体示例中，结合图8(a)所示，LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，外围电路根据第二子前缀命令B对LP数据和MP数据执行异或非运算，生成UP数据为(1111000011110000)序列，XP数据为(1111111111111111)序列，将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，在存储单元阵列中产生4个数据态，如图8c所示，分别是擦除态E(1111)、编程态P4(1001)、编程态P8(0011)和编程态P12(0101)。
需要说明的是，本示例中以LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列、XP数据为(1111111111111111)序列为例进行说明，以便于向本领域技术人员传达本公开，然而本公开并不限于此。LP数据和MP的数据还可以是由“1”和“0”组成的其它序列或者XP数据还可以是全0序列，仅需保证通过对LP数据和MP数据执行第二前缀命令B生成UP数据后，在QLC存储器中产生擦除态E至编程态P15中任意4个不同的数据态即可。
优选地，LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，XP数据为(1111111111111111)序列，如图8(c)所示，当将QLC存储器中的部分存储空间用作MLC时，相邻的两个数据态之间的阈值电压差M3基本相同，即读取裕度(margin)分布较为均匀，有利于保证用作MLC时读取操作的准确性。
本公开实施例中，当m和n的差值为2时，外围电路根据第二子前缀命令对n组逻辑页数据执行异或运算，可生成第n+1组逻辑页数据，并将n组逻辑页数据、第n+1组逻辑页数据和第m组逻辑页数据写入存储单元阵列，在存储单元中存储m个比特信息的同时可在存储单元阵列中产生2n个不同的数据态，例如，当存储器是QLC时，可将QLC存储器的部分存储空间用作MLC，使得存储器兼具至少两种存储单元模式，有利于增加存储器的应用场景，在与主流存储器兼容的同时可以更好的满足客户需求。
在其它实施例中，当m和n的差值为2时，外围电路还可根据前缀命令对n组逻辑页数据执行异或运算或者复制操作，生成第n+1组逻辑页数据。这里，可根据实际情况进行选择，本公开对此并无特殊限制。
在一些实施例中，在执行步骤S202之前，上述操作方法还包括：将n组逻辑页数据和第n+1组逻辑页数据分别存储至多个数据寄存器；其中，每个数据寄存器用于存储一组逻辑页数据；在将第m组逻辑页数据写入存储单元阵列之前，上述操作方法还包括：将第m组逻辑页数据存储至缓存寄存器。
示例性地，结合图9所示，将LP数据(1111111100000000)存储至数据寄存器1、MP数据(1111000000001111)存储至数据寄存器2以及XP数据(1111111111111111)存储至缓存寄存器，在生成UP数据后，将UP数据(1111000011110000)存储至数据寄存器3，在接收到80h命令后，依次将数据寄存器1存储的LP数据、数据寄存器2存储的MP数据、数据寄存器3存储的UP数据以及缓存寄存器存储的XP数据写入存储单元阵列。
在一些实施例中，当m和n的差值为3时，前缀命令包括：第三子前缀命令C；其中，第三子前缀命令C指示第n+1组逻辑页数据等于第n组逻辑页数据；
上述步骤S201包括：外围电路根据第三子前缀命令C对n组逻辑页数据执行复制操作，生成第n+1组逻辑页数据；
上述操作方法还包括：将第n+2组逻辑页数据和第m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息；其中，第n+2组逻辑页数据和第m组逻辑页数据为全0序列或全1序列。
仍以QLC存储器为例，存储器控制器向外围电路发送第三子前缀命令C以及LP数据，外围电路根据第三子前缀命令C对LP数据执行复制操作，生成MP数据，即MP数据与LP数据相同；向外围电路发送写入命令(例如，80h)，外围电路开始将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，以在存储单元中存储4个比特信息，并产生2个不同的数据态，即将QLC存储 器中的部分存储空间用作SLC，如图6中④所示。这里，UP数据和XP数据为全0序列或全1序列。
需要说明的是，第三子前缀命令C在80h命令之前发送。具体地，图7(d)示出了将QLC存储器中的部分存储空间用作SLC的写入时序图，在QLC存储器中写入SLC模式时，首先发送第三子前缀命令C，在确定MP数据后再发送80h命令，然后在地址周期发送地址信号C1、C2、R1、R2和R3，通过该地址信号可以确定待写入的存储单元所在的逻辑地址，并将LP数据、MP数据、UP数据和XP数据写入存储单元。
在一具体示例中，结合图8(a)所示，LP数据为(1111111100000000)序列，外围电路根据第三子前缀命令C对LP数据执行复制操作，生成MP数据为(1111111100000000)序列，UP数据为(1111111111111111)序列，XP数据为(1111111111111111)序列，将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，在存储单元阵列中产生2个数据态，如图8(d)所示，分别是擦除态E(1111)和编程态P8(0011)。
需要说明的是，本示例中以LP数据为(1111111100000000)序列，UP数据为(1111111111111111)序列、XP数据为(1111111111111111)序列为例进行说明，以便于向本领域技术人员传达本公开，然而本公开并不限于此。LP的数据还可以是由“1”和“0”组成的其它序列或者UP数据和XP数据还可以是全0序列，仅需保证通过对LP数据执行第三前缀命令C生成MP数据后，在QLC存储器中产生擦除态E至编程态P15中任意2个不同的数据态即可。
优选地，LP数据为(1111111100000000)序列，UP数据为(1111111111111111)序列，XP数据为(1111111111111111)序列，如图8(d)所示，当将QLC存储器中的部分存储空间用作SLC时，擦除态E和编程态P8之间的阈值电压差M4较大，有利于保证用作MLC时读取操作的准确性。
本公开实施例中，当m和n的差值为3时，外围电路根据第三子前缀命令对n组逻辑页数据执行复制操作，可生成第n+1组逻辑页数据，并将n组逻辑 页数据、第n+1组逻辑页数据、第n+2组逻辑页数据和第m组逻辑页数据写入存储单元阵列，在存储单元中存储m个比特信息的同时可在存储单元阵列中产生2n个不同的数据态，例如，当存储器是QLC时，可将QLC存储器的部分存储空间用作SLC，使得存储器兼具至少两种存储单元模式，有利于增加存储器的应用场景，在与主流存储器兼容的同时可以更好的满足客户需求。
在一些实施例中，在执行步骤S202之前，上述操作方法还包括：将n组逻辑页数据和第n+1组逻辑页数据分别存储至多个数据寄存器；其中，每个数据寄存器用于存储一组逻辑页数据；
在将第n+2组逻辑页数据和第m组逻辑页数据写入存储单元阵列之前，上述操作方法还包括：将第n+2组逻辑页数据存储至数据寄存器；将第m组逻辑页数据存储至缓存寄存器。
示例性地，结合图9所示，将LP数据(1111111100000000)存储至数据寄存器1、UP数据(1111111111111111)存储至数据寄存器3以及XP数据(1111111111111111)存储至缓存寄存器，在生成MP数据后，将MP数据(1111111100000000)存储至数据寄存器2，在接收到80h命令后，依次将数据寄存器1存储的LP数据、数据寄存器2存储的MP数据、数据寄存器3存储的UP数据以及缓存寄存器存储的XP数据写入存储单元阵列。
在一些实施例中，在确定第n+1组逻辑页数据之前，上述操作方法还包括：
判断外围电路是否接收到前缀命令，并生成判断结果；
在判断结果指示外围电路接收到前缀命令时，根据接收的前缀命令和n组逻辑页数据，确定第n+1组逻辑页数据；
在判断结果指示外围电路未接收到前缀命令时，将m组逻辑页数据写入存储单元阵列，以在存储单元阵列中产生2m个不同的数据态。
仍以QLC存储器为例，外围电路中的逻辑控制单元可读取命令寄存器，并根据读取结果判断命令寄存器是否存储有前缀命令(例如，第一子前缀命令或第二子前缀命令或第三子前缀命令)，在读取结果指示命令寄存器中存储有前 缀命令时，外围电路根据前缀命令和n组逻辑页数据确定第n+1组逻辑页数据，即将QLC存储器的部分存储空间用作TLC、MLC或SLC。
在读取结果指示命令寄存器中未存储有前缀命令时，向外围电路发送80h命令，外围电路将m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息，并在存储单元阵列中产生2m个不同的数据态。这里，写入m组逻辑页数据的存储空间用作QLC，如图6中①所示。
在一具体示例中，参照图8(a)所示，LP数据为(1111111100000000)序列，MP数据为(1111000000001111)序列，UP数据为(1100001111000011)序列，XP数据为(1001100110011001)序列，外围电路根据80h命令将LP数据、MP数据、UP数据和XP数据写入存储单元阵列，在存储单元阵列中产生16个数据态，如图8(a)所示，分别是擦除态E(1111)、编程态P1(1110)、编程态P2(1100)、编程态P3(1101)、编程态P4(1001)、编程态P5(1000)、编程态P6(1010)、编程态P7(1011)、编程态P8(0011)、编程态P9(0010)、编程态P10(0000)、编程态P11(0001)、编程态P12(0101)、编程态P13(0100)、编程态P14(0110)和编程态P15(0111)。
本公开实施例中，通过判断外围电路是否接收到前缀命令并生成判断结果，根据判断结果确定是否将QLC存储器的部分存储空间用作SLC、MLC、TLC、中的至少一个，有利于精确的配置NAND存储器。
在一些实施例中，上述操作方法还包括：在数据寄存器损坏时，外围电路将n组逻辑页数据中的一组逻辑页数据存储至备用数据寄存器。例如，参照图9所示，在数据寄存器1损坏时，外围电路将LP数据存储至备用数据寄存器4；和/或，在数据寄存器2损坏时，外围电路将MP数据存储至备用数据寄存器5等。
需要说明的是，本示例中仅示意出2个备用数据寄存器，存储器中备用数据寄存器的数量不限于2个，还可以是1个、3个甚至更多个，本公开在此不作限制。在实际应用中，可根据需求合理设置备用数据寄存器的数量。
本公开实施例还提供一种存储器控制器，存储器控制器耦合到存储器，存储器包括存储单元阵列以及与存储单元阵列耦合的外围电路，存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；存储器控制器被配置为：将前缀命令和n组逻辑页数据发送给外围电路，以使外围电路根据前缀命令和n组逻辑页数据确定第n+1组逻辑页数据，并在存储单元阵列中产生2n个不同的数据态；其中，n为正整数，n+1为小于或等于m的正整数。
在一些实施例中，前缀命令包括：第一子前缀命令，第一子前缀命令用于指示对n组逻辑页数据执行异或运算；
存储器控制器具体被配置为：将第一子前缀命令和n组逻辑页数据发送给外围电路，以使外围电路根据第一子前缀命令对n组逻辑页数据执行异或运算，生成第m组逻辑页数据；其中，n+1等于m。
在一些实施例中，前缀命令包括：第二子前缀命令，第二子前缀命令用于指示对n组逻辑页数据执行异或非运算；
存储器控制器具体被配置为：将第二子前缀命令和n组逻辑页数据发送给外围电路，以使外围电路根据第二子前缀命令对n组逻辑页数据执行异或运算，生成第n+1组逻辑页数据；
存储器控制器还被配置为：将第m组逻辑页数据发送给外围电路；其中，第m组逻辑页数据为全0序列或全1序列，m和n的差值为2。
在一些实施例中，前缀命令包括：第三子前缀命令，第三子前缀命令用于指示第n+1组逻辑页数据等于第n组逻辑页数据；
存储器控制器具体被配置为：将第三子前缀命令和n组逻辑页数据发送给外围电路，以使外围电路根据第三子前缀命令对n组逻辑页数据执行复制操作，生成第n+1组逻辑页数据；
存储器控制器还被配置为：将第n+2组逻辑页数据和第m组逻辑页数据发送给外围电路；其中，第n+2组逻辑页数据和第m组逻辑页数据为全0序列或全1序列，m和n的差值为3。
在一些实施例中，存储器控制器还被配置为：在发送前缀命令后，将写入命令发送给外围电路，以使外围电路根据写入命令至少将n组逻辑页数据和第n+1组逻辑页数据写入存储单元阵列。
图10是根据本公开实施例示出的一种存储器100的示意图。参照图10所示，存储器100包括：
存储单元阵列101，存储单元阵列101包括能存储m个比特信息的存储单元106；
外围电路102，耦合到存储单元阵列101；其中，
外围电路102被配置为根据接收的前缀命令和接收的n组逻辑页数据确定第n+1组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
外围电路102还被配置为将n组逻辑页数据和第n+1组逻辑页数据写入存储单元阵列101，以在存储单元阵列101中产生2n个不同的数据态。
存储单元阵列101可以是NAND闪存存储器单元阵列，其中，存储单元阵列101以NAND存储串108的阵列的形式提供，每个NAND存储串108垂直地延伸。在一些实施方式中，每个NAND存储串108包括串联耦合并且垂直地堆叠的多个存储单元106。每个存储单元106可以保持连续模拟值，例如，电压或电荷，其取决于在存储单元106的区域内捕获的电子的数量。每个存储单元106可以是包括浮栅晶体管的浮栅类型的存储单元，或者是包括电荷捕获晶体管的电荷捕获类型的存储单元。
在一些实施方式中，每个存储单元106是具有两种可能的数据态并且因此可以存储1比特数据的单级单元。例如，第一数据态“0”可以对应于第一电压范围，并且第二数据态“1”可以对应于第二电压范围。
在一些实施方式中，每个存储单元106是能够在多于四个的数据态中存储多于1比特数据的单元。例如，可以每单元存储2比特(又被称为多级单元)，可以每单元存储3比特(又被称为三级单元)，或者可以每单元存储4比特(又被称为四级单元)。每个多级单元可以被编程为采取可能的标称存储值的范围。 在一个示例中，如果每个多级单元存储2比特数据，则多级单元可以被写入为通过将三个可能的标称存储值中的一个写入到该单元而从擦除状态采取三个可能的数据态中的一个。第四标称存储值可以用于擦除状态。
如图10中所示，每个NAND存储串108可以包括在其源极端处的源极选择晶体管(Source Select Transistor，SST)110和在其漏极端处的漏极选择晶体管(Drain Select Transistor，DST)112。源极选择晶体管110和漏极选择晶体管112可以被配置为在读取和写入操作期间激活选定的NAND存储串108(阵列的列)。
在一些实施方式中，同一存储块104中的NAND存储串108的源极通过同一源极线(Source Line，SL)114耦合。换句话说，根据一些实施方式，同一存储块104中的所有NAND存储串108具有阵列公共源极(Array Common Source，ACS)。
根据一些实施方式，每个NAND存储串108的漏极选择晶体管112耦合到相应的位线116，可以经由输出总线(未示出)从位线116读取或写入数据。
在一些实施方式中，每个NAND存储串108被配置为通过经由一个或多个漏极选择栅线111将选择电压(例如，高于漏极选择晶体管112的阈值电压)或取消选择电压(例如，0V)施加到相应的漏极选择栅极，这里，选择电压用于导通漏极选择晶体管112，取消选择电压用于关断漏极选择晶体管112。和/或，在一些实施方式中，每个NAND存储串108被配置为通过经由一个或多个源极选择栅线115将选择电压(例如，高于源极选择晶体管110的阈值电压)或取消选择电压(例如，0V)施加到相应的源极选择栅极，这里，选择电压用于导通源极选择晶体管110，取消选择电压用于关断源极选择晶体管110。
如图10中所示，NAND存储串108可以被组织为多个存储块104，多个存储块104的每一个可以具有公共源极线114(例如，耦合到地)。在一些实施方式中，每个存储块104是用于擦除操作的基本数据单位，即，同一存储块104上的所有存储单元106同时被擦除。
应当理解，在一些示例中，可以在半块级、在四分之一块级或者在具有任何合适数量的块或块的任何合适的分数的级执行擦除操作。相邻NAND存储串108的存储单元106可以通过字线118耦合，字线118选择存储单元106的哪一行受读取和写入操作的影响。
在一些实施方式中，每个字线118记为一个存储页120。以比特为单位的一个存储页120的大小，可以与一个存储块104中由字线118耦合的NAND存储串108的数量相关。每个字线118可以包括在相应存储页120中的每个存储单元106处的多个控制栅极(栅极电极)以及耦合控制栅极的栅极线。可以理解的是，一个存储单元行即为位于同一存储页120的多个存储单元106。
图11是根据本公开实施例示出的一种NAND存储串108的剖面图。如图11中所示，NAND存储串108可以在衬底202上方垂直地延伸穿过存储堆叠层204。衬底202可以包括硅(例如，单晶硅)、硅锗(SiGe)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)、绝缘体上锗(GOI)或者任何其他合适的材料。
存储堆叠层204可以包括交替的栅极导电层206和栅极电介质层208。存储堆叠层204中的栅极导电层206和栅极电介质层208的对的数量可以确定存储单元阵列101中的存储单元106的数量。
栅极导电层206可以包括导电材料，导电材料包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。在一些实施方式中，每个栅极导电层206可以包括金属层，例如，钨层。在一些实施方式中，每个栅极导电层206可以包括掺杂多晶硅层。每个栅极导电层206可以包括围绕存储单元106的控制栅极，并且可以在存储堆叠层204的顶部处横向地延伸作为漏极选择栅线111、在存储堆叠层204的底部处横向地延伸作为源极选择栅线115、或者在漏极选择栅线111与源极选择栅线115之间横向地延伸作为字线118。
如图11中所示，NAND存储串108包括垂直地延伸穿过存储器堆叠层204的沟道结构212。在一些实施方式中，沟道结构212包括填充有(一种或多种) 半导体材料(例如，作为半导体沟道220)和(一种或多种)电介质材料(例如，作为存储膜218)的沟道孔。在一些实施方式中，半导体沟道220包括硅，例如，多晶硅。在一些实施方式中，存储膜218是包括隧穿层226、存储层224(又称为“电荷捕获/存储层”)和阻挡层222的复合电介质层。沟道结构212可以具有圆柱形状(例如，柱形状)。根据一些实施方式，半导体沟道220、隧穿层226、存储层224和阻挡层222以此顺序从圆柱的中心朝向圆柱的外表面径向布置。隧穿层226可以包括氧化硅、氮氧化硅或其任何组合。存储层224可以包括氮化硅、氮氧化硅或其任何组合。阻挡层222可以包括氧化硅、氮氧化硅、高介电常数(高k)电介质或其任何组合。在一个示例中，存储膜218可以包括氧化硅/氮氧化硅/氧化硅(ONO)的复合层。
根据一些实施方式，如图11中所示，阱214(例如，P阱和/或N阱)形成在衬底202中，并且NAND存储串108的源极端与阱214接触。在一些实施方式中，NAND存储串108还包括在NAND存储串108的漏极端处的沟道插塞216。应当理解，尽管在图11中未示出，但是可以形成存储单元阵列101的附加部件，附加部件包括但不限于栅极线缝隙/源极触点、局部触点、互连层等。
返回参考图10，外围电路102可以通过位线116、字线118、源极线114、源极选择栅线115和漏极选择栅线111耦合到存储单元阵列101。外围电路102可以包括任何合适的模拟、数字以及混合信号电路，以用于通过经由位线116、字线118、源极线114、源极选择栅线115和漏极选择栅线111将电压信号和/或电流信号施加到每个存储单元106以及从每个存储单元106感测电压信号和/或电流信号来促进存储单元阵列101的操作。
在一些实施例中，当n+1等于m时，前缀命令包括：第一子前缀命令；其中，第一子前缀命令指示对n组逻辑页数据执行异或运算；
外围电路102具体被配置为：根据第一子前缀命令对n组逻辑页数据执行异或运算，生成第m组逻辑页数据；
外围电路102还具体被配置为：将n组逻辑页数据和第m组逻辑页数据写 入存储单元阵列，以在存储单元中存储m个比特信息。
在一些实施例中，外围电路102包括：
多个数据寄存器，用于存储n组逻辑页数据；其中，每个数据寄存器用于存储一组逻辑页数据；
缓存寄存器，用于存储第m组逻辑页数据。
在一些实施例中，外围电路102包括：
备用数据寄存器，用于在数据寄存器损坏时存储n组逻辑页数据中的一组逻辑页数据。
在一些实施例中，当m和n的差值为2时，前缀命令包括：第二子前缀命令；其中，第二子前缀命令指示对n组逻辑页数据执行异或非运算；
外围电路102具体被配置为：根据第二子前缀命令对n组逻辑页数据执行异或非运算，生成第n+1组逻辑页数据；
外围电路102还被配置为：将第m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息；其中，第m组逻辑页数据为全0序列或全1序列。
在一些实施例中，外围电路102包括：
多个数据寄存器，用于存储n组逻辑页数据和第n+1组逻辑页数据；其中，每个数据寄存器用于存储一组逻辑页数据；
缓存寄存器，用于存储第m组逻辑页数据。
在一些实施例中，当m和n的差值为3时，前缀命令包括：第三子前缀命令；其中，第三子前缀命令指示第n+1组逻辑页数据等于第n组逻辑页数据；
外围电路102具体被配置为：根据第三子前缀命令对n组逻辑页数据执行复制操作，生成第n+1组逻辑页数据；
外围电路102还被配置为：将第n+2组逻辑页数据和第m组逻辑页数据写入存储单元阵列，以在存储单元中存储m个比特信息；其中，第n+2组逻辑页数据和第m组逻辑页数据为全0序列或全1序列。
在一些实施例中，外围电路102包括：
多个数据寄存器，用于存储n组逻辑页数据、第n+1组逻辑页数据和第n+2组逻辑页数据；其中，每个数据寄存器用于存储一组逻辑页数据；
缓存寄存器，用于存储第m组逻辑页数据。
在一些实施例中，外围电路102还被配置为:
在确定第n+1组逻辑页数据之前，判断是否接收到前缀命令，并生成判断结果；
在判断结果指示接收到前缀命令时，根据接收的前缀命令和n组逻辑页数据，确定第n+1组逻辑页数据；
在判断结果指示未接收到前缀命令时，将m组逻辑页数据写入存储单元阵列，以在存储单元阵列中产生2m个不同的数据态。
外围电路102可以包括使用金属-氧化物-半导体(MOS)技术形成的各种类型的外围电路。例如，图12示出了一些示例性外围电路102，外围电路102包括页缓冲器/感测放大器304、列解码器/位线(BL)驱动器306、行解码器/字线(WL)驱动器308、电压发生器310、控制逻辑单元312、寄存器314、接口316和数据总线318。应当理解，在一些示例中，还可以包括图12中未示出的附加外围电路。
页缓冲器/感测放大器304可以被配置为根据来自控制逻辑单元312的控制信号从存储单元阵列101读取数据以及向存储单元阵列101写入(编程)数据。在一个示例中，页缓冲器/感测放大器304可以存储要被编程到存储单元阵列101的一个存储页120中的一页写入数据(编程数据)。在另一示例中，页缓冲器/感测放大器304可以执行编程验证操作，以确保数据已经被正确地编程到耦合到选定字线118的存储单元106中。在又一示例中，页缓冲器/感测放大器304还可以感测来自位线116的表示存储在存储单元106中的数据位的低功率信号，并且在读取操作中将小电压摆幅放大到可识别的逻辑电平。列解码器/位线驱动器306可以被配置为由控制逻辑单元312控制，并且通过施加从电压 发生器310生成的位线电压来选择一个或多个NAND存储串108。
行解码器/字线驱动器308可以被配置为由控制逻辑单元312控制，并且选择/取消选择存储单元阵列101的存储块104并且选择/取消选择存储块104的字线118。行解码器/字线驱动器308还可以被配置为使用从电压发生器310生成的字线电压(VWL)来驱动字线118。在一些实施方式中，行解码器/字线驱动器308还可以选择/取消选择并且驱动源极选择栅线115和漏极选择栅线111。如下文详细描述的，行解码器/字线驱动器308被配置为对耦合到(一个或多个)选定字线118的存储单元106执行擦除操作。电压发生器310可以被配置为由控制逻辑单元312控制，并且生成要被供应到存储单元阵列101的字线电压(例如，读取电压、写入电压、通过电压、局部电压、验证电压等)、位线电压和源极线电压。
控制逻辑单元312可以耦合到上文描述的每个外围电路，并且被配置为控制每个外围电路的操作。寄存器314可以耦合到控制逻辑单元312，并且包括状态寄存器、命令寄存器和地址寄存器，以用于存储用于控制每个外围电路的操作的状态信息、命令操作码(OP码)和命令地址。接口316可以耦合到控制逻辑单元312，并且充当控制缓冲器，以缓冲从主机(未示出)接收的控制命令并且并将其中继到控制逻辑单元312，以及缓冲从控制逻辑单元312接收的状态信息并且将其中继到主机。接口316还可以经由数据总线318耦合到列解码器/位线驱动器306，并且充当数据I/O接口和数据缓冲器，以缓冲数据并且将其中继到存储单元阵列101或从存储单元阵列101中继或缓冲数据。
需要强调的是，外围电路102被配置为对多个存储器单元行中的选定存储器单元行执行本公开实施例提供的写入操作。
图13是根据本公开实施例示出的一种存储系统400的示意图。参照图13所示，存储系统400，包括：
一个或多个如上述实施例中的存储器100；
如上述实施例中的存储器控制器406，耦合到存储器100并且被配置为控 制存储器100。
系统400可以是移动电话、台式计算机、膝上型计算机、平板计算机、车辆计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或者其中具有储存器的任何其他合适的电子设备。
如图13中所示，系统400可以包括主机408和存储子系统402，存储子系统402具有一个或多个存储器100，存储子系统还包括存储器控制器406。主机408可以是电子设备的处理器(例如，中央处理单元(CPU))或者片上系统(SoC)(例如，应用处理器(AP))。主机408可以被配置为将数据发送到存储器100。或者，主机408可以被配置为从存储器100接收数据。
存储器100可以是本公开中公开的任何存储器器件。存储器100(例如，NAND闪存存储器器件(例如，三维(3D)NAND闪存存储器器件))可以在擦除操作期间具有来自耦合到未选定字线的驱动晶体管(例如，串驱动器)的减小的漏电流，这允许驱动晶体管的进一步尺寸缩小。
根据一些实施方式，存储器控制器406还耦合到主机408。存储器控制器406可以管理存储在存储器100中的数据，并且与主机408通信。
在一些实施方式中，存储器控制器406被设计为用于在低占空比环境中操作，如安全数字(SD)卡、紧凑型闪存(CF)卡、通用串行总线(USB)闪存驱动器、或用于在诸如个人计算器、数字相机、移动电话等的电子设备中使用的其他介质。
在一些实施方式中，存储器控制器406被设计为用于在高占空比环境固态硬盘(SSD)或嵌入式多媒体卡(eMMC)中操作，SSD或eMMC用作诸如智能电话、平板计算机、膝上型计算机等的移动设备的数据储存器以及企业存储阵列。
存储器控制器406可以被配置为控制存储器100的操作，例如读取、擦除和编程操作。存储器控制器406还可以被配置为管理关于存储在或要存储在存 储器100中的数据的各种功能，包括但不限于坏块管理、垃圾收集、逻辑到物理地址转换、损耗均衡等。在一些实施方式中，存储器控制器406还被配置为处理关于从存储器100读取的或者被写入到存储器100的数据的纠错码(ECC)。
存储器控制器406还可以执行任何其他合适的功能，例如，格式化存储器100。存储器控制器406可以根据特定通信协议与外部设备(例如，主机408)通信。例如，存储器控制器406可以通过各种接口协议中的至少一种与外部设备通信，接口协议例如USB协议、MMC协议、外围部件互连(PCI)协议、PCI高速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(SCSI)协议、增强型小型磁盘接口(ESDI)协议、集成驱动电子设备(IDE)协议、Firewire协议等。
存储器控制器406和一个或多个存储器100可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(UFS)封装或eMMC封装)中。也就是说，存储系统400可以实施并且封装到不同类型的终端电子产品中。
在如图14a中所示的一个示例中，存储器控制器406和单个存储器100可以集成到存储器卡502中。存储器卡502可以包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、CF卡、智能媒体(SM)卡、存储器棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。存储器卡502还可以包括将存储器卡502与主机(例如，图13中的主机408)耦合的存储器卡连接器504。
在如图14b中所示的另一示例中，存储器控制器406和多个存储器100可以集成到固态驱动器(SSD)506中。固态驱动器506还可以包括将固态驱动器506与主机(例如，图13中的主机408)耦合的固态驱动器连接器508。在一些实施方式中，固态驱动器506的存储容量和/或操作速度大于存储器卡502的存储容量和/或操作速度。
可以理解的是，存储器控制器406可以执行如本公开任一实施例提供的操 作方法。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本公开创造的保护范围之中。

Claims (21)

  1. 一种存储系统的操作方法，所述存储系统包括存储器，所述存储器包括存储单元阵列以及与所述存储单元阵列耦合的外围电路，所述存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；所述操作方法包括：
    所述外围电路根据接收的前缀命令和接收的n组逻辑页数据，确定第n+1组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
    将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2n个不同的数据态。
  2. 根据权利要求1所述的操作方法，其中，当n+1等于m时，所述前缀命令包括：第一子前缀命令；其中，所述第一子前缀命令指示对所述n组逻辑页数据执行异或运算；
    所述外围电路根据接收的前缀命令和n组逻辑页数据确定第n+1组逻辑页数据，包括：
    所述外围电路根据所述第一子前缀命令对所述n组逻辑页数据执行所述异或运算，生成第m组逻辑页数据；
    所述将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，包括：
    将所述n组逻辑页数据和所述第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息。
  3. 根据权利要求2所述的操作方法，其中，在将所述n组逻辑页数据和所述第m组逻辑页数据写入所述存储单元阵列之前，所述操作方法还包括：
    将所述n组逻辑页数据分别存储至多个数据寄存器；其中，每个所述数据寄存器用于存储一组逻辑页数据；
    将所述第m组逻辑页数据存储至缓存寄存器。
  4. 根据权利要求1所述的操作方法，其中，当m和n的差值为2时，所述 前缀命令包括：第二子前缀命令；其中，所述第二子前缀命令指示对所述n组逻辑页数据执行异或非运算；
    所述外围电路根据接收的前缀命令和n组逻辑页数据确定第n+1组逻辑页数据，包括：
    所述外围电路根据所述第二子前缀命令对所述n组逻辑页数据执行所述异或非运算，生成所述第n+1组逻辑页数据；
    所述操作方法还包括：
    将第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息；其中，所述第m组逻辑页数据为全0序列或全1序列。
  5. 根据权利要求1所述的操作方法，其中，当m和n的差值为3时，所述前缀命令包括：第三子前缀命令；其中，所述第三子前缀命令指示所述第n+1组逻辑页数据等于第n组逻辑页数据；
    所述外围电路根据接收的前缀命令和n组逻辑页数据确定第n+1组逻辑页数据，包括：
    所述外围电路根据所述第三子前缀命令对所述n组逻辑页数据执行复制操作，生成所述第n+1组逻辑页数据；
    所述操作方法还包括：
    将第n+2组逻辑页数据和第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息；其中，所述第n+2组逻辑页数据和所述第m组逻辑页数据为全0序列或全1序列。
  6. 根据权利要求1所述的操作方法，其中，在确定所述第n+1组逻辑页数据之前，所述操作方法还包括：
    判断是否接收到所述前缀命令，并生成判断结果；
    在所述判断结果指示接收到所述前缀命令时，根据接收的所述前缀命令和所述n组逻辑页数据，确定所述第n+1组逻辑页数据。
  7. 根据权利要求6所述的操作方法，其中，
    在所述判断结果指示未接收到所述前缀命令时，将m组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2m个不同的数据态。
  8. 一种存储器控制器，所述存储器控制器耦合到存储器，所述存储器包括存储单元阵列以及与所述存储单元阵列耦合的外围电路，所述存储单元阵列包括能存储m个比特信息的存储单元，m为大于1的正整数；所述存储器控制器被配置为：
    将前缀命令和n组逻辑页数据发送给所述外围电路，以使所述外围电路根据所述前缀命令和所述n组逻辑页数据确定第n+1组逻辑页数据，并在所述存储单元阵列中产生2n个不同的数据态；其中，n为正整数，n+1为小于或等于m的正整数。
  9. 根据权利要求8所述的存储器控制器，其中，所述前缀命令包括：第一子前缀命令，所述第一子前缀命令用于指示对所述n组逻辑页数据执行异或运算；
    所述存储器控制器具体被配置为：将所述第一子前缀命令和n组逻辑页数据发送给所述外围电路，以使所述外围电路根据所述第一子前缀命令对所述n组逻辑页数据执行所述异或运算，生成第m组逻辑页数据；其中，n+1等于m。
  10. 根据权利要求8所述的存储器控制器，其中，所述前缀命令包括：第二子前缀命令，所述第二子前缀命令用于指示对所述n组逻辑页数据执行异或非运算；
    所述存储器控制器具体被配置为：将所述第二子前缀命令和n组逻辑页数据发送给所述外围电路，以使所述外围电路根据所述第二子前缀命令对所述n组逻辑页数据执行所述异或运算，生成所述第n+1组逻辑页数据；
    所述存储器控制器还被配置为：将第m组逻辑页数据发送给所述外围电路；其中，所述第m组逻辑页数据为全0序列或全1序列，m和n的差值为2。
  11. 根据权利要求8所述的存储器控制器，其中，所述前缀命令包括：第三子前缀命令，所述第三子前缀命令用于指示所述第n+1组逻辑页数据等于第n 组逻辑页数据；
    所述存储器控制器具体被配置为：将所述第三子前缀命令和n组逻辑页数据发送给所述外围电路，以使所述外围电路根据所述第三子前缀命令对所述n组逻辑页数据执行复制操作，生成所述第n+1组逻辑页数据；
    所述存储器控制器还被配置为：将第n+2组逻辑页数据和第m组逻辑页数据发送给所述外围电路；其中，所述第n+2组逻辑页数据和所述第m组逻辑页数据为全0序列或全1序列，m和n的差值为3。
  12. 根据权利要求8所述的存储器控制器，其中，所述存储器控制器还被配置为：
    在发送所述前缀命令后，将写入命令发送给所述外围电路，以使所述外围电路根据所述写入命令至少将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列。
  13. 一种存储器，包括：
    存储单元阵列，所述存储单元阵列包括能存储m个比特信息的存储单元；
    外围电路，耦合到所述存储单元阵列；其中，
    所述外围电路被配置为根据接收的前缀命令和接收的n组逻辑页数据确定第n+1组逻辑页数据；其中，n为正整数，n+1为小于或等于m的正整数；
    所述外围电路还被配置为将所述n组逻辑页数据和所述第n+1组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2n个不同的数据态。
  14. 根据权利要求13所述的存储器，其中，当n+1等于m时，所述前缀命令包括：第一子前缀命令；其中，所述第一子前缀命令指示对所述n组逻辑页数据执行异或运算；
    所述外围电路具体被配置为：根据所述第一子前缀命令对所述n组逻辑页数据执行所述异或运算，生成第m组逻辑页数据；
    所述外围电路还具体被配置为：将所述n组逻辑页数据和所述第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息。
  15. 根据权利要求14所述的存储器，其中，所述外围电路包括：
    多个数据寄存器，用于存储所述n组逻辑页数据；其中，每个所述数据寄存器用于存储一组逻辑页数据；
    缓存寄存器，用于存储所述第m组逻辑页数据。
  16. 根据权利要求15所述的存储器，其中，所述外围电路包括：
    备用数据寄存器，用于在所述数据寄存器损坏时存储所述n组逻辑页数据中的一组逻辑页数据。
  17. 根据权利要求13所述的存储器，其中，当m和n的差值为2时，所述前缀命令包括：第二子前缀命令；其中，所述第二子前缀命令指示对所述n组逻辑页数据执行异或非运算；
    所述外围电路具体被配置为：根据所述第二子前缀命令对所述n组逻辑页数据执行所述异或非运算，生成所述第n+1组逻辑页数据；
    所述外围电路还被配置为：将第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息；其中，所述第m组逻辑页数据为全0序列或全1序列。
  18. 根据权利要求13所述的存储器，其中，当m和n的差值为3时，所述前缀命令包括：第三子前缀命令；其中，所述第三子前缀命令指示所述第n+1组逻辑页数据等于第n组逻辑页数据；
    所述外围电路具体被配置为：根据所述第三子前缀命令对所述n组逻辑页数据执行复制操作，生成所述第n+1组逻辑页数据；
    所述外围电路还被配置为：将第n+2组逻辑页数据和第m组逻辑页数据写入所述存储单元阵列，以在所述存储单元中存储m个比特信息；其中，所述第n+2组逻辑页数据和所述第m组逻辑页数据为全0序列或全1序列。
  19. 根据权利要求13所述的存储器，其中，所述外围电路还被配置为：
    在确定所述第n+1组逻辑页数据之前，判断是否接收到所述前缀命令，并生成判断结果；
    在所述判断结果指示接收到所述前缀命令时，根据接收的所述前缀命令和所述n组逻辑页数据，确定所述第n+1组逻辑页数据。
  20. 根据权利要求19所述的存储器，其中，所述外围电路还被配置为：在所述判断结果指示未接收到所述前缀命令时，将m组逻辑页数据写入所述存储单元阵列，以在所述存储单元阵列中产生2m个不同的数据态。
  21. 一种存储系统，包括：
    一个或多个如权利要求13至20任一项所述的存储器；
    如权利要求8至12任一项所述的存储器控制器，耦合到所述存储器并且被配置为控制所述存储器。
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