WO2024078006A1 - 芯片的地址重构方法、装置以及电子设备、存储介质 - Google Patents

芯片的地址重构方法、装置以及电子设备、存储介质 Download PDF

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Publication number
WO2024078006A1
WO2024078006A1 PCT/CN2023/101784 CN2023101784W WO2024078006A1 WO 2024078006 A1 WO2024078006 A1 WO 2024078006A1 CN 2023101784 W CN2023101784 W CN 2023101784W WO 2024078006 A1 WO2024078006 A1 WO 2024078006A1
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Prior art keywords
routing information
address
chip
target
request
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PCT/CN2023/101784
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English (en)
French (fr)
Inventor
刘明
石昊明
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声龙(新加坡)私人有限公司
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Publication of WO2024078006A1 publication Critical patent/WO2024078006A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric

Definitions

  • the present application relates to the field of chip technology, and in particular to a chip address reconstruction method, device, electronic device, and storage medium.
  • the design methods used for large-capacity chips are: 1) using a large amount of DRAM (Dynamic Random Access Memory); 2) using advanced packaging processes, such as HBM (High Bandwidth Memory) and 3D IC chips.
  • DRAM Dynamic Random Access Memory
  • HBM High Bandwidth Memory
  • 3D IC chips The common characteristics of these chips are: a large number of storage control units, a larger number of storage units, and a high storage density.
  • the same problem they face due to process manufacturing limitations, the yield of the storage control unit is low, resulting in a low chip yield. Among them, the greater the number and density of storage units, the lower the yield.
  • the related technology uses the memory repair method, but the number of rows repaired by this method is limited, and the chip cannot be completely repaired.
  • there are many storage control units and the probability of a bad storage control unit is extremely high.
  • there is also a method of address reconstruction in the related technology but this method has limitations on the storage capacity or structure of the chip. The reason is that for chips with large-capacity storage, the storage space managed by each storage control unit may include multiple storage units, and when using this method to access the memory, it is to directly access all the storage units managed by the storage control unit, which is poorly targeted. If each storage control unit only manages one storage unit, then the access requires the use of a large amount of computing resources inside the chip, and at this time, there will be a delay in processing data.
  • the purpose of this application is to provide a chip address reconstruction method, device, electronic device, and storage medium.
  • the present application proposes a chip address reconstruction method, wherein the crossbar switch in the chip adopts a hierarchical structure, and the method comprises: obtaining address request information, wherein the address request information comprises a request address; parsing the request address to obtain initial routing information and an addressing address; searching for a preset mapping relationship to obtain target routing information corresponding to the initial routing information, wherein the preset mapping relationship is obtained by a host computer based on the hierarchical structure. To; based on the target routing information and the addressing address, determine the target address, wherein the target address is used to access the target storage control unit in the chip managed by the storage space of the target storage unit.
  • the present application proposes an address reconstruction device for a chip, wherein a cross switch in the chip adopts a hierarchical structure, and the device comprises: an acquisition unit, used to acquire address request information, wherein the address request information comprises a request address; a parsing unit, used to parse the request address to obtain initial routing information and an addressing address; a table lookup unit, used to search for a preset mapping relationship to obtain target routing information corresponding to the initial routing information, wherein the preset mapping relationship is obtained by a host computer based on the hierarchical structure; a determination unit, used to determine a target address based on the target routing information and the addressing address, wherein the target address is used to access a target storage unit in a storage space managed by a target storage control unit in the chip.
  • the present application proposes an electronic device, comprising: a processor, suitable for executing a computer program; a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by the processor, the address reconstruction method of the above-mentioned chip is implemented.
  • the present application proposes a computer-readable storage medium, which stores a computer program.
  • the computer program When executed by a processor, it implements the address reconstruction method of the above-mentioned chip.
  • the chip address reconstruction method, device, electronic device, and storage medium of the embodiment of the present application obtain initial routing information and addressing address by parsing the request address, and determine the target routing information corresponding to the initial routing information by searching the preset mapping relationship configured by the host computer, that is, obtaining the routing information of the storage space managed by the effective storage control unit in the chip, which can perform targeted access to the storage unit and save chip computing resources.
  • the memory access can skip the damaged storage control unit and access the effective storage control unit; based on the target routing information and the addressing address, the target address is determined, which can ensure that the target storage control unit hit by the chip based on the target address during memory access is intact, thereby ensuring that the memory access of the chip is reliable.
  • FIG1 is a block diagram of a chip according to an example of the present application.
  • FIG2 is a schematic diagram of the structure of a crossbar switch according to an example of the present application.
  • FIG3 is a flow chart of a chip address reconstruction method according to an embodiment of the present application.
  • FIG4 is a block diagram of a chip address reconstruction device according to an embodiment of the present application.
  • FIG. 5 is a structural block diagram of an electronic device according to an embodiment of the present application.
  • FIG1 is a block diagram of a chip structure of an example of the present application.
  • the chip 100 is an integrated large-capacity storage chip, which may include: computing unit 0 to computing unit M-1, storage control unit 0 to storage control unit N-1, lookup table unit 0 to lookup table unit M-1, and a cross switch; wherein M and N are both integers greater than or equal to 1.
  • Computing unit 0 to computing unit M-1 indicate that the chip 100 integrates M computing units, wherein each of the M computing units has a need to access memory.
  • Storage control unit 0 to storage control unit N-1 indicate that the chip 100 integrates N storage control units, wherein each of the N storage control units manages a storage space within the chip 100; if the address depth of each storage space is D, then the maximum addressable address range of the entire chip 100 is 0 to (N*D-1).
  • Lookup table unit 0 to lookup table unit M-1 are M completely identical lookup table units, wherein each computing unit is equipped with one lookup table unit, and the address sent by the computing unit is converted by the equipped lookup table unit.
  • the address request sent by the computing unit is received through the lookup table unit, and the address in the address request is converted into a target address that can access a valid storage control unit. Since the damaged storage control unit is skipped when accessing the memory based on the converted target address, it is guaranteed that the target storage control unit finally hit is intact, thereby ensuring that the access of computing units 0 to computing unit M-1 to the memory in the target storage control unit is reliable.
  • the crossbar switch is an M ⁇ N data path interconnection structure, and its function is to route the request to the target storage control unit according to the address request issued by the computing unit.
  • any computing unit from computing unit 0 to computing unit M-1 can access addresses in the range of 0 to (N*D-1).
  • computing unit 0 sends a memory access request to the cross switch.
  • the cross switch After receiving the access request sent by computing unit 0, the cross switch routes the address request to the target storage control unit based on the address in the access request, and then accesses the memory in the storage space managed by the target storage control unit based on the address in the access request.
  • the storage control unit can be repaired by using methods such as memory repair, for chips with integrated large-capacity storage, due to the large number of storage control units, the number of storage units they manage is even greater, the density is high, and the chip size is large, even after the memory repair, some storage control units may still be damaged. For all computing units, access to damaged storage control units is unreliable, so it is still difficult to improve the yield of the chip; and what is accessed is all the storage space managed by the storage control unit, which is less targeted and time-consuming.
  • the present application sets a cross switch to adopt a hierarchical structure, that is, a hierarchical modular design of the cross switch, which can adopt mesh (which may include the above-mentioned computing units and query units). table search unit) and the structure of the cross switch.
  • the hierarchical structure may adopt an interconnected two-layer structure, wherein the first layer structure is: a b ⁇ b crossbars; the second layer structure is: b a ⁇ (N/b) crossbars.
  • a, b, M, N, and N/b are all positive integers.
  • the present application proposes an address reconstruction method. Compared with the address reconstruction scheme in the related art, the present application directly configures the final routing information into the lookup table in the chip by the upper-layer software, specifically, performing routing calculation based on the hierarchical structure in the host computer, and directly configuring the calculation result into the chip's lookup table through a communication interface (such as an SPI interface).
  • a communication interface such as an SPI interface
  • Fig. 3 is a flow chart of a chip address reconstruction method according to an embodiment of the present application. The method can be executed by the above-mentioned chip, and the crossbar switch in the chip adopts a hierarchical structure.
  • the address reconstruction method of the chip includes:
  • the target storage control unit is a valid storage control unit, that is, an undamaged storage control unit; the storage space managed by each storage control unit may include one or more storage units.
  • the chip obtains address request information, parses the request address in the address request information, obtains initial routing information and an addressing address, then searches a preset mapping relationship configured in advance by a host computer to determine the target routing information corresponding to the initial routing information, which is used to characterize the effective storage control unit in the chip, and finally recombines the target routing information and the addressing address to obtain a target address, and accesses the target storage unit in the storage space managed by the target storage control unit based on the target address.
  • the chip can issue an address request through a computing unit, receive the address request information through a table lookup unit, and parse the request address in the address request information to obtain the parsed initial routing information and addressing address; then the table lookup unit searches for a preset mapping relationship pre-configured by the host computer, determines the target routing information corresponding to the initial routing information and used to characterize the effective storage control unit in the chip, and recombine the target routing information and addressing address to obtain the target address; finally, the table lookup unit sends the target address to a cross switch in a hierarchical structure, and the cross switch routes the target address to the target storage control unit to access the target storage unit.
  • the calculation unit, the lookup table unit and the cross switch may be any one of the calculation units shown in FIG. 1 , the lookup table unit corresponding to the any one of the calculation units and the cross switch with a hierarchical structure shown in FIG. 2 , respectively.
  • the lookup table unit can also be integrated into the cross switch as a sub-unit to communicate with the host computer and implement the above-mentioned conversion process from the request address to the target address, and the present application does not impose specific restrictions on this.
  • the address request is received through the cross switch, and the address request is parsed to obtain the parsed initial routing information and addressing address; then the target routing information corresponding to the initial routing information for characterizing the effective storage control unit in the chip is determined through the cross switch, and the target routing information and addressing address are recombined to obtain the target address; finally, the target address is routed to the target storage control unit through the cross switch to access the target storage unit.
  • the initial routing information and the addressing address are obtained, which is equivalent to parsing the request address to obtain the routing information of the storage control unit and the addressing address in the target storage control unit;
  • the preset mapping relationship configured by the host computer is searched to determine the target routing information corresponding to the initial routing information, which is equivalent to converting the initial routing information into the routing information of the effective storage control unit in the chip, and the calculation is completed in the host computer, so that even if the chip still has a damaged storage control unit after the memory is repaired, the memory access can skip the damaged storage control unit and access the target storage unit of the storage space managed by the effective storage control unit, and save chip computing resources; finally, based on the target routing information and the addressing address, the target address is determined, which can make the target storage control unit hit by the chip based on the target address during memory access intact, thereby ensuring that the memory access of the chip is reliable.
  • the address reconstruction method of the chip converts the request address into the target address by calling the preset mapping relationship configured by the upper computer, thereby ensuring access to a specific storage unit. At the same time, it can ensure that even if the chip has a damaged storage control unit after the memory is repaired, the memory access of the chip is reliable. That is, on the basis of ensuring the functionality and stability of the chip, the yield of chip mass production is improved and the computing resources of the chip can be saved.
  • the initial routing information is used to represent the routing information of the storage control unit, and the addressing address is the address in the target storage control unit.
  • the S302 may include: obtaining a valid addressing range of the chip; when the request address is within the valid addressing range of the chip, parsing the request address based on a preset addressing method to obtain the initial routing information and the addressing address.
  • the request address if the request address does not exceed the effective addressing range of the chip, the request address is split into two segments A and B according to the established preset addressing method, where A represents the initial routing information and B represents the addressing address.
  • the effective addressing range of the chip is used to represent the range of the storage space managed by the effective storage control unit in the chip.
  • the effective addressing range of the chip is 0 to (N*D-1).
  • the chip will re-encode the (N-Z) valid storage control units according to addresses 0 to (D*(N-Z)-1), that is, the maximum effective addressing range of the chip is 0 to (D*(N-Z)-1).
  • the preset addressing mode may include horizontal addressing or vertical addressing.
  • the preset addressing mode is horizontal addressing; wherein, S302 may include: modulo the request address with a first value to obtain the initial routing information, and using the ratio of the request address to the first value as the addressing address, wherein the first value is the number of valid storage control units in the chip.
  • the chip modulo the request address and the number of valid storage control units in the chip to obtain initial routing information, and calculates the ratio of the request address to the first value, and uses the ratio as the addressing address.
  • the chip has N storage control units in total and there is no damaged storage control unit, the number of valid storage control units in the chip is N.
  • the request address is addr_ori
  • the initial routing information A addr_ori% N
  • the addressing address B addr_ori/N. Since the value of A is addr_ori modulo N, the value of A is 0, 1, 2, 3, ..., N-1.
  • the initial routing information is obtained by taking the modulo N-Z of the request address, which is equivalent to, considering that the number of effective storage control units among the N storage control units is N-Z, by converting the routing information of N storage control units into the routing information of N-Z storage control units, the design complexity of the correspondence between the initial routing information and the target routing information can be reduced.
  • the preset addressing mode is vertical addressing; wherein, S302 may include: based on the chip bit width of the chip, determining a first bit in the request address for representing the initial routing information; and determining a value corresponding to the first bit as the initial routing information.
  • the chip determines the memory interval where the request address is located based on the bit width of the storage control unit, determines the first bit used to represent the initial routing information in the request address, and determines the value corresponding to the first bit as the initial routing information.
  • the method of obtaining the addressing address in this embodiment is the same as the method of obtaining the addressing address in the above-mentioned horizontal addressing, and will not be repeated here.
  • the chip width of the chip is 10 bits
  • the request address is 16 bits
  • the high 6 bits of the request address are the initial routing information.
  • the chip has a total of N storage control units, and there are Z damaged storage control units among the N storage control units, then for the vertical addressing method, it is equivalent to the addresses of all storage control units being connected end to end and continuous in the order of 0 to N-Z-1.
  • the preset mapping relationship includes a first sub-mapping relationship and a second sub-mapping relationship; wherein the first sub-mapping relationship includes at least one first routing information and at least one second routing information, at least one first routing information corresponds one-to-one to at least one second routing information, at least one first routing information includes initial routing information, and the second routing information is the routing information of the effective storage control unit in the chip; the second sub-mapping relationship includes at least one second routing information and at least one third routing information, at least one second routing information corresponds one-to-one to at least one third routing information, and at least one third routing information includes target routing information, wherein the third routing information is calculated by the upper computer based on the hierarchical structure for the second routing information corresponding to the third routing information, and is the routing information of the storage space managed by the corresponding effective storage control unit.
  • the chip first determines the second routing information corresponding to the initial routing information in the first sub-mapping relationship based on the first sub-mapping relationship; then determines the third routing information corresponding to the determined second routing information in the second sub-mapping relationship based on the second sub-mapping relationship as the target routing information.
  • the chip can also directly determine the third routing information corresponding to the initial routing information based on the preset mapping relationship, and use the third routing information as the target routing information.
  • the preset mapping relationship may be integrated into the chip in the form of a vocabulary file or in the form of a corresponding relationship graph.
  • the present application does not impose any specific limitation on the integration method of the first mapping relationship.
  • the third routing information corresponding to the initial routing information is determined through a preset mapping relationship, and the third routing information is determined as the target routing information, which is equivalent to using the preset mapping relationship to convert the initial routing information into routing information of the storage space managed by the effective storage control unit in the chip, so that even if the chip still has a damaged storage control unit after the memory is repaired, the memory access can skip the damaged storage control unit, ensuring that the target storage control unit hit during the memory access is intact and can access a specific storage unit, thereby ensuring that the memory access of the chip is reliable and targeted.
  • each first routing information and its corresponding second routing information are the same.
  • the first routing information and its corresponding third routing information are the same.
  • the routing information may also be different, as long as the second routing information corresponding to each first routing information is different from each other. This application does not impose any specific restrictions on this.
  • the value range of the initial routing information can be 0 to N-Z-1, that is, when the target routing information corresponding to the initial routing information is determined through a preset mapping relationship, the first routing information in the range of (N-Z) to (N-1) in the preset mapping relationship will not be accessed, so the third routing information corresponding to the first routing information in the range of (N-Z) to (N-1) is not concerned, and there is no need to reflect the third routing information corresponding to the first routing information in the range of (N-Z) to (N-1) in the preset mapping relationship, which can reduce the design complexity of the correspondence between the initial routing information and the target routing information.
  • the first mapping relationship when designing the first mapping relationship, it is only necessary to determine the third routing information corresponding to the first routing information in the range of 0 to N-Z-1 as the routing information of the effective storage control unit, and the second routing information corresponding to each first routing information in the range of 0 to N-Z-1 is different from each other.
  • the initial routing information is obtained by taking the modulus of the request address pair (N-Z)
  • the Z damaged storage control units are 1, 4, 5, 100, ... respectively
  • the damaged storage control units 1, 4, 5, 100, ... are removed from the N storage control units to obtain valid storage control units 0, 2, 3, 6 ... 99, 101, ..., N-1.
  • the initial routing information is obtained by taking the modulus of the request address pair (N-Z)
  • the first routing information in the range of (N-Z) to (N-1) in the preset mapping relationship will not be accessed, so the first routing information in the range of 0 to N-Z-1 is respectively corresponded to the routing information 0, 2, 3, 6 ... 99, 101, ..., N-1 of the valid storage control units.
  • first routing information and the second routing information are merely an example of the present application and should not be a limitation of the present application. In other alternative implementations, it is only necessary to determine the second routing information corresponding to each first routing information as the routing information of the effective control unit, and they are different from each other.
  • the design complexity of the first mapping relationship can be reduced on the basis of ensuring that the target storage control unit hit during memory access is intact.
  • the correspondence between the initial routing information and the target routing information is configured before obtaining the address request.
  • the host computer configures the correspondence between the initial routing information and the target routing information through the SPI interface.
  • the number of meshes corresponding to the input port of the first layer crossbar is The one-to-many route corresponding to the output port of the second-layer crossbar switch is 1toU.
  • the present application proposes a method for directly configuring the final routing information into a lookup table unit by upper-level software: three division and remainder operations are calculated in the host computer, and directly configured to the lookup table unit of the chip through the SPI interface.
  • the host computer may be triggered to update the preset mapping relationship every time the effective addressing range is updated.
  • the third routing information is composed of R1, R2, T1 and U mentioned above.
  • the corresponding D is 13’b00,000,100,00000, indicating that the mesh accessing the memory is numbered 13’b00
  • the first-level S ⁇ S cross switch is numbered 000
  • the second-level S ⁇ S cross switch is numbered 100
  • the router is numbered 00000, that is, the mesh numbered 13’b00 accesses the target storage unit managed by the storage control unit at address 0 through the first-level S ⁇ S cross switch numbered 000, the second-level S ⁇ S cross switch numbered 100, and the router numbered 00000.
  • the routing information D in Table 2 above is calculated by the upper-layer software (i.e., the host computer) and configured into the chip through the SPI interface.
  • the upper-layer software i.e., the host computer
  • a large amount of chip resources can be saved: for one computing unit, a set of divider and register resources can be saved, and for M computing units, M times of resources can be saved.
  • the size of the serial numbers of the above-mentioned processes does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
  • FIG4 is a structural block diagram of an address reconstruction device of a chip according to an embodiment of the present application, wherein the crossbar switch in the chip adopts a hierarchical structure.
  • the address reconstruction device 400 of the chip may include:
  • An acquiring unit 410 is configured to acquire address request information, wherein the address request information includes a request address;
  • a parsing unit 420 configured to parse the request address to obtain initial routing information and an addressing address
  • a table lookup unit 430 is used to look up a preset mapping relationship to obtain target routing information corresponding to the initial routing information, wherein the preset mapping relationship is obtained by the host computer based on the hierarchical structure and configured in the chip;
  • the determination unit 440 is used to determine a target address based on the target routing information and the addressing address, wherein the target address is used to access a target storage unit in a storage space managed by a target storage control unit in the chip.
  • the parsing unit 420 may be specifically used to: obtain the effective addressing range of the chip; when the request address is within the effective addressing range of the chip, parse the request address based on the first addressing method to obtain initial routing information and addressing address.
  • the parsing unit 420 may be specifically used for:
  • the request address is modulo the first value to obtain initial routing information, and the ratio of the request address to the first value is used as the addressing address, wherein the first value is the number of effective storage control units in the chip.
  • the preset mapping relationship includes a first sub-mapping relationship and a second sub-mapping relationship; wherein the first sub-mapping relationship includes at least one first routing information and at least one second routing information, at least one first routing information corresponds one-to-one to at least one second routing information, at least one first routing information includes initial routing information, and the second routing information is the routing information of the effective storage control unit in the chip; the second sub-mapping relationship includes at least one second routing information and at least one third routing information, at least one second routing information corresponds one-to-one to at least one third routing information, and at least one third routing information includes target routing information, wherein the third routing information is calculated by the upper computer based on the hierarchical structure for the second routing information corresponding to the third routing information, and is the routing information of the storage space managed by the corresponding effective storage control unit.
  • the hierarchical structure adopts an interconnected two-layer structure, wherein the first layer structure is: a b ⁇ b crossbars; the second layer structure is: b a ⁇ (N/b) crossbars.
  • a, b, M, N, and N/b are all positive integers.
  • the preset mapping relationship is configured in the chip by a host computer through a serial peripheral interface SPI.
  • the device embodiment and the method embodiment may correspond to each other, and similar descriptions may refer to the method embodiment. To avoid repetition, they are not described here.
  • the aforementioned and other operations and/or functions of each module in the device 400 are respectively for implementing the corresponding processes in the method shown in FIG3, and for the sake of brevity, they are not described here.
  • the various units in the device 400 involved in the embodiment of the present application can be separately or completely combined into one or more other units to constitute, or one (some) of the units can be further divided into multiple functionally smaller units to constitute, which can achieve the same operation without affecting the realization of the technical effects of the embodiments of the present application.
  • the above units are divided based on logical functions. In actual applications, the function of one unit can also be implemented by multiple units, or the functions of multiple units can be implemented by one unit. In other embodiments of the present application, the chip 400 can also be Including other units, in practical applications, these functions can also be implemented with the assistance of other units, and can be implemented by multiple units working together.
  • the chip 400 involved in the embodiment of the present application can be constructed by running a computer program (including program code) capable of executing each step involved in the corresponding method on a general-purpose computing device of a general-purpose computer including processing elements and storage elements such as a central processing unit (CPU), a random access storage medium (RAM), and a read-only storage medium (ROM), and the address reconstruction method of the chip in the embodiment of the present application can be implemented.
  • the computer program can be recorded on, for example, a computer-readable storage medium, and loaded into an electronic device through a computer-readable storage medium, and run therein to implement the corresponding method of the embodiment of the present application.
  • each step of the method embodiment in the embodiment of the present application can be completed by an integrated logic circuit of hardware in a processor and/or an instruction in software, and the steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or by a combination of hardware and software in a decoding processor.
  • the software may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiment in combination with its hardware.
  • FIG. 5 is a structural block diagram of an electronic device according to an embodiment of the present application.
  • the electronic device 500 at least includes a processor 510 and a computer-readable storage medium 520.
  • the processor 510 and the computer-readable storage medium 520 may be connected via a bus or other means.
  • the computer-readable storage medium 520 is used to store a computer program 521, which includes computer instructions, and the processor 510 is used to execute the computer instructions stored in the computer-readable storage medium 520.
  • the processor 510 is the computing core and control core of the electronic device 500, which is suitable for implementing one or more computer instructions, and is specifically suitable for loading and executing one or more computer instructions to implement the corresponding method flow or corresponding function.
  • the processor 510 may also be referred to as a central processing unit (CPU).
  • the processor 510 may include, but is not limited to, a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the computer-readable storage medium 520 can be a high-speed RAM memory, or a non-volatile memory, such as at least one disk storage; it can also be at least one computer-readable storage medium located away from the aforementioned processor 510.
  • the computer-readable storage medium 520 includes, but is not limited to: a volatile memory and/or a non-volatile memory.
  • the non-volatile memory can be a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, or a flash memory.
  • the volatile memory can be a random access memory, which is used as an external high-speed cache.
  • RAM random access memory
  • static random access memory dynamic random access memory
  • dynamic random access memory synchronous dynamic random access memory
  • double data rate synchronous random access memory etc.
  • Dynamic Random Access Memory Enhanced Synchronous Dynamic Random Access Memory, Synchronously Attached Dynamic Random Access Memory, and Direct Memory Bus Random Access Memory.
  • the electronic device 500 may include the device 400 shown in Figure 4; the computer-readable storage medium 520 stores computer instructions; the processor 510 loads and executes the computer instructions stored in the computer-readable storage medium 520 to implement the corresponding steps in the method embodiment shown in Figure 3; in a specific implementation, the computer instructions in the computer-readable storage medium 520 are loaded by the processor 510 and the corresponding steps are executed. To avoid repetition, they are not repeated here.
  • the embodiment of the present application also provides a computer-readable storage medium, which is a memory device in the electronic device 500 for storing programs and data.
  • a computer-readable storage medium 520 is a memory device in the electronic device 500 for storing programs and data.
  • a computer-readable storage medium 520 can include both the built-in storage medium in the electronic device 500 and the extended storage medium supported by the electronic device 500.
  • the computer-readable storage medium provides a storage space, which stores the operating system of the electronic device 500.
  • one or more computer instructions suitable for being loaded and executed by the processor 510 are also stored in the storage space. These computer instructions can be one or more computer programs 521 (including program codes).
  • the electronic device 500 may further include a transceiver 530 , which may be connected to the processor 510 or the computer-readable storage medium 520 .
  • the computer-readable storage medium 520 may control the transceiver 530 to communicate with other devices, specifically, to send information or data to other devices, or to receive information or data sent by other devices.
  • the transceiver 530 may include a transmitter and a receiver.
  • the transceiver 530 may further include an antenna, and the number of antennas may be one or more.
  • the present application also provides a computer program product or a computer program, which includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium.
  • a computer program 521 the electronic device 500 can be a computer, and the processor 510 reads the computer instruction from the computer-readable storage medium 520, and the processor 510 executes the computer instruction, so that the computer executes the chip address reconstruction method provided in the above various optional ways.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices.
  • the computer instruction can be stored in a computer-readable storage medium, or transmitted from a computer-readable storage medium to another computer-readable storage medium, for example, the computer instruction can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line, etc.) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center.
  • wired e.g., coaxial cable, optical fiber, digital subscriber line, etc.
  • wireless e.g., infrared, wireless, microwave, etc.

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Abstract

一种芯片的地址重构方法、装置以及电子设备、存储介质，涉及芯片技术领域，芯片内的交叉开关采用分层结构，方法包括：获取地址请求信息，其中，地址请求信息包括请求地址；对请求地址进行解析，得到初始路由信息和寻址地址；查找预设映射关系，得到与初始路由信息对应的目标路由信息，其中，预设映射关系由上位机基于分层结构得到；基于目标路由信息和寻址地址，确定目标地址，其中，目标地址用于访问芯片内目标存储控制单元所管理的存储空间中的目标存储单元。

Description

芯片的地址重构方法、装置以及电子设备、存储介质
相关申请的交叉引用
本申请要求于2022年10月09日提交的申请号为202211225064.2、名称为“芯片的地址重构方法、装置以及电子设备、存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种芯片的地址重构方法、装置以及电子设备、存储介质。
背景技术
随着半导体制造和计算机技术的发展，越来越多的芯片设计有高带宽的、大容量的内存计算需求。拥有大容量的芯片，采用的设计方法有：1)大量使用DRAM(Dynamic Random Access Memory，动态随机存取存储器)；2)采用先进封装工艺，比如HBM(High Band width Memory，高带宽内存)、3D IC芯片，这类芯片共同的特点是：存储控制单元数量多，存储单元数量更多，存储密度大。它们面临的相同的问题是：受工艺制造限制，存储控制单元的良率低，导致芯片良率低。其中，存储单元的数量和密度越大，良率越低。
为了解决存储良率问题，相关技术中采用memory repair(记忆修复)的方式，但是此方法修复的行列是有限的，并不能将芯片完全修复，且存储控制单元数量多，出现坏存储控制单元的概率极高。另外，还有相关技术中采用地址重构的方式，但该方式对芯片的存储容量或结构有限制，理由是：对于大容量存储的芯片，每个存储控制单元所管理的存储空间可能包括多个存储单元，而采用该方式在内存访问时，是直接访问存储控制单元所管理的所有存储单元，针对性差，且若每个存储控制单元仅管理一个存储单元，那么访问就需要使用大量芯片内部的计算资源，此时会面临处理数据产生延时问题。
发明内容
本申请的目的在于提出一种芯片的地址重构方法、装置以及电子设备、存储介质。
第一方面，本申请提出了一种芯片的地址重构方法，所述芯片内的交叉开关采用分层结构，所述方法包括：获取地址请求信息，其中，所述地址请求信息包括请求地址；对所述请求地址进行解析，得到初始路由信息和寻址地址；查找预设映射关系，得到与所述初始路由信息对应的目标路由信息，其中，所述预设映射关系由上位机基于所述分层结构得 到；基于所述目标路由信息和所述寻址地址，确定目标地址，其中，所述目标地址用于访问所述芯片内的目标存储控制单元所管理的存储空间中的目标存储单元。
第二方面，本申请提出了一种芯片的地址重构装置，所述芯片内的交叉开关采用分层结构，所述装置包括：获取单元，用于获取地址请求信息，其中，所述地址请求信息包括请求地址；解析单元，用于对所述请求地址进行解析，得到初始路由信息和寻址地址；查表单元，用于查找预设映射关系，得到与所述初始路由信息对应的目标路由信息，其中，所述预设映射关系由上位机基于所述分层结构得到；确定单元，用于基于所述目标路由信息和所述寻址地址，确定目标地址，其中，所述目标地址用于访问所述芯片内目标存储控制单元所管理的存储空间中的目标存储单元。
第三方面，本申请提出一种电子设备，包括：处理器，适于执行计算机程序；计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，该计算机程序被该处理器执行时，实现上述芯片的地址重构方法。
第四方面，本申请提出了一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序，该计算机程序被处理器执行时，实现上述芯片的地址重构方法。
本申请实施例的芯片的地址重构方法、装置以及电子设备、存储介质，通过对请求地址进行解析，得到初始路由信息和寻址地址，并通过查找上位机配置的预设映射关系，确定与该初始路由信息对应的目标路由信息，即得到芯片内有效存储控制单元所管理存储空间的路由信息，能够对存储单元进行针对性访问，且节省芯片计算资源，同时使芯片即使在内存修复后，仍然存在损坏的存储控制单元的情况时，内存访问可以跳过损坏的存储控制单元，访问有效存储控制单元；基于该目标路由信息和该寻址地址，确定目标地址，能够使芯片基于目标地址在内存访问时所命中的目标存储控制单元是完好的，进而保证芯片的内存访问是可靠的。
附图说明
图1是本申请一个示例的芯片的结构框图；
图2是本申请一个示例的交叉开关的结构示意图；
图3是本申请实施例的芯片的地址重构方法的流程图；
图4是本申请实施例的芯片的地址重构装置的结构框图；
图5是本申请实施例的电子设备的结构框图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同 或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性地，旨在用于解释本申请，而不能理解为对本申请的限制。
首先对通用的集成大容量存储的芯片的结构进行举例说明。
图1是本申请一个示例的芯片的结构框图。
如图1所示，该芯片100为集成大容量存储芯片，可包括：计算单元0～计算单元M-1、存储控制单元0～存储控制单元N-1、查找表单元0～查找表单元M-1、交叉开关；其中，M和N均为大于或等于1的整数。
计算单元0～计算单元M-1表示该芯片100集成了M个计算单元，其中，M个计算单元中的每个计算单元有访问内存的需求。
存储控制单元0～存储控制单元N-1表示该芯片100集成了N个存储控制单元，其中，N个存储控制单元中的每个存储控制单元管理了芯片100内的一段存储空间；若每段存储空间的地址深度均为D，则整个芯片100最大的可寻址的地址范围为0～(N*D-1)。
查找表单元0～查找表单元M-1为M个完全相同的查找表单元，其中，每个计算单元配套1个查找表单元，通过配套的查找表单元对计算单元发出的地址进行地址转换。
通过查找表单元接收计算单元发送的地址请求，并将该地址请求中的地址转换为可访问有效存储控制单元的目标地址，由于基于转换后的目标地址在访问内存时，会跳过损坏的存储控制单元，保证最终所命中的目标存储控制单元是完好的，从而保证计算单元0～计算单元M-1，对目标存储控制单元中内存的访问是可靠的。
交叉开关，是一个M×N的数据通路互联结构，其作用是，根据计算单元发出的地址请求，将请求路由到目标存储控制单元。
在本申请中，计算单元0～计算单元M-1中的任意一个计算单元，都可以访问0～(N*D-1)范围内的地址。
示例性地，计算单元0向交叉开关发送内存的访问请求，交叉开关接收到该计算单元0发送的访问请求后，基于该访问请求中的地址，将该地址请求路由到目标存储控制单元，进而基于该访问请求中的地址访问目标存储控制单元所管理的存储空间中的内存。
由于受到制造工艺的制约，尽管采用内存修复等方式，可以对存储控制单元进行修复，但是对于集成大容量存储的芯片来说，由于存储控制单元数量大，其管理的存储单元数量更大，密度高，芯片的尺寸大，即使进行内存修复之后，仍有可能部分存储控制单元是损坏的。而针对所有的计算单元，对存在损坏的存储控制单元的访问是不可靠的，所以，导致芯片的良率仍然难以提升；并且，访问的是存储控制单元管理的所有存储空间，针对性差，耗时长。为此，相较于相关技术中芯片的地址重构方案，本申请设置交叉开关采用分层结构，即对交叉开关进行分层的模块化设计，可采用mesh(可包括上述的计算单元和查 找表单元)和交叉开关的结构。
示例性地，如图2所示，分层结构可采用互联的两层结构，其中，第一层结构为：a个b×b结构的交叉开关；第二层结构为：b个a×(N/b)结构的交叉开关。其中，第一层结构的输出口数量为a×b＝M，第二层结构的输入口数量为b×a＝M，a、b、M、N、N/b均为正整数。
由于大型的交叉开关的分层结构中，需要使用大量芯片内部的计算资源，可能会面临处理数据产生延时问题。为此，基于交叉开关采用分层结构的芯片100，本申请提出了一种地址重构方法。相较于相关技术中的地址重构方案，本申请由上层软件直接将最终路由信息配置到芯片内的查找表中，具体为在上位机中基于分层结构进行路由计算，并将计算结果通过通信接口(如SPI接口)直接配置到芯片的查找表中。
图3是本申请实施例的芯片的地址重构方法的流程图。该方法可由上述的芯片执行，且芯片内的交叉开关采用分层结构。
如图3所示，该芯片的地址重构方法包括：
S301，获取地址请求信息，其中，地址请求信息包括请求地址。
S302，对请求地址进行解析，得到初始路由信息和寻址地址。
S303，查找预设映射关系，得到与初始路由信息对应的目标路由信息，其中，预设映射关系由上位机基于分层结构得到并配置在芯片中。
S304，基于目标路由信息和该寻址地址，确定目标地址，其中，目标地址用于访问该目标存储控制单元所管理的存储空间中的目标存储单元。
其中，目标存储控制单元为有效存储控制单元，即未损坏的存储控制单元；每个存储控制单元所管理的存储空间可包括一个或多个存储单元。
具体地，芯片获取地址请求信息，通过对地址请求信息中的请求地址进行解析，得到初始路由信息和寻址地址，再查找预先由上位机配置的预设映射关系确定与该初始路由信息对应的，用于表征芯片内有效存储控制单元的目标路由信息，最后将目标路由信息和该寻址地址重新组合，得到目标地址，并基于该目标地址访问目标存储控制单元管理的存储空间中的目标存储单元。
示例性地，该芯片可通过计算单元发出地址请求，通过查找表单元接收该地址请求信息，并对该地址请求信息中的请求地址进行解析，得到解析后的初始路由信息和寻址地址；再通过查找表单元查找预先由上位机配置的预设映射关系，确定与初始路由信息对应的用于表征该芯片内有效存储控制单元的目标路由信息，并对目标路由信息和寻址地址进行重新组合，得到目标地址；最后，通过查找表单元将目标地址发送给分层结构的交叉开关，通过交叉开关将目标地址路由到目标存储控制单元访问目标存储单元。需要说明的是，该 计算单元、查找表单元和交叉开关分别可以是图1所示的任意一个计算单元、和该任意一个计算单元对应的查找表单元以及图2所示的采用分级结构的交叉开关。
当然，在本申请其他可替代的实施例中，该查找表单元也可以集成在交叉开关中，作为一个子单元，与上位机通信，并实现上述请求地址到目标地址的转换过程，本申请对此不做具体限制。示例性地，该芯片通过计算单元发出地址请求后，通过交叉开关接收到该地址请求，并对该地址请求进行解析，得到解析后的初始路由信息和寻址地址；再通过交叉开关确定与该初始路由信息对应的用于表征该芯片内有效存储控制单元的目标路由信息，并对目标路由信息和寻址地址进行重新组合，得到目标地址；最后，通过交叉开关将目标地址路由到目标存储控制单元访问目标存储单元。
基于以上技术方案，首先，通过对请求地址进行解析，得到初始路由信息和寻址地址，相当于，对请求地址进行解析，得到存储控制单元的路由信息和目标存储控制单元内的寻址地址；其次，查找上位机配置的预设映射关系，确定与该初始路由信息对应的目标路由信息，相当于，将初始路由信息转化为芯片内有效存储控制单元的路由信息，且计算在上位机完成，能够使芯片即使在内存修复后，仍然存在损坏的存储控制单元的情况时，内存访问可以跳过损坏的存储控制单元，访问有效存储控制单元所管理存储空间的目标存储单元，且节省芯片计算资源；最后，基于该目标路由信息和该寻址地址，确定目标地址，能够使芯片基于目标地址在内存访问时所命中的目标存储控制单元是完好的，进而保证芯片的内存访问是可靠的。
此外，由于该类芯片即使在内存修复后，仍然存在损坏的存储控制单元的情况时，基于目标地址进行内存访问，使得芯片也能可靠工作，即保证了芯片的功能性和稳定性，所以，该类芯片也不会归类为坏片，从而提升了芯片量产的良率。并且，路由计算在上位机完成，可节省芯片的计算资源。
简言之，本申请提供的芯片的地址重构方法，通过调用上位机配置的预设映射关系，将请求地址转换为目标地址，能够保证访问到具体的存储单元，同时能够保证芯片即使在内存修复后，仍然存在有损坏的存储控制单元的情况时，芯片的内存访问也是可靠的，即在保证芯片的功能性和稳定性的基础上，提升了芯片量产的良率，且能够节省芯片的计算资源。
需要说明的是，该初始路由信息用于表征存储控制单元的路由信息，该寻址地址为目标存储控制单元内的地址。
在本申请的一些实施例中，该S302可包括：获取芯片的有效寻址范围；当该请求地址在芯片的有效寻址范围内时，基于预设寻址方式对该请求地址进行解析，得到该初始路由信息和该寻址地址。
换言之，若请求地址未超过该芯片的有效寻址范围，则按照既定的预设寻址方式将请求地址拆分成两段A和B，其中，A表示初始路由信息，B表示寻址地址。其中，芯片的有效寻址范围用于表征该芯片内有效存储控制单元所管理的存储空间的范围。
示例性地，若该芯片共有N个存储控制单元，且无损坏的存储控制单元，其中，N个存储控制单元中的每个存储控制单元管理的存储空间的地址深度为D，则该芯片的有效寻址范围是0～(N*D-1)。
示例性地，若该芯片共有N个存储控制单元，且N个存储控制单元中存在Z个损坏的存储控制单元，其中，N个存储控制单元中的每个存储控制单元管理的存储空间的地址深度为D，则芯片会将(N-Z)个有效存储控制单元，按照0～(D*(N-Z)-1)地址重新编码，即该芯片最大的有效寻址范围是0～(D*(N-Z)-1)。
在申请中，预设寻址方式可包括横向寻址或纵向寻址。
在一些实施例中，预设寻址方式为横向寻址；其中，该S302可包括：将请求地址对第一数值取余，得到该初始路由信息，并将请求地址与第一数值的比值作为寻址地址，其中，第一数值为该芯片内有效存储控制单元的数量。
换言之，若预设寻址方式为横向寻址，则芯片将请求地址对芯片内有效存储控制单元的数量进行取余，得到初始路由信息，并计算请求地址与第一数值的比值，将该比值作为寻址地址。
示例性地，若该芯片共有N个存储控制单元，且无损坏的存储控制单元时，则芯片内有效存储控制单元的数量为N，当请求地址为addr_ori，则初始路由信息A＝addr_ori％N，寻址地址B＝addr_ori/N。其中，由于A的值为addr_ori对N取余，所以A的值为0,1,2,3,……,N-1。
示例性地，若该芯片共有N个存储控制单元，且N个存储控制单元中存在Z个损坏的存储控制单元，则芯片内有效存储控制单元的数量为N-Z，当请求地址为addr_ori，则初始路由信息A＝addr_ori％(N-Z)，寻址地址B＝addr_ori/(N-Z)。其中，由于A的值为addr_ori对(N-Z)取余，所以A的值为0,1,2,3,……,N-Z-1。
通过将请求地址对N-Z取余得到初始路由信息，相当于，考虑到N个存储控制单元中有效存储控制单元的个数为N-Z个，通过将N个存储控制单元的路由信息转换为N-Z个存储控制单元的路由信息，能够降低初始路由信息和目标路由信息之间的对应关系的设计复杂度。
在另一些实施例中，该预设寻址方式为纵向寻址；其中，该S302可包括：基于该芯片的芯片位宽，在该请求地址中确定用于表征该初始路由信息的第一比特位；将该第一比特位对应的数值，确定为该初始路由信息。
换言之，若预设寻址方式为纵向寻址，则芯片基于存储控制单元的位宽，对请求地址所在的内存区间进行判断，在请求地址中确定用于表征该初始路由信息的第一比特位，并将第一比特位对应的数值，确定为初始路由信息。需要说明的是，该实施例中获取寻址地址的方式，与上述横向寻址中获取寻址地址的方式相同，此处不做赘述。
示例性地，若芯片内每个存储空间的地址深度的取值范围是0～1023，则该芯片的芯片位宽为10bit，且当请求地址为16bit时，则请求地址的高6bit即为初始路由信息。
需要说明的是，若该芯片共有N个存储控制单元，且N个存储控制单元中存在Z个损坏的存储控制单元，则对于纵向寻址的方式，相当于所有存储控制单元的地址，按照0～N-Z-1的顺序，首尾相接且连续。
在本申请的一些实施例中，预设映射关系包括第一子映射关系和第二子映射关系；其中，第一子映射关系包括至少一个第一路由信息和至少一个第二路由信息，至少一个第一路由信息与至少一个第二路由信息一一对应，至少一个第一路由信息包括初始路由信息，第二路由信息为芯片内有效存储控制单元的路由信息；第二子映射关系包括至少一个第二路由信息和至少一个第三路由信息，至少一个第二路由信息与至少一个第三路由信息一一对应，至少一个第三路由信息包括目标路由信息，其中，第三路由信息由上位机基于分层结构对该第三路由信息对应的第二路由信息计算得到，为对应有效存储控制单元所管理存储空间的路由信息。
换言之，芯片首先基于第一子映射关系，确定第一子映射关系中与初始路由信息对应的第二路由信息；再基于第二子映射关系，确定第二子映射关系中与确定的第二路由信息对应的第三路由信息，作为目标路由信息。当然，芯片也可基于预设映射关系，直接确定与初始路由信息对应的第三路由信息，将该第三路由信息作为目标路由信息。
在示例性实施方式中，该预设映射关系可以以词表文件的方式集成在芯片中，也可以以对应关系图的方式集成在芯片中，本申请对第一映射关系的集成方式不作具体限制。
通过预设映射关系确定与该初始路由信息对应的第三路由信息，并将该第三路由信息，确定为目标路由信息，相当于，利用预设映射关系，将初始路由信息转化为芯片内有效存储控制单元所管理存储空间的路由信息，能够使芯片即使在内存修复后，仍然存在损坏的存储控制单元的情况时，内存访问也可以跳过损坏的存储控制单元，保证内存访问时所命中的目标存储控制单元是完好的，且能访问到具体的存储单元，进而保证芯片的内存访问是可靠的、针对性的。
示例性地，芯片共有N个存储控制单元、且芯片内无损坏的存储控制单元时，每一个第一路由信息和其对应的第二路由信息的均相同。当然，在其他可替代的实现方式中，当芯片共有N个存储控制单元，且无损坏的存储控制单元时，第一路由信息和其对应的第三 路由信息也可以不同，只需满足每一个第一路由信息对应的第二路由信息互不相同即可，本申请对此不作具体限制。
示例性地，芯片共有N个存储控制单元、且芯片内存在Z个损坏的存储控制单元时，若初始路由信息为请求地址对(N-Z)取余得到的，则初始路由信息的数值范围可以是0～N-Z-1，即在通过预设映射关系确定初始路由信息对应的目标路由信息时，预设映射关系中(N-Z)～(N-1)范围内的第一路由信息不会被访问到，所以对(N-Z)～(N-1)范围内的第一路由信息分别对应的第三路由信息也并不关心，无需在预设映射关系中体现(N-Z)～(N-1)范围内的第一路由信息分别对应的第三路由信息，能够降低初始路由信息和目标路由信息之间的对应关系的设计复杂度。
简言之，在设计第一映射关系时只需将0～N-Z-1范围内的第一路由信息分别对应的第三路由信息，确定为有效存储控制单元的路由信息、且0～N-Z-1范围内的每一个第一路由信息分别对应的第二路由信息互不相同。
示例性地，当初始路由信息为请求地址对(N-Z)取余得到的，且该Z个损坏的存储控制单元分别为1,4,5,100,…时，从N个存储控制单元中去除损坏的存储控制单元1,4,5,100,…，得到有效的存储控制单元0,2,3,6…99,101,…,N-1，又由于初始路由信息为请求地址对(N-Z)取余得到的，则预设映射关系中(N-Z)～(N-1)范围内的第一路由信息不会被访问到，所以将0～N-Z-1范围内的第一路由信息分别对应有效存储控制单元的路由信息0,2,3,6…99,101,…,N-1。
需要说明的是，第一路由信息和第二路由信息之间的对应关系，仅仅为本申请的示例，不应为本申请的限制，在其他可替代的实现方式中，只需将每一个第一路由信息对应的第二路由信息，确定为有效控制单元的路由信息、且互不相同即可。
通过将请求地址对(N-Z)取余，得到初始路由信息，再基于预设映射关系，确定与初始路由信息对应的目标路由信息，能够在保证内存访问时所命中的目标存储控制单元是完好的基础上，降低第一映射关系的设计复杂度。
在本申请的一些实施例中，该初始路由信息和该目标路由信息的对应关系是在获取该地址请求前配置的。
示例性地，在芯片通过计算单元发送内存访问需求前，由上位机通过SPI接口配置初始路由信息和该目标路由信息的对应关系。
下面结合图2，说明本申请中预设映射关系的得到方式：
如图2所示，访问所述芯片存储单元的mesh数量为R，a＝T，b＝S，N/b＝T，每个存储控制单元通过U个路由器管理相应存储空间中的U个存储单元，即第一层结构中采用S×S交叉开关，第二层结构中采用T×T交叉开关，第一层交叉开关的输入口对应的mesh个数 为R，第二层交叉开关输出口对应的1对多的路由为1toU。
mesh的寻址方法是：根据路由信息C(即第二路由信息)计算可得每个mesh的编号R1＝C％R，将路由信息C转化到每个mesh内的路由信息R2＝C/R。第一层结构中，每个S×S的交叉开关含有S个输入端口和S个输出端口；其寻址方法是：每个S×S的交叉开关的编号S1＝R2％S，一个S×S的交叉开关的端口的路由信息由R2转化为S2＝S1/S。第二层结构中，每个T×T的交叉开关含有T个输入端口和T个输出端口；每个T×T的交叉开关的编号为T1＝S2％T。1对U的路由器，每个路由器的编号为U＝S2/T。
从上述路由信息的公式推导可以看出，需要经过三次除法和求余运算才能得到最终的路由信息(即第三路由信息)，在电路设计中，为了满足设计时序，在每个除法计算之间都要插入足够多的寄存器。为此，本申请提出一种由上层软件直接将最终路由信息配置到查找表单元中的方法：在上位机中计算三次除法和求余运算，通过SPI接口直接配置到芯片的查找表单元。
在示例性实施方式中，为保证芯片访问的可靠性，可在每当有效寻址范围更新时，触发上位机进行预设映射关系的更新。
示例性地，查找表单元的配置信息如下：以120x3000的交叉开关的情况来设计查找表，假设R＝4,S＝6,T＝5,U＝25，对于转换后的路由信息D(即第三路由信息)的排列格式如下表1：
表1
参见表1，第三路由信息由上述的R1、R2、T1和U组成。
由存储控制单元的路由信息A转换得到的中间路由信息C的对应关系，以及由中间转换的路由信息C与最终转换后的路由信息D的对应关系，即预设映射关系，如下表2：
表2

参见表2，A＝0，C＝0时，对应的D为13’b00,000,100,00000，表示访问内存的mesh的编号为13’b00，一级S×S交叉开关的编号为000，二级S×S交叉开关的编号为100，路由器的编号为00000，即编号为13’b00的mesh，依次通过编号为000的一级S×S交叉开关、编号为100的二级S×S交叉开关和编号为00000的路由器，访问0地址的存储控制单元管理的目标存储单元。
上表2中的路由信息D，是经过上层软件(即上位机)计算得到，并通过SPI接口配置到芯片中的。由此，可以节省大量的芯片资源：对于一个计算单元，可以节省一套除法器和寄存器资源，对于M个计算单元可以节省M倍的资源。
还应理解，在本申请的各种方法实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
下面对本申请实施例提供的装置进行说明。
图4是本申请实施例的芯片的地址重构装置的结构框图，芯片内的交叉开关采用分层结构。
如图4所示，该芯片的地址重构装置400可包括：
获取单元410，用于获取地址请求信息，其中，地址请求信息包括请求地址；
解析单元420，用于对请求地址进行解析，得到初始路由信息和寻址地址；
查表单元430，用于查找预设映射关系，得到与初始路由信息对应的目标路由信息，其中，预设映射关系由上位机基于分层结构得到并配置在芯片中；
确定单元440，用于基于目标路由信息和寻址地址，确定目标地址，其中，目标地址用于访问芯片内目标存储控制单元所管理的存储空间中的目标存储单元。
在本申请的一些实施例中，解析单元420可具体用于：获取芯片的有效寻址范围；当请求地址在芯片的有效寻址范围内时，基于第一寻址方式对请求地址进行解析，得到初始路由信息和寻址地址。
在本申请的一些实施例中，第一寻址方式为横向寻址时，解析单元420可具体用于： 将请求地址对第一数值取余，得到初始路由信息，并将请求地址与第一数值的比值作为寻址地址，其中，第一数值为芯片内有效存储控制单元的数量。
在本申请的一些实施例中，预设映射关系包括第一子映射关系和第二子映射关系；其中，第一子映射关系包括至少一个第一路由信息和至少一个第二路由信息，至少一个第一路由信息与至少一个第二路由信息一一对应，至少一个第一路由信息包括初始路由信息，第二路由信息为芯片内有效存储控制单元的路由信息；第二子映射关系包括至少一个第二路由信息和至少一个第三路由信息，至少一个第二路由信息与至少一个第三路由信息一一对应，至少一个第三路由信息包括目标路由信息，其中，第三路由信息由上位机基于分层结构对该第三路由信息对应的第二路由信息计算得到，为对应有效存储控制单元所管理存储空间的路由信息。
在本申请的一些实施例中，分层结构采用互联的两层结构，其中，第一层结构为：a个b×b结构的交叉开关；第二层结构为：b个a×(N/b)结构的交叉开关。其中，第一层结构的输出口数量为a×b＝M，第二层结构的输入口数量为b×a＝M，a、b、M、N、N/b均为正整数。
进一步地，在本申请的一些实施例中，当访问所述芯片存储单元的mesh数量为R，a＝T，b＝S，N/b＝T，每个存储控制单元通过U个路由器管理相应存储空间中的U个存储单元时，每个mesh的编号为R1＝C％R，每个mesh的路由信息为R2＝C/R，其中，C为所述第二路由信息；每个S×S交叉开关的编号S1＝R2％S，每个S×S交叉开关端口的路由信息为S2＝S1/S；每个T×T交叉开关的编号为T1＝S2％T；路由器的编号为U＝S2/T；其中，所述第三路由信息由R1、R2、T1和U组成。
在本申请的一些实施例中，预设映射关系由上位机通过串行外设接口SPI配置在芯片中。
在本申请的一些实施例中，装置400还可包括：更新单元，用于在芯片内的存储控制单元存在损坏时，对芯片的有效地址进行重新编码，以更新芯片的有效寻址范围。
应理解，装置实施例与方法实施例可以相互对应，类似的描述可以参照方法实施例。为避免重复，此处不再赘述。具体地，该装置400中的各个模块的前述和其它操作和/或功能分别为了实现图3所示的方法中的相应流程，为了简洁，在此不再赘述。
还应当理解，本申请实施例涉及的该装置400中的各个单元可以分别或全部合并为一个或若干个另外的单元来构成，或者其中的某个(些)单元还可以再拆分为功能上更小的多个单元来构成，这可以实现同样的操作，而不影响本申请的实施例的技术效果的实现。上述单元是基于逻辑功能划分的，在实际应用中，一个单元的功能也可以由多个单元来实现，或者多个单元的功能由一个单元实现。在本申请的其它实施例中，该芯片400也可以 包括其它单元，在实际应用中，这些功能也可以由其它单元协助实现，并且可以由多个单元协作实现。根据本申请的另一个实施例，可以通过在包括例如中央处理单元(CPU)、随机存取存储介质(RAM)、只读存储介质(ROM)等处理元件和存储元件的通用计算机的通用计算设备上运行能够执行相应方法所涉及的各步骤的计算机程序(包括程序代码)，来构造本申请实施例涉及的该芯片400，以及来实现本申请实施例的芯片的地址重构方法。其中，计算机程序可以记载于例如计算机可读存储介质上，并通过计算机可读存储介质装载于电子设备中，并在其中运行，来实现本申请实施例的相应方法。
换言之，上文涉及的单元可以通过硬件形式实现，也可以通过软件形式的指令实现，还可以通过软硬件结合的形式实现。具体地，本申请实施例中的方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路和/或软件形式的指令完成，结合本申请实施例公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件组合执行完成。
在示例性实施方式中，软件可以位于随机存储器，闪存、只读存储器、可编程只读存储器、电可擦写可编程存储器、寄存器等本领域的成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法实施例中的步骤。
图5是本申请实施例的电子设备的结构框图。
如图5所示，该电子设备500至少包括处理器510以及计算机可读存储介质520。其中，处理器510以及计算机可读存储介质520可通过总线或者其它方式连接。计算机可读存储介质520用于存储计算机程序521，计算机程序521包括计算机指令，处理器510用于执行计算机可读存储介质520存储的计算机指令。处理器510是电子设备500的计算核心以及控制核心，其适于实现一条或多条计算机指令，具体适于加载并执行一条或多条计算机指令从而实现相应方法流程或相应功能。
作为示例，处理器510也可称为中央处理器CPU。处理器510可以包括但不限于：通用处理器、数字信号处理器DSP、专用集成电路ASIC、现场可编程门阵列FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等等。
作为示例，计算机可读存储介质520可以是高速RAM存储器，也可以是非不稳定的存储器，例如至少一个磁盘存储器；还可以是至少一个位于远离前述处理器510的计算机可读存储介质。具体而言，计算机可读存储介质520包括但不限于：易失性存储器和/或非易失性存储器。其中，非易失性存储器可以是只读存储器、可编程只读存储器、可擦除可编程只读存储器、电可擦除可编程只读存储器或闪存。易失性存储器可以是随机存取存储器，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器、动态随机存取存储器、同步动态随机存取存储器、双倍数据速率同步 动态随机存取存储器、增强型同步动态随机存取存储器、同步连接动态随机存取存储器和直接内存总线随机存取存储器。
在一种实现方式中，该电子设备500可以包括图4所示的装置400；该计算机可读存储介质520中存储有计算机指令；由处理器510加载并执行计算机可读存储介质520中存放的计算机指令，以实现图3所示方法实施例中的相应步骤；具体实现中，计算机可读存储介质520中的计算机指令由处理器510加载并执行相应步骤，为避免重复，此处不再赘述。
本申请实施例还提供了一种计算机可读存储介质，计算机可读存储介质是电子设备500中的记忆设备，用于存放程序和数据。例如，计算机可读存储介质520。可以理解的是，此处的计算机可读存储介质520既可以包括电子设备500中的内置存储介质，当然也可以包括电子设备500所支持的扩展存储介质。计算机可读存储介质提供存储空间，该存储空间存储了电子设备500的操作系统。并且，在该存储空间中还存放了适于被处理器510加载并执行的一条或多条的计算机指令，这些计算机指令可以是一个或多个的计算机程序521(包括程序代码)。
该电子设备500还可包括：收发器530，该收发器530可连接至该处理器510或计算机可读存储介质520。
其中，计算机可读存储介质520可以控制该收发器530与其他设备进行通信，具体地，可以向其他设备发送信息或数据，或接收其他设备发送的信息或数据。收发器530可以包括发射机和接收机。收发器530还可以进一步包括天线，天线的数量可以为一个或多个。
本申请还提供了一种计算机程序产品或计算机程序，该计算机程序产品或计算机程序包括计算机指令，该计算机指令存储在计算机可读存储介质中。例如，计算机程序521。此时，电子设备500可以是计算机，处理器510从计算机可读存储介质520读取该计算机指令，处理器510执行该计算机指令，使得该计算机执行上述各种可选方式中提供的芯片的地址重构方法。
换言之，当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行该计算机程序指令时，全部或部分地运行本申请实施例的流程或实现本申请实施例的功能。该计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质进行传输，例如，该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线等)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。
以上结合附图详细描述了本申请的优选实施方式，但本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。例如，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。又例如，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元以及流程步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
最后需要说明的是，以上仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种芯片的地址重构方法，其中，所述芯片内的交叉开关采用分层结构，所述方法包括：
    获取地址请求信息，其中，所述地址请求信息包括请求地址；
    对所述请求地址进行解析，得到初始路由信息和寻址地址；
    查找预设映射关系，得到与所述初始路由信息对应的目标路由信息，其中，所述预设映射关系由上位机基于所述分层结构得到并配置在所述芯片中；
    基于所述目标路由信息和所述寻址地址，确定目标地址，其中，所述目标地址用于访问所述芯片内的目标存储控制单元所管理的存储空间中的目标存储单元。
  2. 根据权利要求1所述的方法，其中，所述预设映射关系包括第一子映射关系和第二子映射关系；其中，
    所述第一子映射关系包括至少一个第一路由信息和至少一个第二路由信息，所述至少一个第一路由信息与所述至少一个第二路由信息一一对应，所述至少一个第一路由信息包括所述初始路由信息，所述第二路由信息为所述芯片内有效存储控制单元的路由信息；
    所述第二子映射关系包括至少一个第二路由信息和至少一个第三路由信息，所述至少一个第二路由信息与所述至少一个第三路由信息一一对应，所述至少一个第三路由信息包括所述目标路由信息，其中，所述第三路由信息由上位机基于所述分层结构对该第三路由信息对应的第二路由信息计算得到，为对应有效存储控制单元所管理存储空间的路由信息。
  3. 根据权利要求2所述的方法，其中，所述分层结构采用互联的两层结构，其中，
    第一层结构为：a个b×b结构的交叉开关；
    第二层结构为：b个a×(N/b)结构的交叉开关；
    其中，所述第一层结构的输出口数量为a×b＝M，所述第二层结构的输入口数量为b×a＝M，a、b、M、N、N/b均为正整数。
  4. 根据权利要求3所述的方法，其中，当访问所述芯片存储单元的mesh数量为R，a＝T，b＝S，N/b＝T，每个存储控制单元通过U个路由器管理相应存储空间中的U个存储单元时，
    每个mesh的编号为R1＝C％R，每个mesh的路由信息为R2＝C/R，其中，C为所述第二路由信息；
    每个S×S交叉开关的编号S1＝R2％S，每个S×S交叉开关端口的路由信息为S2＝S1/S；
    每个T×T交叉开关的编号为T1＝S2％T；
    路由器的编号为U＝S2/T；
    其中，所述第三路由信息由R1、R2、T1和U组成。
  5. 根据权利要求1-4中任一项所述的方法，其中，所述对所述请求地址进行解析，得到初始路由信息和寻址地址，包括：
    获取所述芯片的有效寻址范围；
    当所述请求地址在所述芯片的有效寻址范围内时，基于预设寻址方式对所述请求地址进行解析，得到所述初始路由信息和所述寻址地址。
  6. 根据权利要求5所述的方法，其中，所述方法还包括：
    当所述芯片内的存储控制单元存在损坏时，对所述芯片的有效地址进行重新编码，以更新所述芯片的有效寻址范围。
  7. 根据权利要求1-6中任一项所述的方法，其中，所述预设映射关系由所述上位机通过串行外设接口SPI配置在所述芯片中。
  8. 一种芯片的地址重构装置，其中，所述芯片内的交叉开关采用分层结构，所述装置包括：
    获取单元，用于获取地址请求信息，其中，所述地址请求信息包括请求地址；
    解析单元，用于对所述请求地址进行解析，得到初始路由信息和寻址地址；
    查表单元，用于查找预设映射关系，得到与所述初始路由信息对应的目标路由信息，其中，所述预设映射关系由上位机基于所述分层结构得到并配置在所述芯片中；
    确定单元，用于基于所述目标路由信息和所述寻址地址，确定目标地址，其中，所述目标地址用于访问所述芯片内目标存储控制单元所管理的存储空间中的目标存储单元。
  9. 一种电子设备，其中，包括：
    处理器，适于执行计算机程序；
    计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，所述计算机程序被所述处理器执行时，实现如权利要求1-7中任一项所述的方法。
  10. 一种计算机可读存储介质，其中，存储有存储计算机程序，所述计算机程序被处理器执行时，实现如权利要求1-7中任一项所述的方法。
PCT/CN2023/101784 2022-10-09 2023-06-21 芯片的地址重构方法、装置以及电子设备、存储介质 WO2024078006A1 (zh)

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