WO2016101490A1 - 更新处理方法及装置 - Google Patents

更新处理方法及装置 Download PDF

Info

Publication number
WO2016101490A1
WO2016101490A1 PCT/CN2015/078622 CN2015078622W WO2016101490A1 WO 2016101490 A1 WO2016101490 A1 WO 2016101490A1 CN 2015078622 W CN2015078622 W CN 2015078622W WO 2016101490 A1 WO2016101490 A1 WO 2016101490A1
Authority
WO
WIPO (PCT)
Prior art keywords
tcam
update processing
dram
write table
table operation
Prior art date
Application number
PCT/CN2015/078622
Other languages
English (en)
French (fr)
Inventor
姜海明
朱延灵
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2016101490A1 publication Critical patent/WO2016101490A1/zh

Links

Images

Definitions

  • the present invention relates to the field of communications, and in particular to an update processing method and apparatus.
  • network chips include ASIC and NP (network processor). With its high-speed processing and flexible programmability, network processors have become an effective solution for data processing in today's networks.
  • SRAM Static Random Access Ram
  • TCAM ternary content addressable memory
  • SDRAM Dynamic Random Access Ram
  • TCAM is a three-state content-addressable memory, which is mainly used to quickly find ACLs, routes, and other entries.
  • the main feature of TCAM is fast parallel search.
  • the application on the network processor is usually that the microcode composes a KEY (key value) from the message extraction information, and sends a search command to the TCAM through the NP TCAM controller, and processes the result according to the result. Message.
  • KEY key value
  • FIG. 1 is a schematic diagram of a TCAM-based ACL device in the related art, as shown in FIG.
  • the CPU accesses the external TCAM through the TCAM adaptation interface of the NP, and the NP and the TCAM are interconnected via the Interlaken bus.
  • a typical service application of the TCAM is an Access Control List (ACL), as shown in Figure 1, where the ACL rules are stored in the external TCAM connected to the NP; the ACL action table is stored in the external dynamic random storage ( Dynamic Random Access Ram (referred to as DRAM).
  • DRAM Dynamic Random Access Ram
  • the corresponding TCAM entries in the TCAM are in one-to-one correspondence with the action table entries in the DRAM. For NP microcode, hitting the TCAM entry returns the TCAM address to the NP, through which the NP translates to the address of the corresponding action table entry in the DRAM, finds the action table and performs the associated ACL action.
  • TCAM entry data width is usually very wide.
  • IPV6 ACL TCAM key value usually needs more than 640 BIT; in addition, DRAM has the advantage of large capacity, but its update rate is also slow.
  • Current industry ACL The general practice of updating is that TCAM and DRAM updates are serial operations, and in the case of large-capacity ACL entry updates, the update efficiency is very low.
  • the embodiment of the invention provides an update processing method and device, so as to at least solve the problem that the update efficiency of the large-capacity TCAM entry is low in the related art.
  • an update processing method including: determining a TCAM write table operation of a tri-state content addressed TCAM entry and a dynamic random access memory DRAM write table operation; for the TCAM entry
  • the TCAM write table operation and the DRAM write table operation perform parallel update processing.
  • performing parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry includes: not completing the TCAM write table operation update process on the TCAM entry In the case, the update processing of the DRAM write table operation is started.
  • performing the parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry includes: determining whether the TCAM of the TCAM entry and the DRAM are paralleled for the first time. Update processing; in the case where the determination result is YES, the TCAM of the TCAM entry and the DRAM are subjected to parallel update processing.
  • performing the parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry includes: determining whether the previous TCAM is completed before the determination result is negative Performing an update process; if the determination result is YES, performing an update process on the TCAM; determining whether the DRAM is updated before the previous time is completed; and if the determination result is YES, updating the DRAM .
  • the parallel update processing of the TCAM write table operation and the DRAM write table operation of the TCAM entry includes: the TCAM write table operation of the TCAM entry and the DRAM
  • the write table operation performs parallel update processing with the TCAM write table operation of the next TCAM entry and the DRAM write table operation.
  • the TCAM write table operation and the DRAM write table operation of the TCAM entry are performed with the TCAM write table operation and the DRAM write table operation of the next TCAM entry.
  • the parallel update process includes: after starting the update process on the DRAM, completing the previous In the case where the TCAM performs an update process, the TCAM is subjected to an update process; and/or, after the update process of the TCAM is started, in the case where the update process of the DRAM is completed the previous time, the DRAM is Perform update processing.
  • the TCAM entry includes one of the following: an access control list ACL, a routing table, and a quality of service (QoS).
  • an update processing apparatus including: a determining module configured to determine a TCAM write table operation of a tri-state content addressed TCAM entry and a dynamic random access memory DRAM write table operation;
  • the update processing module is configured to perform parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry.
  • the update processing module includes: a first update processing unit, configured to start writing to the DRAM in a case where the TCAM write table operation update process of the TCAM entry is not completed The operation is updated.
  • the update processing module includes: a first determining unit, configured to determine whether to perform parallel update processing on the TCAM and the DRAM of the TCAM entry for the first time; and a second update processing unit, configured to In the case where the determination result is YES, the TCAM of the TCAM entry and the DRAM are subjected to parallel update processing.
  • the update processing module includes: a second determining unit, configured to determine whether the update processing of the TCAM is completed before the determination result is negative; the third update processing unit sets In the case where the determination result is YES, the TCAM is subjected to an update process; the third determination unit is configured to determine whether the DRAM is updated before the previous time is completed; and the fourth update processing unit is set to In the case of YES, the DRAM is updated.
  • the update processing module includes: a fifth update processing unit, configured to perform the TCAM write table operation and the DRAM write table operation of the TCAM entry for the next time
  • the TCAM write table operation of the TCAM entry and the DRAM write table operation are performed in parallel update processing.
  • the third update processing unit includes: a first update processing sub-unit, configured to, after the update processing of the DRAM is started, in a case where the update processing of the TCAM is completed before the previous time And performing an update process on the TCAM; and/or, the second update processing sub-unit is configured to, after performing the update process on the TCAM, and in the case of performing the update process on the DRAM the previous time, The DRAM is updated.
  • a TCAM write table operation for determining a TCAM entry and a dynamic random access memory DRAM write table operation are used; and the TCAM write table operation and the DRAM write table operation of the TCAM entry are concurrently updated.
  • the problem that the update efficiency of the large-capacity TCAM entry is low in the related art is solved, thereby improving the effect of updating the capacity of the large-capacity TCAM entry.
  • FIG. 1 is a schematic diagram of a TCAM-based ACL device in the related art
  • FIG. 3 is a block diagram of an update processing apparatus according to an embodiment of the present invention.
  • FIG. 4 is a block diagram of an update processing apparatus according to a preferred embodiment 1 of the present invention.
  • FIG. 5 is a block diagram of an update processing apparatus in accordance with a preferred embodiment 2 of the present invention.
  • FIG. 6 is a block diagram of an update processing apparatus in accordance with a preferred embodiment 3 of the present invention.
  • FIG. 7 is a block diagram of an update processing apparatus in accordance with a preferred embodiment 4 of the present invention.
  • FIG. 8 is a block diagram of an update processing apparatus in accordance with a preferred embodiment 5 of the present invention.
  • FIG. 10 is a flow chart of an ACL write table according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of an update processing method according to an embodiment of the present invention. As shown in FIG. 2, the flow includes the following steps:
  • Step S202 determining a TCAM write table operation of the tri-state content addressing TCAM entry and a dynamic random access memory DRAM write table operation;
  • Step S204 performing parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry.
  • determining a TCAM write table operation of the TCAM entry and a dynamic random access memory DRAM write table operation determining a TCAM write table operation of the TCAM entry and a dynamic random access memory DRAM write table operation; performing a parallel update process on the TCAM write table operation and the DRAM write table operation of the TCAM entry, wherein the TCAM entry is
  • Related services written in the TCAM format may be an access control list ACL, a routing table, or QoS, which solves the problem of low efficiency of updating large-capacity TCAM entries in related technologies, thereby improving the efficiency of updating large-capacity TCAM entries. effect.
  • the method may include: not completing the TCAM write table for the TCAM entry.
  • the update processing of the DRAM write table operation is started, and since the TCAM write table operation update processing is not completed, the DRAM write table operation can be directly updated, thereby greatly shortening the time for updating the TCAM entry. , improve the update efficiency.
  • the parallel update processing of the TCAM write table operation of the TCAM entry and the DRAM write table operation may further perform different processing according to whether it is the first update process, first determining whether the TCAM of the TCAM entry and the DRAM are first. Performing parallel update processing; if the determination result is yes, performing parallel update processing on the TCAM of the TCAM entry and the DRAM: if the determination result is negative, determining whether the update processing of the TCAM is completed before; When the result of the determination is YES, the TCAM is subjected to an update process; it is judged whether or not the update processing of the DRAM is completed the previous time; and if the result of the determination is YES, the DRAM is updated.
  • the parallel update processing of the TCAM write table operation of the TCAM entry and the DRAM write table operation may further include: the TCAM write table operation of the TCAM entry for the second time and the DRAM write table operation and the next TCAM entry.
  • the TCAM write table operation and the DRAM write table operation are performed in parallel update processing. That is, it can be realized by: after starting the update processing on the DRAM, performing update processing on the TCAM in the case where the update processing of the TCAM is completed before; and/or, starting to update the TCAM. After the processing, in the case where the update processing of the DRAM is completed the previous time, the DRAM is subjected to the update processing, and the update processing is performed in parallel multiple times, thereby improving the efficiency of the TCAM entry.
  • the above TCAM entry may include one of the following: an access control list ACL, a routing table, and a quality of service QoS.
  • the embodiment of the present invention further provides an update processing device, which is used to implement the foregoing embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 3 is a block diagram of an update processing apparatus according to an embodiment of the present invention. As shown in FIG. 3, the method includes:
  • the determining module 32 is configured to determine a TCAM write table operation of the tri-state content addressing TCAM entry and a dynamic random access memory DRAM write table operation;
  • the update processing module 34 is configured to perform parallel update processing on the TCAM write table operation and the DRAM write table operation of the TCAM entry.
  • the update processing module 34 includes:
  • the first update processing unit 42 is arranged to start the update processing of the DRAM write table operation without completing the TCAM write table operation update processing for the TCAM entry.
  • the update processing module 34 includes:
  • the first determining unit 52 is configured to determine whether to perform parallel update processing on the TCAM of the TCAM entry and the DRAM for the first time;
  • the second update processing unit 54 is configured to perform parallel update processing on the TCAM of the TCAM entry and the DRAM if the determination result is YES.
  • FIG. 6 is a block diagram of an update processing apparatus according to a preferred embodiment 3 of the present invention. As shown in FIG. 6, the update processing module 34 includes:
  • the second determining unit 62 is configured to determine whether the update processing of the TCAM is completed the previous time if the determination result is negative;
  • the third update processing unit 64 is configured to perform an update process on the TCAM if the determination result is YES;
  • the third determining unit 66 is configured to determine whether the DRAM is updated after the previous time is completed;
  • the fourth update processing unit 68 is arranged to perform an update process on the DRAM when the determination result is YES.
  • FIG. 7 is a block diagram of an update processing apparatus according to a preferred embodiment 4 of the present invention. As shown in FIG. 7, the update processing module 34 includes:
  • the fifth update processing unit 72 is configured to perform parallel update of the TCAM write table operation of the TCAM entry and the DRAM write table operation of the TCAM entry of the next TCAM entry and the DRAM write table operation of the next TCAM entry. deal with.
  • FIG. 8 is a block diagram of an update processing apparatus according to a preferred embodiment 5 of the present invention.
  • the third update processing unit 72 includes:
  • the first update processing sub-unit 82 is configured to, after the update processing of the DRAM is started, perform update processing on the TCAM in the case where the update processing of the TCAM is completed before; and/or,
  • the second update processing sub-unit 84 is arranged to perform an update process on the DRAM after the update processing of the DRAM is completed before starting the update processing of the TCAM.
  • the TCAM-based ACL device includes:
  • control plane CPU complete NP and TCAM configuration, and ACL to deliver raw data to TCAM and DRAM hardware entries conversion
  • 102NP network processor
  • CPU interface CPU accesses TCAM and DRAM through the CPU interface;
  • TCAM interface NP and TCAM adapter interface, NP through Interlaken and TCAM interconnection, in addition to the MDIO interface for out-of-band register access;
  • DRAM interface NP and DRAM adapter interface.
  • FIG. 9 is a flowchart of an ACL write table in the related art. As shown in FIG. 9, the ACL update can be summarized into three steps:
  • Step 1 The application software layer converts the ACL rule according to the format defined by the TCAM; the ACL action is converted according to the format defined by the DRAM;
  • Step two update the TCAM rule until the end
  • Step three update the DRAM action table until the end.
  • the conversion of the first step is caused by the data format transmitted by the upper platform, which is inconsistent with the data format of the underlying chip. Therefore, the upper layer software needs to perform the corresponding adaptation conversion when each rule and corresponding action is sent; the second step is in the typical application. It takes a long time, such as IPV4ACL, in addition to the quintuple (source IP, destination IP, protocol number, source port, destination port), it may also include destination MAC, source MAC, Ethernet type (ETHERTYPE), interface number, etc.
  • the TCAM key width typically includes 80bit, 160bit, 320bit, 640bit, so only 640bit can be used.
  • Step 1 the 80 bytes of data are transmitted on Interlaken, and the control word defined by Interlaken is also added.
  • Control Word the data transmission time is relatively long, in addition to waiting for the TCAM to return the response result before the TCAM update is completed, only step 3 can be performed;
  • Step 3 update the DRAM action table, similar to step 2, currently with the network service
  • the ACL action table is usually wider, and the data reaches the NP and DRAM adapter interface through the PCI-E interface of the NP through the interface.
  • New DRAM, DRAM wait for the end of the write operation to complete this step.
  • the optional embodiment performs hardware operation and software operation in parallel. For example, when the TCAM is updated in step 2, the TCAM write table may be completed and the response result may be returned, and step 3 is directly performed. In step 3, only the DRAM write needs to be started. The table operation does not have to wait for completion, so that the next ACL entry is updated. Step 1 of the second loop assembles the TCAM key value of the next ACL rule and the contents of the DRAM table.
  • the second cycle step two when writing the TCAM again, it is necessary to judge whether the previous operation ends or not. If the execution ends, the TCAM write operation of the second cycle can be started; the second cycle step 3 is similar to this, write Before DRAM, judge whether the last execution ended.
  • the current ACL update process includes the following steps:
  • Step S902 the control plane assembles the hardware key value, and decomposes the ACL original data transmitted by the upper layer, and converts one piece into a TCAM write table key value and a DRAM entry content;
  • Step S904 writing a TCAM entry, waiting for completion, writing the assembled TCAM key value to the TCAM response entry in step S902, waiting for the data transmission on Interlaken to be completed and the TCAM returns a successful response result of the write table;
  • Step S906 writing a DRAM entry, waiting for completion, writing the contents of the DRAM action table assembled in step S902 to the corresponding address of the DRAM, and waiting for the execution to succeed;
  • FIG. 10 is a flowchart of an ACL write table according to an embodiment of the present invention. As shown in FIG. 10, the method includes the following steps:
  • Step S1002 the control plane assembles the hardware key value, decomposes the ACL original data transmitted by the upper layer, and converts one piece into a TCAM write table key value and a DRAM entry content;
  • step S1004 it is checked whether the previous TCAM write table is completed. If yes, go to step S1008, otherwise go to step S1006; if it is judged whether the previous TCAM update is completed, there may be different implementation methods.
  • the NP usually has a status register, which indicates whether the data transmission on the Interlaken is completed, whether the Interlaken data response is received, etc.; if the TCAM has a corresponding register, it can also be used as a basis for judging whether the previous TCAM update is completed.
  • the TCAM write table usually does not need to wait for the TCAM response and parse. If TCAM parsing is to be performed, the judgment of the previous TCAM return result needs to be added. If the execution fails, the failure list is added for failure rewriting. This operation does not belong to the core idea of this patent and will not be described in detail.
  • Step S1006 waiting, waiting for a certain period, and then proceeding to step S1004 to check until the previous write table is completed, the waiting period is usually microsecond or millisecond;
  • step S1008 the TCAM is started to be written, the TCAM related register is configured, and the key value assembled in step S1002 is started to be written into the TCAM. It should be noted that, for the first write table, the determination of step S1004 is not required, and the table is directly written; Just turn on the data transfer of TCAM data on the Interlaken bus of NP and TCAM, without waiting for completion;
  • Step S1010 determining whether the previous DRAM operation is completed
  • step S1004 it is determined whether the previous operation is completed, if the process proceeds to step S1014; otherwise, proceeds to step S1012;
  • Step S1012 waiting, waiting for a certain period, and then proceeding to step S1010, checking until the previous write table is completed, the waiting period is usually microsecond or millisecond;
  • step S1014 the DRAM is started to be written, the DRAM related registers are configured, and the assembled key value is started to be written into the DRAM in step S1002.
  • This step is only to enable the data transmission of the DRAM data on the NP and DRAM hardware bus, and does not need to wait for completion; the loop ends, and the process proceeds to step S1002, and the next ACL data is sent;
  • the batch ACL write time can be shortened to one percent of the serial mode.
  • This alternative embodiment provides a fast write table mode for the problem that the current batch write TCAM is slow.
  • this alternative embodiment solves the hardware operation and the software operation by the serial operation of the current commonly used serial operation, and waits for the write table to be changed into parallel operation.
  • the latter operation waits for the previous completion mode, which greatly improves the efficiency of TCAM-based ACL update, especially in the case of large-capacity ACL update, which is extremely useful.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • a TCAM write table operation for determining a TCAM entry and a dynamic random access memory DRAM write table operation are employed; the TCAM write table operation for the TCAM entry and the DRAM
  • the write table operation performs parallel update processing, which solves the problem of low efficiency of updating large-capacity TCAM entries in the related art, thereby improving the efficiency of updating large-capacity TCAM entries.

Abstract

一种更新处理方法及装置，其中，该方法包括：确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作（S202）；对该TCAM条目的该ACL的该TCAM写表操作及该DRAM写表操作进行并行更新处理（S204）。其解决了相关技术中对大容量TCAM条目更新效率低的问题，从而提高了大容量TCAM条目更新效率的效果。

Description

更新处理方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及一种更新处理方法及装置。
背景技术
现今网络发展速度惊人，网络流量的增长及新业务的出现，需要网络设备具有线速和灵活的处理能力。目前网络芯片包括ASIC和NP(网络处理器)两大类。网络处理器凭借其高速处理及灵活的可编程性，已成为当今网络中数据处理的有效解决方案。
网络处理器中有多种不同的存储器，如静态随机储存器(Static Random Access Ram，简称为SRAM)、三态内容寻址存储器(ternary content addressable memory，简称为TCAM)、同步动态随机储存器(Dynamic Random Access Ram，简称为SDRAM)等，这些存储器存放着各种业务表项，如端口表、MAC表、路由表等。
TCAM是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。TCAM的主要特点是快速并行查找，在网络处理器上的应用通常是，微码从报文抽取相关信息组成一个KEY(键值)，通过NP的TCAM控制器向TCAM发送查找命令，根据结果处理报文。
目前一种常用的网络处理器连接TCAM方式，图1是相关技术中基于TCAM的ACL装置的示意图，如图1所示。CPU通过NP的TCAM适配接口访问外部TCAM，NP和TCAM之间通过Interlaken总线互联。
TCAM的一种典型业务应用为访问控制列表(Access Control List，简称为ACL)，如图1所示，其中ACL规则存放于NP相连的外部TCAM中；ACL动作表存放在于外部动态随机储存器(Dynamic Random Access Ram，简称为DRAM)中。TCAM中规则相应的TCAM条目和DRAM中的动作表条目一一对应。对NP微码而言，命中TCAM条目会向NP返回TCAM地址，NP通过该地址转换成相应动作表条目在DRAM中的地址，找到动作表并执行相关ACL动作。
目前TCAM条目数据宽度通常非常宽，典型地，IPV6 ACL，TCAM键值通常需要640BIT以上；另外，DRAM优点是大容量，但其更新速率也比较慢。目前业界ACL 更新通用做法是TCAM和DRAM更新是串行操作，在大容量ACL条目更新情况下，更新效率非常低下。
针对相关技术中对大容量TCAM条目更新效率低的问题，目前尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种更新处理方法及装置，以至少解决相关技术中对大容量TCAM条目更新效率低的问题。
根据本发明实施例的一个方面，提供了一种更新处理方法，包括：确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
在本发明实施例中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：在没有完成对所述TCAM条目的所述TCAM写表操作更新处理的情况下，开始对所述DRAM写表操作进行更新处理。
在本发明实施例中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：判断是否首次对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理；在判断结果为是的情况下，对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理。
在本发明实施例中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：在判断结果为否的情况下，判断前一次是否完成对所述TCAM进行更新处理；在判断结果为是的情况下，对所述TCAM进行更新处理；判断前一次是否完成对所述DRAM进行更新处理；在判断结果为是的情况下，对所述DRAM进行更新处理。
在本发明实施例中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：对此次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
在本发明实施例中，对此次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：在开始对所述DRAM进行更新处理之后，在前一次完成对所述 TCAM进行更新处理的情况下，对所述TCAM进行更新处理；和/或，在开始对所述TCAM进行更新处理之后，在前一次完成对所述DRAM进行更新处理的情况下，对所述DRAM进行更新处理。
在本发明实施例中，所述TCAM条目包括以下之一：接入控制列表ACL，路由表，服务质量(Quality of Service，简称为QoS)。
根据本发明实施例的另一方面，提供了一种更新处理装置，包括：确定模块，设置为确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；更新处理模块，设置为对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
在本发明实施例中，所述更新处理模块包括：第一更新处理单元，设置为在没有完成对所述TCAM条目的所述TCAM写表操作更新处理的情况下，开始对所述DRAM写表操作进行更新处理。
在本发明实施例中，所述更新处理模块包括：第一判断单元，设置为判断是否首次对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理；第二更新处理单元，设置为在判断结果为是的情况下，对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理。
在本发明实施例中，所述更新处理模块包括：第二判断单元，设置为在判断结果为否的情况下，判断前一次是否完成对所述TCAM进行更新处理；第三更新处理单元，设置为在判断结果为是的情况下，对所述TCAM进行更新处理；第三判断单元，设置为判断前一次是否完成对所述DRAM进行更新处理；第四更新处理单元，设置为在判断结果为是的情况下，对所述DRAM进行更新处理。
在本发明实施例中，所述更新处理模块包括：第五更新处理单元，设置为对此次的所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次的所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
在本发明实施例中，所述第三更新处理单元包括：第一更新处理子单元，设置为在开始对所述DRAM进行更新处理之后，在前一次完成对所述TCAM进行更新处理的情况下，对所述TCAM进行更新处理；和/或，第二更新处理子单元，设置为在开始对所述TCAM进行更新处理之后，在前一次完成对所述DRAM进行更新处理的情况下，对所述DRAM进行更新处理。
通过本发明实施例，采用确定TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理，解决了相关技术中对大容量TCAM条目更新效率低的问题，从而的提高了大容量TCAM条目更新效率的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是相关技术中基于TCAM的ACL装置的示意图；
图2是根据本发明实施例的更新处理方法的流程图；
图3是根据本发明实施例的更新处理装置的框图；
图4是根据本发明优选实施例一的更新处理装置的框图；
图5是根据本发明优选实施例二的更新处理装置的框图；
图6是根据本发明优选实施例三的更新处理装置的框图；
图7是根据本发明优选实施例四的更新处理装置的框图；
图8是根据本发明优选实施例五的更新处理装置的框图；
图9是相关技术中的ACL写表的流程图；
图10是根据本发明实施例的ACL写表流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在本实施例中提供了一种更新处理方法，图2是根据本发明实施例的更新处理方法的流程图，如图2所示，该流程包括如下步骤：
步骤S202，确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；
步骤S204，对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理。
通过上述步骤，确定TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理，其中，TCAM条目为按照TCAM格式写入的相关业务，例如，可以是访问控制列表ACL、路由表或QoS，解决了相关技术中对大容量TCAM条目更新效率低的问题，从而的提高了大容量TCAM条目更新效率的效果。
对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理的方式有很多种，在一个可选的实施例中，可以包括：在没有完成对该TCAM条目的该TCAM写表操作更新处理的情况下，开始对该DRAM写表操作进行更新处理，由于不用等待TCAM写表操作更新处理完毕，就可以直接对DRAM写表操作进行更新处理，从而大大缩短了更新TCAM条目的时间，提高了更新效率。
对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理还可以根据是否是首次更新处理，从而做出不同的处理，首先判断是否首次对该TCAM条目的该TCAM及该DRAM进行并行更新处理；在判断结果为是的情况下，对该TCAM条目的该TCAM及该DRAM进行并行更新处理：在判断结果为否的情况下，判断前一次是否完成对该TCAM进行更新处理；在判断结果为是的情况下，对该TCAM进行更新处理；判断前一次是否完成对该DRAM进行更新处理；在判断结果为是的情况下，对该DRAM进行更新处理。
对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理还可以包括：对此次的该TCAM条目的该TCAM写表操作及该DRAM写表操作与下一次的该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理。即可以通过以下的方式实现：在开始对该DRAM进行更新处理之后，在前一次完成对该TCAM进行更新处理的情况下，对该TCAM进行更新处理；和/或，在开始对该TCAM进行更新处理之后，在前一次完成对该DRAM进行更新处理的情况下，对该DRAM进行更新处理，通过多次并行执行更新处理，提高了对TCAM条目的更行效率。
上述的TCAM条目可以包括以下之一：访问控制列表ACL，路由表，服务质量QoS。
本发明实施例还提供了一种更新处理装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图3是根据本发明实施例的更新处理装置的框图，如图3所示，包括：
确定模块32，设置为确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；
更新处理模块34，设置为对该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理。
图4是根据本发明优选实施例一的更新处理装置的框图，如图4所示，该更新处理模块34包括：
第一更新处理单元42，设置为在没有完成对该TCAM条目的该TCAM写表操作更新处理的情况下，开始对该DRAM写表操作进行更新处理。
图5是根据本发明优选实施例二的更新处理装置的框图，如图5所示，该更新处理模块34包括：
第一判断单元52，设置为判断是否首次对该TCAM条目的该TCAM及该DRAM进行并行更新处理；
第二更新处理单元54，设置为在判断结果为是的情况下，对该TCAM条目的该TCAM及该DRAM进行并行更新处理。
图6是根据本发明优选实施例三的更新处理装置的框图，如图6所示，该更新处理模块34包括：
第二判断单元62，设置为在判断结果为否的情况下，判断前一次是否完成对该TCAM进行更新处理；
第三更新处理单元64，设置为在判断结果为是的情况下，对该TCAM进行更新处理；
第三判断单元66，设置为判断前一次是否完成对该DRAM进行更新处理；
第四更新处理单元68，设置为在判断结果为是的情况下，对该DRAM进行更新处理。
图7是根据本发明优选实施例四的更新处理装置的框图，如图7所示，该更新处理模块34包括：
第五更新处理单元72，设置为对此次的该TCAM条目的该TCAM写表操作及该DRAM写表操作与下一次的该TCAM条目的该TCAM写表操作及该DRAM写表操作进行并行更新处理。
图8是根据本发明优选实施例五的更新处理装置的框图，如图8所示，该第三更新处理单元72包括：
第一更新处理子单元82，设置为在开始对该DRAM进行更新处理之后，在前一次完成对该TCAM进行更新处理的情况下，对该TCAM进行更新处理；和/或，
第二更新处理子单元84，设置为在开始对该TCAM进行更新处理之后，在前一次完成对该DRAM进行更新处理的情况下，对该DRAM进行更新处理。
下面以TCAM条目为访问控制列表ACL为例，结合可选实施例对本发明实施例进行进一步说明。
如图1所示，基于TCAM的ACL装置包括：
101CPU，控制面CPU，完成NP及TCAM配置，以及ACL下发原始数据到TCAM及DRAM硬件条目的转换；
102NP，网络处理器，包括：
CPU接口：CPU通过CPU接口访问TCAM及DRAM；
TCAM接口：NP与TCAM的适配接口，NP通过Interlaken与TCAM互联，另外通过MDIO接口进行带外的寄存器访问；
DRAM接口：NP与DRAM的适配接口。
图9是相关技术中的ACL写表的流程图，如图9所示，ACL更新可以归结为三个步骤：
步骤一，应用软件层将ACL规则按照TCAM定义的格式进行转换；ACL动作根据DRAM定义的格式进行转换；
步骤二，更新TCAM规则直至结束；
步骤三，更新DRAM动作表直至结束。
这三个步骤是ACL更新主要的三个时间耗费点。步骤一的转换是由于上层平台传递下来的数据格式，与芯片底层的数据格式不一致导致的，因此需要上层软件在每一个规则及相应动作下发时候做相应的适配转换；步骤二在典型应用中耗费时间也很长，比如IPV4ACL，除了五元组(源IP，目的IP，协议号，源端口，目的端口)外，还可能包括目的MAC、源MAC、以太类型(ETHERTYPE)、接口号等，而TCAM的键值宽度典型的包括80bit、160bit、320bit、640bit，因此只能用640bit，按照图1所示，这80字节的数据在Interlaken上传输，还需要加上Interlaken定义的控制字(Control Word)，数据传输时间比较长，另外需要等待TCAM返回响应结果后才能断定TCAM更新完成，才可以进行步骤三；步骤三，更新DRAM动作表，与步骤二类似，目前随着网络业务的复杂度增加，ACL动作表通常也比较宽，数据通过NP的PCI-E接口到达NP与DRAM的适配接口，通过该接口更新DRAM，等待写DRAM结束完成该步操作。
目前上层业务经常大批量写表，比如ACL，可能一次用户定义上万条ACL规则。业界通用做法是这三个步骤顺序串行执行，一次更新通常需要十几秒甚至几十秒。
本可选实施例将硬件操作、软件操作并行执行，比如步骤二TCAM更新时，可以不需要等待TCAM写表完成并返回响应结果，而直接进行步骤三，在步骤三，也只需要开启DRAM写表操作不必等待完成，从而进行下一个ACL条目的更新，第二个循环的步骤一，组装下一条ACL规则的TCAM键值及DRAM表内容。
在第二个循环步骤二，再一次写TCAM时，需要判断前一次操作是否执行结束，如果执行结束才可以开始第二个循环的TCAM写表操作；第二个循环步骤三与此类似，写DRAM前判断上一次执行是否结束。
通过上述软件、硬件并行操作，可以大大提高ACL更新效率。
如图9所示，目前ACL更新流程包括以下步骤：
步骤S902，控制面组装硬件键值，将上层传递的ACL原始数据进行分解，一条一条的转换成TCAM写表键值及DRAM条目内容；
步骤S904，写TCAM条目，等待完成，将步骤S902，组装好后的TCAM键值写入TCAM响应条目，等待Interlaken上数据传输完成并且TCAM返回写表成功的响应结果；
步骤S906，写DRAM条目，等待完成，将步骤S902组装好后的DRAM动作表内容写入DRAM相应地址，并等待执行成功；
一次循环结束，开始下次循环写ACL下一个条目，跳到步骤S902。
图10是根据本发明实施例的ACL写表流程图，如图10所示，包括以下步骤：
步骤S1002，控制面组装硬件键值，将上层传递的ACL原始数据进行分解，一条一条的转换成TCAM写表键值及DRAM条目内容；
步骤S1004，检查前一次TCAM写表是否完成，如果完成，进入步骤S1008，否则进入步骤S1006；如何判断前一次TCAM更新是否完成，可以有不同实现方法。比如，NP通常有状态寄存器，表征Interlaken上数据传输是否完成，是否收到Interlaken的数据响应等；如果TCAM有相应寄存器，也可以作为前一次TCAM更新是否完成的判断依据。为了节省TCAM更新效率，TCAM写表通常不需要等待TCAM响应并解析，如果要做TCAM解析，则需要加上前一次TCAM返回结果的判断解析，如果执行失败，则加入失败链表进行失败重写。该操作不属于本专利的核心思想，不做赘述。
步骤S1006，进行等待，等待一定周期，再进入步骤S1004检查，直到前一次写表完成为止，等待周期通常是微秒或者毫秒级；
步骤S1008，开始写TCAM，配置TCAM相关寄存器，将步骤S1002组装的键值开始写入TCAM，需要说明的是对于第一次写表，不需要执行步骤S1004，的判断，直接写表；本步骤只是开启TCAM数据在NP和TCAM的Interlaken总线上的数据传输，不需要等待完成；
步骤S1010，判断前一次DRAM操作是否完成；
与步骤S1004类似，判断前一次操作是否完成，如果完成进入步骤S1014；否则进入步骤S1012；
步骤S1012，等待，等待一定周期，再进入步骤S1010，检查直到前一次写表完成为止，等待周期通常是微秒或者毫秒级；
步骤S1014，开始写DRAM，配置DRAM相关寄存器，将步骤S1002，组装的键值开始写入DRAM。本步骤只是开启DRAM数据在NP和DRAM硬件总线上的数据传输，不需要等待完成；本次循环结束，进入步骤S1002，开始下一条ACL数据的下发；
在所有ACL数据下发完成之后，更新结束。
由于采用并行执行，每次判断硬件前一次操作是否执行完成时，只有非常小的概率是未完成需要等待的。实际测试，采用本专利方法，批量ACL写表时间可以缩短到串行方式的百分之一。
本可选实施例针对目前批量写TCAM生效慢的问题，提供了一种快速写表模式。将软件组键值、硬件写TCAM、硬件写DRAM，由通常的串行执行，改为并行执行。在硬件写表时不等待，而直接进行下一步操作，这样并行执行极大提高了写表效率。因此本可选实施例在大容量写表情况下可以节省很多时间，极大缩短了ACL业务生效时间。
本可选实施例相对目前基于TCAM的批量ACL写表慢的问题，通过分解ACL的执行步骤，将其中的硬件操作、软件操作由目前通常惯用的串行操作，等待写表完成改为并行操作，后一次操作等待前一次完成的方式，极大提高了基于TCAM的ACL更新效率，特别在大容量ACL更新情况下，显得极为有应用价值。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，通过上述实施例及优选实施方式，采用确定TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理，解决了相关技术中对大容量TCAM条目更新效率低的问题，从而的提高了大容量TCAM条目更新效率的效果。

Claims (13)

  1. 一种更新处理方法，包括：
    确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；
    对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
  2. 根据权利要求1所述的方法，其中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：
    在没有完成对所述TCAM条目的所述TCAM写表操作更新处理的情况下，开始对所述DRAM写表操作进行更新处理。
  3. 根据权利要求1或2所述的方法，其中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：
    判断是否首次对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理；
    在判断结果为是的情况下，对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理。
  4. 根据权利要求3所述的方法，其中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：
    在判断结果为否的情况下，判断前一次是否完成对所述TCAM进行更新处理；
    在判断结果为是的情况下，对所述TCAM进行更新处理；
    判断前一次是否完成对所述DRAM进行更新处理；
    在判断结果为是的情况下，对所述DRAM进行更新处理。
  5. 根据权利要求1所述的方法，其中，对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：
    对此次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
  6. 根据权利要求5所述的方法，其中，对此次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理包括：
    在开始对所述DRAM进行更新处理之后，在前一次完成对所述TCAM进行更新处理的情况下，对所述TCAM进行更新处理；和/或，
    在开始对所述TCAM进行更新处理之后，在前一次完成对所述DRAM进行更新处理的情况下，对所述DRAM进行更新处理。
  7. 根据权利要求1至2、4至6中任一项所述的方法，其中，所述TCAM条目包括以下之一：访问控制列表ACL，路由表，服务质量QoS。
  8. 一种更新处理装置，包括：
    确定模块，设置为确定三态内容寻址TCAM条目的TCAM写表操作及动态随机存取储存器DRAM写表操作；
    更新处理模块，设置为对所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
  9. 根据权利要求8所述的装置，其中，所述更新处理模块包括：
    第一更新处理单元，设置为在没有完成对所述TCAM条目的所述TCAM写表操作更新处理的情况下，开始对所述DRAM写表操作进行更新处理。
  10. 根据权利要求8或9所述的装置，其中，所述更新处理模块包括：
    第一判断单元，设置为判断是否首次对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理；
    第二更新处理单元，设置为在判断结果为是的情况下，对所述TCAM条目的所述TCAM及所述DRAM进行并行更新处理。
  11. 根据权利要求10所述的装置，其中，所述更新处理模块包括：
    第二判断单元，设置为在判断结果为否的情况下，判断前一次是否完成对所述TCAM进行更新处理；
    第三更新处理单元，设置为在判断结果为是的情况下，对所述TCAM进行更新处理；
    第三判断单元，设置为判断前一次是否完成对所述DRAM进行更新处理；
    第四更新处理单元，设置为在判断结果为是的情况下，对所述DRAM进行更新处理。
  12. 根据权利要求8所述的装置，其中，所述更新处理模块包括：
    第五更新处理单元，设置为对此次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作与下一次所述TCAM条目的所述TCAM写表操作及所述DRAM写表操作进行并行更新处理。
  13. 根据权利要求12所述的装置，其中，所述第三更新处理单元包括：
    第一更新处理子单元，设置为在开始对所述DRAM进行更新处理之后，在前一次完成对所述TCAM进行更新处理的情况下，对所述TCAM进行更新处理；和/或，
    第二更新处理子单元，设置为在开始对所述TCAM进行更新处理之后，在前一次完成对所述DRAM进行更新处理的情况下，对所述DRAM进行更新处理。
PCT/CN2015/078622 2014-12-26 2015-05-08 更新处理方法及装置 WO2016101490A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410836357.3A CN105791163B (zh) 2014-12-26 2014-12-26 更新处理方法及装置
CN201410836357.3 2014-12-26

Publications (1)

Publication Number Publication Date
WO2016101490A1 true WO2016101490A1 (zh) 2016-06-30

Family

ID=56149082

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/078622 WO2016101490A1 (zh) 2014-12-26 2015-05-08 更新处理方法及装置

Country Status (2)

Country Link
CN (1) CN105791163B (zh)
WO (1) WO2016101490A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112667526A (zh) * 2021-03-22 2021-04-16 芯启源（南京）半导体科技有限公司 一种访问控制列表电路实现方法及其电路
CN115499345A (zh) * 2022-09-22 2022-12-20 北京沃东天骏信息技术有限公司 数据测试方法、装置及存储介质、计算机产品

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111064714A (zh) * 2019-11-29 2020-04-24 苏州浪潮智能科技有限公司 一种基于fpga的智能网卡acl更新装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1798088A (zh) * 2004-12-30 2006-07-05 中兴通讯股份有限公司 基于fpga的路由查找和刷新的调度方法及其装置
CN101986271A (zh) * 2010-10-29 2011-03-16 中兴通讯股份有限公司 调度tcam查询和刷新消息的方法和装置
US7986696B1 (en) * 2009-02-12 2011-07-26 Compass Electro-Optical Systems Method and apparatus for longest prefix matching
CN102307149A (zh) * 2011-09-23 2012-01-04 中国科学院计算技术研究所 Ip查找方法和装置以及路由更新方法和装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1798088A (zh) * 2004-12-30 2006-07-05 中兴通讯股份有限公司 基于fpga的路由查找和刷新的调度方法及其装置
US7986696B1 (en) * 2009-02-12 2011-07-26 Compass Electro-Optical Systems Method and apparatus for longest prefix matching
CN101986271A (zh) * 2010-10-29 2011-03-16 中兴通讯股份有限公司 调度tcam查询和刷新消息的方法和装置
CN102307149A (zh) * 2011-09-23 2012-01-04 中国科学院计算技术研究所 Ip查找方法和装置以及路由更新方法和装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112667526A (zh) * 2021-03-22 2021-04-16 芯启源（南京）半导体科技有限公司 一种访问控制列表电路实现方法及其电路
CN115499345A (zh) * 2022-09-22 2022-12-20 北京沃东天骏信息技术有限公司 数据测试方法、装置及存储介质、计算机产品

Also Published As

Publication number Publication date
CN105791163A (zh) 2016-07-20
CN105791163B (zh) 2019-09-24

Similar Documents

Publication Publication Date Title
EP3239984B1 (en) Methods and systems for analyzing record and usage in post package repair
US10333845B2 (en) Forwarding data packets
CN104468401B (zh) 一种报文处理方法和装置
US20150304212A1 (en) Method and apparatus for matching flow table, and switch
WO2016101488A1 (zh) 一种三态内容可寻址存储器tcam查表方法及装置
US20220029918A1 (en) SRv6 with Micro Segment Identifiers
US10574570B2 (en) Communication processing method and apparatus
US10404611B2 (en) Discovering path maximum transmission unit
CN106878184A (zh) 一种数据报文传输方法和装置
WO2016101490A1 (zh) 更新处理方法及装置
CN111026324B (zh) 转发表项的更新方法及装置
WO2015131720A1 (zh) 报文处理方法及装置
JPH11191781A (ja) 経路検索回路及び通信制御装置
CN104601645B (zh) 一种数据包处理方法及装置
US10587519B2 (en) Clos network load balancing method and apparatus
US11914540B2 (en) On-chip integrated circuit, data processing device, and data processing method
WO2016197607A1 (zh) 一种实现路由查找的方法及装置
CN115883681A (zh) 报文解析方法、装置、电子设备及存储介质
JP2020088517A (ja) 通信装置、通信装置の制御方法およびプログラム
US9747144B2 (en) Function processing apparatus and function processing method dynamically process network function using commands
CN105786733A (zh) 一种写入tcam条目的方法及装置
US20220239767A1 (en) Efficient packet re-transmission for express data paths
US11362969B2 (en) Efficient packet re-transmission for express data paths
US20170155543A1 (en) Control apparatus, communication system, and control method
US20230254248A1 (en) L2 switch, communication control method, and communication control program

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15871566

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15871566

Country of ref document: EP

Kind code of ref document: A1