WO2024073907A1 - 一种ecs电路、方法和存储器 - Google Patents

一种ecs电路、方法和存储器 Download PDF

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Publication number
WO2024073907A1
WO2024073907A1 PCT/CN2022/127048 CN2022127048W WO2024073907A1 WO 2024073907 A1 WO2024073907 A1 WO 2024073907A1 CN 2022127048 W CN2022127048 W CN 2022127048W WO 2024073907 A1 WO2024073907 A1 WO 2024073907A1
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Prior art keywords
signal
ecs
module
counting
error
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PCT/CN2022/127048
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English (en)
French (fr)
Inventor
黄泽群
孙凯
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长鑫存储技术有限公司
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Publication of WO2024073907A1 publication Critical patent/WO2024073907A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • the present disclosure relates to the field of semiconductor technology, and more particularly to an ECS circuit, method and memory.
  • DDR double data rate
  • DRAM dynamic random access memory
  • ECS error check and scrub
  • Embodiments of the present disclosure provide an ECS circuit, method, and memory.
  • an embodiment of the present disclosure provides an ECS circuit, including an ECS control module, a command generation module, an address counting module, and an error tracking and recording module, wherein:
  • the ECS control module is configured to receive a mode control signal and generate an ECS command signal according to the mode control signal;
  • the command generation module is configured to generate an internal command signal according to the ECS command signal, wherein the internal command signal is used to execute a corresponding ECS operation;
  • the address counting module is configured to perform address counting according to the internal command signal and generate a counting end signal when the target address is finished counting;
  • the error tracking and recording module is configured to receive an error signal and generate an error tracking signal according to the count end signal and the error signal, wherein the error tracking signal is used to record error information of the ECS operation.
  • the mode control signal comprises a multi-purpose command MPC signal or a refresh command signal, wherein:
  • the ECS control module is further configured to generate the ECS command signal according to the MPC signal when the ECS is operated in a manual ECS operation mode, or;
  • the ECS control module is further configured to generate the ECS command signal according to the refresh command signal when the ECS operates in an automatic ECS operation mode.
  • the ECS control module includes a first timing module and a command control module, wherein:
  • the first timing module is configured to generate an ECS identification signal
  • the command control module is configured to receive the ECS identification signal, and when the ECS identification signal is in a valid state, obtain a refresh command signal, and generate the ECS command signal according to the refresh command signal.
  • the first timing module is configured to receive a first clock signal, count according to the first clock signal, generate the ECS identification signal, and send the ECS identification signal to the command control module; wherein, when the count value meets a preset condition, the ECS identification signal is in a valid state.
  • the first timing module is further configured to stop the counting when the ECS identification signal is in a valid state
  • the command control module is further configured to generate a reset signal after generating the ECS command signal according to the refresh command signal, and send the reset signal to the first timing module so that the first timing module restarts counting and controls the ECS identification signal to be in an invalid state.
  • the command control module is further configured to output the received refresh command signal as an internal refresh signal to perform a refresh operation when the ECS identification signal is in an invalid state.
  • the command generation module includes an internal command generation module and a second timing module, wherein:
  • the internal command generation module is configured to generate an activation signal, a read command signal, a write command signal and a precharge signal in sequence according to preset timing conditions after receiving the ECS command signal;
  • the second timing module is configured to control the time interval between the activation signal and the read command signal to meet a first timing condition, control the time interval between the read command signal and the write command signal to meet a second timing condition, and control the time interval between the write command signal and the precharge signal to meet a third timing condition;
  • the preset timing condition is composed of the first timing condition, the second timing condition and the third timing condition.
  • the ECS circuit further includes a storage control module and a storage array, the storage array includes at least one storage group, the storage group includes at least one storage block, the storage block includes at least one row and at least one column, wherein:
  • the storage control module is configured to receive the internal command signal and perform an ECS operation on the storage array according to the internal command signal, and;
  • the storage control module is further configured to generate the error signal if error information is detected when executing the ECS operation, and send the error signal to the error tracking and recording module.
  • the address counting module includes a column counting module, a row counting module and an array counting module, wherein:
  • the column counting module is configured to receive the pre-charge signal, perform column counting on the target row according to the pre-charge signal; and generate a column output signal and a column end signal when the column counting of the target row is completed;
  • the row counting module is configured to receive the precharge signal and the column output signal, and count the rows of the target storage block according to the precharge signal and the column output signal; when the row counting of the target storage block is completed, generate a row output signal and a row end signal;
  • the array counting module is configured to receive the precharge signal and the row output signal, count the storage blocks of the target storage group according to the precharge signal and the row output signal; generate a storage block output signal and a storage block end signal when the storage block count of the target storage group is completed; and count the storage groups of the storage array according to the precharge signal and the storage block output signal; generate a storage group end signal and an ECS end signal when the storage group count of the storage array is completed.
  • the array counting module includes a storage block counting module and a storage group counting module, wherein:
  • the storage block counting module is configured to receive the precharge signal and the row output signal, count the storage blocks of the target storage group according to the precharge signal and the row output signal; and generate the storage block output signal and the storage block end signal when the storage block counting of the target storage group is completed;
  • the storage group counting module is configured to receive the precharge signal and the storage block output signal, and count the storage groups of the storage array according to the precharge signal and the storage block output signal; when the storage group counting of the storage array is completed, generate the storage group end signal and the ECS end signal.
  • the column counting module is further configured to continue to perform column counting of the next target row after generating the column output signal and the column end signal until the column counting of each row in the storage array is completed;
  • the row counting module is further configured to continue to perform row counting of the next target storage block after generating the row output signal and the row end signal until the row counting of each storage block in the storage array is completed;
  • the array counting module is further configured to continue counting the storage blocks of the next target storage group after generating the storage block output signal and the storage block end signal until the storage block counting of each storage group in the storage array is completed.
  • the error tracking and recording module includes a first error tracking and recording module, wherein:
  • the first error tracking and recording module is configured to receive a counting mode signal, and when the counting mode signal is a first value, determine that the counting mode of the first error tracking and recording module is a codeword counting mode; or, when the counting mode signal is a second value, determine that the counting mode of the first error tracking and recording module is a row counting mode.
  • the first error tracking and recording module is configured to receive the error signal when the counting mode is the codeword counting mode, count codewords according to the error signal, and determine a first count value when the ECS end signal is received; and compare the first count value with a first threshold, and save the first count value when the first count value is greater than or equal to the first threshold; wherein the first count value is used to characterize the number of codewords with error information in the storage array.
  • the first error tracking and recording module is configured to, when the counting mode is the row counting mode, receive the error signal and the column end signal, perform error row counting according to the error signal and the column end signal, and determine a second count value when the ECS end signal is received; and compare the second count value with a second threshold value, and save the second count value when the second count value is greater than the second threshold value; wherein the second count value is used to characterize the number of rows in the storage array that have at least one error information.
  • the error tracking and recording module further includes a second error tracking and recording module, wherein:
  • the second error tracking and recording module is configured to receive the error signal, and count the error information of the target row according to the error signal and the column end signal, and after determining the third count value of the target row, compare the third count value with the target count value stored in the first register module, if the third count value is greater than the target count value, clear the target count value stored in the first register module, and save the third count value as the target count value in the first register module; and continue to count errors for the next target row according to the error signal and the column end signal until the ECS end signal is received, and then determine the target count value stored in the first register module; wherein the third count value is used to characterize the number of codewords with error information in the target row.
  • the second error tracking and recording module is further configured to save the address information corresponding to the target count value in the second register module when the target count value is saved in the first register module; wherein the address information includes row address information, storage block address information and storage group address information corresponding to the target count value.
  • the second error tracking and recording module is further configured to compare the target count value currently stored in the first register module with a third threshold after receiving the ECS end signal; if the target count value is greater than or equal to the third threshold, the target count value stored in the first register module and the address information stored in the second register module are retained; if the target count value is less than the third threshold, the target count value stored in the first register module and the address information stored in the second register module are cleared.
  • an embodiment of the present disclosure provides an ECS method, which is applied to the ECS circuit as described in the first aspect, and the method includes:
  • the command generation module receives the ECS command signal, and generates an internal command signal according to the ECS command signal, wherein the internal command signal is used to execute a corresponding ECS operation;
  • the internal command signal is received by the address counting module, address counting is performed according to the internal command signal, and a counting end signal is generated when the target address is counted;
  • the error tracking recording module receives the count end signal and the error signal, and generates an error tracking signal according to the count end signal and the error signal, wherein the error tracking signal is used to record error information of the ECS operation.
  • an embodiment of the present disclosure provides a memory, which includes the ECS circuit as described in the first aspect.
  • the disclosed embodiment provides an ECS circuit, method and memory
  • the ECS circuit includes an ECS control module, a command generation module, an address counting module and an error tracking recording module
  • the ECS control module is configured to receive a mode control signal and generate an ECS command signal according to the mode control signal
  • the command generation module is configured to generate an internal command signal according to the ECS command signal, and the internal command signal is used to perform a corresponding ECS operation
  • the address counting module is configured to perform address counting according to the internal command signal and generate a counting end signal when the target address completes counting
  • the error tracking recording module is configured to receive an error signal and generate an error tracking signal according to the counting end signal and the error signal, and the error tracking signal is used to record the error information of the ECS operation.
  • the disclosed embodiment generates an ECS command signal based on the mode control signal to perform the ECS operation, so that the memory can be completely checked and cleared for errors, and after the ECS operation is completed, an error tracking signal can be generated according to the error signal and the counting end signal to record the error information of the ECS operation, so that the location of the error information in the memory can be quickly located and repaired, and the performance of the memory is finally improved.
  • FIG1 is a schematic diagram of the composition structure of an ECS circuit provided in an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of selecting an ECS operation mode provided by an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the composition structure of an ECS control module provided in an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a structure of a command generation module provided in an embodiment of the present disclosure.
  • FIG5 is a partial structural diagram of an ECS circuit provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a composition structure of a storage array provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structure of an address counting module provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the composition structure of another address counting module provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of a specific structure of an ECS circuit provided in an embodiment of the present disclosure.
  • FIG10 is a schematic flow chart of an ECS method provided in an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that “first ⁇ second ⁇ third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
  • DRAM Dynamic Random Access Memory
  • DDR5 5th generation DDR standard (DDR5 Specification, DDR5 SPEC);
  • Multi-Purpose Command (MPC)
  • ECS Error Check and Scrub
  • Self-refresh (Self_Refresh, Self_REF or SRE);
  • the ECS mode allows the DRAM to read and modify the detected error codewords, write the corrected data back to the storage array, and record the error count. It requires a complete error check and clearing of the DRAM at least once every 24 hours.
  • the ECS operation mode includes automatic and manual operation modes, which can be selected through the mode register signal MR14OP[7].
  • the ECS command signal can be obtained with the help of the refresh command signal and the self-refresh command signal.
  • the MPC signal is required to perform manual ECS operation.
  • MR15 can also decide whether to perform manual ECS operation during self-refresh.
  • an ECS circuit including an ECS control module, a command generation module, an address counting module and an error tracking recording module, wherein: the ECS control module is configured to receive a mode control signal and generate an ECS command signal according to the mode control signal; the command generation module is configured to generate an internal command signal according to the ECS command signal, and the internal command signal is used to perform a corresponding ECS operation; the address counting module is configured to perform address counting according to the internal command signal and generate a counting end signal when the target address completes counting; the error tracking recording module is configured to receive an error signal and generate an error tracking signal according to the counting end signal and the error signal, and the error tracking signal is used to record the error information of the ECS operation.
  • the embodiment of the present disclosure generates an ECS command signal based on the mode control signal to perform the ECS operation, so that the memory can be completely checked and cleared, and after the ECS operation is completed, an error tracking signal can be generated according to the error signal and the counting end signal to record the error information of the ECS operation, so that the location of the error information in the memory can be quickly located and repaired, and finally the performance of the memory is improved.
  • the ECS circuit 10 may include an ECS control module 11, a command generation module 12, an address counting module 13, and an error tracking and recording module 14, wherein:
  • the ECS control module 11 is configured to receive the mode control signal and generate an ECS command signal according to the mode control signal;
  • a command generation module 12 configured to generate an internal command signal according to the ECS command signal, the internal command signal being used to execute a corresponding ECS operation;
  • the address counting module 13 is configured to count addresses according to the internal command signal and generate a counting end signal when the target address is counted;
  • the error tracking and recording module 14 is configured to receive the error signal and generate an error tracking signal according to the count end signal and the error signal, wherein the error tracking signal is used to record error information of the ECS operation.
  • the embodiments of the present disclosure relate to the overall framework design of the ECS circuit in the integrated circuit design, and in particular to the DRAM DDR5 chip, which needs to perform a complete error check and clearing of the DRAM at least once every 24 hours.
  • the overall framework of the ECS circuit is used to generate ECS command signals and some internal command signals, as well as error tracking signals, to detect error information and perform internal read and write error detection and repair. It can be applied to the relevant circuits that perform the ECS function in the DRAM DDR5 chip, but is not limited to this scope. Other memory chips, as well as other internal command generation, timing control and counting circuits, etc. can adopt this design.
  • the ECS circuit provided in the embodiment of the present disclosure can realize error checking and clearing of the storage array.
  • the function to be realized by the embodiment of the present disclosure is: in the manual ECS operation mode and the automatic ECS operation mode, the ECS command signal is generated by using a multi-purpose command signal (which can be represented by MPC) or a refresh command signal, and the internal command signal necessary for the internal execution of the ECS operation is generated to perform a complete error check and clearing of the DRAM, and other modules are used to track and record the detected error information.
  • the refresh command signal may include a refresh signal (which can be represented by REFab) and a self-refresh signal (which can be represented by Self-REF).
  • REFab refresh signal
  • Self-REF self-refresh signal
  • the generation of the ECS command signal can be based on the MPC signal or the refresh command signal, or it can also be based on other suitable signals, without any limitation here.
  • the ECS control module 11 is a module for generating an ECS command signal. Each time an ECS command signal is generated, the DRAM will perform an ECS operation accordingly. Here, an ECS operation is performed on a storage bit in the storage array. The ECS operation is used to determine whether there is a codeword error in the detected storage bit, and to perform error correction when a codeword error is detected.
  • the ECS control module is further configured to receive an ECS mode selection signal, and when the ECS mode selection signal is a first value, determine that the ECS operation mode is a manual ECS operation mode, or, when the ECS mode selection signal is a second value, determine that the ECS operation is an automatic ECS operation mode.
  • the ECS control module 11 is further configured to generate an ECS command signal according to the MPC signal when the ECS is operated in a manual ECS operation mode, or;
  • the ECS control module 11 is further configured to receive the first mode register signal and generate the ECS command signal according to the first mode register signal and the refresh command signal when the ECS is operated in the manual ECS operation mode, or;
  • the ECS control module 11 is further configured to generate an ECS command signal according to the refresh command signal when the ECS is operated in the automatic ECS operation mode.
  • the ECS operation mode includes a manual ECS operation mode and an automatic ECS operation mode, which can be selected according to an ECS mode selection signal, wherein the ECS mode selection signal can be a mode register signal MR14 OP[7].
  • the ECS mode selection signal can be a mode register signal MR14 OP[7].
  • the ECS control module when the ECS control module receives a specific MPC signal, it generates an ECS command signal according to the MPC signal to perform the ECS operation; here, the specific MPC signal may refer to the value of the MPC signal being: 00001100.
  • the refresh command signal refers to the self-refresh signal (Self-REF)
  • the first mode register signal may refer to the mode register signal MR15 OP[3]. It can be understood that when the Self-REF signal is received, the DRAM needs to perform a self-refresh operation.
  • MR15 OP[3] may determine whether an ECS operation needs to be performed before performing the self-refresh operation.
  • MR15OP[3] When MR15OP[3] is equal to 1, an ECS operation needs to be performed when entering the self-refresh mode, that is, the ECS control module generates an ECS command signal based on the first mode register signal and the Self-REF signal with a specific bit value of 1 to perform the ECS operation; and when MR15OP[3] is equal to 0, the ECS operation will not be performed during the self-refresh mode, that is, the ECS control module will not generate an ECS command signal, and the DRAM will perform the self-refresh mode.
  • the refresh command signal includes a self-refresh signal (Self-REF) and a refresh signal (REFab).
  • Self-REF self-refresh signal
  • REFab refresh signal
  • an ECS command signal can be generated according to the REFab signal to perform an ECS operation; or, when entering the self-refresh, an ECS command signal can also be generated according to the Self-REF signal to perform an ECS operation, wherein the average interval time for performing error checking and clearing can be represented by tECSint.
  • an ECS command signal can be generated based on different command signals to perform ECS operation, wherein, in the automatic ECS operation mode, the automatic ECS operation can be performed based on the refresh signal (REFab), or based on the self-refresh signal (Self_REF), and in the manual ECS operation mode, the ECS operation can be performed based on a specific MPC signal, or combined with the first mode register signal to determine whether to perform the ECS operation during self-refresh.
  • the automatic ECS operation can be performed based on the refresh signal (REFab), or based on the self-refresh signal (Self_REF)
  • the ECS operation in the manual ECS operation mode, the ECS operation can be performed based on a specific MPC signal, or combined with the first mode register signal to determine whether to perform the ECS operation during self-refresh.
  • the ECS control module can generate an ECS command signal based on the MPC signal and/or the refresh command signal to perform the ECS operation, simplifying the process required to generate the ECS operation; at the same time, different ECS operation modes can be selected in combination with the mode register signal, and it can be determined whether the ECS operation needs to be performed, which increases the flexibility of performing the ECS operation.
  • FIG3 shows a schematic diagram of the composition structure of an ECS control module 11 provided in an embodiment of the present disclosure.
  • the ECS control module 11 includes a first timing module 111 and a command control module 112, wherein:
  • a first timing module 111 is configured to generate an ECS identification signal
  • the command control module 112 is configured to receive the ECS identification signal, and when the ECS identification signal is in a valid state, obtain the refresh command signal, and generate the ECS command signal according to the refresh command signal.
  • the ECS control module 11 mainly includes a first timing module 111 and a command control module 112.
  • the command control module 112 selects which ECS operation mode to execute through the mode register signal MR14 OP[7].
  • the first timing module is required to plan the ECS interval time to ensure that the error check and clearing of all storage arrays are completed within 24 hours.
  • the first timing module 111 can generate an ECS identification signal (represented by ECS_Flag in FIG. 3 ) and send it to the command control module 112, and the ECS_Flag signal is in a valid state at every predetermined preset time interval.
  • the command control module 112 receives the ECS_Flag signal, and when the ECS_Flag signal is in a valid state, obtains a refresh command signal to generate an ECS command signal (represented by ECS_CMD in FIG. 3 ) according to the obtained refresh command signal.
  • the refresh command signal here may include at least one of the following: a refresh signal (REFab) and a self-refresh signal (Self-REF).
  • the first timing module is configured to receive a first clock signal, count according to the first clock signal, generate an ECS identification signal, and send the ECS identification signal to the command control module; wherein, when the count value meets a preset condition, the ECS identification signal is in a valid state.
  • the first timing module when it performs timing planning, it may count the first clock signal. When the count value meets the preset conditions, the ECS_Flag is in a valid state. At this time, the command control module 112 will obtain the refresh command signal, thereby generating an ECS command signal for instructing the execution of the ECS operation.
  • the refresh command signal obtained at this time is a refresh command signal that appears after the count value meets the preset conditions; therefore, compared with the moment when the count value meets the preset conditions, the refresh command signal obtained at this time specifically refers to the refresh command signal that appears at the next moment, which can also be referred to as the next refresh command signal. In this way, the interval time of the ECS operation is planned according to whether the count value meets the preset conditions, which can ensure a complete error check and clearing within 24 hours.
  • the first timing module is further configured to stop counting when the ECS identification signal is in a valid state
  • the command control module is further configured to generate a reset signal after generating an ECS command signal according to the refresh command signal, and send the reset signal to the first timing module so that the first timing module restarts counting and controls the ECS identification signal to be in an invalid state.
  • the ECS_Flag signal can be in a valid state or in an invalid state.
  • the first timing module 111 generates an ECS_Flag signal in a valid state after a certain period of time, which is used to generate an ECS command signal; after generating the ECS command signal, the command control module 112 generates a reset signal (indicated by Reset in FIG. 3 ) and sends it to the first timing module 111, so that the ECS_Flag signal is in an invalid state, and the first timing module 111 restarts counting.
  • the command control module is further configured to output the received refresh command signal as an internal refresh signal to perform a refresh operation when the ECS identification signal is in an invalid state.
  • the level value of the ECS identification signal may include a first value and a second value, wherein the first value may be a logic 1 indicating a high level, and the second value may be a logic 0 indicating a low level; or the first value may be a logic 0 indicating a low level, and the second value may be a logic 1 indicating a high level, and there is no limitation on this.
  • the level value of the ECS identification signal is logic 1
  • the ECS identification signal if the ECS identification signal is in a valid state, then the refresh command signal received at the next moment can be stolen, and the ECS command signal is generated according to the refresh command signal, and the corresponding stolen refresh command signal will disappear to perform the ECS operation; if the ECS identification signal is in an invalid state, then the refresh command signal will not be stolen, and it will be directly output as an internal refresh signal to perform the refresh operation.
  • the internal refresh signal is represented by REF_NEW.
  • the first timing module will generate a valid ECS flag signal ECS_Flag after every fixed time period and stop the timing count.
  • the ECS_Flag signal will be transmitted to the command control module, and then the command control module will steal the next REFab signal or Self_REF signal to generate the ECS command signal.
  • the corresponding stolen refresh command will disappear, and then a reset signal will be generated to the first timing module to reset the ECS_Flag signal to an invalid value, and at the same time, the first timing module will restart counting.
  • the refresh command will not be stolen, but the REF_NEW signal will be directly obtained, and the refresh operation will not be affected.
  • the command control module 112 "steals" the refresh command signal, that is, when the ECS command signal is generated, the corresponding refresh command signal will disappear, and the refresh operation will not be performed during the execution of the ECS operation. In this way, the power consumption of the memory during the execution of the ECS can be reduced, and the memory failure caused by the simultaneous execution of the refresh operation during the execution of the ECS operation can be prevented.
  • the ECS control module 11 After the ECS control module 11 generates the ECS command signal, it sends the ECS command signal to the command generation module 12 , and the command generation module 12 generates an internal command signal according to the ECS command signal, wherein the internal command signal is the command signal required to perform the ECS operation.
  • the command generation module 12 includes an internal command generation module 122 and a second timing module 121, wherein:
  • the internal command generation module 122 is configured to generate an activation signal, a read command signal, a write command signal and a precharge signal in sequence according to a preset timing condition after receiving the ECS command signal;
  • a second timing module 121 configured to control the time interval between the activation signal and the read command signal to meet a first timing condition, control the time interval between the read command signal and the write command signal to meet a second timing condition, and control the time interval between the write command signal and the precharge signal to meet a third timing condition;
  • the preset timing condition consists of a first timing condition, a second timing condition and a third timing condition.
  • the internal command signal may include an activation signal (Active, represented by ACT in FIG. 4 ), a read command signal (Read, represented by RD in FIG. 4 ), a write command signal (Write, represented by WR in FIG. 4 ) and a precharge signal (Precharge, represented by PRE in FIG. 4 ).
  • the ECS command signal represented by ECS_CMD in FIG. 4
  • the internal command generation module 122 sequentially generates an ACT signal, an RD signal, a WR signal and a PRE signal according to preset timing conditions, wherein the timing between each internal command signal is controlled by the second timing module 121.
  • the time interval between the ACT signal and the RD signal is represented by tRCD
  • the time interval between the RD signal and the WR signal is represented by WL
  • the time interval between the WR signal and the PRE signal is represented by tWR.
  • the internal command generation module first generates an ACT signal, and under the control of the second timing module 121, the ACT signal is delayed by tRCD to obtain the RD signal, and then under the control of the second timing module 121, the RD signal is delayed by WL to obtain the WR signal, and under the control of the second timing module 121, the WR signal is delayed by tWR to obtain the PRE signal.
  • the ECS control module 11 controls the MPC signal, REFab signal and Self_REF signal in the automatic ECS operation mode and the manual ECS operation mode respectively to generate an ECS command signal to the command generation module 12.
  • the minimum time required for each execution of the ECS operation is recorded as tECSc.
  • the counting pointer refers to the clock signal of the address counting module
  • the timing between the command signals satisfies tRCD, WL, tWR, so that an ECS operation is completed within tECSc, that is, the sum of tRCD, WL, and tWR is less than (or equal to) tECSc, ensuring that the execution of the ECS operation will not time out.
  • the timing control between the command signals can be specifically implemented by a delay chain (Delay Line).
  • the ECS operation can be implemented by controlling the storage array by the storage control module.
  • FIG5 a partial structural diagram of an ECS circuit provided by an embodiment of the present disclosure is shown.
  • the ECS circuit 10 further includes a storage control module 15 and a storage array 16, the storage array 16 includes at least one storage group, the storage group includes at least one storage block, the storage block includes at least one row and at least one column, wherein:
  • a storage control module 15 configured to receive an internal command signal and perform an ECS operation on the storage array according to the internal command signal
  • the storage control module 15 is further configured to generate an error signal if error information is detected when executing the ECS operation, and send the error signal to the error tracking and recording module 14 .
  • FIG6 shows a schematic diagram of the composition structure of a storage array 16 provided in an embodiment of the present disclosure.
  • the storage array 16 (also referred to as Array, DRAM Array) includes 4 storage groups (Bank Growp, BG): BG0, BG1, BG2 and BG3, each storage group includes 4 storage blocks (Bank, BA): BA0, BA1, BA2 and BA3, taking BA3 in BG1 as an example, the storage block BA3 includes 6 rows (Row): ROW0, ROW1, ROW2, ROW3, ROW4 and ROW5, and the storage block BA3 includes 5 columns (Column, Col): Col0, Col1, Col2, Col3 and Col4.
  • a circle represents a storage bit. For example, in BA3, ROW0 and Col0 can locate the storage bit Bit00.
  • Each ECS operation is performed on a storage bit in the storage array 16.
  • command generation module 12 generates an internal command signal and sends it to the storage control module 15 (also called DRAM control module, DRAM Control).
  • the storage control module 15 performs ECS operations on the storage bits in the storage array 16 according to the internal command signal.
  • the ECS operation may include: an activation operation, a read operation, an error correction operation, a write operation, and a precharge operation.
  • the storage control module 15 first receives the ACT signal, activates the word line of the corresponding address, and then receives the RD signal to read the codeword from the storage bit.
  • the ECS circuit may also include an error correction circuit, which executes an error check and correction (Error Check and Correct, ECC) algorithm, and the read codeword will be sent to the error correction circuit for verification.
  • the codeword may include data and parity check, and the error correction code may be used to generate the parity check from the data.
  • the error correction circuit may check the error of the codeword, and correct the error of the codeword to generate the corrected codeword.
  • the write operation is performed to write the corrected codeword into the storage bit.
  • the PRE signal is received, precharge is performed.
  • ECC_Error ECC error signal
  • the embodiment of the present disclosure generates an internal command signal according to the ECS command signal, and performs an ECS operation according to the internal command signal, thereby enabling error checking and clearing of the storage array.
  • the storage array 16 here may refer to a storage particle (Die) in the DRAM.
  • Die storage particle
  • the ECS operation is performed in the same manner to achieve complete error checking and clearing of the DRAM.
  • the address counting module While the storage control module performs ECS operation on the storage array according to the internal command signal, the address counting module also performs address counting according to the internal command signal to generate a counting end signal.
  • the address counting module counts according to the PRE signal, and the PRE signal serves as the clock signal of the address counting module.
  • the address counting module can count the columns, rows, storage blocks and storage groups of the storage array respectively, and when the counting is completed, generate a counting end signal to send to the error tracking and recording module.
  • the counting end signal includes a column end signal indicating that the counting of each storage bit in a row is completed, a row end signal indicating that the counting of each row in a storage block is completed, a storage block end signal indicating that the counting of each storage block in a storage group is completed, a storage group end signal indicating that the counting of each storage group in the storage array is completed, and an ECS end signal indicating that the counting of all storage bits in the entire storage array is completed.
  • the address calculation module will also send address information such as column address information, storage block information, storage group information, etc. to the error tracking and recording module, so that the error tracking and recording module can save the required address information.
  • FIG7 shows a schematic diagram of the composition structure of an address counting module 13 provided in an embodiment of the present disclosure.
  • the address counting module 13 includes a column counting module 131, a row counting module 132 and an array counting module 133, wherein:
  • the column counting module 131 is configured to receive a precharge signal, count the columns of the target row according to the precharge signal, and generate a column output signal and a column end signal when the column counting of the target row is completed;
  • the row counting module 132 is configured to receive the precharge signal and the column output signal, and count the rows of the target storage block according to the precharge signal and the column output signal; when the row counting of the target storage block is completed, generate a row output signal and a row end signal;
  • the array counting module 133 is configured to receive a precharge signal and a row output signal, count the storage blocks of the target storage group according to the precharge signal and the row output signal; generate a storage block output signal and a storage block end signal when the storage block count of the target storage group is completed; and count the storage groups of the storage array according to the precharge signal and the storage block output signal; generate a storage group end signal and an ECS end signal when the storage group count of the storage array is completed.
  • PRE represents the precharge signal
  • Col_Wrap represents the column output signal
  • COL_END represents the column end signal
  • Row_Wrap represents the row output signal
  • ROW represents the row address information
  • BA represents the storage block address information
  • BG represents the storage group address information
  • the storage block address information and the storage group address information are collectively recorded as BG/BA in Figure 7
  • ECS_END represents the ECS end signal, and these address information need to be sent to the error tracking recording module 14.
  • the row end signal (also called ROW_END) indicates that the row count in a storage block is completed
  • the storage block end signal (also called BA_END) indicates that the storage block count in a storage group is completed
  • the storage group end signal (also called BG_END) indicates that the count of all storage groups in the storage array is completed.
  • each BA in the storage array 16 is the same as that of BA3 in BG1.
  • each storage bit is recorded as Bitxy, where x represents the row where the storage bit is located in the BA, and y represents the column where the storage bit is located in the BG.
  • Bit32 represents the storage bit located by ROW3 and Col2 in the BA, and the storage bit currently being subjected to the ECS operation is recorded as the target storage bit.
  • the row, storage block, and storage group to which the target storage bit belongs are recorded as the target row, target storage block, and target storage group, respectively.
  • each counting module uses the PRE signal as a clock.
  • the column counting module 131 can count the storage bits included in each row of the storage array 16 in sequence. In this way, in a complete ECS process of the storage array 16, the ECS operation is first performed in sequence on each storage bit in the first row ROW0 in BA0 in BG0. When the ECS operation is performed on Bit00, the corresponding PRE signal will be sent to the clock end of the column counting module 131 (CNT_CLK is used in FIG. 7 to represent the clock end of each counting module). Each time a PRE signal is received, the column count value of ROW0 will increase by 1. It can be understood that the column count value represents the number of storage bits in the target row that have completed the ECS operation.
  • the column counting module 131 will generate a Col_Wrap signal and a COL_END signal, wherein the Col_Wrap signal is sent to the row counting module 132, and the COL_END signal is sent to the error tracking and recording module. After completing the column counting of ROW0, the column counting module 131 will clear the count value, and then continue to count the columns of ROW1, and count each row of the storage array 16 in turn according to this process until the column counting of each row of the storage array 16 is completed. In other words, the column counting module 131 is also configured to continue to perform the column counting of the next target row after generating the column output signal and the column end signal until the column counting of each row in the storage array is completed.
  • the row counting module 132 counts according to the PRE signal and the Col_Wrap signal. Still taking BA0 in BG0 as an example, specifically, after the column counting module 131 completes the counting of ROW0, it will generate a Col_Wrap signal and send it to the row counting module 132, and the row count value of the target storage block counted by the row counting module 132 will be increased by 1. It can be understood that the row count value represents the number of rows in the target storage block that have completed the ECS operation.
  • the column counting module 131 After completing the counting of ROW1, the column counting module 131 will send another Col_Wrap signal to the row counting module 132, and the row count value of the target storage block will continue to increase by 1, ..., since BA0 includes 6 rows, then when the row count value of the target storage block is 6, it means that the row counting of BA0 is completed.
  • the row counting module 132 will generate a Row_Wrap signal and row address information (ROW), wherein the Row_Wrap signal is sent to the storage block counting module 1331, and the row address information will be sent to the error tracking and recording module 14.
  • the row counting module 132 will also generate a row end signal (ROW_END) to indicate that the row counting in the target storage block is completed. After completing the row counting of BA0, the row counting module 132 will clear the count value to zero, and then continue to count BA1, and count each BA of the storage array 16 in turn according to this process until the counting of each BA in the storage array 16 is completed. In other words, the row counting module 132 is also configured to continue to perform row counting of the next target storage block after generating the row output signal and the row end signal until the row counting of each storage block in the storage array is completed.
  • ROW_END row end signal
  • the array counting module 133 counts not only the storage blocks but also the storage groups.
  • FIG8 which shows a schematic diagram of the composition structure of another address counting module 13 provided in an embodiment of the present disclosure.
  • the array counting module includes a storage block counting module 1331 and a storage group counting module 1332, wherein:
  • the storage block counting module 1331 is configured to receive a precharge signal and a row output signal, count the storage blocks of the target storage group according to the precharge signal and the row output signal; and generate a storage block output signal and a storage block end signal when the storage block counting of the target storage group is completed;
  • the storage group counting module 1332 is configured to receive the precharge signal and the storage block output signal, count the storage groups of the storage array according to the precharge signal and the storage block output signal; and generate a storage group end signal and an ECS end signal when the storage group counting of the storage array is completed.
  • the storage block counting module 1331 counts according to the PRE signal and the Row_Wrap signal. Still taking BG0 as an example, after completing the counting of BA0, the row counting module 132 will generate a Row_Wrap signal and send it to the storage block counting module 1331, and the storage block count value of the target storage group counted by the storage block counting module 1331 will increase by 1. It can be understood that the storage block count value represents the number of storage blocks in the target storage group that have completed the ECS operation.
  • the row counting module 132 After completing the counting of BA1, the row counting module 132 will generate another Row_Wrap signal and send it to the storage block counting module 1331, and the storage block count value of the target storage group will continue to increase by 1, ..., since BG0 includes 4 BAs, when the storage block count value of the target storage group is 4, it means that the storage block counting of BG0 is completed.
  • the storage block counting module 1331 will generate a BA_Wrap signal and storage block address information (BA), wherein the BA_Wrap signal is sent to the storage group counting module 1332, and the storage block address information will be sent to the error tracking and recording module 14.
  • BA BA_Wrap signal and storage block address information
  • the storage block counting module 1331 will also generate a storage block end signal (BA_END) to indicate that the storage block counting in the target storage group is completed.
  • BA_END storage block end signal
  • the storage block counting module 1331 will clear the count value, and then continue to count the rows of BG1, and count each BG of the storage array 16 in turn according to this process until the counting of each BG in the storage array 16 is completed. That is to say, in the array counting module 133, the storage block counting module 1331 is also configured to continue to execute the storage block counting of the next target storage group after generating the storage block output signal and the storage block end signal, until the storage block counting of each storage group in the storage array is completed.
  • the storage group counting module 1332 counts according to the PRE signal and the BA_Wrap signal. After completing the counting of BG0, the storage block counting module 1331 will generate a BA_Wrap signal and send it to the storage group counting module 1332, and the storage group count value will increase by 1. It can be understood that the storage group count value represents the number of storage groups that have completed the ECS operation in the storage array 16.
  • the storage block counting module 1331 After completing the counting of BG1, the storage block counting module 1331 will generate another BA_Wrap signal and send it to the storage group counting module 1332, and the storage group count value will continue to increase by 1, ..., since the storage array 16 includes 4 BGs, when the storage group count value is 4, it means that the storage group count of the storage array 16 is completed, that is, each storage bit in the storage array 16 has completed the ECS operation.
  • the storage group counting module 1332 will generate storage group address information (BG) and ECS_END signal, wherein the storage group address information and ECS_END signal will be sent to the error tracking and recording module 14.
  • the storage group counting module 1332 will also generate a storage group end signal (BG_END) to indicate that the storage group counting in the storage array is completed. After the storage group counting is completed, the storage group counting module 1332 will clear the count value until the next ECS operation is performed on the storage array 16, and continue to count according to the above process.
  • BG_END storage group end signal
  • the storage block counting module 1331 is configured to count storage blocks of the storage group
  • the storage group counting module 1332 is configured to count storage groups in the storage array.
  • the storage block counting module 1331 and the storage group counting module 1332 can be integrated in the array counting module 133 to realize related functions.
  • each output signal and count signal (or ECS command signal, etc.) generated can be a high-level pulse. That is, when certain conditions are met, these signals are in a valid state, so that the corresponding module can generate other signals or perform counting, reading or writing operations according to these signals.
  • the main functions of the address counting module are as follows: In order to perform complete error checking and clearing on the DRAM, the rows and columns in all storage blocks in all storage groups must be accessed. For each ECS operation, the address counting module increases the column address count (i.e., the column count of the target row) after each internal PRE command signal. When the column address count of the target row is completed, the row address count (i.e., the row count of the target storage block) begins to increase until the codewords of each row in a storage block are accessed. Then the storage block count (i.e., the storage block count of the target storage group) begins to increase, and the previous storage block access codeword process is repeated. When the counts of all storage blocks in a storage group are completed, the storage group count (storage group count) begins to increase until all storage blocks of the DRAM are accessed, and a complete error checking and clearing operation is completed.
  • the column address count i.e., the column count of the target row
  • the row address count i.e., the row count
  • the PRE command signal when performing the ECS operation is used as the clock of the address counting module to count the rows, storage blocks and storage groups respectively. No additional clock is required, and it is possible to accurately determine whether the ECS operation of the rows, storage blocks and storage groups is completed.
  • the internal command signal PRE generated by the command generation module is used as the clock signal of the address counting module.
  • the count of the column counting module also referred to as the column address counter, COL_CNT
  • the Col_Wrap signal is output as the input of the row counting module (also referred to as the row address counter, ROW_CNT).
  • the count of the row counting module starts to increase.
  • Row_Wrap is output as the input of the array counting module (also referred to as the BG/BA counter, BA/BG_CNT).
  • the ECS_END signal is output, indicating that a complete error check and clearing is completed.
  • the output COL_END signal indicates that a row count is completed, which is applied to the row mode of the error counter.
  • the address counting module sends the counting end signal and address information to the error tracking and recording module, and the error tracking and recording module generates an error tracking signal according to the counting end signal, address information and error signal to record the error information of the ECS operation.
  • the counting end signal mainly includes the column end signal and the ECS end signal
  • the address information mainly includes the row address information, the storage block address information and the storage group address information.
  • FIG9 shows a specific structural diagram of an ECS circuit 10 provided by an embodiment of the present disclosure.
  • the error tracking and recording module 14 is composed of a first error tracking and recording module 141 and a second error tracking and recording module 142 .
  • the first error tracking and recording module 141 is configured to receive a counting mode signal, and when the counting mode signal is a first value, determine that the counting mode of the first error tracking and recording module 141 is a codeword counting mode; or, when the counting mode signal is a second value, determine that the counting mode of the first error tracking and recording module 141 is a row counting mode.
  • the first error tracking and recording module 141 (also referred to as ERROR_COUNT, EC) has two working modes, namely, a code word counting mode and a row counting mode, and the two working modes can be switched according to a counting mode signal, wherein the counting mode signal can be MR14 OP[5] (MRS is used to represent MR14 OP[5] in FIG. 9 ).
  • the counting mode signal can be MR14 OP[5] (MRS is used to represent MR14 OP[5] in FIG. 9 ).
  • the code word counting mode is executed to count the number of code word errors in the storage array
  • the row counting mode is executed to count the number of rows in the storage array that have at least one code word error.
  • the first value may be a logic 1 indicating a high level
  • the second value may be a logic 0 indicating a low level
  • the first value may be a logic 0 indicating a low level
  • the second value may be a logic 1 indicating a high level
  • the working mode of the first error tracking and recording module is determined by the counting mode signal, which can not only count the code words with error information in the storage array, but also count the rows with at least one error information in the storage array, thereby increasing the flexibility of recording error information. In practical applications, it can be set as required.
  • the first error tracking and recording module 141 is configured to receive an error signal, count codewords according to the error signal, and determine a first count value when an ECS end signal is received; and compare the first count value with a first threshold, and save the first count value when the first count value is greater than or equal to the first threshold; wherein the first count value is used to characterize the number of codewords having error information in the storage array.
  • the error information mainly refers to the code word error information, so the error information can also be called a code word error.
  • the first error tracking and recording module needs to count the code words with error information in the storage array.
  • an error signal represented by ECC_Error in FIG. 9
  • ECC_Error can be a high-level pulse, so that the first error tracking and recording module can count the code words with error information in the storage array according to ECC_Error, and when the ECS end signal (represented by ECS_END in FIG.
  • the storage array has completed a complete ECS operation, and at this time the first error tracking and recording module stops counting and obtains the first count value. It can be understood that the first count value represents the number of code words with error information in the storage array.
  • the location where the first count value is saved may be mode register 20 (MR20).
  • the DRAM may ignore the number of codeword errors that is less than the first threshold, that is, when the first count value is less than the first threshold, the first count value will not be saved in MR20, and the first count value will be saved only when the first count value is greater than or equal to the first threshold.
  • the first threshold value may be determined by the error count threshold value and the storage density of the storage array, wherein the error count threshold value (Error Threshold Count, referred to as ETC) may be set according to the mode register signal MR15 OP[2:0] (in FIG. 9 , MRS may also represent MR15 OP[2:0]).
  • ETC Error Threshold Count
  • ETC is 4; when OP[2:0] is 001B, ETC is 16; when OP[2:0] is 010B, ETC is 64; when OP[2:0] is 011B, ETC is 256; when OP[2:0] is 100B, ETC is 1024; when OP[2:0] is 101B, ETC is 4096.
  • the default setting of ETC is 256 per memory cell, where 1 memory cell may represent 1Gb.
  • the storage density of the storage array is 16Gb and the ETC is 4, then when the number of codeword errors per Gb is less than 4, it will be ignored.
  • the first error tracking and recording module can count the codewords containing error information in the storage array to obtain a first count value, and save the first count value in the mode register according to the first threshold value, thereby ensuring that the first count value is saved for subsequent needs only when the number of error information is too large, thereby saving power consumption and storage space.
  • the first error tracking and recording module is configured to receive an error signal and a column end signal, perform an error row count according to the error signal and the column end signal, and determine a second count value when an ECS end signal is received; and compare the second count value with a second threshold value, and save the second count value when the second count value is greater than the second threshold value; wherein the second count value is used to characterize the number of rows in the storage array that have at least one error information.
  • the first error tracking and recording module needs to count the rows in the storage array that have at least one error information, that is, the second count value represents the number of rows that have at least one codeword error.
  • the first error tracking and recording module in order to count the rows with at least one error message, needs to receive ECC_Error and column end signal (Col_END).
  • ECC_Error indicating error message
  • the first error tracking and recording module 141 will count according to ECC_Error to obtain the row error count value.
  • Col_END it means that the storage bits in the current row have completed a complete ECS operation.
  • the row error count value of the current row is greater than 0, it means that there is at least one codeword error in the current row, then the second count value is increased by 1, otherwise, the second count value is not increased by 1, and then the row error count value is cleared, and the count is restarted according to ECC_Error.
  • the next Col_END it is continued to determine whether the second count value needs to be increased by 1 according to the row error count value until ECS_END is received, indicating that the storage array has completed a complete ECS operation.
  • the first error tracking and recording module stops counting and obtains the second count value.
  • ECC_Error may also be a pulse signal generated when a row with a codeword error is detected.
  • the first error tracking and recording module directly counts the ECC_Error, and obtains a second count value representing the number of rows with codeword errors.
  • the first error tracking module may also be connected to a selection module, and the selection module selects a codeword counting mode or a row counting mode according to a counting mode signal.
  • the selection module In the codeword counting mode, the selection module generates a first pulse signal according to ECC_Error, and the first error tracking module counts the first pulse signal to obtain a first count value; in the row counting module, the selection module generates a second pulse signal according to ECC_Error, and the first error tracking module counts the second pulse signal to obtain a second count value.
  • the saving location may be mode register 20 (indicated by MR20 in FIG. 9 ).
  • the DRAM may ignore the number of row errors that is less than the second threshold, that is, when the second count value is less than the second threshold, the second count value will not be saved in MR20, and the second count value will be saved only when the second count value is greater than or equal to the second threshold.
  • the second threshold is 4, if the second count value is greater than or equal to 4, the second count value is loaded into MR20 for storage, otherwise it is not stored. Then, the second count value is reset, and the count is restarted when the next completed ECS operation is executed.
  • the second threshold may be the aforementioned ETC, and the second threshold may be determined in the same manner as the first threshold.
  • the first error tracking and recording module can count the rows with error information in the storage array to obtain a second count value, and save the second count value in the mode register according to the second threshold value, thereby ensuring that the second count value is saved for subsequent needs only when the number of rows with error information is too large, thereby saving power consumption and storage space.
  • the second error tracking and recording module 142 is configured to receive an error signal, and count the error information of the target row according to the error signal and the column end signal, and after determining the third count value of the target row, compare the third count value with the target count value stored in the first register module, if the third count value is greater than the target count value, clear the target count value stored in the first register module, and save the third count value as the target count value in the first register module; and continue to count errors for the next target row according to the error signal and the column end signal until the ECS end signal is received, and then determine the target count value stored in the first register module; wherein the third count value is used to characterize the number of codewords with error information in the target row.
  • the second error tracking and recording module 142 can count the codeword errors of each row in the storage array, and save the number of codeword errors of the row with the largest number of codeword errors and the address information of the row. Among them, the second error tracking and recording module 142 can count the error information of each row according to ECC_Error and Col_END. For example, count the error information of the i-th row in the storage array. Assuming that the storage array includes a total of N rows, N is an integer greater than 0, then i is an integer greater than 0 and less than or equal to N.
  • the Col_END signal When the Col_END signal is received, it means that the storage bits of the i-th row have completed the ECS operation. At this time, the error information counting of the i-th row can be ended, and the obtained count value is called the third count value. It can be understood that the third count value represents the number of error information (i.e., the number of error codewords) in the i-th row.
  • the third count value corresponding to the first row is saved as the target count value in the first register module, wherein the first register module may be the mode register 19 (indicated by MR[19] in FIG. 9 ); then continue to count errors of the second row, and compare the obtained third count value with the target count value already saved in the register, if the third count value corresponding to the second row is greater than the target count value, then clear the target count value saved in the first register module, and save the third count value corresponding to the second row as the new target count value in the first register module...
  • the second error tracking and recording module is configured to receive an error signal, count the error information of the first row according to the error signal and the column end signal, and after determining the third count value of the first row, save the third count value of the first row as the target count value in the first register module.
  • the target row is counted in the aforementioned manner. At this time, the target row represents other rows except the first row. In this case, even if the third count value of the first row is 0, it can be saved in the first register module first. For the second row, the corresponding third count value is compared with 0 until the final target count value is determined.
  • the second error tracking and recording module is also configured to save the address information corresponding to the target count value in the second register module when the target count value is saved in the first register module; wherein the address information includes row address information, storage block address information and storage group address information corresponding to the target count value.
  • the second register module may include mode register 16, mode register 17 and mode register 18, which are represented by MR[16:18] in Figure 9. It can be understood that each time the target count value in the first register module is replaced by a larger third count value, the address information in the second register module is also replaced by the corresponding address information. In this way, when the ECS end signal is received, the second register module stores the row address information, storage block address information and storage group address information of the row with the largest number of error information.
  • the second error tracking and recording module is also configured to, after receiving the ECS end signal, compare the target count value currently stored in the first register module with the third threshold value; if the target count value is greater than or equal to the third threshold value, retain the target count value stored in the first register module and the address information stored in the second register module; if the target count value is less than the third threshold value, clear the target count value stored in the first register module and the address information stored in the second register module.
  • the disclosed embodiment can also save the target count value and the corresponding address information only when the final target count value is greater than the third threshold value.
  • the third threshold value is also called the row error count threshold (Row Error threshold Count, RETC).
  • RETC Row Error threshold Count
  • the value of RETC can be fixed to 4. Taking the value of RETC equal to 4 as an example, if the final target count value is greater than 4, the target count value in the first register module is retained, and the address information in the second register module is retained, otherwise, the address information of the current target count value is cleared.
  • the address information of the final target count value is BG1-BA2-ROW1, which means that the target row is the second row ROW1 in the storage block BA2 in the storage group BG1 in the storage array.
  • the row address information, the storage block address information and the storage group address information are sent to the error tracking and recording module during the counting process of the address counting module, so that the error tracking and recording module can accurately save the address information corresponding to the target count value.
  • the second error tracking and recording module can save the information of the row with the largest number of error messages in the mode register according to the third threshold, ensuring that the information of the error row is saved for subsequent needs only when the number of error messages is too large, saving power consumption and storage space.
  • the target count value is represented by REC[5:0] and is stored in MR19.
  • the address information corresponding to the target count value can be represented by MAX_ADD, including row address information, storage block address information and storage group address information, which are respectively stored in MR[16:18].
  • ROW, BG/BA output by the row counting module and the array counting module are used to record the specific information of the row address with the maximum error count so as to be stored in the register.
  • the error tracking signal mainly refers to the first count value or the second count value stored by the first error tracking recording module, and the final target count value and the corresponding address information stored by the second error tracking recording module.
  • error tracking signals can record information such as the number of errors in the storage array.
  • the first count value, the second count value and the target count value can be encoded and stored in a unique hot encoding manner.
  • the error tracking and recording module includes two error counters: the first error tracking and recording module (EC) and the second error tracking and recording module (EPRC).
  • the EC module has two modes, which need to be switched according to MR14 OP[5].
  • ECC_Error and COL_END are used to count how many rows have at least one error.
  • the ECC_Error signal is used to count the number of code word errors.
  • the EPRC module uses ECC_Error, BG/BA, and ROW to record which row has the largest number of error information, and also records the address information MAX_ADD of the row with the largest number of error information.
  • ECC_Error ECC_Error
  • BG/BA BG/BA
  • ROW ROW
  • the address information is loaded into MR[16:18]
  • the error count of the row will be loaded into MR19 according to RETC.
  • the data recorded by EC and EPRC is not loaded directly into the register, but after a complete ECS operation is completed, it is loaded into the corresponding register according to ETC and RETC.
  • module for executing the counting function involved in the embodiment of the present disclosure can be implemented by a synchronous counter or an asynchronous counter, which is not specifically limited here.
  • the disclosed embodiment provides an ECS circuit, which generates an ECS command signal based on a mode control signal to execute an ECS operation, thereby enabling complete error checking and clearing of a memory.
  • an error tracking signal can be generated based on the error signal and the count end signal to record error information of the ECS operation, thereby enabling rapid location of the error information in the memory and repairing it, thereby ultimately improving the performance of the memory.
  • FIG10 a schematic flow chart of an ECS method provided by an embodiment of the present disclosure is shown. As shown in FIG10 , the method may include:
  • S1002 Receive an ECS command signal through a command generation module, and generate an internal command signal according to the ECS command signal, where the internal command signal is used to execute a corresponding ECS operation.
  • S1004 Receive a count end signal and an error signal through an error tracking and recording module, and generate an error tracking signal according to the count end signal and the error signal.
  • the error tracking signal is used to record error information of the ECS operation.
  • the mode control signal includes a multi-purpose command MPC signal or a refresh command signal
  • generating the ECS command signal according to the mode control signal may include:
  • the ECS command signal is generated according to the refresh command signal.
  • ECS operations can be generated based on different command signals.
  • automatic ECS operations can be performed based on the refresh signal (REFab), or based on the self-refresh signal (Self_REF).
  • manual ECS operation mode ECS operations can be performed based on specific MPC signals, or whether to perform ECS operations during self-refresh can be determined in combination with the first mode register signal.
  • generating an ECS command signal according to a mode control signal may include:
  • the ECS identification signal is received through the command control module, and when the ECS identification signal is in a valid state, a refresh command signal is acquired, and an ECS command signal is generated according to the refresh command signal.
  • generating the ECS identification signal by the first timing module may include:
  • the first clock signal is received through the first timing module, counting is performed according to the first clock signal, an ECS identification signal is generated, and the ECS identification signal is sent to the command control module; wherein, when the count value meets the preset condition, the ECS identification signal is in a valid state.
  • the method may further include:
  • the first timing module stops counting
  • the command control module After generating the ECS command signal according to the refresh command signal, the command control module generates a reset signal and sends the reset signal to the first timing module, so that the first timing module restarts counting and controls the ECS identification signal to be in an invalid state.
  • the method may further include:
  • the received refresh command signal is output as an internal refresh signal through the command control module to perform a refresh operation.
  • generating an internal command signal according to an ECS command signal may include:
  • An ECS command signal is received through an internal command generation module, and after receiving the ECS command signal, an activation signal, a read command signal, a write command signal and a precharge signal are sequentially generated according to a preset timing condition; and through a second timing module, a time interval between the activation signal and the read command signal is controlled to meet a first timing condition, a time interval between the read command signal and the write command signal is controlled to meet a second timing condition, and a time interval between the write command signal and the precharge signal is controlled to meet a third timing condition;
  • the preset timing condition consists of a first timing condition, a second timing condition and a third timing condition.
  • the method may further include:
  • An internal command signal is received through a storage control module, and an ECS operation is performed on the storage array according to the internal command signal; and when performing the ECS operation, if error information is detected, an error signal is generated and sent to an error tracking and recording module.
  • performing address counting according to an internal command signal and generating a counting end signal when the target address is finished counting may include:
  • a precharge signal and a row output signal are received through an array counting module, and storage blocks of a target storage group are counted according to the precharge signal and the row output signal; when the storage block count of the target storage group is completed, a storage block output signal and a storage block end signal are generated; and, storage group counts are performed on the storage array according to the precharge signal and the storage block output signal; when the storage group count of the storage array is completed, a storage group end signal and an ECS end signal are generated.
  • receiving a precharge signal and a row output signal through an array counting module, counting storage blocks of a target storage group according to the precharge signal and the row output signal; generating a storage block output signal and a storage block end signal when the storage block count of the target storage group is completed; and counting storage groups of a storage array according to the precharge signal and the storage block output signal; generating a storage group end signal and an ECS end signal when the storage group count of the storage array is completed, may include:
  • the storage group counting module receives the precharge signal and the storage block output signal, and counts the storage groups of the storage array according to the precharge signal and the storage block output signal; when the storage group counting of the storage array is completed, a storage group end signal and an ECS end signal are generated.
  • the method may further include:
  • the column counting module After generating the column output signal and the column end signal, the column counting module continues to perform column counting of the next target row until the column counting of each row in the storage array is completed;
  • the row counting module After generating the row output signal and the row end signal, the row counting module continues to perform row counting of the next target storage block until the row counting of each storage block in the storage array is completed;
  • the storage block counting module After generating the storage block output signal and the storage block end signal, the storage block counting module continues to count the storage blocks of the next target storage group until the storage block counting of each storage group in the storage array is completed.
  • the method may further include:
  • a counting mode signal is received through the first error tracking and recording module, and when the counting mode signal is a first value, the counting mode of the first error tracking and recording module is determined to be a codeword counting mode; or when the counting mode signal is a second value, the counting mode of the first error tracking and recording module is determined to be a row counting mode.
  • generating an error tracking signal according to the counting end signal and the error signal may include:
  • An error signal is received through a first error tracking and recording module, a codeword count is performed according to the error signal, and a first count value is determined when an ECS end signal is received; and the first count value is compared with a first threshold value, and when the first count value is greater than or equal to the first threshold value, the first count value is saved; wherein the first count value is used to characterize the number of codewords having error information in the storage array.
  • generating an error tracking signal according to the counting end signal and the error signal may include:
  • the error signal and the column end signal are received through the first error tracking and recording module, the error row count is performed according to the error signal and the column end signal, and a second count value is determined when the ECS end signal is received; and the second count value is compared with a second threshold value, and when the second count value is greater than the second threshold value, the second count value is saved; wherein the second count value is used to characterize the number of rows in the storage array having at least one error information.
  • generating an error tracking signal according to the count end signal and the error signal may include:
  • An error signal is received through a second error tracking and recording module, and error information of a target row is counted according to the error signal and a column end signal. After a third count value of the target row is determined, the third count value is compared with a target count value stored in the first register module. If the third count value is greater than the target count value, the target count value stored in the first register module is cleared, and the third count value is saved as the target count value in the first register module; and error counting of the next target row is continued according to the error signal and the column end signal until an ECS end signal is received, and the target count value stored in the first register module is determined; wherein the third count value is used to characterize the number of codewords having error information in the target row.
  • the method may further include:
  • the address information corresponding to the target count value is saved in the second register module; wherein the address information includes row address information of the row corresponding to the target count value, storage block address information and storage group address information.
  • the method may further include:
  • the target count value currently stored in the first register module is compared with the third threshold. If the target count value is greater than or equal to the third threshold, the target count value stored in the first register module and the address information stored in the second register module are retained. If the target count value is less than the third threshold, the target count value stored in the first register module and the address information stored in the second register module are cleared.
  • An ECS method provided by an embodiment of the present disclosure generates an ECS command signal based on a mode control signal to execute an ECS operation, thereby enabling complete error checking and clearing of a memory.
  • an error tracking signal can be generated based on the error signal and the count end signal to record error information of the ECS operation, thereby enabling rapid location of the error information in the memory and repairing it, thereby ultimately improving the performance of the memory.
  • Fig. 11 shows a schematic diagram of the composition structure of a memory 20 provided by the embodiment of the present disclosure.
  • the memory 20 may include the ECS circuit 10 described in any one of the above embodiments.
  • the memory 20 may include DRAM.
  • the disclosed embodiment is a new operating mode of DDR5: the overall framework design of the error check and clear mode, which realizes the generation of ECS command signals through MPC, REFab, and SREF in manual and automatic ECS operating modes, and then realizes the internal self-generated commands to perform error checking and clearing operations on the corresponding addresses.
  • the errors found in the ECS operation are recorded in EC and EPRC, and the address counting module count is incremented after each ECS command ends.
  • the timing control between the command generation modules and the timing control module in the ECS design need to ensure that an ECS operation can be completed within tECSc, and a complete error check and clearing of the DRAM is performed at least once within 24 hours.
  • DRAM for DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.
  • the memory 20 since the memory 20 includes the ECS circuit 10 described in the above embodiment, the ECS operation of the memory can be implemented, thereby improving the performance of the memory.
  • the disclosed embodiment generates an ECS command signal based on a mode control signal to execute an ECS operation, thereby enabling complete error checking and clearing of the memory.
  • an error tracking signal can be generated based on the error signal and the count end signal to record the error information of the ECS operation, thereby enabling the location of the error information in the memory to be quickly located and repaired, ultimately improving the performance of the memory.

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Abstract

本公开实施例提供了一种ECS电路、方法和存储器，该ECS电路包括ECS控制模块、命令生成模块、地址计数模块和错误追踪记录模块，其中：ECS控制模块，配置为接收模式控制信号，根据模式控制信号生成ECS命令信号；命令生成模块，配置为根据ECS命令信号生成内部命令信号，内部命令信号用于执行对应的ECS操作；地址计数模块，配置为根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；错误追踪记录模块，配置为接收错误信号，并根据计数结束信号和错误信号生成错误追踪信号，错误追踪信号用于记录ECS操作的错误信息。

Description

一种ECS电路、方法和存储器
相关申请的交叉引用
本公开基于申请号为202211222144.2、申请日为2022年10月08日、发明名称为“一种ECS电路、方法和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种ECS电路、方法和存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
然而，随着存储器的传输速度越来越快、存储单元缩小以及行锤击(Row hammer)等原因，存储器中可能会发生错误，这就需要对存储器进行错误检查并及时纠正检查到的错误。以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，需要至少每24小时对DRAM进行一次完整的错误检查与清除(Error Check and Scrub，ECS)。
发明内容
本公开实施例提供了一种ECS电路、方法和存储器。
第一方面，本公开实施例提供了一种ECS电路，包括ECS控制模块、命令生成模块、地址计数模块和错误追踪记录模块，其中：
所述ECS控制模块，配置为接收模式控制信号，根据所述模式控制信号生成ECS命令信号；
所述命令生成模块，配置为根据所述ECS命令信号生成内部命令信号，所述内部命令信号用于执行对应的ECS操作；
所述地址计数模块，配置为根据所述内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；
所述错误追踪记录模块，配置为接收错误信号，并根据所述计数结束信号和所述错误信号生成错误追踪信号，所述错误追踪信号用于记录所述ECS操作的错误信息。
在一些实施例中，所述模式控制信号包括多用途命令MPC信号或刷新命令信号，其中：
所述ECS控制模块，还配置为在所述ECS操作为手动ECS操作模式的情况下，根据所述MPC信号生成所述ECS命令信号，或者；
所述ECS控制模块，还配置为在所述ECS操作为自动ECS操作模式的情况下，根据所述刷新命令信号生成所述ECS命令信号。
在一些实施例中，所述ECS控制模块包括第一时序模块和命令控制模块，其中：
所述第一时序模块，配置为生成ECS标识信号；
所述命令控制模块，配置为接收所述ECS标识信号，以及在所述ECS标识信号处于有效状态时，获取刷新命令信号，并根据所述刷新命令信号产生所述ECS命令信号。
在一些实施例中，所述第一时序模块，配置为接收第一时钟信号，根据所述第一时钟信号进行计数，生成所述ECS标识信号，并将所述ECS标识信号发送给所述命令控制模块；其中，在计数值满足预设条件时，所述ECS标识信号处于有效状态。
在一些实施例中，所述第一时序模块，还配置为在所述ECS标识信号处于有效状态时，停止 所述计数；
所述命令控制模块，还配置为在根据所述刷新命令信号产生所述ECS命令信号之后，生成复位信号，将所述复位信号发送给所述第一时序模块，以使所述第一时序模块重新开始计数并且控制所述ECS标识信号处于无效状态。
在一些实施例中，所述命令控制模块，还配置为在所述ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号，以执行刷新操作。
在一些实施例中，所述命令生成模块包括内部命令生成模块和第二时序模块，其中：
所述内部命令生成模块，配置为在接收到所述ECS命令信号后，按照预设时序条件依次生成激活信号、读命令信号、写命令信号和预充电信号；
所述第二时序模块，配置为控制所述激活信号和所述读命令信号之间的时间间隔满足第一时序条件，控制所述读命令信号和所述写命令信号之间的时间间隔满足第二时序条件以及控制所述写命令信号和所述预充电信号之间的时间间隔满足第三时序条件；
其中，所述预设时序条件是由所述第一时序条件、所述第二时序条件和所述第三时序条件组成。
在一些实施例中，所述ECS电路还包括存储控制模块和存储阵列，所述存储阵列包括至少一个存储组，所述存储组包括至少一个存储块，所述存储块包括至少一行和至少一列，其中：
所述存储控制模块，配置为接收所述内部命令信号，并根据所述内部命令信号对所述存储阵列执行ECS操作，以及；
所述存储控制模块，还配置为在执行所述ECS操作时，若检测到错误信息，则生成所述错误信号，并将所述错误信号发送给所述错误追踪记录模块。
在一些实施例中，所述地址计数模块包括列计数模块、行计数模块和阵列计数模块，其中：
所述列计数模块，配置为接收所述预充电信号，根据所述预充电信号对目标行进行列计数；在所述目标行的列计数完成时，生成列输出信号和列结束信号；
所述行计数模块，配置为接收所述预充电信号和所述列输出信号，根据所述预充电信号和所述列输出信号对目标存储块进行行计数；在所述目标存储块的行计数完成时，生成行输出信号和行结束信号；
所述阵列计数模块，配置为接收所述预充电信号和所述行输出信号，根据所述预充电信号和所述行输出信号对目标存储组进行存储块计数；在所述目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；以及，根据所述预充电信号和所述存储块输出信号对所述存储阵列进行存储组计数；在所述存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
在一些实施例中，所述阵列计数模块包括存储块计数模块和存储组计数模块，其中：
所述存储块计数模块，配置为接收所述预充电信号和所述行输出信号，根据所述预充电信号和所述行输出信号对目标存储组进行存储块计数；在所述目标存储组的存储块计数完成时，生成所述存储块输出信号和所述存储块结束信号；
所述存储组计数模块，配置为接收所述预充电信号和所述存储块输出信号，根据所述预充电信号和所述存储块输出信号对所述存储阵列进行存储组计数；在所述存储阵列的存储组计数完成时，生成所述存储组结束信号和所述ECS结束信号。
在一些实施例中，所述列计数模块，还配置为在生成所述列输出信号和所述列结束信号之后，继续执行下一目标行的列计数，直至完成所述存储阵列中的每一行的列计数；
所述行计数模块，还配置为在生成所述行输出信号和所述行结束信号之后，继续执行下一目标存储块的行计数，直至完成所述存储阵列中的每一存储块的行计数；
所述阵列计数模块，还配置为在生成所述存储块输出信号和所述存储块结束信号之后，继续执行下一目标存储组的存储块计数，直至完成对所述存储阵列中的每一存储组的存储块计数。
在一些实施例中，所述错误追踪记录模块包括第一错误追踪记录模块，其中：
所述第一错误追踪记录模块，配置为接收计数模式信号，以及在所述计数模式信号为第一值的情况下，确定所述第一错误追踪记录模块的计数模式为码字计数模式；或者，在所述计数模式信号为第二值的情况下，确定所述第一错误追踪记录模块的计数模式为行计数模式。
在一些实施例中，所述第一错误追踪记录模块，配置为在所述计数模式为所述码字计数模式 的情况下，接收所述错误信号，根据所述错误信号进行码字计数，并在接收到所述ECS结束信号时，确定第一计数值；以及将所述第一计数值与第一阈值进行比较，在所述第一计数值大于或者等于所述第一阈值的情况下，将所述第一计数值进行保存；其中，所述第一计数值用于表征所述存储阵列中存在错误信息的码字数量。
在一些实施例中，所述第一错误追踪记录模块，配置为在所述计数模式为所述行计数模式的情况下，接收所述错误信号和所述列结束信号，根据所述错误信号和所述列结束信号进行错误行计数，并在接收到所述ECS结束信号时，确定第二计数值；以及将所述第二计数值与第二阈值进行比较，在所述第二计数值大于所述第二阈值的情况下，将所述第二计数值进行保存；其中，所述第二计数值用于表征所述存储阵列中存在至少一个错误信息的行数量。
在一些实施例中，所述错误追踪记录模块还包括第二错误追踪记录模块，其中：
所述第二错误追踪记录模块，配置为接收所述错误信号，并根据所述错误信号和所述列结束信号对目标行的错误信息进行计数，在确定所述目标行的第三计数值后，将所述第三计数值与第一寄存器模块中存储的目标计数值进行比较，若所述第三计数值大于所述目标计数值，则将所述第一寄存器模块中存储的目标计数值清除，并将所述第三计数值保存为所述第一寄存器模块中的目标计数值；以及继续根据所述错误信号和所述列结束信号对下一目标行进行错误计数，直至接收到所述ECS结束信号后，确定所述第一寄存器模块中存储的目标计数值；其中，所述第三计数值用于表征所述目标行中存在错误信息的码字数量。
在一些实施例中，所述第二错误追踪记录模块，还配置为在将所述目标计数值保存进第一寄存器模块时，将所述目标计数值对应的地址信息保存在第二寄存器模块中；其中，所述地址信息包括所述目标计数值对应的行地址信息、存储块地址信息和存储组地址信息。
在一些实施例中，所述第二错误追踪记录模块，还配置为在接收到所述ECS结束信号后，将所述第一寄存器模块中当前存储的目标计数值与第三阈值进行比较，若所述目标计数值大于或者等于所述第三阈值，则保留所述第一寄存器模块中存储的目标计数值和所述第二寄存器模块中存储的地址信息，若所述目标计数值小于所述第三阈值，则将所述第一寄存器模块中存储的目标计数值和所述第二寄存器模块中存储的地址信息清除。
第二方面，本公开实施例提供了一种ECS方法，应用于如第一方面所述的ECS电路，该方法包括：
通过所述ECS控制模块接收模式控制信号，并根据所述模式控制信号生成ECS命令信号；
通过所述命令生成模块接收所述ECS命令信号，根据所述ECS命令信号生成内部命令信号，所述内部命令信号用于执行对应的ECS操作；
通过所述地址计数模块接收所述内部命令信号，根据所述内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；
通过所述错误追踪记录模块接收所述计数结束信号和错误信号，根据所述计数结束信号和所述错误信号生成错误追踪信号，所述错误追踪信号用于记录所述ECS操作的错误信息。
第三方面，本公开实施例提供了一种存储器，该存储器包括如第一方面所述的ECS电路。
本公开实施例提供了一种ECS电路、方法和存储器，该ECS电路包括ECS控制模块、命令生成模块、地址计数模块和错误追踪记录模块，其中ECS控制模块，配置为接收模式控制信号，根据模式控制信号生成ECS命令信号；命令生成模块，配置为根据ECS命令信号生成内部命令信号，内部命令信号用于执行对应的ECS操作；地址计数模块，配置为根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；所述错误追踪记录模块，配置为接收错误信号，并根据计数结束信号和错误信号生成错误追踪信号，错误追踪信号用于记录ECS操作的错误信息。这样，本公开实施例基于模式控制信号来生成ECS命令信号，以执行ECS操作，从而能够实现对存储器进行完整的错误检查与清除，而且在执行ECS操作完成之后，还可以根据错误信号和计数结束信号来生成错误追踪信号，用以记录ECS操作的错误信息，进而能够快速定位存储器中存在错误信息的位置并进行修复，最终提升存储器的性能。
附图说明
图1为本公开实施例提供的一种ECS电路的组成结构示意图；
图2为本公开实施例提供的一种选择ECS操作模式的选择示意图；
图3为本公开实施例提供的一种ECS控制模块的组成结构示意图；
图4为本公开实施例提供的一种命令生成模块的组成结构示意图；
图5为本公开实施例提供的一种ECS电路的部分结构示意图；
图6为本公开实施例提供的一种存储阵列的组成结构示意图；
图7为本公开实施例提供的一种地址计数模块的组成结构示意图；
图8为本公开实施例提供的另一种地址计数模块的组成结构示意图；
图9为本公开实施例提供的一种ECS电路的具体结构示意图；
图10为本公开实施例提供的一种ECS方法的流程示意图；
图11为本公开实施例提供的一种存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
对本公开实施例进行进一步详细说明之前，先对本公开实施例中涉及的名词和术语进行说明，本公开实施例中涉及的名词和术语适用于如下的解释：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)；
双倍速率(Double Data Rate，DDR)；
第5代DDR标准(DDR5 Specification，DDR5 SPEC)；
多用途命令(Multi-Purpose Command，MPC)；
错误检查与清除(Error Check and Scrub，ECS)；
模式寄存器(Mode Register，MR)；
自动刷新(Auto_Refresh，REFab)；
自刷新(Self_Refresh，Self_REF或者SRE)；
错误检查与纠正(Error Check and Correct，ECC)。
以DDR5 DRAM为例，ECS模式允许DRAM内部读取、修改检测到的错误码字，并将修正后的数据写回存储阵列，同时记录错误计数。它要求至少每24小时对DRAM进行一次完整的错误检查与清除。ECS的操作模式包括自动和手动两种操作模式，可以通过模式寄存器信号MR14OP[7]来选择。在执行自动ECS操作时，可以借助刷新命令信号和自刷新命令信号来得到ECS命令信号，执行手动ECS操作则需要MPC信号，同时MR15还可以决定是否在自刷新时执行手动ECS操作。
为了实现错误检查与清除以及将检测到的错误信息进行记录的功能，本公开实施例提供了一种ECS电路，包括ECS控制模块、命令生成模块、地址计数模块和错误追踪记录模块，其中：ECS控制模块，配置为接收模式控制信号，根据模式控制信号生成ECS命令信号；命令生成模块，配置为根据ECS命令信号生成内部命令信号，内部命令信号用于执行对应的ECS操作；地址计数模块，配置为根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；错误追踪记录模块，配置为接收错误信号，并根据计数结束信号和错误信号生成错误追踪信号，错误追踪信号用于记录ECS操作的错误信息。这样，本公开实施例基于模式控制信号来生成ECS命令 信号，以执行ECS操作，从而能够实现对存储器进行完整的错误检查与清除，而且在执行ECS操作完成之后，还可以根据错误信号和计数结束信号来生成错误追踪信号，用以记录ECS操作的错误信息，进而能够快速定位存储器中存在错误信息的位置并进行修复，最终提升存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图1，其示出了本公开实施例提供的一种ECS电路10的组成结构示意图。如图1所示，该ECS电路10可以包括ECS控制模块11、命令生成模块12、地址计数模块13和错误追踪记录模块14，其中：
ECS控制模块11，配置为接收模式控制信号，根据模式控制信号生成ECS命令信号；
命令生成模块12，配置为根据ECS命令信号生成内部命令信号，内部命令信号用于执行对应的ECS操作；
地址计数模块13，配置为根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；
错误追踪记录模块14，配置为接收错误信号，并根据计数结束信号和错误信号生成错误追踪信号，错误追踪信号用于记录ECS操作的错误信息。
需要说明的是，本公开实施例涉及集成电路设计中，ECS电路的总体框架设计，特别涉及DRAM DDR5芯片中，需要在至少每24小时对DRAM进行一次完整的错误检查与清除。该ECS电路的总体框架是用来产生ECS命令信号和一些内部命令信号，以及错误追踪信号，用来检测错误信息的同时执行内部读写检错和修复。可以应用于DRAM DDR5芯片中执行ECS功能的相关电路，但不局限于此范围，其他存储器芯片、以及其他内部产生命令、时序控制以及计数电路等均可采用此设计。
还需要说明的是，以应用于DRAM中执行ECS操作为例，本公开实施例提供的ECS电路可以实现对存储阵列的错误检查与清除。简单来说，本公开实施例要实现的功能是：在手动ECS操作模式和自动ECS操作模式下，实现利用多用途命令信号(可以用MPC表示)或刷新命令信号产生ECS命令信号，并产生内部执行ECS操作所必要的内部命令信号，以对DRAM进行完整的错误检查与清除，并利用其它模块追踪和记录检测到的错误信息。其中，刷新命令信号可以包括刷新信号(可以用REFab表示)和自刷新信号(可以用Self-REF表示)。这样，在本公开实施例中，对于ECS命令信号的产生，可以是基于MPC信号或者刷新命令信号来产生的，或者也可以是基于其它合适的信号来产生的，这里不作任何限定。
如图1所示，ECS控制模块11是用来产生ECS命令信号的模块，每生成一个ECS命令信号，DRAM就会对应执行一次ECS操作。这里，一次ECS操作是针对存储阵列中的一个存储位执行的，ECS操作用于判断被检测的存储位是否存在码字错误，并在检测到码字错误时进行纠错。
对于生成ECS命令信号的方式，在一些实施例中，ECS控制模块，还配置为接收ECS模式选择信号，以及在ECS模式选择信号为第一值的情况下，确定ECS操作模式为手动ECS操作模式，或者，在ECS模式选择信号为第二值的情况下，确定ECS操作为自动ECS操作模式。
在一些实施例中，ECS控制模块11，还配置为在ECS操作为手动ECS操作模式的情况下，根据MPC信号生成ECS命令信号，或者；
ECS控制模块11，还配置为在ECS操作为手动ECS操作模式的情况下，接收第一模式寄存器信号，根据第一模式寄存器信号和刷新命令信号生成ECS命令信号，或者；
ECS控制模块11，还配置为在ECS操作为自动ECS操作模式的情况下，根据刷新命令信号生成ECS命令信号。
需要说明的是，参见图2，其示出了本公开实施例提供的一种选择ECS操作模式的选择示意图。如图2所示，ECS操作模式包括手动ECS操作模式和自动ECS操作模式，可以根据ECS模式选择信号进行选择，其中，ECS模式选择信号可以为模式寄存器信号MR14 OP[7]，当MR14 OP[7]等于1时，DRAM执行手动ECS操作模式，当MR14 OP[7]等于0时，执行自动ECS操作模式。在本公开实施例中，1表示高电平的逻辑1，0表示低电平的逻辑0。
在手动ECS操作模式下，ECS控制模块会在收到特定的MPC信号时，根据MPC信号生成ECS命令信号，以执行ECS操作；这里，特定的MPC信号可以是指MPC信号的值为：00001100。
另外，在手动ECS操作模式下，还会根据刷新命令信号和第一模式寄存器信号决定是否执行ECS操作，在这种情况下，刷新命令信号是指自刷新信号(Self-REF)，第一模式寄存器信号可以 是指模式寄存器信号MR15 OP[3]。可以理解的是，在接收到Self-REF信号时，DRAM需要执行自刷新操作，MR15 OP[3]可以决定在执行自刷新操作之前是否需要执行一次ECS操作，当MR15OP[3]等于1时，在进入自刷新时需要执行一次ECS操作，也就是ECS控制模块会根据特定位取值为1的第一模式寄存器信号和Self-REF信号生成ECS命令信号，以执行ECS操作；而当MR15OP[3]等于0时，在自刷新时不会执行ECS操作，即ECS控制模块不会生成ECS命令信号，DRAM执行自刷新操作。
在自动ECS操作模式下，刷新命令信号包括自刷新信号(Self-REF)和刷新信号(REFab)，在接收到REFab信号时，可以根据REFab信号生成ECS命令信号，以执行ECS操作；或者，在进入自刷新时，也可以根据Self-REF信号生成ECS命令信号，以执行ECS操作，其中，执行错误检查与清除的平均间隔时间可以用tECSint表示。
也就是说，在不同的ECS操作模式下，可以基于不同的命令信号来产生ECS命令信号以执行ECS操作，其中，在自动ECS操作模式下，可以基于刷新信号(REFab)来执行自动ECS操作，或者基于自刷新信号(Self_REF)来执行自动ECS操作，在手动ECS操作模式下，可以基于特定的MPC信号执行ECS操作，或者结合第一模式寄存器信号决定在自刷新时是否执行ECS操作。这样，ECS控制模块可以根据MPC信号和/或刷新命令信号来生成ECS命令信号，以执行ECS操作，简化了产生ECS操作所需的流程；同时，还可以结合模式寄存器信号选择不同的ECS操作模式，并决定是否需要执行ECS操作，增加了执行ECS操作的灵活性。
进一步地，对于ECS控制模块的组成，参见图3，其示出了本公开实施例提供的一种ECS控制模块11的组成结构示意图。如图3所示，在一些实施例中，ECS控制模块11包括第一时序模块111和命令控制模块112，其中：
第一时序模块111，配置为生成ECS标识信号；
命令控制模块112，配置为接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
需要说明的是，如图3所示，ECS控制模块11主要包括第一时序模块111和命令控制模块112。其中，命令控制模块112通过模式寄存器信号MR14 OP[7]来选择执行哪一种ECS操作模式，当MR14 OP[7]＝0时，执行自动ECS操作模式，也是DDR5的默认模式；当MR14 OP[7]＝1时，执行手动ECS操作模式，同时需要MPC信号的取值为OP[7:0]＝00001100。
还需要说明的是，由于DRAM要求至少在24小时内对整个存储阵列进行一次完整的错误检查与清除，在自动ECS操作模式下，需要第一时序模块来规划ECS的间隔时间，以确保24小时内完成所有存储阵列的错误检查与清除。
也就是说，在自动ECS操作模式下，第一时序模块111可以生成ECS标识信号(在图3中用ECS_Flag表示)发送给命令控制模块112，而且每间隔一定的预设时间，该ECS_Flag信号处于有效状态。命令控制模块112接收ECS_Flag信号，并在ECS_Flag信号处于有效状态时，获取刷新命令信号，以根据获取到的刷新命令信号生成ECS命令信号(在图3中用ECS_CMD表示)。这里的刷新命令信号可以包括下述至少之一：刷新信号(REFab)和自刷新信号(Self-REF)。
对于第一时序模块规划时序的方式，在一些实施例中，第一时序模块，配置为接收第一时钟信号，根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，ECS标识信号处于有效状态。
需要说明的是，第一时序模块在进行时序规划时，可以是对第一时钟信号进行计数，在计数值满足预设条件时，使得ECS_Flag处于有效状态，此时命令控制模块112会获取刷新命令信号，从而产生用于指示执行ECS操作的ECS命令信号。需要注意的是，这时候获取的刷新命令信号是在计数值满足预设条件之后出现的刷新命令信号；因此，与计数值满足预设条件的时刻相比，这时候获取的刷新命令信号具体是指下一时刻出现的刷新命令信号，也可简称为下一个刷新命令信号。如此，根据计数值是否满足预设条件来规划ECS操作的间隔时间，能够确保24小时内进行一次完整的错误检查与清除。
其中，第一时钟信号可以是由振荡器产生的具有固定频率的时钟信号。示例性地，如果第一时钟信号的周期为4.4微秒(microseconds，us)，对于16GB的内存配置，为了满足24小时内对DRAM完成一次完整的错误检查与清除，ECS操作的时间间隔为644us，那么需要计数大约644/4.4＝146次时表示一次计数完成，此时计数值满足预设条件。即计数值达到146时，可以产生 处于有效状态的ECS标识信号。
在一些实施例中，第一时序模块，还配置为在ECS标识信号处于有效状态时，停止计数；
命令控制模块，还配置为在根据刷新命令信号产生ECS命令信号后，生成复位信号，将复位信号发送给第一时序模块，以使第一时序模块重新开始计数并且控制ECS标识信号处于无效状态。
需要说明的是，在本公开实施例中，ECS_Flag信号可以是处于有效状态，也可以是处于无效状态。其中，第一时序模块111会在每间隔一段时间之后产生处于有效状态的ECS_Flag信号，用于产生ECS命令信号；命令控制模块112在产生ECS命令信号之后，还会再产生一个复位信号(在图3中用Reset表示)发送给第一时序模块111，使ECS_Flag信号处于无效状态，同时使第一时序模块111重新开始计数。
在一些实施例中，命令控制模块，还配置为在ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号，以执行刷新操作。
具体来说，ECS标识信号的电平值可以包括第一值和第二值。其中，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
示例性地，如果ECS标识信号的电平值为逻辑1，那么可以确定ECS标识信号处于有效状态；否则，如果ECS标识信号的电平值为逻辑0，那么可以确定ECS标识信号处于无效状态。
还需要说明的是，在本公开实施例中，如果ECS标识信号处于有效状态，那么可以偷取下一时刻接收到的刷新命令信号，并根据该刷新命令信号产生ECS命令信号，同时对应被偷取的刷新命令信号会消失，以执行ECS操作；如果ECS标识信号处于无效状态，那么刷新命令信号不会被偷取，直接输出为内部刷新信号，以执行刷新操作。在图3中，内部刷新信号用REF_NEW表示。
也就是说，第一时序模块会在每间隔一个固定时间段之后产生一个有效ECS的标志信号ECS_Flag，并且停止时序的计数。该ECS_Flag信号会传输到命令控制模块，然后命令控制模块偷取下一个REFab信号或者Self_REF信号用来产生ECS命令信号，同时对应被偷取的刷新命令会消失，然后再产生一个复位信号给第一时序模块，使ECS_Flag信号复位为无效值，同时使第一时序模块重新开始计数。在ECS_Flag信号为无效值期间，刷新命令不会被偷取，而是直接得到REF_NEW信号，进行的刷新操作不会受影响。
这样，由于命令控制模块112是将刷新命令信号“偷取”，即在生成ECS命令信号时，对应的刷新命令信号就会消失，那么在执行ECS操作期间就不会执行刷新操作。这样，还可以降低在执行ECS期间存储器的功耗，并且还能够防止在执行ECS操作期间同时执行刷新操作引起的存储器故障。
进一步地，如图1所示，ECS控制模块11生成ECS命令信号之后，将ECS命令信号发送给命令生成模块12，命令生成模块12根据ECS命令信号生成内部命令信号，其中，内部命令信号即执行ECS操作所需的命令信号。
对于命令生成模块12，参见图4，其示出了本公开实施例提供的一种命令生成模块12的组成结构示意图。如图4所示，在一些实施例中，命令生成模块12包括内部命令生成模块122和第二时序模块121，其中：
内部命令生成模块122，配置为在接收到ECS命令信号后，按照预设时序条件依次生成激活信号、读命令信号、写命令信号和预充电信号；
第二时序模块121，配置为控制激活信号和读命令信号之间的时间间隔满足第一时序条件，控制读命令信号和写命令信号之间的时间间隔满足第二时序条件以及控制写命令信号和预充电信号之间的时间间隔满足第三时序条件；
其中，预设时序条件由第一时序条件、第二时序条件和第三时序条件组成。
需要说明的是，内部命令信号可以包括激活信号(Active，在图4中用ACT表示)、读命令信号(Read，在图4中用RD表示)、写命令信号(Write，在图4中用WR表示)和预充电信号(Precharge，在图4中用PRE表示)。具体来说，内部命令生成模块122在接收到ECS命令信号(在图4中用ECS_CMD表示)之后，按照预设时序条件依次生成ACT信号、RD信号、WR信号和PRE信号，其中，各内部命令信号之间的时序由第二时序模块121控制。
还需要说明的是，ACT信号和RD信号之间时间间隔用tRCD表示，RD信号和WR信号之间的时间间隔用WL表示，WR信号和PRE信号之间的时间间隔用tWR表示。示例性地，内部命令 生成模块在接收到ECS命令信号之后，首先生成ACT信号，在第二时序模块121的控制下，将ACT信号延迟tRCD后，得到RD信号，接着在第二时序模块121的控制下，将RD信号延时WL后，得到WR信号，继续在第二时序模块121的控制下，将WR信号延时tWR之后，得到PRE信号。
还需要说明的是，命令生成模块12的主要功能如下：ECS控制模块11在自动ECS操作模式和手动ECS操作模式下，分别对MPC信号，REFab信号和Self_REF信号进行控制产生ECS命令信号给命令产生模块12。将每次执行ECS操作所需的最小时间记为tECSc。在此时间段内，由于ECS要对计数指针(计数指针是指地址计数模块的时钟信号)控制的某存储组中的某存储块中的某行中的某列(也就是存储阵列中一个具体的存储位)进行内部读写和检错修改，因此需要自产生内部ACT命令信号、RD命令信号、WR命令信号和PRE命令信号，且命令信号之间的时序满足tRCD、WL、tWR，从而使得一次ECS操作在tECSc内完成，也就是说tRCD、WL、tWR三者之和要小于(或者等于)tECSc，保证执行ECS操作不会超时。其中，命令信号之间的时序控制具体可以由延迟链(Delay Line)来实现。
进一步地，ECS操作可以由存储控制模块控制存储阵列来实现。参见图5，其示出了本公开实施例提供的一种ECS电路的部分结构示意图。如图5所示，在一些实施例中，ECS电路10还包括存储控制模块15和存储阵列16，存储阵列16包括至少一个存储组，存储组包括至少一个存储块，存储块包括至少一行和至少一列，其中：
存储控制模块15，配置为接收内部命令信号，并根据内部命令信号对存储阵列执行ECS操作；以及，
存储控制模块15，还配置为在执行ECS操作时，若检测到错误信息，则生成错误信号，并将错误信号发送给错误追踪记录模块14。
需要说明的是，在图5中，对于ECS控制模块11和命令生成模块12的描述可以参照前述，这里不再赘述。对于存储阵列16，参见图6，其示出了本公开实施例提供的一种存储阵列16的组成结构示意图。在图6所示的示例中，存储阵列16(也称作Array、DRAM Array)包括4个存储组(Bank Growp，BG)：BG0、BG1、BG2和BG3，每个存储组包括4个存储块(Bank，BA)：BA0、BA1、BA2和BA3，以BG1中的BA3为例，存储块BA3包括6行(Row)：ROW0、ROW1、ROW2、ROW3、ROW4和ROW5，存储块BA3包括5列(Column，Col)：Col0、Col1、Col2、Col3和Col4。在图6中，一个圆圈表示一个存储位，例如，在BA3中，ROW0和Col0就可以定位出存储位Bit00。每次ECS操作均是针对存储阵列16中的一个存储位。
还需要说明的是，命令生成模块12生成内部命令信号发送给存储控制模块15(也称作DRAM控制模块、DRAM Control)，存储控制模块15根据内部命令信号对存储阵列16中的存储位执行ECS操作。
还需要说明的是，ECS操作可以包括：激活操作、读取操作、错误校正操作、写入操作和预充电操作。存储控制模块15首先接收ACT信号，将对应地址的字线激活，然后接收RD信号，从存储位中读取码字，这里，ECS电路还可以包括错误纠正电路，错误纠正电路执行错误检查与纠正(Error Check and Correct，ECC)算法，被读取的码字会被发送到错误纠正电路进行校验。其中，码字可以包括数据和奇偶校验，可以利用错误校正码从数据生成奇偶校验。当执行错误校正操作时，错误校正电路可以检查码字的错误，并且将码字的错误校正，生成被校正的码字。在接收到WR信号时，执行写入操作，将被校正的码字写入存储位。另外，如果没有检查到码字错误，则无需执行写入操作，最后在接收到PRE信号时，进行预充电。
还需要说明的是，在执行ECS操作期间，如果检测到存在错误信息的码字，就生成错误信号，发送给错误追踪记录模块，以使错误追踪记录模块对错误信息进行记录和追踪，由于错误信息是从存储阵列中读取出来数据再通过错误检查与纠正(ECC)算法检测出来的错误，因此错误信号也称为ECC错误信号，在图5中用ECC_Error表示。
这样，本公开实施例根据ECS命令信号生成内部命令信号，根据内部命令信号执行ECS操作，从而能够实现对存储阵列的错误检查与清除。
还需要说明的是，这里的存储阵列16可以是指DRAM中的一个存储颗粒(Die)，对每一个Die，均按照相同的方式执行ECS操作，实现对DRAM完整的错误检查与清除。
在存储控制模块根据内部命令信号对存储阵列执行ECS操作的同时，地址计数模块还根据内 部命令信号进行地址计数，以生成计数结束信号。这里，地址计数模块根据PRE信号进行计数，PRE信号作为地址计数模块的时钟信号。地址计数模块可以分别对存储阵列的列、行、存储块和存储组进行计数，并在计数完成时，生成计数结束信号发送给错误追踪记录模块。其中，计数结束信号包括标志一行中的每个存储位计数完成的列结束信号、标志一个存储块中的每行计数完成的行结束信号、标志一个存储组中的每个存储块计数完成的存储块结束信号、标志存储阵列中的每个存储组计数完成的存储组结束信号和标志着整个存储阵列中的所有存储位计数完成的ECS结束信号。另外，地址计算模块还会将列地址信息、存储块信息、存储组信息等地址信息发送给错误追踪记录模块，以使得错误追踪记录模块将需要的地址信息进行保存。
对于地址计数模块而言，参见图7，其示出了本公开实施例提供的一种地址计数模块13的组成结构示意图。如图7所示，在一些实施例中，地址计数模块13包括列计数模块131、行计数模块132和阵列计数模块133，其中：
列计数模块131，配置为接收预充电信号，根据预充电信号对目标行进行列计数；在目标行的列计数完成时，生成列输出信号和列结束信号；
行计数模块132，配置为接收预充电信号和列输出信号，根据预充电信号和列输出信号对目标存储块进行行计数；在目标存储块的行计数完成时，生成行输出信号和行结束信号；
阵列计数模块133，配置为接收预充电信号和行输出信号，根据预充电信号和行输出信号对目标存储组进行存储块计数；在目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；以及，根据预充电信号和存储块输出信号对存储阵列进行存储组计数；在存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
需要说明的是，在图7中，PRE表示预充电信号，Col_Wrap表示列输出信号，COL_END表示列结束信号，Row_Wrap表示行输出信号，ROW表示行地址信息，BA表示存储块地址信息，BG表示存储组地址信息，存储块地址信息和存储组地址信息在图7中共同记作BG/BA，ECS_END表示ECS结束信号，这些地址信息需要被发送给错误追踪记录模块14，另外，行结束信号(也称作ROW_END)表示一个存储块中的行计数完成，存储块结束信号(也称作BA_END)表示一个存储组中的存储块计数完成，存储组结束信号(也称作BG_END)表示存储阵列中的所有存储组计数完成。
还需要说明的是，仍以图6示出的存储阵列16为例，结合图7对地址计数模块13的工作过程进行描述。假设存储阵列16中的每一个BA的组成均与BG1中的BA3相同。在每一个BG中，将每一个存储位记作Bitxy，其中，x表示存储位在BA中的所在行，y表示存储位在BG中的所在列，例如：Bit32表示由BA中的ROW3和Col2定位出的存储位，当前正在被执行ECS操作的存储位被记作目标存储位，目标存储位所属的行、存储块、存储组分别记作目标行、目标存储块和目标存储组。例如，正在执行针对BG1中的BA2中的Bit11的ECS操作，则目标行为BG1中的BA2中的ROW1，目标存储块为BG1中的BA2，目标存储组为BG1。这里，每一个计数模块均以PRE信号作为时钟。
列计数模块131可以按顺序对存储阵列16中每一行所包括的存储位进行计数。这样，在对存储阵列16的一次完整的ECS过程中，首先对BG0中的BA0中的第一行ROW0中的每个存储位按顺序执行ECS操作，当对Bit00执行ECS操作时，相应的PRE信号会发送给列计数模块131的时钟端(图7中用CNT_CLK表示各计数模块的时钟端)，每接收到一个PRE信号，ROW0的列计数值会加1。可以理解，列计数值表示的是目标行中已经完成ECS操作的存储位的数量。由于ROW0包括5个存储位，那么在ROW0的列计数值为5时，说明ROW0的列计数完成。这时候，列计数模块131会生成一个Col_Wrap信号和一个COL_END信号，其中，Col_Wrap信号被发送给行计数模块132，COL_END信号被发送给错误追踪记录模块。在完成ROW0的列计数后，列计数模块131会将计数值清零，然后继续对ROW1进行列计数，并依次对存储阵列16的每一行都按这个流程进行计数，直到完成对存储阵列16的每一行的列计数。也就是说，列计数模块131，还配置为在生成列输出信号和列结束信号之后，继续执行下一目标行的列计数，直至完成存储阵列中的每一行的列计数。
行计数模块132根据PRE信号和Col_Wrap信号进行计数。仍以BG0中的BA0为例，具体来说，列计数模块131在完成ROW0的计数后，就会生成一个Col_Wrap信号发送给行计数模块132，行计数模块132计数的目标存储块的行计数值会加1。可以理解，行计数值表示的目标存储 块中已经完成ECS操作的行的数量。列计数模块131在完成ROW1的计数后，会再发送一个Col_Wrap信号给行计数模块132，目标存储块的行计数值继续加1，…，由于BA0包括6行，那么当目标存储块的行计数值为6时，说明BA0的行计数完成。这时候，行计数模块132会生成Row_Wrap信号和行地址信息(ROW)，其中，Row_Wrap信号被发送给存储块计数模块1331，行地址信息会被发送给错误追踪记录模块14。另外，在计数过程中，行计数模块132在目标存储块中的行计数结束之后，还会生成行结束信号(ROW_END)，以表示该目标存储块中的行计数完成。在完成BA0的行计数后，行计数模块132会将计数值清零，然后继续对BA1进行行计数，并依次对存储阵列16的每一个BA都按这个流程进行计数，直至完成对存储阵列16中的每一个BA的计数。也就是说，行计数模块132，还配置为在生成行输出信号和行结束信号之后，继续执行下一目标存储块的行计数，直至完成存储阵列中的每一存储块的行计数。
阵列计数模块133不仅对存储块进行计数，还对存储组进行计数。对于阵列计数模块133，参见图8，其示出了本公开实施例提供的另一种地址计数模块13的组成结构示意图。如图8所示，在一些实施例中，阵列计数模块包括存储块计数模块1331和存储组计数模块1332，其中：
存储块计数模块1331，配置为接收预充电信号和行输出信号，根据预充电信号和行输出信号对目标存储组进行存储块计数；在目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；
存储组计数模块1332，配置为接收预充电信号和存储块输出信号，根据预充电信号和存储块输出信号对存储阵列进行存储组计数；在存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
需要说明的是，存储块计数模块1331根据PRE信号和Row_Wrap信号进行计数。仍以BG0为例，行计数模块132在完成BA0的计数后，会生成一个Row_Wrap信号发送给存储块计数模块1331，存储块计数模块1331计数的目标存储组的存储块计数值会加1。可以理解，存储块计数值表示的目标存储组中已经完成ECS操作的存储块的数量，行计数模块132在完成BA1的计数后，会再生成一个Row_Wrap信号发送给存储块计数模块1331，目标存储组的存储块计数值继续加1，…，由于BG0包括4个BA，那么当目标存储组的存储块计数值为4时，说明BG0的存储块计数完成。这时候，存储块计数模块1331会生成BA_Wrap信号和存储块地址信息(BA)，其中，BA_Wrap信号被发送给存储组计数模块1332，存储块地址信息会被发送给错误追踪记录模块14。另外，在计数过程中，存储块计数模块1331在目标存储组的存储块计数结束之后，还会生成存储块结束信号(BA_END)，以表示该目标存储组中的存储块计数完成。在完成BG0的存储块计数后，存储块计数模块1331会将计数值清零，然后继续对BG1进行行计数，并依次对存储阵列16的每一个BG都按这个流程进行计数，直至完成对存储阵列16中的每一个BG的计数。也就是说，在阵列计数模块133中，存储块计数模块1331，还配置为在生成存储块输出信号和存储块结束信号之后，继续执行下一目标存储组的存储块计数，直至完成对存储阵列中的每一存储组的存储块计数。
存储组计数模块1332根据PRE信号和BA_Wrap信号进行计数。存储块计数模块1331在完成BG0的计数后，会生成一个BA_Wrap信号发送给存储组计数模块1332，存储组计数值会加1。可以理解，存储组计数值表示的是存储阵列16中已经完成ECS操作的存储组的数量，存储块计数模块1331在完成BG1的计数后，会再生成一个BA_Wrap信号发送给存储组计数模块1332，存储组计数值继续加1，…，由于存储阵列16包括4个BG，那么当存储组计数值为4时，说明该存储阵列16的存储组计数完成，即存储阵列16中的每一个存储位均完成了ECS操作。这时候，存储组计数模块1332会生成存储组地址信息(BG)和ECS_END信号，其中，存储组地址信息和ECS_END信号均会被发送给错误追踪记录模块14。另外，在计数过程中，存储组计数模块1332在存储阵列中的存储组计数结束之后，还会生成存储组结束信号(BG_END)以表示该存储阵列中的存储组计数完成。在完成存储组计数后，存储组计数模块1332会将计数值清零，直到下一次对存储阵列16进行ECS操作时，继续按照上述流程进行计数。
可以理解的是，存储块计数模块1331配置为对存储组进行存储块计数，存储组计数模块1332配置为对存储阵列中的存储组进行计数，存储块计数模块1331和存储组计数模块1332可以集成在阵列计数模块133这一个模块中，以实现相关功能。
还需要说明的是，在本公开实施例中，生成的每一个输出信号和计数信号(或者ECS命令信 号等)都可以是一个高电平脉冲。也就是说，在满足一定的条件时，这些信号处于有效的状态，从而能够使得对应的模块可以根据这些信号生成其它信号或者执行计数、读或者写等操作。
也就是说，地址计数模块(也称作地址计数器)主要功能如下：为了对DRAM进行完整的错误检查与清除，要对所有存储组中的所有存储块中的行和列进行访问。对于每次ECS操作，地址计数模块在每个内部PRE命令信号后增加列地址的计数(即目标行的列计数)，当目标行的列地址计数完成后，行地址的计数(即目标存储块的行计数)开始增加，直到一个存储块中的每一行的码字被访问完为止，接着存储块的计数(即目标存储组的存储块计数)开始增加，重复之前存储块访问码字的过程，当一个存储组的所有存储块计数完成，存储组的计数(存储组计数)开始增加直到DRAM所有的存储块被访问完为止，一次完整的错误检查与清除操作就完成了。
这样，以执行ECS操作时的PRE命令信号作为地址计数模块的时钟，分别对行、存储块和存储组进行计数，不需要额外的时钟，而且能够准确判断行、存储块和存储组的ECS操作是否完成。
这样，在本公开实施例中，命令生成模块产生的内部命令信号PRE作为地址计数模块的时钟信号，每执行一次ECS操作，列计数模块(也称作列地址计数器、COL_CNT)的计数开始增加，当一个行上的列地址计数完成，输出Col_Wrap信号作为行计数模块(也称作行地址计数器、ROW_CNT)的输入，行计数模块的计数开始增加，当一个存储块中行地址计数计数完成，输出Row_Wrap作为阵列计数模块(也称作BG/BA计数器、BA/BG_CNT)的输入，当BG/BA计数完输出ECS_END信号，标志着一次完整的错误检查与清除完成。输出COL_END信号标志着一个行计数完成，应用于错误计数器的行模式。
地址计数模块将计数结束信号和地址信息发送给错误追踪记录模块，错误追踪记录模块根据计数结束信号、地址信息和错误信号生成错误追踪信号，以记录ECS操作的错误信息。其中，计数结束信号主要包括列结束信号和ECS结束信号，地址信息主要包括行地址信息、存储块地址信息和存储组地址信息。
对于错误追踪记录模块而言，在图5的基础上，参见图9，其示出了本公开实施例提供的一种ECS电路10的具体结构示意图。如图9所示，错误追踪记录模块14由第一错误追踪记录模块141和第二错误追踪记录模块142组成。
对于第一错误追踪记录模块141而言，在一些实施例中，第一错误追踪记录模块141，配置为接收计数模式信号，以及在计数模式信号为第一值的情况下，确定第一错误追踪记录模块141的计数模式为码字计数模式；或者，在计数模式信号为第二值的情况下，确定第一错误追踪记录模块141的计数模式为行计数模式。
需要说明的是，第一错误追踪记录模块141(也称作ERROR_COUNT，EC)有两种工作模式，分别为码字计数模式和行计数模式，两种工作模式可以根据计数模式信号进行切换，其中，计数模式信号可以为MR14 OP[5](在图9中用MRS表示MR14 OP[5])。当计数模式信号的取值为第一值时，执行码字计数模式，用于计数存储阵列的码字错误数，当计数模式信号的取值为第二值时，执行行计数模式，用于计数存储阵列中存在至少有一个码字错误的行数。
在这里，第一值可以为指示高电平的逻辑1，第二值可以为指示低电平的逻辑0；或者，第一值可以为指示低电平的逻辑0，第二值可以为指示高电平的逻辑1，对此并不作任何限定。
这样，由计数模式信号确定第一错误追踪记录模块的工作方式，不仅可以对存储阵列的存在错误信息的码字进行计数，还可以对存储阵列中存在至少一个错误信息的行进行计数，增加了记录错误信息的灵活性，在实际应用中，可以按需求进行设置。
进一步地，在计数模式为码字计数模式的情况下，如图9所示，在一些实施例中，第一错误追踪记录模块141，配置为接收错误信号，根据错误信号进行码字计数，并在接收到ECS结束信号时，确定第一计数值；以及将第一计数值与第一阈值进行比较，在第一计数值大于或者等于第一阈值的情况下，将第一计数值进行保存；其中，第一计数值用于表征存储阵列中存在错误信息的码字数量。
需要说明的是，在本公开实施例中，错误信息主要是指码字错误信息，因此错误信息也可以称为码字错误。在码字计数模式下，第一错误追踪记录模块需要对存储阵列中存在错误信息的码字进行计数。其中，每当存储控制模块在存储阵列中检测到一个码字错误，就生成错误信号(在图9中用ECC_Error表示)。其中，检测到码字错误时，ECC_Error可以为一个高电平脉冲，从而第一错误追踪记录模块可以根据ECC_Error对存储阵列中的存在错误信息的码字进行计数，当 接收到ECS结束信号(在图9中用ECS_END表示)时，说明存储阵列已经完成了一次完整的ECS操作，这时候第一错误追踪记录模块就停止计数，得到第一计数值。可以理解，第一计数值表示的就是存储阵列中存在错误信息的码字数量。
如图9所示，将第一计数值进行保存的位置可以为模式寄存器20(MR20)。另外，对于码字计数模式，DRAM可以忽略小于第一阈值的码字错误数量，即在第一计数值小于第一阈值时，不会将第一计数值在MR20中进行保存，只有在第一计数值大于或者等于第一阈值时，才会将第一计数值进行保存。
在本公开实施例中，第一阈值可以由错误计数阈值和存储阵列的存储密度来确定，其中，错误计数阈值(Error Threshold Count，简称ETC)可以根据模式寄存器信号MR15 OP[2:0](在图9中，MRS还可以表示MR15 OP[2:0])进行设置，例如，在DDR5中，当OP[2:0]为000B时，ETC为4；当OP[2:0]为001B，ETC为16；当OP[2:0]为010B时，ETC为64；当OP[2:0]为011B时，ETC为256；当OP[2:0]为100B，时，ETC为1024；当OP[2:0]为101B时，ETC为4096。其中，ETC的默认设置是256个每内存单元，这里，1个内存单元可以表示1Gb。
假设存储阵列的存储密度为16Gb，ETC为4，那么当每Gb的码字错误数量小于4时就会被忽略，对于存储阵列整体而言，当码字错误数量小于4×16＝64时，就可以忽略不计。也就是说，在这种示例下，第一阈值为64，如果第一计数值大于或者等于64，第一计数值就被加载到MR20中进行保存，否则不会进行保存。然后，第一计数值会被重置，在执行下一次完整的ECS操作时，重新进行计数。
这样，在码字计数模式下，第一错误追踪记录模块可以对存储阵列中存在错误信息的码字进行计数，得到第一计数值，并根据第一阈值将第一计数值在模式寄存器中进行保存，保证只在错误信息数量过大的情况下，才将第一计数值进行保存以供后续所需，节省了功耗和存储空间。
进一步地，在计数模式为行计数模式的情况下，如图9所示，在一些实施例中，第一错误追踪记录模块，配置为接收错误信号和列结束信号，根据错误信号和列结束信号进行错误行计数，并在接收到ECS结束信号时，确定第二计数值；以及将第二计数值与第二阈值进行比较，在第二计数值大于第二阈值的情况下，将第二计数值进行保存；其中，第二计数值用于表征存储阵列中存在至少一个错误信息的行数量。
需要说明的是，在行计数模式下，第一错误追踪记录模块需要对存储阵列中存在至少一个错误信息的行进行计数，也就是说第二计数值代表存在至少一个码字错误的行数量。
在一种具体的实现方式中，为了实现对存在至少一个错误信息的行的计数，第一错误追踪记录模块需要接收ECC_Error和列结束信号(Col_END)。示例性地，当收到表示错误信息的ECC_Error时，第一错误追踪记录模块141会根据ECC_Error进行计数，得到行错误计数值，当接收到Col_END时，说明当前行中的存储位都已经完成了一次完整的ECS操作，这时候如果当前行的行错误计数值大于0，说明当前行存在至少一个码字错误，那么第二计数值就加1，否则，第二计数值不加1，然后将行错误计数值清零，根据ECC_Error重新进行计数，在收到下一个Col_END时，继续根据行错误计数值判断是否需要对第二计数值加1，直至接收到ECS_END，说明存储阵列已经完成了一次完整的ECS操作，这时候第一错误追踪记录模块就停止计数，得到第二计数值。
在其它实现方式中，ECC_Error还可以是在检测到存在码字错误的行时生成的脉冲信号，这时候，第一错误追踪记录模块直接对ECC_Error进行计数，得到的就是代表存在码字错误的行数的第二计数值。或者，第一错误追踪模块还可以与选择模块连接，选择模块根据计数模式信号选择码字计数模式或者行计数模式，在码字计数模式下，选择模块根据ECC_Error生成第一脉冲信号，第一错误追踪模块对第一脉冲信号进行计数，得到第一计数值；在行计数模块下，选择模块根据ECC_Error生成第二脉冲信号，第一错误追踪模块对第二脉冲信号进行计数，得到第二计数值。
将第二计数值进行保存时，保存的位置可以为模式寄存器20(在图9中用MR20表示)。另外，对于行计数模式，DRAM可以忽略小于第二阈值的行错误数量，即在第二计数值小于第二阈值时，不会将第二计数值在MR20中进行保存，只有在第二计数值大于或者等第二阈值时，才会将第二计数值进行保存。
在本公开实施例中，假设第二阈值为4，如果第二计数值大于或者等于4，第二计数值就被加 载到MR20中进行保存，否则不会进行保存。然后，第二计数值会被重置，在执行下一次完成的ECS操作时，重新进行计数。另外，第二阈值可以为前述的ETC，第二阈值的确定方式可以与第一阈值的确定方式相同。
这样，在行计数模式下，第一错误追踪记录模块可以对存储阵列中存在错误信息的行进行计数，得到第二计数值，并根据第二阈值将第二计数值在模式寄存器中进行保存，保证只在存在错误信息的行的数量过大的情况下，才将第二计数值进行保存以供后续所需，节省了功耗和存储空间。
对于第二错误追踪记录模块142而言，如图9所示，在一些实施例中，第二错误追踪记录模块142，配置为接收错误信号，并根据错误信号和列结束信号对目标行的错误信息进行计数，在确定目标行的第三计数值后，将第三计数值与第一寄存器模块中存储的目标计数值进行比较，若第三计数值大于目标计数值，则将第一寄存器模块中存储的目标计数值清除，并将第三计数值保存为第一寄存器模块中的目标计数值；以及继续根据错误信号和列结束信号对下一目标行进行错误计数，直至接收到ECS结束信号后，确定第一寄存器模块中存储的目标计数值；其中，第三计数值用于表征目标行中存在错误信息的码字数量。
需要说明的是，第二错误追踪记录模块142(也称作每行错误计数器，ERROR PER ROW CNT，EPRC)可以对存储阵列中每一行的码字错误进行计数，并将码字错误数量最大的行的码字错误数量以及该行的地址信息进行保存。其中，第二错误追踪记录模块142可以根据ECC_Error和Col_END对每一行的错误信息进行计数。例如，对存储阵列中的第i行进行错误信息计数，假设存储阵列总共包括N行，N为大于0的整数，则i为大于0且小于或者等于N的整数，在收到Col_END信号时，说明第i行的存储位均完成了ECS操作，这时候就可以结束对第i行的错误信息计数，将得到的计数值称作第三计数值，可以理解，第三计数值表示的就是第i行的错误信息数量(即错误码字数量)。
还需要说明的是，从对第一行进行错误计数开始，如果第一行存在至少一个错误信息，即第一行的第三计数值大于0，就将第一行对应的第三计数值作为目标计数值保存在第一寄存器模块中，其中第一寄存器模块可以为模式寄存器19(在图9中用MR[19]表示)；然后继续对第二行进行错误计数，并将得到的第三计数值与寄存器中已经保存的目标计数值进行比较，如果第二行对应的第三计数值大于目标计数值，则将第一寄存器模块中保存的目标计数值清除，第二行对应的第三计数值作为新的目标计数值保存进第一寄存器模块中……这样依次执行，由于每当出现了更大的第三计数值，就会替换第一寄存器模块中的目标计数值，这样，第一寄存器模块中保存的目标计数值始终是当前已经计数过的行中错误信息数量最多的行对应的第三计数值。这样，在收到ECS结束信号时，第一寄存器模块中保存的目标计数值就是错误信息数量最多的行的第三计数值。
可以理解的是，如果第1行至第i-1行中均未出现错误信息，直到第i行才出现错误信息，则第i行没有可以用于比较的目标计数值，第i行对应的第三计数值就直接作为目标计数值保存进第一寄存器模块中。或者，第二错误追踪记录模块，配置为接收错误信号，根据错误信号和列结束信号对第一行的错误信息进行计数，在确定第一行的第三计数值后，将第一行的第三计数值保存为第一寄存器模块中的目标计数值，在第一行计数结束后，按照前述方式对目标行进行计数，这时候，目标行表示除第一行之外的其它行。在这种情况下，即使第一行的第三计数值为0也可以先保存在第一寄存器模块中，对于第二行而言，对应的第三计数值就与0进行比较，直至确定出最终的目标计数值。
还需要说明的是，在每一次将第三计数值作为目标计数值保存进行第一寄存器模块时，第二错误追踪记录模块，还配置为在将目标计数值保存进第一寄存器模块时，将目标计数值对应的地址信息保存在第二寄存器模块中；其中，地址信息包括目标计数值对应的行地址信息、存储块地址信息和存储组地址信息。
其中，第二寄存器模块可以包括模式寄存器16、模式寄存器17和模式寄存器18，在图9中用MR[16:18]表示。可以理解，每次用更大的第三计数值替换第一寄存器模块中的目标计数值时，也会用相应的地址信息替换第二寄存器模块中的地址信息。这样，在接收到ECS结束信号时，第二寄存器模块中保存的是错误信息数量最多的行的行地址信息、存储块地址信息和存储组地址信息。
进一步地，在一些实施例中，第二错误追踪记录模块，还配置为在接收到ECS结束信号后， 将第一寄存器模块中当前存储的目标计数值与第三阈值进行比较，若目标计数值大于或者等于第三阈值，则保留第一寄存器模块中存储的目标计数值和第二寄存器模块中存储的地址信息，若目标计数值小于第三阈值，则将第一寄存器模块中存储的目标计数值和第二寄存器模块中存储的地址信息清除。
还需要说明的是，本公开实施例还可以是只在最终的目标计数值大于第三阈值时，才将该目标计数值和对应的地址信息进行保存。其中，第三阈值又称作行错误计数阈值(Row Error threshold Count，RETC)，在DDR中，RETC的值可以固定为4。以RETC的值等于4为例，如果最终的目标计数值大于4，就保留第一寄存器模块中的目标计数值，并保留第二寄存器模块中的地址信息，否则，就将当前的目标计数值的地址信息清除。
示例性地，在图6中，最终的目标计数值的地址信息为BG1-BA2-ROW1，则表示该目标行为存储阵列中的存储组BG1中的存储块BA2中的第二行ROW1。其中，行地址信息、存储块地址信息和存储组地址信息是在地址计数模块进行计数的过程中发送给错误追踪记录模块的，从而错误追踪记录模块能够将目标计数值对应的地址信息准确保存。
这样，第二错误追踪记录模块可以根据第三阈值将错误信息数量最大的行的信息在模式寄存器中进行保存，保证只在错误信息数量过大的情况下，才将错误行的信息进行保存以供后续所需，节省了功耗和存储空间。
还需要说明的是，在图9中，目标计数值用REC[5:0]表示，保存在MR19中，目标计数值对应的地址信息可以用MAX_ADD表示，包括行地址信息、存储块地址信息和存储组地址信息，分别保存在MR[16:18]中。其中，行计数模块、阵列计数模块输出的ROW、BG/BA用于记录有最大错误计数的行地址的具体信息，以便保存在寄存器中。也就是说，在本公开实施例中，错误追踪信号主要是指第一错误追踪记录模块保存的第一计数值或者第二计数值，以及第二错误追踪记录模块保存的最终的目标计数值和对应的地址信息，这些错误追踪信号能够记录存储阵列中的错误数等信息。另外，在将第一计数值、第二计数值和目标计数值进行保存时，可以采用独热编码的方式对第一计数值、第二计数值和目标计数值进行编码后保存。
简言之，对于错误追踪记录模块，其包括两种错误计数器：第一错误追踪记录模块(EC)和第二错误追踪记录模块(EPRC)。EC模块有两种模式，需要根据MR14 OP[5]进行切换，当OP[5]＝0时为行计数模式，在行计数模式下，ECC_Error和COL_END用于用来计数有多少行至少有一个错误。当OP[5]＝1时为码字计数模式，在码字计数模式下，用ECC_Error信号计数有多少码字错误数。等所有ECS完成一次时，EC的结果将根据ETC加载到MR20中，EC在值被转移到模式寄存器后被重置。
EPRC模块使用ECC_Error、BG/BA和ROW来记录哪一行有最大的错误信息数量，同时记录有最大错误信息数量的行的地址信息MAX_ADD。等所有ECS完成一次时，该地址信息加载到MR[16:18]，该行的错误计数将会根据RETC加载到MR19。这里，EC和EPRC记录的数据不是直接加载到寄存器，而是等完成一次完整的ECS操作，根据ETC和RETC加载到对应的寄存器中。
还需要说明的是，对于本公开实施例所涉及的执行计数功能的模块，可以通过同步计数器来实现，也可以通过异步计数器来实现，这里不作具体限定。
本公开实施例提供了一种ECS电路，基于模式控制信号来生成ECS命令信号，以执行ECS操作，从而能够实现对存储器进行完整的错误检查与清除，而且在执行ECS操作完成之后，还可以根据错误信号和计数结束信号来生成错误追踪信号，用以记录ECS操作的错误信息，进而能够快速定位存储器中存在错误信息的位置并进行修复，最终提升存储器的性能。
本公开的另一实施例中，参见图10，其示出了本公开实施例提供的一种ECS方法的流程示意图。如图10所示，该方法可以包括：
S1001、通过ECS控制模块接收模式控制信号，并根据模式控制信号生成ECS命令信号。
S1002、通过命令生成模块接收ECS命令信号，根据ECS命令信号生成内部命令信号，内部命令信号用于执行对应的ECS操作。
S1003、通过地址计数模块接收内部命令信号，根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号。
S1004、通过错误追踪记录模块接收计数结束信号和错误信号，根据计数结束信号和错误信号生成错误追踪信号，错误追踪信号用于记录ECS操作的错误信息。
在一些实施例中，模式控制信号包括多用途命令MPC信号或刷新命令信号，根据模式控制信号生成ECS命令信号，可以包括：
在ECS操作为手动ECS操作模式的情况下，根据MPC信号生成ECS命令信号，或者；
在ECS操作为自动ECS操作模式的情况下，根据刷新命令信号生成ECS命令信号。
需要说明的是，在不同的ECS操作模式下，可以基于不同的命令信号产生ECS操作，其中，在自动ECS操作模式下，可以基于刷新信号(REFab)来执行自动ECS操作，或者基于自刷新信号(Self_REF)来执行自动ECS操作，在手动ECS操作模式下，可以基于特定的MPC信号执行ECS操作，或者结合第一模式寄存器信号决定在自刷新时是否执行ECS操作。
在一些实施例中，根据模式控制信号生成ECS命令信号，可以包括：
通过第一时序模块生成ECS标识信号；
通过命令控制模块接收ECS标识信号，以及在ECS标识信号处于有效状态时，获取刷新命令信号，并根据刷新命令信号产生ECS命令信号。
在一些实施例中，通过第一时序模块生成ECS标识信号，可以包括：
通过第一时序模块接收第一时钟信号，根据第一时钟信号进行计数，生成ECS标识信号，并将ECS标识信号发送给命令控制模块；其中，在计数值满足预设条件时，ECS标识信号处于有效状态。
在一些实施例中，该方法还可以包括：
在ECS标识信号处于有效状态时，第一时序模块停止计数；
在根据刷新命令信号产生ECS命令信号之后，命令控制模块生成复位信号，将复位信号发送给第一时序模块，以使第一时序模块重新开始计数并且控制ECS标识信号处于无效状态。
在一些实施例中，该方法还可以包括：
在ECS标识信号处于无效状态时，通过命令控制模块将所接收到的刷新命令信号输出为内部刷新信号，以执行刷新操作。
在一些实施例中，根据ECS命令信号生成内部命令信号，可以包括：
通过内部命令生成模块接收ECS命令信号，并在接收到所述ECS命令信号后，按照预设时序条件依次生成激活信号、读命令信号、写命令信号和预充电信号；以及通过第二时序模块，控制激活信号和读命令信号之间的时间间隔满足第一时序条件，控制读命令信号和写命令信号之间的时间间隔满足第二时序条件以及控制写命令信号和预充电信号之间的时间间隔满足第三时序条件；
其中，预设时序条件由第一时序条件、第二时序条件和第三时序条件组成。
在一些实施例中，该方法还可以包括：
通过存储控制模块接收内部命令信号，并根据内部命令信号对存储阵列执行ECS操作；以及，在执行ECS操作时，若检测到错误信息，则生成错误信号，并将错误信号发送给错误追踪记录模块。
在一些实施例中，根据内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号，可以包括：
通过列计数模块接收预充电信号，根据预充电信号对目标行进行列计数；在目标行的列计数完成时，生成列输出信号和列结束信号；
通过行计数模块接收预充电信号和列输出信号，根据预充电信号和列输出信号对目标存储块进行行计数；在目标存储块的行计数完成时，生成行输出信号和行结束信号；
通过阵列计数模块接收预充电信号和行输出信号，根据预充电信号和行输出信号对目标存储组进行存储块计数；在目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；以及，根据预充电信号和存储块输出信号对存储阵列进行存储组计数；在存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
在一些实施例中，通过阵列计数模块接收预充电信号和行输出信号，根据预充电信号和行输出信号对目标存储组进行存储块计数；在目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；以及，根据预充电信号和存储块输出信号对存储阵列进行存储组计数；在存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号，可以包括：
通过存储块计数模块接收预充电信号和行输出信号，根据预充电信号和行输出信号对目标存储组进行存储块计数；在目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；
通过存储组计数模块接收预充电信号和存储块输出信号，根据预充电信号和存储块输出信号对存储阵列进行存储组计数；在存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
在一些实施例中，该方法还可以包括：
在生成列输出信号和列结束信号之后，列计数模块继续执行下一目标行的列计数，直至完成存储阵列中的每一行的列计数；
在生成行输出信号和行结束信号之后，行计数模块继续执行下一目标存储块的行计数，直至完成存储阵列中的每一存储块的行计数；
在生成存储块输出信号和存储块结束信号之后，存储块计数模块继续执行下一目标存储组的存储块计数，直至完成对存储阵列中的每一存储组的存储块计数。
在一些实施例中，该方法还可以包括：
通过第一错误追踪记录模块接收计数模式信号，以及在计数模式信号为第一值的情况下，确定第一错误追踪记录模块的计数模式为码字计数模式；或者，在计数模式信号为第二值的情况下，确定第一错误追踪记录模块的计数模式为行计数模式。
在一些实施例中，在码字计数模式下，根据计数结束信号和错误信号生成错误追踪信号，可以包括：
通过第一错误追踪记录模块接收错误信号，根据错误信号进行码字计数，并在接收到ECS结束信号时，确定第一计数值；以及将第一计数值与第一阈值进行比较，在第一计数值大于或者等于所述第一阈值的情况下，将第一计数值进行保存；其中，第一计数值用于表征存储阵列中存在错误信息的码字数量。
在一些实施例中，在行计数模式下，根据计数结束信号和错误信号生成错误追踪信号，可以包括：
通过第一错误追踪记录模块接收错误信号和所述列结束信号，根据错误信号和列结束信号进行错误行计数，并在接收到ECS结束信号时，确定第二计数值；以及将第二计数值与第二阈值进行比较，在第二计数值大于第二阈值的情况下，将第二计数值进行保存；其中，第二计数值用于表征存储阵列中存在至少一个错误信息的行数量。
在一些实施例中，根据计数结束信号和错误信号生成错误追踪信号，可以包括：
通过第二错误追踪记录模块接收错误信号，并根据错误信号和列结束信号对目标行的错误信息进行计数，在确定目标行的第三计数值后，将第三计数值与第一寄存器模块中存储的目标计数值进行比较，若第三计数值大于目标计数值，则将第一寄存器模块中存储的目标计数值清除，并将第三计数值保存为第一寄存器模块中的目标计数值；以及继续根据错误信号和列结束信号对下一目标行进行错误计数，直至接收到ECS结束信号后，确定第一寄存器模块中存储的目标计数值；其中，第三计数值用于表征目标行中存在错误信息的码字数量。
在一些实施例中，该方法还可以包括：
在将目标计数值保存进第一寄存器模块时，将目标计数值对应的地址信息保存在第二寄存器模块中；其中，地址信息包括目标计数值对应行的行地址信息、存储块地址信息和存储组地址信息。
在一些实施例中，该方法还可以包括：
在接收到ECS结束信号后，将第一寄存器模块中当前存储的目标计数值与第三阈值进行比较，若目标计数值大于或者等于第三阈值，则保留第一寄存器模块中存储的目标计数值和第二寄存器模块中存储的地址信息，若目标计数值小于第三阈值，则将第一寄存器模块中存储的目标计数值和第二寄存器模块中存储的地址信息清除。
需要说明的是，本公开实施例提供的ECS方法应用于前述实施例提供的ECS电路，对于本公开实施例未披露的细节，请参照前述实施例的描述而理解。
本公开实施例提供的一种ECS方法，基于模式控制信号来生成ECS命令信号，以执行ECS操作，从而能够实现对存储器进行完整的错误检查与清除，而且在执行ECS操作完成之后，还可 以根据错误信号和计数结束信号来生成错误追踪信号，用以记录ECS操作的错误信息，进而能够快速定位存储器中存在错误信息的位置并进行修复，最终提升存储器的性能。
本公开的再一实施例中，参见图11，其示出了本公开实施例提供的一种存储器20的组成结构示意图。如图11所示，该存储器20可以包括前述实施例任一项所述的ECS电路10。
在一些实施例中，该存储器20可以包括DRAM。
需要说明的是，本公开实施例是对DDR5新的操作模式：错误检查与清除模式的总体框架设计，实现了在手动和自动ECS操作模式下，通过MPC，REFab，SREF产生ECS命令信号，然后实现了内部自产生命令进行对应地址的错误检查和清除操作。同时将ECS操作发现的错误记录在EC和EPRC中，且在每次ECS命令结束之后将地址计数模块的计数递增。命令生成模块间的时序控制和ECS设计中的时序控制模块需要保证一个ECS操作可以在tECSc内完成，且至少24小时内对DRAM进行一次完整的错误检查与清除。
在本公开实施例中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5、DDR6等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5、LPDDR6等内存规格，这里不作任何限定。
在本公开实施例中，对于该存储器20，由于其包括前述实施例所述的ECS电路10，从而可以实现对存储器的ECS操作，进而提升存储器的性能。
以上所述，仅为本公开的示例实施例，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或电路实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例基于模式控制信号来生成ECS命令信号，以执行ECS操作，从而能够实现对存储器进行完整的错误检查与清除，而且在执行ECS操作完成之后，还可以根据错误信号和计数结束信号来生成错误追踪信号，用以记录ECS操作的错误信息，进而能够快速定位存储器中存在错误信息的位置并进行修复，最终提升存储器的性能。

Claims (19)

  1. 一种错误检查与清除ECS电路，包括ECS控制模块、命令生成模块、地址计数模块和错误追踪记录模块，其中：
    所述ECS控制模块，配置为接收模式控制信号，根据所述模式控制信号生成ECS命令信号；
    所述命令生成模块，配置为根据所述ECS命令信号生成内部命令信号，所述内部命令信号用于执行对应的ECS操作；
    所述地址计数模块，配置为根据所述内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；
    所述错误追踪记录模块，配置为接收错误信号，并根据所述计数结束信号和所述错误信号生成错误追踪信号，所述错误追踪信号用于记录所述ECS操作的错误信息。
  2. 根据权利要求1所述的ECS电路，其中，所述模式控制信号包括多用途命令MPC信号或刷新命令信号，其中：
    所述ECS控制模块，还配置为在所述ECS操作为手动ECS操作模式的情况下，根据所述MPC信号生成所述ECS命令信号，或者；
    所述ECS控制模块，还配置为在所述ECS操作为自动ECS操作模式的情况下，根据所述刷新命令信号生成所述ECS命令信号。
  3. 根据权利要求2所述的ECS电路，其中，所述ECS控制模块包括第一时序模块和命令控制模块，其中：
    所述第一时序模块，配置为生成ECS标识信号；
    所述命令控制模块，配置为接收所述ECS标识信号，以及在所述ECS标识信号处于有效状态时，获取刷新命令信号，并根据所述刷新命令信号产生所述ECS命令信号。
  4. 根据权利要求3所述的ECS电路，其中，所述第一时序模块，配置为接收第一时钟信号，根据所述第一时钟信号进行计数，生成所述ECS标识信号，并将所述ECS标识信号发送给所述命令控制模块；其中，在计数值满足预设条件时，所述ECS标识信号处于有效状态。
  5. 根据权利要求4所述的ECS电路，其中，所述第一时序模块，还配置为在所述ECS标识信号处于有效状态时，停止所述计数；
    所述命令控制模块，还配置为在根据所述刷新命令信号产生所述ECS命令信号之后，生成复位信号，将所述复位信号发送给所述第一时序模块，以使所述第一时序模块重新开始计数并且控制所述ECS标识信号处于无效状态。
  6. 根据权利要求5所述的ECS电路，其中，所述命令控制模块，还配置为在所述ECS标识信号处于无效状态时，将所接收到的刷新命令信号输出为内部刷新信号，以执行刷新操作。
  7. 根据权利要求1所述的ECS电路，其中，所述命令生成模块包括内部命令生成模块和第二时序模块，其中：
    所述内部命令生成模块，配置为在接收到所述ECS命令信号后，按照预设时序条件依次生成激活信号、读命令信号、写命令信号和预充电信号；
    所述第二时序模块，配置为控制所述激活信号和所述读命令信号之间的时间间隔满足第一时序条件，控制所述读命令信号和所述写命令信号之间的时间间隔满足第二时序条件以及控制所述写命令信号和所述预充电信号之间的时间间隔满足第三时序条件；
    其中，所述预设时序条件是由所述第一时序条件、所述第二时序条件和所述第三时序条件组成。
  8. 根据权利要求7所述的ECS电路，其中，所述ECS电路还包括存储控制模块和存储阵列，所述存储阵列包括至少一个存储组，所述存储组包括至少一个存储块，所述存储块包括至少一行和至少一列，其中：
    所述存储控制模块，配置为接收所述内部命令信号，并根据所述内部命令信号对所述存储阵列执行ECS操作，以及；
    所述存储控制模块，还配置为在执行所述ECS操作时，若检测到错误信息，则生成所述错误信号，并将所述错误信号发送给所述错误追踪记录模块。
  9. 根据权利要求8所述的ECS电路，其中，所述地址计数模块包括列计数模块、行计数模块和阵列计数模块，其中：
    所述列计数模块，配置为接收所述预充电信号，根据所述预充电信号对目标行进行列计数；在所述目标行的列计数完成时，生成列输出信号和列结束信号；
    所述行计数模块，配置为接收所述预充电信号和所述列输出信号，根据所述预充电信号和所述列输出信号对目标存储块进行行计数；在所述目标存储块的行计数完成时，生成行输出信号和行结束信号；
    所述阵列计数模块，配置为接收所述预充电信号和所述行输出信号，根据所述预充电信号和所述行输出信号对目标存储组进行存储块计数；在所述目标存储组的存储块计数完成时，生成存储块输出信号和存储块结束信号；以及，根据所述预充电信号和所述存储块输出信号对所述存储阵列进行存储组计数；在所述存储阵列的存储组计数完成时，生成存储组结束信号和ECS结束信号。
  10. 根据权利要求9所述的ECS电路，其中，所述阵列计数模块包括存储块计数模块和存储组计数模块，其中：
    所述存储块计数模块，配置为接收所述预充电信号和所述行输出信号，根据所述预充电信号和所述行输出信号对目标存储组进行存储块计数；在所述目标存储组的存储块计数完成时，生成所述存储块输出信号和所述存储块结束信号；
    所述存储组计数模块，配置为接收所述预充电信号和所述存储块输出信号，根据所述预充电信号和所述存储块输出信号对所述存储阵列进行存储组计数；在所述存储阵列的存储组计数完成时，生成所述存储组结束信号和所述ECS结束信号。
  11. 根据权利要求9所述的ECS电路，其中，所述列计数模块，还配置为在生成所述列输出信号和所述列结束信号之后，继续执行下一目标行的列计数，直至完成所述存储阵列中的每一行的列计数；
    所述行计数模块，还配置为在生成所述行输出信号和所述行结束信号之后，继续执行下一目标存储块的行计数，直至完成所述存储阵列中的每一存储块的行计数；
    所述阵列计数模块，还配置为在生成所述存储块输出信号和所述存储块结束信号之后，继续执行下一目标存储组的存储块计数，直至完成对所述存储阵列中的每一存储组的存储块计数。
  12. 根据权利要求10所述的ECS电路，其中，所述错误追踪记录模块包括第一错误追踪记录模块，其中：
    所述第一错误追踪记录模块，配置为接收计数模式信号，以及在所述计数模式信号为第一值的情况下，确定所述第一错误追踪记录模块的计数模式为码字计数模式；或者，在所述计数模式信号为第二值的情况下，确定所述第一错误追踪记录模块的计数模式为行计数模式。
  13. 根据权利要求12所述的ECS电路，其中，所述第一错误追踪记录模块，配置为在所述计数模式为所述码字计数模式的情况下，接收所述错误信号，根据所述错误信号进行码字计数，并在接收到所述ECS结束信号时，确定第一计数值；以及将所述第一计数值与第一阈值进行比较，在所述第一计数值大于或者等于所述第一阈值的情况下，将所述第一计数值进行保存；
    其中，所述第一计数值用于表征所述存储阵列中存在错误信息的码字数量。
  14. 根据权利要求12所述的ECS电路，其中，所述第一错误追踪记录模块，配置为在所述计数模式为所述行计数模式的情况下，接收所述错误信号和所述列结束信号，根据所述错误信号和所述列结束信号进行错误行计数，并在接收到所述ECS结束信号时，确定第二计数值；以及将所述第二计数值与第二阈值进行比较，在所述第二计数值大于所述第二阈值的情况下，将所述第二计数值进行保存；
    其中，所述第二计数值用于表征所述存储阵列中存在至少一个错误信息的行数量。
  15. 根据权利要求10所述的ECS电路，其中，所述错误追踪记录模块还包括第二错误追踪记录模块，其中：
    所述第二错误追踪记录模块，配置为接收所述错误信号，并根据所述错误信号和所述列结束信号对目标行的错误信息进行计数，在确定所述目标行的第三计数值后，将所述第三计数值与第一寄存器模块中存储的目标计数值进行比较，若所述第三计数值大于所述目标计数值，则将所述第一寄存器模块中存储的目标计数值清除，并将所述第三计数值保存为所述第一寄存器模块中的 目标计数值；以及继续根据所述错误信号和所述列结束信号对下一目标行进行错误计数，直至接收到所述ECS结束信号后，确定所述第一寄存器模块中存储的目标计数值；其中，所述第三计数值用于表征所述目标行中存在错误信息的码字数量。
  16. 根据权利要求15所述的ECS电路，其中，所述第二错误追踪记录模块，还配置为在将所述目标计数值保存进第一寄存器模块时，将所述目标计数值对应的地址信息保存在第二寄存器模块中；其中，所述地址信息包括所述目标计数值对应的行地址信息、存储块地址信息和存储组地址信息。
  17. 根据权利要求16所述的ECS电路，其中，所述第二错误追踪记录模块，还配置为在接收到所述ECS结束信号后，将所述第一寄存器模块中当前存储的目标计数值与第三阈值进行比较，若所述目标计数值大于或者等于所述第三阈值，则保留所述第一寄存器模块中存储的目标计数值和所述第二寄存器模块中存储的地址信息，若所述目标计数值小于所述第三阈值，则将所述第一寄存器模块中存储的目标计数值和所述第二寄存器模块中存储的地址信息清除。
  18. 一种ECS方法，应用于如权利要求1至17任一项所述的ECS电路，所述方法包括：
    通过所述ECS控制模块接收模式控制信号，并根据所述模式控制信号生成ECS命令信号；
    通过所述命令生成模块接收所述ECS命令信号，根据所述ECS命令信号生成内部命令信号，所述内部命令信号用于执行对应的ECS操作；
    通过所述地址计数模块接收所述内部命令信号，根据所述内部命令信号进行地址计数，在目标地址完成计数时生成计数结束信号；
    通过所述错误追踪记录模块接收所述计数结束信号和错误信号，根据所述计数结束信号和所述错误信号生成错误追踪信号，所述错误追踪信号用于记录所述ECS操作的错误信息。
  19. 一种存储器，所述存储器包括如权利要求1至17任一项所述的ECS电路。
PCT/CN2022/127048 2022-10-08 2022-10-24 一种ecs电路、方法和存储器 WO2024073907A1 (zh)

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