WO2024072186A1

WO2024072186A1 - Circuit board and semiconductor package comprising same

Info

Publication number: WO2024072186A1
Application number: PCT/KR2023/015221
Authority: WO
Inventors: 이수민; 심우섭; 유종현
Original assignee: 엘지이노텍 주식회사
Priority date: 2022-09-29
Filing date: 2023-10-04
Publication date: 2024-04-04
Also published as: KR20240044978A

Abstract

A semiconductor package according to an embodiment comprises: an insulation layer; a plurality of electrode parts including a through-part extending therethrough from the upper surface of the insulation layer to a partial area thereof; and a connection member embedded in the insulation layer, wherein the plurality of electrode parts include a first electrode part including a first through-part vertically overlapping the connection member and a second electrode part including a second through-part which does not vertically overlap the connection member, and the size of the first through-part satisfies a range of 80 % to 100 % of the size of the second through-part.

Description

Circuit board and semiconductor package containing the same

The embodiment relates to a circuit board, and in particular, to a circuit board capable of resolving height differences between a plurality of through electrodes connected to a semiconductor device and a semiconductor package including the same.

As the performance of electrical/electronic products progresses, technologies for arranging a greater number of semiconductor devices on a limited-sized semiconductor package substrate are being proposed and researched. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in obtaining the desired performance.

Accordingly, recently, semiconductor packages in which a plurality of semiconductor elements are arranged using a plurality of substrates have been provided. Such a semiconductor package has a structure in which a plurality of semiconductor devices are connected to each other in the horizontal and/or vertical directions on a substrate. Accordingly, the semiconductor package has the advantage of efficiently using the mounting area of the semiconductor device and enabling high-speed signal transmission through a short signal transmission path between the semiconductor devices.

Due to these advantages, the above semiconductor package is widely applied to mobile devices, etc.

In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), self-driving cars, and high-performance servers have increased the number of semiconductor devices and/or the size of each semiconductor device due to the trend of high integration. As the functional parts of devices are divided, the concept is expanding to semiconductor chiplets.

Accordingly, mutual communication between semiconductor devices and/or semiconductor chiplets is becoming important, and accordingly, there is a trend to place interposers between the semiconductor devices and the substrate of the semiconductor package.

The interposer gradually increases the width or width of the circuit pattern from the semiconductor device to the semiconductor package in order to facilitate mutual communication between semiconductor devices and/or semiconductor chiplets, or to interconnect semiconductor devices and semiconductor package substrates. By functioning as a redistribution layer, it can function to facilitate electrical signals between the semiconductor device and the semiconductor package substrate, which has a circuit pattern that is relatively large compared to the circuit pattern of the semiconductor device.

Meanwhile, a package substrate and/or an interposer applied to a semiconductor package is provided with a connection member connected to a semiconductor device and/or a semiconductor chiplet. The connecting member functions to horizontally connect a plurality of semiconductor devices and/or semiconductor chiplets. Accordingly, the connection member may be embedded in the package substrate and/or the interposer. At this time, the package substrate and/or the interposer are provided with a plurality of through electrodes connected to the semiconductor device and/or the semiconductor chiplet. The through electrode includes a first through electrode that overlaps the connection member in a vertical direction, and a second through electrode that does not overlap the connection member in the vertical direction but overlaps the first through electrode in the horizontal direction.

At this time, the first through electrode is connected to the connection member. Accordingly, the width and/or thickness of the first through electrode may be determined by the width of the connection electrode provided on the connection member and the thickness of the connection member. Accordingly, the first through electrode and the second through electrode may have different widths and/or thicknesses.

Because of this, the first through electrode and the second through electrode provided on the package substrate and/or interposer may have different heights. For example, due to the difference in width and/or thickness, a difference may occur in the height of the first through electrode and the height of the second through electrode. In addition, when there is a difference in height between the first and second through electrodes, a problem may occur in which the semiconductor device and/or the semiconductor chiplet cannot be mounted stably, thereby causing the semiconductor device and/or the semiconductor Problems may arise where the operating characteristics of the chiplet deteriorate.

Embodiments provide a circuit board with a new structure and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board with embedded connection members and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board capable of controlling a height difference between a plurality of through electrodes connected to a semiconductor device and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board with improved heat dissipation characteristics and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board with improved adhesion between the board and the connection member and a semiconductor package including the same.

The technical challenges to be achieved in the proposed embodiment are not limited to the technical challenges mentioned above, and other technical challenges not mentioned are clear to those skilled in the art from the description below. It will be understandable.

A circuit board according to an embodiment includes an insulating layer; a plurality of electrode portions including penetrating portions penetrating from the upper surface of the insulating layer to a portion of the region; and a connecting member embedded in the insulating layer, wherein the plurality of electrode portions include a first electrode portion including a first penetration portion that overlaps the connecting member in a vertical direction, and a first electrode portion that does not overlap the connecting member in the vertical direction. and a second electrode portion including a second through portion that does not include a second through portion, and the size of the first through portion satisfies a range of 80% to 100% of the size of the second through portion.

Additionally, a plurality of each of the first and second penetration parts is provided, and the size of each of the plurality of first penetration parts satisfies a range of 80% to 100% of the size of each of the plurality of second penetration parts.

Additionally, the plurality of first penetration parts overlap the plurality of second penetration parts in the horizontal direction.

In addition, the vertical thickness of the first penetration part and the second penetration part are the same, and the horizontal width of the first penetration part and the second penetration part are the same.

Additionally, the vertical thickness of the first penetration part is smaller than the vertical thickness of the second penetration part, and the horizontal width of the first penetration part is greater than the horizontal width of the second penetration part.

Additionally, the vertical thickness of the first penetration part is greater than the vertical thickness of the second penetration part, and the horizontal width of the first penetration part is smaller than the horizontal width of the second penetration part.

Additionally, at least one of the density and volume of the first penetrating portion satisfies a range of 80% to 100% of at least one of the density and volume of the second penetrating portion.

Additionally, the first electrode portion is disposed on the first through portion and includes a first protrusion protruding onto the insulating layer, and the second electrode portion is disposed on the second through portion and includes a first protrusion protruding onto the insulating layer. It includes a protruding second protrusion.

Additionally, the height of the upper surface of the first protrusion is the same as the height of the upper surface of the second protrusion.

Additionally, the horizontal width of the first penetration part satisfies the range of 10㎛ to 40㎛.

Additionally, each of the first and second penetrating portions has an inclination in which the width gradually decreases from the upper surface to the lower surface.

Additionally, each of the first and second penetration parts includes a first metal layer; and a second metal layer disposed on the first metal layer and including a metal material different from the first metal layer.

Additionally, the lower surface of the first metal layer of each of the first and second penetrating portions includes a convex portion toward the lower surface of the insulating layer.

In addition, the semiconductor package further includes first and second semiconductor devices disposed on the first and second electrode portions, and the first electrode portion is connected to a terminal of the first semiconductor device. It includes an electrode portion and a second group of first electrode portions connected to terminals of the second semiconductor device, wherein the second electrode portion includes a first group of second electrode portions connected to terminals of the first semiconductor device and the second semiconductor portion. It includes a second group of second electrode parts connected to the terminals of the device.

Additionally, the second penetration portion of at least one of the second electrode portions of the first group and the second group includes a plurality of sub-penetrating portions that vertically overlap with the single protrusion and are horizontally spaced apart from each other.

Additionally, the upper surface of the single protrusion that vertically overlaps the plurality of sub-penetrating parts includes a concave portion facing each of the plurality of sub-penetrating parts.

The embodiment can minimize the difference in height of the first and second electrode portions that are connected to the semiconductor device and penetrate a portion of the upper surface of the insulating layer.

Specifically, the first electrode portion may overlap the connecting member vertically, and the second electrode portion may overlap the first electrode portion horizontally without vertically overlapping the connecting member. The first electrode unit may include a first penetration part penetrating at least a portion of an insulating layer and a first protrusion located on the first penetration part and protruding on the insulating layer. The second electrode unit may include a second penetration part penetrating at least a portion of the insulating layer and a second protrusion located on the second penetration part and protruding on the insulating layer. At this time, the size of the second penetrating portion may correspond to the size of the first penetrating portion. Preferably, the size of the second through portion may satisfy a range of 80% to 100% of the size of the first through portion. The embodiment can minimize the height difference between the first electrode portion and the second electrode portion that occurs due to the size difference between the first penetration portion and the second penetration portion, and through this, the height difference between the first and second electrode portions can be minimized. Semiconductor devices can be placed stably.

Preferably, the vertical thickness of the first penetration part may be the same as the vertical thickness of the second penetration part, and the horizontal width of the first penetration part may be the same as the horizontal width of the second penetration part. You can.

Additionally, the vertical thickness of the first penetration part may be smaller than the vertical thickness of the second penetration part, and the horizontal width of the first penetration part may be greater than the horizontal width of the second penetration part.

Additionally, the vertical thickness of the first penetration part may be greater than the vertical thickness of the second penetration part, and the horizontal width of the first penetration part may be smaller than the horizontal width of the second penetration part.

Through this, the embodiment can ensure that the height of the first electrode portion and the height of the second electrode portion are uniform. The first and second semiconductor devices can be stably placed. Accordingly, the embodiment can improve the operating characteristics of the first and second semiconductor devices. Furthermore, the embodiment can ensure smooth operation of the first and second semiconductor devices, and thereby enable smooth operation of electronic products or servers.

In addition, the embodiment allows the first electrode portion and the second electrode portion to have the same height to prevent impedance changes that occur due to changes in the thickness of the first electrode portion and the second electrode portion, thereby further improving electrical reliability. It can be improved.

Meanwhile, the second penetration portion of the second electrode portion may include a plurality of sub-penetration portions that vertically overlap in common with one second pad portion. Additionally, the size of each of the plurality of sub-penetrating parts may correspond to the size of the first penetrating part. Therefore, even if the second penetration part includes a plurality of sub-penetrating parts, the first electrode part and the second electrode part can be made to have uniform heights. Additionally, a concave portion may be provided on the upper surface of the second protrusion that vertically overlaps the plurality of sub-penetrating portions. Additionally, a conductive adhesive member such as solder can be stably seated in the concave portion provided in the second protrusion. For example, the concave portion of the second protrusion may function as a dam that prevents movement of the solder while guiding the seating position where the solder is seated. Furthermore, the embodiment allows heat to be transmitted through the plurality of sub-penetrating portions, thereby improving the heat dissipation characteristics of the semiconductor package and further improving the operating characteristics of the semiconductor package.

Furthermore, in the embodiment, as the second penetrating portion includes a plurality of sub-penetrating portions, an impedance change caused by a decrease in the width of the second penetrating portion can be prevented, thereby improving the operation of the first and second semiconductor devices. Characteristics can be improved. Furthermore, the embodiment can ensure smooth operation of the first and second semiconductor devices, and thereby enable smooth operation of electronic products or servers.

1A is a cross-sectional view showing a semiconductor package according to a first embodiment.

FIG. 1B is a cross-sectional view showing a semiconductor package according to a second embodiment.

Figure 1C is a cross-sectional view showing a semiconductor package according to a third embodiment.

Figure 1D is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

FIG. 3 is a plan view of the circuit board of FIG. 2 viewed from above.

FIG. 4 is an enlarged cross-sectional view of the first region R1 of FIG. 2.

FIG. 5 is a cross-sectional view showing the detailed layer structure of the first and second through electrodes of FIG. 2.

FIG. 6 is an enlarged cross-sectional view of the first region of FIG. 2 according to the second embodiment.

FIG. 7 is an enlarged cross-sectional view of the first region of FIG. 2 according to the third embodiment.

FIG. 8 is an enlarged cross-sectional view of the first region of FIG. 2 according to the fourth embodiment.

FIG. 9 is an enlarged cross-sectional view of the first region of FIG. 2 according to the fifth embodiment.

Figure 10 is a cross-sectional view showing a circuit board according to the sixth embodiment.

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. However, identical or similar components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted. The suffixes “module” and “part” for components used in the following description are given or used interchangeably only for the ease of preparing the specification, and do not have distinct meanings or roles in themselves. Additionally, in describing the embodiments disclosed in this specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed descriptions will be omitted. In addition, the attached drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and all changes included in the spirit and technical scope of the present invention are not limited. , should be understood to include equivalents or substitutes.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

-전자 디바이스--Electronic Device-

Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on the semiconductor package.

The semiconductor device may include active devices and/or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one chip. Semiconductor devices may be logic chips, memory chips, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.

The memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the product lines to which the semiconductor package of the embodiment is applied include Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and SIP ( System In Package), but is not limited to this.

In addition, the electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, and network systems. ), computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive It may be, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board, which will be described later.

And in one embodiment, the circuit board may be a first board described below.

Additionally, in another embodiment, the circuit board may be a second board described below.

FIG. 1A is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 1B is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 1C is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 1D is a cross-sectional view showing a semiconductor package according to a fourth embodiment, and FIG. 1E is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

Referring to FIG. 1A , the semiconductor package of the first embodiment may include a first substrate 1100, a second substrate 1200, and a semiconductor device 1300.

The first substrate 1100 may refer to a package substrate.

For example, the first substrate 1100 may provide a space where at least one external substrate is coupled. The external substrate may refer to a second substrate 1200 coupled to the first substrate 1100. Additionally, the external substrate may refer to a main board included in an electronic device coupled to the lower portion of the first substrate 1100.

Additionally, although not shown in the drawing, the first substrate 1100 may provide a space where at least one semiconductor device is mounted.

The first substrate 1100 may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

A second substrate 1200 may be disposed on the first substrate 1100.

The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space where at least one semiconductor device is mounted. The second substrate 1200 may be connected to the at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space where the first semiconductor device 1310 and the second semiconductor device 1320 are mounted. The second substrate 1200 electrically connects the first semiconductor device 1310 and the second semiconductor device 1320, and connects the first and

second semiconductor devices

1310 and 1320 to the first substrate ( 1100) can be electrically connected. That is, the second substrate 1200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor devices and the package substrate.

In FIG. 1A, two

semiconductor devices

1310 and 1320 are shown disposed on the second substrate 1200, but the present invention is not limited thereto. For example, one semiconductor device may be disposed on the second substrate 1200, or alternatively, three or more semiconductor devices may be disposed on the second substrate 1200.

The second substrate 1200 may be disposed between the at least one semiconductor device 1300 and the first substrate 1100.

In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertical stack structure on the first substrate 1100 and function as a plurality of logic chips. Being able to have the functions of a logic chip may mean having the functions of an active element and a passive element. In the case of active devices, unlike passive devices, the current and voltage characteristics may not be linear, and in the case of active interposers, they may have the function of active devices. Additionally, the active interposer may function as a corresponding logic chip and perform a signal transmission function between the first substrate 1100 and a second logic chip disposed on top of the active interposer.

According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may function as a signal relay between the semiconductor device 1300 and the first substrate 1100, and may have passive device functions such as a resistor, capacitor, and inductor. there is. For example, the number of terminals of the semiconductor device 1300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 1300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced. At this time, the first substrate 1100 may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate 1100 to have a width and spacing for being connected to the semiconductor device 1300 and the main board, the thickness of the first substrate 1100 must be increased, or the thickness of the first substrate 1100 must be increased. There is a problem that the layer structure of the first substrate 1100 becomes complicated. Accordingly, in the first embodiment, the second substrate 1200 may be disposed on the first substrate 1100 and the semiconductor device 1300. And the second substrate 1200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 1300.

The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an AP that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application -specific IC), etc., or it may be a chip set containing a specific combination of those listed so far. And the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

The semiconductor package of the first embodiment may include a connection portion.

For example, a semiconductor package may include a first connection portion 1410 disposed between the first substrate 1100 and the second substrate 1200. The first connection part 1410 may couple the second substrate 1200 to the first substrate 1100 and electrically connect them.

For example, the semiconductor package may include a second connection portion 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection part 1420 may couple the semiconductor device 1300 to the second substrate 1200 and electrically connect them.

The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first substrate 1100. The third connection part 1430 can connect the first substrate 1100 to the main board and electrically connect them.

At this time, the first connection part 1410, the second connection part 1420, and the third connection part 1430 electrically connect a plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. You can connect with . That is, because the first connection part 1410, the second connection part 1420, and the third connection part 1430 have the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package is solder or It can be understood as an electrically connected part rather than a wire.

The wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu. In addition, the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. . And the direct bonding method between metals may refer to a bonding method using the second connection part 1420. In this case, the second connection portion 1420 may refer to a metal layer formed between a plurality of components through recrystallization.

Specifically, the first connection part 1410, the second connection part 1420, and the third connection part 1430 may be connected to a plurality of components using a thermal compression bonding method. The thermocompression bonding method may refer to a method of directly bonding a plurality of components by applying heat and pressure to the first connection part 1410, the second connection part 1420, and the third connection part 1430.

At this time, in at least one of the first substrate 1100 and the second substrate 1200, the electrode on which the first connection part 1410, the second connection part 1420, and the third connection part 1430 are disposed has the corresponding substrate. A protrusion may be provided that protrudes in an outward direction away from the insulating layer. The protrusion may protrude outward from the first substrate 1100 or the second substrate 1200.

The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode of the second substrate 1200 on which the second connection portion 1420 for coupling to the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between the plurality of second connection portions 1420 respectively connected to the plurality of terminals of the semiconductor device 1300 by conductive adhesive such as solder. there is. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion 1420. Accordingly, the embodiments are based on the degree of conformity, diffusion power, and diffusion prevention power that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and/or the substrate. For security purposes, the electrode of the second substrate 1200 on which the second connection portion 1420 is disposed may include a protrusion.

Additionally, the semiconductor package may include a connection member 1210.

The connecting member may be referred to as a bridge board. For example, the connecting member 1210 may include a redistribution layer. The connection member 1210 may function to electrically connect a plurality of semiconductor devices to each other horizontally. For example, because the area that a semiconductor device must have is generally too large, the connection member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, a buffering role of the circuit pattern for electrical connection is required. The buffering role may mean having an intermediate size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer has the buffering function. It can be included.

In one embodiment, the connecting member 1210 may be an inorganic bridge. As an example, the inorganic bridge may include a silicon bridge. That is, the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic substrate containing an organic material instead of the silicon substrate. The connecting member 1210 may be embedded in the second substrate 1200.

To this end, the second substrate 1200 may include a cavity, and the connecting member 1210 may be disposed within the cavity of the second substrate 1200. The connecting member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second substrate 1200.

Referring to FIG. 1B, the semiconductor package of the second embodiment may include a second substrate 1200 and a semiconductor device 1300. At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate 1100 is omitted compared to the semiconductor package of the first embodiment.

That is, the second substrate 1200 of the second embodiment can function as an interposer and as a package substrate.

The first connection portion 1410 disposed on the lower surface of the second substrate 1200 may couple the second substrate 1200 to the main board of the electronic device.

Referring to FIG. 1C, the semiconductor package of the third embodiment may include a first substrate 1100 and a semiconductor device 1300.

At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate 1200 is omitted compared to the semiconductor package of the first embodiment.

That is, the first substrate 1100 of the third embodiment can function as a package substrate and connect the semiconductor device 1300 and the main board. To this end, the first substrate 1100 may include a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 may be an inorganic bridge or an organic bridge that connects a plurality of semiconductor devices.

Referring to FIG. 1D , the semiconductor package of the fourth embodiment may further include a third semiconductor device 1330 compared to the semiconductor package of the third embodiment.

To this end, a fourth connection portion 1440 may be disposed on the lower surface of the first substrate 1100.

Additionally, a third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fourth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.

At this time, the third semiconductor device 1330 may have a structure disposed on the lower surface of the second substrate 1200 in the semiconductor package of FIG. 1B.

Referring to FIG. 1E, the semiconductor package of the fifth embodiment may include a first substrate 1100. First and

second semiconductor devices

1310 and 1320 may be disposed on the first substrate 1100. To this end, a first connection portion 1410 may be disposed between the first substrate 1100 and the first and

second semiconductor devices

1310 and 1320.

Additionally, a connecting member 1110 may be embedded in the first substrate 1110. The connecting member 1110 may horizontally connect the first and

second semiconductor devices

1310 and 1320.

Additionally, the first substrate 1100 may include a conductive coupling portion 1450. The conductive coupling portion 1450 may protrude further from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump or, alternatively, may be referred to as a post. The conductive coupling portion 1450 may be disposed with a protruding structure on the electrode disposed on the uppermost side of the first substrate 1100.

A third semiconductor device 1330 may be disposed on the conductive coupling portion 1450. At this time, the third semiconductor device 1330 may be connected to the first substrate 1100 through the conductive coupling portion 1450. Additionally, a second connection portion 1420 may be disposed between the first and

second semiconductor devices

1310 and 1320 and the third semiconductor device 1330.

Accordingly, the third semiconductor device 1330 may be electrically connected to the first and

second semiconductor devices

1310 and 1320 through the second connection portion 1420.

That is, the third semiconductor device 1330 is connected to the first substrate 1100 through the conductive coupling portion 1450, and the first and

second semiconductor devices

1310 and 1320 are connected to each other through the second connection portion 1420. It can also be connected with .

At this time, the third semiconductor device 1330 may receive a power signal and/or power through the conductive coupling portion 1450. Additionally, the third semiconductor device 1330 may exchange communication signals with the first and

second semiconductor devices

1310 and 1320 through the second connection unit 1420.

The semiconductor package of the fifth embodiment provides sufficient power for driving the third semiconductor device 1330 by supplying a power signal and/or power to the third semiconductor device 1330 through the conductive coupling portion 1450. However, smooth control of power operation may be possible.

Accordingly, the embodiment can improve the driving characteristics of the third semiconductor device 1330. That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor device 1330. Furthermore, the embodiment may allow at least one of the power signal, power, and communication signal of the third semiconductor device 1330 to be provided through different paths through the conductive coupling portion 1450 and the second connection portion 1420. there is. Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, embodiments may minimize mutual interference between power signals and communication signals.

Meanwhile, the third semiconductor device 1330 in the fifth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be disposed on the first substrate 1100. For example, the third semiconductor device 1330 may be a memory package including a memory chip. And the memory package may be coupled to the conductive coupling portion 1450. At this time, the memory package may not be connected to the first and

second semiconductor devices

1310 and 1320.

FIG. 2 is a cross-sectional view showing a circuit board according to the first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 viewed from above, FIG. 4 is an enlarged cross-sectional view of the first region R1 of FIG. 2, and FIG. 5 is a cross-sectional view showing the detailed layer structure of the first and second through electrodes of FIG. 2, FIG. 6 is an enlarged cross-sectional view of the first area of FIG. 2 according to the second embodiment, and FIG. 7 is a third embodiment. FIG. 8 is an enlarged cross-sectional view of the first region of FIG. 2 according to an example, FIG. 8 is an enlarged cross-sectional view of the first region of FIG. 2 according to the fourth embodiment, and FIG. 9 is an enlarged cross-sectional view of the first region of FIG. 2 according to the fifth embodiment. It is a cross-sectional view enlarging an area, and Figure 10 is a cross-sectional view showing a circuit board according to the sixth embodiment.

Hereinafter, a circuit board provided in a semiconductor package according to an embodiment and a connection member embedded in the circuit board will be described with reference to FIGS. 2 to 10.

Referring to FIG. 2, the semiconductor package of the embodiment may include a substrate 100 and a connection member 200 embedded in the substrate 100. As described with reference to FIGS. 1A to 1E, the connecting member 200 can horizontally connect a plurality of semiconductor devices, and for this purpose, it can include high-density electrode patterns. Additionally, the connecting member 200 may include at least one of an inorganic bridge and an organic bridge.

The substrate 100 may provide a space in which the connecting member 200 is buried. Additionally, the substrate 100 may provide a space where a plurality of semiconductor devices are mounted.

For example, first and second semiconductor devices may be mounted on the substrate 100 while being spaced apart from each other in the horizontal direction. At least one first terminal provided in the first semiconductor device and at least one second terminal provided in the second semiconductor device may be electrically connected to each other through the connecting member 200. For example, the first semiconductor device and the second semiconductor device may need to exchange signals with each other, and terminals for the mutual signal exchange may be electrically connected to the connection member 200.

The substrate 100 for this purpose may include an insulating layer 110 and an electrode portion.

The insulating layer 110 may include multiple layers. The insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The first insulating layer 111 may constitute an inner layer of the insulating substrate. The second insulating layer 112 may be disposed on the first insulating layer 111. For example, the second insulating layer 112 may refer to an insulating layer disposed on the uppermost side of the insulating substrate. The third insulating layer 113 may be disposed below the first insulating layer 111. For example, the third insulating layer 113 may refer to an insulating layer disposed on the lowermost side of the insulating substrate.

The first insulating layer 111 of the substrate may have a layer structure of at least one layer. Preferably, the first insulating layer 111 of the substrate may have a plurality of stacked structures. The laminated structure can be divided by the electrode portion. For example, the electrode unit may include a first electrode (EP1) and a second electrode (EP2). The first electrode EP1 may refer to a pad and/or trace. The second electrode EP2 may represent a via electrode. The first electrode EP1 and the second electrode EP2 may have different widths and/or different vertical cross-sectional shapes. Accordingly, the stacked structure can be distinguished based on the difference in width and/or the difference in vertical cross-sectional shape between the first electrode (EP1) and the second electrode (EP2). Through the above-described stacked structure, the substrate of the embodiment can electrically and efficiently connect at least one semiconductor device and/or the second substrate to the main board.

At this time, the first insulating layer 111 of the substrate in FIG. 2 is shown as having a four-layer structure, but it is not limited to this. For example, the first insulating layer 111 of the substrate may have a number of layers of 3 or less, and may have a number of layers of 5 or more.

Additionally, when the first insulating layer 111 includes a plurality of layers, each of the plurality of layers may include the same insulating material. In this case, the interface between the plurality of layers of the first insulating layer 111 may not be distinguished, and accordingly, the stacked structure can be distinguished based on the first electrode (EP1) and the second electrode (EP2).

Additionally, when the first insulating layer 111 includes a plurality of layers, at least one layer among the plurality of layers may include an insulating material different from at least one other layer. In this case, the interface between the plurality of layers containing different insulating materials can be distinguished.

Meanwhile, at least one layer among the plurality of layers of the first insulating layer 111 may include a reinforcing member. In one embodiment, the reinforcing member may mean glass fiber. In another embodiment, the reinforcing member may refer to GCP (Glass Core Primer). Additionally, in another embodiment, the plurality of layers of the first insulating layer 111 may not include reinforcing members such as glass fiber and/or GCP.

Meanwhile, a connecting member 200 may be embedded in the first insulating layer 111. For example, the first insulating layer 111 may include a receiving portion 110B in the form of a through hole in which the connecting member 200 is accommodated. The connecting member 200 may be embedded in the receiving portion 110B of the first insulating layer 111. Here, being buried may mean that the connecting member 200 is entirely covered with the first insulating layer 111.

The insulating layer 110 of the substrate may include a second insulating layer 112 and a third insulating layer 113. The second insulating layer 112 and the third insulating layer 113 of the substrate may be resist layers. For example, the second insulating layer 112 of the substrate may be a first resist layer disposed on the uppermost side of the substrate. Additionally, the third insulating layer 113 of the substrate may be a second resist layer disposed on the lowermost side of the substrate.

At this time, the second insulating layer 112 of the substrate may include the same insulating material as the first insulating layer 111 of the substrate. For example, when the first insulating layer 111 of the substrate is composed of a plurality of layers, the first insulating layer closest to the second insulating layer 112 among the first insulating layers of the plurality of layers is the first insulating layer 112. 2 It may include the same insulating material as the insulating layer 112. In this case, the interface between the first insulating layer 111 and the second insulating layer 112 of the substrate may not be distinguished. Correspondingly, the third insulating layer 113 of the substrate may include the same insulating material as the first insulating layer 111 of the substrate.

The second insulating layer 112 and the third insulating layer 113 of the substrate may function to protect the upper and lower surfaces of the first insulating layer 111 of the substrate, respectively. Accordingly, the second insulating layer 112 and the third insulating layer 113 of the substrate can be said to be protective layers. The second insulating layer 112 and the third insulating layer 113 of the substrate may be a solder resist layer containing an organic polymer material. For example, the second insulating layer 112 and the third insulating layer 113 of the substrate may include an epoxy acrylate-based resin. In detail, the second insulating layer 112 and the third insulating layer 113 of the substrate may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. However, the embodiment is not limited to this, and the second insulating layer 112 and the third insulating layer 113 of the substrate may be any one of a photo solder resist layer, a cover-lay, and a polymer material. Of course it exists.

The substrate 100 may include an electrode portion.

The electrode unit may penetrate at least a portion of the insulating layer 110.

The electrode unit may include a plurality of electrode units depending on location and function.

The electrode unit may include a first electrode unit 120. The first electrode portion 120 may penetrate a portion of the upper surface of the insulating layer 110. The first electrode portion 120 may vertically overlap the connecting member 200. The first electrode unit 120 may refer to an electrode electrically connected to the connection member 200.

The first electrode portion 120 may protrude on the insulating layer 110 while penetrating at least a portion of the insulating layer 110 .

For example, the first electrode unit 120 may include a first penetration part 121 that penetrates from the upper surface of the second insulating layer 112 to a partial area. The first penetration part 121 may be a penetration electrode that penetrates at least a portion of the second insulating layer 112 . The first penetrating portion 121 may vertically overlap the connecting member 200. Preferably, the connecting member 200 may include a first connecting electrode 210. The first connection electrode 210 may be a pad provided on the outermost layer of the connection member 200.

The first electrode portion 120 may be provided on the first penetration portion 121 and include a first protrusion 122 that protrudes onto the second insulating layer 112.

At this time, the first penetration part 121 and the first protrusion 122 of the first electrode part 120 may be one electrode formed integrally with each other, and penetrate the second insulating layer 112. The part that is exposed and the part that protrudes onto the second insulating layer 112 may be separated.

Meanwhile, the electrode portion of the substrate 100 may include a second electrode portion 130. The second electrode portion 130 may penetrate a portion of the upper surface of the insulating layer 110. The second electrode unit 130 may overlap the first electrode unit 120 horizontally. For example, the second electrode unit 130 may be an electrode disposed on the same layer as the first electrode unit 120.

The second electrode portion 130 may not overlap the connection member 200 perpendicularly. That is, the second electrode unit 130 may not be directly connected to the connecting member 200. The second electrode unit 130 may refer to an electrode that overlaps the first electrode unit 120 horizontally and does not vertically overlap the connection member 200.

The second electrode portion 130 may protrude on the insulating layer 110 while penetrating a portion of the upper surface of the insulating layer 110 .

For example, the second electrode unit 130 may include a second penetration part 131 that penetrates from the top surface of the second insulating layer 112 to a partial area. The second penetrating portion 131 may be a penetrating electrode that penetrates at least a portion of the second insulating layer 112 . The second penetrating portion 131 may vertically overlap the connecting member 200. The second penetration portion 131 may not vertically overlap the first connection electrode 210 of the connection member 200.

The second electrode portion 130 may be provided on the second penetration portion 131 and include a second protrusion 132 that protrudes onto the second insulating layer 112.

At this time, the second penetration portion 131 and the second protrusion 132 of the second electrode portion 130 may be one electrode formed integrally with each other, and penetrate the second insulating layer 112. The part that is exposed and the part that protrudes onto the second insulating layer 112 may be separated.

The first electrode unit 120 and the second electrode unit 130 may be post bumps connected to a semiconductor device.

That is, as the width of the terminals and the pitch of the terminals of the semiconductor device coupled to the substrate become smaller, when the semiconductor device is mounted using a conductive adhesive such as solder, the conductive adhesive may spread, resulting in a plurality of Problems may arise where the conductive adhesives are connected to each other. Through this, the embodiment can proceed with thermal compression bonding to reduce the volume of the conductive adhesive. At this time, if the substrate 100 does not include the first electrode portion 120 and the second electrode portion 130 that protrude onto the insulating layer 110, it may be difficult to reduce the volume of the conductive adhesive. . This may be because the height of the electrode on which the conductive adhesive is disposed is located lower than the height of the insulating layer 110, and thus the volume of the conductive adhesive increases by the difference between the height of the electrode and the height of the insulating layer.

Therefore, the substrate 100 of the embodiment has a degree of matching with the terminal of the semiconductor device and a diffusion prevention ability to prevent the intermetallic compound (IMC) formed between the conductive adhesive and the electrode portion from diffusing into the substrate. It may be provided with a first electrode part 120 and a second electrode part 130 that have a protruding structure for securing.

Referring to FIG. 3, each of the first electrode unit 120 and the second electrode unit 130 may be divided into a plurality of groups.

The first electrode unit 120 may include a first group of first electrode units 120A and a second group of first electrode units 120B. The first electrode portion 120A of the first group may refer to an electrode portion that overlaps the first semiconductor device in the vertical direction. For example, the first electrode part 120A of the first group may mean an electrode part connected to the first semiconductor device. The first electrode portion 120B of the second group may refer to an electrode portion that overlaps the second semiconductor device in the vertical direction. For example, the first electrode part 120B of the second group may mean an electrode part connected to the second semiconductor device.

The second electrode unit 130 may include a first group of second electrode units 130A and a second group of second electrode units 130B. The second electrode unit 130A of the first group may be disposed adjacent to the first electrode unit 120A of the first group. For example, the second electrode unit 130A of the first group may be disposed on one side of the first electrode unit 120A of the first group. The second electrode portion 130A of the first group may overlap the first semiconductor device in a vertical direction. The second electrode portion 130A of the first group may be connected to the first semiconductor device. The second electrode portion 130B of the second group may be disposed adjacent to the first electrode portion 120B of the second group. For example, the second electrode unit 130B of the second group may be disposed on the other side of the first electrode unit 120B of the second group. The second electrode portion 130B of the second group may overlap the second semiconductor device in a vertical direction. The second electrode portion 130B of the second group may be connected to the first semiconductor device.

Meanwhile, the height of the top surface of the first electrode unit 120 may be the same as the height of the top surface of the second electrode unit 130. For example, the top surface of the first penetration part 121 of the first electrode part 120 may be located on the same plane as the top surface of the second penetration part 131 of the second electrode part 130. . Additionally, the top surface of the first protrusion 122 of the first electrode unit 120 may be located on the same plane as the top surface of the second protrusion 132 of the second electrode unit 130.

To this end, the size of the first through portion 121 of the first electrode portion 120 may be the same as the size of the second through portion 131 of the second electrode portion 130. Here, being the same size means that the difference between the size of the first penetration part 121 of the first electrode part 120 and the size of the second penetration part 131 of the second electrode part 130 is 20. It may mean % or less, 15% or less, 10% or less, or 5% or less.

For example, the size of the first penetration part 121 of the first electrode part 120 is in the range of 80% to 100% of the size of the second penetration part 131 of the second electrode part 130. You can be satisfied. The difference between the size of the first penetration part 121 of the first electrode part 120 and the size of the second penetration part 131 of the second electrode part 130 exceeds 20%, or the first electrode part 120 When the size of one of the first penetration part 121 of the unit 120 and the second penetration part 131 of the second electrode part 130 is less than 80% or more than 100% of the size of the other one. , semiconductor devices may not be stably mounted on the first electrode unit 120 and the second electrode unit 130.

Specifically, if the sizes of the first through portion 121 and the second through portion 131 are outside the above range, plating may be performed in the process of plating the first through portion 121 and the second through portion 131. Deviations may occur. Each of the first through portion 121 and the second through portion 131 fills the inside of each of the first through hole and the second through hole penetrating at least a portion of the second insulating layer 112 with a conductive material. It can be formed by doing so. Additionally, when the difference in size between the first through hole and the second through hole is outside the above range, a difference may occur between the plating amount in the first through hole and the plating amount in the second through hole. Due to this, there is a difference between the height of the upper surface of the first protrusion 122 disposed on the first penetrating portion 121 and the height of the upper surface of the second protruding portion 132 disposed on the second penetrating portion 131. may occur. For example, a protrusion of an electrode unit with a relatively large size may have a lower height than a protrusion of an electrode unit with a relatively small size.

When the upper surfaces of the first electrode unit 120 and the second electrode unit 130 are not flat and have a height difference, the semiconductor device on the first electrode unit 120 and the second electrode unit 130 is tilted. Problems with combining in a true state may occur. In addition, when there is a height difference as described above, the protrusion located relatively high may be electrically connected to the semiconductor device, but the protrusion located relatively low may not be electrically connected to the semiconductor device. Conversely, a protrusion located relatively low may be electrically connected to the semiconductor device, but a protrusion located relatively high may not be electrically connected to the semiconductor device. As a result, the semiconductor device may not operate smoothly, and further, electronic products or servers may not operate smoothly.

Additionally, the substrate can perform impedance matching by adjusting the width or thickness of the electrode portions. At this time, when a thickness difference between the first electrode portion 120 and the second electrode portion 130 occurs due to plating deviation due to the size difference between the first penetration portion 121 and the second penetration portion 131. , impedance matching may not be achieved properly, and problems with the electrical reliability of the semiconductor package may occur due to impedance mismatching.

Therefore, in the embodiment, the difference between the size of the first penetration part 121 of the first electrode part 120 and the size of the second penetration part 131 of the second electrode part 130 satisfies the above range. , Through this, the height difference between the first protrusion 122 of the first electrode unit 120 and the second protrusion 132 of the second electrode unit 130 is minimized, and further, the first protrusion 122 and the second protrusion 132 are The two protrusions 132 may have substantially the same height.

Meanwhile, the size of the first penetration part 121 may mean the density and/or volume of the first penetration part 121. Additionally, the size of the second penetrating part 131 may mean the density and/or volume of the second penetrating part 131. For example, when the vertical thickness of the first penetration part 121 is the same as the vertical thickness of the second penetration part 131, the width of the first penetration part 121 is the same as the vertical thickness of the second penetration part 131. It may range from 80% to 100% of the width of the portion 131. For example, when the vertical thickness of the first penetration part 121 is smaller than the vertical thickness of the second penetration part 131, the width of the first penetration part 121 is equal to the thickness difference. It may be larger than the width of the second penetration portion 131. For example, when the vertical thickness of the first penetration part 121 is greater than the vertical thickness of the second penetration part 131, the width of the first penetration part 121 is greater than the vertical thickness of the second penetration part 131. It may be smaller than the width of (131) by the thickness difference.

In one embodiment, the thickness of the first penetration part 121 in the vertical direction may be the same as the thickness of the second penetration part 131 in the vertical direction. The horizontal width W2 of the second penetrating part 131 may range from 80% to 100% of the horizontal width W1 of the first penetrating part 121. Through this, the embodiment can eliminate the plating deviation between the first through portion 121 and the second through portion 131, and through this, the first protrusion 122 and the second penetrating portion of the first electrode portion 120 The second protrusion 132 of the electrode unit 130 may have a uniform height.

Meanwhile, the width W1 of the first penetration portion 121 may be determined by the width of the first connection electrode 210 provided on the connection member 200. Therefore, it may be difficult to change the width W1 of the first penetration portion 121. Accordingly, the width W1 of the first penetration part 121 can be determined based on the width of the first connection electrode 210 of the connecting member 200, and the width of the second penetration part 131 is corresponding to this. Width (W2) can be adjusted.

For example, the width W1 of the first penetration portion 121 may satisfy the range of 10 μm to 40 μm. Preferably, the width W1 of the first penetration portion 121 may satisfy the range of 12㎛ to 35㎛. More preferably, the width W1 of the first penetration portion 121 may satisfy the range of 15㎛ to 30㎛. If the width W1 of the first penetration part 121 is less than 10㎛, the allowable current of the signal transmitted through the first penetration part 121 may decrease. Additionally, if the width W1 of the first penetration part 121 is smaller than 10㎛, the resistance of the first penetration part 121 may increase. Additionally, if the width W1 of the first penetrating portion 121 is greater than 40 μm, it may be difficult to arrange all of the plurality of first penetrating portions 121 that vertically overlap the connecting member 200.

Meanwhile, the range of the width W1 of the first through portion 121 is determined based on the width of the first connection electrode 210 of the connection member 200, and may be the same or have a deviation of 20% or less. Thus, the width W2 of the second penetrating portion 131 can be determined.

At this time, the width of the first through portion 121 and the width of the second through portion 131 may correspond to the widths of the first and second through holes penetrating the corresponding second insulating layer 112. At this time, the first and second through holes may be formed through exposure and development processes. In another embodiment, the first and second through holes may be formed through a laser process.

Specifically, when the first and second through holes are formed through the exposure and development process, the width of the first and second through holes may be determined by the exposure resolution in the exposure process. However, the minimum width of the first and second through-holes that can be formed in general exposure process capabilities is about 50㎛. At this time, the width of the first and second through holes in the embodiment is 40㎛ or less, and accordingly, in the embodiment, the first and second through

holes

121 and 131 are formed through a laser process. A second through hole may be formed.

Accordingly, the first and second through holes may have a shape whose width changes in the thickness direction. Correspondingly, the first penetration part 121 of the first electrode part 120 and the second penetration part 131 of the second electrode part 130 may have a shape whose width changes in the thickness direction.

Specifically, the first penetrating part 121 and the second penetrating part 131 may have an inclination in which the width gradually decreases from the upper surface to the lower surface. At this time, the width W1 of the first penetration part 121 and the width W2 of the second penetration part 131 may mean the width of the area having the largest width in the entire area in the thickness direction.

Accordingly, the width of the lower surface of each of the first and second penetrating

parts

121 and 131 may be smaller than the width of the upper surface.

Meanwhile, referring to FIG. 4 , the electrode unit may further include a third electrode unit 140 disposed between the connecting member 200 and the first electrode unit 120. The third electrode unit 140 may electrically connect the first connection electrode 210 of the connecting member 200 and the first electrode unit 120.

Additionally, the electrode unit may include a fourth electrode unit 150 that overlaps the third electrode unit 140 in a horizontal direction and does not vertically overlap the connection member 200. The fourth electrode unit 150 may be disposed below the second electrode unit 130 to connect the fourth electrode unit 150 and internal electrodes of the substrate 100.

At this time, as the first through portion 121 and the second through portion 131 have the same width difference in the thickness direction as described above, the first through portion 121 and the third electrode portion 140 ) and/or the bonding force between the second penetration portion 131 and the fourth electrode portion 150 may be reduced. That is, as the contact area between the first penetrating portion 121 and the third electrode portion 140 decreases, the contact area with the third electrode portion 140 is reduced due to various factors (e.g., thermal stress). Cracks may occur in the lower area of the first penetration portion 121. In addition, as the contact area between the second penetrating portion 131 and the fourth electrode portion 150 decreases, various factors (e.g., thermal stress) cause contact with the fourth electrode portion 150. Cracks may occur in the lower area of the second penetration portion 131.

Accordingly, as shown in FIG. 5, each of the first through portion 121 of the first electrode portion 120 and the second through portion 131 of the second electrode portion 130 may include a plurality of metal layers.

For example, referring to (a) of FIG. 5 , the first penetration part 121 may include a first metal layer 121-1 disposed on the third electrode part 140. Additionally, the first penetration portion 121 may include a second metal layer 121-2 disposed on the first metal layer 121-1. At this time, the first metal layer 121-1 and the second metal layer 121-2 may include different metal materials.

Preferably, the first metal layer 121-1 may include nickel. And, the second metal layer 121-2 may include copper. The first metal layer 121-1 may improve the bonding force between the second metal layer 121-2 and the third electrode portion 140. For example, when the second metal layer 121-2 is placed directly on the third electrode portion 140, oxidation of the third electrode portion 140 may occur, which may cause the third electrode portion 140 to be oxidized. The bonding force between the portion 140 and the second metal layer 121-2 may decrease. Therefore, the first metal layer 121-1 functions to prevent oxidation of the third electrode portion 140 and improve the bonding force between the second metal layer 121-2 and the third electrode portion 140. can do. In addition, the first metal layer 121-1 is such that the first penetration portion 121 is separated from the third electrode portion 140 due to contraction and expansion of the second insulating layer 112 due to thermal stress. thing can be solved.

Specifically, when the first metal layer 121-1 includes nickel, adhesion between the third electrode portion 140 and the first penetration portion 121 of the first electrode portion 120 may be improved. You can. In addition, when electrical connection is later made with the first electrode portion 120 through a material such as solder, the solder may spread to form an inter-metallic compound, and the inter-metallic compound may be formed. There is a problem with poor mechanical and electrical reliability. In particular, if the second metal layer 121-2 is made of copper, the problem of forming an intermetallic joint may become worse. When nickel is placed, it is necessary to prevent the formation of an intermetallic joint by preventing diffusion of solder. This can improve the electrical and mechanical reliability of the semiconductor package.

At this time, the third electrode unit 140 may include a crevice 140C. For example, the upper surface of the third electrode portion 140 may include a crevice 140C that vertically overlaps the first penetration portion 121 and is concave toward the lower surface of the third electrode portion 140. . The crevice 140C may be filled with the first metal layer 121-1 of the first penetration part 121. Through this, the contact area between the third electrode portion 140 and the first penetration portion 121 can be increased, and thus the bonding force can be further improved.

In addition, referring to (b) of FIG. 5, the second penetration portion 131 of the second electrode portion 130 may also include a first metal layer 133-1 and a second metal layer 133-2. . The first metal layer 133-1 of the second penetrating portion 131 may be disposed on the fourth electrode portion 150. Additionally, the second metal layer 133-2 of the second electrode unit 130 may be disposed on the first metal layer 133-1. A crevice 150C may be provided on the upper surface of the fourth electrode portion 150, and the first metal layer 133-1 of the second penetration portion 131 may be provided with a crevice (150C) of the fourth electrode portion 150. It can be provided by filling 150C).

Meanwhile, the third electrode part 140 connected to the first electrode part 120 may include a first extension part 141 and a first pad part 142. The first extension portion 141 of the third electrode portion 140 may be connected to the first connection electrode 210 of the connection member 200. The first pad portion 142 of the third electrode portion 140 may be disposed between the first extension portion 141 and the first penetration portion 121 of the first electrode portion 120, and these You can connect between them.

Meanwhile, the fourth electrode portion 150 connected to the second electrode portion 130 may include a second extension portion 151 and a second pad portion 152. The second extension portion 151 of the fourth electrode portion 150 may be connected to the second connection electrode 160 provided on the substrate. The second connection electrode 160 may horizontally overlap the first connection electrode 210 and/or the connection member 200. The second pad portion 152 of the fourth electrode portion 150 may be disposed between the second extension portion 151 and the second penetration portion 131 of the second electrode portion 130, and these You can connect between them.

The first connection electrode 210 of the connection member 200 may include a plurality of electrode parts. For example, the first connection electrode 210 may include a first electrode part 211 disposed on the connection member 200. The first electrode part 211 may refer to an electrode part disposed on the uppermost side among a plurality of electrode parts provided on the connection member 200.

Additionally, the first connection electrode 210 of the connection member 200 may include a second electrode part 212 disposed on the first electrode part 211. The second electrode part 212 may protrude from the first electrode part 211 to have a certain height. The second electrode part 212 may be referred to as a post. The second electrode part 212 may be provided to improve alignment between the first electrode part 211 and the third electrode part 140 on the connecting member 200. For example, the second electrode part 212 may be disposed at a certain height on the first electrode part 211, through which the first electrode part 211 and the plurality of first penetration parts ( 121) can be aligned vertically.

At this time, the first connection electrode 210 and the second connection electrode 160 of the connection member 200 may have different heights.

For example, there may be a difference between the depth of the receiving portion 110B provided in the insulating layer 110 and the thickness of the connecting member 200, and the thickness of the connecting member 200 may be adjusted corresponding to the thickness difference. 1 The connection electrode 210 may be positioned higher or lower than the second connection electrode 160.

Accordingly, a difference may occur between the height of the upper surface of the third electrode unit 140 and the height of the upper surface of the fourth electrode unit 150.

For example, as shown in FIG. 4, the top surface of the first connection electrode 210 of the connection member 200 may be positioned higher than the top surface of the second connection electrode 160. In this case, the upper surface of the third electrode unit 140 may be positioned higher than the upper surface of the fourth electrode unit 150. In this case, when the width of the first penetration part 121 of the first electrode part 120 and the width of the second penetration part 131 of the second electrode part 130 are the same, the width of the first penetration part 121 of the first electrode part 120 is the same. The upper surface of 120 may be positioned higher than the upper surface of the second electrode unit 130. Accordingly, in the embodiment, the width W2 of the second penetration part 131 is smaller than the width W1 of the first penetration part 121. For example, the width W1 of the first through portion 121 is equal to the difference in height between the upper surface of the third electrode portion 140 and the upper surface of the fourth electrode portion 150. Make it larger than the width (W2). Through this, the embodiment can make the thickness of the first penetration part 121 smaller than the thickness of the second penetration part 131 by making a difference in the width, and through this, the first electrode part 120 The height of the upper surface of the first protrusion 122 may be the same as the height of the upper surface of the second protrusion 132 of the second electrode unit 130.

Meanwhile, as shown in FIG. 6, the top surface of the first connection electrode 210 of the connection member 200 may be located lower than the top surface of the second connection electrode 160. For example, the first connection electrode 210 may include only the first electrode part.

In this case, the upper surface of the third electrode unit 140 may be located lower than the upper surface of the fourth electrode unit 150. In this case, when the width of the first penetration part 121 of the first electrode part 120 and the width of the second penetration part 131 of the second electrode part 130 are the same, the width of the first penetration part 121 of the first electrode part 120 is the same. The upper surface of 120 may be located lower than the upper surface of the second electrode unit 130. Accordingly, in the embodiment, the width W2 of the second penetration part 131 is larger than the width W1 of the first penetration part 121. For example, the width W1 of the first through portion 121 is equal to the difference in height between the upper surface of the third electrode portion 140 and the upper surface of the fourth electrode portion 150. Make it smaller than the width (W2). Through this, the embodiment can make the thickness of the first penetration part 121 larger than the thickness of the second penetration part 131 by making a difference in the width, and through this, the first electrode part 120 The height of the upper surface of the first protrusion 122 may be the same as the height of the upper surface of the second protrusion 132 of the second electrode unit 130.

Meanwhile, as shown in FIG. 7, the top surface of the first connection electrode 210 of the connection member 200 may be located on the same plane as the top surface of the second connection electrode 160. In addition, the sizes of the third electrode unit 140 and the fourth electrode unit 150 may be the same, and accordingly, the height of the upper surface of the third electrode unit 140 and the upper surface of the fourth electrode unit 150 The height may be the same. In this case, the thickness of the first penetration part 121 and the thickness of the second penetration part 131 may be the same, and further, the width of the first penetration part 121 and the width of the second penetration part 131 may be the same. may be the same.

Meanwhile, as shown in FIG. 8, the second electrode portion 130 may include at least a plurality of sub-penetrating portions.

Specifically, the first electrode units 120 described above may be spaced apart from each other and may be provided in plural numbers, and the second electrode units 130 may also be provided in plural numbers and spaced apart from each other. Additionally, the size of the first penetration part of each of the plurality of first electrode parts may correspond to the size of the second penetration part of each of the plurality of second electrode parts.

Meanwhile, at least one of the plurality of second electrode units 130 may include a plurality of sub-electrodes commonly connected to one second protrusion 132.

Specifically, the second electrode portion 130 includes a first group of second electrode portions 130A connected to the first semiconductor device and a second group of second electrode portions 130B connected to the second semiconductor device. can do. In addition, at least one second electrode part among the first group of second electrode parts and the second group of second electrode parts may include one second protrusion 132 and a plurality of sub-penetrating parts vertically overlapping. .

Specifically, the second penetrating part 131 may be smaller than the existing penetrating part in order to have the same size as the first penetrating part 121. And when the size of the second penetrating portion 131 decreases, the allowable current of the signal may decrease accordingly. In addition, when the size of the second through portion 131 is reduced, the contact area between the second through portion 131 and the insulating layer 110 decreases, and accordingly, the second through portion 131 The adhesion between the insulating layer 110 and the insulating layer 110 may decrease. Additionally, when the width of the second penetrating part 131 is reduced, the heat transfer characteristics transmitted through the second penetrating part 131 may deteriorate, and thus the heat dissipation characteristics may deteriorate. In addition, when the size of the second penetrating portion 131 is reduced, a corresponding problem may occur in which the impedance matching state is distorted, and as a result, the design of other electrode parts provided on the substrate must be changed to perform impedance matching. can do.

Accordingly, the embodiment allows the second penetrating portion 131 to include a plurality of sub-penetrating portions, thereby improving heat transfer characteristics, increasing heat dissipation effect, and maintaining impedance matching accordingly.

For example, at least one of the plurality of second electrode portions 130 includes a second protrusion 132 and a plurality of first sub-penetrating portions that vertically overlap the second protrusion 132 and are horizontally spaced from each other ( 131a) and a second sub-penetrating part 131b.

The first sub-penetrating part 131a and the second sub-penetrating part 131b may be commonly connected to one second protrusion 132. For example, the first sub-penetrating part 131a and the second sub-penetrating part 131b may each vertically overlap with one second protruding part 132.

Additionally, the first sub-penetrating part 131a and the second sub-penetrating part 131b may have the same thickness and width. For example, the first sub-penetrating part 131a and the second sub-penetrating part 131b may have the same volume. Preferably, the first sub-penetrating part 131a and the second sub-penetrating part 131b may have the same size.

Additionally, the first sub-penetrating part 131a may have the same size as the first penetrating part 121. Additionally, the second sub-penetrating part 131b may have the same volume as the first penetrating part 121. Additionally, the first sub-penetrating part 131a may have the same size as the first penetrating part 121. Through this, the embodiment shows that even if the second penetration part 131 of the second electrode part 130 includes the first sub-penetrating part 131a and the second sub-penetrating part 131b, the first electrode part ( 120) and the second electrode portion 130 can be made to have a uniform height.

However, the upper surface of the second protrusion 132 may have a step. For example, the second protrusion 132 may have a step as it vertically overlaps a plurality of sub-penetrating parts. For example, the second protrusion 132 may include a dimple area provided in an area that vertically overlaps a plurality of penetrating parts. For example, the second protrusion 132 has a concave portion CP in an area vertically overlapping with the first sub-penetrating part 131a and in an area vertically overlapping with the second sub-penetrating part 131b. may be provided.

The concave portion CP may allow a conductive adhesive member such as solder to be stably seated on the second protrusion 134 . For example, the concave portion CP may function as a dam to prevent movement of the solder as it is seated.

Meanwhile, as shown in FIG. 9, in order to improve the heat dissipation characteristics and/or impedance matching, the fourth electrode unit 150, rather than the second electrode unit 130, may include a plurality of sub-extensions. .

For example, at least one of the plurality of fourth electrode parts 150 vertically overlaps one second pad part 152 and includes a first sub-extension part 141a and a second sub-extension part horizontally spaced from each other. It may include (141b). In addition, the first sub-extension portion 141a and the second sub-extension portion 141b of the fourth electrode portion 150 improve heat dissipation characteristics and correspond to a decrease in the width of the second penetration portion 131. Accuracy for changing impedance matching conditions can be improved.

Furthermore, the upper surface of the second pad portion 152 may include a concave portion CP2 that vertically overlaps the first sub-extension portion 141a and the second sub-extension portion 141b. In addition, the concave portion CP2 may function to increase the contact area with the second insulating layer 112, thereby preventing the second insulating layer 112 from being peeled off.

Furthermore, the concave portion CP2 may function as a crevice 150C of the fourth electrode portion 150 described with reference to FIG. 5, and through this, a separate process for forming the crevice 150C can be omitted. You can.

Meanwhile, referring to FIG. 10 , the connecting member 200 may be disposed in a receiving portion provided in the first insulating layer 110. At this time, the receiving part may be provided in at least a portion of the first insulating layer 110. The receiving portion may be in the form of a recess rather than a through hole. Accordingly, an adhesive member 170 may be provided on the recess.

The adhesive member 170 may enable the connecting member 200 to be firmly fixed to the insulating layer 110 . The adhesive member 170 may have a different width from the connecting member 200. Additionally, the adhesive member 170 may be larger than the width of the connecting member 200. Through this, it is possible to prevent the connection member 200 from being separated from various damages inflicted in the operating environment of the semiconductor package.

Specifically, the first electrode portion may vertically overlap the connecting member, and the second electrode portion may overlap the first electrode portion horizontally without vertically overlapping the connecting member. The first electrode unit may include a first penetration part penetrating at least a portion of an insulating layer and a first protrusion located on the first penetration part and protruding on the insulating layer. The second electrode unit may include a second penetration part penetrating at least a portion of the insulating layer and a second protrusion located on the second penetration part and protruding on the insulating layer. At this time, the size of the second penetrating portion may correspond to the size of the first penetrating portion. Preferably, the size of the second through portion may satisfy a range of 80% to 100% of the size of the first through portion. The embodiment can minimize the height difference between the first electrode portion and the second electrode portion that occurs due to the size difference between the first penetration portion and the second penetration portion, and through this, the height difference between the first and second electrode portions can be minimized. Semiconductor devices can be placed stably.

Meanwhile, the second penetration portion of the second electrode unit may include a plurality of sub-penetrating portions that vertically overlap in common with one second pad portion. Additionally, the size of each of the plurality of sub-penetrating parts may correspond to the size of the first penetrating part. Therefore, even if the second penetration part includes a plurality of sub-penetrating parts, the first electrode part and the second electrode part can be made to have uniform heights. Additionally, a concave portion may be provided on the upper surface of the second protrusion that vertically overlaps the plurality of sub-penetrating portions. Additionally, a conductive adhesive member such as solder can be stably seated in the concave portion provided in the second protrusion. For example, the concave portion of the second protrusion may function as a dam that prevents movement of the solder while guiding the seating position where the solder is seated. Furthermore, the embodiment allows heat to be transmitted through the plurality of sub-penetrating portions, thereby improving the heat dissipation characteristics of the semiconductor package and further improving the operating characteristics of the semiconductor package.

Meanwhile, when a circuit board having the characteristics of the above-described invention is used in IT devices such as smartphones, server computers, TVs, or home appliances, functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems such as leakage current or electrical short circuits between terminals. Alternatively, the problem of electrical opening of the terminal supplying the semiconductor chip can be solved. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

When a circuit board having the characteristics of the above-mentioned invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside and prevent leakage. The stability of the transport device can be further improved by solving the problem of electrical short-circuiting between currents or terminals, or the problem of electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

Although the above description focuses on the embodiment, this is only an example and does not limit the embodiment, and those skilled in the art will understand that there are various options not exemplified above without departing from the essential characteristics of the present embodiment. You will see that variations and applications of branches are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences related to application should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims

insulating layer;

a plurality of electrode portions including penetrating portions penetrating from the upper surface of the insulating layer to a portion of the region; and

It includes a connecting member embedded in the insulating layer,

The plurality of electrode units,

A first electrode portion including a first penetration portion that overlaps the connection member in a vertical direction,

A second electrode portion including a second penetrating portion that does not overlap the connecting member in a vertical direction,

A semiconductor package in which the size of the first through portion satisfies a range of 80% to 100% of the size of the second through portion.
According to paragraph 1,

Each of the first and second penetrating portions is provided in plural numbers,

A semiconductor package in which the size of each of the plurality of first through parts satisfies a range of 80% to 100% of the size of each of the plurality of second through parts.
According to paragraph 2,

A semiconductor package, wherein the plurality of first penetration parts overlap the plurality of second penetration parts in a horizontal direction.
According to any one of claims 1 to 3,

The vertical thicknesses of the first penetrating portion and the second penetrating portion are the same,

A semiconductor package, wherein the horizontal widths of the first through portion and the second through portion are equal to each other.
According to any one of claims 1 to 3,

The vertical thickness of the first penetrating portion is smaller than the vertical thickness of the second penetrating portion,

A semiconductor package wherein the horizontal width of the first through portion is greater than the horizontal width of the second through portion.
According to any one of claims 1 to 3,

The vertical thickness of the first penetrating portion is greater than the vertical thickness of the second penetrating portion,

A semiconductor package wherein the horizontal width of the first through portion is smaller than the horizontal width of the second through portion.
According to any one of claims 3 to 5,

A semiconductor package, wherein at least one of the density and volume of the first penetrating portion satisfies a range of 80% to 100% of at least one of the density and volume of the second penetrating portion.
According to any one of claims 1 to 3,

The first electrode portion is disposed on the first through portion and includes a first protrusion protruding onto the insulating layer,

The second electrode portion is disposed on the second penetration portion and includes a second protrusion protruding onto the insulating layer.
According to clause 8,

A semiconductor package wherein the height of the top surface of the first protrusion is equal to the height of the top surface of the second protrusion.
According to any one of claims 1 to 3,

A semiconductor package wherein the horizontal width of the first through portion satisfies the range of 10㎛ to 40㎛.