WO2024071701A2 - Dispositif synaptique, son procédé de fabrication et dispositif neuromorphique comprenant un dispositif synaptique - Google Patents

Dispositif synaptique, son procédé de fabrication et dispositif neuromorphique comprenant un dispositif synaptique Download PDF

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WO2024071701A2
WO2024071701A2 PCT/KR2023/012887 KR2023012887W WO2024071701A2 WO 2024071701 A2 WO2024071701 A2 WO 2024071701A2 KR 2023012887 W KR2023012887 W KR 2023012887W WO 2024071701 A2 WO2024071701 A2 WO 2024071701A2
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electrode
synaptic
lithium
synaptic device
voltage
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English (en)
Korean (ko)
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최병준
박규민
박주환
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서울과학기술대학교 산학협력단
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Publication of WO2024071701A2 publication Critical patent/WO2024071701A2/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides

Definitions

  • the present invention relates to an electronic device, a method of manufacturing the same, and a device including the electronic device, and more specifically, to a synaptic device, a method of manufacturing the same, and a neuromorphic device including the synaptic device.
  • Neuromorphic computing is the implementation of artificial intelligence behavior by imitating the human brain in hardware. Focusing on the fact that the human brain performs very complex functions but consumes only about 20W of energy, neuromorphic computing mimics the human brain structure itself to provide superior association, reasoning, and recognition capabilities compared to existing von Neumann computing. Artificial intelligence operations can be performed with ultra-low power.
  • the neuromorphic system that operates such neuromorphic computing is composed of numerous neurons (neuronal elements) and synapses (synaptic elements), just like the human brain, and includes additional circuits for signal processing and transmission. Synapses remember the connection strength (weight) according to the correlation of spikes expressed by neurons, and in some cases, adjust the connection strength through the process of strengthening/increasing (potentiation) and weakening/depression (depression). Should be.
  • synaptic devices resistive random access memory (RRAM) and memristor-based devices are being studied, and recently, synaptic devices based on MOSFET (metal-oxide-semiconductor field-effect transistor) are also being studied.
  • RRAM resistive random access memory
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • existing RRAM-based synaptic devices require a fairly high forming voltage, they have various problems and limitations in this regard. For example, in order to apply a high forming voltage, it may be required to complicate the structure of the device. Therefore, manufacturing the device becomes difficult and scaling may be disadvantageous. Additionally, the durability of the device may be reduced due to the high forming voltage. In addition, existing RRAM-based synaptic devices have a problem in that it is not easy to secure high linearity and symmetry in conductance modulation characteristics.
  • the technical problem to be achieved by the present invention is to provide a synaptic device that can significantly reduce the forming voltage and is advantageous for reduced scaling and manufacturing (mass production) through a simple structure.
  • the technical problem to be achieved by the present invention is to provide a synaptic device that can secure relatively excellent linearity and symmetry in conductance modulation characteristics.
  • the technical problem to be achieved by the present invention is to provide a method of manufacturing the synaptic device.
  • the technical problem to be achieved by the present invention is to provide a neuromorphic device (neuromorphic system) including the synaptic device.
  • a synaptic device includes: a first electrode capable of absorbing and releasing lithium (Li); a second electrode disposed spaced apart from the first electrode; and a switching layer disposed between the first electrode and the second electrode and comprising a mixture of an insulator and lithium (Li), wherein the switching layer includes a first region in contact with the first electrode and A synaptic device is provided, including a second region in contact with the second electrode, wherein the second region has a higher lithium concentration than the first region.
  • the lithium concentration in the second region may range from about 10 at% to 40 at%.
  • the first electrode may include at least one of TiN, TiON, and TiO 2 .
  • the first electrode may include TiN.
  • the first electrode may include a solid electrolyte containing lithium (Li).
  • the solid electrolyte is, for example, at least one selected from the group consisting of LGPS (Li 10 GeP 2 S 12 ), LSPSCl (Li 9.54 Si 1.74 P 1.44 S 11.7 Cl 0.3 ), LPS, LiCl, and LLTO, or at least one of these. May contain combinations of the two.
  • the combination may include, for example, a combination of LPS and LiCl.
  • the LPS represents lithium phosphorus sulfide
  • the LiCl represents lithium chloride
  • the LLTO represents lithium lanthanum titanate.
  • the LLTO may have a perovskite structure.
  • the insulator may include at least one of HfO 2 , ZrO 2 , Al 2 O 3 , MgO, Y 2 O 3 , La 2 O 3 and Si 3 N 4 .
  • the switching layer may include a solid solution of the insulator (i.e., dielectric material) and lithium (Li).
  • the difference between the forming voltage and the set voltage of the synaptic device may be about 1.2 V or less.
  • the synaptic device may be a forming-free device.
  • a neuromorphic device including the above-described synaptic device is provided.
  • a method of manufacturing a synaptic device includes forming a first electrode capable of absorbing and releasing lithium (Li); forming a switching layer including a mixture of an insulator and lithium (Li) on the first electrode; and forming a second electrode on the switching layer, wherein the switching layer includes a first region in contact with the first electrode and a second region in contact with the second electrode, and the second region Provided is a method of manufacturing a synaptic device having a higher lithium concentration than the first region.
  • the lithium concentration in the second region may range from about 10 at% to 40 at%.
  • the first electrode may include at least one of TiN, TiON, and TiO 2 .
  • the first electrode may include TiN.
  • the first electrode may include a solid electrolyte containing lithium (Li).
  • the solid electrolyte is, for example, at least one selected from the group consisting of LGPS (Li 10 GeP 2 S 12 ), LSPSCl (Li 9.54 Si 1.74 P 1.44 S 11.7 Cl 0.3 ), LPS, LiCl, and LLTO, or at least one of these. May contain combinations of the two.
  • the combination may include, for example, a combination of LPS and LiCl.
  • the LPS represents lithium phosphorus sulfide
  • the LiCl represents lithium chloride
  • the LLTO represents lithium lanthanum titanate.
  • the LLTO may have a perovskite structure.
  • the switching layer can be formed using a co-sputtering method using the insulator target and the lithium (Li) target.
  • the sputter power for the lithium (Li) target may be about 10 W or more, and the sputter power for the insulator target may be about 100 W or more.
  • the insulator may include at least one of HfO 2 , ZrO 2 , Al 2 O 3 , MgO, Y 2 O 3 , La 2 O 3 and Si 3 N 4 .
  • the switching layer may include a solid solution of the insulator (i.e., dielectric material) and lithium (Li).
  • the forming voltage can be greatly reduced, and a synaptic device that is advantageous for reduced scaling and manufacturing (mass production) can be implemented through a simple structure. Additionally, according to embodiments of the present invention, it is possible to implement a synaptic device that can secure relatively excellent linearity and symmetry in conductance modulation characteristics.
  • synaptic devices can be used as artificial synapses that can replace biological synapses, and can be usefully used in neuromorphic devices (neuromorphic systems) and neural networks.
  • Figure 1 is a perspective view showing a synaptic device according to an embodiment of the present invention.
  • 2A to 2C are cross-sectional views for explaining a method of manufacturing a synaptic device according to an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating an exemplary co-sputtering method that can be applied to the method of manufacturing a synaptic device according to an embodiment of the present invention.
  • Figure 4 is a perspective view showing a synaptic device for testing manufactured according to an exemplary embodiment of the present invention.
  • 5 to 8 are graphs showing the results of X-ray photheelectron spectroscopy (XPS) analysis of a switching layer that can be applied to a synaptic device according to an embodiment of the present invention.
  • XPS X-ray photheelectron spectroscopy
  • Figure 9 is a graph showing the change in pristine current of a synaptic device depending on the material of the lower electrode (first electrode).
  • FIG. 10 is a graph showing the results of evaluating DC (direct current) voltage sweep characteristics for the synaptic device according to the comparative example described in FIG. 9.
  • FIG. 11 is a graph showing the results of evaluating DC voltage sweep characteristics for the synaptic device according to the embodiment described in FIG. 9.
  • Figure 12 is a graph showing current change characteristics according to voltage application of a synaptic device according to an embodiment of the present invention.
  • Figure 13 is a graph showing the results of measuring the change in the difference between the forming voltage and the set voltage of the synaptic device according to the sputter power for the Li target when forming the switching layer of the synaptic device according to an embodiment of the present invention.
  • Figure 14 is a graph showing the results of evaluating DC voltage sweep characteristics for a synaptic device according to an embodiment of the present invention.
  • Figure 15 is a diagram for explaining the switching mechanism of a synaptic device according to an embodiment of the present invention.
  • Figure 16 is a graph showing the results of evaluating set and reset operation characteristics while increasing the operating voltage (set voltage and reset voltage) for a synaptic device according to a switching cycle according to an embodiment of the present invention.
  • Figure 17 is a graph showing the results of evaluating set and reset operation characteristics while continuously increasing the operating voltage (set voltage and reset voltage) for a synaptic device according to an embodiment of the present invention.
  • Figures 18 and 19 are graphs showing the results of evaluating continuous resistance change characteristics according to repetitive voltage application to a synaptic device according to an embodiment of the present invention.
  • Figure 20 is a graph showing low voltage operation characteristics of a synaptic device according to an embodiment of the present invention.
  • FIG. 21 is a graph showing change characteristics of an alternating current (AC) pulse when a set operation occurs in FIG. 20.
  • FIG. 22 is a graph showing the change characteristics of the AC pulse when a reset operation occurs in FIG. 20.
  • Figure 23 is a graph showing high voltage operation characteristics of a synaptic device according to an embodiment of the present invention.
  • FIG. 24 is a graph showing the change characteristics of the AC pulse when the set operation occurs in FIG. 23.
  • FIG. 25 is a graph showing the change characteristics of the AC pulse when a reset operation occurs in FIG. 23.
  • Figure 26 is a graph showing the increase characteristics of conductance, that is, the potentiation characteristics, according to the intensity of applied voltage of a synaptic device according to an embodiment of the present invention.
  • Figure 27 is a graph showing the conductance reduction characteristic, that is, the weakening characteristic, according to the intensity of the applied voltage of the synaptic device according to an embodiment of the present invention.
  • Figure 28 is a graph showing the results of measuring the potentiation and depression characteristics of a synaptic device according to an embodiment of the present invention.
  • FIG. 29 is a graph obtained by calculation from the measurement data of FIG. 28 and showing the results of evaluating linearity for each strengthening and weakening operation.
  • Figure 30 is a waveform diagram showing a case where a separate read voltage is added during potentiation and depression operations of a synaptic device according to an embodiment of the present invention.
  • Figure 31 is a waveform diagram showing a case where the width of a program pulse is adjusted in the potentiation and depression operations of a synaptic device according to an embodiment of the present invention.
  • Figure 32 is a diagram showing the form of a paired pulse applied to a synaptic device to evaluate the paired pulse facilitation (PPF) characteristics of the synaptic device according to an embodiment of the present invention.
  • PPF paired pulse facilitation
  • Figure 33 is a graph showing the results of evaluating the paired pulse facilitation (PPF) characteristics of a synaptic device according to an embodiment of the present invention.
  • PPF paired pulse facilitation
  • Figure 34 is a conceptual diagram for explaining the synapse-mimicking characteristics of a synaptic device according to an embodiment of the present invention.
  • Figure 35 is a diagram showing a circuit configuration including a synaptic element according to an embodiment of the present invention.
  • Figure 36 is a circuit diagram showing a synaptic array device using a synaptic device according to an embodiment of the present invention.
  • connection used in this specification not only means that certain members are directly connected, but also includes indirectly connected members with other members interposed between them.
  • a member when a member is said to be located “on” another member in the present specification, this includes not only the case where a member is in contact with another member, but also the case where another member exists between the two members.
  • the term “and/or” includes any one and all combinations of one or more of the listed items.
  • terms such as “about” and “substantially” used in the specification herein are used in the sense of a range or close to the numerical value or degree, taking into account unique manufacturing and material tolerances, and to aid understanding of the present application. Precise or absolute figures provided for this purpose are used to prevent infringers from taking unfair advantage of the stated disclosure.
  • Figure 1 is a perspective view showing a synaptic device according to an embodiment of the present invention.
  • the synaptic device may be a resistive random access memory (RRAM) type device, and may be a device that uses the movement of lithium (Li) ions.
  • the lithium (Li) ion can act as a type of neurotransmitter.
  • the synaptic element includes a first electrode 10 capable of absorbing and releasing lithium (Li), a second electrode 30 disposed spaced apart from the first electrode 10, and the first electrode 10 and the second electrode ( 30) may include a switching layer 20 disposed between them.
  • the switching layer 20 may be referred to as a resistance change layer or variable resistance layer.
  • the switching layer 20 may include a mixture of an insulator (dielectric) and lithium (Li).
  • the thickness of the switching layer 20 may be, as a non-limiting example, about 10 to 100 nm or about 10 to 50 nm.
  • the switching layer 20 may include a first region 20a in contact with the first electrode 10 and a second region 20b in contact with the second electrode 30, and the second region 20b is It may have a higher lithium concentration (content) than the first region 20a.
  • the first electrode 10 may have the characteristic of absorbing lithium (Li) in the first region 20a of the switching layer 20 even when no voltage is applied to the synaptic element. This characteristic can be called a lithium scavenging characteristic. Accordingly, the first area 20a may have a lower lithium concentration (content) than the second area 20b.
  • the switching layer 20 is shown as including two clearly distinct regions, that is, first and second regions 20a and 20b, but this is an example, and lithium in the switching layer 20 Changes in concentration may occur gradually or stepwise.
  • the lithium concentration may gradually or stepwise decrease from the lower surface of the switching layer 20, that is, the surface in contact with the first electrode 10, to the upper surface, that is, the surface in contact with the second electrode 30. there is.
  • the lower region of the switching layer 20 may have a relatively low lithium concentration
  • the upper region of the switching layer 20 may have a relatively high lithium concentration.
  • the first area 20a is indicated as Li-Poor
  • the second area 20b is indicated as Li-Rich.
  • Li-Poor displayed in the first area 20a may mean that the first area 20a has a lower lithium concentration than the second area 20b
  • Li-Rich displayed in the second area 20b may mean that the first area 20a has a lower lithium concentration than the second area 20b. This may mean that the second area 20b has a higher lithium concentration than the first area 20a.
  • a conductive filament CF may be formed in the second region 20b of the switching layer 20.
  • the conductive filament CF may be formed within the second area 20b or within the second area 20b and an area adjacent thereto.
  • the conductive filament (CF) may be formed in a vertical or vertical direction.
  • the conductive filament (CF) may include or be composed of lithium (Li) atoms.
  • the conductive filament CF may be in contact with the second electrode 30 and may have a shape extending from the second electrode 30 side to the first electrode 10 side.
  • the conductive filament CF may have a structure that connects the second electrode 30 and the first region 20a.
  • the conductive filament (CF) may be formed through a predetermined forming process. Here, the case where one conductive filament (CF) is formed is shown, but a plurality of conductive filaments (CF) may be formed.
  • a conduction path connecting the first electrode 10 and the conductive filament (CF) is created, strengthened, weakened, and As it disappears, the resistance of the switching layer 20 may change. Creation, strengthening, weakening, and extinction of the conduction path may be achieved by movement of lithium (Li) ions within the switching layer 20. The movement of the lithium (Li) ions may occur within the first area 20a or within the first area 20a and an area adjacent thereto. Also, at this time, the first electrode 10 may absorb or release lithium (Li). When the first electrode 10 releases lithium (Li) and a conductive path connecting the first electrode 10 and the conductive filament (CF) is formed, the resistance of the switching layer 20 may be lowered. Conversely, if the first electrode 10 absorbs lithium (Li) and the conductive path connecting the first electrode 10 and the conductive filament (CF) disappears, the resistance of the switching layer 20 may increase.
  • the forming process is to apply a high voltage (forming voltage) to the device to make the initial device drivable, thereby causing soft breakdown (i.e., insulation breakdown).
  • forming voltage a high voltage
  • the strength of the forming voltage is It can be significantly higher than the operating voltage (set/reset voltage).
  • set/reset voltage the operating voltage
  • existing RRAM-based devices require a fairly high forming voltage and therefore have various problems and limitations in this regard. For example, in order to apply a high forming voltage, it may be required to complicate the structure of the device. Therefore, manufacturing the device becomes difficult and scaling may be disadvantageous.
  • the durability of the device may be reduced due to the high forming voltage.
  • the forming voltage required for operation of the device can be lowered.
  • forming-free characteristics can be implemented. Therefore, according to an embodiment of the present invention, it is possible to implement a synaptic device that has a low forming voltage or forming-free characteristics, is advantageous for scaling and manufacturing/mass production through a simple structure, and has excellent durability.
  • the synaptic device according to an embodiment of the present invention may have relatively excellent linearity and symmetry in conductance modulation characteristics. In particular, when appropriate operating conditions are set, the linearity and symmetry can be improved.
  • the lithium concentration in the second region 20b of the switching layer 20 may range from about 10 at% to 40 at%.
  • the lithium concentration in the second region 20b may range from about 20 at% to 40 at%. This lithium concentration may be significantly higher than that resulting from simple doping.
  • the switching layer 20 may be composed of or include a solid solution of the insulator and lithium (Li).
  • the solid solution may be a type of mixture of the insulator and lithium (Li).
  • the insulator may be hafnium (Hf) oxide or may include hafnium (Hf) oxide.
  • the hafnium (Hf) oxide may be HfO 2 .
  • the switching layer 20 may be composed of or include a solid solution of HfO 2 and lithium (Li).
  • the hafnium (Hf) oxide it can have an appropriate leakage current level, and this characteristic can be relatively advantageous in synaptic devices.
  • the material of the insulator is not limited to hafnium (Hf) oxide and may change depending on the case. On the other hand, since lithium (Li) has a fairly high mobility, the operation speed of the device can be improved in this regard.
  • the material of the insulator of the switching layer 20 is not limited to HfO 2 , and any material that is a nonconductor and has a dielectric constant (K) similar to or lower than that of HfO 2 can be applied as the material of the insulator. It may be possible.
  • the insulator may include at least one of HfO 2 , ZrO 2 , Al 2 O 3 , MgO, Y 2 O 3 , La 2 O 3 and Si 3 N 4 .
  • the switching layer 20 may include a solid solution of the insulator (i.e., dielectric material) and lithium (Li).
  • the forming voltage can be lowered, so the difference between the forming voltage and the set voltage can be reduced.
  • the difference between the forming voltage and the set voltage of the synaptic device may be about 1.2 V or less.
  • the difference between the forming voltage and the set voltage of the synaptic device may be about 1.1 V or less or about 1 V or less.
  • the difference between the forming voltage and the set voltage may be about 0 V or more.
  • the absolute value of the forming voltage may be about 1.5 V to 2.3 V, and the absolute value of the set voltage may be about 0.8 V to 1.3 V.
  • a synaptic device having forming-free characteristics may be implemented.
  • the first electrode 10 may be made of a material capable of reversible absorption and release of lithium (Li).
  • the first electrode 10 may include at least one of TiN, TiON, and TiO 2 .
  • TiN can have excellent electrical conductivity and excellent lithium (Li) absorption and release characteristics. Accordingly, it may be desirable for the first electrode 10 to include TiN or be made of TiN.
  • the first electrode 10 may include or be composed of a solid electrolyte having Li scavenging properties.
  • the first electrode 10 may include a solid electrolyte containing lithium (Li).
  • the solid electrolyte is, for example, at least one selected from the group consisting of LGPS (Li 10 GeP 2 S 12 ), LSPSCl (Li 9.54 Si 1.74 P 1.44 S 11.7 Cl 0.3 ), LPS, LiCl, and LLTO, or at least one of these. May contain combinations of the two.
  • the combination may include, for example, a combination of LPS and LiCl.
  • the LPS represents lithium phosphorus sulfide
  • the LiCl represents lithium chloride
  • the LLTO represents lithium lanthanum titanate.
  • the LLTO may have a perovskite structure.
  • the second electrode 30 may be an electrode that does not substantially absorb lithium (Li).
  • the second electrode 30 may include at least one of various metals or metal compounds.
  • the second electrode 30 may include a noble metal such as platinum (Pt).
  • the second electrode 30 may be a Pt layer.
  • the material of the second electrode 30 is not limited to platinum (Pt) and may vary in various ways.
  • the second electrode 30 may have a single-layer structure or a multi-layer structure.
  • 2A to 2C are cross-sectional views for explaining a method of manufacturing a synaptic device according to an embodiment of the present invention.
  • a first electrode 10 capable of absorbing and releasing lithium (Li) can be formed on a predetermined substrate (not shown).
  • the first electrode 10 may be made of a material capable of reversible absorption and release of lithium (Li).
  • the first electrode 10 may include at least one of TiN, TiON, and TiO 2 .
  • TiN can have excellent electrical conductivity and excellent lithium (Li) absorption and release characteristics. Accordingly, it may be desirable for the first electrode 10 to include TiN or be made of TiN.
  • the first electrode 10 may include or be composed of a solid electrolyte having Li scavenging properties.
  • the first electrode 10 may include a solid electrolyte containing lithium (Li).
  • the solid electrolyte is, for example, at least one selected from the group consisting of LGPS (Li 10 GeP 2 S 12 ), LSPSCl (Li 9.54 Si 1.74 P 1.44 S 11.7 Cl 0.3 ), LPS, LiCl, and LLTO, or at least one of these. May contain combinations of the two.
  • the combination may include, for example, a combination of LPS and LiCl.
  • the LPS represents lithium phosphorus sulfide
  • the LiCl represents lithium chloride
  • the LLTO represents lithium lanthanum titanate.
  • the LLTO may have a perovskite structure.
  • the first electrode 10 may be formed, for example, by a physical vapor deposition (PVD) method such as an electron beam evaporation (E-beam evaporation) method.
  • PVD physical vapor deposition
  • E-beam evaporation electron beam evaporation
  • the thickness of the first electrode 10 may be, as a non-limiting example, approximately 50 to 500 nm.
  • the first electrode 10 may be formed to have a thickness of about 100 nm.
  • the formation method and thickness conditions of the first electrode 10 are not limited to the above and may vary in various ways.
  • a switching layer 20 containing a mixture of an insulator (dielectric) and lithium (Li) may be formed on the first electrode 10.
  • the switching layer 20 may include a first region 20a in contact with the first electrode 10 and a second region 20b disposed on the first region 20a.
  • the first area 20a may be disposed between the first electrode 10 and the second area 20b.
  • the second area 20b may have a higher lithium concentration (content) than the first area 20a.
  • the first electrode 10 may have the characteristic of absorbing lithium (Li) in the first region 20a of the switching layer 20 even when no voltage is applied to the synaptic element. Accordingly, the first area 20a may have a lower lithium concentration (content) than the second area 20b.
  • the change in lithium concentration within the switching layer 20 may be gradual or stepwise.
  • the lithium concentration may gradually or stepwise decrease from the lower surface of the switching layer 20, that is, the surface in contact with the first electrode 10, to the upper surface. Accordingly, the lower region of the switching layer 20 may have a relatively low lithium concentration, and the upper region of the switching layer 20 may have a relatively high lithium concentration.
  • the switching layer 20 may be composed of or include a solid solution of the insulator and lithium (Li).
  • the insulator may be hafnium (Hf) oxide or may include hafnium (Hf) oxide.
  • the hafnium (Hf) oxide may be HfO 2 .
  • the switching layer 20 may be composed of or include a solid solution of HfO 2 and lithium (Li).
  • the hafnium (Hf) oxide it can have an appropriate leakage current level, and this characteristic can be relatively advantageous in synaptic devices.
  • the material of the insulator is not limited to hafnium (Hf) oxide and may change depending on the case.
  • the material of the insulator of the switching layer 20 is not limited to HfO 2 , and any material that is a nonconductor and has a dielectric constant (K) similar to or lower than that of HfO 2 can be applied as the insulator material.
  • the insulator may include at least one of HfO 2 , ZrO 2 , Al 2 O 3 , MgO, Y 2 O 3 , La 2 O 3 and Si 3 N 4 .
  • the switching layer 20 may include a solid solution of the insulator (i.e., dielectric material) and lithium (Li).
  • the lithium concentration of the second region 20b of the switching layer 20 may be, for example, in the range of about 10 at% to 40 at%.
  • the lithium concentration in the second region 20b may range from about 20 at% to 40 at%, for example. This lithium concentration may be significantly higher than that resulting from general doping.
  • the switching layer 20 uses a co-sputtering method using the insulator target (first target) and the lithium (Li) target (second target). It can be formed by doing so.
  • the sputter power for the lithium (Li) target (second target) may be about 10 W or more or about 40 W or more
  • the insulator target (first target) may be The sputter power may be about 100 W or more.
  • the sputter power for the lithium (Li) target (second target) may be about 10 to 150 W or about 40 to 150 W
  • the sputter power for the insulator target (first target) may be about 100 to 250 W. It may be around W.
  • the sputter power for the lithium (Li) target (second target) may be lower than the sputter power for the insulator target (first target).
  • the switching layer 20 in which the insulator and lithium (Li) are mixed at an appropriate ratio can be more easily formed.
  • the second electrode 30 can be formed on the switching layer 20.
  • the second electrode 30 may contact the upper surface of the second region 20b of the switching layer 20.
  • the second electrode 30 may be an electrode that does not substantially absorb lithium (Li).
  • the second electrode 30 may include at least one of various metals or metal compounds.
  • the second electrode 30 may include a noble metal such as platinum (Pt).
  • the second electrode 30 may be a Pt layer.
  • the material of the second electrode 30 is not limited to platinum (Pt) and may vary in various ways.
  • the second electrode 30 may have a single-layer structure, but in some cases, it may have a multi-layer structure.
  • the second electrode 30 may be formed using, for example, a sputtering method.
  • the thickness of the second electrode 30 may be, as a non-limiting example, approximately 50 to 500 nm.
  • the second electrode 30 may be formed to have a thickness of about 100 nm.
  • the width of the second electrode 30 may be, for example, several nm to hundreds of ⁇ m, or several tens of nm to hundreds of ⁇ m.
  • the formation method, thickness condition, and width condition of the second electrode 30 are not limited to the above and may vary in various ways.
  • the synaptic device of FIG. 2C may be substantially the same as or similar to the synaptic device described in FIG. 1. Therefore, everything described about the synaptic device with reference to FIG. 1 can also be applied to the synaptic device of FIG. 2C.
  • FIG. 3 is a diagram illustrating an exemplary co-sputtering method that can be applied to the method of manufacturing a synaptic device according to an embodiment of the present invention.
  • a co-sputtering method may be used to form a switching layer when manufacturing a synaptic device according to an embodiment of the present invention.
  • the substrate on which the first electrode 10 is formed is placed in the chamber CH1, and an insulator target (first target) T1 and a lithium (Li) target (second By simultaneously sputtering a target (T2), a switching layer (20 in FIG. 2B) in which the insulator and lithium (Li) are mixed can be formed on the exposed surface of the first electrode 10.
  • argon (Ar) gas may be used to form plasma.
  • reference number H1 indicates a substrate holder.
  • Figure 4 is a perspective view showing a synaptic device for testing manufactured according to an exemplary embodiment of the present invention.
  • a synaptic device for testing manufactured according to an exemplary embodiment of the present invention may include a first electrode 11, a switching layer 21, and a second electrode 31.
  • a switching layer 21 may be formed on the first electrode 11, and the switching layer 21 may include a first region 21a and a second region 21b.
  • the second electrode 31 may be formed on the switching layer 21.
  • the second electrode 31 may be formed in plural pieces. At least some of the plurality of second electrodes 31 may have different sizes (widths).
  • the synaptic device for testing can be formed in the same manner as described with reference to FIGS. 2A to 2C.
  • Table 1 summarizes exemplary process conditions that can be applied when manufacturing the synaptic device for testing described above.
  • Table 1 includes process conditions for co-sputtering when forming a switching layer by a co-sputtering method using both a Li target and a HfO 2 target. Additionally, Table 1 includes sputtering conditions for a Pt target and width (diameter) conditions of the second electrode when forming a second electrode of Pt on the switching layer. Among the values in Table 1, the bold and underlined values correspond to the main process conditions. However, the specific process conditions presented in Table 1 are exemplary, and when manufacturing actual devices, the process conditions may vary.
  • the Li content in the manufactured switching layer may be about 23.6 at%, and the Hf content may be about 23.08 at%. Additionally, in this case, the O (oxygen) content in the switching layer may be about 49.56 at%. Additionally, the content of C (carbon) as an impurity included in the switching layer may be about 3.75 at%.
  • 5 to 8 are graphs showing the results of X-ray photheelectron spectroscopy (XPS) analysis of a switching layer that can be applied to a synaptic device according to an embodiment of the present invention.
  • the switching layer was manufactured by a co-sputtering method in which the sputter power for the Li target was set to 50 W and the sputter power for the HfO 2 target was set to 150 W.
  • the process conditions of the co-sputtering were as shown in Table 1.
  • Figure 5 shows the results of XPS analysis of Li-related chemical bonds and materials. From the results in FIG. 5, it can be confirmed that a large amount of unoxidized Li is contained in the switching layer. Unoxidized Li can play an important role in device operation in synaptic devices. Meanwhile, Figure 6 shows the XPS analysis results for Hf-related chemical bonds and materials, Figure 7 shows the XPS analysis results for C-related chemical bonds and materials, and Figure 8 shows the XPS analysis results for O-related chemical bonds and materials. Shows the analysis results.
  • Figure 9 is a graph showing the change in pristine current of a synaptic device depending on the material of the lower electrode (first electrode).
  • the synaptic device has a Pt/Li:HfO 2 /Pt structure.
  • the lower electrode (first electrode) is TiN the synaptic device has a TiN/Li:HfO 2 /Pt structure.
  • Li:HfO 2 is a constituent material of the switching layer and means a mixture of HfO 2 and Li.
  • the case where the lower electrode (first electrode) is TiN may correspond to an embodiment of the present invention.
  • the case where the lower electrode (first electrode) is Pt corresponds to the comparative example.
  • the initial current (pristine current) refers to the current (current between the first and second electrodes) before the forming process, and at this time, the read voltage was 0.1 V.
  • the synaptic device (using a TiN lower electrode) according to the above embodiment has a significantly lower initial current (pristine current) and the dispersion of the initial current is also significantly smaller than the synaptic device (using a Pt lower electrode) according to the comparative example. You can check it.
  • the initial current of the synaptic device according to the above example was reduced by about 10 6 times compared to the initial current of the synaptic device according to the comparative example. This is believed to be because the TiN lower electrode absorbs Li from the switching layer (i.e., Li:HfO 2 layer) even without applying a voltage to the device, thereby ensuring appropriate insulation characteristics in some regions (lower regions) of the switching layer. do.
  • the TiN lower electrode may have the lithium scavenging characteristics described above.
  • FIG. 10 is a graph showing the results of evaluating DC (direct current) voltage sweep characteristics for a synaptic device (Pt/Li:HfO 2 /Pt structure) according to the comparative example described in FIG. 9.
  • FIG. 11 is a graph showing the results of evaluating DC voltage sweep characteristics for a synaptic device (TiN/Li:HfO 2 /Pt structure) according to the embodiment described in FIG. 9.
  • the synaptic device (Pt/Li:HfO 2 /Pt structure) according to the comparative example does not exhibit resistance change characteristics appropriate for a memory device.
  • the synaptic device (TiN/Li:HfO 2 /Pt structure) according to the above embodiment exhibits relatively excellent resistance change characteristics as a memory device.
  • Figure 12 is a graph showing current change characteristics according to voltage application of a synaptic device according to an embodiment of the present invention.
  • a forming voltage is applied to a synaptic device (TiN/Li:HfO 2 /Pt structure) according to an embodiment of the present invention to cause soft breakdown (i.e., insulation breakdown).
  • a forming process can be performed to generate Through this forming process, a conductive filament (CF) may be formed in the switching layer.
  • CF conductive filament
  • Figure 13 is a graph showing the results of measuring the change in the difference between the forming voltage and the set voltage of the synaptic device according to the sputter power for the Li target when forming the switching layer of the synaptic device according to an embodiment of the present invention.
  • each of the forming voltage and the set voltage is expressed as a positive (+) value, that is, as an absolute value.
  • the results were measured when the sputter power for the Li target was 10 W, 30 W, and 50 W.
  • the sputter power for the HfO 2 target was 150 W.
  • the sputter power for the Li target is 50 W
  • the difference between the forming voltage level and the set voltage level is significantly lowered to about 0.94 V.
  • the sputter power for the Li target is about 10 W or more or about 40 W or more
  • the sputter power for the insulator (e.g., HfO 2 ) target is It may be desirable to have about 100 W or more.
  • the forming voltage required for operation of the device can be lowered, and in some cases, forming-free characteristics can be implemented.
  • Figure 14 is a graph showing the results of evaluating DC voltage sweep characteristics for a synaptic device according to an embodiment of the present invention.
  • a synaptic device may exhibit memory operation characteristics and synaptic behavior at a low voltage level.
  • Figure 15 is a diagram for explaining the switching mechanism of a synaptic device according to an embodiment of the present invention.
  • lithium is generated from the first electrode (lower electrode) 10.
  • (Li) can be released, and when a positive (+) voltage is applied to the second electrode 30, the first electrode 10 can absorb lithium (Li).
  • a positive (+) voltage is applied to the first electrode 10
  • lithium (Li) may be released from the first electrode 10
  • a negative (-) voltage may be released from the first electrode 10.
  • the first electrode 10 can absorb lithium (Li).
  • a conduction path connecting the first electrode 10 and the conductive filament (CF) is created, strengthened, weakened, and As it disappears (decomposes), the electrical conductivity (conductance) of the switching layer 20 may change. Creation, strengthening, weakening, and extinction (decomposition) of the conductive path may be achieved by the movement of lithium (Li) ions within the switching layer 20. When the first electrode 10 releases lithium (Li) to form a conductive path connecting the first electrode 10 and the conductive filament (CF), the conductance of the switching layer 20 may increase.
  • the conductance of the switching layer 20 may be lowered.
  • the conductance can be analogously strengthened or weakened.
  • Figure 16 is a graph showing the results of evaluating set and reset operation characteristics while increasing the operating voltage (set voltage and reset voltage) for a synaptic device according to a switching cycle according to an embodiment of the present invention.
  • Figure 17 is a graph showing the results of evaluating set and reset operation characteristics while continuously increasing the operating voltage (set voltage and reset voltage) for a synaptic device according to an embodiment of the present invention.
  • the synaptic device according to the embodiment can exhibit memory behavior.
  • the ON/OFF current ratio of the synaptic device may be about 10 2 or more.
  • Figures 18 and 19 are graphs showing the results of evaluating continuous resistance change characteristics according to repetitive voltage application to a synaptic device according to an embodiment of the present invention.
  • the conductance of the synaptic device may increase continuously, that is, analogically. This may mean the 'potentiation' characteristic of the synaptic device due to an analog increase in conductance.
  • a synaptic device according to an embodiment may exhibit the strengthening characteristics (synaptic behavior) at a relatively low voltage level.
  • the conductance of the synaptic device may decrease continuously, that is, analogically. This may mean a 'depression' characteristic of the synaptic device due to an analog decrease in conductance.
  • a synaptic device according to an embodiment may exhibit the weakening characteristic (synaptic behavior) at a relatively low voltage level.
  • FIG. 20 is a graph showing low voltage operation characteristics of a synaptic device according to an embodiment of the present invention.
  • FIG. 21 is a graph showing change characteristics of an alternating current (AC) pulse when a set operation occurs in FIG. 20.
  • FIG. 22 is a graph showing the change characteristics of the AC pulse when a reset operation occurs in FIG. 20.
  • AC alternating current
  • the speed of the set operation was about 240 ⁇ s, and as can be seen in FIG. 22, the speed of the reset operation was about 49 ms.
  • FIG. 23 is a graph showing high voltage operation characteristics of a synaptic device according to an embodiment of the present invention.
  • FIG. 24 is a graph showing the change characteristics of the AC pulse when the set operation occurs in FIG. 23.
  • FIG. 25 is a graph showing the change characteristics of the AC pulse when a reset operation occurs in FIG. 23.
  • the speed of the set operation was about 34 ns, and as can be seen in FIG. 25, the speed of the reset operation was about 26 ⁇ s.
  • Each of these set/reset operation speeds is faster than the set/reset operation speeds in FIGS. 21 and 22.
  • the synaptic device according to the embodiment of the present invention can easily form a thin conductive path between the first electrode and the conductive filament and can be easily disassembled, so that memory behavior can be achieved even with low voltage and short pulses. You can check what is possible. Additionally, in order to exhibit analog memory characteristics, a certain degree of incomplete set/reset may be required.
  • Figure 26 is a graph showing the increase characteristics of conductance, that is, the potentiation characteristics, according to the intensity of applied voltage of a synaptic device according to an embodiment of the present invention.
  • the pulse width of the applied voltage was 10 ⁇ s.
  • Figure 27 is a graph showing the conductance reduction characteristic, that is, the weakening characteristic, according to the intensity of the applied voltage of the synaptic device according to an embodiment of the present invention.
  • the pulse width of the applied voltage was 10 ⁇ s.
  • the conductance shows a depression characteristic in which the conductance decreases generally linearly.
  • Figure 28 is a graph showing the results of measuring the potentiation and depression characteristics of a synaptic device according to an embodiment of the present invention.
  • programming and reading were performed with the same voltage. That is, a strengthening operation for the synaptic element was repeatedly performed using the same first voltage, and a read operation was also performed using the first voltage. Additionally, a weakening operation on the synaptic element was repeatedly performed using the same second voltage, and a read operation was also performed using the second voltage.
  • FIG. 29 is a graph obtained by calculation from the measurement data of FIG. 28 and showing the results of evaluating linearity for each strengthening and weakening operation.
  • the linearity coefficient u P for the strengthening operation is approximately ⁇ 0, indicating almost complete linearity.
  • the linearity coefficient u D for the weakening operation was approximately ⁇ 3.6, showing a somewhat lower degree of linearity than the strengthening operation.
  • the width of the program voltage pulse during the strengthening operation and the width of the program voltage pulse during the weakening operation can be controlled, and the non-linearity of the weakening operation graph according to reset can be reduced. It can be improved.
  • Figure 30 is a waveform diagram showing a case where a separate read voltage is added during potentiation and depression operations of a synaptic device according to an embodiment of the present invention.
  • a program voltage having a negative intensity can be used, and a read voltage at a level relatively lower than the program voltage can be used.
  • a program voltage having a positive intensity may be used, and a read voltage of a relatively lower level than the program voltage may be used.
  • the strength of the read voltage used in the strengthening and weakening operations may be the same. By adding such a read voltage pulse, the asymmetry between the graph of the strengthening operation and the graph of the weakening operation as shown in FIGS. 28 and 29 can be improved. Therefore, according to an embodiment of the present invention, a synaptic device having excellent symmetry between strengthening and weakening operation characteristics can be implemented.
  • the intensity and polarity of the read voltage shown in FIG. 30 are exemplary and can be adjusted as needed.
  • Figure 31 is a waveform diagram showing a case where the width of a program pulse is adjusted in the potentiation and depression operations of a synaptic device according to an embodiment of the present invention.
  • the difference in operation speed between reset and set can be controlled by controlling the width of the program voltage pulse during the strengthening operation and the width of the program voltage pulse during the weakening operation differently. and the nonlinearity of the weakening motion graph due to reset can be improved.
  • the difference between reset and set operation speeds can be controlled, and as a result, the weakening operation graph Nonlinearity can be improved. Therefore, according to an embodiment of the present invention, a synaptic device having excellent linearity in both strengthening and weakening operation characteristics can be implemented.
  • the waveform of the pulse shown in FIG. 31 is exemplary and may vary as needed.
  • Figure 32 is a diagram showing the form of a paired pulse applied to a synaptic device to evaluate the paired pulse facilitation (PPF) characteristics of the synaptic device according to an embodiment of the present invention.
  • PPF paired pulse facilitation
  • the overlap area of the two pulses may increase.
  • the overlap area may be reduced.
  • Figure 33 is a graph showing the results of evaluating the paired pulse facilitation (PPF) characteristics of a synaptic device according to an embodiment of the present invention.
  • PPF paired pulse facilitation
  • synaptic strength (weight) (%) tends to decrease.
  • Figure 34 is a conceptual diagram for explaining the synapse-mimicking characteristics of the synaptic device (S10) according to an embodiment of the present invention.
  • the synaptic element (S10) when configuring a synapse, which is a connection between a pre-neuron and a post-neuron, in a circuit, the synaptic element (S10) according to an embodiment of the present invention is applied. can do.
  • a pre-neuron can input a pre-spike signal to a synapse, and a synapse can transmit a predetermined synaptic signal to a post-neuron.
  • a post-neuron can generate a post-spike signal.
  • the synaptic element Similar to how a synapse connects a pre-neuron and a post-neuron, the synaptic element (S10) connects a pre-synaptic neuron circuit and a post-synaptic neuron circuit. It can play a role in connecting (post-synaptic neuron circuit).
  • a circuit diagram of this configuration may be as shown in FIG. 35.
  • Figure 35 is a diagram showing a circuit configuration including a synaptic element (S10) according to an embodiment of the present invention.
  • the first electrode 10 of the synaptic element S10 may be connected to a pre-synaptic neuron circuit N1.
  • the second electrode 30 of the synaptic element S10 may be connected to a post-synaptic neuron circuit N2.
  • a pre-spike signal may be applied to the first electrode 10 from the pre-synaptic neuron circuit (N1), and a synaptic signal may be applied to the first electrode 10 through the second electrode 30.
  • signal that is, post-synaptic current
  • a post-spike signal can arise from a post-synaptic neuron circuit (N2).
  • potentiation or depression of the synaptic element S10 may occur.
  • Figure 36 is a circuit diagram showing a synaptic array device using the synaptic device (S10) according to an embodiment of the present invention.
  • a plurality of synaptic elements S10 may be arranged to form a plurality of columns and a plurality of rows.
  • a plurality of first wires W10 may be arranged, and a plurality of second wires W20 may be arranged to intersect therewith, and a synaptic element may be installed at the intersection of the first wire W10 and the second wire W20.
  • S10) may be provided.
  • the plurality of first wires W10 may be connected to the first electrode of the synaptic element S10, and the plurality of second wires W20 may be connected to the second electrode of the synaptic element S10.
  • the first wire (W10) may be connected to a pre-synaptic neuron circuit (N10), and the second wire (W20) may be connected to a post-synaptic neuron circuit (N20).
  • N10 pre-synaptic neuron circuit
  • N20 post-synaptic neuron circuit
  • a pre-spike signal may be applied from the pre-synaptic neuron circuit N10 to the first electrode of the synaptic element S10 through the first wire W10.
  • a synaptic signal that is, a post-synaptic current, may flow into the post-synaptic neuron circuit (N20) through the second electrode of the synaptic element (S10).
  • Post-spike signals can arise from a post-synaptic neuron circuit (N20).
  • a neuromorphic device and system applying the synaptic device according to the above-described embodiment can be constructed.
  • the neuromorphic device may include a complementary metal-oxide-semiconductor (CMOS) peripheral circuit connected to the synaptic device.
  • CMOS peripheral circuit may include a pre-synaptic neuron circuit and a post-synaptic neuron circuit.
  • the synaptic element is according to an embodiment of the present invention and may have, for example, an array structure as described in FIG. 36.
  • the configuration of neuromorphic devices and systems using synaptic devices is well known, so detailed description thereof will be omitted.
  • the forming voltage can be lowered, and a synaptic device that is advantageous for reduced scaling and manufacturing (mass production) and has excellent durability can be implemented through a simple structure.
  • a synaptic device with forming-free characteristics can be implemented, and in this case, significant effects such as improved durability and reduced scaling can be achieved.
  • by adjusting the size of the electrode (first electrode and/or second electrode) of the synaptic device according to embodiments of the present invention off-current characteristics or power consumption characteristics can be controlled. It is expected that it will be possible. Therefore, synaptic devices according to embodiments can be used as artificial synapses that can replace biological synapses, and can be usefully used in neuromorphic devices (neuromorphic systems) and neural networks.
  • Second electrode CF Conductive filament
  • N1 Pre-synaptic neuron circuit
  • N2 Post-synaptic neuron circuit
  • N10 Pre-synaptic neuron circuit
  • N20 Post-synaptic neuron circuit
  • W10 1st wiring
  • W20 2nd wiring

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Abstract

Sont divulgués un dispositif synaptique, son procédé de fabrication et un dispositif neuromorphique comprenant un dispositif synaptique. Le dispositif synaptique divulgué peut être pourvu d'une première électrode permettant d'absorber et de libérer du lithium (Li), d'une seconde électrode disposée de manière à être espacée de la première électrode et d'une couche de commutation disposée entre la première électrode et la seconde électrode et comprenant un mélange d'un isolant et de lithium (Li), la couche de commutation pouvant comprendre une première région en contact avec la première électrode et une seconde région en contact avec la seconde électrode, et la seconde région pouvant avoir une concentration en lithium supérieure à celle de la première région. La concentration en lithium dans la seconde région peut être comprise entre environ 10 % atomique et 40 % atomique.
PCT/KR2023/012887 2022-09-28 2023-08-30 Dispositif synaptique, son procédé de fabrication et dispositif neuromorphique comprenant un dispositif synaptique WO2024071701A2 (fr)

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