WO2024070337A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024070337A1
WO2024070337A1 PCT/JP2023/030103 JP2023030103W WO2024070337A1 WO 2024070337 A1 WO2024070337 A1 WO 2024070337A1 JP 2023030103 W JP2023030103 W JP 2023030103W WO 2024070337 A1 WO2024070337 A1 WO 2024070337A1
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Prior art keywords
layer
internal electrode
electrode
electrode layer
laminate
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PCT/JP2023/030103
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English (en)
French (fr)
Japanese (ja)
Inventor
幸祐 浦谷
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to CN202380063917.3A priority Critical patent/CN119816908A/zh
Priority to JP2024549873A priority patent/JP7838661B2/ja
Publication of WO2024070337A1 publication Critical patent/WO2024070337A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • Patent Document 1 describes a technology for preventing this dielectric breakdown by forming at least a portion of the area near the edge of the internal electrode of the dielectric layer from a dielectric ceramic that has a higher withstand voltage than other areas.
  • the thickness of the dielectric layers in multilayer ceramic capacitors is becoming thinner.
  • the insulation resistance value decreases.
  • the internal electrodes are structurally prone to bending. This causes the thickness of the dielectric layers to decrease locally, making insulation breakdown more likely to occur. Therefore, the objective of the present invention is to provide a multilayer ceramic capacitor in which the occurrence of insulation breakdown is further suppressed.
  • the multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the lamination direction and the width direction, and an external electrode provided on the first end surface and the second end surface
  • the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is drawn out to the first end surface, the second internal electrode layer is drawn out to the second end surface, the external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the first end surface side is a region where the first internal electrode layers do not overlap with each other in the lamination direction, and the second end surface side is a region where the
  • the present invention provides a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed.
  • FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention
  • 2 is a cross-sectional view taken along line II in FIG. 1.
  • 2 is a cross-sectional view taken along line II-II of FIG. 1.
  • 2 is a diagram showing a portion of an LT cross section of the multilayer ceramic capacitor of the present embodiment.
  • FIG. 2 is a diagram showing a portion of a WT cross section of the multilayer ceramic capacitor of the present embodiment.
  • FIG. 11 is a diagram showing a portion of a WT cross section of another configuration of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. FIG. 2 is a plan view of a ceramic green sheet according to the embodiment.
  • FIG. 11 is a plan view of a ceramic green sheet having another configuration in the present embodiment.
  • 4A and 4B are diagrams showing LT cross sections of laminated ceramic green sheets.
  • FIG. 13 is a diagram showing the results of a high-temperature load reliability test.
  • Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of the present embodiment.
  • the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20.
  • the L direction is the length direction L of the multilayer ceramic capacitor 1.
  • the W direction is the width direction W of the multilayer ceramic capacitor 1.
  • the T direction is the stacking direction T of the multilayer ceramic capacitor 1.
  • the cross section shown in FIG. 2 is called an LT cross section, and the cross section shown in FIG. 3 is called a WT cross section.
  • the length direction L, the width direction W, and the stacking direction T do not necessarily have to be perpendicular to each other.
  • the length direction L, the width direction W, and the stacking direction T may intersect each other.
  • the laminate 2 has a substantially rectangular parallelepiped shape.
  • the laminate 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63.
  • the main surface 61 is a surface facing the stacking direction T.
  • the end surface 62 is a surface facing the length direction L.
  • the side surface 63 is a surface facing the width direction W.
  • One of the two main surfaces 61 is a first main surface 61a, and the other is a second main surface 61b.
  • One of the two end surfaces 62 is a first end surface 62a, and the other is a second end surface 62b.
  • One of the two side surfaces 63 is a first side surface 63a, and the other is a second side surface 63b.
  • the second main surface 61b and the first side surface 63a are shown in FIG. 1.
  • the ridges and corners of the laminate 2 are preferably rounded.
  • a ridge is a portion where two surfaces of the laminate 2 intersect.
  • a corner is a portion where three surfaces of the laminate 2 intersect.
  • the size of the laminate 2 is not particularly limited.
  • the laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2.
  • Fig. 2 is a cross-sectional view of the laminated ceramic capacitor 1 shown in Fig. 1 taken along line II.
  • Fig. 2 shows an LT cross-section of the laminated ceramic capacitor 1.
  • the laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in a stacking direction T.
  • the laminate 2 is divided into an inner layer portion 53 and two outer layer portions 54 in the stacking direction T.
  • the outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b.
  • the first outer layer portion 54a and the second outer layer portion 54b are located at positions sandwiching the inner layer portion 53 in the stacking direction T.
  • the inner layer portion 53 a plurality of dielectric layers 4 and a plurality of internal electrode layers 10 are arranged.
  • the plurality of internal electrode layers 10 face each other via the dielectric layer 4. Therefore, a capacitance is formed in the inner layer portion 53. Therefore, the inner layer portion 53 is the portion of the laminate 2 that essentially functions as a capacitor. For this reason, the inner layer portion 53 is also called the effective portion.
  • the first outer layer portion 54a is a portion of the outer layer portion 54 located on the side of the first main surface 61a of the laminate 2.
  • the second outer layer portion 54b is a portion of the outer layer portion 54 located on the side of the second main surface 61b of the laminate 2.
  • the first outer layer portion 54a is a portion between the internal electrode layer 10 closest to the first main surface 61a among the multiple internal electrode layers 10 and the first main surface 61a.
  • the second outer layer portion 54b is a portion between the internal electrode layer 10 closest to the second main surface 61b among the multiple internal electrode layers 10 and the second main surface 61b.
  • No internal electrode layer 10 is arranged in the first outer layer portion 54a and the second outer layer portion 54b.
  • the first outer layer 54a and the second outer layer 54b function as protective layers for the inner layer 53.
  • the dielectric layers 4 can be classified into a dielectric layer 4 arranged in the inner layer portion 53 and a dielectric layer 4 arranged in the outer layer portion 54.
  • the dielectric layer 4 arranged in the inner layer portion 53 is referred to as an inner dielectric layer 4a.
  • the dielectric layer 4 arranged in the outer layer portion 54 is referred to as an outer dielectric layer 4b.
  • the number of dielectric layers 4 stacked on the laminate 2 may be, for example, 5 to 2000.
  • the material of the dielectric layer 4 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3 , CaTiO3 , SrTiO3 , or CaZrO3 .
  • a material in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components may also be used.
  • the thickness of the dielectric layer 4 can be, for example, not less than 0.3 ⁇ m and not more than 0.6 ⁇ m.
  • the internal electrode layers 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b.
  • the first internal electrode layer 10a is an internal electrode layer 10 connected to a first external electrode 20a.
  • the second internal electrode layer 10b is an internal electrode layer 10 connected to a second external electrode 20b.
  • the first internal electrode layer 10a extends from a first end face 62a toward a second end face 62b.
  • the second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.
  • the first internal electrode layer 10 a and the second internal electrode layer 10 b each have a counter electrode portion 11 and an extraction electrode portion 12 .
  • the opposing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T.
  • the extraction electrode portion 12 is a portion of the internal electrode layer 10 that is extracted from the opposing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.
  • the opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a.
  • the extraction electrode portion 12 of the first internal electrode layer 10a is referred to as the first extraction electrode portion 12a.
  • the first extraction electrode portion 12a is a portion that is extracted from the first opposing electrode portion 11a to the first end surface 62a of the laminate 2.
  • the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b.
  • the extraction electrode portion 12 of the second internal electrode layer 10b is referred to as the second extraction electrode portion 12b.
  • the second extraction electrode portion 12b is a portion that is extracted from the second opposing electrode portion 11b to the second end surface 62b of the laminate 2.
  • the number of the internal electrode layers 10 may be, for example, from 10 to 2000.
  • the number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.
  • the thickness of the internal electrode layer 10 can be, for example, 0.1 ⁇ m to 5.0 ⁇ m, preferably 0.2 ⁇ m to 2.0 ⁇ m. When the thickness of the internal electrode layer 10 is 0.5 ⁇ m or more, a plating film is likely to grow when the metal layer of the external electrode 20 is formed by plating.
  • the material of the internal electrode layer 10 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, an alloy of Ni and Cu, an alloy of Ag and Pd, etc.
  • the material of the internal electrode layer 10 may contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 4.
  • the division of the laminate 2 in the longitudinal direction L will be described.
  • the laminate 2 can be divided into an electrode opposing portion 50 and an L gap (L gap region) 51 in the longitudinal direction L.
  • the electrode opposing portion 50 in the division in the longitudinal direction L is referred to as an L opposing portion 50a.
  • the L gap 51 includes a first L gap 51a and a second L gap 51b.
  • the L-opposing portion 50a corresponds to the portion where the first internal electrode layer 10a and the second internal electrode layer 10b oppose each other in the stacking direction T. A capacitance is formed in the L-opposing portion 50a. For this reason, the L-opposing portion 50a is also called the effective portion.
  • the L gap 51 is a portion in the longitudinal direction L of the laminate 2 where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the stacking direction T.
  • the first L gap 51a is between the L opposing portion 50a and the first end face 62a.
  • the second L gap 51b is between the L opposing portion 50a and the second end face 62b.
  • the first internal electrode layer 10a is arranged in the stacking direction T, but the second internal electrode layer 10b is not arranged.
  • the second internal electrode layer 10b is arranged in the stacking direction T, but the first internal electrode layer 10a is not arranged.
  • the first L gap 51a functions as an extension to the first end surface 62a of the first opposing electrode portion 11a.
  • the second L gap 51b functions as an extension to the second end surface 62b of the second opposing electrode portion 11b.
  • the length of the L gap 51 in the longitudinal direction L can be, for example, 10% to 30% of the length of the laminate 2 in the longitudinal direction L.
  • the length of the L gap 51 in the longitudinal direction L can be, for example, 5 ⁇ m to 30 ⁇ m.
  • the external electrodes 20 include a first external electrode 20a and a second external electrode 20b.
  • the first external electrode 20a is an external electrode 20 disposed on the first end surface 62a of the laminate 2.
  • the first external electrode 20a is electrically connected to the first internal electrode layer 10a.
  • the second external electrode 20b is an external electrode 20 disposed on the second end surface 62b of the laminate 2.
  • the second external electrode 20b is electrically connected to the second internal electrode layer 10b.
  • the external electrode 20 extends from one end face 62 to parts of the two main faces 61 and to parts of the two side faces 63 .
  • the layer structure of the external electrode 20 will be described with reference to FIG. 2.
  • the external electrode 20 includes a base electrode layer 21 and a plating layer 23.
  • the plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged in the order of the base electrode layer 21, the inner plating layer 24, and the surface plating layer 25 from the end surface 62 of the laminate 2.
  • the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a.
  • the first plating layer 23a further includes a first inner plating layer 24a and a first surface plating layer 25a.
  • the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b.
  • the second plating layer 23b further includes a second inner plating layer 24b and a second surface plating layer 25b.
  • the first base electrode layer 21a is disposed on and covers the first end face 62a of the laminate 2.
  • the first base electrode layer 21a extends from the first end face 62a to a part of the first main surface 61a, a part of the second main surface 61b, a part of the first side surface 63a, and a part of the second side surface 63b.
  • the second base electrode layer 21b is disposed on the second end face 62b of the laminate 2 and covers the second end face 62b.
  • the second base electrode layer 21b extends from the second end face 62b to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.
  • the first base electrode layer 21a and the second base electrode layer 21b are configured as a baking layer.
  • the baking layer includes a glass component and a metal.
  • the glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc.
  • the metal includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.
  • the baking layer may be a multi-layered layer.
  • the plating layer 23 on the base electrode layer 21 will be described.
  • the plating layer 23 includes the inner plating layer 24 and the surface plating layer 25.
  • the plating layers are a Ni plating layer and a Sn plating layer from the bottom. That is, the inner plating layer 24 is a Ni plating layer, and the surface plating layer 25 is a Sn plating layer.
  • the Ni plating layer can prevent the base electrode layer 21 from being eroded by solder when mounting the multilayer ceramic capacitor 1.
  • the Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1, making mounting easier. Therefore, by making the top plating layer 25 a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved.
  • the thickness of each plating layer is preferably 3 ⁇ m or more and 9 ⁇ m or less.
  • Fig. 3 is a cross-sectional view of the laminate ceramic capacitor 1 shown in Fig. 1 taken along line II-II.
  • the laminate 2 is divided into an electrode opposing portion 50 and a W gap 52 in the width direction W.
  • the electrode opposing portion 50 in the section in the width direction W is referred to as a W opposing portion 50b.
  • the W gap 52 includes a first W gap 52a and a second W gap 52b.
  • the W opposing portion 50b is a portion where the internal electrode layers 10 face each other in the stacking direction T.
  • the W gap 52 is a portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is arranged in the stacking direction T.
  • the first W gap 52a is between the W opposing portion 50b and the first side surface 63a in the width direction W of the laminate 2.
  • the second W gap 52b is between the W opposing portion 50b and the second side surface 63b.
  • the first W gap 52a and the second W gap 52b are arranged to sandwich the W opposing portion 50b.
  • the first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.
  • the length of the width direction W of the W gap 52 can be, for example, 20% to 30% of the length of the width direction W of the laminate 2. In addition, the length of the width direction W of the W gap 52 can be, for example, 5 ⁇ m to 50 ⁇ m.
  • the size of the multilayer ceramic capacitor 1 is not particularly limited.
  • the size of the multilayer ceramic capacitor 1 can be, for example, as follows.
  • the dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the L dimension.
  • the L dimension is preferably 0.25 mm or more and 1.0 mm or less.
  • the dimension in the stacking direction T of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the T dimension.
  • the T dimension is preferably 0.125 mm or more and 0.5 mm or less.
  • the dimension in the width direction W of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the W dimension.
  • the W dimension is preferably 0.125 mm or more and 0.5 mm or less.
  • the lengths of each part of the laminate 2 and the external electrodes 20 can be measured with a micrometer or an optical microscope.
  • the multilayer ceramic capacitor 1 has been described as a two-terminal multilayer ceramic capacitor as an example.
  • the multilayer ceramic capacitor 1 is not limited to being a two-terminal multilayer ceramic capacitor, and may be a multi-terminal multilayer ceramic capacitor having three or more terminals.
  • the multilayer ceramic capacitor 1 of this embodiment includes a Si segregation layer 14 in the L gap 51.
  • the Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 or the like.
  • FIG. 4 is a diagram showing a portion of the LT cross section of the multilayer ceramic capacitor 1 of this embodiment.
  • FIG. 4 corresponds to an enlarged view of the region R1 indicated by the dashed line in FIG. 2.
  • FIG. 4 shows the first L gap 51a and its vicinity.
  • a Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in and near the first L gap 51a.
  • a Si segregation layer 14 is formed on the entire surface of the first lead electrode portion 12a and at least a part of the surface of the first opposing electrode portion 11a. The at least a part of the first opposing electrode portion 11a corresponds to a part of the first opposing electrode portion 11a close to the first L gap 51a.
  • a Si segregation layer 14 is formed on at least a portion of the surface of the second opposing electrode portion 11b.
  • the at least a portion of the second opposing electrode portion 11b corresponds to a portion of the second opposing electrode portion 11b that is close to the first L gap 51a.
  • the portion close to the first L gap 51a refers to the portion, for example, about 50 ⁇ m from the boundary between the first L gap 51a and the L opposing portion 50a in the direction of the L opposing portion 50a.
  • the end of the internal electrode layer 10 is referred to as the electrode end 10e.
  • the end of the internal electrode layer 10 means the end surface parallel to the stacking direction T of the internal electrode layer 10.
  • FIG. 4 shows the electrode end 10e of the second internal electrode layer 10b. In the configuration shown in FIG. 4, a Si segregation layer 14 is formed over the entire electrode end 10e in the direction parallel to the stacking direction T.
  • the Si segregation layer 14 is formed not only on the surface parallel to the length direction L of the internal electrode layer 10, but also on the surface parallel to the stacking direction T at the electrode end 10e. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L gap 51a and its vicinity.
  • Floating island electrode 4
  • a floating island electrode 13 having a floating island shape is formed in the first L gap 51a.
  • a Si segregation layer 14 is also formed on the surface of this floating island electrode 13.
  • the floating island electrode 13 can be formed intentionally when forming the internal electrode layer 10. Alternatively, it may be formed unintentionally when forming the internal electrode layer 10.
  • the Si segregation layer 14 has been described above using the first L gap 51a as an example.
  • the second L gap 51b has a similar configuration. That is, the second lead electrode portion 12b and the first opposing electrode portion 11a in the second L gap 51b also have the same Si segregation layer 14 as the first lead electrode portion 12a and the second opposing electrode portion 11b in the first L gap 51a.
  • Fig. 5 is a diagram showing a part of the WT cross section of the multilayer ceramic capacitor 1 according to the embodiment of the present invention. Note that Fig. 5 is a schematic diagram. Therefore, the number of patterns, etc. may not be consistent with other drawings.
  • the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W. More specifically, the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W over the entire direction parallel to the stacking direction T. The Si segregation layer 14 is also formed on the surface parallel to the width direction W of the internal electrode layer 10. However, the Si segregation layer 14 is not formed to cover the entire surface parallel to the width direction W. The Si segregation layer 14 is formed on a surface parallel to the width direction W a predetermined distance from the electrode end 10e. This predetermined distance is indicated as distance d1 in FIG. 5. Distance d1 can be, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • (Other configurations of the Si segregation layer) 6 is a diagram showing another configuration of the region R2 in FIG. 5.
  • the configuration shown in FIG. 5 and the configuration shown in FIG. 6 differ in the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10.
  • the Si segregation layer 14 is formed over the entire stacking direction T at the electrode end 10e of the internal electrode layer 10.
  • the Si segregation layer 14 is not formed over the entire stacking direction T of the electrode end 10e.
  • the Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T.
  • the Si segregation layer 14 is not formed in the central portion of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central portion of the electrode end 10e in the stacking direction T.
  • the Si segregation layer 14 may be formed over the entire stacking direction T at the electrode end 10e in the width direction W of the internal electrode layer 10, or may be formed over a portion of the stacking direction T.
  • the thickness of the Si segregation layer 14 can be, for example, 0.01 ⁇ m or more and 0.30 ⁇ m or less.
  • the thickness of the Si segregation layer 14 can be obtained by exposing a cross section of the laminate 2, distinguishing between dielectric particles and the Si segregation layer using a scanning electron microscope (SEM), and further performing elemental analysis of the surface using energy dispersive X-ray analysis (EDX).
  • a method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to FIG. (Preparation of laminated blocks)
  • a ceramic green sheet 30, an electrode paste 31 for the internal electrode layer 10, and a step paste 32 for the step layer 5 are prepared.
  • Step layer 5 First, the step layer 5 will be described. It is preferable that the difference in length in the stacking direction T of the laminate 2 is small between the electrode facing portion 50 and the L gap 51. However, in the inner layer portion 53, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51.
  • the dielectric layer 4 and the internal electrode layer 10 are stacked in the electrode facing portion 50. In contrast, the dielectric layer 4 and only the internal electrode layer 10 connected to one external electrode 20 among the internal electrode layers 10 are stacked in the L gap 51. Therefore, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51.
  • an additional dielectric layer 4 is disposed in the L gap 51.
  • This additional dielectric layer 4 is referred to as the step layer 5. It is preferable that the step layer 5 has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited to this.
  • the step layer 5 is shown in Figure 4. As shown in Figure 4, the step layer 5 is disposed in the first L gap 51a between two first opposing electrode portions 11a that face each other in the stacking direction T. The step layer 5 compensates for the thickness of the second internal electrode layer 10b, thereby making it possible to reduce the difference in length in the stacking direction T between the first L gap 51a and the L opposing portion 50a.
  • a Si component is blended into the step paste 32. This Si component will later form the Si segregation layer 14. Note that adding a Si component to the step paste 32 is one example of a method for forming the Si segregation layer 14.
  • the above-mentioned electrode paste 31 and step paste 32 are applied to the ceramic green sheet 30 in a desired pattern.
  • the application of each paste to the ceramic green sheet 30 can be performed by a method such as screen printing or gravure printing.
  • the electrode paste 31 and step paste 32 are printed in a predetermined pattern on the ceramic green sheet 30 by any printing method. In this way, the ceramic green sheet 30 for the inner layer portion 53 on which the paste is printed is obtained.
  • a predetermined number of ceramic green sheets 30 on which the pattern of the internal electrode layer 10 is not printed are laminated. This creates a portion corresponding to the outer layer portion 54.
  • ceramic green sheets 30 for the inner layer portion 53 on which paste has been applied are sequentially laminated. This creates a portion corresponding to the inner layer portion 53.
  • a predetermined number of ceramic green sheets 30 for the other outer layer portion 54 are laminated. This creates a laminated sheet. The laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to create a laminated block.
  • FIG. 7 is a plan view of the ceramic green sheet 30 on which the electrode paste 31 and the step paste 32 are applied.
  • FIG. 7 is a view of the ceramic green sheet 30 as viewed from the lamination direction T. 701 and 702 in FIG. 7 each indicate one ceramic green sheet 30. By laminating these ceramic green sheets 30, a laminated sheet can be obtained.
  • ten electrode patterns are formed on the ceramic green sheet 30 using the electrode paste 31.
  • the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between two electrode patterns arranged in the length direction L.
  • An electrode paste 31 and a step paste 32 are applied in the same pattern to two ceramic green sheets 30 indicated by 701 and 702 in FIG.
  • the laminated block is cut to a predetermined size to cut out laminated chips. At this time, corners and edges of the laminated chips may be rounded by barrel polishing or the like.
  • the laminated chip is fired to produce the laminate 2.
  • the firing temperature depends on the materials of the ceramic layers 4 and the internal electrode layers 10, but is preferably 900° C. or higher and 1400° C. or lower.
  • the external electrodes 20 are formed.
  • (Base electrode layer) A conductive paste that will become the base electrode layer 21 is applied to the two end faces 62 of the laminate 2 to form the base electrode layer 21.
  • a conductive paste containing a glass component and a metal is applied by a method such as dipping.
  • a baking process is performed to form the base electrode layer 21.
  • the temperature of the baking process is preferably 500° C. or higher and 900° C. or lower.
  • the time of the baking process is preferably 30 minutes or higher and 2 hours or lower.
  • the atmosphere of the baking process is preferably a reducing atmosphere containing, for example, H 2 O or H 2 .
  • a plating layer 23 is formed on the surface of the base electrode layer 21.
  • a Ni plating layer is formed on the baked layer. This Ni plating layer becomes the inner plating layer 24.
  • a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the surface plating layer 25.
  • the Ni plating layer and the Sn plating layer are formed in sequence, for example, by barrel plating. In this manner, the multilayer ceramic capacitor 1 is obtained.
  • FIG. 8 is a plan view of a ceramic green sheet 30 on which an electrode paste 31 and a step paste 32 are applied.
  • the shapes of the patterns of the electrode paste 31 and the step paste 32 applied to the ceramic green sheet 30 are different between FIG. 7 and FIG. 8.
  • the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between two electrode patterns arranged in the length direction L.
  • the electrode patterns are arranged in four columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between the first electrode pattern and the second electrode pattern, and between the third electrode pattern and the fourth electrode pattern, in the four electrode patterns arranged in the length direction L.
  • the electrode paste 31 and the step paste 32 can be applied to the ceramic green sheet 30 in a variety of patterns depending on the type of multilayer ceramic capacitor 1 to be manufactured.
  • the ceramic green sheet 30 indicated by 801 in Fig. 8 is the first ceramic green sheet 30a.
  • the ceramic green sheet 30 indicated by 802 in Fig. 8 is the second ceramic green sheet 30b.
  • the first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked with a shift in the same manner as in the configuration shown in Fig. 7. Specifically, they are stacked with a shift of a distance d2 in the longitudinal direction L.
  • FIGS. 9(a) and 9(b) are diagrams showing the LT cross section of the laminated ceramic green sheets 30.
  • FIGS. 9(a) and 9(b) in order to simplify the configuration, only two ceramic green sheets 30 are illustrated as an example. In the following description, the two ceramic green sheets 30 are referred to as a laminate 40.
  • Lines L1 and L2 shown in FIG. 9(a) indicate cutting lines. These lines L1 and L2 correspond to the lines L1 and L2 shown in FIG. 8.
  • FIG. 9(a) shows the laminate 40 before cutting.
  • FIG. 9(b) shows the laminate 40 after cutting along the lines L1 and L2.
  • a central portion 32b in the longitudinal direction L of the pattern of the step paste 32 in the second ceramic green sheet 30b is aligned with an end portion 31a in the longitudinal direction L of the pattern of the electrode paste 31 in the first ceramic green sheet 30a in the longitudinal direction L. That is, the central portion 32b of the pattern of the step paste 32 and the end portion 31a of the pattern of the electrode paste 31 are both located on the line L2.
  • (After disconnection) 9B shows the laminate 40 after cutting.
  • the laminate 40 cut along the lines L1 and L2 has a step layer 5 formed in the L gap 51. This is because the ceramic green sheets 30 are stacked with a shift so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b have the positional relationship described above.
  • the cut surface generated by cutting along line L1 is defined as a first cut surface 41.
  • the cut surface generated by cutting along line L2 is defined as a second cut surface 42.
  • the first cut surface 41 corresponds to a first end surface 62a of the laminate 2.
  • the second cut surface 42 corresponds to a second end surface 62b of the laminate 2.
  • "corresponding" means a portion of the laminate 2 that corresponds when the laminate 40 is fired to become the laminate 2.
  • the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a are exposed.
  • the second cut surface 42 of the laminate 40, in the stacking direction T the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5 are exposed.
  • the portions where the step paste 32 is arranged become the first L gap 51a and the second L gap 51b, respectively.
  • the step paste 32 contains a Si component for forming the Si segregation layer 14.
  • This Si component migrates through the step paste 32 and adheres to the internal electrode layer 10.
  • the Si component is a liquid phase component. Therefore, the Si component can move across the dielectric material and approach the internal electrode layer. Specifically, the Si component adheres to the surface of the extraction electrode portion 12 and at least a part of the end and surface of the counter electrode portion 11. The Si component adhered to each internal electrode layer 10 forms the Si segregation layer 14.
  • the method for forming the Si segregation layer 14 is not limited to the above-mentioned method of blending the Si component into the step paste 32.
  • Another method for forming the Si segregation layer 14 is to apply the Si component to the L gap 51. In this method, the Si component is applied by printing or the like to an application pattern of the electrode paste 31 corresponding to the portion where the Si segregation layer 14 is to be formed.
  • Another method for forming the Si segregation layer 14 is to impregnate the WT end face of the laminated chip before firing, i.e., the face corresponding to the end face 62 of the laminated body 2, with the Si component.
  • the multilayer ceramic capacitor 1 of this embodiment is provided with the Si segregation layer 14 in the L gap 51. This can improve the reliability of the multilayer ceramic capacitor 1. This is because the Si segregation layer 14 has a high IR (insulation resistance).
  • Fig. 10 is a diagram showing the results of the high temperature load reliability test for the comparative example and the example.
  • the method of the high temperature load reliability test is as follows. For each of the comparative example and the examples 1 to 8, 100 samples were prepared. The samples were mounted on a glass epoxy board using eutectic solder. The thickness of the dielectric layer in the sample was set to 0.5 ⁇ m. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy board was placed in a high temperature chamber, and a voltage of 6.3 V was applied to each sample in an environment of 150° C.
  • the insulation resistance value was measured after 200 hours and after 500 hours.
  • the initial insulation resistance value was compared with the insulation resistance value after aging, and a sample with an insulation resistance value that decreased by one digit or more was determined to be defective. As shown in FIG. 10, no defects occurred in the sample having the Si segregation layer after 200 hours. Furthermore, the number of defects was suppressed to 5 or less even after 500 hours.
  • FIG. 11 is a diagram showing the evaluation results of the dielectric constant and the mean time to failure for the comparative example and the example.
  • the thickness of the dielectric layer in the sample was set to four types ranging from 0.3 ⁇ m to 0.6 ⁇ m. By varying the thickness of the dielectric layer, samples with different element thicknesses were produced. In addition, the thickness of the Si segregation layer was set to 0.07 ⁇ m and 0.08 ⁇ m.
  • Si has a low dielectric constant. Therefore, a decrease in dielectric constant was observed in samples with a Si segregation layer. Also, an improvement in MTTF (Mean Time To Failure) was observed in samples with a Si segregation layer.
  • the dielectric layer includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together, a laminate including a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction; external electrodes provided on the first end surface and the second end surface; Equipped with the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is extended to the first end face, the second internal electrode layer is extended to the second end face, the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer; an L-gap region is an area disposed on the first end face side, in which the first internal electrode layers do not overlap with each other in the stacking direction,
  • the thickness of the Si segregation layer is 0.03 ⁇ m or more and 0.15 ⁇ m or less.
  • the Si segregation layer is present at an end portion in the width direction of the first internal electrode layer and an end portion in the width direction of the second internal electrode;
  • the thickness of the dielectric layer is 0.4 ⁇ m or more and 0.5 ⁇ m or less.

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JP2001237140A (ja) * 1999-12-13 2001-08-31 Murata Mfg Co Ltd 積層型セラミック電子部品およびその製造方法ならびにセラミックペーストおよびその製造方法
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WO2010109562A1 (ja) 2009-03-27 2010-09-30 株式会社村田製作所 積層セラミック電子部品の製造方法
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JP2001126951A (ja) * 1999-10-29 2001-05-11 Tdk Corp 積層セラミック電子部品の製造方法
JP2001237140A (ja) * 1999-12-13 2001-08-31 Murata Mfg Co Ltd 積層型セラミック電子部品およびその製造方法ならびにセラミックペーストおよびその製造方法
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CN119764291A (zh) * 2025-03-06 2025-04-04 嘉善复旦研究院 半导体器件、半导体封装和半导体封装方法

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