WO2024070337A1 - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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Publication number
WO2024070337A1
WO2024070337A1 PCT/JP2023/030103 JP2023030103W WO2024070337A1 WO 2024070337 A1 WO2024070337 A1 WO 2024070337A1 JP 2023030103 W JP2023030103 W JP 2023030103W WO 2024070337 A1 WO2024070337 A1 WO 2024070337A1
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layer
internal electrode
electrode
electrode layer
laminate
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PCT/JP2023/030103
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French (fr)
Japanese (ja)
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幸祐 浦谷
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株式会社村田製作所
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Publication of WO2024070337A1 publication Critical patent/WO2024070337A1/en

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  • the present invention relates to a multilayer ceramic capacitor.
  • Patent Document 1 describes a technology for preventing this dielectric breakdown by forming at least a portion of the area near the edge of the internal electrode of the dielectric layer from a dielectric ceramic that has a higher withstand voltage than other areas.
  • the thickness of the dielectric layers in multilayer ceramic capacitors is becoming thinner.
  • the insulation resistance value decreases.
  • the internal electrodes are structurally prone to bending. This causes the thickness of the dielectric layers to decrease locally, making insulation breakdown more likely to occur. Therefore, the objective of the present invention is to provide a multilayer ceramic capacitor in which the occurrence of insulation breakdown is further suppressed.
  • the multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the lamination direction and the width direction, and an external electrode provided on the first end surface and the second end surface
  • the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is drawn out to the first end surface, the second internal electrode layer is drawn out to the second end surface, the external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the first end surface side is a region where the first internal electrode layers do not overlap with each other in the lamination direction, and the second end surface side is a region where the
  • the present invention provides a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed.
  • FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention
  • 2 is a cross-sectional view taken along line II in FIG. 1.
  • 2 is a cross-sectional view taken along line II-II of FIG. 1.
  • 2 is a diagram showing a portion of an LT cross section of the multilayer ceramic capacitor of the present embodiment.
  • FIG. 2 is a diagram showing a portion of a WT cross section of the multilayer ceramic capacitor of the present embodiment.
  • FIG. 11 is a diagram showing a portion of a WT cross section of another configuration of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. FIG. 2 is a plan view of a ceramic green sheet according to the embodiment.
  • FIG. 11 is a plan view of a ceramic green sheet having another configuration in the present embodiment.
  • 4A and 4B are diagrams showing LT cross sections of laminated ceramic green sheets.
  • FIG. 13 is a diagram showing the results of a high-temperature load reliability test.
  • Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of the present embodiment.
  • the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20.
  • the L direction is the length direction L of the multilayer ceramic capacitor 1.
  • the W direction is the width direction W of the multilayer ceramic capacitor 1.
  • the T direction is the stacking direction T of the multilayer ceramic capacitor 1.
  • the cross section shown in FIG. 2 is called an LT cross section, and the cross section shown in FIG. 3 is called a WT cross section.
  • the length direction L, the width direction W, and the stacking direction T do not necessarily have to be perpendicular to each other.
  • the length direction L, the width direction W, and the stacking direction T may intersect each other.
  • the laminate 2 has a substantially rectangular parallelepiped shape.
  • the laminate 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63.
  • the main surface 61 is a surface facing the stacking direction T.
  • the end surface 62 is a surface facing the length direction L.
  • the side surface 63 is a surface facing the width direction W.
  • One of the two main surfaces 61 is a first main surface 61a, and the other is a second main surface 61b.
  • One of the two end surfaces 62 is a first end surface 62a, and the other is a second end surface 62b.
  • One of the two side surfaces 63 is a first side surface 63a, and the other is a second side surface 63b.
  • the second main surface 61b and the first side surface 63a are shown in FIG. 1.
  • the ridges and corners of the laminate 2 are preferably rounded.
  • a ridge is a portion where two surfaces of the laminate 2 intersect.
  • a corner is a portion where three surfaces of the laminate 2 intersect.
  • the size of the laminate 2 is not particularly limited.
  • the laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2.
  • Fig. 2 is a cross-sectional view of the laminated ceramic capacitor 1 shown in Fig. 1 taken along line II.
  • Fig. 2 shows an LT cross-section of the laminated ceramic capacitor 1.
  • the laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in a stacking direction T.
  • the laminate 2 is divided into an inner layer portion 53 and two outer layer portions 54 in the stacking direction T.
  • the outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b.
  • the first outer layer portion 54a and the second outer layer portion 54b are located at positions sandwiching the inner layer portion 53 in the stacking direction T.
  • the inner layer portion 53 a plurality of dielectric layers 4 and a plurality of internal electrode layers 10 are arranged.
  • the plurality of internal electrode layers 10 face each other via the dielectric layer 4. Therefore, a capacitance is formed in the inner layer portion 53. Therefore, the inner layer portion 53 is the portion of the laminate 2 that essentially functions as a capacitor. For this reason, the inner layer portion 53 is also called the effective portion.
  • the first outer layer portion 54a is a portion of the outer layer portion 54 located on the side of the first main surface 61a of the laminate 2.
  • the second outer layer portion 54b is a portion of the outer layer portion 54 located on the side of the second main surface 61b of the laminate 2.
  • the first outer layer portion 54a is a portion between the internal electrode layer 10 closest to the first main surface 61a among the multiple internal electrode layers 10 and the first main surface 61a.
  • the second outer layer portion 54b is a portion between the internal electrode layer 10 closest to the second main surface 61b among the multiple internal electrode layers 10 and the second main surface 61b.
  • No internal electrode layer 10 is arranged in the first outer layer portion 54a and the second outer layer portion 54b.
  • the first outer layer 54a and the second outer layer 54b function as protective layers for the inner layer 53.
  • the dielectric layers 4 can be classified into a dielectric layer 4 arranged in the inner layer portion 53 and a dielectric layer 4 arranged in the outer layer portion 54.
  • the dielectric layer 4 arranged in the inner layer portion 53 is referred to as an inner dielectric layer 4a.
  • the dielectric layer 4 arranged in the outer layer portion 54 is referred to as an outer dielectric layer 4b.
  • the number of dielectric layers 4 stacked on the laminate 2 may be, for example, 5 to 2000.
  • the material of the dielectric layer 4 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3 , CaTiO3 , SrTiO3 , or CaZrO3 .
  • a material in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components may also be used.
  • the thickness of the dielectric layer 4 can be, for example, not less than 0.3 ⁇ m and not more than 0.6 ⁇ m.
  • the internal electrode layers 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b.
  • the first internal electrode layer 10a is an internal electrode layer 10 connected to a first external electrode 20a.
  • the second internal electrode layer 10b is an internal electrode layer 10 connected to a second external electrode 20b.
  • the first internal electrode layer 10a extends from a first end face 62a toward a second end face 62b.
  • the second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.
  • the first internal electrode layer 10 a and the second internal electrode layer 10 b each have a counter electrode portion 11 and an extraction electrode portion 12 .
  • the opposing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T.
  • the extraction electrode portion 12 is a portion of the internal electrode layer 10 that is extracted from the opposing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.
  • the opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a.
  • the extraction electrode portion 12 of the first internal electrode layer 10a is referred to as the first extraction electrode portion 12a.
  • the first extraction electrode portion 12a is a portion that is extracted from the first opposing electrode portion 11a to the first end surface 62a of the laminate 2.
  • the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b.
  • the extraction electrode portion 12 of the second internal electrode layer 10b is referred to as the second extraction electrode portion 12b.
  • the second extraction electrode portion 12b is a portion that is extracted from the second opposing electrode portion 11b to the second end surface 62b of the laminate 2.
  • the number of the internal electrode layers 10 may be, for example, from 10 to 2000.
  • the number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.
  • the thickness of the internal electrode layer 10 can be, for example, 0.1 ⁇ m to 5.0 ⁇ m, preferably 0.2 ⁇ m to 2.0 ⁇ m. When the thickness of the internal electrode layer 10 is 0.5 ⁇ m or more, a plating film is likely to grow when the metal layer of the external electrode 20 is formed by plating.
  • the material of the internal electrode layer 10 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, an alloy of Ni and Cu, an alloy of Ag and Pd, etc.
  • the material of the internal electrode layer 10 may contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 4.
  • the division of the laminate 2 in the longitudinal direction L will be described.
  • the laminate 2 can be divided into an electrode opposing portion 50 and an L gap (L gap region) 51 in the longitudinal direction L.
  • the electrode opposing portion 50 in the division in the longitudinal direction L is referred to as an L opposing portion 50a.
  • the L gap 51 includes a first L gap 51a and a second L gap 51b.
  • the L-opposing portion 50a corresponds to the portion where the first internal electrode layer 10a and the second internal electrode layer 10b oppose each other in the stacking direction T. A capacitance is formed in the L-opposing portion 50a. For this reason, the L-opposing portion 50a is also called the effective portion.
  • the L gap 51 is a portion in the longitudinal direction L of the laminate 2 where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the stacking direction T.
  • the first L gap 51a is between the L opposing portion 50a and the first end face 62a.
  • the second L gap 51b is between the L opposing portion 50a and the second end face 62b.
  • the first internal electrode layer 10a is arranged in the stacking direction T, but the second internal electrode layer 10b is not arranged.
  • the second internal electrode layer 10b is arranged in the stacking direction T, but the first internal electrode layer 10a is not arranged.
  • the first L gap 51a functions as an extension to the first end surface 62a of the first opposing electrode portion 11a.
  • the second L gap 51b functions as an extension to the second end surface 62b of the second opposing electrode portion 11b.
  • the length of the L gap 51 in the longitudinal direction L can be, for example, 10% to 30% of the length of the laminate 2 in the longitudinal direction L.
  • the length of the L gap 51 in the longitudinal direction L can be, for example, 5 ⁇ m to 30 ⁇ m.
  • the external electrodes 20 include a first external electrode 20a and a second external electrode 20b.
  • the first external electrode 20a is an external electrode 20 disposed on the first end surface 62a of the laminate 2.
  • the first external electrode 20a is electrically connected to the first internal electrode layer 10a.
  • the second external electrode 20b is an external electrode 20 disposed on the second end surface 62b of the laminate 2.
  • the second external electrode 20b is electrically connected to the second internal electrode layer 10b.
  • the external electrode 20 extends from one end face 62 to parts of the two main faces 61 and to parts of the two side faces 63 .
  • the layer structure of the external electrode 20 will be described with reference to FIG. 2.
  • the external electrode 20 includes a base electrode layer 21 and a plating layer 23.
  • the plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged in the order of the base electrode layer 21, the inner plating layer 24, and the surface plating layer 25 from the end surface 62 of the laminate 2.
  • the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a.
  • the first plating layer 23a further includes a first inner plating layer 24a and a first surface plating layer 25a.
  • the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b.
  • the second plating layer 23b further includes a second inner plating layer 24b and a second surface plating layer 25b.
  • the first base electrode layer 21a is disposed on and covers the first end face 62a of the laminate 2.
  • the first base electrode layer 21a extends from the first end face 62a to a part of the first main surface 61a, a part of the second main surface 61b, a part of the first side surface 63a, and a part of the second side surface 63b.
  • the second base electrode layer 21b is disposed on the second end face 62b of the laminate 2 and covers the second end face 62b.
  • the second base electrode layer 21b extends from the second end face 62b to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.
  • the first base electrode layer 21a and the second base electrode layer 21b are configured as a baking layer.
  • the baking layer includes a glass component and a metal.
  • the glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc.
  • the metal includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.
  • the baking layer may be a multi-layered layer.
  • the plating layer 23 on the base electrode layer 21 will be described.
  • the plating layer 23 includes the inner plating layer 24 and the surface plating layer 25.
  • the plating layers are a Ni plating layer and a Sn plating layer from the bottom. That is, the inner plating layer 24 is a Ni plating layer, and the surface plating layer 25 is a Sn plating layer.
  • the Ni plating layer can prevent the base electrode layer 21 from being eroded by solder when mounting the multilayer ceramic capacitor 1.
  • the Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1, making mounting easier. Therefore, by making the top plating layer 25 a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved.
  • the thickness of each plating layer is preferably 3 ⁇ m or more and 9 ⁇ m or less.
  • Fig. 3 is a cross-sectional view of the laminate ceramic capacitor 1 shown in Fig. 1 taken along line II-II.
  • the laminate 2 is divided into an electrode opposing portion 50 and a W gap 52 in the width direction W.
  • the electrode opposing portion 50 in the section in the width direction W is referred to as a W opposing portion 50b.
  • the W gap 52 includes a first W gap 52a and a second W gap 52b.
  • the W opposing portion 50b is a portion where the internal electrode layers 10 face each other in the stacking direction T.
  • the W gap 52 is a portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is arranged in the stacking direction T.
  • the first W gap 52a is between the W opposing portion 50b and the first side surface 63a in the width direction W of the laminate 2.
  • the second W gap 52b is between the W opposing portion 50b and the second side surface 63b.
  • the first W gap 52a and the second W gap 52b are arranged to sandwich the W opposing portion 50b.
  • the first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.
  • the length of the width direction W of the W gap 52 can be, for example, 20% to 30% of the length of the width direction W of the laminate 2. In addition, the length of the width direction W of the W gap 52 can be, for example, 5 ⁇ m to 50 ⁇ m.
  • the size of the multilayer ceramic capacitor 1 is not particularly limited.
  • the size of the multilayer ceramic capacitor 1 can be, for example, as follows.
  • the dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the L dimension.
  • the L dimension is preferably 0.25 mm or more and 1.0 mm or less.
  • the dimension in the stacking direction T of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the T dimension.
  • the T dimension is preferably 0.125 mm or more and 0.5 mm or less.
  • the dimension in the width direction W of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the W dimension.
  • the W dimension is preferably 0.125 mm or more and 0.5 mm or less.
  • the lengths of each part of the laminate 2 and the external electrodes 20 can be measured with a micrometer or an optical microscope.
  • the multilayer ceramic capacitor 1 has been described as a two-terminal multilayer ceramic capacitor as an example.
  • the multilayer ceramic capacitor 1 is not limited to being a two-terminal multilayer ceramic capacitor, and may be a multi-terminal multilayer ceramic capacitor having three or more terminals.
  • the multilayer ceramic capacitor 1 of this embodiment includes a Si segregation layer 14 in the L gap 51.
  • the Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 or the like.
  • FIG. 4 is a diagram showing a portion of the LT cross section of the multilayer ceramic capacitor 1 of this embodiment.
  • FIG. 4 corresponds to an enlarged view of the region R1 indicated by the dashed line in FIG. 2.
  • FIG. 4 shows the first L gap 51a and its vicinity.
  • a Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in and near the first L gap 51a.
  • a Si segregation layer 14 is formed on the entire surface of the first lead electrode portion 12a and at least a part of the surface of the first opposing electrode portion 11a. The at least a part of the first opposing electrode portion 11a corresponds to a part of the first opposing electrode portion 11a close to the first L gap 51a.
  • a Si segregation layer 14 is formed on at least a portion of the surface of the second opposing electrode portion 11b.
  • the at least a portion of the second opposing electrode portion 11b corresponds to a portion of the second opposing electrode portion 11b that is close to the first L gap 51a.
  • the portion close to the first L gap 51a refers to the portion, for example, about 50 ⁇ m from the boundary between the first L gap 51a and the L opposing portion 50a in the direction of the L opposing portion 50a.
  • the end of the internal electrode layer 10 is referred to as the electrode end 10e.
  • the end of the internal electrode layer 10 means the end surface parallel to the stacking direction T of the internal electrode layer 10.
  • FIG. 4 shows the electrode end 10e of the second internal electrode layer 10b. In the configuration shown in FIG. 4, a Si segregation layer 14 is formed over the entire electrode end 10e in the direction parallel to the stacking direction T.
  • the Si segregation layer 14 is formed not only on the surface parallel to the length direction L of the internal electrode layer 10, but also on the surface parallel to the stacking direction T at the electrode end 10e. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L gap 51a and its vicinity.
  • Floating island electrode 4
  • a floating island electrode 13 having a floating island shape is formed in the first L gap 51a.
  • a Si segregation layer 14 is also formed on the surface of this floating island electrode 13.
  • the floating island electrode 13 can be formed intentionally when forming the internal electrode layer 10. Alternatively, it may be formed unintentionally when forming the internal electrode layer 10.
  • the Si segregation layer 14 has been described above using the first L gap 51a as an example.
  • the second L gap 51b has a similar configuration. That is, the second lead electrode portion 12b and the first opposing electrode portion 11a in the second L gap 51b also have the same Si segregation layer 14 as the first lead electrode portion 12a and the second opposing electrode portion 11b in the first L gap 51a.
  • Fig. 5 is a diagram showing a part of the WT cross section of the multilayer ceramic capacitor 1 according to the embodiment of the present invention. Note that Fig. 5 is a schematic diagram. Therefore, the number of patterns, etc. may not be consistent with other drawings.
  • the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W. More specifically, the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W over the entire direction parallel to the stacking direction T. The Si segregation layer 14 is also formed on the surface parallel to the width direction W of the internal electrode layer 10. However, the Si segregation layer 14 is not formed to cover the entire surface parallel to the width direction W. The Si segregation layer 14 is formed on a surface parallel to the width direction W a predetermined distance from the electrode end 10e. This predetermined distance is indicated as distance d1 in FIG. 5. Distance d1 can be, for example, 1 ⁇ m or more and 50 ⁇ m or less.
  • (Other configurations of the Si segregation layer) 6 is a diagram showing another configuration of the region R2 in FIG. 5.
  • the configuration shown in FIG. 5 and the configuration shown in FIG. 6 differ in the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10.
  • the Si segregation layer 14 is formed over the entire stacking direction T at the electrode end 10e of the internal electrode layer 10.
  • the Si segregation layer 14 is not formed over the entire stacking direction T of the electrode end 10e.
  • the Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T.
  • the Si segregation layer 14 is not formed in the central portion of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central portion of the electrode end 10e in the stacking direction T.
  • the Si segregation layer 14 may be formed over the entire stacking direction T at the electrode end 10e in the width direction W of the internal electrode layer 10, or may be formed over a portion of the stacking direction T.
  • the thickness of the Si segregation layer 14 can be, for example, 0.01 ⁇ m or more and 0.30 ⁇ m or less.
  • the thickness of the Si segregation layer 14 can be obtained by exposing a cross section of the laminate 2, distinguishing between dielectric particles and the Si segregation layer using a scanning electron microscope (SEM), and further performing elemental analysis of the surface using energy dispersive X-ray analysis (EDX).
  • a method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to FIG. (Preparation of laminated blocks)
  • a ceramic green sheet 30, an electrode paste 31 for the internal electrode layer 10, and a step paste 32 for the step layer 5 are prepared.
  • Step layer 5 First, the step layer 5 will be described. It is preferable that the difference in length in the stacking direction T of the laminate 2 is small between the electrode facing portion 50 and the L gap 51. However, in the inner layer portion 53, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51.
  • the dielectric layer 4 and the internal electrode layer 10 are stacked in the electrode facing portion 50. In contrast, the dielectric layer 4 and only the internal electrode layer 10 connected to one external electrode 20 among the internal electrode layers 10 are stacked in the L gap 51. Therefore, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51.
  • an additional dielectric layer 4 is disposed in the L gap 51.
  • This additional dielectric layer 4 is referred to as the step layer 5. It is preferable that the step layer 5 has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited to this.
  • the step layer 5 is shown in Figure 4. As shown in Figure 4, the step layer 5 is disposed in the first L gap 51a between two first opposing electrode portions 11a that face each other in the stacking direction T. The step layer 5 compensates for the thickness of the second internal electrode layer 10b, thereby making it possible to reduce the difference in length in the stacking direction T between the first L gap 51a and the L opposing portion 50a.
  • a Si component is blended into the step paste 32. This Si component will later form the Si segregation layer 14. Note that adding a Si component to the step paste 32 is one example of a method for forming the Si segregation layer 14.
  • the above-mentioned electrode paste 31 and step paste 32 are applied to the ceramic green sheet 30 in a desired pattern.
  • the application of each paste to the ceramic green sheet 30 can be performed by a method such as screen printing or gravure printing.
  • the electrode paste 31 and step paste 32 are printed in a predetermined pattern on the ceramic green sheet 30 by any printing method. In this way, the ceramic green sheet 30 for the inner layer portion 53 on which the paste is printed is obtained.
  • a predetermined number of ceramic green sheets 30 on which the pattern of the internal electrode layer 10 is not printed are laminated. This creates a portion corresponding to the outer layer portion 54.
  • ceramic green sheets 30 for the inner layer portion 53 on which paste has been applied are sequentially laminated. This creates a portion corresponding to the inner layer portion 53.
  • a predetermined number of ceramic green sheets 30 for the other outer layer portion 54 are laminated. This creates a laminated sheet. The laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to create a laminated block.
  • FIG. 7 is a plan view of the ceramic green sheet 30 on which the electrode paste 31 and the step paste 32 are applied.
  • FIG. 7 is a view of the ceramic green sheet 30 as viewed from the lamination direction T. 701 and 702 in FIG. 7 each indicate one ceramic green sheet 30. By laminating these ceramic green sheets 30, a laminated sheet can be obtained.
  • ten electrode patterns are formed on the ceramic green sheet 30 using the electrode paste 31.
  • the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between two electrode patterns arranged in the length direction L.
  • An electrode paste 31 and a step paste 32 are applied in the same pattern to two ceramic green sheets 30 indicated by 701 and 702 in FIG.
  • the laminated block is cut to a predetermined size to cut out laminated chips. At this time, corners and edges of the laminated chips may be rounded by barrel polishing or the like.
  • the laminated chip is fired to produce the laminate 2.
  • the firing temperature depends on the materials of the ceramic layers 4 and the internal electrode layers 10, but is preferably 900° C. or higher and 1400° C. or lower.
  • the external electrodes 20 are formed.
  • (Base electrode layer) A conductive paste that will become the base electrode layer 21 is applied to the two end faces 62 of the laminate 2 to form the base electrode layer 21.
  • a conductive paste containing a glass component and a metal is applied by a method such as dipping.
  • a baking process is performed to form the base electrode layer 21.
  • the temperature of the baking process is preferably 500° C. or higher and 900° C. or lower.
  • the time of the baking process is preferably 30 minutes or higher and 2 hours or lower.
  • the atmosphere of the baking process is preferably a reducing atmosphere containing, for example, H 2 O or H 2 .
  • a plating layer 23 is formed on the surface of the base electrode layer 21.
  • a Ni plating layer is formed on the baked layer. This Ni plating layer becomes the inner plating layer 24.
  • a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the surface plating layer 25.
  • the Ni plating layer and the Sn plating layer are formed in sequence, for example, by barrel plating. In this manner, the multilayer ceramic capacitor 1 is obtained.
  • FIG. 8 is a plan view of a ceramic green sheet 30 on which an electrode paste 31 and a step paste 32 are applied.
  • the shapes of the patterns of the electrode paste 31 and the step paste 32 applied to the ceramic green sheet 30 are different between FIG. 7 and FIG. 8.
  • the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between two electrode patterns arranged in the length direction L.
  • the electrode patterns are arranged in four columns in the length direction L and five rows in the width direction W.
  • the step paste 32 is applied between the first electrode pattern and the second electrode pattern, and between the third electrode pattern and the fourth electrode pattern, in the four electrode patterns arranged in the length direction L.
  • the electrode paste 31 and the step paste 32 can be applied to the ceramic green sheet 30 in a variety of patterns depending on the type of multilayer ceramic capacitor 1 to be manufactured.
  • the ceramic green sheet 30 indicated by 801 in Fig. 8 is the first ceramic green sheet 30a.
  • the ceramic green sheet 30 indicated by 802 in Fig. 8 is the second ceramic green sheet 30b.
  • the first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked with a shift in the same manner as in the configuration shown in Fig. 7. Specifically, they are stacked with a shift of a distance d2 in the longitudinal direction L.
  • FIGS. 9(a) and 9(b) are diagrams showing the LT cross section of the laminated ceramic green sheets 30.
  • FIGS. 9(a) and 9(b) in order to simplify the configuration, only two ceramic green sheets 30 are illustrated as an example. In the following description, the two ceramic green sheets 30 are referred to as a laminate 40.
  • Lines L1 and L2 shown in FIG. 9(a) indicate cutting lines. These lines L1 and L2 correspond to the lines L1 and L2 shown in FIG. 8.
  • FIG. 9(a) shows the laminate 40 before cutting.
  • FIG. 9(b) shows the laminate 40 after cutting along the lines L1 and L2.
  • a central portion 32b in the longitudinal direction L of the pattern of the step paste 32 in the second ceramic green sheet 30b is aligned with an end portion 31a in the longitudinal direction L of the pattern of the electrode paste 31 in the first ceramic green sheet 30a in the longitudinal direction L. That is, the central portion 32b of the pattern of the step paste 32 and the end portion 31a of the pattern of the electrode paste 31 are both located on the line L2.
  • (After disconnection) 9B shows the laminate 40 after cutting.
  • the laminate 40 cut along the lines L1 and L2 has a step layer 5 formed in the L gap 51. This is because the ceramic green sheets 30 are stacked with a shift so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b have the positional relationship described above.
  • the cut surface generated by cutting along line L1 is defined as a first cut surface 41.
  • the cut surface generated by cutting along line L2 is defined as a second cut surface 42.
  • the first cut surface 41 corresponds to a first end surface 62a of the laminate 2.
  • the second cut surface 42 corresponds to a second end surface 62b of the laminate 2.
  • "corresponding" means a portion of the laminate 2 that corresponds when the laminate 40 is fired to become the laminate 2.
  • the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a are exposed.
  • the second cut surface 42 of the laminate 40, in the stacking direction T the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5 are exposed.
  • the portions where the step paste 32 is arranged become the first L gap 51a and the second L gap 51b, respectively.
  • the step paste 32 contains a Si component for forming the Si segregation layer 14.
  • This Si component migrates through the step paste 32 and adheres to the internal electrode layer 10.
  • the Si component is a liquid phase component. Therefore, the Si component can move across the dielectric material and approach the internal electrode layer. Specifically, the Si component adheres to the surface of the extraction electrode portion 12 and at least a part of the end and surface of the counter electrode portion 11. The Si component adhered to each internal electrode layer 10 forms the Si segregation layer 14.
  • the method for forming the Si segregation layer 14 is not limited to the above-mentioned method of blending the Si component into the step paste 32.
  • Another method for forming the Si segregation layer 14 is to apply the Si component to the L gap 51. In this method, the Si component is applied by printing or the like to an application pattern of the electrode paste 31 corresponding to the portion where the Si segregation layer 14 is to be formed.
  • Another method for forming the Si segregation layer 14 is to impregnate the WT end face of the laminated chip before firing, i.e., the face corresponding to the end face 62 of the laminated body 2, with the Si component.
  • the multilayer ceramic capacitor 1 of this embodiment is provided with the Si segregation layer 14 in the L gap 51. This can improve the reliability of the multilayer ceramic capacitor 1. This is because the Si segregation layer 14 has a high IR (insulation resistance).
  • Fig. 10 is a diagram showing the results of the high temperature load reliability test for the comparative example and the example.
  • the method of the high temperature load reliability test is as follows. For each of the comparative example and the examples 1 to 8, 100 samples were prepared. The samples were mounted on a glass epoxy board using eutectic solder. The thickness of the dielectric layer in the sample was set to 0.5 ⁇ m. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy board was placed in a high temperature chamber, and a voltage of 6.3 V was applied to each sample in an environment of 150° C.
  • the insulation resistance value was measured after 200 hours and after 500 hours.
  • the initial insulation resistance value was compared with the insulation resistance value after aging, and a sample with an insulation resistance value that decreased by one digit or more was determined to be defective. As shown in FIG. 10, no defects occurred in the sample having the Si segregation layer after 200 hours. Furthermore, the number of defects was suppressed to 5 or less even after 500 hours.
  • FIG. 11 is a diagram showing the evaluation results of the dielectric constant and the mean time to failure for the comparative example and the example.
  • the thickness of the dielectric layer in the sample was set to four types ranging from 0.3 ⁇ m to 0.6 ⁇ m. By varying the thickness of the dielectric layer, samples with different element thicknesses were produced. In addition, the thickness of the Si segregation layer was set to 0.07 ⁇ m and 0.08 ⁇ m.
  • Si has a low dielectric constant. Therefore, a decrease in dielectric constant was observed in samples with a Si segregation layer. Also, an improvement in MTTF (Mean Time To Failure) was observed in samples with a Si segregation layer.
  • the dielectric layer includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together, a laminate including a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction; external electrodes provided on the first end surface and the second end surface; Equipped with the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is extended to the first end face, the second internal electrode layer is extended to the second end face, the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer; an L-gap region is an area disposed on the first end face side, in which the first internal electrode layers do not overlap with each other in the stacking direction,
  • the thickness of the Si segregation layer is 0.03 ⁇ m or more and 0.15 ⁇ m or less.
  • the Si segregation layer is present at an end portion in the width direction of the first internal electrode layer and an end portion in the width direction of the second internal electrode;
  • the thickness of the dielectric layer is 0.4 ⁇ m or more and 0.5 ⁇ m or less.

Abstract

The present invention provides a multilayer ceramic capacitor (1) in which the occurrence of dielectric breakdown is further suppressed. The multilayer ceramic capacitor (1) comprises: a laminate (2) including a plurality of dielectric layers (4) and a plurality of internal electrode layers (10) stacked on one another; and external electrodes (20) provided on a first end surface (62a) and a second end surface (62b). The internal electrode layers (10) comprise first internal electrode layers (10a) and second internal electrode layers (10b), the first internal electrode layers (10a) being led to the first end surface (62a), and the second internal electrode layers (10b) being led to the second end surface (62b). The external electrodes (20) include a first external electrode (20a) connected to the first internal electrode layers (10a) and a second external electrode (20b) connected to the second internal electrode layers (10b). A region that is disposed on the first end surface (62a) side and in which the first internal electrode layers (10a) do not overlap each other in the stacking direction (T), and a region that is disposed on the second end surface (62b) side and in which the second internal electrode layers (10b) do not overlap each other in the stacking direction (T) are defined as L gap regions (51). The L gap regions (51) comprise Si segregation layers (14).

Description

積層セラミックコンデンサMultilayer Ceramic Capacitors
　本発明は、積層セラミックコンデンサに関する。 The present invention relates to a multilayer ceramic capacitor.
　積層セラミックコンデンサが小型化し、かつ大容量化すると、積層セラミックコンデンサに絶縁破壊が生じ易くなる。特許文献１には、この絶縁破壊を抑制することを目的として、誘電体層の内部電極のエッジ部近傍の領域の少なくとも一部を他の領域よりも耐電圧の高い誘電体磁器で形成する技術が記載されている。 As multilayer ceramic capacitors become smaller and their capacitance increases, they become more susceptible to dielectric breakdown. Patent Document 1 describes a technology for preventing this dielectric breakdown by forming at least a portion of the area near the edge of the internal electrode of the dielectric layer from a dielectric ceramic that has a higher withstand voltage than other areas.
特開平１１－３１７３２１号公報Japanese Patent Application Laid-Open No. 11-317321
　さらなる小型大容量化を目的に、積層セラミックコンデンサの誘電体層の厚みは、さらに薄くなってきている。誘電体層の厚みが薄くなることで、絶縁抵抗値が低下する。特に積層体の端面側で同じ外部電極に接続する内部電極同士が重なる領域では、構造的に内部電極が湾曲しやすい。そのため、誘電体層の厚みが局所的に低下し、絶縁破壊がより生じやすくなっている。そこで、本発明は、絶縁破壊の発生がより抑制された積層セラミックコンデンサを提供することを課題とする。 In order to further miniaturize and increase capacitance, the thickness of the dielectric layers in multilayer ceramic capacitors is becoming thinner. As the thickness of the dielectric layers becomes thinner, the insulation resistance value decreases. In particular, in the region where internal electrodes connected to the same external electrode overlap on the end face side of the laminate, the internal electrodes are structurally prone to bending. This causes the thickness of the dielectric layers to decrease locally, making insulation breakdown more likely to occur. Therefore, the objective of the present invention is to provide a multilayer ceramic capacitor in which the occurrence of insulation breakdown is further suppressed.
　本発明の積層セラミックコンデンサは、積層された複数の誘電体層と複数の内部電極層とを含み、積層方向に相対する第１の主面及び第２の主面と、積層方向に直交する幅方向に相対する第１の側面及び第２の側面と、積層方向及び幅方向に直交する長さ方向に相対する第１の端面及び第２の端面とを備える積層体と、前記第１の端面及び第２の端面に設けられた外部電極と、を備え、前記内部電極層は第１の内部電極層と第２の内部電極層とを備え、前記第１の内部電極層は、前記第１の端面へ引き出され、前記第２の内部電極層は、前記第２の端面へ引き出され、前記外部電極は、前記第１の内部電極層に接続された第１の外部電極、及び、前記第２の内部電極層に接続された第２の外部電極を含み、前記第１の端面側に配置され、前記第１の内部電極層同士が前記積層方向において重なり合わない領域、及び、前記第２の端面側に配置され、前記第２の内部電極層同士が前記積層方向において重なり合わない領域をＬギャップ領域とし、前記Ｌギャップ領域は、Ｓｉ偏析層を備える。 The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the lamination direction and the width direction, and an external electrode provided on the first end surface and the second end surface, the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is drawn out to the first end surface, the second internal electrode layer is drawn out to the second end surface, the external electrode includes a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, and the first end surface side is a region where the first internal electrode layers do not overlap with each other in the lamination direction, and the second end surface side is a region where the second internal electrode layers do not overlap with each other in the lamination direction, and the L gap region includes a Si segregation layer.
　本発明によれば、絶縁破壊の発生がより抑制された積層セラミックコンデンサを提供することができる。 The present invention provides a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed.
本実施形態の積層セラミックコンデンサの斜視図である。1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; 図１のＩ－Ｉ線断面図である。2 is a cross-sectional view taken along line II in FIG. 1. 図１のＩＩ－ＩＩ線断面図である。2 is a cross-sectional view taken along line II-II of FIG. 1. 本実施形態の積層セラミックコンデンサのＬＴ断面の一部を示す図である。2 is a diagram showing a portion of an LT cross section of the multilayer ceramic capacitor of the present embodiment. FIG. 本実施形態の積層セラミックコンデンサのＷＴ断面の一部を示す図である。2 is a diagram showing a portion of a WT cross section of the multilayer ceramic capacitor of the present embodiment. FIG. 本実施形態の積層セラミックコンデンサの他の構成のＷＴ断面の一部を示す図である。11 is a diagram showing a portion of a WT cross section of another configuration of the multilayer ceramic capacitor according to the present embodiment. FIG. 本実施形態におけるセラミックグリーンシートの平面図である。FIG. 2 is a plan view of a ceramic green sheet according to the embodiment. 本実施形態における他の構成のセラミックグリーンシートの平面図である。FIG. 11 is a plan view of a ceramic green sheet having another configuration in the present embodiment. （ａ）及び（ｂ）は、積層されたセラミックグリーンシートのＬＴ断面を示す図である。4A and 4B are diagrams showing LT cross sections of laminated ceramic green sheets. 高温負荷信頼性試験の結果を示す図である。FIG. 13 is a diagram showing the results of a high-temperature load reliability test. 誘電率及び平均故障時間の結果を示す図である。FIG. 13 shows the results of dielectric constant and mean time to failure.
　以下、添付の図面を参照しながら本発明の積層セラミックコンデンサ１の実施形態の一例について説明する。 Below, an example of an embodiment of the multilayer ceramic capacitor 1 of the present invention will be described with reference to the attached drawings.
（積層セラミックコンデンサの外形）
　図１に基づいて、積層セラミックコンデンサ１の外観の概要を説明する。図１は、本実施形態の積層セラミックコンデンサ１を示す斜視図である。積層セラミックコンデンサ１は、積層体２及び外部電極２０を備える。 (External view of multilayer ceramic capacitor)
The outline of the appearance of the multilayer ceramic capacitor 1 will be described with reference to Fig. 1. Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of the present embodiment. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20.
（方向の定義）
　図面には、適宜、Ｌ方向、Ｗ方向及びＴ方向が示されている。Ｌ方向は、積層セラミックコンデンサ１の長さ方向Ｌである。Ｗ方向は、積層セラミックコンデンサ１の幅方向Ｗである。Ｔ方向は、積層セラミックコンデンサ１の積層方向Ｔである。これにより、図２に示す断面はＬＴ断面といわれ、図３に示す断面はＷＴ断面といわれる。長さ方向Ｌ、幅方向Ｗ及び積層方向Ｔは、必ずしも互いに直交する関係でなくてもよい。長さ方向Ｌ、幅方向Ｗ及び積層方向Ｔは、互いに交差する関係であってもよい。 (Direction definition)
In the drawings, an L direction, a W direction, and a T direction are appropriately shown. The L direction is the length direction L of the multilayer ceramic capacitor 1. The W direction is the width direction W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. As a result, the cross section shown in FIG. 2 is called an LT cross section, and the cross section shown in FIG. 3 is called a WT cross section. The length direction L, the width direction W, and the stacking direction T do not necessarily have to be perpendicular to each other. The length direction L, the width direction W, and the stacking direction T may intersect each other.
（積層体の外形）
　積層体２は、略直方体型の形状を有する。積層体２は、２つの主面６１、２つの端面６２及び２つの側面６３を有する。主面６１は、積層方向Ｔに対向する面である。端面６２は、長さ方向Ｌに対向する面である。側面６３は、幅方向Ｗに対向する面である。２つの主面６１のうちの一方を第１の主面６１ａとし、他方を第２の主面６１ｂとする。２つの端面６２のうちの一方を第１の端面６２ａとし、他方を第２の端面６２ｂとする。２つの側面６３のうち一方を第１の側面６３ａとし、他方を第２の側面６３ｂとする。図１には第２の主面６１ｂ及び第１の側面６３ａが示されている。 (Outer shape of laminate)
The laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63. The main surface 61 is a surface facing the stacking direction T. The end surface 62 is a surface facing the length direction L. The side surface 63 is a surface facing the width direction W. One of the two main surfaces 61 is a first main surface 61a, and the other is a second main surface 61b. One of the two end surfaces 62 is a first end surface 62a, and the other is a second end surface 62b. One of the two side surfaces 63 is a first side surface 63a, and the other is a second side surface 63b. The second main surface 61b and the first side surface 63a are shown in FIG. 1.
　積層体２の稜線及び角部には、丸みがつけられていることが好ましい。稜線とは、積層体２の２面が交わる部分である。角部とは、積層体２の３面が交る部分である。なお、積層体２の大きさは特には限定されない。 The ridges and corners of the laminate 2 are preferably rounded. A ridge is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect. The size of the laminate 2 is not particularly limited.
（積層体の構造）
　積層体２は、複数の誘電体層４及び複数の内部電極層１０を含む。以下、積層体２の断面図を参照しながら、積層体２の構造を説明する。 (Structure of Laminate)
The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2.
（積層体の内部構造（ＬＴ断面））
　図２に基づいて、積層体２の内部構造について説明する。図２は、図１に示す積層セラミックコンデンサ１のＩ－Ｉ線断面図である。図２は、積層セラミックコンデンサ１のＬＴ断面を示す。積層体２は、複数の誘電体層４及び複数の内部電極層１０を含む。複数の誘電体層４及び複数の内部電極層１０は、互いに積層方向Ｔに積層されている。 (Internal structure of laminate (LT cross section))
The internal structure of the laminate 2 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view of the laminated ceramic capacitor 1 shown in Fig. 1 taken along line II. Fig. 2 shows an LT cross-section of the laminated ceramic capacitor 1. The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in a stacking direction T.
（内層部と外層部）
　積層体２は、積層方向Ｔにおいて、内層部５３及び２つの外層部５４に区分される。外層部５４は、第１の外層部５４ａ及び第２の外層部５４ｂを含む。第１の外層部５４ａ及び第２の外層部５４ｂは、内層部５３を積層方向Ｔにおいて挟む位置に位置している。 (Inner and outer layers)
The laminate 2 is divided into an inner layer portion 53 and two outer layer portions 54 in the stacking direction T. The outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b. The first outer layer portion 54a and the second outer layer portion 54b are located at positions sandwiching the inner layer portion 53 in the stacking direction T.
　内層部５３には、複数の誘電体層４及び複数の内部電極層１０が配置されている。内層部５３では、複数の内部電極層１０が誘電体層４を介して対向している。そのため、内層部５３には、静電容量が形成される。そのため、内層部５３は、積層体２のなかで実質的にコンデンサとして機能する部分である。これより、内層部５３は、有効部ともいわれる。 In the inner layer portion 53, a plurality of dielectric layers 4 and a plurality of internal electrode layers 10 are arranged. In the inner layer portion 53, the plurality of internal electrode layers 10 face each other via the dielectric layer 4. Therefore, a capacitance is formed in the inner layer portion 53. Therefore, the inner layer portion 53 is the portion of the laminate 2 that essentially functions as a capacitor. For this reason, the inner layer portion 53 is also called the effective portion.
　第１の外層部５４ａは、外層部５４のうちで、積層体２の第１の主面６１ａの側に位置する部分である。第２の外層部５４ｂは、外層部５４のうちで、積層体２の第２の主面６１ｂの側に位置する部分である。具体的には、第１の外層部５４ａは、複数の内部電極層１０のうち第１の主面６１ａに最も近い内部電極層１０と第１の主面６１ａとの間の部分である。第２の外層部５４ｂは、複数の内部電極層１０のうち第２の主面６１ｂに最も近い内部電極層１０と第２の主面６１ｂとの間の部分である。第１の外層部５４ａ及び第２の外層部５４ｂには、内部電極層１０は配置されていない。第１の外層部５４ａ及び第２の外層部５４ｂには、複数の誘電体層４のうち、内層部５３のための誘電体層４を除く残りの誘電体層４が配置されている。第１の外層部５４ａ及び第２の外層部５４ｂは、内層部５３の保護層として機能する。 The first outer layer portion 54a is a portion of the outer layer portion 54 located on the side of the first main surface 61a of the laminate 2. The second outer layer portion 54b is a portion of the outer layer portion 54 located on the side of the second main surface 61b of the laminate 2. Specifically, the first outer layer portion 54a is a portion between the internal electrode layer 10 closest to the first main surface 61a among the multiple internal electrode layers 10 and the first main surface 61a. The second outer layer portion 54b is a portion between the internal electrode layer 10 closest to the second main surface 61b among the multiple internal electrode layers 10 and the second main surface 61b. No internal electrode layer 10 is arranged in the first outer layer portion 54a and the second outer layer portion 54b. The remaining dielectric layers 4 of the multiple dielectric layers 4, excluding the dielectric layer 4 for the internal layer portion 53, are arranged in the first outer layer portion 54a and the second outer layer portion 54b. The first outer layer 54a and the second outer layer 54b function as protective layers for the inner layer 53.
（誘電体層）
　誘電体層４は、内層部５３に配置された誘電体層４と、外層部５４に配置された誘電体層４とに分類することができる。内層部５３に配置された誘電体層４を、内層誘電体層４ａとする。外層部５４に配置された誘電体層４を、外層誘電体層４ｂとする。 (Dielectric Layer)
The dielectric layers 4 can be classified into a dielectric layer 4 arranged in the inner layer portion 53 and a dielectric layer 4 arranged in the outer layer portion 54. The dielectric layer 4 arranged in the inner layer portion 53 is referred to as an inner dielectric layer 4a. The dielectric layer 4 arranged in the outer layer portion 54 is referred to as an outer dielectric layer 4b.
（誘電体層の層数）
　積層体２に積層される誘電体層４は、例えば、５層以上２０００層以下とすることができる。 (Number of dielectric layers)
The number of dielectric layers 4 stacked on the laminate 2 may be, for example, 5 to 2000.
（誘電体層の材料）
　誘電体層４の材料としては、例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３、ＣａＺｒＯ３などの主成分からなる誘電体セラミックを用いることができる。また、これらの主成分にＭｎ化合物、Ｆｅ化合物、Ｃｒ化合物、Ｃｏ化合物、Ｎｉ化合物などの副成分を添加したものを用いてもよい。 (Dielectric Layer Material)
The material of the dielectric layer 4 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3 , CaTiO3 , SrTiO3 , or CaZrO3 . In addition, a material in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components may also be used.
（誘電体層の厚み）
　誘電体層４の厚みは、例えば、０．３μｍ以上０．６μｍ以下とすることができる。 (Thickness of dielectric layer)
The thickness of the dielectric layer 4 can be, for example, not less than 0.3 μm and not more than 0.6 μm.
（内部電極層）
　内部電極層１０は、第１の内部電極層１０ａ及び第２の内部電極層１０ｂに分類することができる。第１の内部電極層１０ａは、第１の外部電極２０ａに接続された内部電極層１０である。第２の内部電極層１０ｂは、第２の外部電極２０ｂに接続された内部電極層１０である。第１の内部電極層１０ａは、第１の端面６２ａから、第２の端面６２ｂに向かって延在する。第２の内部電極層１０ｂは、第２の端面６２ｂから、第１の端面６２ａに向かって延在する。 (internal electrode layer)
The internal electrode layers 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is an internal electrode layer 10 connected to a first external electrode 20a. The second internal electrode layer 10b is an internal electrode layer 10 connected to a second external electrode 20b. The first internal electrode layer 10a extends from a first end face 62a toward a second end face 62b. The second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.
（対向部と引き出し部）
　第１の内部電極層１０ａ及び第２の内部電極層１０ｂは、それぞれ、対向電極部１１及び引き出し電極部１２を有する。
　対向電極部１１は、内部電極層１０において、第１の内部電極層１０ａと第２の内部電極層１０ｂとが積層方向Ｔにおいて対向する部分である。引き出し電極部１２は、内部電極層１０において、対向電極部１１から、積層体２の第１の端面６２ａ又は第２の端面６２ｂまで引き出された部分である。 (Facing part and pull-out part)
The first internal electrode layer 10 a and the second internal electrode layer 10 b each have a counter electrode portion 11 and an extraction electrode portion 12 .
The opposing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The extraction electrode portion 12 is a portion of the internal electrode layer 10 that is extracted from the opposing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.
　第１の内部電極層１０ａの対向電極部１１を第１の対向電極部１１ａとする。第１の内部電極層１０ａの引き出し電極部１２を第１の引き出し電極部１２ａとする。第１の引き出し電極部１２ａは、第１の対向電極部１１ａから、積層体２の第１の端面６２ａまで引き出された部分である。 The opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a. The extraction electrode portion 12 of the first internal electrode layer 10a is referred to as the first extraction electrode portion 12a. The first extraction electrode portion 12a is a portion that is extracted from the first opposing electrode portion 11a to the first end surface 62a of the laminate 2.
　同様に、第２の内部電極層１０ｂの対向電極部１１を第２の対向電極部１１ｂとする。第２の内部電極層１０ｂの引き出し電極部１２を第２の引き出し電極部１２ｂとする。第２の引き出し電極部１２ｂは、第２の対向電極部１１ｂから、積層体２の第２の端面６２ｂまで引き出された部分である。 Similarly, the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b. The extraction electrode portion 12 of the second internal electrode layer 10b is referred to as the second extraction electrode portion 12b. The second extraction electrode portion 12b is a portion that is extracted from the second opposing electrode portion 11b to the second end surface 62b of the laminate 2.
（内部電極層の層数）
　内部電極層１０は、例えば、１０層以上２０００層以下とすることができる。この内部電極層１０の層数は、第１の内部電極層１０ａの層数及び第２の内部電極層１０ｂの層数を含む層数である。 (Number of internal electrode layers)
The number of the internal electrode layers 10 may be, for example, from 10 to 2000. The number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.
（内部電極層の厚み）
　内部電極層１０の厚みは、例えば、０．１μｍ以上５．０μｍ以下、好ましくは、０．２μｍ以上２．０μｍ以下とすることができる。内部電極層１０の厚みが０．５μｍ以上である場合には、外部電極２０の金属層をめっきにより形成する際に、めっき膜が成長しやすくなる。 (Thickness of internal electrode layer)
The thickness of the internal electrode layer 10 can be, for example, 0.1 μm to 5.0 μm, preferably 0.2 μm to 2.0 μm. When the thickness of the internal electrode layer 10 is 0.5 μm or more, a plating film is likely to grow when the metal layer of the external electrode 20 is formed by plating.
（内部電極層の材料）
　内部電極層１０の材料は、例えば、Ｎｉ、Ｃｕ、Ａｇ、Ｐｄ、及びＡｕなどの金属や、ＮｉとＣｕとの合金やＡｇとＰｄとの合金などとすることができる。内部電極層１０の材料は、それに加えて、誘電体層４に含まれるセラミックと同一組成系の誘電体粒子を含んでいてもよい。 (Material of the internal electrode layer)
The material of the internal electrode layer 10 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, an alloy of Ni and Cu, an alloy of Ag and Pd, etc. In addition, the material of the internal electrode layer 10 may contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 4.
（電極対向部）
　積層体２の長さ方向Ｌの区分について説明する。積層体２は、長さ方向Ｌにおいて、電極対向部５０及びＬギャップ（Ｌギャップ領域）５１に区分することができる。長さ方向Ｌの区分における電極対向部５０を、Ｌ対向部５０ａとする。また、Ｌギャップ５１は、第１のＬギャップ５１ａ及び第２のＬギャップ５１ｂを含む。 (Electrode opposing portion)
The division of the laminate 2 in the longitudinal direction L will be described. The laminate 2 can be divided into an electrode opposing portion 50 and an L gap (L gap region) 51 in the longitudinal direction L. The electrode opposing portion 50 in the division in the longitudinal direction L is referred to as an L opposing portion 50a. The L gap 51 includes a first L gap 51a and a second L gap 51b.
　Ｌ対向部５０ａは、第１の内部電極層１０ａと第２の内部電極層１０ｂとが積層方向Ｔにおいて対向する部分に対応する。Ｌ対向部５０ａには容量が形成される。これより、Ｌ対向部５０ａは、有効部ともいわれる。 The L-opposing portion 50a corresponds to the portion where the first internal electrode layer 10a and the second internal electrode layer 10b oppose each other in the stacking direction T. A capacitance is formed in the L-opposing portion 50a. For this reason, the L-opposing portion 50a is also called the effective portion.
（Ｌギャップ）
　Ｌギャップ５１は、積層体２の長さ方向Ｌにおいて、第１の内部電極層１０ａと第２の内部電極層１０ｂとが積層方向Ｔに対向しない部分である。Ｌギャップ５１のうち、第１のＬギャップ５１ａは、Ｌ対向部５０ａと第１の端面６２ａとの間である。第２のＬギャップ５１ｂは、Ｌ対向部５０ａと第２の端面６２ｂとの間である。 (L Gap)
The L gap 51 is a portion in the longitudinal direction L of the laminate 2 where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the stacking direction T. Of the L gaps 51, the first L gap 51a is between the L opposing portion 50a and the first end face 62a. The second L gap 51b is between the L opposing portion 50a and the second end face 62b.
　第１のＬギャップ５１ａでは、積層方向Ｔにおいて、第１の内部電極層１０ａは配置されているが、第２の内部電極層１０ｂは配置されていない。第２のＬギャップ５１ｂでは、積層方向Ｔにおいて、第２の内部電極層１０ｂは配置されているが、第１の内部電極層１０ａは配置されていない。 In the first L gap 51a, the first internal electrode layer 10a is arranged in the stacking direction T, but the second internal electrode layer 10b is not arranged. In the second L gap 51b, the second internal electrode layer 10b is arranged in the stacking direction T, but the first internal electrode layer 10a is not arranged.
　第１のＬギャップ５１ａは、第１の対向電極部１１ａの第１の端面６２ａへの引出部として機能する。第２のＬギャップ５１ｂは、第２の対向電極部１１ｂの第２の端面６２ｂへの引出部として機能する。 The first L gap 51a functions as an extension to the first end surface 62a of the first opposing electrode portion 11a. The second L gap 51b functions as an extension to the second end surface 62b of the second opposing electrode portion 11b.
　Ｌギャップ５１の長さ方向Ｌの長さは、例えば、積層体２の長さ方向Ｌの長さの１０％以上３０％以下とすることができる。また、Ｌギャップ５１の長さ方向Ｌの長さは、例えば、５μｍ以上３０μｍ以下とすることができる。 The length of the L gap 51 in the longitudinal direction L can be, for example, 10% to 30% of the length of the laminate 2 in the longitudinal direction L. The length of the L gap 51 in the longitudinal direction L can be, for example, 5 μm to 30 μm.
（外部電極）
　外部電極２０は、第１の外部電極２０ａ及び第２の外部電極２０ｂを含む。
（第１の外部電極）
　第１の外部電極２０ａは、積層体２の第１の端面６２ａに配置された外部電極２０である。第１の外部電極２０ａは、第１の内部電極層１０ａと電気的に接続されている。
（第２の外部電極）
　第２の外部電極２０ｂは、積層体２の第２の端面６２ｂに配置された外部電極２０である。第２の外部電極２０ｂは、第２の内部電極層１０ｂと電気的に接続されている。 (External electrode)
The external electrodes 20 include a first external electrode 20a and a second external electrode 20b.
(First External Electrode)
The first external electrode 20a is an external electrode 20 disposed on the first end surface 62a of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a.
(Second External Electrode)
The second external electrode 20b is an external electrode 20 disposed on the second end surface 62b of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.
（各面の外部電極）
　外部電極２０は、一方の端面６２から、２つの主面６１の一部まで及び２つの側面６３の一部まで延在する。 (External electrodes on each side)
The external electrode 20 extends from one end face 62 to parts of the two main faces 61 and to parts of the two side faces 63 .
（外部電極の層構成）
　外部電極２０の層構成を、図２に基づいてについて説明する。外部電極２０は、下地電極層２１及びめっき層２３を含む。めっき層２３は、内めっき層２４及び表めっき層２５を含む。これらの層は、積層体２の端面６２から、下地電極層２１、内めっき層２４、表めっき層２５の順に配置されている。詳しくは、第１の外部電極２０ａは、第１の下地電極層２１ａ及び第１のめっき層２３ａを含む。さらに第１のめっき層２３ａは、第１の内めっき層２４ａ及び第１の表めっき層２５ａを含む。同様に、第２の外部電極２０ｂは、第２の下地電極層２１ｂ及び第２のめっき層２３ｂを含む。さらに第２のめっき層２３ｂは、第２の内めっき層２４ｂ及び第２の表めっき層２５ｂを含む。 (Layer configuration of external electrodes)
The layer structure of the external electrode 20 will be described with reference to FIG. 2. The external electrode 20 includes a base electrode layer 21 and a plating layer 23. The plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged in the order of the base electrode layer 21, the inner plating layer 24, and the surface plating layer 25 from the end surface 62 of the laminate 2. In detail, the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a. The first plating layer 23a further includes a first inner plating layer 24a and a first surface plating layer 25a. Similarly, the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b. The second plating layer 23b further includes a second inner plating layer 24b and a second surface plating layer 25b.
（下地電極層）
　第１の下地電極層２１ａは、積層体２の第１の端面６２ａの上に配置されており、第１の端面６２ａを覆う。第１の下地電極層２１ａは、第１の端面６２ａから、第１の主面６１ａの一部、第２の主面６１ｂの一部、第１の側面６３ａの一部及び第２の側面６３ｂの一部にまで延在している。 (Base electrode layer)
The first base electrode layer 21a is disposed on and covers the first end face 62a of the laminate 2. The first base electrode layer 21a extends from the first end face 62a to a part of the first main surface 61a, a part of the second main surface 61b, a part of the first side surface 63a, and a part of the second side surface 63b.
　同様に、第２の下地電極層２１ｂは、積層体２の第２の端面６２ｂの上に配置されており、第２の端面６２ｂを覆う。第２の下地電極層２１ｂは、第２の端面６２ｂから、第１の主面６１ａの一部、第２の主面６１ｂの一部、第１の側面６３ａの一部及び第２の側面６３ｂの一部にまで延在している。 Similarly, the second base electrode layer 21b is disposed on the second end face 62b of the laminate 2 and covers the second end face 62b. The second base electrode layer 21b extends from the second end face 62b to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.
（焼き付け層）
　第１の下地電極層２１ａ及び第２の下地電極層２１ｂは、焼き付け層として構成されている。焼き付け層は、ガラス成分及び金属を含む。ガラス成分としては、Ｂ、Ｓｉ、Ｂａ、Ｍｇ、Ａｌ、Ｌｉなどから選ばれる少なくとも１つを含む。金属としては、例えば、Ｃｕ、Ｎｉ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕなどから選ばれる少なくとも１つを含む。焼き付け層は、複数層であってもよい。 (Baked layer)
The first base electrode layer 21a and the second base electrode layer 21b are configured as a baking layer. The baking layer includes a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer.
（めっき層）
　下地電極層２１の上のめっき層２３について説明する。前述のように、本実施形態では、めっき層２３は、内めっき層２４及び表めっき層２５を含む。めっき層２３を二層にする場合には、下層から、Ｎｉめっき層及びＳｎめっき層の順とすることが好ましい。すなわち、内めっき層２４がＮｉめっき層になり、表めっき層２５がＳｎめっき層になる。 (Plating layer)
The plating layer 23 on the base electrode layer 21 will be described. As described above, in this embodiment, the plating layer 23 includes the inner plating layer 24 and the surface plating layer 25. When the plating layer 23 is made of two layers, it is preferable that the plating layers are a Ni plating layer and a Sn plating layer from the bottom. That is, the inner plating layer 24 is a Ni plating layer, and the surface plating layer 25 is a Sn plating layer.
　Ｎｉめっき層は、下地電極層２１が積層セラミックコンデンサ１を実装する際のはんだによって侵食されることを防止することができる。Ｓｎめっき層は、積層セラミックコンデンサ１を実装する際のはんだの濡れ性を向上させ、実装を容易にすることができる。そのため、表めっき層２５をＳｎめっき層とすることで、外部電極２０に対するはんだの濡れ性を向上させることができる。めっき層一層あたりの厚みは、３μｍ以上９μｍ以下であることが好ましい。 The Ni plating layer can prevent the base electrode layer 21 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1, making mounting easier. Therefore, by making the top plating layer 25 a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved. The thickness of each plating layer is preferably 3 μm or more and 9 μm or less.
（積層体の内部構造（ＷＴ断面））
　図３に基づいて、積層体２の内部構造を説明する。図３は、図１に示す積層セラミックコンデンサ１のＩＩ－ＩＩ線断面図である。積層体２は、幅方向Ｗにおいて、電極対向部５０及びＷギャップ５２に区分される。幅方向Ｗの区分における電極対向部５０を、Ｗ対向部５０ｂとする。また、Ｗギャップ５２は、第１のＷギャップ５２ａ及び第２のＷギャップ５２ｂを含む。 (Internal structure of laminate (WT cross section))
The internal structure of the laminate 2 will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view of the laminate ceramic capacitor 1 shown in Fig. 1 taken along line II-II. The laminate 2 is divided into an electrode opposing portion 50 and a W gap 52 in the width direction W. The electrode opposing portion 50 in the section in the width direction W is referred to as a W opposing portion 50b. The W gap 52 includes a first W gap 52a and a second W gap 52b.
　Ｗ対向部５０ｂは、内部電極層１０が積層方向Ｔにおいて対向する部分である。Ｗギャップ５２は、幅方向Ｗにおいて、前記第１の内部電極層１０ａ及び前記第２の内部電極層１０ｂのいずれもが積層方向Ｔに配置されていない部分である。 The W opposing portion 50b is a portion where the internal electrode layers 10 face each other in the stacking direction T. The W gap 52 is a portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is arranged in the stacking direction T.
　Ｗギャップ５２のうち、第１のＷギャップ５２ａは、積層体２の幅方向Ｗおける、Ｗ対向部５０ｂと第１の側面６３ａとの間である。第２のＷギャップ５２ｂは、Ｗ対向部５０ｂと第２の側面６３ｂとの間である。 Of the W gaps 52, the first W gap 52a is between the W opposing portion 50b and the first side surface 63a in the width direction W of the laminate 2. The second W gap 52b is between the W opposing portion 50b and the second side surface 63b.
　第１のＷギャップ５２ａ及び第２のＷギャップ５２ｂは、Ｗ対向部５０ｂを挟み込むように配置されている。第１のＷギャップ５２ａ及び第２のＷギャップ５２ｂは、内部電極層１０の保護層として機能する。 The first W gap 52a and the second W gap 52b are arranged to sandwich the W opposing portion 50b. The first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.
　Ｗギャップ５２の幅方向Ｗの長さは、例えば、積層体２の幅方向Ｗの長さの２０％以上３０％以下とすることができる。また、Ｗギャップ５２の幅方向Ｗの長さは、例えば、５μｍ以上５０μｍ以下とすることができる。 The length of the width direction W of the W gap 52 can be, for example, 20% to 30% of the length of the width direction W of the laminate 2. In addition, the length of the width direction W of the W gap 52 can be, for example, 5 μm to 50 μm.
（積層セラミックコンデンサの大きさ）
　積層セラミックコンデンサ１の大きさ特には限定されない。積層セラミックコンデンサ１の大きさは、例えば下記のようにすることができる。積層体２及び外部電極２０を含む積層セラミックコンデンサ１の長さ方向Ｌの寸法をＬ寸法とする。Ｌ寸法は、０．２５ｍｍ以上１．０ｍｍ以下であることが好ましい。積層体２及び外部電極２０を含む積層セラミックコンデンサ１の積層方向Ｔの寸法をＴ寸法とする。Ｔ寸法は、０．１２５ｍｍ以上０．５ｍｍ以下であることが好ましい。積層体２及び外部電極２０を含む積層セラミックコンデンサ１の幅方向Ｗの寸法をＷ寸法とする。Ｗ寸法は、０．１２５ｍｍ以上０．５ｍｍ以下であることが好ましい。なお、積層体２及び外部電極２０の各部の長さは、マイクロメータ又は光学顕微鏡で測定することができる。 (Size of multilayer ceramic capacitor)
The size of the multilayer ceramic capacitor 1 is not particularly limited. The size of the multilayer ceramic capacitor 1 can be, for example, as follows. The dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the L dimension. The L dimension is preferably 0.25 mm or more and 1.0 mm or less. The dimension in the stacking direction T of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the T dimension. The T dimension is preferably 0.125 mm or more and 0.5 mm or less. The dimension in the width direction W of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 20 is defined as the W dimension. The W dimension is preferably 0.125 mm or more and 0.5 mm or less. The lengths of each part of the laminate 2 and the external electrodes 20 can be measured with a micrometer or an optical microscope.
（端子の構成）
　本実施形態では、積層セラミックコンデンサ１は、２端子の積層セラミックコンデンサであることを例として説明した。ただし、積層セラミックコンデンサ１は、２端子の積層セラミックコンデンサであることに限定されず、３端子以上の多端子の積層セラミックコンデンサとすることもできる。 (Terminal configuration)
In the present embodiment, the multilayer ceramic capacitor 1 has been described as a two-terminal multilayer ceramic capacitor as an example. However, the multilayer ceramic capacitor 1 is not limited to being a two-terminal multilayer ceramic capacitor, and may be a multi-terminal multilayer ceramic capacitor having three or more terminals.
（Ｓｉ偏析層）
　本実施形態の積層セラミックコンデンサ１は、Ｌギャップ５１にＳｉ偏析層１４を備えている。Ｓｉ偏析層１４とは、内部電極層１０などの表面に形成されるＳｉ層のことをいう。 (Si segregation layer)
The multilayer ceramic capacitor 1 of this embodiment includes a Si segregation layer 14 in the L gap 51. The Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 or the like.
　図４に基づいてＳｉ偏析層１４について説明する。図４は、本実施形態の積層セラミックコンデンサ１のＬＴ断面の一部を示す図である。図４は、図２に破線で示す領域Ｒ１を拡大した図に相当する。図４は、第１のＬギャップ５１ａ及びその近傍を示している。 The Si segregation layer 14 will be described with reference to FIG. 4. FIG. 4 is a diagram showing a portion of the LT cross section of the multilayer ceramic capacitor 1 of this embodiment. FIG. 4 corresponds to an enlarged view of the region R1 indicated by the dashed line in FIG. 2. FIG. 4 shows the first L gap 51a and its vicinity.
　第１のＬギャップ５１ａ及びその近傍において、内部電極層１０の表面には、Ｓｉ偏析層１４が形成されている。
（第１の内部電極層）
　第１の内部電極層１０ａについては、第１の引き出し電極部１２ａの全体、及び、第１の対向電極部１１ａの少なくとも一部の表面に、Ｓｉ偏析層１４が形成されている。第１の対向電極部１１ａの少なくとも一部とは、第１の対向電極部１１ａの、第１のＬギャップ５１ａに近い部分に対応する。 A Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in and near the first L gap 51a.
(First internal electrode layer)
For the first internal electrode layer 10a, a Si segregation layer 14 is formed on the entire surface of the first lead electrode portion 12a and at least a part of the surface of the first opposing electrode portion 11a. The at least a part of the first opposing electrode portion 11a corresponds to a part of the first opposing electrode portion 11a close to the first L gap 51a.
（第２の内部電極層）
　第２の内部電極層１０ｂについては、第２の対向電極部１１ｂの少なくとも一部の表面に、Ｓｉ偏析層１４が形成されている。第２の対向電極部１１ｂの少なくとも一部とは、第２の対向電極部１１ｂの、第１のＬギャップ５１ａに近い部分に対応する。 (Second Internal Electrode Layer)
For the second internal electrode layer 10b, a Si segregation layer 14 is formed on at least a portion of the surface of the second opposing electrode portion 11b. The at least a portion of the second opposing electrode portion 11b corresponds to a portion of the second opposing electrode portion 11b that is close to the first L gap 51a.
　第１の内部電極層１０ａ及び第２の内部電極層１０ｂについて、第１のＬギャップ５１ａに近い部分とは、第１のＬギャップ５１ａとＬ対向部５０ａとの境界から、Ｌ対向部５０ａの方向に、例えば、５０μｍ程度の部分をいう。 With respect to the first internal electrode layer 10a and the second internal electrode layer 10b, the portion close to the first L gap 51a refers to the portion, for example, about 50 μm from the boundary between the first L gap 51a and the L opposing portion 50a in the direction of the L opposing portion 50a.
　内部電極層１０の端部を電極端部１０ｅとする。内部電極層１０の端部とは、内部電極層１０の積層方向Ｔに並行な端面を意味する。図４には、第２の内部電極層１０ｂの電極端部１０ｅが示されている。図４に示す構成では、この電極端部１０ｅには、積層方向Ｔに並行な方向の全体にわたってＳｉ偏析層１４が形成されている。 The end of the internal electrode layer 10 is referred to as the electrode end 10e. The end of the internal electrode layer 10 means the end surface parallel to the stacking direction T of the internal electrode layer 10. FIG. 4 shows the electrode end 10e of the second internal electrode layer 10b. In the configuration shown in FIG. 4, a Si segregation layer 14 is formed over the entire electrode end 10e in the direction parallel to the stacking direction T.
　以上のように、Ｓｉ偏析層１４は、内部電極層１０の長さ方向Ｌと並行な面のみならず、電極端部１０ｅにおける積層方向Ｔと並行な面にも形成されている。このように、第１のＬギャップ５１ａ及びその近傍部分において、内部電極層１０の表面には、Ｓｉ偏析層１４が形成されている。 As described above, the Si segregation layer 14 is formed not only on the surface parallel to the length direction L of the internal electrode layer 10, but also on the surface parallel to the stacking direction T at the electrode end 10e. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L gap 51a and its vicinity.
（浮島電極）
　図４に示す例では、第１のＬギャップ５１ａに、浮島形状の浮島電極１３が形成されている。この浮島電極１３の表面にも、Ｓｉ偏析層１４が形成されている。なお、浮島電極１３は、内部電極層１０を形成する際に意図的に形成することができる。または、内部電極層１０を形成する際に、意図せずに形成される場合もある。 (Floating island electrode)
4, a floating island electrode 13 having a floating island shape is formed in the first L gap 51a. A Si segregation layer 14 is also formed on the surface of this floating island electrode 13. The floating island electrode 13 can be formed intentionally when forming the internal electrode layer 10. Alternatively, it may be formed unintentionally when forming the internal electrode layer 10.
（第２のＬギャップ）
　以上、第１のＬギャップ５１ａを例にＳｉ偏析層１４について説明した。ただし、第２のＬギャップ５１ｂも同様の構成を有している。すなわち、第２のＬギャップ５１ｂにおける第２の引き出し電極部１２ｂ及び第１の対向電極部１１ａなどにも、第１のＬギャップ５１ａにおける第１の引き出し電極部１２ａ及び第２の対向電極部１１ｂなどと同様のＳｉ偏析層１４が形成されている。 (Second L Gap)
The Si segregation layer 14 has been described above using the first L gap 51a as an example. However, the second L gap 51b has a similar configuration. That is, the second lead electrode portion 12b and the first opposing electrode portion 11a in the second L gap 51b also have the same Si segregation layer 14 as the first lead electrode portion 12a and the second opposing electrode portion 11b in the first L gap 51a.
（幅方向の電極端部）
　図５に基づいて、内部電極層１０の幅方向Ｗにおける電極端部１０ｅについて説明する。図５は、本発明の実施形態の積層セラミックコンデンサ１のＷＴ断面の一部を示す図である。なお、図５は模式図である。そのため、パターンの数などは、他の図面などと整合しない場合がある。 (Electrode end in width direction)
The electrode end portion 10e in the width direction W of the internal electrode layer 10 will be described with reference to Fig. 5. Fig. 5 is a diagram showing a part of the WT cross section of the multilayer ceramic capacitor 1 according to the embodiment of the present invention. Note that Fig. 5 is a schematic diagram. Therefore, the number of patterns, etc. may not be consistent with other drawings.
　図５に示すように、幅方向Ｗの電極端部１０ｅにもＳｉ偏析層１４は形成されている。詳しくは、Ｓｉ偏析層１４は、幅方向Ｗの電極端部１０ｅにおいても、積層方向Ｔに並行な方向の全体にわたって形成されている。また、Ｓｉ偏析層１４は、内部電極層１０の幅方向Ｗと並行な表面にも形成されている。ただし、Ｓｉ偏析層１４は、幅方向Ｗと並行な表面においては、その全体を覆うようには形成されていない。Ｓｉ偏析層１４は、電極端部１０ｅから所定の距離だけ、幅方向Ｗと並行な面に形成されている。図５にこの所定の距離を距離ｄ１で示す。距離ｄ１は、例えば、１μｍ以上５０μｍ以下とすることができる。 As shown in FIG. 5, the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W. More specifically, the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W over the entire direction parallel to the stacking direction T. The Si segregation layer 14 is also formed on the surface parallel to the width direction W of the internal electrode layer 10. However, the Si segregation layer 14 is not formed to cover the entire surface parallel to the width direction W. The Si segregation layer 14 is formed on a surface parallel to the width direction W a predetermined distance from the electrode end 10e. This predetermined distance is indicated as distance d1 in FIG. 5. Distance d1 can be, for example, 1 μm or more and 50 μm or less.
（Ｓｉ偏析層の他の構成）
　図６は、図５の領域Ｒ２について、他の構成を示す図である。図５に示した構成と、図６に示す構成とでは、内部電極層１０の表面において、Ｓｉ偏析層１４が形成されている位置が異なる。図５に示した構成では、領域Ｒ２に示すように、内部電極層１０の電極端部１０ｅには、積層方向Ｔの全体にわたってＳｉ偏析層１４が形成されていた。これに対して、図６に示す構成例では、Ｓｉ偏析層１４は、電極端部１０ｅの積層方向Ｔの全体にわたっては形成されていない。電極端部１０ｅの積層方向Ｔにおける両端部には、Ｓｉ偏析層１４が形成されている。一方、電極端部１０ｅの積層方向Ｔにおける中央部分には、Ｓｉ偏析層１４は形成されていない。そのため、電極端部１０ｅの積層方向Ｔにおける中央部からは、内部電極層１０が露出している。 (Other configurations of the Si segregation layer)
6 is a diagram showing another configuration of the region R2 in FIG. 5. The configuration shown in FIG. 5 and the configuration shown in FIG. 6 differ in the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10. In the configuration shown in FIG. 5, as shown in the region R2, the Si segregation layer 14 is formed over the entire stacking direction T at the electrode end 10e of the internal electrode layer 10. In contrast, in the configuration example shown in FIG. 6, the Si segregation layer 14 is not formed over the entire stacking direction T of the electrode end 10e. The Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T. On the other hand, the Si segregation layer 14 is not formed in the central portion of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central portion of the electrode end 10e in the stacking direction T.
　図５及び図６に示すように、Ｓｉ偏析層１４は、内部電極層１０の幅方向Ｗの電極端部１０ｅにおいて、その積層方向Ｔの全体に形成されていてもよく、また、積層方向Ｔの一部に形成されていてもよい。 As shown in Figures 5 and 6, the Si segregation layer 14 may be formed over the entire stacking direction T at the electrode end 10e in the width direction W of the internal electrode layer 10, or may be formed over a portion of the stacking direction T.
（Ｓｉ偏析層の厚み）
　Ｓｉ偏析層１４の厚みは、例えば、０．０１μｍ以上０．３０μｍ以下とすることができる。なお、Ｓｉ偏析層１４の厚みは、積層体２の断面を露出させ、走査型電子顕微鏡（ＳＥＭ）を用いて誘電体粒子とＳｉ偏析層を判別し、さらにエネルギー分散型Ｘ線分析（ＥＤＸ）を用いてその表面の元素解析を行うことで求めることができる。 (Thickness of Si segregation layer)
The thickness of the Si segregation layer 14 can be, for example, 0.01 μm or more and 0.30 μm or less. The thickness of the Si segregation layer 14 can be obtained by exposing a cross section of the laminate 2, distinguishing between dielectric particles and the Si segregation layer using a scanning electron microscope (SEM), and further performing elemental analysis of the surface using energy dispersive X-ray analysis (EDX).
（積層セラミックコンデンサの製造方法）
　積層セラミックコンデンサ１の製造方法を図７などに基づいて説明する。
（積層ブロックの作製）
　セラミックグリーンシート３０、内部電極層１０用の電極ペースト３１、及び段差層５用の段差ペースト３２を用意する。 (Manufacturing method of multilayer ceramic capacitors)
A method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to FIG.
(Preparation of laminated blocks)
A ceramic green sheet 30, an electrode paste 31 for the internal electrode layer 10, and a step paste 32 for the step layer 5 are prepared.
（段差層）
　まず、段差層５について説明する。積層体２の積層方向Ｔの長さは、電極対向部５０とＬギャップ５１とにおいて差が小さいことが好ましい。しかしながら、内層部５３では、電極対向部５０とＬギャップ５１とで、積層方向Ｔの長さが相違しやすくなる。電極対向部５０には誘電体層４及び内部電極層１０が積層される。これに対して、Ｌギャップ５１には誘電体層４、及び、内部電極層１０のうちで一方の外部電極２０に接続されている内部電極層１０のみ、が積層される。そのため、電極対向部５０とＬギャップ５１とで、積層方向Ｔの長さが相違しやすくなる。 (Step layer)
First, the step layer 5 will be described. It is preferable that the difference in length in the stacking direction T of the laminate 2 is small between the electrode facing portion 50 and the L gap 51. However, in the inner layer portion 53, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51. The dielectric layer 4 and the internal electrode layer 10 are stacked in the electrode facing portion 50. In contrast, the dielectric layer 4 and only the internal electrode layer 10 connected to one external electrode 20 among the internal electrode layers 10 are stacked in the L gap 51. Therefore, the length in the stacking direction T tends to differ between the electrode facing portion 50 and the L gap 51.
　そこで、Ｌギャップ５１と電極対向部５０との積層方向Ｔの長さの差を小さくするために、Ｌギャップ５１に追加の誘電体層４を配置する。この追加の誘電体層４を段差層５とする。段差層５は、誘電体層４と同様の成分を有することが好ましい。ただし、誘電体層４の成分は、これに限定されるものではない。 Therefore, in order to reduce the difference in length in the stacking direction T between the L gap 51 and the electrode opposing portion 50, an additional dielectric layer 4 is disposed in the L gap 51. This additional dielectric layer 4 is referred to as the step layer 5. It is preferable that the step layer 5 has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited to this.
　図４に段差層５を示す。図４に示すように、段差層５は、第１のＬギャップ５１ａにおいて、積層方向Ｔに対向する２つの第１の対向電極部１１ａの間に配置されている。段差層５が第２の内部電極層１０ｂの厚さを補うことによって、第１のＬギャップ５１ａとＬ対向部５０ａとの積層方向Ｔの長さの差を小さくすることができる。 The step layer 5 is shown in Figure 4. As shown in Figure 4, the step layer 5 is disposed in the first L gap 51a between two first opposing electrode portions 11a that face each other in the stacking direction T. The step layer 5 compensates for the thickness of the second internal electrode layer 10b, thereby making it possible to reduce the difference in length in the stacking direction T between the first L gap 51a and the L opposing portion 50a.
　また本実施形態では、段差ペースト３２に、Ｓｉ成分を配合しておく。このＳｉ成分は、後にＳｉ偏析層１４を形成する。なお、段差ペースト３２にＳｉ成分を添加しておくことは、Ｓｉ偏析層１４を形成する方法の一例である。 In addition, in this embodiment, a Si component is blended into the step paste 32. This Si component will later form the Si segregation layer 14. Note that adding a Si component to the step paste 32 is one example of a method for forming the Si segregation layer 14.
（ペーストの塗布）
　段差層５を形成する場合のセラミックグリーンシート３０の積層の概要について説明する。なお、電極ペースト３１及び段差ペースト３２のパターンの形状については、後に説明する。まず、セラミックグリーンシート３０に、前述の電極ペースト３１及び段差ペースト３２を所望のパターンで塗布する。セラミックグリーンシート３０への各ペーストの塗布は、例えば、スクリーン印刷やグラビア印刷などの方法により行うことができる。任意の印刷方法で、セラミックグリーンシート３０に所定のパターンで電極ペースト３１及び段差ペースト３２を印刷する。これにより、ペーストが印刷された内層部５３用のセラミックグリーンシート３０を得る。 (Paste application)
An outline of lamination of the ceramic green sheets 30 when forming the step layer 5 will be described. The pattern shapes of the electrode paste 31 and the step paste 32 will be described later. First, the above-mentioned electrode paste 31 and step paste 32 are applied to the ceramic green sheet 30 in a desired pattern. The application of each paste to the ceramic green sheet 30 can be performed by a method such as screen printing or gravure printing. The electrode paste 31 and step paste 32 are printed in a predetermined pattern on the ceramic green sheet 30 by any printing method. In this way, the ceramic green sheet 30 for the inner layer portion 53 on which the paste is printed is obtained.
（積層）
　内部電極層１０のパターンが印刷されていないセラミックグリーンシート３０を所定枚数積層する。これにより、外層部５４に対応する部分を作製する。この上に、ペーストが塗布された内層部５３用のセラミックグリーンシート３０を順次積層する。これにより、内層部５３に対応する部分が積層される。さらにその上に、もう一方の外層部５４用のセラミックグリーンシート３０を所定枚数積層する。これにより、積層シートを作製する。積層シートを静水圧プレスなどの手段により積層方向にプレスし、積層ブロックを作製する。 (Lamination)
A predetermined number of ceramic green sheets 30 on which the pattern of the internal electrode layer 10 is not printed are laminated. This creates a portion corresponding to the outer layer portion 54. On top of this, ceramic green sheets 30 for the inner layer portion 53 on which paste has been applied are sequentially laminated. This creates a portion corresponding to the inner layer portion 53. Furthermore, on top of that, a predetermined number of ceramic green sheets 30 for the other outer layer portion 54 are laminated. This creates a laminated sheet. The laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to create a laminated block.
（パターン）
　図７は、電極ペースト３１及び段差ペースト３２が塗布されたセラミックグリーンシート３０の平面図である。図７は、セラミックグリーンシート３０を積層方向Ｔから見た図である。図７の７０１及び７０２は、それぞれ、１枚のセラミックグリーンシート３０を示している。これらのセラミックグリーンシート３０を積層することで、積層シートを得ることができる。図７に示す例では、セラミックグリーンシート３０に１０個の電極用のパターンが電極ペースト３１により形成されている。電極用のパターンは、長さ方向Ｌに２列、幅方向Ｗに５行、配置されている。また、長さ方向Ｌに並ぶ２つの電極用のパターンの間には、段差ペースト３２が塗布されている。
　図７の７０１及び７０２に示す２枚のセラミックグリーンシート３０には、電極ペースト３１及び段差ペースト３２が同様のパターンで塗布されている。 (pattern)
7 is a plan view of the ceramic green sheet 30 on which the electrode paste 31 and the step paste 32 are applied. FIG. 7 is a view of the ceramic green sheet 30 as viewed from the lamination direction T. 701 and 702 in FIG. 7 each indicate one ceramic green sheet 30. By laminating these ceramic green sheets 30, a laminated sheet can be obtained. In the example shown in FIG. 7, ten electrode patterns are formed on the ceramic green sheet 30 using the electrode paste 31. The electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W. In addition, the step paste 32 is applied between two electrode patterns arranged in the length direction L.
An electrode paste 31 and a step paste 32 are applied in the same pattern to two ceramic green sheets 30 indicated by 701 and 702 in FIG.
（積層）
　図７の７０１及び７０２に示す２枚のセラミックグリーンシート３０を積層する際、長さ方向Ｌにずらして積層する。図７にずらす距離を距離ｄ２で示す。２枚のセラミックグリーンシート３０をずらして積層することで、第１のＬギャップ５１ａ及び第２のＬギャップ５１ｂのいずれにもＳｉ偏析層１４が形成された積層セラミックコンデンサ１を容易に作製することができる。これについては、後に説明する。 (Lamination)
When two ceramic green sheets 30 shown in 701 and 702 in Fig. 7 are laminated, they are laminated with a shift in the length direction L. The shift distance is indicated as a distance d2 in Fig. 7. By laminating two ceramic green sheets 30 with a shift, it is possible to easily manufacture a multilayer ceramic capacitor 1 in which a Si segregation layer 14 is formed in both the first L gap 51a and the second L gap 51b. This will be described later.
（積層チップの作製）
　積層ブロックを所定のサイズにカットし、積層チップを切り出す。このとき、バレル研磨などにより積層チップの角部及び稜線部に丸みをつけてもよい。 (Fabrication of stacked chips)
The laminated block is cut to a predetermined size to cut out laminated chips. At this time, corners and edges of the laminated chips may be rounded by barrel polishing or the like.
（焼成）
　次に、積層チップを焼成し積層体２を作製する。焼成温度は、セラミック層４や内部電極層１０の材料にもよるが、９００℃以上１４００℃以下であることが好ましい。 (Firing)
Next, the laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the ceramic layers 4 and the internal electrode layers 10, but is preferably 900° C. or higher and 1400° C. or lower.
（外部電極）
　次に、外部電極２０を形成する。
（下地電極層）
　積層体２の２つの端面６２に下地電極層２１となる導電性ペーストを塗布し、下地電極層２１を形成する。焼き付け層を形成するために、ガラス成分と金属とを含む導電性ペーストをディッピングなどの方法により塗布する。その後、焼き付け処理を行い、下地電極層２１を形成する。焼き付け処理の温度は、５００℃以上９００℃以下が好ましい。また、焼き付け処理の時間は、３０分以上２時間以下が好ましい。また、焼き付け処理の雰囲気は、例えば、Ｈ２ＯやＨ２を入れた還元雰囲気であることが好ましい。 (External electrode)
Next, the external electrodes 20 are formed.
(Base electrode layer)
A conductive paste that will become the base electrode layer 21 is applied to the two end faces 62 of the laminate 2 to form the base electrode layer 21. To form a baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping. Then, a baking process is performed to form the base electrode layer 21. The temperature of the baking process is preferably 500° C. or higher and 900° C. or lower. The time of the baking process is preferably 30 minutes or higher and 2 hours or lower. The atmosphere of the baking process is preferably a reducing atmosphere containing, for example, H 2 O or H 2 .
　次に、下地電極層２１の表面にめっき層２３を形成する。本実施形態では焼き付け層上にＮｉめっき層を形成する。このＮｉめっき層が内めっき層２４となる。次に、Ｎｉめっき層上にＳｎめっき層を形成する。このＳｎめっき層が表めっき層２５となる。Ｎｉめっき層及びＳｎめっき層は、たとえばバレルめっき法により、順次形成される。このようにして、積層セラミックコンデンサ１が得られる。 Next, a plating layer 23 is formed on the surface of the base electrode layer 21. In this embodiment, a Ni plating layer is formed on the baked layer. This Ni plating layer becomes the inner plating layer 24. Next, a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the surface plating layer 25. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by barrel plating. In this manner, the multilayer ceramic capacitor 1 is obtained.
（積層と切断）
　図８及び図９に基づいて、本実施形態の積層セラミックコンデンサ１に製造方法における積層と切断について、より詳しく説明する。図８は、電極ペースト３１及び段差ペースト３２が塗布されたセラミックグリーンシート３０の平面図である。図７と図８とでは、セラミックグリーンシート３０に塗布された電極ペースト３１及び段差ペースト３２のパターンの形状が異なる。図７に示した構成では、電極用のパターンは、長さ方向Ｌに２列、幅方向Ｗに５行、配置されていた。また、段差ペースト３２は、長さ方向Ｌに並ぶ２つの電極用のパターンの間に塗布されていた。これに対し、図８に示す構成では、電極用のパターンは、長さ方向Ｌに４列、幅方向Ｗに５行、配置されている。また、段差ペースト３２は、長さ方向Ｌに並ぶ４つの電極用のパターンにおいて、１つ目の電極用のパターンと２つ目の電極用のパターンとの間、及び、３つ目の電極用のパターンと４つ目の電極用のパターンとの間に塗布されている。このように、セラミックグリーンシート３０には、製造する積層セラミックコンデンサ１の種類に応じて、多様なパターンで、電極ペースト３１及び段差ペースト３２を塗布することができる。 (Lamination and cutting)
8 and 9, the lamination and cutting in the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described in more detail. FIG. 8 is a plan view of a ceramic green sheet 30 on which an electrode paste 31 and a step paste 32 are applied. The shapes of the patterns of the electrode paste 31 and the step paste 32 applied to the ceramic green sheet 30 are different between FIG. 7 and FIG. 8. In the configuration shown in FIG. 7, the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between two electrode patterns arranged in the length direction L. In contrast, in the configuration shown in FIG. 8, the electrode patterns are arranged in four columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between the first electrode pattern and the second electrode pattern, and between the third electrode pattern and the fourth electrode pattern, in the four electrode patterns arranged in the length direction L. In this manner, the electrode paste 31 and the step paste 32 can be applied to the ceramic green sheet 30 in a variety of patterns depending on the type of multilayer ceramic capacitor 1 to be manufactured.
（積層）
　図８に８０１で示すセラミックグリーンシート３０を第１のセラミックグリーンシート３０ａとする。図８に８０２で示すセラミックグリーンシート３０を第２のセラミックグリーンシート３０ｂとする。第１のセラミックグリーンシート３０ａと第２のセラミックグリーンシート３０ｂとは、図７に示した構成と同様に、ずらして積層される。具体的には、長さ方向Ｌに距離ｄ２ずらして積層される。 (Lamination)
The ceramic green sheet 30 indicated by 801 in Fig. 8 is the first ceramic green sheet 30a. The ceramic green sheet 30 indicated by 802 in Fig. 8 is the second ceramic green sheet 30b. The first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked with a shift in the same manner as in the configuration shown in Fig. 7. Specifically, they are stacked with a shift of a distance d2 in the longitudinal direction L.
（切断）
　図９に基づいて、積層されたセラミックグリーンシート３０の切断について説明する。図９（ａ）及び図９（ｂ）は、積層されたセラミックグリーンシート３０のＬＴ断面を示す図である。図９（ａ）及び図９（ｂ）では、構成を単純にするために、セラミックグリーンシート３０が２枚のみ積層された状態を例示している。このセラミックグリーンシート３０が２枚積層されたものを、以下の説明において積層物４０という。図９（ａ）に示す線Ｌ１及び線Ｌ２は、切断線を示す。この線Ｌ１及び線Ｌ２は、図８に示した線Ｌ１及び線Ｌ２に対応している。図９（ａ）は、切断前の積層物４０を示す。図９（ｂ）は、線Ｌ１及び線Ｌ２で切断した後の積層物４０を示す。 (Disconnect)
The cutting of the laminated ceramic green sheets 30 will be described with reference to FIG. 9. FIGS. 9(a) and 9(b) are diagrams showing the LT cross section of the laminated ceramic green sheets 30. In FIGS. 9(a) and 9(b), in order to simplify the configuration, only two ceramic green sheets 30 are illustrated as an example. In the following description, the two ceramic green sheets 30 are referred to as a laminate 40. Lines L1 and L2 shown in FIG. 9(a) indicate cutting lines. These lines L1 and L2 correspond to the lines L1 and L2 shown in FIG. 8. FIG. 9(a) shows the laminate 40 before cutting. FIG. 9(b) shows the laminate 40 after cutting along the lines L1 and L2.
（線Ｌ１）
　図９（ａ）に示すように、積層物４０における第１のセラミックグリーンシート３０ａと第２のセラミックグリーンシート３０ｂとは、長さ方向Ｌにずらして積層されている。そのため、第２のセラミックグリーンシート３０ｂにおける電極ペースト３１のパターンの長手方向Ｌの端部３１ｂは、第１のセラミックグリーンシート３０ａにおける段差ペースト３２のパターンの長手方向Ｌの中央部３２ａと、長手方向Ｌの位置において揃っている。すなわち、電極ペースト３１のパターンの端部３１ｂ、及び、段差ペースト３２のパターンの中央部３２ａは、いずれも線Ｌ１上に位置している。 (Line L1)
9(a), the first ceramic green sheet 30a and the second ceramic green sheet 30b in the laminate 40 are stacked with a shift in the length direction L. Therefore, the end 31b in the longitudinal direction L of the pattern of the electrode paste 31 in the second ceramic green sheet 30b is aligned in the longitudinal direction L with the center 32a in the longitudinal direction L of the pattern of the step paste 32 in the first ceramic green sheet 30a. In other words, the end 31b of the pattern of the electrode paste 31 and the center 32a of the pattern of the step paste 32 are both located on the line L1.
（線Ｌ２）
　同様に、第２のセラミックグリーンシート３０ｂにおける段差ペースト３２のパターンの長手方向Ｌの中央部３２ｂは、第１のセラミックグリーンシート３０ａにおける電極ペースト３１のパターンの長手方向Ｌの端部３１ａと、長手方向Ｌの位置において揃っている。すなわち、段差ペースト３２のパターンの中央部３２ｂ、及び、電極ペースト３１のパターンの端部３１ａは、いずれも線Ｌ２上に位置している。 (Line L2)
Similarly, a central portion 32b in the longitudinal direction L of the pattern of the step paste 32 in the second ceramic green sheet 30b is aligned with an end portion 31a in the longitudinal direction L of the pattern of the electrode paste 31 in the first ceramic green sheet 30a in the longitudinal direction L. That is, the central portion 32b of the pattern of the step paste 32 and the end portion 31a of the pattern of the electrode paste 31 are both located on the line L2.
（切断後）
　切断後の積層物４０を図９（ｂ）に示す。線Ｌ１及び線Ｌ２で切断された積層物４０は、Ｌギャップ５１に段差層５が形成された形態となっている。これは、第１のセラミックグリーンシート３０ａに塗布されたパターンと、第２のセラミックグリーンシート３０ｂに塗布されたパターンとが前述のような位置関係になるようにセラミックグリーンシート３０がずらして積層されているためである。 (After disconnection)
9B shows the laminate 40 after cutting. The laminate 40 cut along the lines L1 and L2 has a step layer 5 formed in the L gap 51. This is because the ceramic green sheets 30 are stacked with a shift so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b have the positional relationship described above.
（切断面）
　線Ｌ１で切断したことによって生じた切断面を第１の切断面４１とする。また、線Ｌ２で切断したことによって生じた切断面を第２の切断面４２とする。第１の切断面４１は積層体２における第１の端面６２ａに対応する。また、第２の切断面４２は積層体２における第２の端面６２ｂに対応する。ここで、対応するとは、積層物４０が焼成されて積層体２になった場合に対応する積層体２の部位、との意味である。 (Cut surface)
The cut surface generated by cutting along line L1 is defined as a first cut surface 41. Moreover, the cut surface generated by cutting along line L2 is defined as a second cut surface 42. The first cut surface 41 corresponds to a first end surface 62a of the laminate 2. Moreover, the second cut surface 42 corresponds to a second end surface 62b of the laminate 2. Here, "corresponding" means a portion of the laminate 2 that corresponds when the laminate 40 is fired to become the laminate 2.
　積層物４０の第１の切断面４１からは、積層方向Ｔにおいて順に、内層誘電体層４ａに対応する第１のグリーンシート３０ａ、段差層５に対応する段差ペースト３２、内層誘電体層４ａに対応する第２のグリーンシート３０ｂ、及び、第１の内部電極層１０ａに対応する電極ペースト３１が露出している。同様に、積層物４０の第２の切断面４２からは、積層方向Ｔにおいて順に、内層誘電体層４ａに対応する第１のグリーンシート３０ａ、第２の内部電極層１０ｂに対応する電極ペースト３１、内層誘電体層４ａに対応する第２のグリーンシート３０ｂ、及び、段差層５に対応する段差ペースト３２、が露出している。そして、長さ方向Ｌにおいて、段差ペースト３２が配置されている部分が、それぞれ、第１のＬギャップ５１ａ及び第２のＬギャップ５１ｂとなる。 From the first cut surface 41 of the laminate 40, in the stacking direction T, the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a are exposed. Similarly, from the second cut surface 42 of the laminate 40, in the stacking direction T, the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5 are exposed. In the length direction L, the portions where the step paste 32 is arranged become the first L gap 51a and the second L gap 51b, respectively.
（Ｓｉ偏析層の形成）
　前述のように、段差ペースト３２には、Ｓｉ偏析層１４を形成するためのＳｉ成分が配合されている。このＳｉ成分は段差ペースト３２内を移行し、内部電極層１０に付着する。Ｓｉ成分は液相成分である。そのため、Ｓｉ成分は、誘電体材料をこえて内部電極層に寄っていくことが可能だからである。具体的には、Ｓｉ成分は、引き出し電極部１２の表面、及び対向電極部１１の端部及び表面の少なくとも一部に付着する。この各内部電極層１０に付着したＳｉ成分がＳｉ偏析層１４を形成する。 (Formation of Si Segregation Layer)
As described above, the step paste 32 contains a Si component for forming the Si segregation layer 14. This Si component migrates through the step paste 32 and adheres to the internal electrode layer 10. The Si component is a liquid phase component. Therefore, the Si component can move across the dielectric material and approach the internal electrode layer. Specifically, the Si component adheres to the surface of the extraction electrode portion 12 and at least a part of the end and surface of the counter electrode portion 11. The Si component adhered to each internal electrode layer 10 forms the Si segregation layer 14.
（他のＳｉ偏析層の形成方法）
　なお、Ｓｉ偏析層１４の形成方法は、前述した段差ペースト３２にＳｉ成分を配合する方法に限定されない。他のＳｉ偏析層１４の形成方法としては、Ｌギャップ５１にＳｉ成分を塗布する方法がある。この方法では、Ｓｉ偏析層１４を形成したい部分に対応する電極ペースト３１の塗布パターンに、Ｓｉ成分を印刷などによって塗布する。その他のＳｉ偏析層１４の形成方法としては、焼成前の積層チップのＷＴ端面、すなわち積層体２の端面６２に対応する面から、Ｓｉ成分を含侵させる方法などがある。 (Other methods for forming a Si segregation layer)
The method for forming the Si segregation layer 14 is not limited to the above-mentioned method of blending the Si component into the step paste 32. Another method for forming the Si segregation layer 14 is to apply the Si component to the L gap 51. In this method, the Si component is applied by printing or the like to an application pattern of the electrode paste 31 corresponding to the portion where the Si segregation layer 14 is to be formed. Another method for forming the Si segregation layer 14 is to impregnate the WT end face of the laminated chip before firing, i.e., the face corresponding to the end face 62 of the laminated body 2, with the Si component.
（Ｓｉ偏析層の効果）
　本実施形態の積層セラミックコンデンサ１は、Ｌギャップ５１にＳｉ偏析層１４が備えられている。そのため、積層セラミックコンデンサ１の信頼性を向上させることができる。Ｓｉ偏析層１４は、ＩＲ（Ｉｎｓｕｌａｔｉｏｎ　Ｒｅｓｉｓｔａｎｃｅ、絶縁抵抗）が高いためである。 (Effect of Si Segregation Layer)
The multilayer ceramic capacitor 1 of this embodiment is provided with the Si segregation layer 14 in the L gap 51. This can improve the reliability of the multilayer ceramic capacitor 1. This is because the Si segregation layer 14 has a high IR (insulation resistance).
　以下、積層セラミックコンデンサ１の特性の評価結果を示す。
（高温負荷信頼性試験）
　図１０に基づいて、高温負荷信頼性試験の結果を説明する。図１０は、比較例及び実施例について、高温負荷信頼性試験の結果を示す図である。
　高温負荷信頼性試験の方法は次の通りである。比較例及び実施例１から８について、それぞれ試料を１００ずつ用意した。その試料を、共晶半田を用いて、ガラスエポキシ基板に実装した。試料における誘電体層の厚みは、０．５μｍとした。まず、各試料の初期の絶縁抵抗値を測定した。次に、ガラスエポキシ基板を高温槽内に入れ、１５０℃の環境下において、各試料に対して６．３Ｖの電圧を印加した。その後、２００時間経過時と、５００時間経過時とに、絶縁抵抗値を測定した。初期の絶縁抵抗値と、経時後の絶縁抵抗値とを比較して、絶縁抵抗値が１桁以上低下したものを不良とした。図１０に示すように、Ｓｉ偏析層を備える試料では、２００時間において不良は発生しなかった。また、５００時間においても、不良の数を５以下に抑えることができた。 The evaluation results of the characteristics of the multilayer ceramic capacitor 1 are shown below.
(High temperature load reliability test)
The results of the high temperature load reliability test will be described with reference to Fig. 10. Fig. 10 is a diagram showing the results of the high temperature load reliability test for the comparative example and the example.
The method of the high temperature load reliability test is as follows. For each of the comparative example and the examples 1 to 8, 100 samples were prepared. The samples were mounted on a glass epoxy board using eutectic solder. The thickness of the dielectric layer in the sample was set to 0.5 μm. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy board was placed in a high temperature chamber, and a voltage of 6.3 V was applied to each sample in an environment of 150° C. Then, the insulation resistance value was measured after 200 hours and after 500 hours. The initial insulation resistance value was compared with the insulation resistance value after aging, and a sample with an insulation resistance value that decreased by one digit or more was determined to be defective. As shown in FIG. 10, no defects occurred in the sample having the Si segregation layer after 200 hours. Furthermore, the number of defects was suppressed to 5 or less even after 500 hours.
　特に、Ｓｉ偏析層の厚みが０．０３μｍ以上０．１５μｍ以下である実施例２から実施例６では、２００時間経過後に加えて、５００時間経過後においても、不良は発生しなかった。 In particular, in Examples 2 to 6, in which the thickness of the Si segregation layer was 0.03 μm or more and 0.15 μm or less, no defects occurred even after 500 hours, in addition to after 200 hours.
（誘電率及び平均故障時間）
　図１１に基づいて、誘電率及び平均故障時間の評価結果を説明する。図１１は、比較例及び実施例について、誘電率及び平均故障時間の評価結果を示す図である。試料における誘電体層の厚みは、０．３μｍから０．６μｍまでの４種類とした。誘電体層の厚みを異ならせることで、素子の厚みが異なる試料を作製した。また、Ｓｉ偏析層の厚みは、０．０７μｍ及び０．０８μｍとした。 (Dielectric constant and mean time to failure)
The evaluation results of the dielectric constant and the mean time to failure will be described with reference to FIG. 11. FIG. 11 is a diagram showing the evaluation results of the dielectric constant and the mean time to failure for the comparative example and the example. The thickness of the dielectric layer in the sample was set to four types ranging from 0.3 μm to 0.6 μm. By varying the thickness of the dielectric layer, samples with different element thicknesses were produced. In addition, the thickness of the Si segregation layer was set to 0.07 μm and 0.08 μm.
　Ｓｉは誘電率が低い。そのため、Ｓｉ偏析層が形成された試料では、誘電率の低下がみられた。また、Ｓｉ偏析層が形成された試料では、ＭＴＴＦ（Ｍｅａｎ　Ｔｉｍｅ　Ｔｏ　Ｆａｉｌｕｒｅ、平均故障時間）の改善が見られた。 Si has a low dielectric constant. Therefore, a decrease in dielectric constant was observed in samples with a Si segregation layer. Also, an improvement in MTTF (Mean Time To Failure) was observed in samples with a Si segregation layer.
　特に、誘電体層の厚みが０．４μｍ以上０．５μｍ以下である実施例Ｂ及び実施例Ｃでは、ＭＴＴＦに大きな改善が見られた。 In particular, in Examples B and C, where the thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less, a significant improvement in MTTF was observed.
　以上本発明の実施形態について説明したが、本発明は前述した実施形態に限定されることなく、種々の変更及び変形が可能である。 The above describes an embodiment of the present invention, but the present invention is not limited to the above embodiment and various modifications and variations are possible.
＜１＞
　積層された複数の誘電体層と複数の内部電極層とを含み、
　積層方向に相対する第１の主面及び第２の主面と、積層方向に直交する幅方向に相対する第１の側面及び第２の側面と、積層方向及び幅方向に直交する長さ方向に相対する第１の端面及び第２の端面とを備える積層体と、
　前記第１の端面及び第２の端面に設けられた外部電極と、
　を備え、
　前記内部電極層は第１の内部電極層と第２の内部電極層とを備え、
　前記第１の内部電極層は、前記第１の端面へ引き出され、
　前記第２の内部電極層は、前記第２の端面へ引き出され、
　前記外部電極は、前記第１の内部電極層に接続された第１の外部電極、及び、前記第２の内部電極層に接続された第２の外部電極を含み、
　前記第１の端面側に配置され、前記第１の内部電極層同士が前記積層方向において重なり合わない領域、及び、前記第２の端面側に配置され、前記第２の内部電極層同士が前記積層方向において重なり合わない領域をＬギャップ領域とし、
　前記Ｌギャップ領域は、Ｓｉ偏析層を備えることを特徴とする、
　積層セラミックコンデンサ。 ＜1＞
The dielectric layer includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together,
a laminate including a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction;
external electrodes provided on the first end surface and the second end surface;
Equipped with
the internal electrode layer includes a first internal electrode layer and a second internal electrode layer,
the first internal electrode layer is extended to the first end face,
the second internal electrode layer is extended to the second end face,
the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer;
an L-gap region is an area disposed on the first end face side, in which the first internal electrode layers do not overlap with each other in the stacking direction, and an area disposed on the second end face side, in which the second internal electrode layers do not overlap with each other in the stacking direction;
The L gap region is characterized by comprising a Si segregation layer.
Multilayer ceramic capacitor.
＜２＞
　前記Ｓｉ偏析層の厚みは、０．０３μｍ以上０．１５μｍ以下である、
　＜１＞に記載の積層セラミックコンデンサ。 ＜2＞
The thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less.
The multilayer ceramic capacitor according to <1>.
＜３＞
　前記第１の内部電極層の前記幅方向の端部、及び、前記第２の内部電極の前記幅方向の端部には、前記Ｓｉ偏析層が存在する、
　＜１＞又は＜２＞に記載の積層セラミックコンデンサ。 ＜3＞
the Si segregation layer is present at an end portion in the width direction of the first internal electrode layer and an end portion in the width direction of the second internal electrode;
The multilayer ceramic capacitor according to <1> or <2>.
＜４＞
　前記誘電体層の厚みは、０．４μｍ以上０．５μｍ以下である、
　＜１＞から＜３＞のいずれか１つに記載の積層セラミックコンデンサ。 ＜4＞
The thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less.
<1> The multilayer ceramic capacitor according to any one of <1> to <3>.
　１　　　積層セラミックコンデンサ
　２　　　積層体
　４　　　誘電体層
　５　　　段差層
　１０　　内部電極層
　１１　　対向電極部
　１２　　引き出し電極部
　１３　　浮島電極
　１４　　Ｓｉ偏析層
　２０　　外部電極
　２１　　下地電極層
　２３　　めっき層
　２４　　内めっき層
　２５　　表めっき層
　３０　　セラミックグリーンシート
　３１　　電極ペースト
　３２　　段差ペースト
　４０　　積層物
　４１　　第１の切断面
　４２　　第２の切断面
　５０　　電極対向部
　５１　　Ｌギャップ（Ｌギャップ領域）
　５２　　Ｗギャップ
　５３　　内層部
　５４　　外層部
　６１　　主面
　６２　　端面
　６３　　側面
　Ｒ１　　領域
　Ｒ２　　領域
　Ｔ　　　積層方向
　Ｌ　　　長さ方向
　Ｗ　　　幅方向 REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 4 Dielectric layer 5 Step layer 10 Internal electrode layer 11 Counter electrode portion 12 Lead electrode portion 13 Floating island electrode 14 Si segregation layer 20 External electrode 21 Base electrode layer 23 Plating layer 24 Inner plating layer 25 Surface plating layer 30 Ceramic green sheet 31 Electrode paste 32 Step paste 40 Laminate 41 First cut surface 42 Second cut surface 50 Electrode opposing portion 51 L gap (L gap region)
52 W gap 53 inner layer portion 54 outer layer portion 61 main surface 62 end surface 63 side surface R1 region R2 region T stacking direction L length direction W width direction

Claims (4)

  1. 　積層された複数の誘電体層と複数の内部電極層とを含み、
    　積層方向に相対する第１の主面及び第２の主面と、積層方向に直交する幅方向に相対する第１の側面及び第２の側面と、積層方向及び幅方向に直交する長さ方向に相対する第１の端面及び第２の端面とを備える積層体と、
    　前記第１の端面及び第２の端面に設けられた外部電極と、
    　を備え、
    　前記内部電極層は第１の内部電極層と第２の内部電極層とを備え、
    　前記第１の内部電極層は、前記第１の端面へ引き出され、
    　前記第２の内部電極層は、前記第２の端面へ引き出され、
    　前記外部電極は、前記第１の内部電極層に接続された第１の外部電極、及び、前記第２の内部電極層に接続された第２の外部電極を含み、
    　前記第１の端面側に配置され、前記第１の内部電極層同士が前記積層方向において重なり合わない領域、及び、前記第２の端面側に配置され、前記第２の内部電極層同士が前記積層方向において重なり合わない領域をＬギャップ領域とし、
    　前記Ｌギャップ領域は、Ｓｉ偏析層を備えることを特徴とする、
    　積層セラミックコンデンサ。     The dielectric layer includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together,
    a laminate including a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction;
    external electrodes provided on the first end surface and the second end surface;
    Equipped with
    the internal electrode layer includes a first internal electrode layer and a second internal electrode layer,
    the first internal electrode layer is extended to the first end face,
    the second internal electrode layer is extended to the second end face,
    the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer;
    an L-gap region is an area disposed on the first end face side, in which the first internal electrode layers do not overlap with each other in the stacking direction, and an area disposed on the second end face side, in which the second internal electrode layers do not overlap with each other in the stacking direction;
    The L gap region is characterized by comprising a Si segregation layer.
    Multilayer ceramic capacitor.
  2. 　前記Ｓｉ偏析層の厚みは、０．０３μｍ以上０．１５μｍ以下である、
    　請求項１に記載の積層セラミックコンデンサ。     The thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less.
    The multilayer ceramic capacitor according to claim 1 .
  3. 　前記第１の内部電極層の前記幅方向の端部、及び、前記第２の内部電極層の前記幅方向の端部には、前記Ｓｉ偏析層が存在する、
    　請求項１又は２に記載の積層セラミックコンデンサ。     the Si segregation layer is present at an end portion in the width direction of the first internal electrode layer and an end portion in the width direction of the second internal electrode layer;
    3. The multilayer ceramic capacitor according to claim 1 or 2.
  4. 　前記誘電体層の厚みは、０．４μｍ以上０．５μｍ以下である、
    　請求項１から３のいずれか１項に記載の積層セラミックコンデンサ。     The thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less.
    The multilayer ceramic capacitor according to claim 1 .
PCT/JP2023/030103 2022-09-27 2023-08-22 Multilayer ceramic capacitor WO2024070337A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-153369 2022-09-27
JP2022153369 2022-09-27

Publications (1)

Publication Number Publication Date
WO2024070337A1 true WO2024070337A1 (en) 2024-04-04

Family

ID=90477034

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/030103 WO2024070337A1 (en) 2022-09-27 2023-08-22 Multilayer ceramic capacitor

Country Status (1)

Country Link
WO (1) WO2024070337A1 (en)

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