WO2024066561A1 - 查找空闲存储的装置、方法及芯片 - Google Patents

查找空闲存储的装置、方法及芯片 Download PDF

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WO2024066561A1
WO2024066561A1 PCT/CN2023/103331 CN2023103331W WO2024066561A1 WO 2024066561 A1 WO2024066561 A1 WO 2024066561A1 CN 2023103331 W CN2023103331 W CN 2023103331W WO 2024066561 A1 WO2024066561 A1 WO 2024066561A1
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logic gate
output
input
storage unit
level
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PCT/CN2023/103331
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English (en)
French (fr)
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刘明
石昊明
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声龙(新加坡)私人有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit design, and in particular, to a device, method, and chip for searching for free storage.
  • the present disclosure provides a device for searching for free storage, including:
  • An indication queue processing module configured to construct an indication queue for a storage block to indicate the occupancy of a storage unit in the storage block; wherein the indication queue includes a plurality of elements, and a value of the element is used to indicate whether the storage unit corresponding to the element is idle;
  • the information collection module is configured to obtain the information of the indication queue of the storage block through the first logic gate tree before writing the target data to the storage block, and determine the Whether there are free storage units in the storage block;
  • the arbitration and control module is configured to use the second logic gate tree to search for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule when there is a free storage unit in the storage block, and use the free storage unit corresponding to the target element as the target free storage unit to write the target data.
  • the present disclosure provides a method for searching for free storage, including:
  • an indication queue for a storage block Constructing an indication queue for a storage block to indicate the occupancy of storage units in the storage block; wherein the indication queue includes a plurality of elements, and the value of the element is used to indicate whether the storage unit corresponding to the element is idle;
  • the information of the indication queue of the storage block is obtained through the first logic gate tree, and it is determined whether there is a free storage unit in the storage block according to the information of the indication queue; when there is a free storage unit in the storage block, a target element indicating a free storage unit is searched from the indication queue of the storage block according to the binary search rule by using the second logic gate tree, and the free storage unit corresponding to the target element is used as the target free storage unit to write the target data.
  • An embodiment of the present disclosure provides a chip, including the above-mentioned device for searching for free storage.
  • FIG1 is a schematic diagram of the structure of a device for searching for free storage according to an embodiment of the present disclosure
  • FIG2 is a schematic diagram of the structure of a first logic gate tree according to an embodiment of the present disclosure
  • FIG3 is a schematic diagram of the structure of an example of the first logic gate tree shown in FIG2 (indicating that the queue includes 16 bits);
  • FIG4 is a schematic diagram of the structure of a second logic gate tree according to an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the structure of another second logic gate tree according to an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the structure of an example of the second logic gate tree shown in FIG5 (indicating that the queue includes 16 bits);
  • FIG7 is a schematic diagram of the structure of another second logic gate tree according to an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of an example of the second logic gate tree shown in FIG7 (indicating that the queue includes 16 bits);
  • FIG9-1 is a schematic diagram of the structure of a second logic gate (combination of AND gates) according to an embodiment of the present disclosure
  • FIG9-2 is a schematic diagram of the structure of another second logic gate (combination of AND gates) according to an embodiment of the present disclosure
  • FIG10-1 is a schematic diagram of the structure of another second logic gate (or a combination of gates) according to an embodiment of the present disclosure
  • FIG10-2 is a schematic diagram of the structure of another second logic gate (or a combination of gates) according to an embodiment of the present disclosure
  • FIG11 is a flow chart of a method for searching for free storage according to an embodiment of the present disclosure.
  • FIG12-1 is a flow chart of a method for searching a target position by binary search according to an embodiment of the present disclosure
  • FIG12-2 is a flow chart of another method for searching a target position by binary search according to an embodiment of the present disclosure.
  • the present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique invention scheme defined by the appended claims.
  • Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the appended claims. Therefore, it should be understood that any feature shown and/or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations.
  • various modifications and changes may be made within the scope of protection of the appended claims.
  • the present disclosure provides a device for searching for free storage.
  • the device for searching for free storage includes:
  • the indication queue processing module 10 is configured to construct an indication queue for a storage block to indicate the occupancy of a storage unit in the storage block; wherein the indication queue includes a plurality of elements, and the value of the element is used to indicate whether the storage unit corresponding to the element is idle;
  • the information collection module 20 is configured to obtain information of the indication queue of the storage block through the first logic gate tree before writing the target data into the storage block, and determine whether there is an idle storage unit in the storage block according to the information of the indication queue;
  • the arbitration and control module 30 is configured to use the second logic gate tree to search for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule when there is a free storage unit in the storage block, and use the free storage unit corresponding to the target element as the target free storage unit to write the target data.
  • the apparatus for searching for free storage includes an indication queue processing module, an information collection module, and an arbitration and control module.
  • the indication queue processing module constructs an indication queue for a storage block to indicate the occupancy of storage units in the storage block; before writing target data to the storage block, the information collection module obtains the information of the indication queue of the storage block through a first logic gate tree, and The information of the indication queue determines whether there is a free storage unit in the storage block; when there is a free storage unit in the storage block, the arbitration and control module uses the second logic gate tree to search for a target element indicating a free storage unit from the indication queue of the storage block according to the binary search rule, and uses the free storage unit corresponding to the target element as the target free storage unit to write the target data. Since the binary search can reduce the search amount by half, the device for searching free storage provided by the above embodiment can speed up the speed of searching free storage.
  • the storage block is a cache.
  • the elements of the indication queue are 1-bit binary numbers.
  • the value of the indication queue may be stored in a register, and each bit of the register corresponds one-to-one to each element of the indication queue.
  • the numerical value of the element is used to indicate whether the storage unit corresponding to the element is free, including: 0 indicates that the storage unit corresponding to the element is occupied (not free), and 1 indicates that the storage unit corresponding to the element is free; or, 1 indicates that the storage unit corresponding to the element is occupied (not free), and 0 indicates that the storage unit corresponding to the element is free.
  • the information collection module is configured to obtain the information of the indication queue of the storage block through the first logic gate tree in the following manner:
  • the following information is obtained through the first logic gate group of the first level: whether there is an element indicating a free storage unit in each first level sub-queue of the indication queue; wherein the first level sub-queues of the indication queue are 2 m-1 in total;
  • the k-th level first logic gate group of the first logic gate tree is used to obtain the following information: whether there is an element indicating a free storage unit in each k-th level sub-queue of the indication queue; wherein the k-th level sub-queues of the indication queue are 2mk in total; 2 ⁇ k ⁇ m-1;
  • the following information is obtained through the first logic gate group of the mth stage: whether there is an element indicating a free storage unit among all elements of the indication queue;
  • the arbitration and control module is configured to use the following method to utilize Using the second logic gate tree, a target element indicating a free storage unit is searched from the indication queue of the storage block according to the binary search rule:
  • the output of the second logic gate of the previous level is input to the first input terminal of the second logic gate of the kth level
  • the output of the first logic gate of the m-kth level is input to the second input terminal
  • the outputs of the two output terminals are respectively used as the inputs of two adjacent second logic gates of the next level; 2 ⁇ k ⁇ m-1;
  • the output of the second logic gate of the previous level is input to the first input terminal of the second logic gate of the mth level of the second logic gate tree, the value of an element of the indication queue is input to the second input terminal, and the outputs of the two output terminals respectively indicate whether the storage cells corresponding to the element and the adjacent elements of the element of the indication queue are free storage cells;
  • the processing logic of the second logic gate is as follows: when the input of the first input terminal is true, one and only one of the outputs of the two output terminals is true, and the input of the second input terminal is used to determine which output terminal's output is true; when the input of the first input terminal is false, the outputs of the two output terminals are both false.
  • the arbitration and control module is further configured to send a first control signal to the indication queue processing module through a second logic gate tree after writing the target data into the target free storage unit; wherein the first control signal carries information of a target element in the indication queue corresponding to the target free storage unit;
  • the indication queue processing module is further configured to update the indication queue corresponding to the target free storage unit upon receiving the first control signal: modify the value of the target element corresponding to the target free storage unit in the indication queue to indicate that the storage unit is occupied.
  • the arbitration and control module is further configured to send a second control signal to the indication queue processing module through a second logic gate tree after reading data from the target storage unit; wherein the second control signal carries information of a target element in the indication queue corresponding to the target storage unit;
  • the indication queue processing module is further configured to receive a second control signal and update the target The indication queue corresponding to the storage unit: the value of the target element corresponding to the target storage unit in the indication queue is modified to indicate that the storage unit is idle.
  • the first logic gate comprises: two input terminals and one output terminal;
  • the two input ends of the first logic gate of the first level of the first logic gate tree are respectively input with the values of two adjacent elements of the indication queue, and the output end is connected to the input end of the first logic gate of the next level;
  • Two input ends of the mth level first logic gate of the first logic gate tree are respectively connected to the output ends of two adjacent previous level first logic gates, and the output of the output end is used to indicate whether there is a free storage unit in the storage block corresponding to the indication queue;
  • the two input ends of the k-th level first logic gate of the first logic gate tree are respectively connected to the output ends of two adjacent first logic gates of the previous level, and the output end is connected to the input end of the first logic gate of the next level; 2 ⁇ k ⁇ m-1;
  • the processing logic of the first logic gate is: when at least one of the inputs of the two input terminals is true, the output of the output terminal is true; when the inputs of the two input terminals are both false, the output of the output terminal is false.
  • the first logic gate comprises: a first input terminal, a second input terminal and an output terminal;
  • the first input terminal of the j-th first logic gate L(1,j) of the first stage inputs the 2j-1th bit of the indication queue, and the second input terminal of L(1,j) inputs the 2jth bit of the indication queue; 1 ⁇ j ⁇ 2 m-1 ;
  • the first logic gate of the m-th level includes a first logic gate L(m,1), a first input end of L(m,1) is connected to the output end of the first first logic gate L(m-1,1) of the m-1-th level, and a second input end of L(m,1) is connected to the output end of the second first logic gate L(m-1,2) of the m-1-th level;
  • the first input end of the jth first logic gate L(k,j) of the kth level is connected to the output end of the 2j-1th first logic gate L(k-1,2j-1) of the k-1th level, and the second input end of L(k,j) is connected to the output end of the 2jth first logic gate L(k-1,2j) of the k-1th level; 2 ⁇ k ⁇ m-1; 1 ⁇ j ⁇ 2 mk .
  • Table 1 below is a truth table of the first logic gate.
  • the input of the first input terminal is x1
  • the input of the second input terminal is x2
  • the output of the output terminal is y.
  • the first-level first logic gate group includes 8 first logic gates, namely: L(1,1), L(1,2), L(1,3), L(1,4), L(1,5), L(1,6), L(1,7), L(1,8).
  • the two inputs of L(1,1) are: the 1st and 2nd bits of the indication queue.
  • the two inputs of L(1,2) are: the 3rd and 4th bits of the indication queue.
  • the two inputs of L(1,3) are: the 5th and 6th bits of the indication queue.
  • the two inputs of L(1,4) are: the 7th and 8th bits of the indication queue.
  • the two inputs of L(1,5) are: the 9th and 10th bits of the indication queue.
  • the two inputs of L(1,6) are: the 11th and 12th bits of the indication queue.
  • the two inputs of L(1,5) are: the 13th and 14th bits of the indication queue.
  • the two inputs of L(1,6) are: the 15th and 16th bits of the indication queue.
  • the second-level first logic gate group includes four first logic gates, namely: L(2,1), L(2,2), L(2,3), L(2,4).
  • the two inputs of L(2,1) are: the output of L(1,1) and the output of L(1,2).
  • the two inputs of L(2,2) are: the output of L(1,3) and the output of L(1,4).
  • the two inputs of L(2,3) are: the output of L(1,5) and the output of L(1,6).
  • the two inputs of L(2,4) are: the output of L(1,7) and the output of L(1,8).
  • the third-level first logic gate group includes two first logic gates, namely: L(3,1) and L(3,2).
  • the two inputs of L(3,1) are: the output of L(2,1) and the output of L(2,2).
  • the two inputs of L(3,2) are: the output of L(2,3) and the output of L(2,4).
  • the fourth-level first logic gate group includes a first logic gate L(4,1).
  • the two inputs of L(4,1) are It is: the output of L(3,1) the output of L(3,2).
  • the second logic gate comprises: a first input terminal, a second input terminal and two output terminals;
  • the first input end of the second logic gate of the first level of the second logic gate tree is connected to the output end of the first logic gate of the mth level, the second input end is connected to the output end of the first logic gate of the m-1th level, and the two output ends are respectively connected to the input ends of two adjacent second logic gates of the next level;
  • the first input end of the second logic gate of the mth level of the second logic gate tree is connected to the output end of the second logic gate of the previous level, the second input end inputs the value of an element of the indication queue, and the outputs of the two output ends respectively indicate whether the storage cells corresponding to the element and the adjacent elements of the element of the indication queue are free storage cells;
  • the first input end of the second logic gate of the kth level of the second logic gate tree is connected to the output end of the second logic gate of the previous level, the second input end is connected to the output end of the first logic gate of the m-kth level, and the two output ends are respectively connected to the input ends of two adjacent second logic gates of the next level;
  • the processing logic of the second logic gate is: when the input of the first input terminal is true, one and only one of the outputs of the two output terminals is true, and the input of the second input terminal is used to determine which output terminal's output is true; when the input of the first input terminal is false, the outputs of both output terminals are false.
  • the two input ends of the first-stage second logic gate R(1,1) are respectively connected to the output end of the m-th-stage first logic gate and the output end of the m-1-th-stage first logic gate, and the two output ends of R(1,1) are respectively connected to the input ends of two adjacent second-stage second logic gates;
  • One of the two input terminals of the j-th second logic gate R(m,j) of the m-th stage is connected to the k-1-th second logic gate R(m,j).
  • the output end of the second logic gate, the other input indicates the value of an element of the queue H, and the outputs of the two output ends of R (m, j) respectively indicate whether the storage unit corresponding to the element and the adjacent element of the element of the queue is a free storage unit;
  • the two input ends of the j-th second logic gate R(k,j) of the k-th level are respectively connected to the output end of the second logic gate of the k-1-th level and the output end of the first logic gate of the m-k-th level, and the two output ends of R(k,j) are respectively connected to the input ends of two adjacent second logic gates of the k+1-th level; 2 ⁇ k ⁇ m-1.
  • Any second logic gate comprises: a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
  • the first input end of the second logic gate R(1,1) of the first stage is connected to the output end of the first first logic gate L(m,1) of the mth stage, the second input end of R(1,1) is connected to the output end of the second first logic gate L(m-1,2) of the m-1th stage, the first output end of R(1,1) is connected to the first input end of the first second logic gate R(2,1) of the second stage, and the second output end of R(1,1) is connected to the first input end of the second second logic gate R(2,2) of the second stage;
  • the first input end of the 2t-1th second logic gate R(m,2t-1) of the mth level is connected to the first output end of the tth second logic gate R(m-1,t) of the m-1th level, the second input end of R(m,2t-1) inputs the value of the 4t-2th element of the indication queue, the output of the first output end of R(m,2t-1) indicates whether the storage unit corresponding to the 4t-3th element of the indication queue is free, and the output of the second output end of R(m,2t-1) indicates whether the storage unit corresponding to the 4t-2th element of the indication queue is free; 1 ⁇ t ⁇ 2 m-2 ;
  • the first input end of the 2t-th second logic gate R(m,2t) of the m-th level is connected to the second output end of the t-th second logic gate R(m-1,t) of the m-1-th level, the second input end of R(m,2t) inputs the value of the 4t-th element of the indication queue, the output of the first output end of R(m,2t) indicates whether the storage unit corresponding to the 4t-1-th element of the indication queue is free, and the output of the second output end of R(m,2t) indicates whether the storage unit corresponding to the 4t-th element of the indication queue is free; 1 ⁇ t ⁇ 2 m-2 ;
  • the first input terminal of the 2t-1 second logic gate R(k,2t-1) of the k-th level is connected to the first output terminal of the t-th second logic gate R(k-1,t) of the k-1-th level, and the second input terminal of R(k,2t-1) is connected to the first output terminal of the t-th second logic gate R(k-1,t) of the k-1-th level.
  • the output end of the 4t-2 first logic gate L(mk,4t-2) of the mkth level is connected, the first output end of R(k,2t-1) is connected to the first input end of the 4t-3 second logic gate R(k+1,4t-3) of the k+1th level, and the second output end of R(k,2t-1) is connected to the first input end of the 4t-2 second logic gate R(k+1,4t-2) of the k+1th level; wherein, 2 ⁇ k ⁇ m-1; 1 ⁇ t ⁇ 2 k-2 ;
  • the first input end of the 2t-th second logic gate R(k,2t) of the k-th level is connected to the second output end of the t-th second logic gate R(k-1,t) of the k-1-th level
  • the second input end of R(k,2t) is connected to the output end of the 4t-th first logic gate L(mk,4t) of the mk-th level
  • the first output end of R(k,2t) is connected to the first input end of the 4t-1-th second logic gate R(k+1,4t-1) of the k+1-th level
  • the second output end of R(k,2t) is connected to the first input end of the 4t-th second logic gate R(k+1,4t) of the k+1-th level; wherein, 2 ⁇ k ⁇ m-1; 1 ⁇ t ⁇ 2 k-2 .
  • the processing logic of the second logic gate is: when the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, the output y2 of the second output terminal is true and the output y1 of the first output terminal is false; when the input x2 of the second input terminal is false, the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • Table 2 below is a truth table of the second logic gate.
  • the first-stage second logic gate group includes a second logic gate R(1,1).
  • the first input terminal of R(1,1) is connected to The second input end of R(1,1) is connected to the output end of the first first logic gate L(4,1) of the fourth level, the second input end of R(1,1) is connected to the output end of the second first logic gate L(3,2) of the third level, the first output end of R(1,1) is connected to the first input end of the first second logic gate R(2,1) of the second level, and the second output end of R(1,1) is connected to the first input end of the second second logic gate R(2,2) of the second level.
  • the second logic gate group of the second level includes two second logic gates, namely: R(2,1) and R(2,2).
  • the first input terminal of R(2,1) is connected to the first output terminal of the first second logic gate R(1,1) of the first level
  • the second input terminal of R(2,1) is connected to the output terminal of the second first logic gate L(2,2) of the second level
  • the first output terminal of R(2,1) is connected to the first input terminal of the first second logic gate R(3,1) of the third level
  • the second output terminal of R(2,1) is connected to the first input terminal of the second second logic gate R(3,2) of the third level.
  • the first input terminal of R(2,2) is connected to the second output terminal of the first second logic gate R(1,1) of the first level
  • the second input terminal of R(2,2) is connected to the output terminal of the fourth first logic gate L(2,4) of the second level
  • the first output terminal of R(2,2) is connected to the first input terminal of the third second logic gate R(3,3) of the third level
  • the second output terminal of R(2,2) is connected to the first input terminal of the fourth second logic gate R(3,4) of the third level.
  • the third-level second logic gate group includes four second logic gates, namely: R(3,1), R(3,2), R(3,3) and R(3,4).
  • the first input end of R(3,1) is connected to the first output end of the first second logic gate R(2,1) of the second level
  • the second input end of R(3,1) is connected to the output end of the second first logic gate L(1,2) of the first level
  • the first output end of R(3,1) is connected to the first input end of the first second logic gate R(4,1) of the fourth level
  • the second output end of R(3,1) is connected to the first input end of the second second logic gate R(4,2) of the fourth level.
  • the first input terminal of R(3,2) is connected to the second output terminal of the first second logic gate R(2,1) of the second level
  • the second input terminal of R(3,2) is connected to the output terminal of the fourth first logic gate L(1,4) of the first level
  • the first output terminal of R(3,2) is connected to the first input terminal of the third second logic gate R(4,3) of the fourth level
  • the second output terminal of R(3,2) is connected to the first input terminal of the fourth second logic gate R(4,4) of the fourth level.
  • the first input terminal of R(3,3) is connected to the first output terminal of the second second logic gate R(2,2) of the second level
  • the second input terminal of R(3,3) is connected to the output terminal of the sixth first logic gate L(1,6) of the first level
  • the first output terminal of R(3,3) is connected to the first input terminal of the fifth second logic gate R(4,5) of the fourth level
  • the second output terminal of R(3,3) is connected to the first input terminal of the sixth second logic gate R(4,6) of the fourth level.
  • the first input terminal of R(3,4) is connected to the second output terminal of the second second logic gate R(2,2) of the second stage.
  • the second input end of R(3,4) is connected to the output end of the 8th first logic gate L(1,8) of the 1st level
  • the first output end of R(3,4) is connected to the first input end of the 7th second logic gate R(4,7) of the 4th level
  • the second output end of R(3,4) is connected to the first input end of the 8th second logic gate R(4,8) of the 4th level.
  • the 4th-level second logic gate group includes 8 second logic gates, namely: R(4,1), R(4,2), R(4,3), R(4,4), R(4,5), R(4,6), R(4,7), and R(4,8).
  • the first input end of R(4,1) is connected to the first output end of the first second logic gate R(3,1) of the third level, the second input end of R(4,1) inputs the value of the second bit of the indication queue, the output of the first output end of R(4,1) indicates whether the storage unit corresponding to the first bit of the indication queue is idle, and the output of the second output end of R(4,1) indicates whether the storage unit corresponding to the second bit of the indication queue is idle.
  • the first input end of R(4,2) is connected to the second output end of the first second logic gate R(3,1) of the third level, the second input end of R(4,2) inputs the value of the 4th bit of the indication queue, the output of the first output end of R(4,2) indicates whether the storage unit corresponding to the 3rd bit of the indication queue is idle, and the output of the second output end of R(4,2) indicates whether the storage unit corresponding to the 4th bit of the indication queue is idle.
  • the first input end of R(4,3) is connected to the first output end of the second second logic gate R(3,2) of the third level, the second input end of R(4,3) inputs the value of the 6th bit of the indication queue, the output of the first output end of R(4,3) indicates whether the storage unit corresponding to the 5th bit of the indication queue is idle, and the output of the second output end of R(4,3) indicates whether the storage unit corresponding to the 6th bit of the indication queue is idle.
  • the first input end of R(4,4) is connected to the second output end of the second second logic gate R(3,1) of the third level, the second input end of R(4,4) inputs the value of the 8th bit of the indication queue, the output of the first output end of R(4,4) indicates whether the storage unit corresponding to the 7th bit of the indication queue is idle, and the output of the second output end of R(4,4) indicates whether the storage unit corresponding to the 8th bit of the indication queue is idle.
  • the first input end of R(4,5) is connected to the first output end of the third second logic gate R(3,3) of the third level, the second input end of R(4,5) inputs the value of the 10th bit of the indication queue, the output of the first output end of R(4,5) indicates whether the storage unit corresponding to the 9th bit of the indication queue is idle, and the output of the second output end of R(4,5) indicates whether the storage unit corresponding to the 10th bit of the indication queue is idle.
  • the first input of R(4,6) is connected to the second output of the third second logic gate R(3,3) of the third level.
  • the second input of R(4,6) inputs the value of the 12th bit of the indication queue.
  • the output of the first output of R(4,6) indicates whether the storage unit corresponding to the 11th bit of the indication queue is free.
  • the second output of R(4,6) The output indicates whether the storage unit corresponding to the 12th bit of the indication queue is free.
  • the first input end of R(4,7) is connected to the first output end of the fourth second logic gate R(3,4) of the third level, the second input end of R(4,7) inputs the value of the 14th bit of the indication queue, the output of the first output end of R(4,7) indicates whether the storage unit corresponding to the 13th bit of the indication queue is idle, and the output of the second output end of R(4,7) indicates whether the storage unit corresponding to the 14th bit of the indication queue is idle.
  • the first input end of R(4,8) is connected to the second output end of the fourth second logic gate R(3,4) of the third level, the second input end of R(4,8) inputs the value of the 16th bit of the indication queue, the output of the first output end of R(4,8) indicates whether the storage unit corresponding to the 15th bit of the indication queue is idle, and the output of the second output end of R(4,8) indicates whether the storage unit corresponding to the 16th bit of the indication queue is idle.
  • Any second logic gate comprises: a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
  • the first input end of the second logic gate R(1,1) of the first stage is connected to the output end of the first first logic gate L(m,1) of the m-th stage, the second input end of R(1,1) is connected to the output end of the first first logic gate L(m-1,1) of the m-1-th stage, the first output end of R(1,1) is connected to the first input end of the first second logic gate R(2,1) of the second stage, and the second output end of R(1,1) is connected to the first input end of the second second logic gate R(2,2) of the second stage;
  • the first input end of the 2t-1th second logic gate R(m,2t-1) of the mth level is connected to the first output end of the tth second logic gate R(m-1,t) of the m-1th level, the second input end of R(m,2t-1) inputs the value of the 4t-3th element of the indication queue, the output of the first output end of R(m,2t-1) indicates whether the storage unit corresponding to the 4t-3th element of the indication queue is free, and the output of the second output end of R(m,2t-1) indicates whether the storage unit corresponding to the 4t-2th element of the indication queue is free; 1 ⁇ t ⁇ 2 m-2 ;
  • the first input end of the 2t-th second logic gate R(m,2t) of the m-th level is connected to the second output end of the t-th second logic gate R(m-1,t) of the m-1-th level.
  • the second input end of R(m,2t) inputs the value of the 4t-1-th element of the indication queue.
  • the output of the first output end of R(m,2t) indicates whether the storage unit corresponding to the 4t-1-th element of the indication queue is free.
  • the output of the second output end of R(m,2t) indicates whether the storage unit corresponding to the 4t-1-th element of the indication queue is free. Whether the storage units corresponding to the 4t elements are free; 1 ⁇ t ⁇ 2 m-2 ;
  • the first input end of the 2t-1 second logic gate R(k,2t-1) of the kth level is connected to the first output end of the tth second logic gate R(k-1,t) of the k-1th level
  • the second input end of R(k,2t-1) is connected to the output end of the 4t-3 first logic gate L(mk,4t-3) of the mkth level
  • the first output end of R(k,2t-1) is connected to the first input end of the 4t-3 second logic gate R(k+1,4t-3) of the k+1th level
  • the second output end of R(k,2t-1) is connected to the first input end of the 4t-2 second logic gate R(k+1,4t-2) of the k+1th level
  • the first input end of the 2t-th second logic gate R(k,2t) of the k-th level is connected to the second output end of the t-th second logic gate R(k-1,t) of the k-1-th level
  • the second input end of R(k,2t) is connected to the output end of the 4t-1-th first logic gate L(mk,4t) of the mk-th level
  • the first output end of R(k,2t) is connected to the first input end of the 4t-1-th second logic gate R(k+1,4t-1) of the k+1-th level
  • the second output end of R(k,2t) is connected to the first input end of the 4t-1-th second logic gate R(k+1,4t-1) of the k+1-th level; wherein, 2 ⁇ k ⁇ m-1; 1 ⁇ t ⁇ 2 k-2 .
  • the processing logic of the second logic gate is: when the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x2 of the second input terminal is false, the output y2 of the second output terminal is true and the output y1 of the first output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • Table 3 below is a truth table of the second logic gate.
  • the first-stage second logic gate group includes a second logic gate R(1,1).
  • the first input end of R(1,1) is connected to the output end of the first first logic gate L(4,1) of the fourth stage, the second input end of R(1,1) is connected to the output end of the first first logic gate L(3,1) of the third stage, the first output end of R(1,1) is connected to the first input end of the first second logic gate R(2,1) of the second stage, and the second output end of R(1,1) is connected to the first input end of the second second logic gate R(2,2) of the second stage.
  • the second logic gate group of the second level includes two second logic gates, namely: R(2,1) and R(2,2).
  • the first input terminal of R(2,1) is connected to the first output terminal of the first second logic gate R(1,1) of the first level
  • the second input terminal of R(2,1) is connected to the output terminal of the first first logic gate L(2,1) of the second level
  • the first output terminal of R(2,1) is connected to the first input terminal of the first second logic gate R(3,1) of the third level
  • the second output terminal of R(2,1) is connected to the first input terminal of the second second logic gate R(3,2) of the third level.
  • the first input terminal of R(2,2) is connected to the second output terminal of the first second logic gate R(1,1) of the first level
  • the second input terminal of R(2,2) is connected to the output terminal of the third first logic gate L(2,3) of the second level
  • the first output terminal of R(2,2) is connected to the first input terminal of the third second logic gate R(3,3) of the third level
  • the second output terminal of R(2,2) is connected to the first input terminal of the fourth second logic gate R(3,4) of the third level.
  • the third-level second logic gate group includes four second logic gates, namely: R(3,1), R(3,2), R(3,3) and R(3,4).
  • the first input end of R(3,1) is connected to the first output end of the first second logic gate R(2,1) of the second level
  • the second input end of R(3,1) is connected to the output end of the first first logic gate L(1,1) of the first level
  • the first output end of R(3,1) is connected to the first input end of the first second logic gate R(4,1) of the fourth level
  • the second output end of R(3,1) is connected to the first input end of the second second logic gate R(4,2) of the fourth level.
  • the first input terminal of R(3,2) is connected to the second output terminal of the first second logic gate R(2,1) of the second level
  • the second input terminal of R(3,2) is connected to the output terminal of the third first logic gate L(1,3) of the first level
  • the first output terminal of R(3,2) is connected to the first input terminal of the third second logic gate R(4,3) of the fourth level
  • the second output terminal of R(3,2) is connected to the first input terminal of the fourth second logic gate R(4,4) of the fourth level.
  • the first input end of R(3,3) is connected to the first output end of the second second logic gate R(2,2) of the second stage, and the second input end of R(3,3) is connected to the output end of the fifth first logic gate L(1,5) of the first stage.
  • the first output terminal is connected to the first input terminal of the fifth second logic gate R(4,5) of the fourth stage, and the second output terminal of R(3,3) is connected to the first input terminal of the sixth second logic gate R(4,6) of the fourth stage.
  • the first input terminal of R(3,4) is connected to the second output terminal of the second second logic gate R(2,2) of the second level
  • the second input terminal of R(3,4) is connected to the output terminal of the seventh first logic gate L(1,7) of the first level
  • the first output terminal of R(3,4) is connected to the first input terminal of the seventh second logic gate R(4,7) of the fourth level
  • the second output terminal of R(3,4) is connected to the first input terminal of the eighth second logic gate R(4,8) of the fourth level.
  • the 4th-level second logic gate group includes 8 second logic gates, namely: R(4,1), R(4,2), R(4,3), R(4,4), R(4,5), R(4,6), R(4,7), and R(4,8).
  • the first input end of R(4,1) is connected to the first output end of the first second logic gate R(3,1) of the third level, the second input end of R(4,1) inputs the value of the first bit of the indication queue, the output of the first output end of R(4,1) indicates whether the storage unit corresponding to the first bit of the indication queue is idle, and the output of the second output end of R(4,1) indicates whether the storage unit corresponding to the second bit of the indication queue is idle.
  • the first input end of R(4,2) is connected to the second output end of the first second logic gate R(3,1) of the third level, the second input end of R(4,2) inputs the value of the third bit of the indication queue, the output of the first output end of R(4,2) indicates whether the storage unit corresponding to the third bit of the indication queue is idle, and the output of the second output end of R(4,2) indicates whether the storage unit corresponding to the fourth bit of the indication queue is idle.
  • the first input end of R(4,3) is connected to the first output end of the second second logic gate R(3,2) of the third level, the second input end of R(4,3) inputs the value of the 5th bit of the indication queue, the output of the first output end of R(4,3) indicates whether the storage unit corresponding to the 5th bit of the indication queue is idle, and the output of the second output end of R(4,3) indicates whether the storage unit corresponding to the 6th bit of the indication queue is idle.
  • the first input end of R(4,4) is connected to the second output end of the second second logic gate R(3,1) of the third level, the second input end of R(4,4) inputs the value of the 7th bit of the indication queue, the output of the first output end of R(4,4) indicates whether the storage unit corresponding to the 7th bit of the indication queue is idle, and the output of the second output end of R(4,4) indicates whether the storage unit corresponding to the 8th bit of the indication queue is idle.
  • the first input end of R(4,5) is connected to the first output end of the third second logic gate R(3,3) of the third level, the second input end of R(4,5) inputs the value of the 9th bit of the indication queue, the output of the first output end of R(4,5) indicates whether the storage unit corresponding to the 9th bit of the indication queue is idle, and the output of the second output end of R(4,5) indicates whether the storage unit corresponding to the 10th bit of the indication queue is idle.
  • the first input end of R(4,6) is connected to the second output end of the third second logic gate R(3,3) of the third level, the second input end of R(4,6) inputs the value of the 11th bit of the indication queue, the output of the first output end of R(4,6) indicates whether the storage unit corresponding to the 11th bit of the indication queue is idle, and the output of the second output end of R(4,6) indicates whether the storage unit corresponding to the 12th bit of the indication queue is idle.
  • the first input end of R(4,7) is connected to the first output end of the fourth second logic gate R(3,4) of the third level, the second input end of R(4,7) inputs the value of the 13th bit of the indication queue, the output of the first output end of R(4,7) indicates whether the storage unit corresponding to the 13th bit of the indication queue is idle, and the output of the second output end of R(4,7) indicates whether the storage unit corresponding to the 14th bit of the indication queue is idle.
  • the first input end of R(4,8) is connected to the second output end of the fourth second logic gate R(3,4) of the third level, the second input end of R(4,8) inputs the value of the 15th bit of the indication queue, the output of the first output end of R(4,8) indicates whether the storage unit corresponding to the 15th bit of the indication queue is idle, and the output of the second output end of R(4,8) indicates whether the storage unit corresponding to the 16th bit of the indication queue is idle.
  • the second logic gate includes: a first AND gate, a second AND gate, a first inverter, a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
  • the first AND gate and the second AND gate each include two input terminals and one output terminal;
  • the first inverter includes an input terminal and an output terminal;
  • One input end of the first AND gate and the second AND gate are both connected to the first input end of the second logic gate, the other input end of the first AND gate is connected to the second input end of the second logic gate, the other input end of the second AND gate is connected to the output end of the first inverter, and the input end of the first inverter is connected to the second input end of the second logic gate; the output end of the first AND gate is connected to the first output end of the second logic gate, and the output end of the second AND gate is connected to the second output end of the second logic gate.
  • the second logic gate includes: a first OR gate, a second OR gate, a second inverter, a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
  • the first OR gate and the second OR gate each include two input terminals and one output terminal;
  • the second inverter includes an input terminal and an output terminal;
  • One input end of the first OR gate and the second OR gate are both connected to the first input end of the second logic gate, and the other input end of the first OR gate is connected to the second input end of the second logic gate.
  • the other input end of the second OR gate is connected to the output end of the second inverter, and the input end of the second inverter is connected to the second input end of the second logic gate; the output end of the first OR gate is connected to the first output end of the second logic gate, and the output end of the second OR gate is connected to the second output end of the second logic gate.
  • the second logic gate when the value of any element in the indication queue is 0, it indicates that the storage unit corresponding to the element is occupied, and the value is 1, it indicates that the storage unit corresponding to the element is idle, then the second logic gate is a combination of OR gates, "0" indicates “false", and “1” indicates “true”.
  • the second logic gate is a combination of AND gates, "1" indicates “false", and "0” indicates "true”.
  • the second logic gate includes a first AND gate R1, a second AND gate R2, a first inverter D1, a first input terminal X1, a second input terminal X2, a first output terminal Y1, and a second output terminal Y2; the first AND gate and the second AND gate each include two input terminals and one output terminal;
  • One input end of the first AND gate is connected to the first input end of the second logic gate, and the other input end is connected to the output end of the first inverter, the input end of the first inverter is connected to the second input end of the second logic gate; the output end of the first AND gate is connected to the first output end of the second logic gate;
  • Two input terminals of the second AND gate are respectively connected to the first input terminal and the second input terminal of the second logic gate, and one output terminal is connected to the second output terminal of the second logic gate.
  • the processing logic of the second logic gate shown in FIG9-1 is: when the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, then the output y2 of the second output terminal is true and the output y1 of the first output terminal is false, when the input x2 of the second input terminal is false, then the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • the value of any element in the indication queue is 0, indicating that the storage unit corresponding to the element is occupied, and the value is 1, indicating that the storage unit corresponding to the element is idle.
  • "0" represents "false” and "1" represents "true”.
  • the second logic gate includes a third AND gate R3, fourth AND gate R4 and second inverter D2, first input terminal X1, second input terminal X2, first output terminal Y1 and second output terminal Y2; the third AND gate and the fourth AND gate each include two input terminals and one output terminal;
  • Two input terminals of the third AND gate are respectively connected to the first input terminal and the second input terminal of the second logic gate, and one output terminal is connected to the first output terminal of the second logic gate;
  • One input end of the fourth AND gate is connected to the first input end of the second logic gate, and the other input end is connected to the output end of the second inverter.
  • the input end of the second inverter is connected to the second input end of the second logic gate; the output end of the fourth AND gate is connected to the second output end of the second logic gate.
  • the processing logic of the second logic gate shown in FIG9-2 is: when the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, then the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x2 of the second input terminal is false, then the output y2 of the second output terminal is true and the output y1 of the first output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • the value of any element in the indication queue is 0, indicating that the storage unit corresponding to the element is occupied, and the value is 1, indicating that the storage unit corresponding to the element is idle.
  • "0" represents "false” and "1" represents "true”.
  • the second logic gate includes a first OR gate L1, a second OR gate L2, a third inverter D3, a first input terminal X1, a second input terminal X2, a first output terminal Y1, and a second output terminal Y2; the first OR gate and the second OR gate each include two input terminals and one output terminal;
  • One input end of the first OR gate is connected to the first input end of the second logic gate, and the other input end is connected to the output end of the first inverter, the input end of the first inverter is connected to the second input end of the second logic gate; the output end of the first OR gate is connected to the first output end of the second logic gate;
  • Two input terminals of the second OR gate are respectively connected to the first input terminal and the second input terminal of the second logic gate, and one output terminal is connected to the second output terminal of the second logic gate.
  • the processing logic of the second logic gate shown in FIG. 10-1 is: When the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, the output y2 of the second output terminal is true and the output y1 of the first output terminal is false; when the input x2 of the second input terminal is false, the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • the value of any element in the indication queue is 1, indicating that the storage unit corresponding to the element is occupied, and the value is 0, indicating that the storage unit corresponding to the element is idle.
  • "1" means “false” and "0” means "true”.
  • the second logic gate includes a third OR gate L3, a fourth OR gate L4, a fourth inverter D4, a first input terminal X1, a second input terminal X2, a first output terminal Y1, and a second output terminal Y2; the first OR gate and the second OR gate each include two input terminals and one output terminal;
  • Two input terminals of the third OR gate are respectively connected to the first input terminal and the second input terminal of the second logic gate, and one output terminal is connected to the first output terminal of the second logic gate;
  • One input end of the fourth OR gate is connected to the first input end of the second logic gate, and the other input end is connected to the output end of the fourth inverter.
  • the input end of the fourth inverter is connected to the second input end of the second logic gate; the output end of the fourth OR gate is connected to the second output end of the second logic gate.
  • the processing logic of the second logic gate shown in FIG. 10-2 is: when the input x1 of the first input terminal is true, when the input x2 of the second input terminal is true, then the output y1 of the first output terminal is true and the output y2 of the second output terminal is false; when the input x2 of the second input terminal is false, then the output y2 of the second output terminal is true and the output y1 of the first output terminal is false; when the input x1 of the first input terminal is false, the output y1 of the first output terminal and the output y2 of the second output terminal are both false.
  • the value of any element in the indication queue is 1, indicating that the storage unit corresponding to the element is occupied, and the value is 0, indicating that the storage unit corresponding to the element is idle.
  • "1" indicates “false” and "0" indicates "true”.
  • the present disclosure provides a method for searching for free storage. As shown in FIG11 , the method for searching for free storage includes:
  • Step S10 constructing an indication queue for a storage block to indicate the occupancy of storage units in the storage block; wherein the indication queue includes a plurality of elements, and the value of the element is used to indicate whether the storage unit corresponding to the element is idle;
  • Step S20 before writing the target data to the storage block, obtain the information of the indication queue of the storage block through the first logic gate tree, and judge whether there are free storage cells in the storage block according to the information of the indication queue; when there are free storage cells in the storage block, use the second logic gate tree to search for a target element indicating a free storage cell from the indication queue of the storage block according to the binary search rule, and use the free storage cell corresponding to the target element as the target free storage cell to write the target data.
  • the method for searching free storage builds an indication queue for a storage block to indicate the occupancy of storage units in the storage block; before writing target data to the storage block, obtains information of the indication queue of the storage block through a first logic gate tree, and determines whether there are free storage units in the storage block according to the information of the indication queue; when there are free storage units in the storage block, searches for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule using a second logic gate tree, and uses the free storage unit corresponding to the target element as a target free storage unit to write the target data. Since the binary search can reduce the search amount by half, the method for searching free storage provided by the above embodiment can speed up the search for free storage.
  • the storage block is a cache.
  • the elements of the indication queue are 1-bit binary numbers.
  • the value of the indication queue may be stored in a register, and each bit of the register corresponds one-to-one to each element of the indication queue.
  • the numerical value of the element is used to indicate whether the storage unit corresponding to the element is free, including: 0 indicates that the storage unit corresponding to the element is occupied (not free), and 1 indicates that the storage unit corresponding to the element is free; or, 1 indicates that the storage unit corresponding to the element is occupied (not free), and 0 indicates that the storage unit corresponding to the element is free.
  • acquiring the information of the indication queue of the storage block through the first logic gate tree includes:
  • the following information is obtained through the first logic gate group of the first level: whether there is an element indicating a free storage unit in each first level sub-queue of the indication queue; wherein the first level sub-queues of the indication queue are 2 m-1 in total;
  • the k-th level first logic gate group of the first logic gate tree is used to obtain the following information: whether there is an element indicating a free storage unit in each k-th level sub-queue of the indication queue; wherein the k-th level sub-queues of the indication queue are 2mk in total; 2 ⁇ k ⁇ m-1;
  • the following information is obtained through the first logic gate group of the mth stage: whether there is an element indicating a free storage unit among all elements of the indication queue;
  • searching for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule using the second logic gate tree includes:
  • the output of the second logic gate of the previous level is input to the first input terminal of the second logic gate of the kth level
  • the output of the first logic gate of the m-kth level is input to the second input terminal
  • the outputs of the two output terminals are respectively used as the inputs of two adjacent second logic gates of the next level; 2 ⁇ k ⁇ m-1;
  • the output of the second logic gate of the previous level is input to the first input terminal of the second logic gate of the mth level of the second logic gate tree, the value of an element of the indication queue is input to the second input terminal, and the outputs of the two output terminals respectively indicate whether the storage cells corresponding to the element and the adjacent elements of the element of the indication queue are free storage cells;
  • the processing logic of the second logic gate is as follows: when the input of the first input terminal is true, one and only one of the outputs of the two output terminals is true, and the input of the second input terminal is used to determine which output terminal's output is true; when the input of the first input terminal is false, the outputs of the two output terminals are both false.
  • the method further includes: after writing the target data into the target free storage unit, updating the indication queue corresponding to the target free storage unit through a second logic gate tree: modifying the value of the target element corresponding to the target free storage unit in the indication queue to indicate that the storage unit is occupied.
  • the method further includes: after reading data from the target storage unit, updating the indication queue corresponding to the target storage unit through a second logic gate tree: modifying the value of the target element corresponding to the target storage unit in the indication queue to indicate that the storage unit is idle.
  • searching for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule includes:
  • Step b Split the original bit sequence H(i) of the i-th round into two halves to generate the i-th round first subsequence H1(i) containing the lower x(i)/2 bits and the i-th round second subsequence H2(i) containing the upper x(i)/2 bits;
  • x(i) is the number of original bits of the original bit sequence H(i) in round i;
  • Step c performing a first logic operation on all bits of the second subsequence H2(i) of the i-th round;
  • Step d Determine whether there is a bit indicating that the storage unit is idle in the second subsequence H2(i) of the i-th round according to the result of the first logical operation, if yes, execute step e, otherwise execute step f;
  • Step e increase i by 1, take the second subsequence H2(i-1) of the i-1th round as the original bit sequence H(i) of the i-th round, and go to step g;
  • Step f increase i by 1, take the first subsequence H1(i-1) of the i-1th round as the original bit sequence H(i) of the i-th round, and go to step g;
  • Step g Determine whether i is greater than or equal to m, if yes, go to step h, otherwise go to step b;
  • the original number of bits x(m) of the original bit sequence H(m) of the mth round is 2;
  • Step h determine whether the value of the high bit of the original bit sequence H(m) of the mth round indicates that the corresponding storage unit is idle, if yes, execute step i, otherwise execute step j;
  • Step i Take the high bit of the original bit sequence H(m) of the mth round as the target bit (target element), and end;
  • the storage unit indicated by the target element is a free storage unit
  • Step j Take the low bit of the original bit sequence H(m) of the mth round as the target bit (target element), and end;
  • the storage unit indicated by the target element is a free storage unit
  • the first logical operation when the value of any one bit in the indication queue is 0, it indicates that the storage unit corresponding to the bit is occupied, and the value is 1, it indicates that the storage unit corresponding to the bit is idle, then the first logical operation is an OR operation; when the value of any one bit in the indication queue is 1, it indicates that the storage unit corresponding to the bit is occupied, and the value is 0, it indicates that the storage unit corresponding to the bit is idle, then the first logical operation is an AND operation. For example, assuming that the bit sequence is a 0 a 1 a 2 ... a n , performing an OR operation on all bits in the bit sequence means: a 0 U a 1 U a 2 ... U a n .
  • the result of performing an OR operation on all bits is 0; when the value of at least one bit in the bit sequence is 1, the result of performing an OR operation on all bits is 1.
  • performing an AND operation on all bits in the bit sequence means: a 0 I a 1 I a 2 ... I a n .
  • the result of the AND operation on all bits is 1; when the value of at least one bit in the bit sequence is 0, the result of the AND operation on all bits is 0.
  • searching for a target element indicating a free storage unit from the indication queue of the storage block according to a binary search rule includes:
  • Step b Split the original bit sequence H(i) of the i-th round into two halves to generate the i-th round first subsequence H1(i) containing the lower x(i)/2 bits and the i-th round second subsequence H2(i) containing the upper x(i)/2 bits; where x(i) is the original number of bits of the original bit sequence H(i) of the i-th round;
  • Step c performing a first logic operation on all bits of the first subsequence H1(i) of the i-th round;
  • Step d Determine whether there is a bit indicating that the storage unit is idle in the first subsequence H1(i) of the i-th round according to the result of the first logical operation, if yes, execute step e, otherwise execute step f;
  • Step e increase i by 1, take the first subsequence H1(i-1) of the i-1th round as the original bit sequence H(i) of the i-th round, and go to step g;
  • Step f increase i by 1, take the second subsequence H2(i-1) of the i-1th round as the original bit sequence H(i) of the i-th round, and go to step g;
  • Step g Determine whether i is greater than or equal to m, if yes, go to step h, otherwise go to step b;
  • the original number of bits x(m) of the original bit sequence H(m) of the mth round is 2;
  • Step h determine whether the value of the low bit of the original bit sequence H(m) of the mth round indicates that the corresponding storage unit is idle, if yes, execute step i, otherwise execute step j;
  • Step i Take the low bit of the original bit sequence H(m) of the mth round as the target bit (target element), and end;
  • the storage unit indicated by the target element is a free storage unit
  • Step j Use the high bit of the original bit sequence H(m) of the mth round as the target bit (target element), and end;
  • the storage unit indicated by the target element is a free storage unit
  • the first logical operation is an OR operation
  • the value of any bit in the indication queue is 1, it means that the storage unit corresponding to the bit is occupied, and the value is 0, it means that the storage unit corresponding to the bit is idle, then the first logical operation is an AND operation.
  • the indication queue is an 8-bit bit sequence, assuming that a value of 0 indicates that the storage unit corresponding to the bit is occupied, and a value of 1 indicates that the storage unit corresponding to the bit is idle.
  • the indication queue is "00110101"
  • the binary search algorithm is that the storage unit corresponding to the lowest bit has the lowest search priority, and the storage unit corresponding to the highest bit has the highest search priority, then the storage unit corresponding to the 6th bit of the indication queue will be used as the target idle storage unit.
  • the storage unit corresponding to the 1st bit of the indication queue will be used as the target idle storage unit.
  • the indication queue is an 8-bit bit sequence. If the value is 1, it means that the storage unit corresponding to the bit is occupied, and if the value is 0, it means that the storage unit corresponding to the bit is idle.
  • the storage unit corresponding to the 8th bit of the indication queue will be used as the target free storage unit.
  • the storage unit corresponding to the 2nd bit of the indication queue will be used as the target free storage unit.
  • An embodiment of the present disclosure provides a chip, including the above-mentioned device for searching for free storage.
  • the functional modules/units in the apparatus disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof.
  • the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation.
  • Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application specific integrated circuit.

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Abstract

本文公开一种查找空闲存储的装置、方法及芯片。查找空闲存储的装置包括：指示队列处理模块，设置为为存储块构建指示队列以表示存储块中存储单元的占用情况；指示队列包括多个元素，元素的数值用于指示元素对应的存储单元是否空闲；信息收集模块，设置为在向存储块写入目标数据前，通过第一逻辑门树获取存储块的指示队列的信息，根据所述信息判断存储块中是否存在空闲存储单元；仲裁及控制模块，设置为当存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将目标元素对应的空闲存储单元作为目标空闲存储单元以写入目标数据。

Description

查找空闲存储的装置、方法及芯片
交叉引用
本公开要求于2022年9月26日提交中国专利局、申请号为202211169106.5、发明名称为“查找空闲存储的装置、方法及芯片”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开实施例涉及但不限于集成电路设计领域，尤其涉及一种查找空闲存储的装置、方法及芯片。
背景技术
在很多需要使用片内缓存的芯片应用场景下，为避免把已经写入的数据覆盖，通常需要查询缓存地址是否被占用。由于数据的读写行为具有随机性，即存储地址的占用和解除带有随机性，因此需要反复去检查存储地址的占用情况。
当面对大缓存深度的存储器时，一旦存储器处于大部分被占用的情况，则查找空闲存储的逻辑路径会相当冗长，当系统频率很高时，可能无法在单个系统时钟周期内完成空闲存储的查找。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种查找空闲存储的装置，包括：
指示队列处理模块，设置为为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
信息收集模块，设置为在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述 存储块中是否存在空闲存储单元；
仲裁及控制模块，设置为当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
本公开实施例提供了一种查找空闲存储的方法，包括：
为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
本公开实施例提供了一种芯片，包括上述查找空闲存储的装置。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例的一种查找空闲存储的装置的结构示意图；
图2为本公开实施例的一种第一逻辑门树的结构示意图；
图3为图2所示的第一逻辑门树的一个示例的结构示意图(指示队列包括16比特)；
图4为本公开实施例的一种第二逻辑门树的结构示意图；
图5为本公开实施例的另一种第二逻辑门树的结构示意图；
图6为图5所示的第二逻辑门树的一个示例的结构示意图(指示队列包括16比特)；
图7为本公开实施例的另一种第二逻辑门树的结构示意图；
图8为图7所示的第二逻辑门树的一个示例的结构示意图(指示队列包括16比特)；
图9-1为本公开实施例的一种第二逻辑门的结构示意图(与门的组合)；
图9-2为本公开实施例的另一种第二逻辑门的结构示意图(与门的组合)；
图10-1为本公开实施例的另一种第二逻辑门的结构示意图(或门的组合)；
图10-2为本公开实施例的另一种第二逻辑门的结构示意图(或门的组合)；
图11为本公开实施例的一种查找空闲存储的方法的流程图；
图12-1为本公开实施例的一种通过二分法搜索目标位的方法流程图；
图12-2为本公开实施例的另一种通过二分法搜索目标位的方法流程图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组 合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由所附权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由所附权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
本公开实施例提供一种查找空闲存储的装置。如图1所示，一种查找空闲存储的装置，包括：
指示队列处理模块10，设置为为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
信息收集模块20，设置为在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；
仲裁及控制模块30，设置为当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
本公开实施例提供的查找空闲存储的装置包括指示队列处理模块、信息收集模块和仲裁及控制模块。指示队列处理模块为存储块构建指示队列以表示所述存储块中存储单元的占用情况；信息收集模块在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述 指示队列的信息判断所述存储块中是否存在空闲存储单元；仲裁及控制模块当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。由于二分法可以缩小一半的搜索量，因此上述实施例提供的查找空闲存储的装置能够加快查找空闲存储的速度。
在一些示例性的实施方式中，所述存储块为缓存。
在一些示例性的实施方式中，所述指示队列的元素为1比特二进制数。
在一些示例性的实施方式中，所述指示队列的数值可以保存在寄存器中，寄存器的每位与指示队列的每个元素一一对应。
在一些示例性的实施方式中，所述元素的数值用于指示该元素对应的存储单元是否空闲，包括：0表示该元素对应的存储单元被占用(不空闲)，1表示该元素对应的存储单元为空闲；或者，1表示该元素对应的存储单元被占用(不空闲)，0表示该元素对应的存储单元为空闲。
在一些示例性的实施方式中，信息收集模块，设置为采用以下方式通过第一逻辑门树获取所述存储块的指示队列的信息：
通过第1级第一逻辑门组获取以下信息：指示队列的每个第1级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第1级子队列共2m-1个；
当m大于2时，所述第一逻辑门树的第k级第一逻辑门组用于获取以下信息：指示队列的每个第k级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第k级子队列共2m-k个；2≤k≤m-1；
通过第m级第一逻辑门组获取以下信息：指示队列的所有元素中是否存在指示空闲存储单元的元素；
其中，所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N为存储块包含的存储单元的总数，N＝2m；m为大于1的正整数。
在一些示例性的实施方式中，仲裁及控制模块，设置为采用以下方式利 用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素：
向所述第二逻辑门树的第1级第二逻辑门输入第m级第一逻辑门的输出以及第m-1级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；
当m大于2时，向所述第二逻辑门树的第k级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入第m-k级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；2≤k≤m-1；
向所述第二逻辑门树的第m级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入指示队列的一个元素的数值，两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
其中，所述第二逻辑门的处理逻辑为：当第一输入端的输入为真时，两个输出端中有且仅有一个的输出为真，第二输入端的输入用于确定哪一个输出端的输出为真；当第一输入端的输入为假时，两个输出端的输出均为假。
在一些示例性的实施方式中，所述仲裁及控制模块，还设置为将所述目标数据写入所述目标空闲存储单元中后，通过第二逻辑门树向指示队列处理模块发送第一控制信号；其中，所述第一控制信号携带所述目标空闲存储单元对应的指示队列中的目标元素的信息；
所述指示队列处理模块，还设置为接收到第一控制信号，更新所述目标空闲存储单元对应的指示队列：将所述指示队列中所述目标空闲存储单元对应的目标元素的数值修改为指示所述存储单元被占用。
在一些示例性的实施方式中，所述仲裁及控制模块，还设置为从目标存储单元中读出数据后，通过第二逻辑门树向指示队列处理模块发送第二控制信号；其中，所述第二控制信号携带所述目标存储单元对应的指示队列中的目标元素的信息；
所述指示队列处理模块，还设置为接收到第二控制信号，更新所述目标 存储单元对应的指示队列：将所述指示队列中所述目标存储单元对应的目标元素的数值修改为指示所述存储单元为空闲。
在一些示例性的实施方式中，所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N为存储块包含的存储单元的总数，N＝2m；m为大于1的正整数；
所述第一逻辑门包括：两个输入端和一个输出端；
所述第一逻辑门树的第1级第一逻辑门的两个输入端分别输入指示队列的两个相邻元素的数值，输出端连接下一级的第一逻辑门的输入端；
所述第一逻辑门树的第m级第一逻辑门的两个输入端分别连接两个相邻的上一级第一逻辑门的输出端，输出端的输出用于指示所述指示队列对应的存储块中是否存在空闲存储单元；
当m大于2时，所述第一逻辑门树的第k级第一逻辑门的两个输入端分别连接两个相邻的上一级第一逻辑门的输出端，输出端连接下一级的第一逻辑门的输入端；2≤k≤m-1；
所述第一逻辑门的处理逻辑为：当两个输入端的输入中至少一个为真时，输出端的输出为真；当两个输入端的输入均为假时，输出端的输出为假。
在一些示例性的实施方式中，如图2所示，所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N＝2m；m为大于1的正整数；
第一逻辑门包括：第一输入端、第二输入端和输出端；
第1级第j个第一逻辑门L(1,j)的第一输入端输入指示队列的第2j-1位，L(1,j)的第二输入端输入指示队列的第2j位；1≤j≤2m-1；
第m级第一逻辑门包括一个第一逻辑门L(m,1)，L(m,1)的第一输入端连接第m-1级第1个第一逻辑门L(m-1,1)的输出端，L(m,1)的第二输入端连接第m-1级第2个第一逻辑门L(m-1,2)的输出端；
当m大于2时，第k级第j个第一逻辑门L(k,j)的第一输入端连接第k-1级第2j-1个第一逻辑门L(k-1,2j-1)的输出端，L(k,j)的第二输入端连接第k-1级第2j个第一逻辑门L(k-1,2j)的输出端；2≤k≤m-1；1≤j≤2m-k。
下述表1是第一逻辑门的一种真值表。第一输入端的输入为x1、第二输入端的输入为x2，输出端的输出为y。
表1
如图3所示，假设指示队列包括16个元素，每个元素是1比特的二进制数(0或者1)，N＝16＝24；第一逻辑门树包括4级级联的第一逻辑门L(i,j)组，1≤i≤4,1≤j≤24-i。
第一级第一逻辑门组包括8个第一逻辑门，分别是：L(1,1)，L(1,2)，L(1,3)，L(1,4)，L(1,5)，L(1,6)，L(1,7)，L(1,8)。L(1,1)的两个输入分别是：指示队列的第1位和第2位。L(1,2)的两个输入分别是：指示队列的第3位和第4位。L(1,3)的两个输入分别是：指示队列的第5位和第6位。L(1,4)的两个输入分别是：指示队列的第7位和第8位。L(1,5)的两个输入分别是：指示队列的第9位和第10位。L(1,6)的两个输入分别是：指示队列的第11位和第12位。L(1,5)的两个输入分别是：指示队列的第13位和第14位。L(1,6)的两个输入分别是：指示队列的第15位和第16位。
第二级第一逻辑门组包括4个第一逻辑门，分别是：L(2,1)，L(2,2)，L(2,3)，L(2,4)。L(2,1)的两个输入分别是：L(1,1)的输出和L(1,2)的输出。L(2,2)的两个输入分别是：L(1,3)的输出和L(1,4)的输出。L(2,3)的两个输入分别是：L(1,5)的输出和L(1,6)的输出。L(2,4)的两个输入分别是：L(1,7)的输出和L(1,8)的输出。
第三级第一逻辑门组包括2个第一逻辑门，分别是：L(3,1)，L(3,2)。L(3,1)的两个输入分别是：L(2,1)的输出和L(2,2)的输出。L(3,2)的两个输入分别是：L(2,3)的输出和L(2,4)的输出。
第四级第一逻辑门组包括1个第一逻辑门L(4,1)。L(4,1)的两个输入分别 是：L(3,1)的输出L(3,2)的输出。
在一些示例性的实施方式中，所述第二逻辑门树包括级联的m级第二逻辑门组，第i级第二逻辑门组包括2i-1个第二逻辑门R(i,j)；其中，1≤i≤m；1≤j≤2i-1；N＝2m，m为大于1的正整数；
所述第二逻辑门包括：第一输入端、第二输入端和两个输出端；
所述第二逻辑门树的第1级第二逻辑门的第一输入端连接第m级第一逻辑门的输出端，第二输入端连接第m-1级第一逻辑门的输出端，两个输出端分别连接两个相邻的下一级第二逻辑门的输入端；
所述第二逻辑门树的第m级第二逻辑门的第一输入端连接上一级第二逻辑门的输出端，第二输入端输入指示队列的一个元素的数值，两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
当m大于2时，所述第二逻辑门树的第k级第二逻辑门的第一输入端连接上一级第二逻辑门的输出端，第二输入端连接第m-k级第一逻辑门的输出端，两个输出端分别连接两个相邻的下一级第二逻辑门的输入端；
所述第二逻辑门的处理逻辑为：当第一输入端的输入为真时，两个输出端中有且仅有一个的输出为真，第二输入端的输入用于确定哪一个输出端的输出为真；当第一输入端的输入为假时，两个输出端的输出均为假。
在一些示例性的实施方式中，如图4所示，所述第二逻辑门树包括级联的m级第二逻辑门组，第i级第二逻辑门组包括2i-1个第二逻辑门R(i,j)；其中，1≤i≤m；1≤j≤2i-1；N＝2m，m为大于1的正整数；任意一个第二逻辑门包括：两个输入端和两个输出端；
第1级第二逻辑门R(1,1)的两个输入端分别连接第m级第一逻辑门的输出端和第m-1级第一逻辑门的输出端，R(1,1)的两个输出端分别连接两个相邻的第2级第二逻辑门的输入端；
第m级第j个第二逻辑门R(m,j)的两个输入端中的一个连接第k-1级第 二逻辑门的输出端，另一个输入指示队列H的一个元素的数值，R(m,j)的两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
当m大于2时，第k级第j个第二逻辑门R(k,j)的两个输入端分别连接第k-1级第二逻辑门的输出端和第m-k级第一逻辑门的输出端，R(k,j)的两个输出端分别连接两个相邻的第k+1级第二逻辑门的输入端；2≤k≤m-1。
在一些示例性的实施方式中，如图5所示，所述第二逻辑门树包括级联的m级第二逻辑门组，第i级第二逻辑门组包括2i-1个第二逻辑门R(i,j)；其中，1≤i≤m；1≤j≤2i-1；N＝2m，m为大于1的正整数；
任意一个第二逻辑门包括：第一输入端、第二输入端、第一输出端和第二输出端；
第1级第二逻辑门R(1,1)的第一输入端连接第m级第1个第一逻辑门L(m,1)的输出端，R(1,1)的第二输入端连接第m-1级第2个第一逻辑门L(m-1,2)的输出端，R(1,1)的第一输出端连接第2级第1个第二逻辑门R(2,1)的第一输入端，R(1,1)的第二输出端连接第2级第2个第二逻辑门R(2,2)的第一输入端；
第m级第2t-1个第二逻辑门R(m,2t-1)的第一输入端连接第m-1级第t个第二逻辑门R(m-1,t)的第一输出端，R(m,2t-1)的第二输入端输入指示队列的第4t-2个元素的数值，R(m,2t-1)的第一输出端的输出表示指示队列的第4t-3个元素对应的存储单元是否空闲，R(m,2t-1)的第二输出端的输出表示指示队列的第4t-2个元素对应的存储单元是否空闲；1≤t≤2m-2；
第m级第2t个第二逻辑门R(m,2t)的第一输入端连接第m-1级第t个第二逻辑门R(m-1,t)的第二输出端，R(m,2t)的第二输入端输入指示队列的第4t个元素的数值，R(m,2t)的第一输出端的输出表示指示队列的第4t-1个元素对应的存储单元是否空闲，R(m,2t)的第二输出端的输出表示指示队列的第4t个元素对应的存储单元是否空闲；1≤t≤2m-2；
当m大于2时，第k级第2t-1个第二逻辑门R(k,2t-1)的第一输入端连接第k-1级第t个第二逻辑门R(k-1,t)的第一输出端，R(k,2t-1)的第二输入端 连接第m-k级第4t-2个第一逻辑门L(m-k,4t-2)的输出端，R(k,2t-1)的第一输出端连接第k+1级第4t-3个第二逻辑门R(k+1,4t-3)的第一输入端，R(k,2t-1)的第二输出端连接第k+1级第4t-2个第二逻辑门R(k+1,4t-2)的第一输入端；其中，2≤k≤m-1；1≤t≤2k-2；
当m大于2时，第k级第2t个第二逻辑门R(k,2t)的第一输入端连接第k-1级第t个第二逻辑门R(k-1,t)的第二输出端，R(k,2t)的第二输入端连接第m-k级第4t个第一逻辑门L(m-k,4t)的输出端，R(k,2t)的第一输出端连接第k+1级第4t-1个第二逻辑门R(k+1,4t-1)的第一输入端，R(k,2t)的第二输出端连接第k+1级第4t个第二逻辑门R(k+1,4t)的第一输入端；其中，2≤k≤m-1；1≤t≤2k-2。
在一些示例性的实施方式中，所述第二逻辑门的处理逻辑为：当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第二输出端的输出y2为真且第一输出端的输出y1为假，当第二输入端的输入x2为假，则第一输出端的输出y1为真且第二输出端的输出y2为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。
下述表2是第二逻辑门的一种真值表。
表2
在上述表2中，“*”表示“真”和“假”均可。
如图6所示，假设指示队列包括16个元素，每个元素是1比特的二进制数(0或者1)，N＝16＝24；第二逻辑门树包括4级级联的第二逻辑门R(i,j)组，1≤i≤4,1≤j≤2i-1。
第1级第二逻辑门组包括1个第二逻辑门R(1,1)。R(1,1)的第一输入端连 接第4级第1个第一逻辑门L(4,1)的输出端，R(1,1)的第二输入端连接第3级第2个第一逻辑门L(3,2)的输出端，R(1,1)的第一输出端连接第2级第1个第二逻辑门R(2,1)的第一输入端，R(1,1)的第二输出端连接第2级第2个第二逻辑门R(2,2)的第一输入端。
第2级第二逻辑门组包括2个第二逻辑门，分别是：R(2,1)和R(2,2)。
R(2,1)的第一输入端连接第1级第1个第二逻辑门R(1,1)的第一输出端，R(2,1)的第二输入端连接第2级第2个第一逻辑门L(2,2)的输出端，R(2,1)的第一输出端连接第3级第1个第二逻辑门R(3,1)的第一输入端，R(2,1)的第二输出端连接第3级第2个第二逻辑门R(3,2)的第一输入端。
R(2,2)的第一输入端连接第1级第1个第二逻辑门R(1,1)的第二输出端，R(2,2)的第二输入端连接第2级第4个第一逻辑门L(2,4)的输出端，R(2,2)的第一输出端连接第3级第3个第二逻辑门R(3,3)的第一输入端，R(2,2)的第二输出端连接第3级第4个第二逻辑门R(3,4)的第一输入端。
第3级第二逻辑门组包括4个第二逻辑门，分别是：R(3,1)、R(3,2)、R(3,3)和R(3,4)。
R(3,1)的第一输入端连接第2级第1个第二逻辑门R(2,1)的第一输出端，R(3,1)的第二输入端连接第1级第2个第一逻辑门L(1,2)的输出端，R(3,1)的第一输出端连接第4级第1个第二逻辑门R(4,1)的第一输入端，R(3,1)的第二输出端连接第4级第2个第二逻辑门R(4,2)的第一输入端。
R(3,2)的第一输入端连接第2级第1个第二逻辑门R(2,1)的第二输出端，R(3,2)的第二输入端连接第1级第4个第一逻辑门L(1,4)的输出端，R(3,2)的第一输出端连接第4级第3个第二逻辑门R(4,3)的第一输入端，R(3,2)的第二输出端连接第4级第4个第二逻辑门R(4,4)的第一输入端。
R(3,3)的第一输入端连接第2级第2个第二逻辑门R(2,2)的第一输出端，R(3,3)的第二输入端连接第1级第6个第一逻辑门L(1,6)的输出端，R(3,3)的第一输出端连接第4级第5个第二逻辑门R(4,5)的第一输入端，R(3,3)的第二输出端连接第4级第6个第二逻辑门R(4,6)的第一输入端。
R(3,4)的第一输入端连接第2级第2个第二逻辑门R(2,2)的第二输出端， R(3,4)的第二输入端连接第1级第8个第一逻辑门L(1,8)的输出端，R(3,4)的第一输出端连接第4级第7个第二逻辑门R(4,7)的第一输入端，R(3,4)的第二输出端连接第4级第8个第二逻辑门R(4,8)的第一输入端。
第4级第二逻辑门组包括8个第二逻辑门，分别是：R(4,1)、R(4,2)、R(4,3)、R(4,4)、R(4,5)、R(4,6)、R(4,7)、R(4,8)。
R(4,1)的第一输入端连接第3级第1个第二逻辑门R(3,1)的第一输出端，R(4,1)的第二输入端输入指示队列的第2位的数值，R(4,1)的第一输出端的输出表示指示队列的第1位对应的存储单元是否空闲，R(4,1)的第二输出端的输出表示指示队列的第2位对应的存储单元是否空闲。
R(4,2)的第一输入端连接第3级第1个第二逻辑门R(3,1)的第二输出端，R(4,2)的第二输入端输入指示队列的第4位的数值，R(4,2)的第一输出端的输出表示指示队列的第3位对应的存储单元是否空闲，R(4,2)的第二输出端的输出表示指示队列的第4位对应的存储单元是否空闲。
R(4,3)的第一输入端连接第3级第2个第二逻辑门R(3,2)的第一输出端，R(4,3)的第二输入端输入指示队列的第6位的数值，R(4,3)的第一输出端的输出表示指示队列的第5位对应的存储单元是否空闲，R(4,3)的第二输出端的输出表示指示队列的第6位对应的存储单元是否空闲。
R(4,4)的第一输入端连接第3级第2个第二逻辑门R(3,1)的第二输出端，R(4,4)的第二输入端输入指示队列的第8位的数值，R(4,4)的第一输出端的输出表示指示队列的第7位对应的存储单元是否空闲，R(4,4)的第二输出端的输出表示指示队列的第8位对应的存储单元是否空闲。
R(4,5)的第一输入端连接第3级第3个第二逻辑门R(3,3)的第一输出端，R(4,5)的第二输入端输入指示队列的第10位的数值，R(4,5)的第一输出端的输出表示指示队列的第9位对应的存储单元是否空闲，R(4,5)的第二输出端的输出表示指示队列的第10位对应的存储单元是否空闲。
R(4,6)的第一输入端连接第3级第3个第二逻辑门R(3,3)的第二输出端，R(4,6)的第二输入端输入指示队列的第12位的数值，R(4,6)的第一输出端的输出表示指示队列的第11位对应的存储单元是否空闲，R(4,6)的第二输出端 的输出表示指示队列的第12位对应的存储单元是否空闲。
R(4,7)的第一输入端连接第3级第4个第二逻辑门R(3,4)的第一输出端，R(4,7)的第二输入端输入指示队列的第14位的数值，R(4,7)的第一输出端的输出表示指示队列的第13位对应的存储单元是否空闲，R(4,7)的第二输出端的输出表示指示队列的第14位对应的存储单元是否空闲。
R(4,8)的第一输入端连接第3级第4个第二逻辑门R(3,4)的第二输出端，R(4,8)的第二输入端输入指示队列的第16位的数值，R(4,8)的第一输出端的输出表示指示队列的第15位对应的存储单元是否空闲，R(4,8)的第二输出端的输出表示指示队列的第16位对应的存储单元是否空闲。
在一些示例性的实施方式中，如图7所示，所述第二逻辑门树包括级联的m级第二逻辑门组，第i级第二逻辑门组包括2i-1个第二逻辑门R(i,j)；其中，1≤i≤m；1≤j≤2i-1；N＝2m，m为大于1的正整数；
任意一个第二逻辑门包括：第一输入端、第二输入端、第一输出端和第二输出端；
第1级第二逻辑门R(1,1)的第一输入端连接第m级第1个第一逻辑门L(m,1)的输出端，R(1,1)的第二输入端连接第m-1级第1个第一逻辑门L(m-1,1)的输出端，R(1,1)的第一输出端连接第2级第1个第二逻辑门R(2,1)的第一输入端，R(1,1)的第二输出端连接第2级第2个第二逻辑门R(2,2)的第一输入端；
第m级第2t-1个第二逻辑门R(m,2t-1)的第一输入端连接第m-1级第t个第二逻辑门R(m-1,t)的第一输出端，R(m,2t-1)的第二输入端输入指示队列的第4t-3个元素的数值，R(m,2t-1)的第一输出端的输出表示指示队列的第4t-3个元素对应的存储单元是否空闲，R(m,2t-1)的第二输出端的输出表示指示队列的第4t-2个元素对应的存储单元是否空闲；1≤t≤2m-2；
第m级第2t个第二逻辑门R(m,2t)的第一输入端连接第m-1级第t个第二逻辑门R(m-1,t)的第二输出端，R(m,2t)的第二输入端输入指示队列的第4t-1个元素的数值，R(m,2t)的第一输出端的输出表示指示队列的第4t-1个元素对应的存储单元是否空闲，R(m,2t)的第二输出端的输出表示指示队列的第 4t个元素对应的存储单元是否空闲；1≤t≤2m-2；
当m大于2时，第k级第2t-1个第二逻辑门R(k,2t-1)的第一输入端连接第k-1级第t个第二逻辑门R(k-1,t)的第一输出端，R(k,2t-1)的第二输入端连接第m-k级第4t-3个第一逻辑门L(m-k,4t-3)的输出端，R(k,2t-1)的第一输出端连接第k+1级第4t-3个第二逻辑门R(k+1,4t-3)的第一输入端，R(k,2t-1)的第二输出端连接第k+1级第4t-2个第二逻辑门R(k+1,4t-2)的第一输入端；其中，2≤k≤m-1；1≤t≤2k-2；
当m大于2时，第k级第2t个第二逻辑门R(k,2t)的第一输入端连接第k-1级第t个第二逻辑门R(k-1,t)的第二输出端，R(k,2t)的第二输入端连接第m-k级第4t-1个第一逻辑门L(m-k,4t)的输出端，R(k,2t)的第一输出端连接第k+1级第4t-1个第二逻辑门R(k+1,4t-1)的第一输入端，R(k,2t)的第二输出端连接第k+1级第4t个第二逻辑门R(k+1,4t)的第一输入端；其中，2≤k≤m-1；1≤t≤2k-2。
在一些示例性的实施方式中，所述第二逻辑门的处理逻辑为：当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第一输出端的输出y1为真且第二输出端的输出y2为假，当第二输入端的输入x2为假，则第二输出端的输出y2为真且第一输出端的输出y1为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。
下述表3是第二逻辑门的一种真值表。
表3
在上述表3中，“*”表示“真”和“假”均可。
如图8所示，假设指示队列包括16个元素，每个元素是1比特二进制数 (0或者1)，N＝16＝24；第二逻辑门组包括4级级联的第二逻辑门R(i,j)组，1≤i≤4,1≤j≤2i-1。
第1级第二逻辑门组包括1个第二逻辑门R(1,1)。R(1,1)的第一输入端连接第4级第1个第一逻辑门L(4,1)的输出端，R(1,1)的第二输入端连接第3级第1个第一逻辑门L(3,1)的输出端，R(1,1)的第一输出端连接第2级第1个第二逻辑门R(2,1)的第一输入端，R(1,1)的第二输出端连接第2级第2个第二逻辑门R(2,2)的第一输入端。
第2级第二逻辑门组包括2个第二逻辑门，分别是：R(2,1)和R(2,2)。
R(2,1)的第一输入端连接第1级第1个第二逻辑门R(1,1)的第一输出端，R(2,1)的第二输入端连接第2级第1个第一逻辑门L(2,1)的输出端，R(2,1)的第一输出端连接第3级第1个第二逻辑门R(3,1)的第一输入端，R(2,1)的第二输出端连接第3级第2个第二逻辑门R(3,2)的第一输入端。
R(2,2)的第一输入端连接第1级第1个第二逻辑门R(1,1)的第二输出端，R(2,2)的第二输入端连接第2级第3个第一逻辑门L(2,3)的输出端，R(2,2)的第一输出端连接第3级第3个第二逻辑门R(3,3)的第一输入端，R(2,2)的第二输出端连接第3级第4个第二逻辑门R(3,4)的第一输入端。
第3级第二逻辑门组包括4个第二逻辑门，分别是：R(3,1)、R(3,2)、R(3,3)和R(3,4)。
R(3,1)的第一输入端连接第2级第1个第二逻辑门R(2,1)的第一输出端，R(3,1)的第二输入端连接第1级第1个第一逻辑门L(1,1)的输出端，R(3,1)的第一输出端连接第4级第1个第二逻辑门R(4,1)的第一输入端，R(3,1)的第二输出端连接第4级第2个第二逻辑门R(4,2)的第一输入端。
R(3,2)的第一输入端连接第2级第1个第二逻辑门R(2,1)的第二输出端，R(3,2)的第二输入端连接第1级第3个第一逻辑门L(1,3)的输出端，R(3,2)的第一输出端连接第4级第3个第二逻辑门R(4,3)的第一输入端，R(3,2)的第二输出端连接第4级第4个第二逻辑门R(4,4)的第一输入端。
R(3,3)的第一输入端连接第2级第2个第二逻辑门R(2,2)的第一输出端，R(3,3)的第二输入端连接第1级第5个第一逻辑门L(1,5)的输出端，R(3,3)的 第一输出端连接第4级第5个第二逻辑门R(4,5)的第一输入端，R(3,3)的第二输出端连接第4级第6个第二逻辑门R(4,6)的第一输入端。
R(3,4)的第一输入端连接第2级第2个第二逻辑门R(2,2)的第二输出端，R(3,4)的第二输入端连接第1级第7个第一逻辑门L(1,7)的输出端，R(3,4)的第一输出端连接第4级第7个第二逻辑门R(4,7)的第一输入端，R(3,4)的第二输出端连接第4级第8个第二逻辑门R(4,8)的第一输入端。
第4级第二逻辑门组包括8个第二逻辑门，分别是：R(4,1)、R(4,2)、R(4,3)、R(4,4)、R(4,5)、R(4,6)、R(4,7)、R(4,8)。
R(4,1)的第一输入端连接第3级第1个第二逻辑门R(3,1)的第一输出端，R(4,1)的第二输入端输入指示队列的第1位的数值，R(4,1)的第一输出端的输出表示指示队列的第1位对应的存储单元是否空闲，R(4,1)的第二输出端的输出表示指示队列的第2位对应的存储单元是否空闲。
R(4,2)的第一输入端连接第3级第1个第二逻辑门R(3,1)的第二输出端，R(4,2)的第二输入端输入指示队列的第3位的数值，R(4,2)的第一输出端的输出表示指示队列的第3位对应的存储单元是否空闲，R(4,2)的第二输出端的输出表示指示队列的第4位对应的存储单元是否空闲。
R(4,3)的第一输入端连接第3级第2个第二逻辑门R(3,2)的第一输出端，R(4,3)的第二输入端输入指示队列的第5位的数值，R(4,3)的第一输出端的输出表示指示队列的第5位对应的存储单元是否空闲，R(4,3)的第二输出端的输出表示指示队列的第6位对应的存储单元是否空闲。
R(4,4)的第一输入端连接第3级第2个第二逻辑门R(3,1)的第二输出端，R(4,4)的第二输入端输入指示队列的第7位的数值，R(4,4)的第一输出端的输出表示指示队列的第7位对应的存储单元是否空闲，R(4,4)的第二输出端的输出表示指示队列的第8位对应的存储单元是否空闲。
R(4,5)的第一输入端连接第3级第3个第二逻辑门R(3,3)的第一输出端，R(4,5)的第二输入端输入指示队列的第9位的数值，R(4,5)的第一输出端的输出表示指示队列的第9位对应的存储单元是否空闲，R(4,5)的第二输出端的输出表示指示队列的第10位对应的存储单元是否空闲。
R(4,6)的第一输入端连接第3级第3个第二逻辑门R(3,3)的第二输出端，R(4,6)的第二输入端输入指示队列的第11位的数值，R(4,6)的第一输出端的输出表示指示队列的第11位对应的存储单元是否空闲，R(4,6)的第二输出端的输出表示指示队列的第12位对应的存储单元是否空闲。
R(4,7)的第一输入端连接第3级第4个第二逻辑门R(3,4)的第一输出端，R(4,7)的第二输入端输入指示队列的第13位的数值，R(4,7)的第一输出端的输出表示指示队列的第13位对应的存储单元是否空闲，R(4,7)的第二输出端的输出表示指示队列的第14位对应的存储单元是否空闲。
R(4,8)的第一输入端连接第3级第4个第二逻辑门R(3,4)的第二输出端，R(4,8)的第二输入端输入指示队列的第15位的数值，R(4,8)的第一输出端的输出表示指示队列的第15位对应的存储单元是否空闲，R(4,8)的第二输出端的输出表示指示队列的第16位对应的存储单元是否空闲。
在一些示例性的实施方式中，所述第二逻辑门包括：第一与门、第二与门、第一反向器、第一输入端、第二输入端、第一输出端和第二输出端；
第一与门和第二与门均包括两个输入端和一个输出端；第一反向器包括一个输入端和一个输出端；
所述第一与门和第二与门的一个输入端均连接所述第二逻辑门的第一输入端，所述第一与门的另一个输入端与所述第二逻辑门的第二输入端连接，所述第二与门的另一个输入端与第一反向器的输出端连接，所述第一反向器的输入端与所述第二逻辑门的第二输入端连接；所述第一与门的输出端与所述第二逻辑门的第一输出端连接，所述第二与门的输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，所述第二逻辑门包括：第一或门、第二或门、第二反向器、第一输入端、第二输入端、第一输出端和第二输出端；
第一或门和第二或门均包括两个输入端和一个输出端；第二反向器包括一个输入端和一个输出端；
所述第一或门和第二或门的一个输入端均连接所述第二逻辑门的第一输入端，所述第一或门的另一个输入端与所述第二逻辑门的第二输入端连接， 所述第二或门的另一个输入端与第二反向器的输出端连接，所述第二反向器的输入端与所述第二逻辑门的第二输入端连接；所述第一或门的输出端与所述第二逻辑门的第一输出端连接，所述第二或门的输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，当所述指示队列中任意一个元素的数值为0表示该元素对应的存储单元被占用，数值为1表示该元素对应的存储单元空闲，则所述第二逻辑门为或门的组合，“0”表示“假”，“1”表示“真”。当所述指示队列中任意一个元素的数值为1表示该元素对应的存储单元被占用，数值为0表示该元素对应的存储单元空闲，则所述第二逻辑门为与门的组合，“1”表示“假”，“0”表示“真”。
在一些示例性的实施方式中，如图9-1所示，所述第二逻辑门包括第一与门R1、第二与门R2和第一反向器D1、第一输入端X1、第二输入端X2、第一输出端Y1和第二输出端Y2；第一与门和第二与门均包括两个输入端和一个输出端；
所述第一与门的一个输入端与所述第二逻辑门的第一输入端连接，另一个输入端与第一反向器的输出端连接，所述第一反向器的输入端与所述第二逻辑门的第二输入端连接；所述第一与门的输出端与所述第二逻辑门的第一输出端连接；
所述第二与门的两个输入端分别与所述第二逻辑门的第一输入端和第二输入端连接，一个输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，图9-1所示的第二逻辑门的处理逻辑为：当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第二输出端的输出y2为真且第一输出端的输出y1为假，当第二输入端的输入x2为假，则第一输出端的输出y1为真且第二输出端的输出y2为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。所述指示队列中任意一个元素的数值为0表示该元素对应的存储单元被占用，数值为1表示该元素对应的存储单元空闲，在逻辑处理过程中“0”表示“假”，“1”表示“真”。
在一些示例性的实施方式中，如图9-2所示，所述第二逻辑门包括第三 与门R3、第四与门R4和第二反向器D2、第一输入端X1、第二输入端X2、第一输出端Y1和第二输出端Y2；第三与门和第四与门均包括两个输入端和一个输出端；
所述第三与门的两个输入端分别与所述第二逻辑门的第一输入端和第二输入端连接，一个输出端与所述第二逻辑门的第一输出端连接；
所述第四与门的一个输入端与所述第二逻辑门的第一输入端连接，另一个输入端与第二反向器的输出端连接，所述第二反向器的输入端与所述第二逻辑门的第二输入端连接；所述第四与门的输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，图9-2所示的第二逻辑门的处理逻辑为：当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第一输出端的输出y1为真且第二输出端的输出y2为假，当第二输入端的输入x2为假，则第二输出端的输出y2为真且第一输出端的输出y1为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。所述指示队列中任意一个元素的数值为0表示该元素对应的存储单元被占用，数值为1表示该元素对应的存储单元空闲，在逻辑处理过程中“0”表示“假”，“1”表示“真”。
在一些示例性的实施方式中，如图10-1所示，所述第二逻辑门包括第一或门L1、第二或门L2和第三反向器D3、第一输入端X1、第二输入端X2、第一输出端Y1和第二输出端Y2；第一或门和第二或门均包括两个输入端和一个输出端；
所述第一或门的一个输入端与所述第二逻辑门的第一输入端连接，另一个输入端与第一反向器的输出端连接，所述第一反向器的输入端与所述第二逻辑门的第二输入端连接；所述第一或门的输出端与所述第二逻辑门的第一输出端连接；
所述第二或门的两个输入端分别与所述第二逻辑门的第一输入端和第二输入端连接，一个输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，图10-1所示的第二逻辑门的处理逻辑为： 当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第二输出端的输出y2为真且第一输出端的输出y1为假，当第二输入端的输入x2为假，则第一输出端的输出y1为真且第二输出端的输出y2为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。所述指示队列中任意一个元素的数值为1表示该元素对应的存储单元被占用，数值为0表示该元素对应的存储单元空闲，在逻辑处理过程中“1”表示“假”，“0”表示“真”。
在一些示例性的实施方式中，如图10-2所示，所述第二逻辑门包括第三或门L3、第四或门L4和第四反向器D4、第一输入端X1、第二输入端X2、第一输出端Y1和第二输出端Y2；第一或门和第二或门均包括两个输入端和一个输出端；
所述第三或门的两个输入端分别与所述第二逻辑门的第一输入端和第二输入端连接，一个输出端与所述第二逻辑门的第一输出端连接；
所述第四或门的一个输入端与所述第二逻辑门的第一输入端连接，另一个输入端与第四反向器的输出端连接，所述第四反向器的输入端与所述第二逻辑门的第二输入端连接；所述第四或门的输出端与所述第二逻辑门的第二输出端连接。
在一些示例性的实施方式中，图10-2所示的第二逻辑门的处理逻辑为：当第一输入端的输入x1为真时，当第二输入端的输入x2为真，则第一输出端的输出y1为真且第二输出端的输出y2为假，当第二输入端的输入x2为假，则第二输出端的输出y2为真且第一输出端的输出y1为假；当第一输入端的输入x1为假时，第一输出端的输出y1和第二输出端的输出y2均为假。所述指示队列中任意一个元素的数值为1表示该元素对应的存储单元被占用，数值为0表示该元素对应的存储单元空闲，在逻辑处理过程中“1”表示“假”，“0”表示“真”。
本公开实施例提供了一种查找空闲存储的方法。如图11所示，一种查找空闲存储的方法，包括：
步骤S10，为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
步骤S20，在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
本公开实施例提供的查找空闲存储的方法，为存储块构建指示队列以表示所述存储块中存储单元的占用情况；在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。由于二分法可以缩小一半的搜索量，因此上述实施例提供的查找空闲存储的方法能够加快查找空闲存储的速度。
在一些示例性的实施方式中，所述存储块为缓存。
在一些示例性的实施方式中，所述指示队列的元素为1比特二进制数。
在一些示例性的实施方式中，所述指示队列的数值可以保存在寄存器中，寄存器的每位与指示队列的每个元素一一对应。
在一些示例性的实施方式中，所述元素的数值用于指示该元素对应的存储单元是否空闲，包括：0表示该元素对应的存储单元被占用(不空闲)，1表示该元素对应的存储单元为空闲；或者，1表示该元素对应的存储单元被占用(不空闲)，0表示该元素对应的存储单元为空闲。
在一些示例性的实施方式中，所述通过第一逻辑门树获取所述存储块的指示队列的信息，包括：
通过第1级第一逻辑门组获取以下信息：指示队列的每个第1级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第1级子队列共2m-1个；
当m大于2时，所述第一逻辑门树的第k级第一逻辑门组用于获取以下信息：指示队列的每个第k级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第k级子队列共2m-k个；2≤k≤m-1；
通过第m级第一逻辑门组获取以下信息：指示队列的所有元素中是否存在指示空闲存储单元的元素；
其中，所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N为存储块包含的存储单元的总数，N＝2m；m为大于1的正整数。
在一些示例性的实施方式中，所述利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，包括：
向所述第二逻辑门树的第1级第二逻辑门输入第m级第一逻辑门的输出以及第m-1级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；
当m大于2时，向所述第二逻辑门树的第k级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入第m-k级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；2≤k≤m-1；
向所述第二逻辑门树的第m级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入指示队列的一个元素的数值，两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
其中，所述第二逻辑门的处理逻辑为：当第一输入端的输入为真时，两个输出端中有且仅有一个的输出为真，第二输入端的输入用于确定哪一个输出端的输出为真；当第一输入端的输入为假时，两个输出端的输出均为假。
在一些示例性的实施方式中，所述方法还包括：将所述目标数据写入所述目标空闲存储单元中后，通过第二逻辑门树更新所述目标空闲存储单元对应的指示队列：将所述指示队列中所述目标空闲存储单元对应的目标元素的数值修改为指示所述存储单元被占用。
在一些示例性的实施方式中，所述方法还包括：从目标存储单元中读出数据后，通过第二逻辑门树更新所述目标存储单元对应的指示队列：将所述指示队列中所述目标存储单元对应的目标元素的数值修改为指示所述存储单元为空闲。
在一些示例性的实施方式中，如图12-1所示，按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，包括：
步骤a：设i＝1，将整个指示队列作为第1轮原始位序列H(1)；
其中，所述指示队列包括N个元素，每个元素是1比特二进制数(0或者1)；也即，所述指示队列为N比特的位序列，N＝2m；m为正整数；
步骤b：将第i轮原始位序列H(i)对半分，生成包含低x(i)/2个位的第i轮第一子序列H1(i)和包含高x(i)/2个位的第i轮第二子序列H2(i)；
其中，x(i)是第i轮原始位序列H(i)的原始位数；
步骤c：对第i轮第二子序列H2(i)的所有位进行第一逻辑操作；
步骤d：根据第一逻辑操作的结果确定第i轮第二子序列H2(i)中是否存在指示存储单元空闲的位，是则执行步骤e，否则执行步骤f；
步骤e：将i增加1，将第i-1轮第二子序列H2(i-1)作为第i轮原始位序列H(i)，转至步骤g；
步骤f：将i增加1，将第i-1轮第一子序列H1(i-1)作为第i轮原始位序列H(i)，转至步骤g；
步骤g：判断i是否大于或等于m，是则转至步骤h，否则转至步骤b；
其中，第m轮原始位序列H(m)的原始位数x(m)＝2；
步骤h：判断第m轮原始位序列H(m)的高位的数值是否指示对应的存储单元空闲，是则执行步骤i，否则执行步骤j；
步骤i：将第m轮原始位序列H(m)的高位作为目标位(目标元素)，结束；
其中，目标元素指示的存储单元为空闲存储单元；
步骤j：将第m轮原始位序列H(m)的低位作为目标位(目标元素)，结束；
其中，目标元素指示的存储单元为空闲存储单元；
其中，当所述指示队列中任意一位的数值为0表示该位对应的存储单元被占用，数值为1表示该位对应的存储单元空闲，则所述第一逻辑操作为或操作；当所述指示队列中任意一位的数值为1表示该位对应的存储单元被占用，数值为0表示该位对应的存储单元空闲，则所述第一逻辑操作为与操作。比如，假设位序列为a0a1a2…an，对位序列中的所有位进行或操作，是指：a0 U a1 U a2...U an。当位序列的所有位的数值均为0，则所有位进行或操作的结果为0；当位序列中至少一位的数值为1，则所有位进行或操作的结果为1。比如，假设位序列为a0a1a2…an，对位序列中的所有位进行与操作，是指：a0 I a1 I a2...I an。当位序列的所有位的数值均为1，则所有位进行与操作的结果为1；当位序列中至少一位的数值为0，则所有位进行与操作的结果为0。
在一些示例性的实施方式中，如图12-2所示，按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，包括：
步骤a：设i＝1，将整个指示队列作为第1轮原始位序列H(1)；
其中，所述指示队列包括N个元素，每个元素是1比特二进制数(0或者1)；也即，所述指示队列为N比特的位序列，N＝2m；m为正整数；
步骤b：将第i轮原始位序列H(i)对半分，生成包含低x(i)/2个位的第i轮第一子序列H1(i)和包含高x(i)/2个位的第i轮第二子序列H2(i)；其中，x(i)是第i轮原始位序列H(i)的原始位数；
步骤c：对第i轮第一子序列H1(i)的所有位进行第一逻辑操作；
步骤d：根据第一逻辑操作的结果确定第i轮第一子序列H1(i)中是否存在指示存储单元空闲的位，是则执行步骤e，否则执行步骤f；
步骤e：将i增加1，将第i-1轮第一子序列H1(i-1)作为第i轮原始位序列H(i)，转至步骤g；
步骤f：将i增加1，将第i-1轮第二子序列H2(i-1)作为第i轮原始位序列H(i)，转至步骤g；
步骤g：判断i是否大于或等于m，是则转至步骤h，否则转至步骤b；
其中，第m轮原始位序列H(m)的原始位数x(m)＝2；
步骤h：判断第m轮原始位序列H(m)的低位的数值是否指示对应的存储单元空闲，是则执行步骤i，否则执行步骤j；
步骤i：将第m轮原始位序列H(m)的低位作为目标位(目标元素)，结束；
其中，目标元素指示的存储单元为空闲存储单元；
步骤j：将第m轮原始位序列H(m)的高位作为目标位(目标元素)，结束；
其中，目标元素指示的存储单元为空闲存储单元；
其中，当所述指示队列中任意一位的数值为0表示该位对应的存储单元被占用，数值为1表示该位对应的存储单元空闲，则所述第一逻辑操作为或操作；当所述指示队列中任意一位的数值为1表示该位对应的存储单元被占用，数值为0表示该位对应的存储单元空闲，则所述第一逻辑操作为与操作。
比如，指示队列为8比特的位序列，假设数值为0表示该位对应的存储单元被占用，数值为1表示该位对应的存储单元空闲。当指示队列为“00110101”时，当二分法的搜索算法是最低位对应的存储单元具有最低的搜索优先级，最高位对应的存储单元具有最高的搜索优先级，则指示队列的第6位对应的存储单元将被作为目标空闲存储单元。当指示队列为“00110101”时，当二分法的搜索算法是最高位对应的存储单元具有最低的搜索优先级，最低位对应的存储单元具有最高的搜索优先级，则指示队列的第1位对应的存储单元将被作为目标空闲存储单元。
比如，指示队列为8比特的位序列，假设数值为1表示该位对应的存储单元被占用，数值为0表示该位对应的存储单元空闲。当指示队列为 “00110101”时，当二分法的搜索算法是最低位对应的存储单元具有最低的搜索优先级，最高位对应的存储单元具有最高的搜索优先级，则指示队列的第8位对应的存储单元将被作为目标空闲存储单元。当指示队列为“00110101”时，当二分法的搜索算法是最高位对应的存储单元具有最低的搜索优先级，最低位对应的存储单元具有最高的搜索优先级，则指示队列的第2位对应的存储单元将被作为目标空闲存储单元。
本公开实施例提供了一种芯片，包括上述查找空闲存储的装置。
本领域普通技术人员可以理解，上文中所公开的装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
应该注意，上述实施例或实施方式仅仅是示例性的，而不是限制性的。因此，本公开不限于在此具体示出和描述的内容。可以对实施的形式及细节进行多种修改、替换或省略，而不脱离本公开的范围。

Claims (15)

  1. 一种查找空闲存储的装置，包括：
    指示队列处理模块，设置为为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
    信息收集模块，设置为在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；
    仲裁及控制模块，设置为当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
  2. 如权利要求1所述的装置，其中：
    所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N为存储块包含的存储单元的总数，N＝2m；m为大于1的正整数；
    所述第一逻辑门包括：两个输入端和一个输出端；
    所述第一逻辑门树的第1级第一逻辑门的两个输入端分别输入指示队列的两个相邻元素的数值，输出端连接下一级的第一逻辑门的输入端；
    所述第一逻辑门树的第m级第一逻辑门的两个输入端分别连接两个相邻的上一级第一逻辑门的输出端，输出端的输出用于指示所述指示队列对应的存储块中是否存在空闲存储单元；
    当m大于2时，所述第一逻辑门树的第k级第一逻辑门的两个输入端分别连接两个相邻的上一级第一逻辑门的输出端，输出端连接下一级的第一逻辑门的输入端；2≤k≤m-1；
    所述第一逻辑门的处理逻辑为：当两个输入端的输入中至少一个为真时，输出端的输出为真；当两个输入端的输入均为假时，输出端的输出为假。
  3. 如权利要求2所述的装置，其中：
    所述第二逻辑门树包括级联的m级第二逻辑门组，第i级第二逻辑门组包括2i-1个第二逻辑门R(i,j)；其中，1≤i≤m；1≤j≤2i-1；N＝2m，m为大于1的正整数；
    所述第二逻辑门包括：第一输入端、第二输入端和两个输出端；
    所述第二逻辑门树的第1级第二逻辑门的第一输入端连接第m级第一逻辑门的输出端，第二输入端连接第m-1级第一逻辑门的输出端，两个输出端分别连接两个相邻的下一级第二逻辑门的输入端；
    所述第二逻辑门树的第m级第二逻辑门的第一输入端连接上一级第二逻辑门的输出端，第二输入端输入指示队列的一个元素的数值，两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
    当m大于2时，所述第二逻辑门树的第k级第二逻辑门的第一输入端连接上一级第二逻辑门的输出端，第二输入端连接第m-k级第一逻辑门的输出端，两个输出端分别连接两个相邻的下一级第二逻辑门的输入端；
    所述第二逻辑门的处理逻辑为：当第一输入端的输入为真时，两个输出端中有且仅有一个的输出为真，第二输入端的输入用于确定哪一个输出端的输出为真；当第一输入端的输入为假时，两个输出端的输出均为假。
  4. 如权利要求1-3中任一项所述的装置，其中：
    所述第一逻辑门包括：与门或者或门。
  5. 如权利要求1-3中任一项所述的装置，其中：
    所述第二逻辑门包括：第一与门、第二与门、第一反向器、第一输入端、第二输入端、第一输出端和第二输出端；
    第一与门和第二与门均包括两个输入端和一个输出端；第一反向器包括一个输入端和一个输出端；
    所述第一与门和第二与门的一个输入端均连接所述第二逻辑门的第一输入端，所述第一与门的另一个输入端与所述第二逻辑门的第二输入端连接，所述第二与门的另一个输入端与第一反向器的输出端连接，所述第一反向器 的输入端与所述第二逻辑门的第二输入端连接；所述第一与门的输出端与所述第二逻辑门的第一输出端连接，所述第二与门的输出端与所述第二逻辑门的第二输出端连接。
  6. 如权利要求1-3中任一项所述的装置，其中：
    所述第二逻辑门包括：第一或门、第二或门、第二反向器、第一输入端、第二输入端、第一输出端和第二输出端；
    第一或门和第二或门均包括两个输入端和一个输出端；第二反向器包括一个输入端和一个输出端；
    所述第一或门和第二或门的一个输入端均连接所述第二逻辑门的第一输入端，所述第一或门的另一个输入端与所述第二逻辑门的第二输入端连接，所述第二或门的另一个输入端与第二反向器的输出端连接，所述第二反向器的输入端与所述第二逻辑门的第二输入端连接；所述第一或门的输出端与所述第二逻辑门的第一输出端连接，所述第二或门的输出端与所述第二逻辑门的第二输出端连接。
  7. 如权利要求1所述的装置，其中：
    所述仲裁及控制模块，还设置为将所述目标数据写入所述目标空闲存储单元中后，通过第二逻辑门树向指示队列处理模块发送第一控制信号；其中，所述第一控制信号携带所述目标空闲存储单元对应的指示队列中的目标元素的信息；
    所述指示队列处理模块，还设置为接收到第一控制信号，更新所述目标空闲存储单元对应的指示队列：将所述指示队列中所述目标空闲存储单元对应的目标元素的数值修改为指示所述存储单元被占用。
  8. 如权利要求1所述的装置，其中：
    所述仲裁及控制模块，还设置为从目标存储单元中读出数据后，通过第二逻辑门树向指示队列处理模块发送第二控制信号；其中，所述第二控制信号携带所述目标存储单元对应的指示队列中的目标元素的信息；
    所述指示队列处理模块，还设置为接收到第二控制信号，更新所述目标存储单元对应的指示队列：将所述指示队列中所述目标存储单元对应的目标 元素的数值修改为指示所述存储单元为空闲。
  9. 如权利要求1所述的装置，其中：
    所述指示队列的元素为1比特二进制数。
  10. 一种查找空闲存储的方法，包括：
    为存储块构建指示队列以表示所述存储块中存储单元的占用情况；其中，所述指示队列包括多个元素，所述元素的数值用于指示该元素对应的存储单元是否空闲；
    在向所述存储块写入目标数据前，通过第一逻辑门树获取所述存储块的指示队列的信息，根据所述指示队列的信息判断所述存储块中是否存在空闲存储单元；当所述存储块中存在空闲存储单元时，利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，将所述目标元素对应的空闲存储单元作为目标空闲存储单元以写入所述目标数据。
  11. 如权利要求10所述的方法，其中：
    所述通过第一逻辑门树获取所述存储块的指示队列的信息，包括：
    通过第1级第一逻辑门组获取以下信息：指示队列的每个第1级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第1级子队列共2m-1个；
    当m大于2时，所述第一逻辑门树的第k级第一逻辑门组用于获取以下信息：指示队列的每个第k级子队列中是否存在指示空闲存储单元的元素；其中，指示队列的第k级子队列共2m-k个；2≤k≤m-1；
    通过第m级第一逻辑门组获取以下信息：指示队列的所有元素中是否存在指示空闲存储单元的元素；
    其中，所述第一逻辑门树包括级联的m级第一逻辑门组，第i级第一逻辑门组包括2m-i个第一逻辑门L(i,j)；其中，1≤i≤m；1≤j≤2m-i；N为存储块包含的存储单元的总数，N＝2m；m为大于1的正整数。
  12. 如权利要求11所述的方法，其中：
    所述利用第二逻辑门树按照二分法的搜索规则从所述存储块的指示队列中搜索一个指示空闲存储单元的目标元素，包括：
    向所述第二逻辑门树的第1级第二逻辑门输入第m级第一逻辑门的输出以及第m-1级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；
    当m大于2时，向所述第二逻辑门树的第k级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入第m-k级第一逻辑门的输出，两个输出端的输出分别作为两个相邻的下一级第二逻辑门的输入；2≤k≤m-1；
    向所述第二逻辑门树的第m级第二逻辑门的第一输入端输入上一级第二逻辑门的输出，第二输入端输入指示队列的一个元素的数值，两个输出端的输出分别表示指示队列的该元素和该元素的相邻元素对应的存储单元是否为空闲存储单元；
    其中，所述第二逻辑门的处理逻辑为：当第一输入端的输入为真时，两个输出端中有且仅有一个的输出为真，第二输入端的输入用于确定哪一个输出端的输出为真；当第一输入端的输入为假时，两个输出端的输出均为假。
  13. 如权利要求10所述的方法，其中，所述方法还包括：
    将所述目标数据写入所述目标空闲存储单元中后，通过第二逻辑门树更新所述目标空闲存储单元对应的指示队列：将所述指示队列中所述目标空闲存储单元对应的目标元素的数值修改为指示所述存储单元被占用。
  14. 如权利要求10所述的方法，其中，所述方法还包括：
    从目标存储单元中读出数据后，通过第二逻辑门树更新所述目标存储单元对应的指示队列：将所述指示队列中所述目标存储单元对应的目标元素的数值修改为指示所述存储单元为空闲。
  15. 一种芯片，包括权利要求1-9中任一项所述的查找空闲存储的装置。
PCT/CN2023/103331 2022-09-26 2023-06-28 查找空闲存储的装置、方法及芯片 WO2024066561A1 (zh)

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