WO2024066225A1

WO2024066225A1 - Semiconductor structure and manufacturing method for semiconductor structure

Info

Publication number: WO2024066225A1
Application number: PCT/CN2023/081549
Authority: WO
Inventors: 赵永丽; 陆勇; 徐亚超
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-27
Filing date: 2023-03-15
Publication date: 2024-04-04
Also published as: CN117832196A

Abstract

Provided in the present disclosure is a semiconductor structure, the semiconductor structure comprising: a semiconductor substrate having a word line trench (101), a gate dielectric layer (500) provided on the trench wall of the word line trench (101), and a word line structure (200). The word line structure (200) comprises a word line (210) and a dielectric combination layer, the dielectric combination layer comprising a first dielectric layer (220) and a second dielectric layer (230). The first dielectric layer (220) and the second dielectric layer (230) are both provided on the word line (210), the dielectric constant of the second dielectric layer (230) being higher than the dielectric constant of the first dielectric layer (220).

Description

Semiconductor structure and method for preparing semiconductor structure

Related Applications

This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on September 27, 2022, with application number 2022111816215 and public name “Semiconductor Structure and Method for Preparing Semiconductor Structure,” the entire text of which is hereby incorporated by reference.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in computers and other electronic devices. Dynamic random access memory includes a memory cell array for storage and a circuit located outside the memory cell array. Each memory cell usually includes a transistor, a word line, a bit line, and a capacitor. The word line is used to control the opening or closing of the channel in the transistor, and the bit line is used to read the data information stored in the capacitor or write the data information into the capacitor for storage.

With the rapid development of semiconductor storage technology and the actual demand for miniaturization of electronic devices, it is necessary to continuously improve the integration of dynamic random access memory, which in turn requires the continuous reduction of the size of transistors. Dynamic random access memory with buried word line structure has gradually become the mainstream. However, as the size of transistors decreases, the spacing of buried word lines and the isolation structure between transistors are constantly shrinking, and problems such as gate induced drain leakage current and channel leakage of transistors are becoming more and more serious, seriously affecting the access and storage reliability of the device.

Summary of the invention

According to some embodiments of the present disclosure, there is provided a semiconductor structure, including:

A semiconductor substrate, the semiconductor substrate comprising an active area, and a word line trench is provided in the semiconductor substrate;

A gate dielectric layer, wherein the gate dielectric layer is disposed on a groove wall of the word line groove;

A word line structure, the word line structure comprising a word line and a dielectric combination layer; the word line is located in the word line groove, the top surface of the word line is lower than the top of the word line groove; the dielectric combination layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are both arranged on the word line; the first dielectric layer is located on the surface of the gate dielectric layer facing the word line groove, and the second dielectric layer is located on the surface of the first dielectric layer away from the gate dielectric layer the dielectric constant of the second dielectric layer is higher than the dielectric constant of the first dielectric layer.

In some embodiments of the present disclosure, the material of the first dielectric layer includes a low dielectric constant material, and the material of the second dielectric layer includes a high dielectric constant material.

In some embodiments of the present disclosure, the low dielectric constant material includes one or more of silicon dioxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, and fluorocarbon compounds.

In some embodiments of the present disclosure, the high dielectric constant material includes one or more of silicon nitride, silicon oxynitride and metal oxide.

In some embodiments of the present disclosure, the word line structure further includes a low work function layer, wherein the low work function layer is located on the word line, and the work function of the low work function layer is lower than the work function of the word line.

In some embodiments of the present disclosure, the work function of the low work function layer is below 4.5 eV.

In some embodiments of the present disclosure, the material of the low work function layer includes a low work function metal material or a low work function silicon material.

In some embodiments of the present disclosure, the low work function metal material is selected from one or more of silver, aluminum, titanium, zinc and indium.

In some embodiments of the present disclosure, a gap is formed inside the dielectric combination layer, and the low work function layer is disposed in the gap.

In some embodiments of the present disclosure, the top surface of the low work function layer is lower than the top of the word line groove, and the word line structure also includes an insulating barrier layer, which is arranged on a side of the low work function layer away from the word line, and the insulating barrier layer is located in the gap of the dielectric combination layer.

In some embodiments of the present disclosure, the material of the insulating barrier layer includes silicon nitride.

In some embodiments of the present disclosure, the word line includes a first part and a second part located on the first part; the second part has a top surface and two opposite side walls located on both sides of the top surface, the top surface is a plane, the two side walls of the second part are concave, and the width of the second part increases gradually from the top of the second part to the bottom of the second part.

In some embodiments of the present disclosure, the low work function layer is disposed on a top surface of the second portion.

In some embodiments of the present disclosure, the word line structure further includes a blocking layer, which is disposed between the word line and the gate dielectric layer and below the first dielectric layer.

In some embodiments of the present disclosure, the material of the barrier layer includes titanium nitride.

Furthermore, according to some other embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, comprising the following steps:

etching word line trenches in an active region of a semiconductor substrate;

forming a gate dielectric layer on the groove wall of the word line groove;

Filling the word line groove with a word line material, and etching back to remove a portion of the word line material to form a word line whose top surface is lower than the notch of the word line groove;

Filling the word line trench with a first dielectric material, and removing a portion of the first dielectric material in the middle by etching back to form a first dielectric layer;

A second dielectric material is filled in the word line groove, and a portion of the second dielectric material located in the middle is removed by etching back to form a second dielectric layer, wherein the second dielectric layer is located on a surface of the first dielectric layer away from the gate dielectric layer, and the dielectric constant of the second dielectric layer is higher than the dielectric constant of the first dielectric layer.

In some embodiments of the present disclosure, the further step includes: preparing a low work function layer on the sub-line, wherein the work function of the low work function layer is lower than the work function of the word line.

In some embodiments of the present disclosure, the dielectric combination layer includes the first dielectric layer and the second dielectric layer, the dielectric combination layer has a gap inside, the low work function layer is prepared after the step of forming the second dielectric layer, and the low work function layer is prepared in the gap inside the dielectric combination layer.

In some embodiments of the present disclosure, the step of preparing the low work function layer includes: filling the word line trench with a low work function material and etching back to form the low work function layer having a top surface lower than the top of the word line trench.

In some embodiments of the present disclosure, after the step of preparing the low work function layer, the step further includes: preparing an insulating barrier layer in the gap inside the dielectric combination layer.

In some embodiments of the present disclosure, in the step of etching back to remove part of the word line material, the amount of the word line material removed in the middle part is made the same to form a planar top surface, and the amount of the word line material removed is gradually increased along the direction from the top surface to both sides of the word line material to form two concave side walls on both sides of the top surface.

In some embodiments of the present disclosure, before the step of filling the word line material in the word line trench, the method further includes: filling the word line trench with a blocking material;

After the step of etching back to remove part of the word line material, the method further includes etching back to remove part of the barrier material to form a barrier layer.

The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other embodiments can be obtained based on these drawings without creative work. Attached picture of example.

FIG1 is a top view of a semiconductor structure according to an embodiment of the present disclosure;

FIG2 is a schematic cross-sectional view of the semiconductor structure at AA′ in FIG1 ;

FIG3 is an enlarged structural diagram of the word line in FIG2 ;

FIG4 is a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

FIG5 is a schematic diagram showing a structure in which a word line trench is formed in an active region of a semiconductor substrate;

FIG6 is a schematic diagram showing a structure in which a gate dielectric layer is further prepared in the structure of FIG5 ;

FIG. 7 is a schematic diagram showing a structure in which a word line is further prepared in the structure of FIG. 6 ;

FIG8 is a schematic diagram showing a structure in which a first dielectric layer is further prepared in the structure of FIG7 ;

FIG9 is a schematic diagram showing a structure in which a second dielectric layer is further prepared in the structure of FIG8 ;

FIG10 is a schematic diagram showing a structure in which a low work function layer is further prepared in the structure of FIG9 ;

FIG11 is a schematic diagram showing a structure in which an insulating barrier layer is further prepared in the structure of FIG10;

The reference numerals and their meanings are as follows:

100, active area; 101, word line groove; 200, word line structure; 210, word line; 211, first part; 212, second part; 2121, plane; 2122, concave surface; 220, first dielectric layer; 230, second dielectric layer; 240, low work function layer; 250, insulating barrier layer; 260, blocking layer; 300, bit line structure; 310, bit line contact; 400, shallow trench isolation structure; 500, gate dielectric layer; 610, insulating dielectric layer; 620, double gate oxide layer.

Detailed ways

In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and/or" used herein includes any and all combinations of one or more related listed items.

It should be understood that when an element or layer is referred to as being "on,""adjacentto,""connectedto," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Electrical connection is used to indicate that current can be conducted between electrically connected elements, and the specific manner may be that one element directly contacts another element, or that one element is connected to another element through other conductive elements. Conversely, when an element is referred to as being "directly on,""directly adjacent to,""directly connected to," When a first element, component, region, layer or part is "directly coupled to" another element or layer, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said/the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and/or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or groups. When used herein, the term "and/or" includes any and all combinations of the relevant listed items.

An embodiment of the present disclosure provides a semiconductor structure, comprising:

A gate dielectric layer, the gate dielectric layer is arranged on the groove wall of the word line groove;

A word line structure, the word line structure includes a word line and a dielectric combination layer; the word line is located in a word line groove, and the top surface of the word line is lower than the top of the word line groove; the dielectric combination layer includes a first dielectric layer and a second dielectric layer, and the first dielectric layer and the second dielectric layer are both arranged on the word line; the first dielectric layer is located on the surface of the gate dielectric layer facing the word line groove, and the second dielectric layer is located on the surface of the first dielectric layer away from the gate dielectric layer; the dielectric constant of the second dielectric layer is higher than the dielectric constant of the first dielectric layer.

It can be understood that the semiconductor structure also includes a bit line contact electrically connected to the active area. The bit line contact can be arranged above the semiconductor structure and in contact with the top surface of the active area. The bit line contact is used as an electrical contact structure arranged between the bit line and the active area. The gate dielectric layer has a side wall away from the bit line contact and a side side wall away from the bit line contact.

In addition, the semiconductor structure may further include a shallow trench isolation structure, which is disposed on the semiconductor substrate and is used to separate a surface layer of the semiconductor substrate into a plurality of active regions arranged in an array.

The semiconductor structure has a word line structure arranged in a word line groove. The word line structure includes a word line and a dielectric combination layer, wherein the word line, a first dielectric layer and a second dielectric layer are arranged on the word line, and the second dielectric layer is located on a surface of the first dielectric layer away from the gate dielectric layer, and the dielectric constant of the second dielectric layer is higher than the dielectric constant of the first dielectric layer. By further arranging a dielectric combination layer on the word line serving as a gate, the gate induced drain leakage current is reduced while ensuring the carrier migration capability, thereby improving the problem of the gate induced drain leakage current.

To facilitate understanding of the semiconductor structure provided by the present disclosure, the present disclosure provides Figures 1 and 2, wherein Figure 1 shows a top view of the semiconductor structure, and Figure 2 shows a cross-sectional schematic diagram at AA' in Figure 1.

1 , the semiconductor structure includes a semiconductor substrate and a bit line. The semiconductor substrate includes an active region 100 . The bit line is disposed on the semiconductor substrate and extends along a first direction, such as the direction shown in FIG. 1 . The first direction is the y direction.

As shown in FIG. 2 , a wordline groove 101 is provided in a semiconductor substrate. The semiconductor structure further includes a gate dielectric layer 500 and a wordline structure 200. The gate dielectric layer 500 is disposed on the groove wall of the wordline groove 101, and is used to insulate and space the wordline structure 200 from the semiconductor substrate. The wordline structure 200 includes a wordline 210 and a dielectric combination layer, and the dielectric combination layer includes a first dielectric layer 220 and a second dielectric layer 230. The wordline 210, the first dielectric layer 220 and the second dielectric layer 230 are all located in the wordline groove 101, the top surface of the wordline 210 is lower than the top of the wordline groove 101, and the first dielectric layer 220 and the second dielectric layer 230 are disposed on the top surface of the wordline 210. In the wordline groove 101, the first dielectric layer 220 and the second dielectric layer 230 are stacked in sequence along the direction away from the gate dielectric layer 500. The dielectric constant of the second dielectric layer 230 is higher than the dielectric constant of the first dielectric layer 220.

The word line 210 is disposed in the word line groove 101 and extends in a second direction intersecting the first direction. Optionally, the word line 210 extends in a direction perpendicular to the bit line, such as the direction shown in FIG. 1 , in which the word line 210 extends in the x direction.

In some examples of this embodiment, the material of the first dielectric layer 220 includes a low dielectric constant material. The low dielectric constant material is also referred to as a low-k material. The low dielectric constant material refers to a material with a dielectric constant below 3.9. Optionally, the material of the first dielectric layer 220 is a low dielectric constant material.

In some examples of this embodiment, the low dielectric constant material may include one or more of silicon dioxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, and fluorocarbon compounds, so as to be prepared in the word line trench 101 .

In some examples of this embodiment, the material of the second dielectric layer 230 may include a high dielectric constant material. The high dielectric constant material is also referred to as a high-k material. The high dielectric constant material corresponding to the low dielectric constant material may refer to a material having a dielectric constant greater than 3.9, and further, the dielectric constant of the high dielectric constant material is greater than 20.

In some examples of this embodiment, the high dielectric constant material includes one or more of silicon nitride, silicon oxynitride, and metal oxide. Optionally, the high dielectric constant material includes metal oxide, such as one or more of titanium dioxide and hafnium dioxide. Optionally, the material of the second dielectric layer 230 is a high dielectric constant material.

By sequentially arranging the first dielectric layer 220 and the second dielectric layer 230 in the word line trench 101 in a direction away from the gate dielectric layer 500, the first dielectric layer 220 and the second dielectric layer 230 cooperate with each other, and the deposition of the second dielectric layer with a high dielectric constant can effectively block the depletion layer in the gate-drain overlap region, and improve the gate induced drain leakage current. However, filling only with high dielectric constant materials will inhibit the migration of carriers and reduce the device read and write performance. By filling the first dielectric layer with a low dielectric constant to form a dielectric combination layer, the gate induced drain leakage current can be improved while ensuring the carrier migration capability.

In some examples of this embodiment, there are two dielectric combination layers, the inner sides of the two dielectric combination layers have a gap, and the two dielectric combination layers are respectively arranged close to the two side walls of the gate dielectric layer 500. That is, there are two first dielectric layers 220 and two second dielectric layers 230. In each dielectric combination layer, the second dielectric layer 230 is arranged on a side of the first dielectric layer 220 away from the gate dielectric layer 500.

2 , the gate dielectric layer 500 has two sidewalls located on the left and right sides. The first dielectric layer 220 near the left sidewall and the second dielectric layer 230 near the left sidewall are sequentially stacked in a direction away from the gate dielectric layer 500, and the first dielectric layer 220 near the right sidewall and the second dielectric layer 230 near the right sidewall are also sequentially stacked in a direction away from the sidewall of the gate dielectric layer 500. By arranging two dielectric combination layers respectively near the two sidewalls of the gate dielectric layer 500, the improvement effect on the gate induced drain leakage current can be further optimized.

2 , in some examples of this embodiment, the word line structure 200 further includes a low work function layer 240 . The work function of the low work function layer 240 is lower than that of the word line 210 , and the low work function layer 240 is disposed on the word line 210 .

Optionally, the material of the word line 210 includes tungsten or doped silicon material. The doped polysilicon can be selected from P-type doped polysilicon.

In some examples of this embodiment, the work function of the low work function layer 240 is below 4.5 eV. Optionally, the material of the low work function layer 240 includes a low work function metal material or a low work function silicon material, wherein the low work function metal material is selected from a metal material having a work function below 4.5 eV, and the low work function silicon material is selected from a silicon material having a work function below 4.5 eV. For example, the low work function metal material may include one or more of silver, aluminum, titanium, zinc, and indium. The low work function silicon material may be selected from N-type doped polysilicon.

By backfilling and disposing a low work function layer 240 on the word line 210 , the problem of gate induced drain leakage current can be further improved.

2 , in some examples of this embodiment, there are two dielectric combination layers, and the two dielectric combination layers are opposite to each other with a gap therebetween, and the low work function layer 240 is disposed in the gap between the two opposite second dielectric layers 230 .

In some examples of this embodiment, the top surface of the low work function layer 240 is lower than the top of the word line trench 101, and the word line structure 200 further includes an insulating barrier layer 250, which is disposed on a side of the low work function layer 240 away from the word line 210. The insulating barrier layer 250 is used to enclose the low work function layer 240 in the word line trench 101, and insulate and space the low work function layer 240 from other components subsequently disposed above the word line trench 101.

In some examples of this embodiment, the insulating barrier layer 250 includes silicon nitride.

2 , in some examples of this embodiment, there are two dielectric combination layers, and the two dielectric combination layers are opposite to each other with a gap therebetween, and the insulating barrier layer 250 is also disposed in the gap between the two opposite dielectric combination layers.

Figure 3 shows an enlarged structural schematic diagram of the word line 210 in Figure 2. As shown in Figure 3, in some examples of this embodiment, the word line 210 includes a first portion 211 and a second portion 212 located on the first portion 211, the second portion 212 has a top surface and two opposite side walls located on both sides of the top surface, the top surface is a plane 2121, and the two side walls of the second portion 212 are concave surfaces 2122, and the width of the second portion 212 increases successively from the top of the second portion 212 to the bottom of the second portion 212.

It can be understood that the “concave shape” may be: along the direction from the side wall of the word line 210 toward the middle, the height of the side wall gradually increases, and the height increase amplitude of the side wall also gradually increases, so that the side wall as a whole presents a concave shape toward the middle of the word line 210. In some specific examples of this embodiment, the shape including two side walls and a top surface may also be shaped as a “reverse Ω shape”.

The top surface of a conventional word line 210 is usually flat, and there is also a part of the word line 210 that has a convex top surface. In this embodiment, the side wall of the second portion 212 of the word line 210 is designed to be a concave surface 2122, which can increase the distance between the word line 210 and the bit line contact 310 above the side of the word line 210, reduce the electrical coupling between the word line 210 and the bit line contact 310, and thus increase the short circuit window between the word line 210 and the bit line contact 310.

2 , in some examples of this embodiment, the gap between the two dielectric combination layers exposes at least a portion of the top surface, and correspondingly, the low work function layer 240 may be disposed above the flat portion.

2 , in some examples of this embodiment, the word line structure 200 further includes a barrier layer 260, which is disposed between the word line 210 and the gate dielectric layer 500. The barrier layer 260 is used to block atomic diffusion between the word line 210 and the semiconductor substrate.

In some examples of this embodiment, the material of barrier layer 260 includes titanium nitride.

2 , in some examples of this embodiment, the first dielectric layer 220 is disposed above the barrier layer 260 and a portion of the concave surface 2122 , the second dielectric layer 230 is disposed above the concave surface 2122 , and the entire plane 2121 is exposed between the two dielectric combination layers.

In the embodiment of the semiconductor structure shown in FIG2 , a dielectric combination layer is provided, in which a first dielectric layer 220 and a second dielectric layer 230 are sequentially provided in the dielectric combination layer along a direction away from the gate dielectric layer 500. By providing the dielectric combination layer, it is possible to improve the gate induced drain leakage current while ensuring the carrier migration capability. Furthermore, a low work function layer 240 is further provided between the two dielectric combination layers, which can further reduce the gate induced drain leakage current. Furthermore, the second portion 212 of the word line 210 is designed to be a top surface with a plane 2121 and two side walls with a concave surface 2122, so as to reduce the width of the depletion layer in the gate-drain overlap region and increase the distance from the word line 210 to the bit line contact 310, thereby reducing the trap The probability of tunneling and channel leakage is assisted, and the coupling between the word line 210 and the bit line contact 310 is reduced, thereby making the short circuit window between the word line 210 and the bit line contact 310 larger.

The present disclosure further provides a method for preparing a semiconductor structure, which comprises the following steps:

Etching a word line trench 101 in an active region 100 of a semiconductor substrate;

Forming a gate dielectric layer 500 on the wall of the word line trench 101;

Fill the word line 210 material in the word line trench 101, and etch back to remove part of the word line 210 material to form a word line 210 whose top surface is lower than the notch of the word line trench 101;

Filling the word line trench 101 with a first dielectric material, and removing a portion of the first dielectric material in the middle by etching back to form a first dielectric layer 220;

A second dielectric material is filled in the word line trench 101 , and a portion of the second dielectric material in the middle is removed by etching back to form a second dielectric layer 230 . The second dielectric layer 230 is located on a surface of the first dielectric layer 220 away from the gate dielectric layer 500 , and a dielectric constant of the second dielectric layer 230 is higher than that of the first dielectric layer 220 .

In order to facilitate understanding of the method for preparing the semiconductor structure, FIG. 4 of the present disclosure further provides an implementation of the method for preparing the semiconductor structure. Referring to FIG. 4 , the method includes steps S1 to S7 , which are specifically as follows.

Step S1 , etching a word line trench 101 in an active area 100 of a semiconductor substrate.

In some examples of this embodiment, the step of forming an active area 100 on a semiconductor substrate includes: etching a shallow trench in the surface layer of the semiconductor and filling it with an insulating medium to form a shallow trench isolation structure 400, wherein the shallow trench isolation structure 400 separates the surface layer of the semiconductor substrate into a plurality of active areas 100 arranged in an array.

In some examples of this embodiment, when the word line trench 101 is etched in the active area 100 of the semiconductor substrate, the word line trench 101 simultaneously penetrates the shallow trench isolation structure 400 and the active area 100 in the semiconductor substrate. It can be understood that during preparation, a portion of the word line 210 located in the active area 100 can be used as a gate to control the conduction of the channel in the active area 100.

5 shows a schematic structural diagram of a word line trench 101 formed in an active region 100. In this example, two adjacent word line trenches 101 are disposed in one active region 100. The word line trench 101 has a trench bottom and trench walls on both sides.

In some examples of this embodiment, the semiconductor substrate is a silicon substrate. The word line trench 101 may be formed by etching, such as dry etching or wet etching.

The surface layer of the semiconductor substrate is separated by shallow trench isolation structures 400 to form multiple array-arranged active areas 100 .

Step S2 , forming a gate dielectric layer 500 on the wall of the word line trench 101 .

Figure 6 shows a schematic diagram of a structure in which a gate dielectric layer 500 is further prepared in the structure of Figure 5, wherein the gate dielectric layer 500 covers the entire groove wall of the word line groove 101, and the material of the gate dielectric layer 500 can partially extend to cover the top of the semiconductor structure, and the material of the gate dielectric layer 500 located above the semiconductor structure can be removed in a subsequent preparation process.

In some examples of this embodiment, the gate dielectric layer 500 may be an oxide layer. For example, if the semiconductor substrate is a silicon substrate, the gate dielectric layer 500 may be silicon oxide.

In some examples of this embodiment, the gate dielectric layer 500 is formed by filling silicon oxide in the word line trench 101. In other examples, silicon oxide can be obtained as the gate dielectric layer 500 by directly oxidizing the silicon material on the wall of the word line trench 101.

Step S3 , filling the word line trench 101 with a word line 210 material and preparing the word line 210 .

FIG. 7 shows a schematic diagram of a structure in which a word line 210 is further prepared on the structure of FIG. 6 , wherein the word line 210 is located in the word line trench 101 , and the gate dielectric layer 500 insulates and separates the word line 210 and the active area 100 .

In the process of preparing the word line 210, part of the word line 210 material located at the top of the word line groove 101 is etched back to remove, so that the top surface of the word line 210 material is located below the notch of the word line groove 101, so as to form a word line 210 with a top surface lower than the notch of the word line groove 101.

In some examples of this embodiment, the word line 210 material may include tungsten or doped silicon, wherein the doped silicon may include a P-type doped silicon material.

In some examples of this embodiment, in the step of etching back to remove part of the word line 210 material, the amount of the word line 210 material located in the middle is made the same to form a plane 2121, and the amount of the word line 210 material removed is gradually increased along the direction from the top surface to the two sides of the word line 210 material to form concave surfaces 2122 on both sides of the top surface. By forming two concave sidewalls, it is possible to reduce the width of the depletion layer in the gate-drain overlap region and increase the distance from the word line 210 to the subsequently prepared bit line contact 310, reduce the probability of trap-assisted tunneling and channel leakage, reduce the coupling between the word line 210 and the bit line contact 310, and thus make the short circuit window between the word line 210 and the bit line contact 310 larger.

In some examples of this embodiment, in step S2, a process of preparing a barrier layer 260 is also included. Before the step of filling the word line 210 material in the word line trench 101, the process further includes: filling the barrier material in the word line trench 101, and after the step of etching back to remove part of the word line 210 material, the process further includes: etching back to remove part of the barrier material to form the barrier layer 260.

Optionally, the barrier material used to form the barrier layer 260 may include titanium nitride.

7 , the barrier layer 260 is mainly used to separate the word line 210 and the gate dielectric layer 500 . Therefore, optionally, when a portion of the barrier material is removed by etching back, the height of the formed barrier layer 260 is flush with the side wall height of the word line 210 .

Step S4 , filling the word line trench 101 with a first dielectric material to prepare a first dielectric layer 220 .

FIG. 8 is a schematic diagram showing a structure in which a first dielectric layer 220 is further prepared on the basis of the structure in FIG. 7 .

When preparing the first dielectric layer 220 , a portion of the first dielectric material is removed by etching back to form the first dielectric layer 220 .

In some examples of this embodiment, the step of etching back to remove part of the first dielectric material includes: removing part of the first dielectric material located in the middle to form two first dielectric layers 220 respectively close to the groove walls on both sides of the word line groove 101. In the embodiment, there is a gap between the two first dielectric layers 220 for subsequent preparation of the second dielectric layer 230 .

Optionally, the two first dielectric layers 220 contact two sidewalls of the gate dielectric layer 500 respectively.

In some examples of this embodiment, the first dielectric material is the material of the first dielectric layer 220, and the material of the first dielectric layer 220 includes a low dielectric constant material. Optionally, the low dielectric constant material includes one or more of silicon dioxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, fluorocarbon compounds, etc.

In some examples of this embodiment, the first dielectric layer 220 is located on the barrier layer 260. Optionally, the first dielectric layer 220 may also be located on the barrier layer 260 and a portion of the concave surface 2122.

Step S5 , filling the word line trench 101 with a second dielectric material to prepare a second dielectric layer 230 .

FIG. 9 is a schematic diagram showing a structure in which a second dielectric layer 230 is further prepared on the basis of the structure in FIG. 8 .

When preparing the second dielectric layer 230 , a portion of the second dielectric material is removed by etching back to form the second dielectric layer 230 .

In some examples of this embodiment, the step of etching back to remove part of the second dielectric material includes: removing part of the second dielectric material located in the middle to form two second dielectric layers 230 respectively close to the groove walls on both sides of the word line groove 101. It can be understood that there is a gap between the two second dielectric layers 230 for the subsequent preparation of the low work function layer 240.

Optionally, the two second dielectric layers 230 are stacked on the two first dielectric layers 220 , respectively, and the stacking direction is along a direction away from the corresponding sidewall of the gate dielectric layer 500 .

In some examples of this embodiment, the second dielectric material is the material of the second dielectric layer 230, and the material of the second dielectric layer 230 includes a high dielectric constant material. Optionally, the high dielectric constant material includes one or more of silicon nitride, silicon oxynitride, and metal oxide. Further, the metal oxide can be selected from one or more of titanium dioxide and hafnium dioxide.

It can be understood that in this embodiment, the stacked first dielectric layer 220 and the second dielectric layer 230 together form a dielectric combination layer. The dielectric combination layer can improve the gate induced drain leakage current while ensuring the carrier migration capability.

Step S6 , forming a low work function layer 240 on the word line 210 .

FIG. 10 is a schematic diagram showing a structure in which a low work function layer 240 is further prepared on the basis of the structure in FIG. 9 .

When the low work function layer 240 is formed on the word line 210 , the low work function layer 240 is formed between two second dielectric layers 230 , and the work function of the low work function layer 240 is lower than that of the word line 210 .

In some examples of this embodiment, the step of preparing the low work function layer 240 includes: filling the word line trench 101 with a low work function material and etching back to form the low work function layer 240 with a top surface lower than the notch of the word line trench 101 .

In some examples of this embodiment, the work function of the low work function material is below 4.5 eV. Optionally, the low work function material includes a low work function metal material or a low work function silicon material. Among them, the low work function metal material is selected from metal materials with a work function below 4.5 eV, and the low work function silicon material is selected from silicon materials with a work function below 4.5 eV. For example, the low work function metal material may include one or more of silver, aluminum, titanium, zinc and indium. The low work function silicon material can be selected from N-type doped Polysilicon.

Step S7 , forming an insulating barrier layer 250 on the low work function layer 240 .

FIG. 11 is a schematic diagram showing a structure in which an insulating barrier layer 250 is further prepared on the basis of the structure in FIG. 10 .

The insulating barrier layer 250 is formed in the gap between the two second dielectric layers.

In some examples of this embodiment, the material of the insulating barrier layer 250 includes silicon nitride. The insulating barrier layer 250 may be formed by physical vapor deposition or chemical vapor deposition.

It can be understood that in the process of filling the material of each layer in the word line groove 101, the material of each layer may be deposited on the semiconductor substrate at the same time. Therefore, after preparing the insulating barrier layer 250, a step of removing excess material on the semiconductor substrate may also be included. The method of removing the excess material may include but is not limited to chemical mechanical polishing, dry etching and wet etching. By removing the excess material, the top surface of the prepared word line structure 200 can be made flush with the top surface of the active area 100, which is convenient for the subsequent preparation of other components.

Step S8 , preparing a bit line contact 310 on the semiconductor substrate.

FIG. 2 is a schematic diagram showing a structure in which a bit line contact 310 is further prepared on the basis of the structure in FIG. 11 .

2, the bit line contact 310 is disposed on the active area 100 and is located above and to the side of the word line structure 200. During operation, the bit line contact 310 is electrically connected to the bit line to form a drain, and the word line 210 in the word line structure 200 is used to control the conduction and closing of the channel.

2 , after preparing the insulating barrier layer 250, the method for preparing the semiconductor structure may further include the step of preparing an insulating dielectric layer 610 and a dual-gate oxide layer 620. The insulating dielectric layer 610 and the dual-gate oxide layer 620 are sequentially stacked on the semiconductor substrate.

In some examples of this embodiment, the material of the insulating dielectric layer 610 may include silicon nitride or silicon oxide.

In the structure shown in FIG. 2 , by providing a dielectric combination layer, the gate induced drain leakage current can be improved while ensuring the carrier migration capability. Further providing a low work function layer 240 between two dielectric combination layers can further reduce the gate induced drain leakage current. Designing the second portion 212 of the word line 210 as a top surface of the word line 210 in a plane 2121 and two side walls in a concave surface 2122 can reduce the width of the depletion layer in the gate-drain overlap region and increase the distance from the word line 210 to the bit line contact 310, reduce the probability of trap-assisted tunneling and channel leakage, reduce the coupling between the word line 210 and the bit line contact 310, and thus make the short circuit window between the word line 210 and the bit line contact 310 larger.

Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

It should be understood that, unless otherwise specified herein, there is no strict order restriction for the execution of the steps of, and these steps can be executed in other orders. Moreover, at least a part of the steps of may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be carried out in conjunction with other steps or other stages. At least part of its sub-steps or phases are executed in turn or alternately.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

A semiconductor structure comprising:

A semiconductor substrate, the semiconductor substrate comprising an active area (100), wherein a word line trench (101) is provided in the semiconductor substrate;

A gate dielectric layer (500), the gate dielectric layer (500) being arranged on the groove wall of the word line groove (101);

A word line structure (200), the word line structure (200) comprising a word line (210) and a dielectric combination layer; the word line (210) is located in the word line groove (101), and the top surface of the word line (210) is lower than the top of the word line groove (101); the dielectric combination layer comprises a first dielectric layer (220) and a second dielectric layer (230), and the first dielectric layer (220) and the second dielectric layer (230) are both arranged on the word line (210); the first dielectric layer (220) is located on the surface of the gate dielectric layer (500) facing the word line groove (101), and the second dielectric layer (230) is located on the surface of the first dielectric layer (220) away from the gate dielectric layer (500); the dielectric constant of the second dielectric layer (230) is higher than the dielectric constant of the first dielectric layer (220).
According to the semiconductor structure of claim 1, the material of the first dielectric layer (220) comprises a low dielectric constant material, and the material of the second dielectric layer (230) comprises a high dielectric constant material.
According to the semiconductor structure of claim 2, the low dielectric constant material includes one or more of silicon dioxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, and fluorocarbon compounds.
According to the semiconductor structure of claim 2, the high dielectric constant material comprises one or more of silicon nitride, silicon oxynitride and metal oxide.
According to the semiconductor structure according to any one of claims 1 to 4, the word line structure (200) further comprises a low work function layer (240), wherein the low work function layer (240) is located on the word line (210), and the work function of the low work function layer (240) is lower than the work function of the word line (210).
According to the semiconductor structure of claim 5, the work function of the low work function layer (240) is below 4.5 eV.
According to the semiconductor structure of claim 5, the material of the low work function layer (240) comprises a low work function metal material or a low work function silicon material.
According to the semiconductor structure of claim 7, the low work function metal material is selected from one or more of silver, aluminum, titanium, zinc and indium.
According to the semiconductor structure of claim 5, a gap is provided inside the dielectric combination layer, and the low work function layer (240) is disposed in the gap.
According to the semiconductor structure of claim 9, the top surface of the low work function layer (240) is lower than the top of the word line trench (101), and the word line structure (200) further includes an insulating barrier layer (250), wherein the insulating barrier layer (250) The insulating barrier layer (250) is disposed on a side of the low work function layer (240) away from the word line (210), and the insulating barrier layer (250) is located in the gap of the dielectric combination layer.
According to the semiconductor structure of claim 10, the material of the insulating barrier layer (250) comprises silicon nitride.
According to the semiconductor structure according to any one of claims 5 to 11, the word line (210) comprises a first portion (211) and a second portion (212) located on the first portion (211); the second portion (212) has a top surface and two opposite side walls located on both sides of the top surface, the top surface is a plane, the two side walls of the second portion (212) are concave surfaces, and the width of the second portion (212) increases gradually from the top of the second portion (212) to the bottom of the second portion (212).
According to the semiconductor structure of claim 12, the low work function layer (240) is disposed on a top surface of the second portion (212).
According to the semiconductor structure according to any one of claims 1 to 13, the word line structure (200) further comprises a blocking layer (260), wherein the blocking layer (260) is arranged between the word line (210) and the gate dielectric layer (500) and is located below the first dielectric layer.
According to the semiconductor structure of claim 14, the material of the barrier layer (260) comprises titanium nitride.
A method for preparing a semiconductor structure comprises the following steps:

Etching a word line trench (101) in an active region (100) of a semiconductor substrate;

forming a gate dielectric layer (500) on the wall of the word line trench (101);

Filling the word line groove (101) with a word line material, and etching back to remove a portion of the word line material, to form a word line (210) with a top surface lower than the notch of the word line groove (101);

Filling the word line trench (101) with a first dielectric material, and removing a portion of the first dielectric material in the middle by etching back to form a first dielectric layer (220);

A second dielectric material is filled in the word line trench (101), and a portion of the second dielectric material located in the middle is removed by etching back to form a second dielectric layer (230), wherein the second dielectric layer (230) is located on a surface of the first dielectric layer (220) away from the gate dielectric layer (500), and the dielectric constant of the second dielectric layer (230) is higher than that of the first dielectric layer (220).
The method for preparing a semiconductor structure according to claim 16, further comprising: preparing a low work function layer (240) on the sub-line, the work function of the low work function layer (240) being lower than the work function of the word line (210).
According to the method for preparing a semiconductor structure according to claim 17, the dielectric combination layer comprises the first dielectric layer (220) and the second dielectric layer (230), the inner side of the dielectric combination layer has a gap, the low work function layer (240) is prepared after the step of forming the second dielectric layer (230), and the low work function layer (240) is prepared in the gap inside the dielectric combination layer.
According to the method for preparing a semiconductor structure according to claim 18, the step of preparing the low work function layer (240) comprises: filling the low work function material in the word line trench (101) and etching back to form the low work function layer (240) having a top surface lower than the top of the word line trench (101).
According to the method for preparing a semiconductor structure according to claim 19, after the step of preparing the low work function layer (240), the method further comprises: preparing an insulating barrier layer (250) in the gap inside the dielectric combination layer.
According to the method for preparing a semiconductor structure according to any one of claims 16 to 20, in the step of etching back to remove part of the word line material, the amount of the word line material removed in the middle part is made the same to form a planar top surface, and the amount of the word line material removed is gradually increased along the direction from the top surface to both sides of the word line material to form two concave side walls on both sides of the top surface.
The method for preparing a semiconductor structure according to any one of claims 16 to 21, before the step of filling the word line material in the word line trench (101), further comprises: filling the word line trench (101) with a barrier material;

After the step of etching back to remove part of the word line material, the method further includes etching back to remove part of the blocking material to form a blocking layer (260).