WO2024065678A1 - 一种面板显示方法、装置、系统、设备及存储介质 - Google Patents

一种面板显示方法、装置、系统、设备及存储介质 Download PDF

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Publication number
WO2024065678A1
WO2024065678A1 PCT/CN2022/123275 CN2022123275W WO2024065678A1 WO 2024065678 A1 WO2024065678 A1 WO 2024065678A1 CN 2022123275 W CN2022123275 W CN 2022123275W WO 2024065678 A1 WO2024065678 A1 WO 2024065678A1
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WIPO (PCT)
Prior art keywords
panel
rows
refresh rate
pixels
stream data
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PCT/CN2022/123275
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English (en)
French (fr)
Inventor
魏重光
杨炜帆
刘磊
林金楠
尹晓峰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003407.2A priority Critical patent/CN118120007A/zh
Priority to PCT/CN2022/123275 priority patent/WO2024065678A1/zh
Publication of WO2024065678A1 publication Critical patent/WO2024065678A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technology, and in particular to a panel display method, device, system, equipment and storage medium.
  • the refresh rate of the panel is configured at a high level, the theoretical charging time of a single row of pixels of the panel will often be reduced, which may result in insufficient actual charging time of a single row of pixels, and an inability to fully display the single row of pixel values of the image, thereby reducing the display effect of the panel.
  • the present invention provides a panel display method, device, system, equipment and storage medium to solve the deficiencies in the related art.
  • a panel display method comprising:
  • the refresh rate configuration of the panel is W*N
  • M/N rows of real pixels are determined for the panel, and there are N-1 rows of pixels between the determined adjacent rows of real pixels;
  • the panel includes M rows of pixels, and the resolution of the panel is M*Z; N ⁇ 2;
  • Acquire image stream data having a refresh rate of W*N and containing M/N rows of pixel values; the image resolution in the image stream data is (M/N)*Z;
  • the start time and period of the input latch signal of the panel are adjusted so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • determining that the refresh rate of the panel is configured as W*N includes any of the following:
  • the method further comprises:
  • a single row of mixed pixel values is obtained based on two rows of pixel values displayed in any group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • the step of acquiring image stream data having a refresh rate of W*N and containing M/N rows of pixel values includes:
  • the resolution adjustment unit is used to obtain initial image stream data with a refresh rate of W*N output by the graphics card, adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the image resolution in the initial image stream data is less than or equal to (M/N)*Z.
  • the method further includes:
  • the panel and the resolution adjustment unit are powered off and restarted, the refresh rate configuration of the panel is updated to W*N, and the output of the resolution adjustment unit is updated to image stream data with a refresh rate of W*N and M/N rows of pixel values; the output of the graphics card is updated to image stream data with a refresh rate of W*N.
  • a panel display device comprising:
  • a real module for determining M/N rows of real pixels for the panel when it is determined that the refresh rate configuration of the panel is W*N, and there are N-1 rows of pixels between adjacent real pixel rows; the panel includes M rows of pixels, and the resolution of the panel is M*Z; N ⁇ 2;
  • An acquisition module is used to acquire image stream data having a refresh rate of W*N and containing M/N rows of pixel values; the image resolution in the image stream data is (M/N)*Z;
  • the adjustment module is used to adjust the start time and period of the input latch signal of the panel so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • determining that the refresh rate of the panel is configured as W*N includes any of the following:
  • the adjustment module is further used for:
  • a single row of mixed pixel values is obtained based on two rows of pixel values displayed in any group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • the acquisition module is used to:
  • the resolution adjustment unit is used to obtain initial image stream data with a refresh rate of W*N output by the graphics card, adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the image resolution in the initial image stream data is less than or equal to (M/N)*Z.
  • the real module is further used for:
  • the panel and the resolution adjustment unit are powered off and restarted, the refresh rate configuration of the panel is updated to W*N, and the output of the resolution adjustment unit is updated to image stream data with a refresh rate of W*N and M/N rows of pixel values; the output of the graphics card is updated to image stream data with a refresh rate of W*N.
  • a panel display system comprising: a panel and a resolution adjustment unit;
  • the panel is used to: when it is determined that the refresh rate configuration of the panel is W*N, determine M/N rows of real pixels for the panel, and there are N-1 rows of pixels between the determined adjacent rows of real pixels; the panel includes M rows of pixels, and the resolution of the panel is M*Z; N ⁇ 2;
  • Obtaining image stream data output by a resolution adjustment unit the refresh rate of which is W*N and which contains M/N rows of pixel values; the image resolution in the image stream data is (M/N)*Z;
  • the resolution adjustment unit is used to obtain initial image stream data with a refresh rate of W*N output by the graphics card, adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the resolution adjustment unit is used to, when it is determined that the refresh rate of the panel is configured as W*N, power off and restart the resolution adjustment unit, update the output of the resolution adjustment unit to image stream data with a refresh rate of W*N and containing M/N rows of pixel values; and update the output of the graphics card to image stream data with a refresh rate of W*N;
  • the panel is used to, when it is determined that the refresh rate configuration of the panel is W*N, perform a power-off restart on the panel to update the refresh rate configuration of the panel to W*N.
  • system further comprises: a graphics card
  • the graphics card is used to output initial image stream data with a refresh rate of W*N; the image resolution in the initial image stream data is less than or equal to (M/N)*Z.
  • the theoretical charging time of a single row of pixels on a high refresh rate panel can be increased by adjusting the start time and cycle of the input latch signal, thereby improving the display effect of the panel.
  • FIG1 is a schematic diagram showing a principle of a panel signal timing according to an embodiment of the present invention.
  • FIG2 is a schematic diagram showing another principle of panel signal timing according to an embodiment of the present invention.
  • FIG3 is a schematic diagram showing another principle of panel signal timing according to an embodiment of the present invention.
  • FIG4 is a schematic flow chart of a panel display method according to an embodiment of the present invention.
  • FIG5 is a schematic flow chart of another panel display method according to an embodiment of the present invention.
  • FIG6 is a schematic structural diagram of a panel display device according to an embodiment of the present invention.
  • FIG7 is a schematic structural diagram of a panel display system according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a hardware structure of a computer device configured with a method according to an embodiment of the present invention.
  • the refresh rate of the panel is configured at a high level, the theoretical charging time of a single row of pixels of the panel will often be reduced, which may result in insufficient actual charging time of a single row of pixels, and an inability to fully display the single row of pixel values of the image, thereby reducing the display effect of the panel.
  • an embodiment of the present invention provides a panel display method.
  • the refresh rate of a panel usually represents the number of images that need to be displayed within 1 second, and for one image, the panel usually needs to scan line by line to display it.
  • the theoretical charging time of a single row of pixels on the panel can be calculated based on the number of pixel rows and refresh rate of the panel.
  • the theoretical charging time of a single row of pixels is 1/(W*M) seconds.
  • the single row of pixels can be charged and the single row of pixel values in the corresponding image can be displayed. Specifically, the single row of pixel values in the corresponding image can be sent to the row of pixels in the panel for display.
  • the kth row of pixels in a panel containing M rows may be displayed.
  • a single row of pixels in the panel needs to use three signals to achieve charging and display, namely a clock signal, an input latch signal (TP signal) and a data signal (data signal).
  • TP signal input latch signal
  • data signal data signal
  • a single row of pixels can be charged when the corresponding clock signal cycle is at a high level.
  • the data signal can be turned on to allow a single row of pixel values in the image data to be written for a single row of pixels that is at a high level in the current corresponding clock signal cycle.
  • the clock signal has a period, and two adjacent periods of the same clock signal may correspond to different pixel rows on the panel.
  • 8 clock signals may respectively go through 100 cycles during the process of the panel displaying an image, corresponding to 100 rows of pixels on the panel.
  • the first cycle of the first clock signal may correspond to the first row of pixels on the panel; the first cycle of the second clock signal may correspond to the second row of pixels on the panel; the first cycle of the third clock signal may correspond to the third row of pixels on the panel; ...; the second cycle of the first clock signal may correspond to the ninth row of pixels on the panel; and so on.
  • the input latch signal has a period, and can follow the falling edge generated by the timing, and the turned-on data signal can write the pixel values of a single row in the image data row by row.
  • the turned-on data signal can write the first row of pixel values in the image data.
  • the turned-on data signal can write the second row of pixel values in the image data.
  • image data can be written row by row for pixel rows of the panel through the clock signal and the input latch signal.
  • the theoretical charging time of a single row of pixels in the panel may be from the falling edge of the last input latch signal to the falling edge of the corresponding clock signal cycle during the high level period of the corresponding clock signal cycle.
  • the panel usually controls the theoretical charging time of each row of pixels in the panel to 1 second/(panel refresh rate*number of panel pixel rows) by setting the start time and period of the input latch signal, so that image data can be displayed line by line.
  • FIG. 1 is a schematic diagram showing a principle of a panel signal timing sequence according to an embodiment of the present invention.
  • the panel includes 8 clock signal generators, thereby generating 8 clock signals.
  • the first cycle of clock signal 1 may correspond to pixel row 1 on the panel; the first cycle of clock signal 2 may correspond to pixel row 2 on the panel; the first cycle of clock signal 3 may correspond to pixel row 3 on the panel; ...; the second cycle of clock signal 1 may correspond to pixel row 9 on the panel; and so on.
  • each clock signal is the theoretical charging time of 8 single-row pixels, that is, 8H1.
  • Each cycle includes a high level of 4H1 and a low level of 4H1.
  • H1 1/(W*M) seconds.
  • W is the current refresh rate of the panel
  • M is the total number of pixel rows of the panel.
  • H1 is the theoretical charging time of a single row of pixels in the current panel.
  • the start times of the eight clock signals may differ by an interval of H1, as shown in FIG1 .
  • the first cycle of the corresponding clock signal 2 includes two falling edges of the TP signal. Therefore, for pixel row 2, data row 1 is written first, and then data row 2 is written, overwriting the previously written data row 1, so that data row 2 is finally displayed.
  • the time from the falling edge of the last input latch signal (TP signal) to the falling edge of the clock signal 2 is one H1. Therefore, for pixel row 1, data row 2 can be written, and the theoretical charging time is one H1.
  • H1 1/(W*M) seconds.
  • W is the current refresh rate of the panel
  • M is the total number of pixel rows of the panel.
  • H1 is the theoretical charging time of a single row of pixels in the panel at the refresh rate W.
  • the theoretical charging time of a single row of pixels in the panel is 0.5H1.
  • the theoretical charging time of a single row of pixels in the panel may be during the high level period of the corresponding clock signal cycle, starting from the falling edge of the last input latch signal and ending at the falling edge of the corresponding clock signal cycle.
  • the theoretical charging time of a single row of pixels in the panel can be increased by adjusting the start time and cycle of the input latch signal of the panel.
  • H1 1/(W*M) seconds.
  • W is the current refresh rate W of the panel
  • M is the total number of pixel rows of the panel.
  • H1 is the theoretical charging time of a single row of pixels in the panel at the refresh rate W.
  • the start time and cycle of the input latch signal of the panel can be adjusted so that the theoretical charging time of a single row of pixels in the panel remains H1.
  • FIG. 2 is a schematic diagram showing another principle of panel signal timing according to an embodiment of the present invention.
  • the period of the clock signal becomes the theoretical charging time of 8 single-row pixels, specifically 8H2.
  • the start time and cycle of the input latch signal of the panel may be adjusted.
  • the falling edge of the last input latch signal can be adjusted for the clock signal cycle corresponding to a single pixel row, so that during the high level period, the duration from the falling edge of the input latch signal to the falling edge of the corresponding clock signal cycle is 2H2, that is, H1. This can be specifically shown in Figure 2.
  • the first falling edge of the TP signal can be adjusted to the middle of the high level duration, so that during the high level period, from the falling edge of the input latch signal to the falling edge of the corresponding clock signal cycle, the duration is 2H2, that is, H1.
  • the start time and cycle of the input latch signal on the panel can be adjusted so that the theoretical charging time of a single row of pixels in the panel remains at 2H2, that is, H1.
  • the present method does not improve the timing of the clock signal, when the first falling edge of the TP signal is adjusted to the middle of the high level duration in the first cycle of clock signal 1 corresponding to pixel row 1, it is necessary to ensure that the first falling edge of the TP signal is the last falling edge of the TP signal during the high level period of the first cycle of clock signal 1.
  • the falling edge of the first cycle of clock signal 1 corresponds to 3H2 during the high level period in the first cycle of clock signal 2. Therefore, in order to ensure that the first falling edge of the TP signal is the last TP signal falling edge during the high level period of the first cycle of clock signal 1, the second falling edge of the TP signal needs to be after 3H2 during the high level period in the first cycle of clock signal 2.
  • the first falling edge of the TP signal corresponds to the high level period H2 of the first cycle of the clock signal 2, so the data row 1 can be written first for the pixel row 2.
  • data row 2 will be written later, overwriting the previously written data row 1 with the same charging time.
  • the first falling edge of the TP signal corresponds to 3H2 during the high level period in the first cycle of the clock signal 2. Therefore, the data row 2 can be further written, but the charging time is only H2.
  • a hybrid charging method can be used, specifically including 2H2 duration charging of data row 1 and H2 duration charging of data row 2, and hybrid charging of data row 1 and data row 2.
  • data row 2 cannot completely cover data row 1, so data row 1 and data row 2 can be mixed and displayed by pixel row 2.
  • pixel row 3 For pixel row 3, a method similar to pixel row 1 can be directly used.
  • the second falling edge of the TP signal corresponds to 2H2 during the high level period of the first cycle of clock signal 3, and data row 2 can be completely written.
  • the theoretical charging time of a single row of pixels in the panel can be increased by adjusting the start time and period of the input latch signal, so that the theoretical charging time of a single row of pixels in the panel is not less than the corresponding theoretical charging time H1 of a single row of pixels before the panel refresh rate is increased.
  • some pixel rows in the panel can be directly written with single-row image data, while some pixel rows need to be written with mixed multi-row image data through mixed charging.
  • odd-numbered pixel rows can display a complete single-row image data pixel value, while even-numbered pixel rows can display a mixture of two-row image data pixel values.
  • even-numbered pixel rows may display a complete single-row image data pixel value, while odd-numbered pixel rows may display a mixture of two-row image data pixel values.
  • FIG. 3 is a schematic diagram showing another principle of panel signal timing according to an embodiment of the present invention.
  • Pixel row 3 can display mixed pixel values by mixing and charging data row 1 and data row 2 based on an overlay mechanism.
  • the above method can increase the theoretical charging time of a single row of pixels on the panel after the refresh rate is increased by adjusting the start time and cycle of the input latch signal while increasing the refresh rate of the panel, thereby improving the display effect of the panel.
  • the theoretical charging time of a single row of pixels on the high refresh rate panel can be increased by adjusting the start time and period of the input latch signal, thereby improving the display effect of the panel.
  • FIG. 4 is a schematic flow chart of a panel display method according to an embodiment of the present invention.
  • the execution subject of the method flow is not limited.
  • the execution subject may be a panel, or a control device or a driver of the panel.
  • the method flow may include the following steps.
  • the panel may include M rows of pixels; the resolution of the panel may be M*Z; N ⁇ 2.
  • S102 Obtain image stream data with a refresh rate of W*N and containing M/N rows of pixel values.
  • the image resolution in the image stream data may be (M/N)*Z.
  • S103 Adjust the start time and period of the input latch signal of the panel so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • the method flow can increase the theoretical charging time of a single row of pixels on a panel with a high refresh rate by adjusting the start time and cycle of the input latch signal, thereby improving the display effect of the panel.
  • the panel may include M rows of pixels; the resolution of the panel may be M*Z; N ⁇ 2.
  • N ⁇ 2 and N is an integer, so that double frequency display of the panel can be achieved.
  • the panel may have a refresh rate configuration upper limit, and therefore, W*N may be less than or equal to the refresh rate configuration upper limit of the panel.
  • the panel may include M rows of pixels, and the resolution of the panel may be M*Z.
  • the resolution of the panel may be M*Z, where M represents M rows of pixels of the panel, and Z represents the number of pixels in a single row of pixels in the panel.
  • the resolution of the panel may be 2160*1080.
  • the theoretical charging time of a single row of pixels on the panel can be calculated.
  • determining that the refresh rate configuration of the panel is W*N may include any of the following: determining that the refresh rate configuration of the panel needs to be updated to W*N; determining that the refresh rate configuration of the panel needs to be set to W*N; determining that the refresh rate configuration of the panel needs to be increased from W to W*N.
  • the theoretical charging time of a single row of pixels can be increased by adjusting the start time and period of the panel input latch signal, thereby determining that some pixel rows in the panel can fully display a single row of image data, while some pixel rows can display multiple rows of image data in a mixed manner.
  • M may be an integer multiple of N, so that an integer number of rows of real pixels may be determined for the panel.
  • the method flow is not limited to the way of determining M/N rows of real pixels for the panel, as long as there are N-1 rows of pixels between the determined adjacent rows of real pixels.
  • the corresponding theoretical charging time can be greater than or equal to 1/(W*M) seconds.
  • the first row of pixels in the panel may be determined as real pixels first, and then pixel rows are traversed downward, with every N-1 rows being determined as real pixels.
  • the second row of pixels in the panel may be determined as real pixels, and then the pixel rows are traversed downward, and every N-1 rows are determined as real pixels.
  • S102 Obtain image stream data with a refresh rate of W*N and containing M/N rows of pixel values.
  • the image resolution in the image stream data may be (M/N)*Z.
  • the image stream data may include a plurality of image data, wherein the refresh rate may represent the number of images to be displayed within 1 second.
  • the resolutions of different images in the image stream data may be the same.
  • the panel may adjust its own refresh rate configuration, so as to obtain image stream data with a refresh rate of W*N for display.
  • image stream data containing M/N rows of pixel values can be obtained for display.
  • the image resolution in the image stream data needs to adapt to the panel, so the image resolution in the image stream data is (M/N)*Z.
  • (M/N) represents the total number of rows of pixel values of the image in the image stream data
  • Z represents the number of pixel values in a single row of pixel values of the image in the image stream data, which may be the same as the number of pixels in a single row of pixels in the panel.
  • the method flow does not limit the acquisition source of the image stream data.
  • the panel may acquire image stream data through a configured resolution adjustment unit.
  • obtaining image stream data having a refresh rate of W*N and containing M/N rows of pixel values may include: obtaining image stream data having a refresh rate of W*N and containing M/N rows of pixel values output by a resolution adjustment unit.
  • the resolution adjustment unit may be a Scalar unit.
  • the resolution adjustment unit may be used to adjust the resolution of the image stream data and output the adjusted image stream data to the panel.
  • the resolution adjustment unit may specifically obtain the image stream data from a graphics card, and the graphics card may be used to generate the image stream data for panel display.
  • the resolution adjustment unit may be used to obtain initial image stream data with a refresh rate of W*N output by a graphics card, and adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the amount of image stream data that the graphics card needs to generate per second may be W*M*Z when the refresh rate is W.
  • the resolution adjustment unit may directly send the image stream data generated by the graphics card to the panel for display without adjusting the resolution.
  • the image resolution in the initial image stream data may be less than or equal to (M/N)*Z.
  • the graphics card can generate image stream data with a resolution of (M/N)*Z.
  • the amount of image stream data that the graphics card needs to generate per second can be (W*N)*(M/N)*Z, which is equal to W*M*Z.
  • this embodiment can improve the panel refresh rate without increasing the computing power burden of the graphics card.
  • the resolution adjustment unit may adjust the resolution of the initial image stream data to a resolution that meets the current panel requirements, that is, (M/N)*Z.
  • This embodiment does not limit the specific resolution adjustment method.
  • the method flow is used to increase the theoretical charging time of a single row of pixels. Since the start time and period of the input latch signal of the panel need to be adjusted, and the adjustment strategy and output of the resolution adjustment unit need to be adjusted, the refresh rate of the image stream data output by the graphics card can also be adjusted.
  • the configurations of the panel, the resolution adjustment unit, and the graphics card can be updated by powering off and restarting.
  • the refresh rate configuration of the panel when it is determined that the refresh rate configuration of the panel is W*N, the panel and the resolution adjustment unit can be powered off and restarted, the refresh rate configuration of the panel can be updated to W*N, and the output of the resolution adjustment unit can be updated to an image stream data with a refresh rate of W*N and containing M/N rows of pixel values.
  • the output of the graphics card can be updated to image stream data with a refresh rate of W*N.
  • This embodiment does not limit the execution subject of the update configuration.
  • it can be a panel or a control device of the panel, and specifically, it can be a resolution adjustment unit configured for the panel.
  • This embodiment does not limit the execution subject of controlling the power-off restart.
  • it can be a panel or a control device of the panel, and specifically, it can be a resolution adjustment unit configured for the panel.
  • S103 Adjust the start time and period of the input latch signal of the panel so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • the process of this method does not limit the adjustment method of the input latch signal, as long as the determined M/N rows of real pixels can display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • the start time of the TP signal may be adjusted to 2H2 during the high level period of the first cycle of the clock signal 1, and the cycle of the TP signal may be adjusted to H1.
  • the period of the TP signal is usually the theoretical charging time of a single row of pixels.
  • the period of the TP signal can be H2.
  • the period of the TP signal can be maintained at H1.
  • the start time and cycle of the input latch signal of the panel can be adjusted so that the determined M/N rows of real pixels display the M/N rows of pixel values in the image stream data row by row.
  • the theoretical charging time of the actual pixel row can be ensured to be greater than or equal to H1, that is, 1/(W*M) seconds.
  • the two rows of pixel values may be mixed by utilizing the two rows of pixel values displayed in adjacent real pixel rows in an incompletely overlapping manner.
  • a single row of mixed pixel values is obtained based on two rows of pixel values displayed in the group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • a single-row mixed pixel value is obtained based on the two rows of pixel values displayed in the group of adjacent real pixel rows, which may specifically include that during the high-level period of the clock signal cycle corresponding to the mixed pixel row, there are at least two TP signal falling edges, and the image data written corresponding to the previous TP signal falling edge can be overwritten by the image data written corresponding to the next TP signal falling edge, thereby obtaining an overwriting result.
  • the image data written corresponding to the last falling edge of the TP signal cannot completely cover the image data written corresponding to the previous falling edge of the TP signal. Therefore, two rows of image data can be mixed, thereby obtaining a single row of mixed pixel values based on the two rows of pixel values displayed in the group of adjacent real pixel rows.
  • the theoretical charging time of a single row of pixels can be determined by the last TP signal falling edge during the high level period of the clock signal cycle corresponding to the single row of pixels.
  • the mixed pixel row does not write a single row of image data, but writes multiple rows of image data, which are mixed using an overlay mechanism. Therefore, the theoretical charging time of a single row of pixels in the mixed pixel row can be determined without using the above-mentioned method.
  • the high level period of the clock signal cycle corresponding to a single row of pixels can start from the first TP signal falling edge and end at the falling edge of the clock signal cycle.
  • the theoretical charging time of a single row of pixels in the mixed pixel row may be greater than or equal to 1/(W*M) seconds.
  • the theoretical charging time of pixel row 2 in FIG. 2 can be regarded as starting from the first falling edge of the TP signal and ending at the falling edge of the first cycle of the clock signal 2, that is, 3H2.
  • a mixed charging method is used to utilize an overlay mechanism to achieve pixel value mixing of multiple rows of image data, so that the mixed pixel rows can also display image data and improve the image display transition effect between two real pixel rows adjacent to the mixed pixel rows, thereby improving the display effect of the panel.
  • a single row of mixed pixel values can be obtained based on the two rows of pixel values displayed in each group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • the single-row mixed pixel values displayed by different mixed pixel rows may be different.
  • the single-row mixed pixel values displayed may be different.
  • the present method flow does not limit the specific display mode for the mixed pixel row.
  • the same image data as any adjacent real pixel row can be displayed through program control, or part of the pixels of the mixed pixel row can be controlled through program control to display the same image data as any adjacent real pixel row, and the other pixels of the mixed pixel row can be controlled to display the same image data as another adjacent real pixel row.
  • the image data can specifically include pixel values in the image.
  • an embodiment of the present invention provides another embodiment of a panel display method.
  • FIG. 5 is a schematic flow chart of another panel display method according to an embodiment of the present invention.
  • the execution subject of the method flow is not limited.
  • the execution subject may be a panel or a control device of the panel.
  • the panel includes a normal display mode and a double-frequency display mode that can be switched between each other.
  • the method flow may include the following steps.
  • the panel may include M rows of pixels; the resolution of the panel is M*Z.
  • S203 Obtain image stream data with a refresh rate of W*N and containing M/N rows of pixel values.
  • the image resolution in the image stream data may be (M/N)*Z.
  • S204 Adjust the start time and period of the input latch signal of the panel so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • This method embodiment can realize double frequency display to improve the panel refresh rate and display effect of the panel through the normal display mode and double frequency display mode that can be switched between each other on the panel, and can also increase the theoretical charging time of a single row of pixels on the panel after the refresh rate is increased.
  • the embodiment of the present invention also provides a device embodiment.
  • FIG. 6 is a schematic structural diagram of a panel display device according to an embodiment of the present invention.
  • the device to which the apparatus is applied is not limited.
  • the apparatus can be applied to a panel, or to a control device of a panel.
  • the apparatus may include the following modules.
  • the real module 301 is used to determine M/N rows of real pixels for the panel when it is determined that the refresh rate configuration of the panel is W*N, and there are N-1 rows of pixels between the determined adjacent rows of real pixels.
  • the panel may include M rows of pixels, and the resolution of the panel is M*Z; N ⁇ 2.
  • the acquisition module 302 is used to acquire image stream data having a refresh rate of W*N and containing M/N rows of pixel values.
  • the image resolution in the image stream data is (M/N)*Z.
  • the adjustment module 303 is used to adjust the start time and period of the input latch signal of the panel so that the determined M/N rows of real pixels display the M/N rows of pixel values in the acquired image stream data row by row, and the theoretical charging time of a single row of real pixels is greater than or equal to 1/(W*M) seconds.
  • determining that the refresh rate configuration of the panel is W*N includes any of the following: determining that the refresh rate configuration of the panel needs to be updated to W*N; determining that the refresh rate configuration of the panel needs to be set to W*N; determining that the refresh rate configuration of the panel needs to be increased from W to W*N.
  • the adjustment module 303 is further used for:
  • a single row of mixed pixel values is obtained based on two rows of pixel values displayed in any group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • the acquisition module 302 is used to:
  • the resolution adjustment unit is used to obtain initial image stream data with a refresh rate of W*N output by the graphics card, adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the image resolution in the initial image stream data is less than or equal to (M/N)*Z.
  • the real module 301 is further used for:
  • the refresh rate configuration of the panel is W*N
  • the panel and the resolution adjustment unit are powered off and restarted
  • the refresh rate configuration of the panel is updated to W*N
  • the output of the resolution adjustment unit is updated to image stream data with a refresh rate of W*N and M/N rows of pixel values
  • the output of the graphics card is updated to image stream data with a refresh rate of W*N.
  • the embodiment of the present invention also provides a system embodiment.
  • FIG. 7 is a schematic structural diagram of a panel display system according to an embodiment of the present invention.
  • the system may include: a panel 401 and a resolution adjustment unit 402 .
  • the panel 401 is used to: when it is determined that the refresh rate configuration of the panel 401 is W*N, determine M/N rows of real pixels for the panel 401, and there are N-1 rows of pixels between the determined adjacent rows of real pixels.
  • the panel 401 may include M rows of pixels, and the resolution of the panel 401 may be M*Z; N ⁇ 2.
  • the image stream data output by the resolution adjustment unit 402 has a refresh rate of W*N and contains M/N rows of pixel values; the image resolution in the image stream data is (M/N)*Z;
  • the resolution adjustment unit 402 is used to obtain the initial image stream data with a refresh rate of W*N output by the graphics card, and adjust the image resolution in the initial image stream data to (M/N)*Z, and output the adjustment result.
  • the resolution adjustment unit 402 is used to, when it is determined that the refresh rate of the panel 401 is configured to be W*N, power off and restart the resolution adjustment unit 402, and update the output of the resolution adjustment unit 402 to image stream data with a refresh rate of W*N and containing M/N rows of pixel values; and update the output of the graphics card to image stream data with a refresh rate of W*N.
  • the panel 401 can be powered off and restarted to update the refresh rate configuration of the panel 401 to W*N.
  • the resolution adjustment unit 402 may be configured to, when it is determined that the refresh rate needs to be increased to W*N, power off and restart the panel 401 to update the refresh rate configuration of the panel 401 to W*N.
  • the system may further include: a graphics card 403; the graphics card 403 may be used to output initial image stream data with a refresh rate of W*N; and the image resolution in the initial image stream data is less than or equal to (M/N)*Z.
  • panel 401 can be used to: for any mixed pixel row between any group of adjacent real pixel rows in panel 401, obtain a single row of mixed pixel values based on two rows of pixel values displayed in the group of adjacent real pixel rows, so that the targeted mixed pixel row displays the obtained single row of mixed pixel values.
  • An embodiment of the present invention further provides a computer device, which at least includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any one of the above method embodiments is implemented.
  • An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any of the above-mentioned method embodiments.
  • FIG. 8 is a schematic diagram of the hardware structure of a computer device configured with the method of the embodiment of the present invention according to an embodiment of the present invention, and the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050.
  • the processor 1010, the memory 1020, the input/output interface 1030, and the communication interface 1040 are connected to each other in communication within the device through the bus 1050.
  • Processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present invention.
  • a general-purpose CPU Central Processing Unit
  • ASIC application specific integrated circuit
  • the memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc.
  • the memory 1020 may store an operating system and other application programs.
  • the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.
  • the input/output interface 1030 is used to connect the input/output module to realize information input and output.
  • the input/output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions.
  • the input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc.
  • the output device can include a display, a speaker, a vibrator, an indicator light, etc.
  • the communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices.
  • the communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).
  • the bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input/output interface 1030, and the communication interface 1040).
  • the above device only shows the processor 1010, the memory 1020, the input/output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation.
  • the above device may also only include the components necessary for implementing the embodiments of the present invention, and does not necessarily include all the components shown in the figure.
  • An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored.
  • a computer program is stored on which a computer program is stored.
  • An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program implements any of the above method embodiments when executed by a processor.
  • Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information.
  • Information can be computer readable instructions, data structures, program modules or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
  • computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.
  • the embodiment of the present invention can be implemented by means of software plus the necessary general hardware platform. Based on such an understanding, the technical solution of the embodiment of the present invention can be essentially or the part that makes the contribution in the form of a software product, and the computer software product can be stored in a storage medium, such as ROM/RAM, a disk, an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment of the present invention.
  • a storage medium such as ROM/RAM, a disk, an optical disk, etc.
  • a typical implementation device is a computer, which may be in the form of a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, a game console, a tablet computer, a wearable device or a combination of any of these devices.
  • each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
  • the device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the functions of each module can be implemented in the same one or more software and/or hardware when implementing the embodiment of the present invention. It is also possible to select some or all of the modules according to actual needs to achieve the purpose of the embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
  • plurality refers to two or more than two, unless otherwise clearly defined.

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Abstract

本发明公开了一种面板显示方法、装置、系统、设备及存储介质。所述方法包括：在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。

Description

一种面板显示方法、装置、系统、设备及存储介质 技术领域
本发明涉及显示技术领域，尤其涉及一种面板显示方法、装置、系统、设备及存储介质。
背景技术
在面板显示图像数据时，通常希望提高面板的刷新率，提高面板的显示效果。
但是在面板的刷新率配置较高时，面板的单行像素理论充电时长往往会缩减，可能导致单行像素的实际充电时长不足，无法完整显示图像的单行像素值，降低面板的显示效果。
发明内容
本发明提供一种面板显示方法、装置、系统、设备及存储介质，以解决相关技术中的不足。
根据本发明实施例的第一方面，提供一种面板显示方法，包括：
在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
可选地，所述确定面板的刷新率配置为W*N，包括以下任一项：
确定面板的刷新率配置需要更新为W*N；
确定面板的刷新率配置需要设置为W*N；
确定面板的刷新率配置需要从W提高到W*N。
可选地，所述方法还包括：
针对所述面板中任一组相邻真实像素行之间的任一混合像素行，基于所述任一组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
可选地，所述获取刷新率为W*N，包含M/N行像素值的图像流数据，包括：
获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；
所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
可选地，所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
可选地，在确定面板的刷新率配置为W*N的情况下，所述方法还包括：
在确定需要将刷新率提高到W*N的情况下，针对所述面板和所述分辨率调整单元进行掉电重启，将所述面板的刷新率配置更新为W*N，将所述分辨率调整单元的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据。
根据本发明实施例的第二方面，提供一种面板显示装置，包括：
真实模块，用于在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
获取模块，用于获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
调整模块，用于调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
可选地，所述确定面板的刷新率配置为W*N，包括以下任一项：
确定面板的刷新率配置需要更新为W*N；
确定面板的刷新率配置需要设置为W*N；
确定面板的刷新率配置需要从W提高到W*N。
可选地，所述调整模块还用于：
针对所述面板中任一组相邻真实像素行之间的任一混合像素行，基于所述任一组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
可选地，所述获取模块用于：
获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；
所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
可选地，所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
可选地，所述真实模块还用于：
在确定需要将刷新率提高到W*N的情况下，针对所述面板和所述分辨率调整单元进行掉电重启，将所述面板的刷新率配置更新为W*N，将所述分辨率调整单元的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据。
根据本发明实施例的第三方面，提供一种面板显示系统，包括：面板和分辨率调整单元；
所述面板用于：在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒；
所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
可选地，所述分辨率调整单元用于，在确定面板的刷新率配置为W*N的情况下，针对所述分辨率调整单元进行掉电重启，将所述分辨率调整单元的输出，更新为刷新率 为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据；
所述面板用于，在确定面板的刷新率配置为W*N的情况下，针对所述面板进行掉电重启，将所述面板的刷新率配置更新为W*N。
可选地，所述系统还包括：显卡；
所述显卡用于输出刷新率为W*N的初始图像流数据；所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
根据上述实施例可知，可以通过调整输入锁存器信号的起始时间和周期，增加高刷新率的面板单行像素理论充电时长，提高面板的显示效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。
图1是根据本发明实施例示出的一种面板信号时序的原理示意图；
图2是根据本发明实施例示出的另一种面板信号时序的原理示意图；
图3是根据本发明实施例示出的另一种面板信号时序的原理示意图；
图4是根据本发明实施例示出的一种面板显示方法的流程示意图；
图5是根据本发明实施例示出的另一种面板显示方法的流程示意图；
图6是根据本发明实施例示出的一种面板显示装置的结构示意图；
图7是根据本发明实施例示出的一种面板显示系统的结构示意图；
图8是根据本发明实施例示出的一种配置本发明实施例方法的计算机设备硬件结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附 图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本发明相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本发明的一些方面相一致的装置和方法的例子。
在面板显示图像数据时，通常希望提高面板的刷新率，提高面板的显示效果。
但是在面板的刷新率配置较高时，面板的单行像素理论充电时长往往会缩减，可能导致单行像素的实际充电时长不足，无法完整显示图像的单行像素值，降低面板的显示效果。
为了解决上述问题，本发明实施例提供了一种面板显示方法。
首先分析面板中单行像素的理论充电时间。
面板的刷新率通常表征1秒内需要显示的图像数量，而对于一张图像，面板通常需要逐行扫描进行显示。
因此，面板单行像素的理论充电时长，可以根据面板的像素行数和刷新率进行计算。
具体可以是在刷新率W下，包括M行像素的面板中，单行像素的理论充电时长为1/(W*M)秒。
而基于单行像素的理论充电时长，可以针对单行像素进行充电，并展示相应图像中的单行像素值。具体可以将相应图像中的单行像素值发送到面板中的该行像素进行展示。
例如，对于包含M行的面板中的第k行像素，可以展示包含M行像素值的图像中的第k行像素值。
进一步地，面板中单行像素需要利用3个信号实现充电和显示，分别是时钟信号、输入锁存器信号(TP信号)和数据信号(data信号)。
其中，单行像素在对应的时钟信号周期处于高电平时，可以进行充电。
进一步地，在输入锁存器信号下降沿之后的低电平情况下，可以开启数据信号，允许针对当前对应的时钟信号周期处于高电平的单行像素，写入图像数据中的单行像素值。
其中，时钟信号具有周期，同一时钟信号相邻的两个周期可以对应于面板上不同像素行。
例如，针对面板上的800行像素，8个时钟信号可以在面板显示一张图像的过程中，分别通过100个周期，对应于面板上的100行像素。
具体地，第1个时钟信号的第1个周期，可以对应于面板上的第1行像素；第2个时钟信号的第1个周期，可以对应于面板上的第2行像素；第3个时钟信号的第1个周期，可以对应于面板上的第3行像素；...；第1个时钟信号的第2个周期，可以对应于面板上的第9行像素；以此类推。
输入锁存器信号具有周期，可以随着时序产生的下降沿，所开启的数据信号可以逐行写入图像数据中单行像素值。
例如，针对输入锁存器信号的第一个下降沿后的低电平，开启的数据信号可以写入图像数据中的第一行像素值。针对输入锁存器信号的第二个下降沿后的低电平，开启的数据信号可以写入图像数据中的第二行像素值。
综上，在面板中可以通过时钟信号和输入锁存器信号，为面板的像素行逐行写入图像数据。
需要说明的是，在单行像素对应的时钟信号周期高电平期间，可能出现多个输入锁存器信号的下降沿，从而该行像素可能写入图像数据中的多行像素值。
而对于面板中的单行像素，写入的图像数据中的多行像素值，通常会被最后写入的单行像素值覆盖，从而展示最后写入的单行像素值。
因此，面板中单行像素的理论充电时长，可以是在对应的时钟信号周期高电平期间，从最后一个输入锁存器信号的下降沿开始，到对应的时钟信号周期下降沿结束。
面板通常通过设置输入锁存器信号的起始时间和周期，将面板中每行像素的理论充电时长，控制在1秒/(面板刷新率*面板像素行数)，从而可以逐行显示图像数据。
为了便于理解，如图1所示，图1是根据本发明实施例示出的一种面板信号时序的原理示意图。
其中，面板上包括8个时钟信号发生器，从而可以产生8个时钟信号。
时钟信号1的第1个周期，可以对应于面板上的像素行1；时钟信号2的第1个周期，可以对应于面板上的像素行2；时钟信号3的第1个周期，可以对应于面板上的像素行3；...；时钟信号1的第2个周期，可以对应于面板上的像素行9；以此类推。
由于存在8个时钟信号，因此，每个时钟信号的周期为8个单行像素理论充电时长，也就是8H1。每个周期包括4H1的高电平和4H1的低电平。
其中，H1＝1/(W*M)秒。W为面板当前的刷新率W，M为面板的像素总行数。 H1为当前面板中单行像素的理论充电时长。
8个时钟信号之间，起始时间可以相差一个H1，如图1所示。
针对像素行1，在对应的时钟信号1的第一个周期内，从最后一个输入锁存器信号(TP信号)的下降沿开始，到时钟信号1的下降沿之间，时长为一个H1。因此，针对像素行1可以写入数据行1，理论充电时长为一个H1。
针对像素行2，在对应的时钟信号2的第一个周期内，包括2个TP信号的下降沿。因此，针对像素行2先写入数据行1，再写入数据行2，覆盖之前写入的数据行1，从而最终显示数据行2.
从最后一个输入锁存器信号(TP信号)的下降沿开始，到时钟信号2的下降沿之间，时长为一个H1。因此，针对像素行1可以写入数据行2，理论充电时长为一个H1。
以此类推。
进一步地，通过分析发现，在提高面板刷新率时，相应的单行像素理论充电时长会缩短。
例如，H1＝1/(W*M)秒。W为面板当前的刷新率W，M为面板的像素总行数。H1为刷新率W下面板中单行像素的理论充电时长。而当面板提高刷新率为2W的情况下，面板中单行像素的理论充电时长为0.5H1。
换言之，随着面板的刷新率提高，面板中单行像素的理论充电时长会缩短，从而可能导致单行像素的充电时长不足，显示效果较差。
又因为面板中单行像素的理论充电时长，可以是在对应的时钟信号周期高电平期间，从最后一个输入锁存器信号的下降沿开始，到对应的时钟信号周期下降沿结束。
因此，在本方法中，可以通过调整面板的输入锁存器信号的起始时间和周期，从而增加面板中单行像素的理论充电时长。
例如，H1＝1/(W*M)秒。W为面板当前的刷新率W，M为面板的像素总行数。H1为刷新率W下面板中单行像素的理论充电时长。而当面板提高刷新率为2W的情况下，可以通过调整面板的输入锁存器信号的起始时间和周期，使得面板中单行像素的理论充电时长仍然保持H1。
为了便于理解，如图2所示，图2是根据本发明实施例示出的另一种面板信号时序的原理示意图。
其中，面板的刷新率从W提高到2W，因此，常规情况下单行像素的理论充电时长为0.5H1，为了便于描述，可以描述为H2，从而可以确定H2＝0.5H1。
时钟信号的周期也就变为8个单行像素理论充电时长，具体为8H2。
为了使得面板中单行像素的理论充电时长仍然保持H1，可以调整面板的输入锁存器信号的起始时间和周期。
其中，可以针对单个像素行对应的时钟信号周期，调整最后一个输入锁存器信号的下降沿，使得在高电平期间，从输入锁存器信号的下降沿开始，到对应的时钟信号周期下降沿结束，时长为2H2，也就是H1。具体可以如图2所示。
针对像素行1对应的时钟信号1的第一个周期，可以将TP信号的第一个下降沿调整到高电平时长的中间，从而使得在高电平期间，从输入锁存器信号的下降沿开始，到对应的时钟信号周期下降沿结束，时长为2H2，也就是H1。
换言之，可以通过调整面板上的输入锁存器信号的起始时间和周期，使得面板中单行像素的理论充电时长仍然保持2H2，也就是H1。
此外，需要说明的是，由于本方法并不针对时钟信号的时序进行改进，因此，在针对像素行1对应的时钟信号1的第一个周期，将TP信号的第一个下降沿调整到高电平时长的中间的情况下，需要确保TP信号的第一个下降沿是时钟信号1的第一个周期的高电平期间最后一个TP信号下降沿。
而由于时钟信号之间起始时间的距离，时钟信号1的第一个周期下降沿，对应于时钟信号2的第一个周期内高电平期间的3H2处，因此，为了确保TP信号的第一个下降沿是时钟信号1的第一个周期的高电平期间最后一个TP信号下降沿，TP信号的第二个下降沿需要在时钟信号2的第一个周期内高电平期间的3H2之后。
因此，对于时钟信号2的第一个周期对应的像素行2，由于TP信号的起始时间和周期的调整，无法沿用之前图1的方式，使得像素行2只对应于数据行2。
其中，TP信号的第一个下降沿对应于时钟信号2的第一个周期的高电平期间H2处，因此针对像素行2可以先写入数据行1。
按照之前图1的方式，后续会写入数据行2，通过相同的充电时长覆盖之前写入的数据行1。
但是由于图2中TP信号的调整，TP信号的第一个下降沿对应于时钟信号2的 第一个周期内高电平期间的3H2处，因此，可以进一步写入数据行2，但是充电时长只有H2。
换言之，针对像素行2，可以通过混合充电的方式，具体包括数据行1的2H2时长充电，以及数据行2的H2时长充电，混合数据行1和数据行2进行充电。
具体可以是数据行2的数据无法全部覆盖数据行1，从而可以混合数据行1和数据行2，由像素行2进行显示。
而对于像素行3，可以直接沿用类似像素行1的方式，TP信号的第二个下降沿对应于时钟信号3的第一个周期高电平期间的2H2处，也就可以完整地写入数据行2。
因此，在本发明实施例提供的方法中，可以在面板刷新率提高的情况下，通过调整输入锁存器信号的起始时间和周期，可以增加面板中单行像素的理论充电时长，可以使得面板中单行像素的理论充电时长不少于面板刷新率提高之前对应的单行像素理论充电时长H1。
相对应地，面板中的部分像素行可以直接写入单行图像数据，而部分像素行需要通过混合充电的方式，写入混合的多行图像数据。
此外，基于上述图2的分析，可以确定奇数的像素行可以显示完整的单行图像数据像素值，而偶数的像素行可以显示混合的两行图像数据像素值。
可选地，也可以由偶数的像素行可以显示完整的单行图像数据像素值，而奇数的像素行可以显示混合的两行图像数据像素值。
为了便于理解，如图3所示，图3是根据本发明实施例示出的另一种面板信号时序的原理示意图。
具体的解释可以参考上述图2的分析。其中，像素行3可以基于覆盖的机制，通过数据行1和数据行2的混合充电，显示混合像素值。
上述方法可以在提高面板刷新率的情况下，通过调整输入锁存器信号的起始时间和周期，增加刷新率提高后的面板单行像素理论充电时长，提高面板的显示效果。
相对应地，也就可以在面板刷新率配置较高的情况下，通过调整输入锁存器信号的起始时间和周期，增加高刷新率的面板单行像素理论充电时长，提高面板的显示效果。
如图4所示，图4是根据本发明实施例示出的一种面板显示方法的流程示意图。
其中，并不限定该方法流程的执行主体。可选地，执行主体可以是面板，也可以是面板的控制设备或者驱动。
该方法流程可以包括以下步骤。
S101：在确定面板的刷新率配置为W*N的情况下，针对面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素。
其中，可选地，面板可以包括M行像素；面板的分辨率可以为M*Z；N≥2。
S102：获取刷新率为W*N，包含M/N行像素值的图像流数据。
其中，可选地，图像流数据中的图像分辨率可以是(M/N)*Z。
S103：调整面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
本方法流程，可以通过调整输入锁存器信号的起始时间和周期，增加高刷新率的面板单行像素理论充电时长，提高面板的显示效果。
下面针对上述方法流程进行详细解释。
一、S101：在确定面板的刷新率配置为W*N的情况下，针对面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素。
其中，可选地，面板可以包括M行像素；面板的分辨率可以为M*Z；N≥2。
可选地，N≥2且N为整数。从而可以实现面板的倍频显示。
可选地，面板可以存在刷新率配置上限，因此，W*N可以小于或等于面板的刷新率配置上限。
可选地，面板可以包括M行像素，面板的分辨率可以为M*Z。
在一种可选的实施例中，面板的分辨率可以为M*Z，其中M表示面板的M行像素，Z表示面板中单行像素中的像素数量。例如，面板的分辨率可以是2160*1080。
可选地，基于面板的刷新率和像素总行数，可以计算出面板单行像素的理论充电时长。
可选地，确定面板的刷新率配置为W*N，可以包括以下任一项：确定面板的刷新率配置需要更新为W*N；确定面板的刷新率配置需要设置为W*N；确定面板的刷新 率配置需要从W提高到W*N。
相对应于面板的高刷新率配置，基于上述图2的分析，可以通过调整面板输入锁存器信号的起始时间和周期，提高单行像素的理论充电时长，从而确定面板中的部分像素行可以完整显示单行图像数据，而部分像素行可以混合显示多行图像数据。
可选地，M可以是N的整数倍，从而可以针对面板确定整数行真实像素。
本方法流程并不限定针对面板确定M/N行真实像素的方式。只要所确定的相邻真实像素行之间存在N-1行像素即可。
这是为了确保真实像素对应的时钟信号周期的高电平期间，从TP信号的最后一个下降沿开始，到对应的时钟信号周期下降沿结束，对应的理论充电时长可以大于或等于1/(W*M)秒。
可选地，可以先确定面板中的第一行像素为真实像素，进而向下遍历像素行，每隔N-1行就确定为真实像素。
可选地，可以确定面板中的第二行像素为真实像素，进而向下遍历像素行，每隔N-1行就确定为真实像素。
二、S102：获取刷新率为W*N，包含M/N行像素值的图像流数据。
其中，可选地，图像流数据中的图像分辨率可以是(M/N)*Z。
可选地，图像流数据可以包括多个图像数据，其中刷新率可以表征1秒内需要显示的图像数量。图像流数据中不同图像的分辨率可以相同。
可选地，对于面板而言，可以调整自身的刷新率配置，从而可以获取刷新率为W*N的图像流数据进行显示。
其中，由于面板中所确定的M/N行真实像素，可以显示完整的单行图像数据，因此，可以获取包含M/N行像素值的图像流数据进行显示。
可选地，图像流数据中的图像分辨率需要适应面板，因此，图像流数据中的图像分辨率为(M/N)*Z。其中，(M/N)表示图像流数据中图像的像素值总行数，Z表示图像流数据中图像的单行像素值中的像素值数量，具体可以与面板中单行像素中的像素数量相同。
本方法流程并不限定图像流数据的获取来源。
可选地，面板可以通过配置的分辨率调整单元，获取到图像流数据。
可选地，获取刷新率为W*N，包含M/N行像素值的图像流数据，可以包括：获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据。
其中，分辨率调整单元具体可以是Scalar单元。分辨率调整单元可以用于调整图像流数据的分辨率，向面板输出调整后的图像流数据。
可选地，分辨率调整单元具体可以从显卡获取图像流数据，而显卡可以用于生成图像流数据用于面板显示。
可选地，分辨率调整单元可以用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
在一种可选的实施例中，由于显卡需要生成初始图像流数据，在刷新率为W的情况下，显卡每秒需要生成的图像流数据量可以是W*M*Z。分辨率调整单元可以无需调整分辨率，直接将显卡生成的图像流数据发送到面板进行展示。
而在提高刷新率之后，为了不增加显卡生成图像流数据的负担，可选地，初始图像流数据中的图像分辨率可以小于或等于(M/N)*Z。
在刷新率为W*N的情况下，显卡可以生成分辨率为(M/N)*Z的图像流数据，显卡每秒需要生成的图像流数据量可以是(W*N)*(M/N)*Z，也就可以等于W*M*Z。
因此，本实施例可以在不增加显卡算力负担的前提下，提高面板刷新率。
可选地，针对显卡输出的初始图像流数据，可以由分辨率调整单元，将初始图像流数据的分辨率，调整为适应当前面板需求的分辨率，也就是(M/N)*Z。本实施例并不限定具体的分辨率调整方式。
在一种可选的实施例中，在面板的高刷新率配置的情况下，利用本方法流程提高单行像素理论充电时长，由于需要调整面板的输入锁存器信号的起始时间和周期，并且需要调整分辨率调整单元的调整策略和输出情况，还可以调整显卡输出的图像流数据的刷新率等。
因此，可选地，可以通过掉电重启的方式，更新面板、分辨率调整单元以及显卡的配置。
可选地，在确定面板的刷新率配置为W*N的情况下，可以针对面板和分辨率调整单元进行掉电重启，将面板的刷新率配置更新为W*N，将分辨率调整单元的输出， 更新为刷新率为W*N，包含M/N行像素值的图像流数据。
此外，还可以将显卡的输出更新为刷新率为W*N的图像流数据。
本实施例并不限定更新配置的执行主体。可选地，可以是面板，也可以是面板的控制设备，具体可以针对面板配置的分辨率调整单元。
本实施例并不限定控制进行掉电重启的执行主体。可选地，可以是面板，也可以是面板的控制设备，具体可以针对面板配置的分辨率调整单元。
三、S103：调整面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
本方法流程并不限定输入锁存器信号的调整方式，只要能够使得所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒即可。
可选地，以图2为例，可以将TP信号的起始时间调整为时钟信号1的第一个周期高电平期间的2H2处，将TP信号的周期调整为H1。
需要说明的是，在图1的方式中，TP信号的周期通常就是单行像素的理论充电时长。而在刷新率提高一倍的情况下，按照图1的方式，TP信号的周期可以是H2。而经过图2中的调整，可以将TP信号的周期维持在H1。
基于上述图2的分析，可以通过调整面板的输入锁存器信号的起始时间和周期，使得所确定的M/N行真实像素，逐行显示图像流数据中的M/N行像素值。
并且，真实像素行的理论充电时长可以确保大于或等于H1，也就是1/(W*M)秒。
相对应地，针对相邻真实像素行之间的其他面板像素行，可以描述为混合像素行。
可选地，可以通过利用相邻真实像素行中显示的两行像素值，通过不完全覆盖的方式，混合这两行像素值。
可选地，针对面板中任一组相邻真实像素行之间的任一混合像素行，基于该组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
其中，可选地，基于该组相邻真实像素行中显示的两行像素值得到单行混合像素值，具体可以包括，在混合像素行对应的时钟信号周期的高电平期间，存在至少两次TP信号下降沿，前一次TP信号下降沿对应写入的图像数据，可以被后一次TP信号下降沿对应写入的图像数据覆盖，从而得到覆盖结果。
通常最后一次TP信号下降沿对应写入的图像数据，无法全部覆盖之前TP信号下降沿对应写入的图像数据，因此可以实现两行图像数据的混合，从而实现基于该组相邻真实像素行中显示的两行像素值得到单行混合像素值。
具体可以参见图2的分析。
需要说明的是，在刷新率提高之前，由于面板的每行都需要完整写入单行图像数据，因此，单行像素的理论充电时长的确定方式，可以是根据单行像素对应的时钟信号周期的高电平期间，最后一次TP信号下降沿确定的。
而在刷新率提高之后，由于采用了上述方法流程，混合像素行并不是写入单行图像数据，而是写入多行图像数据，利用覆盖机制进行混合，因此，针对混合像素行的单行像素理论充电时长，可以并不采用上述方式确定。
可选地，针对混合像素行，由于需要利用覆盖机制混合多行图像数据，因此，可以根据单行像素对应的时钟信号周期的高电平期间，从第一次TP信号下降沿开始，到该时钟信号周期的下降沿结束。
可选地，由于对于混合像素行，写入的是两行图像数据混合后的像素值，因此，混合像素行的单行像素理论充电时长，可以大于或等于1/(W*M)秒。
例如，图2中像素行2的理论充电时长，可以看作是从第一次TP信号下降沿开始，到时钟信号2第一个周期的下降沿结束，也就可以是3H2。
在本实施例中，通过面板中的真实像素行和混合像素行，针对真实像素行写入单行图像数据，针对混合像素行通过混合充电的方式，利用覆盖机制实现多行图像数据的像素值混合，从而可以使得混合像素行也显示图像数据，并且提高与混合像素行相邻的两个真实像素行之间的图像显示过渡效果，从而提高面板的显示效果。
可选地，可以针对面板中每组相邻真实像素行之间的每个混合像素行，基于每组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
可选地，不同的混合像素行所显示的单行混合像素值可以不同。对于同一组相邻真实像素行之间的不同混合像素行，所显示的单行混合像素值可以不同。
当然，本方法流程并不限定具体的针对混合像素行的显示方式，可选地，可以通过程序控制，与相邻的任一真实像素行显示相同的图像数据，也可以通过程序控制，使得混合像素行的部分像素，与相邻的任一真实像素行显示相同的图像数据，混合像素行的其他像素，与相邻的另一真实像素行显示相同的图像数据。图像数据具体可以包括图像中的像素值。
为了便于理解，本发明实施例提供了另一种面板显示方法的实施例。
如图5所示，图5是根据本发明实施例示出的另一种面板显示方法的流程示意图。
其中，并不限定该方法流程的执行主体。可选地，执行主体可以是面板，也可以是面板的控制设备。
其中，可选地，面板包括能够互相切换的正常显示模式和倍频显示模式。
该方法流程可以包括以下步骤。
S201：在面板处于正常显示模式，且面板的刷新率配置为W的情况下，面板单行像素的理论充电时长为1/(W*M)秒。
可选地，面板可以包括M行像素；面板的分辨率为M*Z。
S202：在从正常显示模式切换到倍频显示模式，并确定需要将面板的刷新率配置提高到W*N的情况下，针对面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素。
其中，可选地，N≥2。
S203：获取刷新率为W*N，包含M/N行像素值的图像流数据。
其中，可选地，图像流数据中的图像分辨率可以是(M/N)*Z。
S204：调整面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
本方法实施例可以通过面板上能够互相切换的正常显示模式和倍频显示模式， 实现倍频显示提高面板刷新率，提高面板的显示效果，并且还可以增加提高刷新率后的面板单行像素理论充电时长。
本方法实施例的具体解释可以参见上述方法流程S101-S103的解释。
对应于上述方法实施例，本发明实施例还提供了一种装置实施例。
如图6所示，图6是根据本发明实施例示出的一种面板显示装置的结构示意图。
其中，并不限定该装置所应用的设备。可选地，该装置可以应用于面板，也可以应用于面板的控制设备。
该装置可以包括以下模块。
真实模块301，用于在确定面板的刷新率配置为W*N的情况下，针对面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素。
可选地，面板可以包括M行像素，且面板的分辨率为M*Z；N≥2。
获取模块302，用于获取刷新率为W*N，包含M/N行像素值的图像流数据。可选地，图像流数据中的图像分辨率为(M/N)*Z。
调整模块303，用于调整面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
可选地，确定面板的刷新率配置为W*N，包括以下任一项：确定面板的刷新率配置需要更新为W*N；确定面板的刷新率配置需要设置为W*N；确定面板的刷新率配置需要从W提高到W*N。
可选地，调整模块303还用于：
针对所述面板中任一组相邻真实像素行之间的任一混合像素行，基于所述任一组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
可选地，所述获取模块302用于：
获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；
所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
可选地，所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
可选地，所述真实模块301还用于：
在确定面板的刷新率配置为W*N的情况下，针对所述面板和所述分辨率调整单元进行掉电重启，将所述面板的刷新率配置更新为W*N，将所述分辨率调整单元的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据。
具体的解释可以参见上述方法实施例。
对应于上述方法实施例，本发明实施例还提供了一种系统实施例。
如图7所示，图7是根据本发明实施例示出的一种面板显示系统的结构示意图。
该系统可以包括：面板401和分辨率调整单元402。
面板401用于：在确定面板401的刷新率配置为W*N的情况下，针对面板401确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素。
可选地，面板401可以包括M行像素，且面板401的分辨率可以为M*Z；N≥2。
获取分辨率调整单元402输出的刷新率为W*N，包含M/N行像素值的图像流数据；图像流数据中的图像分辨率为(M/N)*Z；
调整面板401的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒；
分辨率调整单元402用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
可选地，分辨率调整单元402用于，在确定面板401的刷新率配置为W*N的情况下，针对分辨率调整单元402进行掉电重启，将分辨率调整单元402的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将显卡的输出更新为刷新率为W*N的图像流数据。
可选地，面板401可以用于，在确定需要将刷新率提高到W*N的情况下，针对面板401进行掉电重启，将面板401的刷新率配置更新为W*N。
可选地，分辨率调整单元402可以用于，在确定需要将刷新率提高到W*N的情况下，针对面板401进行掉电重启，将面板401的刷新率配置更新为W*N。
可选地，系统还可以包括：显卡403；显卡403可以用于输出刷新率为W*N的初始图像流数据；初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
可选地，面板401可以用于：针对面板401中任一组相邻真实像素行之间的任一混合像素行，基于该组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
具体的解释可以参见上述方法实施例。
本发明实施例还提供一种计算机设备，其至少包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，处理器执行所述程序时实现上述任一方法实施例。
本发明实施例还提供一种电子设备，包括：至少一个处理器；以及，与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行上述任一方法实施例。
图8是根据本发明实施例示出的一种配置本发明实施例方法的计算机设备硬件结构示意图，该设备可以包括：处理器1010、存储器1020、输入/输出接口1030、通信接口1040和总线1050。其中处理器1010、存储器1020、输入/输出接口1030和通信接口1040通过总线1050实现彼此之间在设备内部的通信连接。
处理器1010可以采用通用的CPU(Central Processing Unit，中央处理器)、微处理器、应用专用集成电路(Application Specific Integrated Circuit，ASIC)、或者一个或多个集成电路等方式实现，用于执行相关程序，以实现本发明实施例所提供的技术方案。
存储器1020可以采用ROM(Read Only Memory，只读存储器)、RAM(Random Access Memory，随机存取存储器)、静态存储设备，动态存储设备等形式实现。存储器1020可以存储操作系统和其他应用程序，在通过软件或者固件来实现本发明实施例所提供的技术方案时，相关的程序代码保存在存储器1020中，并由处理器1010来调用执行。
输入/输出接口1030用于连接输入/输出模块，以实现信息输入及输出。输入输 出/模块可以作为组件配置在设备中(图中未示出)，也可以外接于设备以提供相应功能。其中输入设备可以包括键盘、鼠标、触摸屏、麦克风、各类传感器等，输出设备可以包括显示器、扬声器、振动器、指示灯等。
通信接口1040用于连接通信模块(图中未示出)，以实现本设备与其他设备的通信交互。其中通信模块可以通过有线方式(例如USB、网线等)实现通信，也可以通过无线方式(例如移动网络、WIFI、蓝牙等)实现通信。
总线1050包括一通路，在设备的各个组件(例如处理器1010、存储器1020、输入/输出接口1030和通信接口1040)之间传输信息。
需要说明的是，尽管上述设备仅示出了处理器1010、存储器1020、输入/输出接口1030、通信接口1040以及总线1050，但是在具体实施过程中，该设备还可以包括实现正常运行所必需的其他组件。此外，本领域的技术人员可以理解的是，上述设备中也可以仅包含实现本发明实施例方案所必需的组件，而不必包含图中所示的全部组件。
本发明实施例还提供一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述任一方法实施例。
本发明实施例还提供一种存储有计算机程序的计算机可读存储介质，所述计算机程序在由处理器执行时实现上述任一方法实施例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
通过以上的实施方式的描述可知，本领域的技术人员可以清楚地了解到本发明实施例可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本发明实施例的技术方案本质上或者说做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使 得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明实施例各个实施例或者实施例的某些部分所述的方法。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于装置实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，在实施本发明实施例方案时可以把各模块的功能在同一个或多个软件和/或硬件中实现。也可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
以上所述仅是本发明实施例的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明实施例的保护。
在本发明中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本发明的其它实施方案。本发明旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

Claims (13)

  1. 一种面板显示方法，其特征在于，包括：
    在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
    获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
    调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
  2. 根据权利要求1所述的方法，其特征在于，所述确定面板的刷新率配置为W*N，包括以下任一项：
    确定面板的刷新率配置需要更新为W*N；
    确定面板的刷新率配置需要设置为W*N；
    确定面板的刷新率配置需要从W提高到W*N。
  3. 根据权利要求1所述的方法，其特征在于，还包括：
    针对所述面板中任一组相邻真实像素行之间的任一混合像素行，基于所述任一组相邻真实像素行中显示的两行像素值得到单行混合像素值，以使所针对的混合像素行显示所得到的单行混合像素值。
  4. 根据权利要求1所述的方法，其特征在于，所述获取刷新率为W*N，包含M/N行像素值的图像流数据，包括：
    获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；
    所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
  5. 根据权利要求4所述的方法，其特征在于，所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
  6. 根据权利要求4所述的方法，其特征在于，在确定面板的刷新率配置为W*N的情况下，所述方法还包括：
    针对所述面板和所述分辨率调整单元进行掉电重启，将所述面板的刷新率配置更新为W*N，将所述分辨率调整单元的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据。
  7. 一种面板显示方法，其特征在于，所述面板包括能够互相切换的正常显示模式和倍频显示模式；
    所述方法包括：
    在所述面板处于正常显示模式，且所述面板的刷新率配置为W的情况下，所述面板单行像素的理论充电时长为1/(W*M)秒；所述面板包括M行像素，且所述面板的分辨率为M*Z；
    在从正常显示模式切换到倍频显示模式，并确定需要将所述面板的刷新率配置提高到W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；N≥2；
    获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
    调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
  8. 一种面板显示装置，其特征在于，包括：
    真实模块，用于在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
    获取模块，用于获取刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
    调整模块，用于调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大于或等于1/(W*M)秒。
  9. 一种面板显示系统，其特征在于，包括面板和分辨率调整单元；
    所述面板用于：在确定面板的刷新率配置为W*N的情况下，针对所述面板确定M/N行真实像素，所确定的相邻真实像素行之间存在N-1行像素；所述面板包括M行像素，且所述面板的分辨率为M*Z；N≥2；
    获取分辨率调整单元输出的刷新率为W*N，包含M/N行像素值的图像流数据；所述图像流数据中的图像分辨率为(M/N)*Z；
    调整所述面板的输入锁存器信号的起始时间和周期，以使所确定的M/N行真实像素逐行显示所获取的图像流数据中M/N行像素值，且单行真实像素的理论充电时长大 于或等于1/(W*M)秒；
    所述分辨率调整单元用于，获取显卡输出的刷新率为W*N的初始图像流数据，并将所述初始图像流数据中的图像分辨率调整为(M/N)*Z，输出调整结果。
  10. 根据权利要求9所述的系统，其特征在于，
    所述分辨率调整单元用于，在确定面板的刷新率配置为W*N的情况下，针对所述分辨率调整单元进行掉电重启，将所述分辨率调整单元的输出，更新为刷新率为W*N，包含M/N行像素值的图像流数据；将所述显卡的输出更新为刷新率为W*N的图像流数据；
    所述面板用于，在确定面板的刷新率配置为W*N的情况下，针对所述面板进行掉电重启，将所述面板的刷新率配置更新为W*N。
  11. 根据权利要求9所述的系统，其特征在于，还包括：显卡；
    所述显卡用于输出刷新率为W*N的初始图像流数据；所述初始图像流数据中的图像分辨率小于或等于(M/N)*Z。
  12. 一种电子设备，其特征在于，包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求1至7中任一项所述方法。
  13. 一种存储有计算机程序的计算机可读存储介质，其特征在于，所述计算机程序在由处理器执行时实现权利要求1至7中任一项所述方法。
PCT/CN2022/123275 2022-09-30 2022-09-30 一种面板显示方法、装置、系统、设备及存储介质 WO2024065678A1 (zh)

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