WO2024065310A1

WO2024065310A1 - Nitride-based semiconductor device and method for manufacturing thereof

Info

Publication number: WO2024065310A1
Application number: PCT/CN2022/122257
Authority: WO
Inventors: Yong Ma; Jingsheng GUO; Yao Liang; Hung-Yu Chen
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2024-04-04

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and at least one electrode structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The at least one electrode structure is disposed on the second nitride-based semiconductor layer. The at least one electrode structure includes a doped silicon nitride layer making contact with the second nitride-based semiconductor layer and an electrode disposed on the doped silicon nitride layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

Inventors: Yong MA; Jingsheng GUO; Yao LIANG; Hung-Yu CHEN

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a modified electrode structure with a doped silicon nitride layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and at least one electrode structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The at least one electrode structure is disposed on the second nitride-based semiconductor layer. The at least one electrode structure includes a doped silicon nitride layer making contact with the second nitride-based semiconductor layer and an electrode disposed on the doped silicon nitride layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed on a first nitride-based semiconductor layer. The second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. A dielectric layer is formed to cover the second nitride-based semiconductor layer, in which the dielectric layer has a through hole. A silicon nitride layer is formed to cover the dielectric layer and the second nitride-based semiconductor layer. A doping process is performed on the silicon nitride layer, such that at least a portion of the silicon nitride layer is doped with a group IV element. An electrode is formed on the doped portion of the silicon nitride layer and in the through hole of the dielectric layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, a silicon nitride layer, an implanted region, and an electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The dielectric layer covers the second nitride-based semiconductor layer and has at least one through hole. The silicon nitride layer penetrates the dielectric layer by the through hole of the dielectric layer. The implanted region includes implant dopants extending into at least a portion of the silicon nitride layer located in the through hole, such that the implant dopants form the concentration distribution that has a peak concentration in the portion of the silicon nitride layer. The electrode is disposed on and makes contact with the implanted region.

By the above configuration, in the present disclosure, the semiconductor device has a modified electrode structure with a doped silicon nitride layer; and therefore, the semiconductor device can have good electrical properties.

In one aspect, with respect to the modified electrode structure, a silicon nitride (SiN) layer is formed between an electrode and a barrier layer and is doped with a group IV element having a greater atomic number than silicon, such that a good ohmic contact between the electrode and the barrier layer can be achieved. Thus, the nitride-based semiconductor device can have good performance.

In another aspect, a SiN layer is formed between an electrode and a nitride-based semiconductor layer (e.g., barrier layer) and is doped with a group III element having a smaller atomic number than silicon, for example, boron. Boron and SiN can collectively form an unstable compound Si _xB _yN, which is advantageous to improve thermal activation rate of silicon. Thus, after a thermal annealing process, more silicon elements in the doped SiN layer can diffuse downward to the nitride-based semiconductor layer, such that the nitride-based semiconductor layer (e.g., AlGaN) is doped with silicon above a certain concentration. The increase of silicon concentration in the nitride-based semiconductor layer helps the number of electrons therein increase, such that the contact resistance between the electrode and the nitride-based semiconductor layer can be reduced. Thus, the semiconductor device can have a good performance.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is an enlarged cross-sectional view of an intrinsic silicon nitride layer without performing doping process and a doped SiN layer;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 6A is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 6B is an enlarged vertical cross-sectional view of a region in the FIG. 6A;

FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 9 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 10 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 11 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 12 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 13 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 14 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1A is a vertical view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, a dielectric layer 20A,

electrode structures

32, 34, intrinsic silicon nitride layers 36, 38, a doped nitride-based semiconductor layer 40, a gate electrode 42, and a dielectric layer 50.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer (not shown) is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The dielectric layer 20A is disposed on/over/above the nitride-based semiconductor layer 14. The dielectric layer 20A makes contact with a top surface of the nitride-based semiconductor layer 14. The dielectric layer 20A covers the nitride-based semiconductor layer 14. The dielectric layer 20A includes a plurality of inner side surfaces IS, and two adjacent inner side surfaces IS define a through hole TH. The inner side surfaces IS of the dielectric layer 20A are, for example, perpendicular to a top surface of the nitride-based semiconductor layer 14. The dielectric layer 20A has three through holes TH, such that portions of the nitride-based semiconductor layer 14 are free from coverage of the dielectric layer 20A.

The material of the dielectric layer 20A can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 20A can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 20A can include an oxide. In some embodiments, the dielectric layer 20A can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

With respect to the semiconductor device, there is a need to form a good ohmic contact between the source/drain electrode and the semiconductor layer thereunder to reduce the contact resistance therebetween, thereby alleviating unwanted heat generation. However, existing devices still cannot achieve good ohmic contacts, resulting in poor device performance.

At least to avoid the aforesaid issue, the present disclosure provides a novel electrode structure for source and drain of the device.

In the present disclosure, an intermediate intrinsic silicon nitride (SiN) layer (i.e., unintentionally doped SiN layer) is formed to cover the dielectric layer 20A and the nitride-based semiconductor layer 14, in which at least a portion of the intermediate intrinsic SiN layer can make contact with the nitride-based semiconductor layer 14 via the through hole TH.

The contact resistance is positively related to a carrier path length in a layer. To shorten the carrier path length, in the present disclosure, a doping process/an implantation process is performed on the intermediate intrinsic SiN layer located in the through holes TH with implant dopants, in which the implant dopants can be selected from a group IV element and the selected group IV element should have an atomic number greater than silicon. In some embodiments, the group IV element includes germanium (Ge) , tin (Sn) , lead (Pb) or a combination thereof. In the embodiment, the group IV element includes one type of the group IV element, for example, Ge.

After the doping process/an implantation process, an implanted region IR including implant dopants extending into at least a portion of the intrinsic SiN layer is located in the through hole TH, such that the implant dopants form a concentration distribution that has a peak concentration in the portion (i.e., the doped portion) of the SiN layer in the through hole TH. Some implant dopants may diffuse into a top portion of the nitride-based semiconductor layer 14 directly under the through hole TH, in which the concentration of the implant dopants in the top portion of the nitride-based semiconductor layer 14 is far less than the portion of the SiN layer in the through hole TH. Thus, the doped/implanted SiN layers 322, 342 can be formed. The rest portions 36, 38 (i.e., the intrinsic silicon nitride layers 36/38) of intermediate intrinsic SiN layer beyond the through hole TH still remain undoped. Then,

electrodes

324, 344 are formed on/over/above the doped SiN layers 322, 342, respectively. Thus, the

electrode structures

32, 34 can be obtained.

FIG. 1B is an enlarged view of an intrinsic SiN layer without performing doping process and a doped SiN layer. Referring to FIG. 1B, after the doping/implantation process, the implant dopants 38 with greater atomic number would effectively compress the original crystal structure of the intrinsic SiN layer, and therefore, the carrier path in the doped SiN layer 322/342 (see the right part in the FIG. 1B) can be less than that of the intrinsic SiN layer performing doping process (see the left part in the FIG. 1B) , thereby reducing heat generation during the operation of the device. Thus, by applying a doping process to at least a portion of the intrinsic SiN layer between the electrode 324/344 and the nitride-based semiconductor layer 14, a good ohmic contact can be formed therebetween. Accordingly, the nitride-based semiconductor device 1A can reduce power/heat consumption.

If the doping concentration of the group IV element/implant dopants 38 in each of the doped SiN layers 322, 342 is less than 10 ¹² cm ^-3, the crystal structure thereof would not be compressed significantly and the carrier path cannot be shortened effectively. If the doping concentration of the group IV element in each of the doped SiN layers 322, 342 is greater than 10 ¹⁴ cm ^-3, the crystal structure thereof would be damaged. The doping concentration of the group IV element in each of the doped SiN layers 322, 342 is controlled to fall in a range of 10 ¹² cm ^-3 to 10 ¹⁴ cm ^-3; and therefore, the trade-off between shortening the carrier path and keeping a good crystal structure quality is a net positive gain by selecting the aforesaid doping concentration range.

In the aforesaid embodiment, the doping/implantation process can be performed using one type of a group IV element (e.g., Ge, Sn, or Pb) to achieve a better process control. In some embodiments, the doping/implantation process can be performed using at least two types of a group IV element to meet different device requirements and provide more design flexibility to the device.

With respect to the formed electrode structure 32, the electrode structure 32 includes a doped SiN layer 322 and the electrode 324, and the electrode structure 32 penetrates the dielectric layer 20A to make contact with the nitride-based semiconductor layer 14. The doped SiN layer 322 of the electrode structure 32 penetrates the dielectric layer 20A to make contact with inner side surfaces IS of the dielectric layer 20A and a top surface of the nitride-based semiconductor layer 14 by a through hole TH the dielectric layer 20A. The formed electrode 324 is disposed on/over/above the doped SiN layer 322. The formed electrode 324 makes contact with the doped SiN layer 322. The formed electrode 324 has a greater thickness than the doped SiN layer 322. The formed electrode 324 is wrapped by the doped SiN layer 322 and located in the through hole TH of the dielectric layer 20A. The formed electrode 324 is spaced apart from the nitride-based semiconductor layer 14 by the implanted region IR (i.e., the doped SiN layer 324) . The doped SiN layer 322 and the electrode 324 can collectively fill up the through hole TH.

With respect to the formed electrode structure 34, the electrode structure 34 includes a doped SiN layer 342 and the electrode 344, and the electrode structure 34 penetrates the dielectric layer 20A to make contact with the nitride-based semiconductor layer 14. The doped SiN layer 342 of the electrode structure 34 penetrates the dielectric layer 20A to make contact with inner side surfaces IS of the dielectric layer 20A and a top surface of the nitride-based semiconductor layer 14 by a through hole TH the dielectric layer 20A. The formed electrode 344 is disposed on/over/above the doped SiN layer 342. The formed electrode 344 makes contact with the doped SiN layer 342. The formed electrode 344 has a greater thickness than the doped SiN layer 342. The formed electrode 344 is wrapped by the doped SiN layer 342 and located in the through hole TH of the dielectric layer 20A. The formed electrode 344 is spaced apart from the nitride-based semiconductor layer 14 by the implanted region IR (i.e., the doped SiN layer 344) . The doped SiN layer 342 and the electrode 344 can collectively fill up the through hole TH.

The intrinsic SiN layer 36 connects the doped SiN layer 322. The intrinsic SiN layer 38 connects the doped SiN layer 342. The intrinsic SiN layers 36, 38 are disposed on/over/above the dielectric layer 20A, and they are separated from the nitride-based semiconductor layer 14 by the dielectric layer 20A. The doped SiN layer 322 is directly located under the electrode 324, and the intrinsic SiN layer 36 surrounds the electrode 324. The doped SiN layer 342 is directly located under the electrode 344, and the intrinsic SiN layer 38 surrounds the electrode 344.

In some embodiments, the electrode 324 can serve as a source electrode. In some embodiments, the electrode 324 can serve as a drain electrode. In some embodiments, the electrode 344 can serve as a source electrode. In some embodiments, the electrode 344 can serve as a drain electrode. The role of the

electrodes

324 and 344 depends on the device design.

In some embodiments, the

electrodes

324 and 344 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

324 and 344 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. In some embodiments, each of the

electrodes

324 and 344 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 40 is disposed on/over/above the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 40 makes contact with a top surface of the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 40 is located between the electrode structures 32A and 34B. The doped nitride-based semiconductor layer 40 makes contact with inner side surfaces of the dielectric layer 20A.

The gate electrode 42 is disposed on/over/above the doped nitride-based semiconductor layer 40. The gate electrode 42 at least covers portions of the intrinsic SiN layers 362A and 364B. The gate electrode 42 extends downward to make contact with a top surface of the doped nitride-based semiconductor layer 40. The doped nitride-based semiconductor layer 40 is located between the gate electrode 42 and the nitride-based semiconductor layer 14. The doped nitride-based semiconductor layer 40 and the gate electrode 42 can collectively act as a gate structure. The gate electrode 42 is located between the

electrode structures

32, 34.

In the exemplary illustration of FIG. 1A, the nitride-based semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 42 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 40 may create at least one p-n junction with the nitride-based semiconductor layer 14 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 42 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.

Due to such mechanism, the nitride-based semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 42 or a voltage applied to the gate electrode 42 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 114) , the zone of the 2DEG region below the gate electrode 42 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 40 can be omitted, such that the nitride-based semiconductor device 1A is a depletion-mode device, which means the nitride-based semiconductor device 1A in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 40 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 40 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 12 includes undoped GaN and the nitride-based semiconductor layer 14 includes AlGaN, and the doped nitride-based semiconductor layer 40 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 42 may include metals or metal compounds. The gate electrode 42 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The dielectric layer 50 can be disposed on/over/above the intrinsic SiN layers 362A, 364B, the electrodes 341A, 341B, and the gate electrode 42. The exemplary material of the dielectric layer 50 can be identical with or similar with that of the dielectric layer 20A. Moreover, the dielectric layer 50 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the dielectric layer 50 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 54 to remove the excess portions, thereby forming a level top surface.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D, as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. Nitride-based semiconductor layers 12 and 14 can be formed on/over/above the substrate 10 in sequence by using deposition techniques. A doped nitride-based semiconductor layer 40 is formed on/over/above the nitride-based semiconductor layer 14. A dielectric layer 20A with through holes TH are formed to cover the nitride-based semiconductor layer 14, in which the through holes TH expose a top surface of the nitride-based semiconductor layer 14.

Referring to FIG. 2B, an intrinsic SiN layer IL (e.g., an unintentionally doped SiN layer) is formed to cover the resulted structure in the FIG. 2A, such that portions of the SiN layer penetrate the dielectric layer 20A by the through holes TH to make contact with the top surface of the nitride-based semiconductor layer 14. Then, a mask layer ML having openings OG is provided on the resulted structure, in which the locations and widths of the opening OG are corresponded to the through holes of the dielectric layer 20A. That is to say, the portions of the intrinsic SiN layer IL remained at inner sidewalls of the dielectric and the top surfaces of the nitride-based semiconductor layer 14 are exposed by the mask layer ML, and the portions of the intrinsic SiN layer IL are corresponded to the through hole TH. After that, a doping/implantation process is performed on the intrinsic SiN layer, such that the portions of the intrinsic SiN layer corresponded to the through hole TH are doped with a group IV element, thereby forming the doped

SiN layer

322 and 342.

Referring to FIG. 2C, electrodes 341A, 342A are formed on/over/above the doped SiN layer 322A and 323B and in the different through holes TH, respectively. Thus, the electrode structures 32, 32B are formed.

Referring to FIG. 2D, at least a portion of the dielectric layer 20A is removed, such that the doped nitride-based semiconductor layer 40 is exposed. A gate electrode 42 is formed on/over/above the doped nitride-based semiconductor layer 40. Then, a dielectric layer 50 is formed to cover the resulted structure in the FIG. 2D. Thus, the nitride-based semiconductor device 1A in the FIG. 1A can be obtained.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the inner side surfaces IS of the dielectric layer 20B are inclined with respect to a top surface of the nitride-based semiconductor layer 14, such that the portions of the doped SiN layer 322B/324B can extend along the inclined inner side surfaces IS of the dielectric layer 20B. By such a configuration, the gate electrode 324B/342B can have a bottom portion with a decreasing width toward the nitride-based semiconductor layer 14. Such a configuration can meet a specific device requirement.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the doped SiN layer 322C/342C extends to a position within a thickness of the nitride-based semiconductor layer 14C, such that doped SiN layer 322C/342C has a bottom surface BS within a thickness of the nitride-based semiconductor layer 14C.

During the formation of the through hole TH, an etching process can be performed on the dielectric layer 20C. In some cases, an over-etching phenomenon may occur, and thus a top portion of the nitride-based semiconductor layer 14C is damaged. The formed doped SiN layer 322C/342C covers the nitride-based semiconductor layer 14C can further passivate the nitride-based semiconductor layer 14C, such that the electrical properties of the nitride-based semiconductor layer 14C can be stabilized.

FIG. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the doped SiN layer 322D/342D makes contact with an entirety of a top surface and inner side surfaces of the dielectric layer 20D. The gate electrode 42 makes contact with the doped SiN layer 322D/342D and the dielectric layer 20D.

During the manufacturing process of the nitride-based semiconductor device 1D, the intrinsic silicon nitride layer is entirely doped with the implant dopant; and therefore, the mask layer ML can be omitted. Thus, the manufacturing cost of the nitride-based semiconductor device 1D can be further reduced.

Based on the above descriptions, in the present disclosure, an intrinsic silicon nitride layer between the electrode and the nitride-based semiconductor layer (e.g., barrier layer) is doped/implanted with a group IV element having a greater atomic number than silicon (e.g., Ge, Sn, Pb) , and thus a doped SiN layer is formed therebetween. The original crystal structure of the intrinsic silicon nitride layer would be compressed after the doping process due to the existence of the group IV element; and therefore, the carrier path (e.g., electron) in the doped SiN layer can be shortened. Thus, a good ohmic contact can be formed between the electrode and the nitride-based semiconductor layer (e.g., barrier layer) , and the nitride-based semiconductor device can have a good performance.

At least to avoid reduce the contact resistance between the source/drain electrode and the semiconductor layer thereunder, the present disclosure provides another way to reduce the aforesaid contact resistance.

FIG. 6A is a vertical cross-sectional view of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The nitride-based semiconductor device 1F includes a substrate 10, nitride-based semiconductor layers 12, 14F, a dielectric layer 20F,

electrode structures

32F, 34F, intrinsic silicon nitride layers 36, 38, a doped nitride-based semiconductor layer 40, a gate electrode 42, and a dielectric layer 50. The nitride-based semiconductor device 1F is similar to the nitride-based semiconductor device 1A as described and illustrated with reference to FIG. 6A, the main difference therebetween would be fully described as follows.

A contact resistance between two layers is related to characteristic of the layers. To reduce the contact resistance, the present disclosure adopts a way of doping more N-type materials into nitride-based semiconductor layer 14, such that the number of electrons therein would increase, thereby reducing the overall contact resistance. To be more specific, an electron providing layer is formed in the through holes TH to make contact with the nitride-based semiconductor layer 14. In some embodiments, the material of the nitride-based semiconductor layer 14 is, for example, selected as AlGaN. Considering that the AlGaN is nitride and the electron providing layer should have the electron providing effect to AlGaN, the aforesaid electron providing layer is, for example, selected as SiN. Thus, an intrinsic SiN layer is at least formed in the through holes TH, such that the intermediate intrinsic SiN layer makes contact with the nitride-based semiconductor layer 14.

However, due to low thermal activation rate of silicon element (i.e., N-type dopants) , it is hard to diffuse silicon into the AlGaN thereunder. The present disclosure adopts to form an unstable silicon compound in the intrinsic SiN layer, so as to enhance the activation rate of silicon element therein. Specifically, a doping process/an implantation process is performed on the intermediate intrinsic SiN layer located in the through holes TH with implant dopants, in which the implant dopants can be selected from a group III element and the selected group III element should have an atomic number smaller than silicon. In the group III elements, the material properties of boron are matched to silicon compared to other group III elements and therefore, boron (B) can assist more silicon elements from the SiN layer to diffuse into AlGaN layer thereunder. In some embodiments, the group III element is selected to be boron.

After the doping process/an implantation process, an implanted region IR including implant dopants extending into at least a portion of the intrinsic SiN layer is located in the through hole TH. Thus, doped/implanted SiN layers 322F, 342F can be formed. The rest portions 36, 38 (i.e., the intrinsic silicon nitride layers 36/38) of intermediate intrinsic SiN layer beyond the through hole TH still remain undoped.

In the doped SiN layers 322F, 342F, boron would break a chemical bond between silicon and nitrogen elements, such that boron and SiN collectively form a Si _xB _yN compound. Compared to SiN, the formed Si _xB _yN compound is unstable. After that, a thermal process is performed on the doped SiN layers 322F and 342F, more silicon elements in the doped SiN layers 322F and 342F would diffuse downward due to the instability of the Si _xB _yN compound, such that at least a portion 142F/144F directly under the doped SiN layer 322F/342F is doped with silicon above a certain concentration. For example, the silicon concentration of the silicon doped portions 142F/144F falls in a range of 10 ¹⁷ cm ^-3 to 10 ²⁰ cm ^-3. Thereafter,

electrodes

324F and 344F are formed. The

electrodes structures

32F, 34F can be obtained.

FIG. 6B is an enlarged vertical cross-sectional view of a region A in the FIG. 6A. Referring to FIG. 6B, with assistance of implant dopants, for example, boron, the doped SiN layer 322F and the silicon doped portion 142F of the nitride-based semiconductor layer 14F have silicon so as to form a concentration distribution C with at least two peaks which are located over and beneath an interface IF between the doped silicon nitride layer 322F and the silicon doped portion 142F. The amplitude of peak of the silicon concentration distribution C in the SiN layer 322F/342F is greater than that of the silicon doped portion 142F/144F. It should be noted that the actual shape of the concentration distribution C is merely an example, and the present disclosure is not limited thereto.

In some embodiments, the nitride-based semiconductor layer 14F can be AlGaN. Since silicon has a greater atomic number than Al, compared with undoped AlGaN layer, the silicon doped portion 142F/144F can have more electrons than undoped AlGaN layer. That is to say, the diffused silicon element from the SiN layer 322F/342F acts as an electron donor to the nitride-based semiconductor layer 14F. The contact resistance between the electrode 324F/344F and the silicon doped portion 142F/144F of the nitride-based semiconductor layer 14F and be reduced, a good ohmic contact can be formed therebetween. Accordingly, the nitride-based semiconductor device 1F can reduce power/heat consumption during its operation.

In some embodiments, the doping concentration of the group III element falls in a range of 10 ¹⁸ cm ^-3 to 10 ²¹ cm ^-3. If the doping concentration of the group III element/implant dopants in each of the doped SiN layers 322F, 342F is less than 10 ¹² cm ^-3, the thermal activation rate of silicon would not enhance effectively. If the doping concentration of the group III element in each of the doped SiN layers 322F, 342F is greater than 10 ¹⁴ cm ^-3, the stability of the doped SiN layers 322F, 342F would be poor. The doping concentration of the group III element in each of the doped SiN layers 322, 342 is controlled to fall in a range of 10 ¹² cm ^-3 to 10 ¹⁴ cm ^-3; and therefore, the trade-off between enhancing thermal activation rate of silicon and keeping a good stability is a net positive gain by selecting the aforesaid doping concentration range.

With respect to the formed electrode structure 32F, the electrode structure 32F includes a doped SiN layer 322F and the electrode 324F, and the electrode structure 32F penetrates the dielectric layer 20F to make contact with the nitride-based semiconductor layer 14F. The doped SiN layer 322F of the electrode structure 32F penetrates the dielectric layer 20A to make contact with inner side surfaces IS of the dielectric layer 20A and a top surface of the nitride-based semiconductor layer 14 by a through hole TH the dielectric layer 20F. The formed electrode 324F is disposed on/over/above the doped SiN layer 322F. The formed electrode 324F makes contact with the doped SiN layer 322F. The formed electrode 324F has a greater thickness than the doped SiN layer 322F. The formed electrode 324F is wrapped by the doped SiN layer 322F and located in the through hole TH of the dielectric layer 20F. The formed electrode 324F is spaced apart from the nitride-based semiconductor layer 14F by the implanted region IR (i.e., the doped SiN layer 324F) . The doped SiN layer 322F and the electrode 324F can collectively fill up the through hole TH.

With respect to the formed electrode structure 34F, the electrode structure 34F includes a doped SiN layer 342F and the electrode 344F, and the electrode structure 34F penetrates the dielectric layer 20F to make contact with the nitride-based semiconductor layer 14F. The doped SiN layer 342F of the electrode structure 34F penetrates the dielectric layer 20F to make contact with inner side surfaces IS of the dielectric layer 20F and a top surface of the nitride-based semiconductor layer 14F by a through hole TH the dielectric layer 20F. The formed electrode 344F is disposed on/over/above the doped SiN layer 342F. The formed electrode 344F makes contact with the doped SiN layer 342F. The formed electrode 344F has a greater thickness than the doped SiN layer 342F. The formed electrode 344F is wrapped by the doped SiN layer 342F and located in the through hole TH of the dielectric layer 20F. The formed electrode 344F is spaced apart from the nitride-based semiconductor layer 14F by the implanted region IR (i.e., the doped SiN layer 344F) . The doped SiN layer 342F and the electrode 344F can collectively fill up the through hole TH.

The intrinsic SiN layer 36 connects the doped SiN layer 322F. The intrinsic SiN layer 38 connects the doped SiN layer 342F. The intrinsic SiN layers 36, 38 are disposed on/over/above the dielectric layer 20F, and they are separated from the nitride-based semiconductor layer 14F by the dielectric layer 20F. The doped SiN layer 322F is directly located under the electrode 324F, and the intrinsic SiN layer 36F surrounds the electrode 324F. The doped SiN layer 342F is directly located under the electrode 344F, and the intrinsic SiN layer 38 surrounds the electrode 344F.

FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 7A, a substrate 10 is provided. A nitride-based semiconductor layer 12 is formed on/over/above the substrate 10 by using deposition techniques. An intermediate nitride-based semiconductor layer 14’ is formed on/over/above the nitride-based semiconductor layer 12. A doped nitride-based semiconductor layer 40 is formed on/over/above the intermediate nitride-based semiconductor layer 14’. A dielectric layer 20F with through holes TH are formed to cover the intermediate nitride-based semiconductor layer 14’, in which the through holes TH expose a top surface of the intermediate nitride-based semiconductor layer 14’.

Referring to FIG. 7B, an intrinsic SiN layer IL (e.g., an unintentionally doped SiN layer) is formed to cover the resulted structure in the FIG. 7A, such that portions of the SiN layer penetrate the dielectric layer 20F by the through holes TH to make contact with the top surface of the intermediate nitride-based semiconductor layer 14’. Then, a mask layer ML having openings OG is provided on the resulted structure, in which the locations and widths of the opening OG are corresponded to the through holes TH of the dielectric layer 20F. That is to say, the portions of the intrinsic SiN layer remained at inner sidewalls of the dielectric and the top surfaces of the nitride-based semiconductor layer 14 are exposed by the mask layer ML, and the portions of the intrinsic SiN layer IL are corresponded to the through hole TH. After that, a doping/implantation process is performed on the intrinsic SiN layer IL, such that the portions of the intrinsic SiN layer IL corresponded to the through hole TH are doped with a group III element, thereby forming the doped SiN layers 322F and 342F. The group III element can be, for example, boron (B) . Due to the doping process, an unstable compound Si _xB _yN compound can be formed in the doped SiN layers 322F and 342F.

Referring to FIG. 7C, a thermal annealing process is performed on the doped SiN layers 322F and 342F, such that silicon elements in the doped SiN layers 322F, 342F diffuse downward into

portions

142F, 144F of the intermediate nitride-based semiconductor layer 14’, thereby forming silicon doped

portions

142F, 144F under the through holes TH, respectively. In some embodiments, process temperature of the thermal annealing process falls in a range of about 600℃to about 900℃. Due to the existence of the Si _xB _yN compound, the thermal activate rate of the silicon during the thermal annealing process can be improved. As such, the doped SiN layers 322F/342F and the silicon doped portion 142F/144F can collectively form a concentration distribution C with at least two peaks as in FIG. 6B. Thus, a nitride-based semiconductor layer 14 with silicon doped portions 142F/144F is formed.

Referring to FIG. 7D, at least a portion of the dielectric layer 20F is removed, such that the doped nitride-based semiconductor layer 40 is exposed. A gate electrode 42 is formed on/over/above the doped nitride-based semiconductor layer 40. Then, a dielectric layer 50 is formed to cover the resulted structure in the FIG. 7D. Thus, the nitride-based semiconductor device 1F in the FIG. 6A can be obtained.

FIG. 8 is a vertical cross-sectional view of a nitride-based semiconductor device 1G according to some embodiments of the present disclosure. The nitride-based semiconductor device 1G is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that the inner side surfaces IS of the dielectric layer 20G are inclined with respect to a top surface of the nitride-based semiconductor layer 14G, such that the portions of the doped SiN layer 322G/324G can extend along the inclined inner side surfaces IS of the dielectric layer 20G. By such a configuration, the gate electrode 324G/342G can have a bottom portion with a decreasing width toward the nitride-based semiconductor layer 14G. Such a configuration can meet a specific device requirement.

FIG. 9 is a vertical cross-sectional view of a nitride-based semiconductor device 1H according to some embodiments of the present disclosure. The nitride-based semiconductor device 1H is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that the doped SiN layer 322H/342H extends to a position within a thickness of the nitride-based semiconductor layer 14H, such that doped SiN layer 322H/342H has a bottom surface BS within a thickness of the nitride-based semiconductor layer 14H.

During the formation of the through hole TH, an etching process can be performed on the dielectric layer 20H. In some cases, an over-etching phenomenon may occur, and thus a top portion of the nitride-based semiconductor layer 14C is damaged. The formed doped SiN layer 322H/342H covers the nitride-based semiconductor layer 14H can further passivate the nitride-based semiconductor layer 14H, such that the electrical properties of the nitride-based semiconductor layer 14H can be stabilized.

FIG. 10 is a vertical cross-sectional view of a nitride-based semiconductor device 1I according to some embodiments of the present disclosure. The nitride-based semiconductor device 1I is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that the doped SiN layer 322I/342I makes contact with an entirety of a top surface and inner side surfaces of the dielectric layer 20I. The gate electrode 42 makes contact with the doped SiN layer 322I/342I and the dielectric layer 20I.

During the manufacturing process of the nitride-based semiconductor device 1I, the intrinsic silicon nitride layer is entirely doped with the implant dopant; and therefore, the mask layer ML can be omitted. Thus, the manufacturing cost of the nitride-based semiconductor device 1I can be further reduced.

FIG. 11 is a vertical cross-sectional view of a nitride-based semiconductor device 1J according to some embodiments of the present disclosure. The nitride-based semiconductor device 1J is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that the silicon doped

portions

142J and 144J are thinner than the whole thickness of the nitride-based semiconductor layer 14J. Such a configuration can meet a specific device requirement.

FIG. 12 is a vertical cross-sectional view of a nitride-based semiconductor device 1K according to some embodiments of the present disclosure. The nitride-based semiconductor device 1K is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, the silicon doped

portions

142K and 144K are thinner than the whole thickness of the nitride-based semiconductor layer 14K. Each of the silicon doped

portions

142K and 144K can have a variable thickness. A curved interface (e.g., a convex interface) is formed between the silicon doped portion 142K/144K and the undoped portion of the nitride-based semiconductor layer 14K. Such a configuration can meet a specific device requirement.

FIG. 13 is a vertical cross-sectional view of a nitride-based semiconductor device 1L according to some embodiments of the present disclosure. The nitride-based semiconductor device 1L is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that the silicon doped

portions

142L and 144L are thinner than the whole thickness of the nitride-based semiconductor layer 14L. Each of the silicon doped

portions

142L and 144L can have a variable thickness. A curved interface (e.g., a concave interface) is formed between the silicon doped portion 142L/144L and the undoped portion of the nitride-based semiconductor layer 14L. Such a configuration can meet a specific device requirement.

FIG. 14 is a vertical cross-sectional view of a nitride-based semiconductor device 1M according to some embodiments of the present disclosure. The nitride-based semiconductor device 1M is similar to the nitride-based semiconductor device 1F as described and illustrated with reference to FIG. 6A, except that silicon doped

portions

142M and 144M of the nitride-based semiconductor layer 14M has parts with different thicknesses. The silicon doped

portions

142M and 144M can have inverted U-shape profile. A thicker part of the silicon doped portion 142M/144M is located directly under a thicker part of doped SiN layer 322B/324B, and a thinner part of the silicon doped portion 142M/144M is located directly under a thinner part of doped SiN layer 322M/324M. Such a configuration can meet a specific device requirement.

Based on above, in the present disclosure, by doping/implanting a group III element into the SiN layer to form unstable silicon compound (e.g., Si _xB _1-xN) therein, a thermal activation rate of silicon in the doped SiN layers during the thermal process can be improved. Thus, more silicon elements can diffuse downward to the nitride-based semiconductor layer (e.g., AlGaN) after a thermal annealing process, such that a portion of the nitride-based semiconductor layer is doped with silicon above a certain concentration. Since silicon can serve as an n-type dopant in the nitride-based semiconductor layer, the number of electrons in the nitride-based semiconductor layer would increase. Therefore, the contact resistance between the electrode and the silicon doped portion of the nitride-based semiconductor layer and be reduced, a good ohmic contact can be formed therebetween. Thus, the semiconductor device can have a good performance.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction; and

at least one electrode structure disposed on the second nitride-based semiconductor layer, wherein the electrode structure comprises a doped silicon nitride layer making contact with the second nitride-based semiconductor layer and an electrode disposed on the doped silicon nitride layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped silicon nitride layer is doped with a group IV element, and the group IV element has a greater atomic number than silicon.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the group IV element comprises germanium (Ge) , tin (Sn) , or lead (Pb) .
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doping concentration of the group IV element falls in a range of 10 ¹² cm ^-3 to 10 ¹⁴ cm ^-3.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising:

an intrinsic silicon nitride layer connected with the doped silicon nitride layer and separated from the second nitride-based semiconductor layer, wherein the doped silicon nitride layer is directly under the electrode, and the intrinsic silicon nitride layer surrounds the electrode.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped silicon nitride layer has a lattice constant smaller than the intrinsic silicon nitride layer.
The nitride-based semiconductor device of any one of the proceeding claims, further comprising a dielectric layer covering the second nitride-based semiconductor layer, wherein the electrode structure penetrates the dielectric layer to make contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped silicon nitride layer penetrates the dielectric layer to make contact with inner side surfaces of the dielectric layer and a top surface of the second nitride-based semiconductor layer through a through hole of the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the electrode is wrapped by the doped silicon nitride layer and located in the through hole of the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the inner side surfaces of the dielectric layer are perpendicular to a top surface of the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the inner side surfaces of the dielectric layer are inclined with respect to a top surface of the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped silicon nitride layer makes contact with an entirety of a top surface and side surfaces of the dielectric layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the electrode has a greater thickness than the doped silicon nitride layer.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the dielectric layer comprises an oxide.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the doped nitride-based semiconductor layer has a bottom surface within a thickness of the second nitride-based semiconductor layer.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer over a substrate;

forming a second nitride-based semiconductor layer on a first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;

forming a dielectric layer covering the second nitride-based semiconductor layer, wherein the dielectric layer has a through hole;

forming a silicon nitride layer to cover the dielectric layer and the second nitride-based semiconductor layer;

performing a doping process on the silicon nitride layer, such that at least a portion of the silicon nitride layer is doped with a group IV element; and

forming an electrode on the doped portion of the silicon nitride layer and in the through hole of the dielectric layer.
The method of any one of the proceeding claims, wherein prior the step of performing the doping process the method further comprises:

providing a mask layer to expose the portion of the silicon nitride layer corresponding to the through hole.
The method of any one of the proceeding claims, wherein the group IV element has an atomic number greater than that of silicon.
The method of any one of the proceeding claims, wherein the group IV element comprises germanium (Ge) , tin (Sn) , or lead (Pb) .
The method of any one of the proceeding claims, wherein the electrode has a thickness greater than that of the silicon nitride layer.
A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;

a dielectric layer covering the second nitride-based semiconductor layer and having at least one through hole;

a silicon nitride layer penetrating the dielectric layer by the through hole of the dielectric layer;

an implanted region including implant dopants extending into at least a portion of the silicon nitride layer located in the through hole and a top portion of the second nitride-based semiconductor layer, such that the implant dopants form a concentration distribution that has a peak concentration in the portion of the silicon nitride layer; and

an electrode disposed on and making contact with the implanted region.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the implant dopants comprise at least one type of group IV element having an atomic number greater than silicon.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the implant dopants comprise germanium (Ge) , tin (Sn) , or lead (Pb) .
The nitride-based semiconductor device of any one of the proceeding claims, wherein the electrode has a greater thickness than the implant region.
The nitride-based semiconductor device of any one of the proceeding claims, wherein the electrode is spaced apart from the second nitride-based semiconductor layer by the implanted region.