WO2024060457A1 - 准z源简化型三电平逆变器的共模电压抑制方法及系统 - Google Patents

准z源简化型三电平逆变器的共模电压抑制方法及系统 Download PDF

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WO2024060457A1
WO2024060457A1 PCT/CN2022/142870 CN2022142870W WO2024060457A1 WO 2024060457 A1 WO2024060457 A1 WO 2024060457A1 CN 2022142870 W CN2022142870 W CN 2022142870W WO 2024060457 A1 WO2024060457 A1 WO 2024060457A1
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vector
duty cycle
small
voltage
sector
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PCT/CN2022/142870
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English (en)
French (fr)
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秦昌伟
李晓艳
褚志元
张洪亮
李延峰
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山东建筑大学
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Priority to US18/280,336 priority Critical patent/US20240348152A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4833—Capacitor voltage balancing
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the invention belongs to the field of power electronic power conversion technology, and specifically relates to a common-mode voltage suppression method and system for a quasi-Z source simplified three-level inverter.
  • the quasi-Z source three-level inverter has the advantages of single-stage power conversion, continuous input current, small capacity of passive components, and no need to set dead time. It has been widely used in solar photovoltaic power generation, energy storage systems, motor drives and other fields. application. Quasi-Z source neutral point clamped (NPC) and T-type (T-Type) three-level inverters are the two most commonly used quasi-Z source three-level inverter topologies, but both require Using a larger number of power switch tubes inevitably increases system cost and volume.
  • the quasi-Z source network can be combined with a simplified three-level inverter to form a quasi-Z source simplified three-level inverter, which contains ten power switches.
  • the number of tubes is further reduced compared with the traditional quasi-Z source three-level inverter topology, and there is no need to use clamping diodes while maintaining the advantages of multi-level output. It has broad application prospects.
  • CMV Common-mode voltage
  • the present invention proposes a common mode voltage suppression method and system for a quasi-Z source simplified three-level inverter.
  • the present invention can effectively suppress the quasi-Z source simplified three-level inverter.
  • the common mode voltage of the inverter system simultaneously realizes the boost function of the system and ensures the midpoint voltage balance.
  • a first aspect of the present invention provides a common mode voltage suppression method for a quasi-Z source simplified three-level inverter.
  • Common mode voltage suppression method for quasi-Z source simplified three-level inverter including:
  • the amplitude and phase angle of the reference voltage vector determine the sector where the reference voltage vector is located
  • two large vectors and two small vectors with low common mode voltage amplitude are selected to form the basic voltage vector
  • a second aspect of the present invention provides a common mode voltage suppression system for a quasi-Z source simplified three-level inverter.
  • Common mode voltage suppression system for quasi-Z source simplified three-level inverter including:
  • a sector determination module configured to: determine the sector where the reference voltage vector is located based on the amplitude and phase angle of the reference voltage vector;
  • Basic voltage vector selection module According to the sector where the reference voltage vector is located, select two large vectors and two small vectors with low common mode voltage amplitude to form the basic voltage vector;
  • the basic voltage vector duty cycle and small vector duty cycle distribution factor calculation module is configured to: write the volt-second balance equation according to the selected basic voltage vector, and combine it with the introduced small vector duty cycle distribution factor to calculate Initial values of each basic voltage vector duty cycle and small vector duty cycle distribution factor;
  • a midpoint voltage balance controller module which is configured to: design a midpoint voltage balance controller and obtain a small vector duty cycle distribution factor correction value
  • a small vector duty cycle distribution factor update module which is configured to: update the small vector duty cycle distribution factor using the small vector duty cycle distribution factor correction value and the initial value in combination with the set midpoint voltage balance control threshold, In this way, the duty cycle of each basic voltage vector is updated;
  • the pass-through state injection and switching sequence design module is configured to: inject the pass-through state into the small vector, design the corresponding switching sequence, convert the switching sequence into the driving signal of the power switch tube, and control the quasi-Z source simplified three-level inverter The inverter works.
  • a third aspect of the invention provides a computer-readable storage medium.
  • a computer-readable storage medium having a computer program stored thereon, which when executed by a processor implements the common-mode voltage suppression method for a quasi-Z source simplified three-level inverter as described in the first aspect above A step of.
  • a fourth aspect of the invention provides a computer device.
  • a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, it implements the simplified quasi-Z source as described in the first aspect. Steps in the common-mode voltage suppression method for three-level inverters.
  • the present invention can limit the common mode voltage of the quasi-Z source simplified three-level inverter system to within ⁇ V dc /6, which is 1/2 lower than the traditional space vector modulation method.
  • the present invention injects a lower pass-through state into the P-type small vector and an upper pass-through state into the N-type small vector to realize the system voltage boosting function without affecting the normal output AC voltage of the system.
  • the present invention updates the small vector distribution factor according to the sector where the reference voltage vector is located and the DC side capacitor voltage deviation value, effectively controls the midpoint voltage balance, and the capacitor voltage fluctuation amplitude is very small.
  • the present invention has the ability to restore the balance of the midpoint voltage, thereby improving the operational reliability of the system.
  • Figure 1 shows the circuit topology of a quasi-Z source simplified three-level inverter
  • Figure 2 is a space vector diagram of the common mode voltage suppression method of the quasi-Z source simplified three-level inverter of the present invention
  • Figure 3 is a control block diagram of the common mode voltage suppression method of the quasi-Z source simplified three-level inverter of the present invention
  • Figure 4(a) and Figure 4(b) are operating waveform diagrams of the system in non-boost operation mode using the method of the present invention, including DC input voltage (V in ), quasi-Z source network output voltage (V dc ), Line voltage (va ab ), common mode voltage (v cm ), three-phase output current ( ia , ib , ic ), DC side capacitor voltage ( VC1 , V C2 , V C3 , V C4 ).
  • Figure 5(a) and Figure 5(b) are the operating waveforms of the system using the traditional space vector modulation method in the non-boost operating mode, including the DC input voltage (V in ) and the quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current ( ia , ib , ic ), DC side capacitor voltage ( VC1 , V C2 , V C3 , V C4 ).
  • Figure 6 (a) and Figure 6 (b) are working waveform diagrams of the system in boost operation mode using the method of the present invention, including DC input voltage (V in ), quasi-Z source network output voltage (V dc ), line Voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , ib , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • Figure 7(a) and Figure 7(b) are the operating waveforms of the system using the traditional space vector modulation method in the boost operation mode, including the DC input voltage (V in ) and the quasi-Z source network output voltage (V dc ) , line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , ib , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • Figure 8(a) and Figure 8(b) are working waveform diagrams of the system using the method of the present invention in the non-boost operating mode and when the midpoint voltage balance control is from enabling to canceling, including the DC input voltage (V in ) , quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , i b , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • Figure 9(a) and Figure 9(b) are working waveform diagrams of the system using the method of the present invention in the boost operation mode when the midpoint voltage balance control is from enabling to canceling, including the DC input voltage (V in ), Quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , i b , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • each block in the flowchart or block diagram may represent a module, program segment, or part of code, and the module, program segment, or part of code may include one or more components for implementing the various embodiments.
  • Executable instructions for the specified logical function may occur out of the order noted in the figures. For example, two blocks shown one after the other may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • This embodiment provides a common mode voltage suppression method for a quasi-Z source simplified three-level inverter.
  • Common mode voltage suppression method for quasi-Z source simplified three-level inverter including:
  • the amplitude and phase angle of the reference voltage vector determine the sector where the reference voltage vector is located
  • two large vectors and two small vectors with low common mode voltage amplitude are selected to form the basic voltage vector
  • Figure 1 shows the circuit topology of a quasi-Z source simplified three-level inverter, including the following components: DC power supply, quasi-Z source network, simplified three-level inverter and load.
  • the quasi-Z source network is connected between the DC power supply and the simplified three-level inverter to realize the boost function; its input voltage is V in and the output voltage is V dc .
  • the simplified three-level inverter consists of 10 power switch tubes (S 1 , S 2 ,..., S 10 ). Pulse Width Modulation (PWM) is used to control the turning on and off of each power switch tube.
  • PWM Pulse Width Modulation
  • the power switch tube is an insulated-gate bipolar transistor (IGBT); the power switch tube can also be implemented using other forms of transistors.
  • IGBT insulated-gate bipolar transistor
  • the common mode voltage is defined as the arithmetic mean of the three-phase output phase voltages of the system, that is
  • v ao , v bo and v co are the three-phase output phase voltages of the quasi-Z source simplified three-level inverter.
  • the switching state of the quasi-Z source simplified three-level inverter can be divided into two types: non-shoot-through state and shoot-through state.
  • the non-shoot-through state of the quasi-Z source simplified three-level inverter includes three types: [P], [O] and [N]. Select the neutral point of the quasi-Z source network (i.e., point O 1 in Figure 1) as the reference point.
  • the switch state is [P]
  • the bridge arm output voltage is +V dc /2
  • the switch state is [O]
  • the bridge arm output voltage is 0
  • the switch state is [N]
  • the bridge arm output voltage is -Vdc /2.
  • Up-Shoot-Through (UST) state (abbreviated as [U]
  • Down-Shoot-Through (DST) state state (abbreviated as [D]
  • Full-Shoot-Through (FST) state (abbreviated as [F]).
  • Figure 2 is a space vector diagram of the common mode voltage suppression method of the quasi-Z source simplified three-level inverter of the present invention.
  • the basic voltage vectors selected by the method of the present invention, the corresponding switching states and the turned-on switching tubes are shown in Table 1. It can be seen that the method of the present invention selects basic voltage vectors with low common mode voltage amplitude (including six large vectors, six small vectors with low common mode voltage amplitude, a zero vector with low common mode voltage amplitude, and six through vectors. ). Among them, the six small vectors selected contain only one P state or one N state at most to suppress the common mode voltage of the system.
  • Figure 3 is a control block diagram of the common mode voltage suppression method of the quasi-Z source simplified three-level inverter of the present invention.
  • a control strategy is designed, including the following steps:
  • the sector in which the reference voltage vector is located is determined based on its amplitude and phase angle.
  • sector 1 is taken as an example to illustrate the basic voltage vector selection and duty cycle calculation method.
  • select large vector V L1 [PNN], large vector V L2 [PPN], small vector V S1 [POO] and small vector V S2 [OON] to synthesize the reference voltage vector.
  • d L1 , d L2 , d S1 and d S2 respectively represent the duty cycle of the large vector [PNN], large vector [PPN], small vector [POO] and small vector [OON], and V ref is the reference voltage vector.
  • m and ⁇ are the modulation degree and the phase angle of the reference voltage vector respectively.
  • dST is the shoot-through duty cycle
  • Get the small vector duty cycle distribution factor initial value is the maximum value and minimum value
  • V C2 and V C3 are the voltages across the capacitors C 2 and C 3 respectively, and k p,np and k i,np are the parameters of the PI regulator.
  • the small vector duty cycle allocation factor correction value is used to update the small vector duty cycle allocation factor.
  • the updated small vector duty cycle distribution factor is further limited, and the duty cycle of each basic voltage vector can be further obtained.
  • the switching sequence is designed.
  • the lower pass-through state is injected into the P-type small vector, and the upper pass-through state is injected into the N-type small vector to realize the boost function without affecting the normal output AC voltage of the system.
  • the switching sequence is designed as:
  • the switching sequence is designed as:
  • the switching sequence is designed as:
  • the switching sequence is designed as:
  • the switching sequence is designed as:
  • the switching sequence is designed as:
  • the switching sequence is converted into the driving signal of the power switch tube, and then the operation of the quasi-Z source simplified three-level inverter system is controlled.
  • FIGS. 4(a) and Figure 4(b) are operating waveform diagrams of the system in non-boost operation mode using the method of the present invention, including DC input voltage (V in ), quasi-Z source network output voltage (V dc ), Line voltage (va ab ), common mode voltage (v cm ), three-phase output current ( ia , ib , ic ), DC side capacitor voltage ( VC1 , V C2 , V C3 , V C4 ).
  • the DC input voltage is set to 400V
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0 respectively.
  • the output voltage of the quasi-Z source network is basically equal to the DC input voltage, the line voltage is a five-level waveform, and the output current is a three-phase symmetrical sinusoidal waveform; the common-mode voltage amplitude is only the output voltage amplitude of the quasi-Z source network. 1/6, that is, 67V; the voltages at both ends of the capacitors C2 and C3 are equal, that is, the method of the present invention can effectively control the midpoint voltage balance.
  • Figure 5(a) and Figure 5(b) are the operating waveforms of the system using the traditional space vector modulation method in the non-boost operating mode, including the DC input voltage (V in ) and the quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current ( ia , ib , ic ), DC side capacitor voltage ( VC1 , V C2 , V C3 , V C4 ).
  • the DC input voltage is set to 400V
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0 respectively.
  • the system common mode voltage amplitude is equal to 1/3 of the quasi-Z source network output voltage amplitude, which is 133V.
  • Figure 6 (a) and Figure 6 (b) are working waveform diagrams of the system in boost operation mode using the method of the present invention, including DC input voltage (V in ), quasi-Z source network output voltage (V dc ), line Voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , ib , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • V in DC input voltage
  • V dc quasi-Z source network output voltage
  • V cm line Voltage
  • v cm common mode voltage
  • V cm three-phase output current
  • ia a , ib , ic three-phase output current
  • V C1 , V C2 , V C3 , V C4 DC side capacitor voltage
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0.1 respectively.
  • the output voltage amplitude of the quasi-Z source network is 400V, which is higher than the DC input voltage, which verifies that the method of the present invention can realize the normal voltage boosting function of the system; the common-mode voltage amplitude is only 1/1 of the output voltage amplitude of the quasi-Z source network. 6, that is, 67V; the voltages at both ends of the capacitors C2 and C3 are equal, and the fluctuation is very small, that is, the method of the present invention can effectively control the midpoint voltage balance.
  • Figure 7(a) and Figure 7(b) are the operating waveforms of the system using the traditional space vector modulation method in the boost operation mode, including the DC input voltage (V in ) and the quasi-Z source network output voltage (V dc ) , line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , ib , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • the DC input voltage is set to 320V
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0.1 respectively.
  • the system common mode voltage amplitude is as high as 1/3 of the output voltage amplitude of the quasi-Z source network, that is, 133V, which is twice the common mode voltage amplitude when the method of the present invention is used.
  • FIGS. 8(a) and Figure 8(b) are working waveform diagrams of the system using the method of the present invention in the non-boost operating mode and when the midpoint voltage balance control is from enabling to canceling, including the DC input voltage (V in ) , quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , i b , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • the DC input voltage is set to 400V
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0 respectively.
  • resistors with resistance values of 10k ⁇ and 1k ⁇ are connected in parallel at both ends of the capacitors C 2 and C 3 respectively.
  • the midpoint balance control function is enabled. It can be seen that although there are resistors with different values in parallel at both ends of the capacitors C 2 and C 3 , the voltages across the two capacitors can still remain equal. After the simulation time of 0.6s, the midpoint balance control function is cancelled, the voltages at both ends of the two capacitors are offset, and the midpoint voltage balance state cannot be maintained. This shows that the method of the present invention has the ability to actively control the midpoint voltage balance. At the same time, the midpoint voltage balance control function does not affect the common mode voltage suppression function.
  • Figure 9(a) and Figure 9(b) are working waveform diagrams of the system using the method of the present invention in the boost operation mode when the midpoint voltage balance control is from enabling to canceling, including the DC input voltage (V in ), Quasi-Z source network output voltage (V dc ), line voltage (va ab ), common mode voltage (v cm ), three-phase output current (ia a , i b , ic ), DC side capacitor voltage (V C1 , V C2 , V C3 , V C4 ).
  • the DC input voltage is set to 320V
  • the modulation degree and pass-through duty cycle are set to 0.8 and 0.1 respectively.
  • resistors with resistance values of 10k ⁇ and 1k ⁇ are connected in parallel at both ends of the capacitors C 2 and C 3 respectively. Obviously, when the midpoint balance control function is cancelled, the voltages at both ends of the capacitors C 2 and C 3 are no longer equal, thus verifying the effectiveness of the midpoint voltage balance control function of the method of the present invention.
  • This embodiment provides a common mode voltage suppression system for a quasi-Z source simplified three-level inverter.
  • Common mode voltage suppression system for quasi-Z source simplified three-level inverter including:
  • a sector determination module configured to: determine the sector where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector;
  • Basic voltage vector selection module According to the sector where the reference voltage vector is located, two large vectors and two small vectors with low common mode voltage amplitude are selected to form the basic voltage vector;
  • the basic voltage vector duty cycle and small vector duty cycle distribution factor calculation module is configured to: write the volt-second balance equation according to the selected basic voltage vector, and combine it with the introduced small vector duty cycle distribution factor to calculate Initial values of each basic voltage vector duty cycle and small vector duty cycle distribution factor;
  • a midpoint voltage balance controller module which is configured to: design a midpoint voltage balance controller and obtain a small vector duty cycle distribution factor correction value
  • a small vector duty cycle distribution factor update module which is configured to: update the small vector duty cycle distribution factor using the small vector duty cycle distribution factor correction value and the initial value in combination with the set midpoint voltage balance control threshold, In this way, the duty cycle of each basic voltage vector is updated;
  • the pass-through state injection and switching sequence design module is configured to: inject the pass-through state into the small vector, design the corresponding switching sequence, convert the switching sequence into the driving signal of the power switch tube, and control the quasi-Z source simplified three-level inverter The inverter works.
  • the factor update module and the pass-through state injection and switch sequence design module have the same examples and application scenarios as those implemented by the steps in Embodiment 1, but are not limited to the content disclosed in Embodiment 1 above. It should be noted that the above-mentioned modules, as part of the system, can be executed in a computer system such as a set of computer-executable instructions.
  • This embodiment provides a computer-readable storage medium on which a computer program is stored.
  • the program is executed by a processor, the common mode of the quasi-Z source simplified three-level inverter as described in the first embodiment is implemented. Steps in the voltage suppression method.
  • This embodiment provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor.
  • the processor executes the program, it implements the method described in Embodiment 1 above. Steps in the common-mode voltage suppression method for Z-source simplified three-level inverter.
  • embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, etc.) embodying computer-usable program code therein.
  • a computer-usable storage media including, but not limited to, magnetic disk storage, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.
  • the program can be stored in a computer-readable storage medium.
  • the program can be stored in a computer-readable storage medium.
  • the process may include the processes of the embodiments of each of the above methods.
  • the storage medium can be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

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Abstract

本发明提供一种准Z源简化型三电平逆变器的共模电压抑制方法及系统。该方法包括根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。

Description

准Z源简化型三电平逆变器的共模电压抑制方法及系统
本发明要求于2022年9月19日提交中国专利局、申请号为202211135853.7、发明名称为“准Z源简化型三电平逆变器的共模电压抑制方法及系统”的中国专利申请的优先权，其全部内容通过引用结合在本发明中。
技术领域
本发明属于电力电子功率变换技术领域，具体涉及一种准Z源简化型三电平逆变器的共模电压抑制方法及系统。
背景技术
本部分的陈述仅仅是提供了与本发明相关的背景技术信息，不必然构成在先技术。
准Z源三电平逆变器具有单级形式功率变换、输入电流连续、无源器件容量小、无需设置死区时间等优势，在太阳能光伏发电、储能系统、电机驱动等领域得到了广泛应用。准Z源中点箝位型(Neutral Point Clamped，NPC)和T型(T-Type)三电平逆变器是最为常用的两种准Z源三电平逆变器拓扑，但两者需采用数量较多的功率开关管，不可避免地增加了系统成本和体积。
为进一步减少功率开关管数量、降低系统体积和成本，可将准Z源网络与简化型三电平逆变器结合，构成准Z源简化型三电平逆变器，其包含十个功率开关管，数量较传统准Z源三电平逆变器拓扑进一步减少，且无需采用箝位二极管，同时保持多电平输出等优点，应用前景广阔。
发明人发现，用于准Z源简化型三电平逆变器的现有调制方法采用全部基本电压矢量合成参考电压矢量，遂使得系统输出共模电压(Common-Mode Voltage，CMV)幅值很高，进而引发共模电流、电磁干扰等诸多弊端，严重影响系统正常运行。因此，适用于准Z源简化型三电平逆变器的共模电压抑制方法亟待研究。
发明内容
为了解决上述背景技术中存在的技术问题，本发明提出了一种准Z源简化型三电平逆变器的共模电压抑制方法及系统，本发明能有效抑制准Z源简化型三电平逆变器系统的共模电压，同时实现系统的升压功能，并保证中点电压平衡。
为了实现上述目的，本发明采用如下技术方案：
本发明的第一个方面提供一种准Z源简化型三电平逆变器的共模电压抑制方法。
准Z源简化型三电平逆变器的共模电压抑制方法，包括：
根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
本发明的第二个方面提供一种准Z源简化型三电平逆变器的共模电压抑制系统。
准Z源简化型三电平逆变器的共模电压抑制系统，包括：
扇区判断模块，其被配置为：根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
基本电压矢量选取模块：根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
基本电压矢量占空比和小矢量占空比分配因子计算模块，其被配置为：根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
中点电压平衡控制器模块，其被配置为：设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
小矢量占空比分配因子更新模块，其被配置为：利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
直通状态注入及开关序列设计模块，其被配置为：在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
本发明的第三个方面提供一种计算机可读存储介质。
一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如 上述第一个方面所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
本发明的第四个方面提供一种计算机设备。
一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如上述第一个方面所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
与现有技术相比，本发明的有益效果是：
1、本发明可将准Z源简化型三电平逆变器系统的共模电压限制在±V dc/6以内，较传统空间矢量调制方法降低1/2。
2、本发明在P型小矢量中注入下直通状态，在N型小矢量中注入上直通状态，以实现系统升压功能，且不影响系统正常输出交流电压。
3、本发明根据参考电压矢量所在的扇区和直流侧电容电压偏差值，更新小矢量分配因子，有效控制中点电压平衡，电容电压波动幅值很小。
4、当异常因素导致中点电压发生偏移时，本发明具备中点电压平衡恢复能力，从而提高了系统的运行可靠性。
本发明附加方面的优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
构成本发明的一部分的说明书附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。
图1为准Z源简化型三电平逆变器的电路拓扑图；
图2为本发明准Z源简化型三电平逆变器的共模电压抑制方法的空间矢量图；
图3为本发明准Z源简化型三电平逆变器的共模电压抑制方法的控制框图；
图4(a)和图4(b)为系统采用本发明方法、在非升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
图5(a)和图5(b)为系统采用传统空间矢量调制方法、在非升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
图6(a)和图6(b)为系统采用本发明方法、在升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相 输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
图7(a)和图7(b)为系统采用传统空间矢量调制方法、在升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
图8(a)和图8(b)为系统采用本发明方法、在非升压运行模式下、中点电压平衡控制由使能至取消时的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
图9(a)和图9(b)为系统采用本发明方法、在升压运行模式下、中点电压平衡控制由使能至取消时的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。
具体实施方式
下面结合附图与实施例对本发明作进一步说明。
应该指出，以下详细说明都是例示性的，旨在对本发明提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本发明所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本发明的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
需要注意的是，附图中的流程图和框图示出了根据本公开的各种实施例的方法和系统的可能实现的体系架构、功能和操作。应当注意，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，所述模块、程序段、或代码的一部分可以包括一个或多个用于实现各个实施例中所规定的逻辑功能的可执行指令。也应当注意，在有些作为备选的实现中，方框中所标注的功能也可以按照不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，或者它们有时也可以按照相反的顺序执行，这取决于所涉及的功能。同样应当注意的是，流程图和/或框图中的每个方框、以及流程图和/或框图中的方框的组合，可以使用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以使用专用硬件与计算机指令的组合来实现。
实施例一
本实施例提供了一种准Z源简化型三电平逆变器的共模电压抑制方法。
准Z源简化型三电平逆变器的共模电压抑制方法，包括：
根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
图1为准Z源简化型三电平逆变器的电路拓扑图，包括如下组成部分：直流电源、准Z源网络、简化型三电平逆变器和负载。其中，准Z源网络连接在直流电源和简化型三电平逆变器之间，用于实现升压功能；其输入电压为V in，输出电压为V dc。简化型三电平逆变器由10只功率开关管(S 1,S 2,…,S 10)组成。采用脉宽调制(Pulse Width Modulation，PWM)方式控制各功率开关管的开通及关断。可以理解的是，功率开关管为绝缘栅双极型晶体管(Insulate-Gate Bipolar Transistor，IGBT)；功率开关管也可采用其他形式晶体管来实现。
在准Z源简化型三电平逆变器系统中，功率器件固有的高频开关特性产生共模电压(Common-Mode Voltage，CMV)，进而引发共模电流、电磁干扰等诸多弊端，严重影响系统正常运行。因此，共模电压抑制已成为亟待解决的关键问题。
共模电压定义为系统三相输出相电压的算术平均值，即
Figure PCTCN2022142870-appb-000001
其中，v ao、v bo和v co为准Z源简化型三电平逆变器的三相输出相电压。
准Z源简化型三电平逆变器的开关状态可分为两种：非直通(Non-Shoot-Through)状态和直通(Shoot-Through)状态。与普通简化型三电平逆变器相同，准Z源简化型三电平逆变器的非直通状态包括三种：[P]、[O]和[N]。选择准Z源网络的中性点(即图 1中的点O 1)作为参考点。当开关状态为[P]时，桥臂输出电压为+V dc/2；当开关状态为[O]时，桥臂输出电压为0；当开关状态为[N]时，桥臂输出电压为-V dc/2。准Z源简化型三电平逆变器的直通状态包括三种：上直通(Up-Shoot-Through,UST)状态(简记为[U])、下直通(Down-Shoot-Through,DST)状态(简记为[D])、全直通(Full-Shoot-Through,FST)状态(简记为[F])。
表1本发明方法选取的基本电压矢量及对应开关状态
Figure PCTCN2022142870-appb-000002
图2为本发明准Z源简化型三电平逆变器的共模电压抑制方法的空间矢量图。本发明方法选取的基本电压矢量、对应开关状态及开通的开关管见表1。可见：本发明方法选取低共模电压幅值的基本电压矢量(包括六个大矢量、六个低共模电压幅值的小矢量、一个低共模电压幅值的零矢量、六个直通矢量)。其中，选取的六个小矢量最多仅包含一个P状态或一个N状态，以抑制系统的共模电压。
图3为本发明准Z源简化型三电平逆变器的共模电压抑制方法的控制框图。为实现共模电压抑制、中点电压平衡控制和升压等目标，设计控制策略，具体包括如下步骤：
1.参考电压矢量所在扇区判断
根据参考电压矢量的幅值和相角，判断其所在扇区(Sector)。
2.基本电压矢量选取及小矢量占空比分配因子计算
不失一般性，以扇区1为例，说明基本电压矢量选取及占空比计算方法。当参考电压矢量位于扇区1时，选取大矢量V L1[PNN]、大矢量V L2[PPN]、小矢量V S1[POO]和小矢量V S2[OON]合成参考电压矢量。根据伏秒平衡原理可得：
Figure PCTCN2022142870-appb-000003
其中，d L1、d L2、d S1和d S2分别表示大矢量[PNN]、大矢量[PPN]、小矢量[POO]和小矢量[OON]的占空比，V ref为参考电压矢量。
因采用四个基本电压矢量合成参考电压矢量，设计间接计算方法求解基本电压矢量占空比。大矢量V L1[PNN]、大矢量V L2[PPN]、小矢量V S1[POO]和小矢量V S2[OON]的表达式分别为
Figure PCTCN2022142870-appb-000004
将各基本电压矢量的表达式代入伏秒平衡方程并化简，可得两个小矢量的占空比之和满足：
Figure PCTCN2022142870-appb-000005
其中，m和θ分别为调制度和参考电压矢量的相角。
引入小矢量占空比分配因子
Figure PCTCN2022142870-appb-000006
将d S1和d S2分别表示为：
Figure PCTCN2022142870-appb-000007
为保证系统的正常升压功能，需对小矢量占空比分配因子
Figure PCTCN2022142870-appb-000008
作限幅处理，即：
Figure PCTCN2022142870-appb-000009
其中，d ST为直通占空比。
求解上述不等式组，可得小矢量占空比分配因子
Figure PCTCN2022142870-appb-000010
需满足
Figure PCTCN2022142870-appb-000011
利用上述小矢量占空比分配因子，两个大矢量的占空比可表示为
Figure PCTCN2022142870-appb-000012
因各基本电压矢量的占空比需大于0、且小于1，可得小矢量占空比分配因子
Figure PCTCN2022142870-appb-000013
的取值范围如下：
Figure PCTCN2022142870-appb-000014
综合考虑小矢量占空比分配因子
Figure PCTCN2022142870-appb-000015
的限幅情况，可得其最小值和最大值分别为
Figure PCTCN2022142870-appb-000016
Figure PCTCN2022142870-appb-000017
由不等式放缩原理，不难得到
Figure PCTCN2022142870-appb-000018
取小矢量占空比分配因子
Figure PCTCN2022142870-appb-000019
的初始值
Figure PCTCN2022142870-appb-000020
为最大值
Figure PCTCN2022142870-appb-000021
和最小值
Figure PCTCN2022142870-appb-000022
的算术平均值，即
Figure PCTCN2022142870-appb-000023
当参考电压矢量位于除扇区1之外的其它扇区时，利用不同扇区之间的相角映射关系及空间矢量图的对称性，不难得到相应基本电压矢量的占空比和小矢量占空比分配因子的值，不再赘述。
3.中点电压平衡控制器设计
采样准Z源网络中电容C 2和C 3两端的电压，计算两电容电压的偏差，并送入PI调节器，其输出量取绝对值运算得到小矢量占空比分配因子修正值y np，即
Figure PCTCN2022142870-appb-000024
其中，V C2和V C3分别为电容C 2和C 3两端的电压，k p,np和k i,np为PI调节器的参数。
4.小矢量占空比分配因子更新
根据系统中点电压平衡控制要求，设置中点电压平衡控制阈值ΔV np_th。根据参考电压矢量所在的扇区和电容C 2、C 3的电压偏差，利用小矢量占空比分配因子修正值，更新小矢量占空比分配因子，具体规则如下：
(1)当-ΔV np_th<V C2-V C3<ΔV np_th时，小矢量占空比分配因子保持为其初始值不变，即
Figure PCTCN2022142870-appb-000025
(2)当参考电压矢量位于扇区1、扇区3或扇区5，且V C2-V C3>ΔV np_th时，将小矢量占空比分配因子更新为
Figure PCTCN2022142870-appb-000026
(3)当参考电压矢量位于扇区1、扇区3或扇区5，且V C2-V C3<-ΔV np_th时，将小矢量占空比分配因子更新为
Figure PCTCN2022142870-appb-000027
(4)当参考电压矢量位于扇区2、扇区4或扇区6，且V C2-V C3>ΔV np_th时，将小矢量占空比分配因子更新为
Figure PCTCN2022142870-appb-000028
(5)当参考电压矢量位于扇区2、扇区4或扇区6，且V C2-V C3<-ΔV np_th时，将小矢量占空比分配因子更新为
Figure PCTCN2022142870-appb-000029
根据式(10)和式(11)给出的限制条件，对更新后的小矢量占空比分配因子作进一步限幅处理，进一步可得各基本电压矢量的占空比。
5.直通状态注入及开关序列设计
考虑输出谐波含量低、开关损耗低等因素，设计开关序列。在P型小矢量中注入下直通状态，在N型小矢量中注入上直通状态，实现升压功能，且不影响系统正常输出交流电压。
当参考电压矢量位于扇区1时，开关序列设计为：
PNN-UUN-OON-PPN-PDD-POO-PDD-PPN-OON-UUN-PNN；
当参考电压矢量位于扇区2时，开关序列设计为：
PPN-DPD-OPO-NPN-UUN-OON-UUN-NPN-OPO-DPD-PPN；
当参考电压矢量位于扇区3时，开关序列设计为：
NPN-NUU-NOO-NPP-DPD-OPO-DPD-NPP-NOO-NUU-NPN；
当参考电压矢量位于扇区4时，开关序列设计为：
NPP-DDP-OOP-NNP-NUU-NOO-NUU-NNP-OOP-DDP-NPP；
当参考电压矢量位于扇区5时，开关序列设计为：
NNP-UNU-ONO-PNP-DDP-OOP-DDP-PNP-ONO-UNU-NNP；
当参考电压矢量位于扇区6时，开关序列设计为：
PNP-PDD-POO-PNN-UNU-ONO-UNU-PNN-POO-PDD-PNP。
将开关序列转换为功率开关管的驱动信号，进而控制准Z源简化型三电平逆变器系统工作。
图4(a)和图4(b)为系统采用本发明方法、在非升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为400V，调制度和直通占空比分别设置为0.8和0。可以看出：准Z源网络输出电压与直流输入电压基本相等，线电压为五电平波形，输出电流为三相对称正弦波形；共模电压幅值仅为准Z源网络输出电压幅值的1/6，即67V；电容C 2和C 3两端的电压相等，即本发明方法能有效控制中点电压平衡。
图5(a)和图5(b)为系统采用传统空间矢量调制方法、在非升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为400V，调制度和直通占空比分别设置为0.8和0。系统共模电压幅值等于准Z源网络输出电压幅值的1/3，即133V。对比图4(a)和图5(a)可以看出：与传统空间矢量调制方法相比，本发明方法可将准Z源简化型三电平逆变器系统的共模电压幅值降低1/2，优势明显。
图6(a)和图6(b)为系统采用本发明方法、在升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为320V，调制度和直通占空比分别设置为0.8和0.1。显而易见，准Z源网络输出电压幅值为400V，高于直流输入电压，验证了本发明方法可实现系统正常升压功能；共模电压幅值仅为准Z源网络输出电压幅值的1/6，即67V；电容C 2和C 3两端的电压相等，且波动很小，即本发明方法能有效控制中点电压平衡。
图7(a)和图7(b)为系统采用传统空间矢量调制方法、在升压运行模式下的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为320V，调制度和直通占空比分别设置为0.8和0.1。显然，当采用传统空间矢量调制方法时，系统共模电压幅值高达准Z源网络输出电压幅值的1/3，即133V， 为采用本发明方法时共模电压幅值的2倍。
图8(a)和图8(b)为系统采用本发明方法、在非升压运行模式下、中点电压平衡控制由使能至取消时的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为400V，调制度和直通占空比分别设置为0.8和0。为验证本发明方法的中点电压平衡控制功能，在电容C 2、C 3两端分别并联阻值为10kΩ、1kΩ的电阻。在仿真时间0.6s之前，使能中点平衡控制功能，可以看出：虽然电容C 2、C 3两端分别并联有阻值不同的电阻，但两个电容两端的电压仍能保持相等。在仿真时间0.6s之后，取消中点平衡控制功能，两个电容两端的电压发生了偏移，无法保持中点电压平衡状态，从而说明本发明方法具备中点电压平衡主动控制能力。同时，中点电压平衡控制功能不影响共模电压抑制功能。
图9(a)和图9(b)为系统采用本发明方法、在升压运行模式下、中点电压平衡控制由使能至取消时的工作波形图，包括直流输入电压(V in)、准Z源网络输出电压(V dc)、线电压(v ab)、共模电压(v cm)、三相输出电流(i a、i b、i c)、直流侧电容电压(V C1、V C2、V C3、V C4)。此时，直流输入电压设置为320V，调制度和直通占空比分别设置为0.8和0.1。为验证本发明方法的中点电压平衡控制功能，在电容C 2、C 3两端分别并联阻值为10kΩ、1kΩ的电阻。显而易见，当取消中点平衡控制功能后，电容C 2、C 3两端的电压不再相等，从而验证了本发明方法中点电压平衡控制功能的有效性。
实施例二
本实施例提供了一种准Z源简化型三电平逆变器的共模电压抑制系统。
准Z源简化型三电平逆变器的共模电压抑制系统，包括：
扇区判断模块，其被配置为：根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
基本电压矢量选取模块：根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
基本电压矢量占空比和小矢量占空比分配因子计算模块，其被配置为：根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
中点电压平衡控制器模块，其被配置为：设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
小矢量占空比分配因子更新模块，其被配置为：利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
直通状态注入及开关序列设计模块，其被配置为：在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
此处需要说明的是，上述扇区判断模块、基本电压矢量选取模块、基本电压矢量占空比和小矢量占空比分配因子计算模块、中点电压平衡控制器模块、小矢量占空比分配因子更新模块和直通状态注入及开关序列设计模块与实施例一中的步骤所实现的示例和应用场景相同，但不限于上述实施例一所公开的内容。需要说明的是，上述模块作为系统的一部分可以在诸如一组计算机可执行指令的计算机系统中执行。
实施例三
本实施例提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如上述实施例一所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
实施例四
本实施例提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如上述实施例一所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功 能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，包括：
    根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
    根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
    根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
    设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
    利用小矢量占空比分配因子修正值和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
    在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
  2. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，选取低共模电压幅值的基本电压矢量，包括：六个大矢量、六个低共模电压幅值的小矢量、一个低共模电压幅值的零矢量、六个直通矢量。
  3. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，所述计算各基本电压矢量占空比具体包括：
    将两个大矢量的表达式、两个小矢量的表达式和参考电压矢量的相角，代入伏秒平衡方程，得到两个小矢量的占空比之和，引入小矢量占空比分配因子，得到两个小矢量的占空比；
    根据小矢量占空比分配因子，得到两个大矢量的占空比；
    由此得到各基本电压矢量的占空比。
  4. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，所述小矢量占空比分配因子的初始值计算的过程包括：
    根据调制度、参考电压矢量的相角和直通占空比，计算小矢量占空比分配因子的最小值和最大值；当参考电压矢量位于扇区1时，小矢量占空比分配因子的最小值和最大值分别为
    Figure PCTCN2022142870-appb-100001
    Figure PCTCN2022142870-appb-100002
    其中，m、θ和d ST分别为调制度、参考电压矢量的相角和直通占空比；
    根据小矢量占空比分配因子的最大值和最小值的算术平均值，得到小矢量占空比分配因子的初始值。
  5. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，所述设计中点电压平衡控制器，得到小矢量占空比分配因子修正值具体包括：
    根据采样准Z源网络中电容C 2和C 3两端的电压，计算两电容电压的偏差，并送入PI调节器，其输出量取绝对值运算得到小矢量占空比分配因子修正值y np，即
    Figure PCTCN2022142870-appb-100003
    其中，V C2和V C3分别为电容C 2和C 3两端的电压，k p,np和k i,np为PI调节器的参数。
  6. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，所述更新小矢量占空比分配因子的过程包括：根据系统中点电压平衡控制要求，设置中点电压平衡控制阈值ΔV np_th；根据参考电压矢量所在的扇区和电容C 2、C 3的电压偏差，利用小矢量占空比分配因子修正值，更新小矢量占空比分配因子；
    当-ΔV np_th<V C2-V C3<ΔV np_th时，小矢量占空比分配因子保持为其初始值不变，即
    Figure PCTCN2022142870-appb-100004
    当参考电压矢量位于扇区1、扇区3或扇区5，且V C2-V C3>ΔV np_th时，将小矢量占空比分配因子更新为
    Figure PCTCN2022142870-appb-100005
    当参考电压矢量位于扇区1、扇区3或扇区5，且V C2-V C3<-ΔV np_th时，将小矢量占空比分配因子更新为
    Figure PCTCN2022142870-appb-100006
    当参考电压矢量位于扇区2、扇区4或扇区6，且V C2-V C3>ΔV np_th时，将小矢量占空比分配因子更新为
    Figure PCTCN2022142870-appb-100007
    当参考电压矢量位于扇区2、扇区4或扇区6，且V C2-V C3<-ΔV np_th时，将小矢量占空比分配因子更新为
    Figure PCTCN2022142870-appb-100008
  7. 根据权利要求1所述的准Z源简化型三电平逆变器的共模电压抑制方法，其特征在于，所述在小矢量中注入直通状态，设计相应的开关序列具体包括：在P型小矢量中注入下直通状态，在N型小矢量中注入上直通状态；
    当参考电压矢量位于扇区1时，开关序列设计为：
    PNN-UUN-OON-PPN-PDD-POO-PDD-PPN-OON-UUN-PNN；
    当参考电压矢量位于扇区2时，开关序列设计为：
    PPN-DPD-OPO-NPN-UUN-OON-UUN-NPN-OPO-DPD-PPN；
    当参考电压矢量位于扇区3时，开关序列设计为：
    NPN-NUU-NOO-NPP-DPD-OPO-DPD-NPP-NOO-NUU-NPN；
    当参考电压矢量位于扇区4时，开关序列设计为：
    NPP-DDP-OOP-NNP-NUU-NOO-NUU-NNP-OOP-DDP-NPP；
    当参考电压矢量位于扇区5时，开关序列设计为：
    NNP-UNU-ONO-PNP-DDP-OOP-DDP-PNP-ONO-UNU-NNP；
    当参考电压矢量位于扇区6时，开关序列设计为：
    PNP-PDD-POO-PNN-UNU-ONO-UNU-PNN-POO-PDD-PNP。
  8. 准Z源简化型三电平逆变器的共模电压抑制系统，其特征在于，包括：
    扇区判断模块，其被配置为：根据参考电压矢量的幅值和相角，判断参考电压矢量所在扇区；
    基本电压矢量选取模块：根据参考电压矢量所在扇区，选取两个大矢量和两个低共模电压幅值的小矢量构成基本电压矢量；
    基本电压矢量占空比和小矢量占空比分配因子计算模块，其被配置为：根据选取的基本电压矢量，列写伏秒平衡方程，结合引入的小矢量占空比分配因子，以此计算各基本电压矢量占空比和小矢量占空比分配因子的初始值；
    中点电压平衡控制器模块，其被配置为：设计中点电压平衡控制器，得到小矢量占空比分配因子修正值；
    小矢量占空比分配因子更新模块，其被配置为：利用小矢量占空比分配因子修正值 和所述初始值，结合设置的中点电压平衡控制阈值，更新小矢量占空比分配因子，以此更新各基本电压矢量的占空比；
    直通状态注入及开关序列设计模块，其被配置为：在小矢量中注入直通状态，设计相应的开关序列，将开关序列转换为功率开关管的驱动信号，控制准Z源简化型三电平逆变器工作。
  9. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该程序被处理器执行时实现如权利要求1-7中任一项所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
  10. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述程序时实现如权利要求1-7中任一项所述的准Z源简化型三电平逆变器的共模电压抑制方法中的步骤。
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