WO2024058820A1 - Forming a partially silicided element - Google Patents

Forming a partially silicided element Download PDF

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Publication number
WO2024058820A1
WO2024058820A1 PCT/US2023/015161 US2023015161W WO2024058820A1 WO 2024058820 A1 WO2024058820 A1 WO 2024058820A1 US 2023015161 W US2023015161 W US 2023015161W WO 2024058820 A1 WO2024058820 A1 WO 2024058820A1
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Prior art keywords
silicided
silicide layer
dielectric
base structure
region
Prior art date
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PCT/US2023/015161
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French (fr)
Inventor
Yaojian Leng
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Microchip Technology Incorporated
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Publication date
Priority claimed from US18/070,748 external-priority patent/US20240087886A1/en
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Publication of WO2024058820A1 publication Critical patent/WO2024058820A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present disclosure relates to integrated circuit (IC) devices, and more particularly to partially silicided elements and methods of forming partially silicided elements in IC devices.
  • IC integrated circuit
  • CMOS complementary metal oxide semiconductor
  • a silicided element includes a metal silicide layer formed on a base structure, e.g., a polysilicon element or an active region, wherein the silicide layer exhibits increased conductance, e.g., to provide improved electrical contact with the underlying base structure.
  • CMOS transistor structures are often formed as silicided elements, or example CMOS transistor gates (“poly gates”) and CMOS transistor active regions (e.g., source and drain regions).
  • silicidation may result in ineffective or undesirable performance.
  • CMOS transistors used in ESD (electrostatic discharge) circuits are typically not silicided, as silicidation may restrict high voltage capability.
  • polysilicon resistors (“poly resistors”) are typically formed without silicidation, in order to achieve desired sheet resistance values.
  • IC elements may be formed partially silicided, elements, wherein a “partially silicided” element refers to a base structure (e.g., a polysilicon structure or a doped silicon region) having a top surface including at least one silicided region (having a silicide layer formed thereon) and at least one non-silicided region (without a silicide layer formed thereon).
  • a “partially silicided” device e.g., a partially silicided CMOS transistor or a partially silicided resistor, refers to a device including at least one partially silicided element.
  • Partially silicided elements are conventionally formed by blocking the formation of silicide on a partial surface area of the base structure top surface, typically with a thin layer of silicon oxide referred to as a silicide block layer or resistor protection oxide (RPO).
  • a silicide blocking process a photo mask is used to etch away selected area of the silicide block layer, allowing silicidation of the exposed areas of the underlying base structure top surface, while preventing silicidation of areas of the base structure top surface covered by the silicide block layer.
  • this silicide blocking process requires an additional photomask process, which adds significant cost to the relevant manufacturing process.
  • the present disclosure provides devices including example partially silicided elements and example methods of forming devices including partially silicided elements.
  • Example types of partially silicided elements disclosed herein include (a) elements of a CMOS transistor (e.g., a partially silicided poly gate, a partially silicided source region, and a partially silicided drain region), and (b) a partially silicided resistive element of an integrated resistor.
  • partially silicided elements may be formed concurrently with respective fully silicided elements.
  • a partially silicided CMOS transistor may be formed concurrently with a fully silicided CMOS transistor.
  • Some examples provide a process of forming a partially silicided element that eliminates the need for a silicide block layer (or RPO) used in conventional processes, which may reduce manufacturing costs.
  • a partially silicided element may be formed without adding any mask layers to the background or baseline manufacturing process of the relevant IC device.
  • a silicided structure is formed, including a silicide layer on a base structure.
  • a dielectric region is formed over the silicided structure.
  • a first etch process is performed to form a contact opening and a tub opening in the dielectric region, the contact opening exposing a first area of the silicide layer, and the tub opening exposing a second area of the silicide layer.
  • a conformal metal is deposited over the dielectric region, the deposited conformal metal (a) filling the contact opening to define a contact conductively connected to the first area of the silicide layer and (b) forming a cup-shaped metal structure in the tub opening.
  • a second etch process is performed to remove the cup-shaped metal structure in the tub opening, to remove the second area of the silicide layer, and to expose an area of the base structure under the second area of the silicide layer, wherein the first area of the silicide layer remains intact after the second etch process.
  • the base structure with the intact first area of the silicide layer and the removed second area of the silicide layer defines the partially silicided element.
  • the base structure comprises a polysilicon element.
  • the base structure may comprise a polysilicon gate of a transistor, or a polysilicon resistor element.
  • the base structure comprises an active region of a transistor, e.g., a doped source region or a doped drain region.
  • the conformal metal comprises tungsten.
  • the method includes filling the tub opening with a dielectric fill material after the second etch process.
  • the second etch process includes (a) a conformal metal etch to remove the cup-shaped metal structure from the tub opening and (b) a silicide etch to remove the second area of the silicide layer.
  • the dielectric region formed over the silicided structure includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch process removes an upper portion of the contact having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer, and the method includes filling the tub opening with a dielectric fill material after the second etch process, and performing a planarization process to remove an upper portion of the dielectric fill material and a remaining portion of the sacrificial dielectric layer.
  • the dielectric base layer and the sacrificial dielectric layer comprise respective portions of a dielectric material deposited over the silicided structure.
  • the base dielectric layer comprises a first dielectric material and the sacrificial dielectric layer comprises a second dielectric material different than the first dielectric material.
  • a lateral width of the tub opening is greater than a lateral width of the contact opening.
  • the contact opening has a lateral width in the range of 0.1 -0.5 pm
  • the tub opening has a lateral width in the range of l-100pm.
  • a device including a partially silicided element including a base structure having a top surface including a silicided region and a non-silicided region. The silicided region of the top surface of the base structure is covered by a silicide layer, and the non-silicided region of the top surface of the base structure is not covered by the silicide layer. A vertical height of the silicided region of the top surface of the base structure is equal to or greater than a vertical height of the non-silicided region of the top surface of the base structure.
  • the base structure comprises a polysilicon element.
  • the base structure may comprise a polysilicon gate of a transistor, or a polysilicon resistor element.
  • the base structure comprises an active region of a transistor, e.g., a doped source region or a doped drain region.
  • the device further includes a fully silicided element including a second base structure having a second top surface fully covered by a second silicide layer, wherein the base structure of the partially silicided element and the second base structure of the fully silicided element comprise respective portions of a common material layer.
  • One aspect provides a method of forming an integrated circuit (IC) device including (a) a partially silicided element and (b) a fully silicided element.
  • a first silicided structure and a second silicided structure are formed, the first silicided structure including a first silicide layer formed on a first base structure, and the second silicided structure including a second silicide layer formed on a second base structure.
  • a dielectric region is formed over the first and second silicided structures.
  • a first etch process is performed to form a first contact opening, a second contact opening, and a tub opening in the dielectric region, wherein the first contact opening exposes the first silicide layer, the second contact opening exposes a first area of the second silicide layer, and the tub opening exposes a second area of the second silicide layer.
  • a conformal metal is deposited over the dielectric region, the deposited conformal metal layer (a) filling the first contact opening to define a first contact conductively connected to the first silicide layer, (b) filling the second contact opening to define a second contact conductively connected to the first area of the second silicide layer, and (c) forming a cup-shaped metal structure in the tub opening.
  • a second etch process is performed to remove the cup-shaped metal structure in the tub opening, to remove the second area of the second silicide layer, and to expose an area of the second base structure under the second area of the second silicide layer, wherein the first silicide layer and the first area of the second silicide layer remain intact after the second etch process.
  • the tub opening is filled with a dielectric fill material.
  • the first base structure with the intact first silicide layer defines the fully silicided element
  • the second base structure with the intact first area of the second silicide layer and the removed second area of the second silicide layer defines the partially silicided element.
  • the dielectric region formed over the first and second silicided structures includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch process removes an upper portion of the first contact and an upper portion of the second contact respectively having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer; and the method includes, after filling the tub opening with the dielectric fill material, performing a planarization process to remove remaining portions of the sacrificial dielectric layer.
  • Figures 1A-1G show an example IC device including a partially silicided CMOS transistor, including a partially silicided poly gate and partially silicided source and drain regions;
  • Figures 2A and 2B show an example IC device including (a) the example partially silicided CMOS transistor structure shown in Figures 1 A-1G and (b) an example fully silicided CMOS transistor structure;
  • Figures 3 A-3B through Figure 8 illustrate an example method of forming the example IC device (including the partially silicided CMOS transistor structure and fully silicided CMOS transistor structure) shown in Figures 2A and 2B;
  • Figures 9A and 9B show an example partially silicided resistor, including a partially silicided resistive element
  • Figures 10A-10B through Figures 15A-15B illustrate an example method of forming the example partially silicided resistor shown in Figures 9A and 9B.
  • CMOS transistor for example a poly gate, a source region, and a drain region
  • CMOS transistor structure may be referred to as a partially silicided CMOS transistor.
  • a resistor may include a resistive element formed as a partially silicided element, wherein such resistor may be referred to as a partially silicided resistor.
  • partially silicided CMOS transistors or partially silicided resistors may be formed concurrently with fully silicided elements (e.g., fully silicided CMOS transistors) in respective IC devices.
  • Figures 1 A-1G show an example IC device 100 including an example partially silicided CMOS transistor 102, according to one example.
  • Figure 1 A shows a top view of the example IC device 100
  • Figures IB, IC, ID, IE, IF, and 1G show cross-sectional side views through respective cut lines 1B-1B, 1C-1C, ID-ID, 1E-1E, 1F-1F, and 1G-1G shown in Figure 1A.
  • the example partially silicided CMOS transistor 102 includes a source region 104 and a drain region 106 formed in a doped well region 108 formed over a substrate 110, and a polysilicon gate (or “poly gate”) 112 formed over a gate oxide region 114.
  • the source region 104 and drain region 106 may respectively comprise doped silicon regions, and may be referred to as “active regions” of the CMOS transistor 102.
  • the substrate 110 may comprise a silicon substrate, and may include an epitaxial layer. Sidewall spacers 116, e.g., comprising silicon nitride (SiN) , may be formed on lateral sides of the poly gate 112.
  • the partially silicided CMOS transistor 102 may be formed laterally between or adjacent respective shallow trench insulation (STI) field oxide regions 118.
  • STI shallow trench insulation
  • the source region 104, the drain region 106, and the poly gate 112 are formed as partially silicided elements, and may thus be referred to as partially silicided source region 104, partially silicided drain region 106, and partially silicided poly gate 112.
  • the respective partially silicided elements 104, 106, and 112 include a respective base structure having a top surface including at least one respective silicided region and at least one respective non-silicided region.
  • the partially silicided source region 104 includes a base structure 120 having a top surface (base structure top surface) 122 including at least one silicided region 124 and at least one non-silicided region 126;
  • the partially silicided drain region 106 includes a base structure 130 (comprising doped silicon) having a top surface (base structure top surface) 132 including at least one silicided region 134 and at least one non- silicided region 136;
  • the partially silicided poly gate 112 includes a base structure 140 having a top surface (base structure top surface) 142 including at least one silicided region 144 and at least one non-silicided region 146.
  • the respective base structures 120 and 130 of the partially silicided source region 104 and partially silicided drain region 106 comprise a respective active region, i.e., a respective doped silicon region.
  • the base structure 140 of the partially silicided poly gate 112 comprises a polysilicon element.
  • a “silicided region” of a respective base structure top surface refers to a region of the base structure top surface that is covered by a silicide layer
  • a “non-silicided region” of respective base structure top surface refers to a region of the base structure top surface that is not covered by a silicide layer, e.g., as a result of a silicide layer removal process as disclosed herein.
  • the base structure top surface 122 of the partially silicided source region 104 includes a silicided region 124 covered by a silicide layer area 128 arranged between (laterally along the y-direction) a pair of non- silicided regions 126 not covered by the silicide layer area 128.
  • the base structure top surface 132 of the partially silicided drain region 106 includes a silicided region 134 covered by a silicide layer area 138 arranged between (laterally along the y-direction) a pair of non-silicided regions 136 not covered by the silicide layer area 138.
  • the base structure top surface 142 of the partially silicided poly gate 112 includes a silicided region 144 covered by a silicide layer area 148 arranged between (laterally along the y-direction) a pair of non-silicided regions 146 not covered by the silicide layer area 148.
  • respective silicide layer areas 128, 138, and 148 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
  • the example IC device 100 also includes a dielectric region 160 formed over the partially silicided CMOS transistor 102, and vertically-extending contacts 150, 152, 154 formed in the dielectric region 160 and conductively connected to the silicided regions 124, 134, and 144, respectively, to provide conductive contact to the source region 104, drain region 106, and poly gate 112 of the CMOS transistor 102.
  • the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112 may be formed with (a) silicided regions 124, 134, and 144 near the respective locations of the contacts 150, 152, 154 (e.g., in the y-direction) to provide conductive contact with the contacts 150, 152, 154, and (b) non-silicided regions 126, 136, and 146 at locations further away (e.g., in the y-direction) from the contacts 150, 152, 154.
  • the contacts 150, 152, 154 may be formed offset or spaced apart from each other in the y-direction, e.g., to avoid or reduce possible parasitic interaction between the silicided regions 124, 134, and 144.
  • Figure 1A shows selected elements of the example IC device 100, but does not show certain other elements shown in Figures 1B-1G, for the purposes of simplified illustration.
  • Figure 1A shows the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112, including the silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146, as well as the contacts 150, 152, 154, but does not explicitly show the base structures 120, 130, and 140, the gate oxide region 114, the sidewall spacers 116, the STI field oxide regions 118, the doped well region 108, or the substrate 110.
  • the silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146 may be formed or defined by a process including forming respective silicide layers on the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112, and selectively removing partial areas of the respective silicide layers, wherein the areas in which the respective silicide layers are removed define the non-silicided regions 126, 136, and 146, and the areas in which the respective silicide layers remain intact define the silicided regions 124, 134, and 144 including silicide layer areas 128, 138, and 148, respectively.
  • Such process may be referred to as a partial silicide layer removal process.
  • the silicided regions 124, 134, and 144 of the respective base structure top surfaces 122, 132, and 142 are located coplanar with, or above, the corresponding non-silicided regions 126, 136, and 146, in the z-direction.
  • a vertical height H124 of the silicided region 124 of the top surface 122 of the base structure 120 of source region 104 is located coplanar with, or above, a vertical height H126 of the non- silicided regions 126 of the top surface 122.
  • the vertical height H126 of the non-silicided regions 126 may be less than the vertical height H124 of the silicided region 124 as a result of overetch (during an etch process to remove the removed areas 128’ of the respective silicide layer) extending down into the underlying base structure 120 (doped silicon region).
  • a vertical height H144 of the silicided region 144 of the top surface 142 of the base structure 140 of the poly gate 112 is located coplanar with, or above, a vertical height Hi46 of the non-silicided regions 146 of the top surface 142.
  • the vertical height Hi46 of the non-silicided regions 146 may be less than the vertical height H144 of the silicided region 144 as a result of overetch extending down into the underlying base structure 140 (poly silicon element).
  • a vertical height H134 of the silicided region 134 of the top surface 132 of the base structure 130 of drain region 106 is located coplanar with, or above, a vertical height H136 of the non-silicided regions 136 of the top surface 132.
  • the vertical height Hi 36 of the non-silicided regions 136 may be less than the vertical height H134 of the silicided region 134 as a result of overetch extending down into the underlying base structure 130 (doped drain region).
  • partially silicided elements formed according to conventional techniques typically utilize a silicide blocking layer formed on the base structure, wherein non-blocked regions are silicided and blocked regions are not, resulting in the base structure having a top surface that is lower in the silicided regions than in the non-silicided regions, due to the silicidation process consuming some vertical thickness of the base structure.
  • Figures 2A and 2B show an example IC device 200 including (a) the example partially silicided CMOS transistor structure 102 shown in Figures 1A-1G and (b) an example fully silicided CMOS transistor structure 202.
  • Figure 2A shows a top view of the example IC device 200
  • Figure 2B shows a cross-sectional side view through cut lines 2B-2B shown in Figure 2A.
  • the partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor structure 202 may be formed concurrently, e.g., according to the example process shown in Figures 3 A-3B through Figure 8 discussed below.
  • the example partially silicided CMOS transistor 102 includes (among other elements) the partially silicided source region 104, partially silicided drain region 106, and partially silicided poly gate 112.
  • the partially silicided source region 104 includes base structure 120 (doped silicon source region) having top surface 122 including silicided region 124 located between (in the y-direction) non-silicided regions 126;
  • partially silicided drain region 106 includes base structure 130 (doped silicon drain region) having top surface 132 including silicided region 134 located between (in the y-direction) non-silicided regions 136;
  • partially silicided poly gate 112 includes base structure 140 (polysilicon element) having top surface 142 including silicided region 144 located between (in the y-direction) non- silicided regions 146.
  • vertically-extending contacts 150, 152, and 154 formed in the dielectric region 160 are conductively connected to silicided regions 124, 134, and 144, respectively, to provide conductive contact to the source region 104, drain region 106, and poly gate 112 of the partially silicided CMOS transistor 102.
  • the example fully silicided CMOS transistor 202 includes (among other elements) a fully silicided source region 204, a fully silicided drain region 206, and a fully silicided poly gate 212.
  • the fully silicided source region 204 includes a base structure 220 (a doped silicon source region) having a top surface 222 having a silicide layer 228 extending along a full length (in the y-direction) of the top surface 222.
  • the fully silicided drain region 206 includes a base structure 230 (a doped silicon drain region) having a top surface 232 having a silicide layer 238 extending along a full length (in the y-direction) of the top surface 232.
  • the base structure 220 (doped source region) and base structure 230 (doped drain region) are formed over a doped well region 208 over the substrate 110.
  • the fully silicided poly gate 212 includes a base structure 240 (a polysilicon element) having a top surface 242 having a silicide layer 248 extending along a full length (in the y- direction) of the top surface 242.
  • the base structure 220 (doped silicon source region) and base structure 230 (doped silicon drain region) of the fully silicided CMOS transistor 202, and the base structure 120 (doped silicon source region) and base structure 130 (doped silicon drain region) of the partially silicided CMOS transistor 102 may comprise respective regions of a common substrate 110 (e.g., silicon substrate).
  • the base structure 240 (polysilicon element) of the fully silicided CMOS transistor 202 and the base structure 140 (polysilicon element) of the partially silicided CMOS transistor 102 may comprise portions of a common (same) polysilicon layer, e.g., wherein polysilicon elements 140 and 240 are formed concurrently.
  • Vertically-extending contacts 250, 252, 254 and formed in the dielectric region 160 are conductively connected to the silicide layers 228, 238, and 248, respectively, to provide conductive contact to the source region 204, drain region 206, and poly gate 212 of the fully silicided CMOS transistor 102.
  • Figures 3 A-3B through Figure 8 illustrate an example method of forming the example IC device 200 shown in Figures 2A and 2B, including the partially silicided CMOS transistor structure 102 and the fully silicided CMOS transistor structure 202.
  • the partially silicided CMOS transistor structure 102 is initially formed with fully silicided elements (e.g., the source region 104, drain region 106, and poly gate 112), and a partial silicide removal process is performed to remove partial areas of the respective silicide layers to define the respective silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146 of the source region 104, drain region 106, and poly gate 112.
  • fully silicided elements e.g., the source region 104, drain region 106, and poly gate 112
  • a partial silicide removal process is performed to remove partial areas of the respective silicide layers to define the respective silicided regions 124, 134, and 144
  • FIG. 3A top view
  • Figure 3B cross-sectional side view through line 3B-3B shown in Figure 3 A
  • various structures of the partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor structure 202 are formed over substrate 110.
  • the base structure 120 (doped source region) of the source region 104 and the base structure 130 (doped drain region) of the drain region 106 are formed over the doped well region 108 over the substrate 110, and the poly silicon element 140 of the poly gate 112 is formed over the gate oxide region 114.
  • Respective silicide layers 310, 312, and 314 are formed on the top surfaces 122, 132, and 142 of the base structures 120, 130, and 140, respectively.
  • respective silicide layers 310, 312, and 314 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
  • the base structure 220 (doped source region) of the source region 204 and the base structure 230 (doped drain region) of the drain region 206 are formed over a doped well region 208 over the substrate 110, and the polysilicon element 240 of the poly gate 212 is formed over a gate oxide region 214.
  • the silicide layers 228, 238, and 248 are formed on the top surfaces 222, 232, and 242 of the base structures 220, 230, and 240, respectively.
  • a dielectric region 302 is formed through a combination of deposition and CMP processes over the partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor 202 being formed.
  • the dielectric region 302 may include a base dielectric layer 304 and a sacrificial dielectric layer 306 over the base dielectric layer 304.
  • the base dielectric layer 304 represents a pre-metal dielectric (PMD) region and the sacrificial dielectric layer 306 represents a partial vertical thickness (z-direction) of the dielectric region 302 that is removed by a subsequent planarization process, e.g., as shown in Figure 8, discussed below.
  • PMD pre-metal dielectric
  • the dielectric region 302 is a continuous region of a dielectric material, e.g., deposited in a single deposition process, wherein the dielectric base layer 304 and the sacrificial dielectric layer 306 comprise respective portions (with respective partial thicknesses) of the deposited dielectric material.
  • the base dielectric layer 304 comprises a first dielectric material and the sacrificial dielectric layer 306 comprises a second dielectric material different than the first dielectric material, e.g., wherein the base dielectric layer 304 is deposited by a first deposition process and the sacrificial dielectric layer 306 is deposited by a second deposition process.
  • the base dielectric layer 304 may comprise silicon oxide (SiCh), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), or a combination thereof.
  • the base dielectric layer 304 has a vertical thickness in the range of 0.5-1.0 pm
  • the sacrificial dielectric layer 306 may comprise silicon oxide (SiCh), with a vertical thickness in the range of 500-2000A (0.05-0.2 pm).
  • a first etch process (e.g., pattern and etch process) is performed to concurrently form various openings in the dielectric region 302, including contact openings 402 formed over the fully silicided CMOS transistor 202, contact openings 404 formed over the partially silicided CMOS transistor 102, and tub openings 406 formed over the CMOS transistor 102.
  • Contact openings 402 expose respective areas of silicide layers 228, 238, and 248 of the fully silicided CMOS transistor 202 being formed.
  • Contact openings 404 and tub openings 406 expose respective areas of silicide layers 310, 312, and 314 of the partially silicided CMOS transistor 102 being formed.
  • an optional etch stop layer (not shown), e.g., a silicon nitride layer having a thickness in the range of 250-750A, may be deposited prior to forming dielectric region 302, e.g., for increased control of the etch process.
  • tub openings 406 are substantially wider (e.g., in the x-direction and y- direction) than contact openings 402 and 404.
  • respective contact openings 402 and 404 may have a lateral width (e.g., in the x-direction and y-direction) in the range of 0.1- 0.5pm
  • respective tub openings 406 may have a lateral width (e.g., in the x-direction and y-direction) of at least 1 m, for example in the range of l-100pm.
  • a respective contact opening 404 and at least one tub opening 406 may be formed over the source region 104, drain region 106, and poly gate 112, respectively, to expose respective areas of the silicide layers 310, 312, and 314.
  • contact openings 402 expose respective areas of silicide layers 228, 238, 248 to allow subsequent formation of respective contacts 250, 252, and 254 on the silicide layers 228, 238, 248, to provide low contact resistance to the fully silicided CMOS transistor 202.
  • contact openings 404 expose respective areas of silicide layers 310, 312, and 314 to allow subsequent formation of contacts 150, 152, and 154 on the silicide layers 310, 312, and 314 (or more particularly, on the silicide layer areas 128, 138, and 148 remaining after the partial silicide removal process discussed herein), to provide low contact resistance to the partially silicided CMOS transistor 102.
  • tub openings 406 expose respective areas of silicide layers silicide layers 310, 312, and 314 to be removed by a subsequent etch process, e.g., as shown in Figures 6A- 6B discussed below.
  • a liner 500 e.g., a titanium nitride (TiN) layer
  • TiN titanium nitride
  • the conformal metal 502 comprises tungsten or other conformal metal deposited with a thickness in the range of 1000-5000A, e.g., deposited using a chemical vapor deposition (CVD) process.
  • the deposited conformal metal 502 concurrently (a) fully fills respective contact openings 402 to form contacts 250, 252, 254 conductively connected to silicide layers 228, 238, and 248, (b) fully fills respective contact openings 404 to form contacts 150, 152, and 154 conductively connected to silicide layers 310, 312, and 314 (in particular, in the silicide layer areas 128, 138, and 148 remaining after the partial silicide removal process discussed herein, e.g., as shown in Figure 6A discussed below), and (c) partially fills respective tub openings 406 to form cup-shaped metal structures 504 in respective tub openings 406.
  • the cup-shaped metal structures 504 are formed over respective sacrificial areas 510 of the underlying silicide layers 310, 312, and 314 to be subsequently removed.
  • a second etch process is performed to remove the cup-shaped metal structures 504 in the respective tub openings 406, along with the underlying sacrificial areas 510 of silicide layers 310, 312, and 314, which exposes respective areas 600 of the base structures 120, 130, and 140 under the sacrificial areas 510 of silicide layers 310, 312, and 314.
  • the second etch process includes multiple etches, e.g., using different etch chemistries or process parameters.
  • the second etch process may include (a) a conformal metal etch to remove the cup-shaped metal structures 504 in the respective tub openings 406, followed by (b) a silicide etch to remove the underlying sacrificial areas 510 of silicide layers 310, 312, and 314.
  • the conformal metal etch (e.g. tungsten etch) may comprise an isotropic wet or dry (plasma) etch, and may involve an over-etch to clear the conformal metal 502 in the respective tub openings 406.
  • the silicide etch may comprise a wet etch process, e.g., using diluted hydrofluoric acid (DHF).
  • DHF diluted hydrofluoric acid
  • the exposed areas 600 of the base structures 120, 130, and 140 define the non-silicided regions 126, 136, and 146 of the base structure top surfaces 122, 132, and 142, respectively, of the partially silicided CMOS transistor 102 being formed, and the remaining areas of silicide layers 310, 312, and 314 (i.e., not removed by the second etch process) define the silicided regions 124, 134, and 144 of the base structure top surfaces 122, 132, and 142, respectively, of the partially silicided CMOS transistor 102 being formed.
  • the second etch process may stop at the original level (vertical height) of the respective base structure top surfaces 122, 132, and 142, or may extend down a small distance into the respective base structures 120, 130, and 140 (e.g., less than lOOA) due to over-etch, resulting in the vertical height of the non-silicided regions 126, 136, and 146 being equal to, or less than, the vertical height of the corresponding silicided regions 124, 134, and 144, e.g., as discussed above regarding Figures IE, IF, and 1G.
  • the second etch process removes a respective upper portion 602 of respective contacts 250, 252, 254, 150, 152, and 154, e.g., by etching an upper portion of the conformal metal 502 forming the respective contacts 250, 252, 254, 150, 152, and 154.
  • the removed upper portions 602 have a vertical depth (z-direction) extending partially through a vertical thickness of the sacrificial dielectric layer 306.
  • a dielectric fill material 700 is deposited over the structure and extending down into the tub openings 406 to fill the tub openings 406.
  • the dielectric fill material 700 may comprise silicon oxide (SiCh) and may be deposited by plasma-enhanced chemical vapor deposition (PECVD).
  • a planarization process e.g., an oxide chemical mechanical planarization (oxide CMP) is performed to remove an upper portion of the dielectric fill material 700 and a remaining portion of the sacrificial dielectric layer 306.
  • the planarization may extend down (in the z-direction) to the top of base dielectric layer 304 or may extend a small distance (less than 500A) into the base dielectric layer 304.
  • the resulting structure of the IC device 200 shown in Figure 8 may correspond with the structure shown in Figure 2B discussed above.
  • additional IC structures and devices may be constructed over the example partially silicided CMOS transistor 102 and fully silicided CMOS transistor 202.
  • resistor formed as a partially silicided element, wherein such resistor may be referred to as a partially silicided resistor.
  • Figures 9A and 9B show an example IC device 900 including a partially silicided resistor 902.
  • Figure 9A shows a top view of the example IC device 900
  • Figure 9B shows a cross-sectional side view through cut line 9B-9B shown in Figure 9A.
  • the partially silicided resistor 902 includes a base structure 906 (polysilicon resistive element) having a top surface 908 (polysilicon resistive element top surface 908) including a pair of silicided regions 910 and a non-silicided region 912 between the pair of silicided regions 910 (in the x-direction).
  • the silicided regions 910 may be referred to as resistor heads
  • the non-silicided region 912 may be referred to as the resistor body.
  • the silicided regions 910 (resistor heads) of the polysilicon resistive element top surface 908 are covered by respective silicide layer areas 920, and the non-silicided region 912 (resistor body) of the polysilicon resistive element top surface 908 is not covered by silicide.
  • a vertical height H910 of the silicided region 910 (in the z-direction) from an arbitrary reference plane, Z re f, is equal to, or greater than, a vertical height H912 of the non-silicided region 912.
  • respective contacts 930 formed in a dielectric region 932 (e.g., a PMD region) over the partially silicided resistor 902 are conductively connected to the respective silicided regions 910 (resistor heads), to provide electrical contact to the polysilicon resistive element 906.
  • Figures 10A-10B through Figures 15A-15B illustrate an example method of forming the example IC device 900 including the partially silicided resistor 902 shown in Figures 9A and 9B.
  • the base structure 906 (polysilicon resistive element) is formed over a substrate 1002, e.g., an STI field oxide region or other dielectric region.
  • the polysilicon resistive element 906 may be formed by depositing, patterning and etching a polysilicon layer, e.g., concurrent with formation of poly gates of respective CMOS transistors formed in the example IC device 900.
  • a silicide layer 1100 is formed on the top surface 908 of the polysilicon resistive element 906.
  • the silicide layer 1100 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
  • a dielectric region 1200 is formed over the structure through a combination of deposition and CMP processes.
  • the dielectric region 1200 may include a base dielectric layer 1202 and a sacrificial dielectric layer 1204 over the base dielectric layer 1202.
  • the base dielectric layer 1202 represents a pre-metal dielectric (PMD) region and the sacrificial dielectric layer 1204 represents a partial vertical thickness (z-direction) of the dielectric region 1200 that is removed by a subsequent planarization process, e.g., as shown in Figure 15, discussed below.
  • PMD pre-metal dielectric
  • sacrificial dielectric layer 1204 represents a partial vertical thickness (z-direction) of the dielectric region 1200 that is removed by a subsequent planarization process, e.g., as shown in Figure 15, discussed below.
  • the dielectric region 1200 may comprise a continuous region of a dielectric material, wherein the dielectric base layer 1202 and sacrificial dielectric layer 1204 comprise respective partial thicknesses of the deposited dielectric material, or alternatively, the base dielectric layer 1202 and sacrificial dielectric layer 1204 may comprise different dielectric materials deposited by respective deposition processes.
  • the base dielectric layer 1202 may comprise SiCh, PSG, BPSG, or a combination thereof.
  • the base dielectric layer 1202 has a vertical thickness in the range of 0.5-1.0 pm
  • the sacrificial dielectric layer 1204 may comprise SiO2, with a vertical thickness in the range of 500-2000A (0.05-0.2 pm).
  • a first etch process (e.g., pattern and etch process) is performed to concurrently form contact openings 1210 and a tub opening 1212 over the polysilicon resistive element 906. Contact openings 1210 and tub opening 1212 expose respective areas of the silicide layer 1100.
  • tub openings 1212 are substantially wider (e.g., in the x-direction and y- direction) than contact openings 1210.
  • respective contact openings 1210 may have a lateral width (e.g., in the x-direction and y-direction) in the range of 0.1-0.5pm
  • respective tub openings 1212 may have a lateral width (e.g., in the x-direction and y-direction) of at least 1pm, for example in the range of l-100pm.
  • a liner 1300 e.g., a titanium nitride (TiN) layer
  • TiN titanium nitride
  • the conformal metal 1302 comprises tungsten or other conformal metal deposited with a thickness in the range of 1000-5000 A, e.g., using a chemical vapor deposition (CVD) process.
  • the deposited conformal metal 1302 concurrently (a) fully fills respective contact openings 1210 to form contacts 930 conductively connected to silicide layer 1100 (in particular, in the silicide layer areas 920 remaining after the partial silicide removal process discussed herein, e.g., as shown in Figures 14A-14B discussed below), and (b) partially fills tub opening 1212 to form a cup-shaped metal structure 1306 in the tub opening 1212.
  • the cupshaped metal structure 1306 is formed over a sacrificial area 1310 of the underlying silicide layer 1100 to be subsequently removed.
  • a second etch process is performed to remove the cup- shaped metal structure 1306 in the tub opening 1212, along with the underlying sacrificial area 1310 of the silicide layer 1100, which exposes an area 1400 of the base structure (polysilicon resistive element) 906 under the sacrificial area 1310 of silicide layer 1100.
  • the second etch process includes multiple etches, e.g., using different etch chemistries or process parameters.
  • the second etch process may include (a) a conformal metal etch to remove the cup-shaped metal structure 1306 in the tub opening 1212, followed by (b) a silicide etch to remove the underlying sacrificial area 1310 of silicide layer 1100.
  • the conformal metal etch e.g. tungsten etch
  • the silicide etch may comprise a wet etch process, e.g., using diluted hydrofluoric acid (DHF).
  • the second etch process may stop at the original level (vertical height) of the base structure top surface 908, or may extend down a small distance into the base structure (polysilicon resistive element) 906 (e.g., less than 100A) due to over etch, resulting in the vertical height of the non-silicided region 912 (resistor body) being equal to, or less than, the vertical height of the silicided regions 910 (resistor heads).
  • an optional implant may be applied to the exposed area 1400 of the polysilicon resistive element 906, using the sacrificial dielectric layer 1204 as a hard mask to block the implant from unwanted areas (i.e., silicided regions 910), to modify the sheet resistance value of the resulting partially silicide resistor 902.
  • the exposed area 1400 of the polysilicon resistive element 906 defines the non-silicided region 912 of the base structure top surface 908 of the partially silicided resistor 902, and the remaining areas of the silicide layer 1100 (i.e., not removed by the second etch process) define the silicided regions 910 of the base structure top surface 908 of the partially silicided resistor 902.
  • a dielectric fill material 1500 is deposited over the structure and extending down into the tub opening 1212 to fill the tub opening 1212.
  • the dielectric fill material 1500 may comprise silicon oxide (SiCh), and may be deposited by plasma-enhanced chemical vapor deposition (PECVD).
  • a planarization process e.g., an oxide CMP process, is performed to remove a remaining portion of the sacrificial dielectric layer 1204.
  • the planarization may extend down (in the z-direction) to the top of base dielectric layer 1202 or may extend a small distance (e.g., less than 500A) into the base dielectric layer 1202.
  • the resulting structure of the IC device 900 shown in Figures 15A- 15B may correspond with the structure shown in Figures 9A-9B discussed above.
  • additional IC structures and devices may be constructed over the example partially silicided resistor 902.

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Abstract

A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

Description

FORMING A PARTIALLY SILICIDED ELEMENT
RELATED APPLICATION
This application claims priority to commonly owned United States Provisional Patent Application No. 63/406,356 filed September 14, 2022, the entire contents of which are hereby incorporated by reference for all purposes.
TECHNICAL FIELD
The present disclosure relates to integrated circuit (IC) devices, and more particularly to partially silicided elements and methods of forming partially silicided elements in IC devices.
BACKGROUND
Many IC devices include silicided elements, for example certain complementary metal oxide semiconductor (CMOS) transistors formed with a silicided poly gate and silicided source and drain region. A silicided element includes a metal silicide layer formed on a base structure, e.g., a polysilicon element or an active region, wherein the silicide layer exhibits increased conductance, e.g., to provide improved electrical contact with the underlying base structure. CMOS transistor structures are often formed as silicided elements, or example CMOS transistor gates (“poly gates”) and CMOS transistor active regions (e.g., source and drain regions).
For some devices, silicidation may result in ineffective or undesirable performance. For example, CMOS transistors used in ESD (electrostatic discharge) circuits are typically not silicided, as silicidation may restrict high voltage capability. As another example, polysilicon resistors (“poly resistors”) are typically formed without silicidation, in order to achieve desired sheet resistance values. However, it is often beneficial to silicide the respective contact areas for such devices, e.g., high voltage CMOS transistors and poly resistors, to improve electrical contact to the relevant device components. Thus, certain IC elements may be formed partially silicided, elements, wherein a “partially silicided” element refers to a base structure (e.g., a polysilicon structure or a doped silicon region) having a top surface including at least one silicided region (having a silicide layer formed thereon) and at least one non-silicided region (without a silicide layer formed thereon). As used herein, a “partially silicided” device, e.g., a partially silicided CMOS transistor or a partially silicided resistor, refers to a device including at least one partially silicided element. Partially silicided elements are conventionally formed by blocking the formation of silicide on a partial surface area of the base structure top surface, typically with a thin layer of silicon oxide referred to as a silicide block layer or resistor protection oxide (RPO). In a typical silicide blocking process, a photo mask is used to etch away selected area of the silicide block layer, allowing silicidation of the exposed areas of the underlying base structure top surface, while preventing silicidation of areas of the base structure top surface covered by the silicide block layer. However, this silicide blocking process requires an additional photomask process, which adds significant cost to the relevant manufacturing process.
There is a need for improved methods of forming partially silicided elements.
SUMMARY
The present disclosure provides devices including example partially silicided elements and example methods of forming devices including partially silicided elements. Example types of partially silicided elements disclosed herein include (a) elements of a CMOS transistor (e.g., a partially silicided poly gate, a partially silicided source region, and a partially silicided drain region), and (b) a partially silicided resistive element of an integrated resistor. In some examples, partially silicided elements may be formed concurrently with respective fully silicided elements. For example, a partially silicided CMOS transistor may be formed concurrently with a fully silicided CMOS transistor.
Some examples provide a process of forming a partially silicided element that eliminates the need for a silicide block layer (or RPO) used in conventional processes, which may reduce manufacturing costs. In some examples a partially silicided element may be formed without adding any mask layers to the background or baseline manufacturing process of the relevant IC device.
One aspect provides a method of forming a partially silicided element. A silicided structure is formed, including a silicide layer on a base structure. A dielectric region is formed over the silicided structure. A first etch process is performed to form a contact opening and a tub opening in the dielectric region, the contact opening exposing a first area of the silicide layer, and the tub opening exposing a second area of the silicide layer. A conformal metal is deposited over the dielectric region, the deposited conformal metal (a) filling the contact opening to define a contact conductively connected to the first area of the silicide layer and (b) forming a cup-shaped metal structure in the tub opening. A second etch process is performed to remove the cup-shaped metal structure in the tub opening, to remove the second area of the silicide layer, and to expose an area of the base structure under the second area of the silicide layer, wherein the first area of the silicide layer remains intact after the second etch process. The base structure with the intact first area of the silicide layer and the removed second area of the silicide layer defines the partially silicided element.
In some examples, the base structure comprises a polysilicon element. For example, the base structure may comprise a polysilicon gate of a transistor, or a polysilicon resistor element.
In other examples, the base structure comprises an active region of a transistor, e.g., a doped source region or a doped drain region.
In some examples, the conformal metal comprises tungsten.
In some examples, the method includes filling the tub opening with a dielectric fill material after the second etch process.
In some examples, the second etch process includes (a) a conformal metal etch to remove the cup-shaped metal structure from the tub opening and (b) a silicide etch to remove the second area of the silicide layer.
In some examples, the dielectric region formed over the silicided structure includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch process removes an upper portion of the contact having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer, and the method includes filling the tub opening with a dielectric fill material after the second etch process, and performing a planarization process to remove an upper portion of the dielectric fill material and a remaining portion of the sacrificial dielectric layer.
In some examples, the dielectric base layer and the sacrificial dielectric layer comprise respective portions of a dielectric material deposited over the silicided structure.
In other examples, the base dielectric layer comprises a first dielectric material and the sacrificial dielectric layer comprises a second dielectric material different than the first dielectric material.
In some examples, a lateral width of the tub opening is greater than a lateral width of the contact opening.
In some examples, the contact opening has a lateral width in the range of 0.1 -0.5 pm, and the tub opening has a lateral width in the range of l-100pm. One aspect provides a device including a partially silicided element including a base structure having a top surface including a silicided region and a non-silicided region. The silicided region of the top surface of the base structure is covered by a silicide layer, and the non-silicided region of the top surface of the base structure is not covered by the silicide layer. A vertical height of the silicided region of the top surface of the base structure is equal to or greater than a vertical height of the non-silicided region of the top surface of the base structure.
In some examples, the base structure comprises a polysilicon element. For example, the base structure may comprise a polysilicon gate of a transistor, or a polysilicon resistor element.
In other examples, the base structure comprises an active region of a transistor, e.g., a doped source region or a doped drain region.
In some examples, the device further includes a fully silicided element including a second base structure having a second top surface fully covered by a second silicide layer, wherein the base structure of the partially silicided element and the second base structure of the fully silicided element comprise respective portions of a common material layer.
One aspect provides a method of forming an integrated circuit (IC) device including (a) a partially silicided element and (b) a fully silicided element. A first silicided structure and a second silicided structure are formed, the first silicided structure including a first silicide layer formed on a first base structure, and the second silicided structure including a second silicide layer formed on a second base structure. A dielectric region is formed over the first and second silicided structures. A first etch process is performed to form a first contact opening, a second contact opening, and a tub opening in the dielectric region, wherein the first contact opening exposes the first silicide layer, the second contact opening exposes a first area of the second silicide layer, and the tub opening exposes a second area of the second silicide layer. A conformal metal is deposited over the dielectric region, the deposited conformal metal layer (a) filling the first contact opening to define a first contact conductively connected to the first silicide layer, (b) filling the second contact opening to define a second contact conductively connected to the first area of the second silicide layer, and (c) forming a cup-shaped metal structure in the tub opening. A second etch process is performed to remove the cup-shaped metal structure in the tub opening, to remove the second area of the second silicide layer, and to expose an area of the second base structure under the second area of the second silicide layer, wherein the first silicide layer and the first area of the second silicide layer remain intact after the second etch process. The tub opening is filled with a dielectric fill material. The first base structure with the intact first silicide layer defines the fully silicided element, and the second base structure with the intact first area of the second silicide layer and the removed second area of the second silicide layer defines the partially silicided element.
In some examples, the dielectric region formed over the first and second silicided structures includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch process removes an upper portion of the first contact and an upper portion of the second contact respectively having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer; and the method includes, after filling the tub opening with the dielectric fill material, performing a planarization process to remove remaining portions of the sacrificial dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
Example aspects of the present disclosure are described below in conjunction with the figures, in which:
Figures 1A-1G show an example IC device including a partially silicided CMOS transistor, including a partially silicided poly gate and partially silicided source and drain regions;
Figures 2A and 2B show an example IC device including (a) the example partially silicided CMOS transistor structure shown in Figures 1 A-1G and (b) an example fully silicided CMOS transistor structure;
Figures 3 A-3B through Figure 8 illustrate an example method of forming the example IC device (including the partially silicided CMOS transistor structure and fully silicided CMOS transistor structure) shown in Figures 2A and 2B;
Figures 9A and 9B show an example partially silicided resistor, including a partially silicided resistive element; and
Figures 10A-10B through Figures 15A-15B illustrate an example method of forming the example partially silicided resistor shown in Figures 9A and 9B.
It should be understood the reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown. DETAILED DESCRIPTION
The present disclosure describes example partially silicided elements and example methods of forming partially silicided elements. Respective elements of different types of IC structures may be formed as partially silicided elements. For example, as discussed below regarding Figures 1A-1G through Figure 8, elements of a CMOS transistor, for example a poly gate, a source region, and a drain region, may be formed as partially silicided elements, wherein such a CMOS transistor structure may be referred to as a partially silicided CMOS transistor. In other examples, e.g., as discussed below regarding Figures 9A-9B through Figures 15A- 15B, a resistor may include a resistive element formed as a partially silicided element, wherein such resistor may be referred to as a partially silicided resistor. As discussed below, in some examples, partially silicided CMOS transistors or partially silicided resistors may be formed concurrently with fully silicided elements (e.g., fully silicided CMOS transistors) in respective IC devices.
Figures 1 A-1G show an example IC device 100 including an example partially silicided CMOS transistor 102, according to one example. In particular, Figure 1 A shows a top view of the example IC device 100, and Figures IB, IC, ID, IE, IF, and 1G show cross-sectional side views through respective cut lines 1B-1B, 1C-1C, ID-ID, 1E-1E, 1F-1F, and 1G-1G shown in Figure 1A.
As shown, the example partially silicided CMOS transistor 102 includes a source region 104 and a drain region 106 formed in a doped well region 108 formed over a substrate 110, and a polysilicon gate (or “poly gate”) 112 formed over a gate oxide region 114. The source region 104 and drain region 106 may respectively comprise doped silicon regions, and may be referred to as “active regions” of the CMOS transistor 102. The substrate 110 may comprise a silicon substrate, and may include an epitaxial layer. Sidewall spacers 116, e.g., comprising silicon nitride (SiN) , may be formed on lateral sides of the poly gate 112. The partially silicided CMOS transistor 102 may be formed laterally between or adjacent respective shallow trench insulation (STI) field oxide regions 118.
In this example, the source region 104, the drain region 106, and the poly gate 112 are formed as partially silicided elements, and may thus be referred to as partially silicided source region 104, partially silicided drain region 106, and partially silicided poly gate 112. The respective partially silicided elements 104, 106, and 112 include a respective base structure having a top surface including at least one respective silicided region and at least one respective non-silicided region. In the illustrated example, the partially silicided source region 104 includes a base structure 120 having a top surface (base structure top surface) 122 including at least one silicided region 124 and at least one non-silicided region 126; the partially silicided drain region 106 includes a base structure 130 (comprising doped silicon) having a top surface (base structure top surface) 132 including at least one silicided region 134 and at least one non- silicided region 136; and the partially silicided poly gate 112 includes a base structure 140 having a top surface (base structure top surface) 142 including at least one silicided region 144 and at least one non-silicided region 146. The respective base structures 120 and 130 of the partially silicided source region 104 and partially silicided drain region 106 comprise a respective active region, i.e., a respective doped silicon region. The base structure 140 of the partially silicided poly gate 112 comprises a polysilicon element.
As used herein, a “silicided region” of a respective base structure top surface refers to a region of the base structure top surface that is covered by a silicide layer, and a “non-silicided region” of respective base structure top surface refers to a region of the base structure top surface that is not covered by a silicide layer, e.g., as a result of a silicide layer removal process as disclosed herein. Thus, for example, as shown in Figures 1A-1G, the base structure top surface 122 of the partially silicided source region 104 includes a silicided region 124 covered by a silicide layer area 128 arranged between (laterally along the y-direction) a pair of non- silicided regions 126 not covered by the silicide layer area 128. Similarly, the base structure top surface 132 of the partially silicided drain region 106 includes a silicided region 134 covered by a silicide layer area 138 arranged between (laterally along the y-direction) a pair of non-silicided regions 136 not covered by the silicide layer area 138. Similarly, the base structure top surface 142 of the partially silicided poly gate 112 includes a silicided region 144 covered by a silicide layer area 148 arranged between (laterally along the y-direction) a pair of non-silicided regions 146 not covered by the silicide layer area 148.
In some examples, respective silicide layer areas 128, 138, and 148 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
The example IC device 100 also includes a dielectric region 160 formed over the partially silicided CMOS transistor 102, and vertically-extending contacts 150, 152, 154 formed in the dielectric region 160 and conductively connected to the silicided regions 124, 134, and 144, respectively, to provide conductive contact to the source region 104, drain region 106, and poly gate 112 of the CMOS transistor 102. Thus, as shown in Figures 1A through 1G, the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112 may be formed with (a) silicided regions 124, 134, and 144 near the respective locations of the contacts 150, 152, 154 (e.g., in the y-direction) to provide conductive contact with the contacts 150, 152, 154, and (b) non-silicided regions 126, 136, and 146 at locations further away (e.g., in the y-direction) from the contacts 150, 152, 154. As shown in Figure 1A, in some examples the contacts 150, 152, 154 may be formed offset or spaced apart from each other in the y-direction, e.g., to avoid or reduce possible parasitic interaction between the silicided regions 124, 134, and 144.
It should be noted that the top view of Figure 1A shows selected elements of the example IC device 100, but does not show certain other elements shown in Figures 1B-1G, for the purposes of simplified illustration. For example, Figure 1A shows the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112, including the silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146, as well as the contacts 150, 152, 154, but does not explicitly show the base structures 120, 130, and 140, the gate oxide region 114, the sidewall spacers 116, the STI field oxide regions 118, the doped well region 108, or the substrate 110.
As discussed below, e.g., with reference to Figures 3A-3B through Figure 8, the silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146 may be formed or defined by a process including forming respective silicide layers on the base structure top surfaces 122, 132, and 142 of the source region 104, drain region 106, and poly gate 112, and selectively removing partial areas of the respective silicide layers, wherein the areas in which the respective silicide layers are removed define the non-silicided regions 126, 136, and 146, and the areas in which the respective silicide layers remain intact define the silicided regions 124, 134, and 144 including silicide layer areas 128, 138, and 148, respectively. Such process may be referred to as a partial silicide layer removal process.
In some examples, as a result of a partial silicide layer removal process (e.g., the process shown in Figures 3A-3B through Figure 8, discussed below), the silicided regions 124, 134, and 144 of the respective base structure top surfaces 122, 132, and 142 are located coplanar with, or above, the corresponding non-silicided regions 126, 136, and 146, in the z-direction. For example, as shown in Figure IE, a vertical height H124 of the silicided region 124 of the top surface 122 of the base structure 120 of source region 104 (measured from an arbitrary reference plane ZRef) is located coplanar with, or above, a vertical height H126 of the non- silicided regions 126 of the top surface 122. In some examples, the vertical height H126 of the non-silicided regions 126 may be less than the vertical height H124 of the silicided region 124 as a result of overetch (during an etch process to remove the removed areas 128’ of the respective silicide layer) extending down into the underlying base structure 120 (doped silicon region).
Also, as shown in Figure IF, a vertical height H144 of the silicided region 144 of the top surface 142 of the base structure 140 of the poly gate 112 is located coplanar with, or above, a vertical height Hi46 of the non-silicided regions 146 of the top surface 142. In some examples, the vertical height Hi46 of the non-silicided regions 146 may be less than the vertical height H144 of the silicided region 144 as a result of overetch extending down into the underlying base structure 140 (poly silicon element).
Also, as shown in Figure 1G, a vertical height H134 of the silicided region 134 of the top surface 132 of the base structure 130 of drain region 106 is located coplanar with, or above, a vertical height H136 of the non-silicided regions 136 of the top surface 132. In some examples, the vertical height Hi 36 of the non-silicided regions 136 may be less than the vertical height H134 of the silicided region 134 as a result of overetch extending down into the underlying base structure 130 (doped drain region).
In contrast to the partially silicided CMOS transistor 102 disclosed herein, partially silicided elements formed according to conventional techniques typically utilize a silicide blocking layer formed on the base structure, wherein non-blocked regions are silicided and blocked regions are not, resulting in the base structure having a top surface that is lower in the silicided regions than in the non-silicided regions, due to the silicidation process consuming some vertical thickness of the base structure.
Figures 2A and 2B show an example IC device 200 including (a) the example partially silicided CMOS transistor structure 102 shown in Figures 1A-1G and (b) an example fully silicided CMOS transistor structure 202. Figure 2A shows a top view of the example IC device 200, and Figure 2B shows a cross-sectional side view through cut lines 2B-2B shown in Figure 2A. The partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor structure 202 may be formed concurrently, e.g., according to the example process shown in Figures 3 A-3B through Figure 8 discussed below. As discussed above, the example partially silicided CMOS transistor 102 includes (among other elements) the partially silicided source region 104, partially silicided drain region 106, and partially silicided poly gate 112. The partially silicided source region 104 includes base structure 120 (doped silicon source region) having top surface 122 including silicided region 124 located between (in the y-direction) non-silicided regions 126; partially silicided drain region 106 includes base structure 130 (doped silicon drain region) having top surface 132 including silicided region 134 located between (in the y-direction) non-silicided regions 136; and partially silicided poly gate 112 includes base structure 140 (polysilicon element) having top surface 142 including silicided region 144 located between (in the y-direction) non- silicided regions 146. As shown in Figure 2A, vertically-extending contacts 150, 152, and 154 formed in the dielectric region 160 are conductively connected to silicided regions 124, 134, and 144, respectively, to provide conductive contact to the source region 104, drain region 106, and poly gate 112 of the partially silicided CMOS transistor 102.
The example fully silicided CMOS transistor 202 includes (among other elements) a fully silicided source region 204, a fully silicided drain region 206, and a fully silicided poly gate 212. The fully silicided source region 204 includes a base structure 220 (a doped silicon source region) having a top surface 222 having a silicide layer 228 extending along a full length (in the y-direction) of the top surface 222. The fully silicided drain region 206 includes a base structure 230 (a doped silicon drain region) having a top surface 232 having a silicide layer 238 extending along a full length (in the y-direction) of the top surface 232. The base structure 220 (doped source region) and base structure 230 (doped drain region) are formed over a doped well region 208 over the substrate 110.
The fully silicided poly gate 212 includes a base structure 240 (a polysilicon element) having a top surface 242 having a silicide layer 248 extending along a full length (in the y- direction) of the top surface 242. The base structure 220 (doped silicon source region) and base structure 230 (doped silicon drain region) of the fully silicided CMOS transistor 202, and the base structure 120 (doped silicon source region) and base structure 130 (doped silicon drain region) of the partially silicided CMOS transistor 102 may comprise respective regions of a common substrate 110 (e.g., silicon substrate). Also, the base structure 240 (polysilicon element) of the fully silicided CMOS transistor 202 and the base structure 140 (polysilicon element) of the partially silicided CMOS transistor 102 may comprise portions of a common (same) polysilicon layer, e.g., wherein polysilicon elements 140 and 240 are formed concurrently.
Vertically-extending contacts 250, 252, 254 and formed in the dielectric region 160 are conductively connected to the silicide layers 228, 238, and 248, respectively, to provide conductive contact to the source region 204, drain region 206, and poly gate 212 of the fully silicided CMOS transistor 102.
Figures 3 A-3B through Figure 8 illustrate an example method of forming the example IC device 200 shown in Figures 2A and 2B, including the partially silicided CMOS transistor structure 102 and the fully silicided CMOS transistor structure 202. As explained below, the partially silicided CMOS transistor structure 102 is initially formed with fully silicided elements (e.g., the source region 104, drain region 106, and poly gate 112), and a partial silicide removal process is performed to remove partial areas of the respective silicide layers to define the respective silicided regions 124, 134, and 144 and non-silicided regions 126, 136, and 146 of the source region 104, drain region 106, and poly gate 112.
As shown in Figure 3A (top view) and Figure 3B (cross-sectional side view through line 3B-3B shown in Figure 3 A), various structures of the partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor structure 202 are formed over substrate 110. For example, for the partially silicided CMOS transistor 102 being formed, the base structure 120 (doped source region) of the source region 104 and the base structure 130 (doped drain region) of the drain region 106 are formed over the doped well region 108 over the substrate 110, and the poly silicon element 140 of the poly gate 112 is formed over the gate oxide region 114. Respective silicide layers 310, 312, and 314 are formed on the top surfaces 122, 132, and 142 of the base structures 120, 130, and 140, respectively. In some examples, respective silicide layers 310, 312, and 314 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
For the fully silicided CMOS transistor 202 being formed, the base structure 220 (doped source region) of the source region 204 and the base structure 230 (doped drain region) of the drain region 206 are formed over a doped well region 208 over the substrate 110, and the polysilicon element 240 of the poly gate 212 is formed over a gate oxide region 214. The silicide layers 228, 238, and 248 are formed on the top surfaces 222, 232, and 242 of the base structures 220, 230, and 240, respectively. A dielectric region 302 is formed through a combination of deposition and CMP processes over the partially silicided CMOS transistor structure 102 and fully silicided CMOS transistor 202 being formed. The dielectric region 302 may include a base dielectric layer 304 and a sacrificial dielectric layer 306 over the base dielectric layer 304. In some examples, the base dielectric layer 304 represents a pre-metal dielectric (PMD) region and the sacrificial dielectric layer 306 represents a partial vertical thickness (z-direction) of the dielectric region 302 that is removed by a subsequent planarization process, e.g., as shown in Figure 8, discussed below. In some examples, the dielectric region 302 is a continuous region of a dielectric material, e.g., deposited in a single deposition process, wherein the dielectric base layer 304 and the sacrificial dielectric layer 306 comprise respective portions (with respective partial thicknesses) of the deposited dielectric material. In other examples, the base dielectric layer 304 comprises a first dielectric material and the sacrificial dielectric layer 306 comprises a second dielectric material different than the first dielectric material, e.g., wherein the base dielectric layer 304 is deposited by a first deposition process and the sacrificial dielectric layer 306 is deposited by a second deposition process.
In some examples, the base dielectric layer 304 may comprise silicon oxide (SiCh), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), or a combination thereof. In some examples, the base dielectric layer 304 has a vertical thickness in the range of 0.5-1.0 pm, and the sacrificial dielectric layer 306 may comprise silicon oxide (SiCh), with a vertical thickness in the range of 500-2000A (0.05-0.2 pm).
As shown in Figure 4A (top view) and Figure 4B (cross-sectional side view through line 4B-4B shown in Figure 4A), a first etch process (e.g., pattern and etch process) is performed to concurrently form various openings in the dielectric region 302, including contact openings 402 formed over the fully silicided CMOS transistor 202, contact openings 404 formed over the partially silicided CMOS transistor 102, and tub openings 406 formed over the CMOS transistor 102. Contact openings 402 expose respective areas of silicide layers 228, 238, and 248 of the fully silicided CMOS transistor 202 being formed. Contact openings 404 and tub openings 406 expose respective areas of silicide layers 310, 312, and 314 of the partially silicided CMOS transistor 102 being formed. In some examples, an optional etch stop layer (not shown), e.g., a silicon nitride layer having a thickness in the range of 250-750A, may be deposited prior to forming dielectric region 302, e.g., for increased control of the etch process. As shown, tub openings 406 are substantially wider (e.g., in the x-direction and y- direction) than contact openings 402 and 404. For example, respective contact openings 402 and 404 may have a lateral width (e.g., in the x-direction and y-direction) in the range of 0.1- 0.5pm, whereas respective tub openings 406 may have a lateral width (e.g., in the x-direction and y-direction) of at least 1 m, for example in the range of l-100pm.
As shown in Figure 4A, a respective contact opening 404 and at least one tub opening 406 (in the illustrated example, a pair of tub openings 406 on opposite sides of the respective contact opening 404) may be formed over the source region 104, drain region 106, and poly gate 112, respectively, to expose respective areas of the silicide layers 310, 312, and 314.
As explained below, contact openings 402 expose respective areas of silicide layers 228, 238, 248 to allow subsequent formation of respective contacts 250, 252, and 254 on the silicide layers 228, 238, 248, to provide low contact resistance to the fully silicided CMOS transistor 202. Similarly, contact openings 404 expose respective areas of silicide layers 310, 312, and 314 to allow subsequent formation of contacts 150, 152, and 154 on the silicide layers 310, 312, and 314 (or more particularly, on the silicide layer areas 128, 138, and 148 remaining after the partial silicide removal process discussed herein), to provide low contact resistance to the partially silicided CMOS transistor 102.
In contrast, tub openings 406 expose respective areas of silicide layers silicide layers 310, 312, and 314 to be removed by a subsequent etch process, e.g., as shown in Figures 6A- 6B discussed below.
As shown in Figure 5A (top view) and Figure 5B (cross-sectional side view through line 5B-5B shown in Figure 5A), a liner 500 (e.g., a titanium nitride (TiN) layer) is deposited over the dielectric region 302 and extending down into contact openings 402 and 404 and tub openings 406, followed by deposition of a conformal metal 502 over the liner 500 and extending down into contact openings 402 and 404 and tub openings 406. In some examples, the conformal metal 502 comprises tungsten or other conformal metal deposited with a thickness in the range of 1000-5000A, e.g., deposited using a chemical vapor deposition (CVD) process.
The deposited conformal metal 502 concurrently (a) fully fills respective contact openings 402 to form contacts 250, 252, 254 conductively connected to silicide layers 228, 238, and 248, (b) fully fills respective contact openings 404 to form contacts 150, 152, and 154 conductively connected to silicide layers 310, 312, and 314 (in particular, in the silicide layer areas 128, 138, and 148 remaining after the partial silicide removal process discussed herein, e.g., as shown in Figure 6A discussed below), and (c) partially fills respective tub openings 406 to form cup-shaped metal structures 504 in respective tub openings 406. The cup-shaped metal structures 504 are formed over respective sacrificial areas 510 of the underlying silicide layers 310, 312, and 314 to be subsequently removed.
As shown in Figure 6A (top view), Figure 6B (cross-sectional side view through line 6B-6B shown in Figure 6A), and Figure 6C (cross-sectional side view through the (serpentine) line 6C-6C shown in Figure 6A), a second etch process is performed to remove the cup-shaped metal structures 504 in the respective tub openings 406, along with the underlying sacrificial areas 510 of silicide layers 310, 312, and 314, which exposes respective areas 600 of the base structures 120, 130, and 140 under the sacrificial areas 510 of silicide layers 310, 312, and 314.
In some examples, the second etch process includes multiple etches, e.g., using different etch chemistries or process parameters. For example, the second etch process may include (a) a conformal metal etch to remove the cup-shaped metal structures 504 in the respective tub openings 406, followed by (b) a silicide etch to remove the underlying sacrificial areas 510 of silicide layers 310, 312, and 314. The conformal metal etch (e.g. tungsten etch) may comprise an isotropic wet or dry (plasma) etch, and may involve an over-etch to clear the conformal metal 502 in the respective tub openings 406. The silicide etch may comprise a wet etch process, e.g., using diluted hydrofluoric acid (DHF).
The exposed areas 600 of the base structures 120, 130, and 140 define the non-silicided regions 126, 136, and 146 of the base structure top surfaces 122, 132, and 142, respectively, of the partially silicided CMOS transistor 102 being formed, and the remaining areas of silicide layers 310, 312, and 314 (i.e., not removed by the second etch process) define the silicided regions 124, 134, and 144 of the base structure top surfaces 122, 132, and 142, respectively, of the partially silicided CMOS transistor 102 being formed.
The second etch process may stop at the original level (vertical height) of the respective base structure top surfaces 122, 132, and 142, or may extend down a small distance into the respective base structures 120, 130, and 140 (e.g., less than lOOA) due to over-etch, resulting in the vertical height of the non-silicided regions 126, 136, and 146 being equal to, or less than, the vertical height of the corresponding silicided regions 124, 134, and 144, e.g., as discussed above regarding Figures IE, IF, and 1G. As shown in Figure 6C, the second etch process removes a respective upper portion 602 of respective contacts 250, 252, 254, 150, 152, and 154, e.g., by etching an upper portion of the conformal metal 502 forming the respective contacts 250, 252, 254, 150, 152, and 154. The removed upper portions 602 have a vertical depth (z-direction) extending partially through a vertical thickness of the sacrificial dielectric layer 306.
As shown in Figure 7A (top view) and Figure 7B (cross-sectional side view through line 7B-7B shown in Figure 7A), a dielectric fill material 700 is deposited over the structure and extending down into the tub openings 406 to fill the tub openings 406. In some examples, the dielectric fill material 700 may comprise silicon oxide (SiCh) and may be deposited by plasma-enhanced chemical vapor deposition (PECVD).
As shown in Figure 8, which is a side cross-sectional side corresponding with the crosssection view shown in Figure 7B, after filling the tub openings 406 with the dielectric fill material 700, a planarization process, e.g., an oxide chemical mechanical planarization (oxide CMP), is performed to remove an upper portion of the dielectric fill material 700 and a remaining portion of the sacrificial dielectric layer 306. The planarization may extend down (in the z-direction) to the top of base dielectric layer 304 or may extend a small distance (less than 500A) into the base dielectric layer 304. The resulting structure of the IC device 200 shown in Figure 8 may correspond with the structure shown in Figure 2B discussed above. After the planarization process, additional IC structures and devices may be constructed over the example partially silicided CMOS transistor 102 and fully silicided CMOS transistor 202.
As discussed above, other examples provide a resistor formed as a partially silicided element, wherein such resistor may be referred to as a partially silicided resistor.
For example, Figures 9A and 9B show an example IC device 900 including a partially silicided resistor 902. In particular, Figure 9A shows a top view of the example IC device 900, and Figure 9B shows a cross-sectional side view through cut line 9B-9B shown in Figure 9A. As shown, the partially silicided resistor 902 includes a base structure 906 (polysilicon resistive element) having a top surface 908 (polysilicon resistive element top surface 908) including a pair of silicided regions 910 and a non-silicided region 912 between the pair of silicided regions 910 (in the x-direction). The silicided regions 910 may be referred to as resistor heads, and the non-silicided region 912 may be referred to as the resistor body.
The silicided regions 910 (resistor heads) of the polysilicon resistive element top surface 908 are covered by respective silicide layer areas 920, and the non-silicided region 912 (resistor body) of the polysilicon resistive element top surface 908 is not covered by silicide. As shown in Figure 9B, a vertical height H910 of the silicided region 910 (in the z-direction) from an arbitrary reference plane, Zref, is equal to, or greater than, a vertical height H912 of the non-silicided region 912.
As shown in Figures 9 A and 9B, respective contacts 930 formed in a dielectric region 932 (e.g., a PMD region) over the partially silicided resistor 902 are conductively connected to the respective silicided regions 910 (resistor heads), to provide electrical contact to the polysilicon resistive element 906.
Figures 10A-10B through Figures 15A-15B illustrate an example method of forming the example IC device 900 including the partially silicided resistor 902 shown in Figures 9A and 9B.
As shown in Figure 10A (top view) and Figure 10B (cross-sectional side view through line 10B-10B shown in Figure 10A), the base structure 906 (polysilicon resistive element) is formed over a substrate 1002, e.g., an STI field oxide region or other dielectric region. The polysilicon resistive element 906 may be formed by depositing, patterning and etching a polysilicon layer, e.g., concurrent with formation of poly gates of respective CMOS transistors formed in the example IC device 900.
As shown in Figure 11 A (top view) and Figure 1 IB (cross-sectional side view through line 1 IB-1 IB shown in Figure 11 A), a silicide layer 1100 is formed on the top surface 908 of the polysilicon resistive element 906. In some examples, the silicide layer 1100 may comprise titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), having a thickness (z-direction) in the range of 50-300A.
As shown in Figure 12A (top view) and Figure 12B (cross-sectional side view through line 12B-12B shown in Figure 12 A), a dielectric region 1200 is formed over the structure through a combination of deposition and CMP processes. The dielectric region 1200 may include a base dielectric layer 1202 and a sacrificial dielectric layer 1204 over the base dielectric layer 1202. In some examples, the base dielectric layer 1202 represents a pre-metal dielectric (PMD) region and the sacrificial dielectric layer 1204 represents a partial vertical thickness (z-direction) of the dielectric region 1200 that is removed by a subsequent planarization process, e.g., as shown in Figure 15, discussed below. As discussed above regarding the base dielectric layer 304 and sacrificial dielectric layer 306 of the dielectric region 302, the dielectric region 1200 may comprise a continuous region of a dielectric material, wherein the dielectric base layer 1202 and sacrificial dielectric layer 1204 comprise respective partial thicknesses of the deposited dielectric material, or alternatively, the base dielectric layer 1202 and sacrificial dielectric layer 1204 may comprise different dielectric materials deposited by respective deposition processes. In some examples, the base dielectric layer 1202 may comprise SiCh, PSG, BPSG, or a combination thereof. In some examples, the base dielectric layer 1202 has a vertical thickness in the range of 0.5-1.0 pm, and the sacrificial dielectric layer 1204 may comprise SiO2, with a vertical thickness in the range of 500-2000A (0.05-0.2 pm).
After forming the dielectric region 1200, a first etch process (e.g., pattern and etch process) is performed to concurrently form contact openings 1210 and a tub opening 1212 over the polysilicon resistive element 906. Contact openings 1210 and tub opening 1212 expose respective areas of the silicide layer 1100.
As shown, tub openings 1212 are substantially wider (e.g., in the x-direction and y- direction) than contact openings 1210. For example, respective contact openings 1210 may have a lateral width (e.g., in the x-direction and y-direction) in the range of 0.1-0.5pm, whereas respective tub openings 1212 may have a lateral width (e.g., in the x-direction and y-direction) of at least 1pm, for example in the range of l-100pm.
As shown in Figure 13 A (top view) and Figure 13B (cross-sectional side view through line 13B-13B shown in Figure 13A), a liner 1300 (e.g., a titanium nitride (TiN) layer) is deposited over the dielectric region 1200 and extending down into contact openings 1210 and tub opening 1212, followed by deposition of a conformal metal 1302 over the liner 1300 and extending down into contact openings 1210 and tub opening 1212. In some examples, the conformal metal 1302 comprises tungsten or other conformal metal deposited with a thickness in the range of 1000-5000 A, e.g., using a chemical vapor deposition (CVD) process.
The deposited conformal metal 1302 concurrently (a) fully fills respective contact openings 1210 to form contacts 930 conductively connected to silicide layer 1100 (in particular, in the silicide layer areas 920 remaining after the partial silicide removal process discussed herein, e.g., as shown in Figures 14A-14B discussed below), and (b) partially fills tub opening 1212 to form a cup-shaped metal structure 1306 in the tub opening 1212. The cupshaped metal structure 1306 is formed over a sacrificial area 1310 of the underlying silicide layer 1100 to be subsequently removed.
As shown in Figure 14A (top view) and Figure 14B (cross-sectional side view through line 14B-14B shown in Figure 14A), a second etch process is performed to remove the cup- shaped metal structure 1306 in the tub opening 1212, along with the underlying sacrificial area 1310 of the silicide layer 1100, which exposes an area 1400 of the base structure (polysilicon resistive element) 906 under the sacrificial area 1310 of silicide layer 1100.
In some examples, the second etch process includes multiple etches, e.g., using different etch chemistries or process parameters. For example, the second etch process may include (a) a conformal metal etch to remove the cup-shaped metal structure 1306 in the tub opening 1212, followed by (b) a silicide etch to remove the underlying sacrificial area 1310 of silicide layer 1100. The conformal metal etch (e.g. tungsten etch) may comprise an isotropic wet or dry (plasma) etch, and may involve an over etch to clear the conformal metal 1302 from the tub opening 1212. The silicide etch may comprise a wet etch process, e.g., using diluted hydrofluoric acid (DHF).
The second etch process may stop at the original level (vertical height) of the base structure top surface 908, or may extend down a small distance into the base structure (polysilicon resistive element) 906 (e.g., less than 100A) due to over etch, resulting in the vertical height of the non-silicided region 912 (resistor body) being equal to, or less than, the vertical height of the silicided regions 910 (resistor heads).
In some examples, an optional implant may be applied to the exposed area 1400 of the polysilicon resistive element 906, using the sacrificial dielectric layer 1204 as a hard mask to block the implant from unwanted areas (i.e., silicided regions 910), to modify the sheet resistance value of the resulting partially silicide resistor 902.
The exposed area 1400 of the polysilicon resistive element 906 defines the non-silicided region 912 of the base structure top surface 908 of the partially silicided resistor 902, and the remaining areas of the silicide layer 1100 (i.e., not removed by the second etch process) define the silicided regions 910 of the base structure top surface 908 of the partially silicided resistor 902.
As shown in Figure 15A (top view) and Figure 15B (cross-sectional side view through line 15B-15B shown in Figure 15 A), a dielectric fill material 1500 is deposited over the structure and extending down into the tub opening 1212 to fill the tub opening 1212. In some examples, the dielectric fill material 1500 may comprise silicon oxide (SiCh), and may be deposited by plasma-enhanced chemical vapor deposition (PECVD).
After filling the tub opening 1212 with the dielectric fill material 1500, a planarization process, e.g., an oxide CMP process, is performed to remove a remaining portion of the sacrificial dielectric layer 1204. The planarization may extend down (in the z-direction) to the top of base dielectric layer 1202 or may extend a small distance (e.g., less than 500A) into the base dielectric layer 1202. The resulting structure of the IC device 900 shown in Figures 15A- 15B may correspond with the structure shown in Figures 9A-9B discussed above. After the planarization process, additional IC structures and devices may be constructed over the example partially silicided resistor 902.
Although example embodiments have been described above, other variations and embodiments may be made from this disclosure without departing from the spirit and scope of these embodiments.

Claims

1. A method, comprising: forming a silicided structure including a silicide layer on a base structure; forming a dielectric region over the silicided structure; performing a first etch process to form a contact opening and a tub opening in the dielectric region, the contact opening exposing a first area of the silicide layer, and the tub opening exposing a second area of the silicide layer; depositing a conformal metal over the dielectric region, the deposited conformal metal (a) filling the contact opening to define a contact conductively connected to the first area of the silicide layer and (b) forming a cup-shaped metal structure in the tub opening; performing a second etch process to remove the cup-shaped metal structure from the tub opening, to remove the second area of the silicide layer and to expose an area of the base structure under the second area of the silicide layer, wherein the first area of the silicide layer remains intact after the second etch process; wherein the base structure with the intact first area of the silicide layer and the removed second area of the silicide layer defines a partially silicided element.
2. The method of Claim 1, wherein the base structure comprises a polysilicon element.
3. The method of Claim 2, wherein the polysilicon element comprises a transistor gate.
4. The method of Claim 2, wherein the polysilicon element comprises a resistor element.
5. The method of any of Claims 1-4, wherein the base structure comprises an active region of a transistor.
6. The method of any of Claims 1-5, wherein the conformal metal comprises tungsten.
7. The method of any of Claims 1-6, comprising filling the tub opening with a dielectric fill material after the second etch process.
8. The method of any of Claims 1-7, wherein the second etch process includes: a conformal metal etch to remove the cup-shaped metal structure from the tub opening; and a silicide etch to remove the second area of the silicide layer.
9. The method of any of Claims 1-8, wherein: the dielectric region formed over the silicided structure includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch removes an upper portion of the contact having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer; and the method includes: filling the tub opening with a dielectric fill material after the second etch process; and after filling the tub opening with the dielectric fill material, performing a planarization process to remove an upper portion of the dielectric fill material and a remaining portion of the sacrificial dielectric layer.
10. The method of Claim 9, wherein the dielectric base layer and the sacrificial dielectric layer comprise respective portions of a dielectric material deposited over the silicided structure.
11. The method of Claim 9, wherein the base dielectric layer comprises a first dielectric material and the sacrificial dielectric layer comprises a second dielectric material different than the first dielectric material.
12. The method of any of Claims 1-11, wherein a lateral width of the tub opening is greater than a lateral width of the contact opening.
13. The method of Claim 12, wherein: the contact opening has a lateral width in the range of 0.1-0.5pm; and the tub opening has a lateral width in the range of l-100pm.
14. A device, comprising: a partially silicided element including a base structure having a top surface including a silicided region and a non-silicided region; wherein the silicided region of the top surface of the base structure is covered by a silicide layer, and the non-silicided region of the top surface of the base structure is not covered by the silicide layer; wherein a vertical height of the silicided region of the top surface of the base structure is equal to, or greater than, a vertical height of the non-silicided region of the top surface of the base structure.
15. The device of Claim 14, wherein the base structure comprises a polysilicon transistor gate.
16. The device of Claim 14, wherein the base structure comprises a polysilicon resistor element.
17. The device of Claim 14, wherein the base structure comprises an active region of a transistor.
18. The device of any of Claims 14-17, further comprising a fully silicided element including a second base structure having a second top surface fully covered by a second silicide layer, wherein the base structure of the partially silicided element and the second base structure of the fully silicided element comprise respective portions of a common material layer.
19. A device, formed by a method of any of Claims 1-13.
20. A method of forming an integrated circuit (IC) device including (a) a partially silicided element and (b) a fully silicided element, the method comprising: forming a first silicided structure including a first silicide layer formed on a first base structure; forming a second silicided structure including a second silicide layer formed on a second base structure; forming a dielectric region over the first and second silicided structures; performing a first etch process to form a first contact opening, a second contact opening, and a tub opening in the dielectric region, wherein the first contact opening exposes the first silicide layer, the second contact opening exposes a first area of the second silicide layer, and the tub opening exposes a second area of the second silicide layer; depositing a conformal metal over the dielectric region, the deposited conformal metal layer:
(a) filling the first contact opening to define a first contact conductively connected to the first silicide layer;
(b) filling the second contact opening to define a second contact conductively connected to the first area of the second silicide layer; and
(c) forming a cup-shaped metal structure in the tub opening; performing a second etch process to remove the cup-shaped metal structure in the tub opening, to remove the second area of the second silicide layer and to expose an area of the second base structure under the second area of the second silicide layer, wherein the first silicide layer and the first area of the second silicide layer remain intact after the second etch process; and filling the tub opening with a dielectric fill material; wherein the first base structure with the intact first silicide layer defines the fully silicided element; and wherein the second base structure with the intact first area of the second silicide layer and the removed second area of the second silicide layer defines the partially silicided element.
21. The method of Claim 20, wherein: the dielectric region formed over the first and second silicided structures includes a base dielectric layer and a sacrificial dielectric layer over the base dielectric layer; the second etch process removes an upper portion of the first contact and an upper portion of the second contact respectively having a vertical depth extending partially through a vertical thickness of the sacrificial dielectric layer; and the method includes, after filling the tub opening with the dielectric fill material, performing a planarization process to remove remaining portions of the sacrificial dielectric layer.
22. An integrated circuit formed by a method of any of Claims 20-21.
PCT/US2023/015161 2022-09-14 2023-03-14 Forming a partially silicided element WO2024058820A1 (en)

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US202263406356P 2022-09-14 2022-09-14
US63/406,356 2022-09-14
US18/070,748 US20240087886A1 (en) 2022-09-14 2022-11-29 Forming a partially silicided element
US18/070,748 2022-11-29

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Citations (5)

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JPH09283462A (en) * 1996-04-11 1997-10-31 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH1079430A (en) * 1996-09-05 1998-03-24 Mitsubishi Electric Corp Manufacturing method of semiconductor device having wiring layer contact structure
US6091154A (en) * 1997-03-19 2000-07-18 Fujitsu Limited Semiconductor device with self-aligned contact and manufacturing method thereof
US20040070033A1 (en) * 2002-10-09 2004-04-15 Yoo-Cheol Shin Semiconductor device with resistor pattern and method of fabricating the same
US20160358905A1 (en) * 2015-06-05 2016-12-08 International Business Machines Corporation Compound semiconductor devices having buried resistors formed in buffer layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283462A (en) * 1996-04-11 1997-10-31 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH1079430A (en) * 1996-09-05 1998-03-24 Mitsubishi Electric Corp Manufacturing method of semiconductor device having wiring layer contact structure
US6091154A (en) * 1997-03-19 2000-07-18 Fujitsu Limited Semiconductor device with self-aligned contact and manufacturing method thereof
US20040070033A1 (en) * 2002-10-09 2004-04-15 Yoo-Cheol Shin Semiconductor device with resistor pattern and method of fabricating the same
US20160358905A1 (en) * 2015-06-05 2016-12-08 International Business Machines Corporation Compound semiconductor devices having buried resistors formed in buffer layer

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