WO2024055760A1 - 多频段低噪声放大器、集成电路芯片及电子设备 - Google Patents

多频段低噪声放大器、集成电路芯片及电子设备 Download PDF

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Publication number
WO2024055760A1
WO2024055760A1 PCT/CN2023/109830 CN2023109830W WO2024055760A1 WO 2024055760 A1 WO2024055760 A1 WO 2024055760A1 CN 2023109830 W CN2023109830 W CN 2023109830W WO 2024055760 A1 WO2024055760 A1 WO 2024055760A1
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switch
capacitor
output
resistance
resistor
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PCT/CN2023/109830
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English (en)
French (fr)
Inventor
苏俊华
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2024055760A1 publication Critical patent/WO2024055760A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the invention relates to the field of electronic technology, and in particular to a multi-band low-noise amplifier, integrated circuit chip and electronic equipment.
  • Embodiments of the present invention provide a multi-frequency low-noise amplifier, an integrated circuit chip and an electronic device, which can realize multi-frequency bands while reducing the chip area and cost of the device.
  • the present invention provides a multi-band low-noise amplifier, including a plurality of signal input terminals, a plurality of input matching networks connected in one-to-one correspondence with the plurality of signal input terminals, and the Multiple input matching networks connect multiple switch switching units, bypass matching networks, common source stage amplification units, output matching networks, resistance attenuation networks, bypass output switches, amplification output switches and signal output terminals in one-to-one correspondence;
  • Each of the switch switching units includes a first switch and a second switch.
  • the common source stage amplification unit includes a first transistor, a second transistor, a first inductor, a stabilizing capacitor, a choke inductor and a feedback inductor.
  • the bypass The circuit matching network includes a first capacitor group, the first capacitor group includes a plurality of first capacitor branches connected in parallel, and each of the first capacitor branches includes a connected first capacitor and a first capacitor switching switch;
  • At least one of the input matching networks includes at least one of a resistor and a capacitor; the input end of each input matching network is connected to a corresponding signal input end, and the first switch of each of the switch switching units The first terminal and the first terminal of the second switch are each connected to the output of the corresponding input matching network.
  • the second end of the first switch of each switch switching unit is connected to the first end of the plurality of first capacitor branches in parallel, and the second end of the second switch of each switch switching unit Both are connected to the first end of the first inductor, the second end of the first inductor is connected to the gate of the first transistor, the source of the first transistor is grounded through the feedback inductor, and the The drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor is connected to ground through the voltage stabilizing capacitor, and the drain of the second transistor is connected to the supply voltage through the choke inductor.
  • the input end of the output matching network is connected to the drain of the second transistor, the output end of the output matching network is connected to the input end of the resistance attenuation network through the amplification output switch, the plurality of The parallel second end of the first capacitor branch is connected to the input end of the resistance attenuation network through the bypass output switch, and the output end of the resistance attenuation network is connected to the signal output end.
  • each of the switch switching units further includes a third switch, a first end of each of the third switches is connected to an output end of a corresponding input matching network, and a second end of each of the third switches is grounded.
  • the output matching network includes a variable capacitor
  • the first end of the variable capacitor is the input end of the output matching network and is connected to the drain of the second transistor.
  • the second end of the variable capacitor is the output end of the output matching network and is connected to the drain of the second transistor.
  • the amplified output switch is connected.
  • variable capacitor includes a second capacitor group, a third capacitor group and a fourth capacitor group;
  • the second capacitor group includes one or a plurality of second capacitor branches connected in parallel, each of the second capacitor branches includes a connected second capacitor and a second capacitor switch, and the third capacitor group includes a Or multiple third capacitor branches connected in parallel, each of the third capacitor branches includes a connected third capacitor and a third capacitor switching switch, and the fourth capacitor group includes one or multiple fourth capacitors connected in parallel. branches, each of the fourth capacitor branches includes a connected fourth capacitor and a fourth capacitor switching switch;
  • first end of the second capacitor branch is connected to the first end of the third capacitor branch to serve as the first end of the variable capacitor
  • the second end of the second capacitor branch The first end of the fourth capacitor branch is connected to serve as the second end of the variable capacitor.
  • the second end of the third capacitor branch and the second end of the fourth capacitor branch are both Ground.
  • the resistance attenuation network includes a fourth switch and a variable resistor
  • the first end of the fourth switch is connected to the first end of the variable resistor to serve as the input end of the resistance attenuation network and is connected to the bypass output switch and the amplification output switch.
  • the second end of the switch is connected to the second end of the variable resistor to serve as the output end of the resistance attenuation network and is connected to the signal output end.
  • variable resistor includes a first resistance group, a second resistance group and a third resistance group
  • the first resistance group includes one or a plurality of first resistance branches connected in parallel, each of the first resistance branches includes a connected first resistor and a first resistance switch, and the second resistance group includes a or a plurality of second resistor branches connected in parallel, each of the second resistor branches includes a connected second resistor and a second resistance switch, and the third resistor group includes one or a plurality of third resistors connected in parallel. branches, each of the third resistance branches includes a connected third resistor and a third resistance switch;
  • first end of the first resistance branch is connected to the first end of the second resistance branch as the first end of the variable resistor
  • the second end of the first resistance branch is The end is connected to the first end of the third resistance branch as the second end of the variable resistor, the second end of the second resistance branch and the second end of the third resistance branch Both terminals are grounded.
  • the common source stage amplification unit further includes a first bias resistor and a second bias resistor;
  • the first end of the first bias resistor is connected to the gate of the first transistor, the second end of the first bias resistor is connected to the first bias signal; the first end of the second bias resistor is connected to the gate of the first transistor.
  • the second end of the second bias resistor is connected to the gate of the second transistor, and the second end of the second bias resistor is connected to the second bias signal.
  • the present invention also provides an integrated circuit chip, including the multi-band low-noise amplifier described in any one of the above.
  • the third invention also provides an electronic device, including the multi-band low-noise amplifier described in any one of the above.
  • a plurality of switch switching units are respectively connected to a plurality of signal input terminals in a one-to-one correspondence, wherein each switch switching unit includes a first switch and a second switch.
  • the switch and the second switch are respectively connected to the bypass matching network and the common source stage amplification unit, whereby by controlling the on and off of the first switch and the second switch, the signal can be output from the bypass matching network or pass through the common source
  • the stage amplification unit amplifies the output, and by setting multiple signal input terminals, multiple signals of different frequency bands can be input, and multiple switch switching units can realize switching of different signal input terminals, such as when one of the signal input terminals needs to input a signal.
  • the first switch or the second switch in the switch switching unit connected to the signal input terminal can be turned on, and the first switch and the second switch of the switch switching unit connected to other signal input terminals can be turned off, thereby Allows low noise amplifier to be connected
  • the signal input by one signal input terminal is bypassed or amplified. Therefore, multi-input and multi-band functions can be achieved through this solution, and multiple signal input terminals share a common source stage amplification unit, which can greatly reduce the occupied space. area, which is conducive to chip miniaturization; in addition, in this solution, at least one of the input matching networks includes at least one of a resistor and a capacitor, that is, the input matching network is implemented using resistors or capacitors. Compared with the inductor method , the area occupied by the resistor or capacitor is smaller, which is conducive to further reducing the chip area.
  • Figure 1 is a schematic structural diagram of a multi-band low-noise amplifier provided by an embodiment of the present invention
  • Figure 2 is a schematic structural diagram of a bypass matching network provided by an embodiment of the present invention.
  • Figure 3 is a schematic structural diagram of an output matching network provided by an embodiment of the present invention.
  • Figure 4 is a schematic structural diagram of a resistance attenuation network provided by an embodiment of the present invention.
  • FIG. 5 is a specific implementation circuit diagram of the multi-band low-noise amplifier provided by the embodiment of the present invention.
  • the low-noise amplifier 100 includes a plurality of signal input terminals RFin1 ⁇ RFinn, which are connected in a one-to-one correspondence with the plurality of signal input terminals RFin1 ⁇ RFinn.
  • Resistor attenuation network 104, bypass output switch SB1, amplification output switch SB2 and signal output terminal RFout Resistor attenuation network 104, bypass output switch SB1, amplification output switch SB2 and signal output terminal RFout.
  • Each switch switching unit Sn includes a first switch SA1 and a second switch SA2.
  • the common source stage amplification unit includes a first transistor M1, a second transistor M2, a first inductor LG, a voltage stabilizing capacitor CCG, and a choke inductor. LD and feedback inductor LS.
  • the bypass matching network 102 includes a first capacitor group.
  • the first capacitor group includes a plurality of first capacitor branches connected in parallel. Each of the first capacitor branches includes a connected first capacitor C11 and a first capacitor branch. Capacitance switch S11.
  • At least one of the input matching networks includes at least one of a resistor and a capacitor.
  • the input end of each input matching network 101n is connected to the corresponding signal input end RFinn, and the first end of the first switch SA1 and the first end of the second switch SA2 of each switch switching unit Sn are connected to the corresponding signal input end RFinn.
  • the output end of the input matching network 101n, the second end of the first switch SA1 of each switch switching unit Sn is connected to the first end of the plurality of first capacitor branches in parallel, and each of the switch switches
  • the second terminals of the second switch SA2 of the unit Sn are both connected to the first terminal of the first inductor LG, and the second terminal of the first inductor LG is connected to the gate of the first transistor M1.
  • the source of a transistor M1 is connected to ground through the feedback inductor LS, the drain of the first transistor M1 is connected to the source of the second transistor M2, and the gate of the second transistor M2 passes through the voltage stabilizing capacitor.
  • CCG is grounded, the drain of the second transistor M2 is connected to the supply voltage VDD through the choke inductor LD, and the input end of the output matching network 103 is connected to the drain of the second transistor M2.
  • the output matching network The output end of 103 is connected to the input end of the resistance attenuation network 104 through the amplification output switch SB2, and the second end of the plurality of first capacitor branches in parallel is connected to the resistance attenuation network through the bypass output switch SB1.
  • the input terminal of the network 104 is connected, and the output terminal of the resistance attenuation network 104 is connected to the signal output terminal RFout.
  • multiple input matching networks 1011 ⁇ 101n serve as input matching for multiple signal input terminals RFin1 ⁇ RFinn, respectively, to provide input impedance matching.
  • Each input matching network can be different.
  • the impedance of each input matching network can be set according to the frequency bands of different input signals, so that the input impedance of the entire low-noise amplifier 100 can operate in multiple frequency bands.
  • the low-noise amplifier 100 of this embodiment by controlling the on and off of the first switch SA1 and the second switch SA2, can cause the signal to be output from the bypass matching network 102 or amplified by the common source stage amplification unit and output through Multiple signal input terminals RFin1 ⁇ RFinn can be set to input signals of multiple different frequency bands, and multiple switch switching units S1 ⁇ Sn can be used to switch different signal input terminals.
  • the signal input terminals when one of the signal input terminals needs to input a signal, it can be The first switch or the second switch in the switch switching unit connected to the signal input terminal is turned on, and the first switch and the second switch of the switch switching unit connected to the other signal input terminals are turned off, thereby making the low voltage
  • the noise amplifier 100 receives the signal input from one signal input terminal and performs bypass output or amplified output. Therefore, the multi-input multi-band function can be realized through this solution, and multiple signal input terminals share a common source stage amplification unit, which can It greatly reduces the occupied area and is conducive to chip miniaturization.
  • At least one of the input matching networks includes at least one of a resistor and a capacitor, that is, the input matching network is implemented using resistors or capacitors.
  • the resistors or capacitors occupy more space. The area is smaller, which is conducive to further reducing the chip area.
  • the first switch SA1 in the switch switching unit S1 corresponding to the signal input terminal RFin1 is in the open state
  • the second switch SA2 is in the closed state
  • the first switch and the second switch in Sn are both in an open state
  • the bypass output switch SB1 is in an open state
  • the amplification output switch SB2 is in a closed state.
  • the low-noise amplifier 100 is in the amplification mode, and the signal input terminal RFin1 After the input signal passes through the input matching network 1011, it is transmitted to the first inductor LG through the second switch SA2 in the switch switching unit S1, so that the common source stage amplification unit amplifies the signal and outputs it to the output matching network 103, and then attenuates it through the resistor.
  • Network 104 outputs to the signal output terminal RFout.
  • the input matching network, the first inductor LG and the feedback inductor LS together form an inductive impedance of the cascode input matching, which resonates with the gate-source parasitic capacitance of the first transistor M1.
  • the first switch SA1 in the switch switching unit S1 corresponding to the signal input terminal RFin1 when the first switch SA1 in the switch switching unit S1 corresponding to the signal input terminal RFin1 is in a closed state, the second switch SA2 is in an open state, and the third switch SA1 in the switch switching units S2 ⁇ Sn corresponding to the other signal input terminals RFin2 ⁇ RFinn.
  • the first switch and the second switch are both in the off state, the bypass output switch SB1 is in the closed state, and the amplification output switch SB2 is in the off state.
  • the low noise amplifier 100 is in the bypass mode, and the signal input to the signal input terminal RFin1 After passing through the input matching network 1011, it is transmitted to the bypass matching network 102 through the first switch SA1 in the switch switching unit S1, and is directly output to the resistance attenuation network 104, and then output through the signal output terminal RFout.
  • the impedance of each input matching network may be different.
  • the impedance of each input matching network may be set according to the frequency band of different input signals, thereby making the entire low noise amplifier 100 Input impedance operates in multiple frequency bands.
  • each switch switching unit Sn further includes a third switch SH, and the first end of each third switch SH is connected to the corresponding input matching network 101n. At the output end, the second end of each third switch SH is grounded.
  • the third switch SH in the switch switching unit S1 is turned off, and the other switch switching units S2 ⁇ Sn are connected. First The three switches SH are closed, thereby causing the other signal input terminals RFin2 to RFinn to be grounded through the corresponding third switch, thereby further avoiding signal interference from the other signal input terminals RFin2 to RFinn.
  • the output matching network 103 includes a variable capacitor.
  • the first end of the variable capacitor is the input end of the output matching network 103 and is connected to the drain of the second transistor M2.
  • the second end of the variable capacitor is the output of the output matching network 103. terminal, connected to the amplification output switch SB2.
  • variable capacitor includes a second capacitor group 22, a third capacitor group 23 and a fourth capacitor group 24;
  • the second capacitor group 22 includes one or a plurality of second capacitor branches connected in parallel. Each of the second capacitor branches includes a connected second capacitor C22 and a second capacitor switch S22.
  • the third capacitor The group 23 includes one or a plurality of third capacitor branches connected in parallel. Each of the third capacitor branches includes a connected third capacitor C23 and a third capacitor switch S23.
  • the fourth capacitor group includes one or a plurality of parallel connected capacitor branches. A plurality of fourth capacitor branches, each of the fourth capacitor branches includes a connected fourth capacitor C24 and a fourth capacitor switch S24.
  • first end of the second capacitor branch is connected to the first end of the third capacitor branch to serve as the first end of the variable capacitor
  • the second end of the second capacitor branch The first end of the fourth capacitor branch is connected to serve as the second end of the variable capacitor.
  • the second end of the third capacitor branch and the second end of the fourth capacitor branch are both Ground.
  • the second capacitor group 22 has a plurality of second capacitor branches connected in parallel
  • the third capacitor group 23 has a plurality of third capacitor branches connected in parallel
  • the fourth capacitor group 24 has a plurality of fourth capacitors connected in parallel.
  • the first end of the parallel connection of the plurality of second capacitance branches is connected to the first end of the parallel connection of the plurality of third capacitance branches
  • the connection node serves as the first end of the variable capacitor to communicate with the second transistor M2
  • the drain is connected
  • the second end of the parallel connection of the plurality of second capacitance branches is connected to the first end of the parallel connection of the plurality of fourth capacitance branches
  • the connection node serves as the second end of the variable capacitor to communicate with the amplification output switch SB2 connection.
  • the second ends of the parallel connection of the plurality of third capacitor branches and the second ends of the parallel connection of the plurality of fourth capacitor branches are both grounded.
  • the capacitance of the variable capacitor can be changed, thereby achieving a change in the output impedance of the output matching network 103 . Therefore, the output impedance of the output matching network 103 can be adjusted according to the required operating frequency band.
  • the resistance attenuation network 104 includes a fourth switch S30 and a variable resistor.
  • the first end of the fourth switch S30 is connected to the first end of the variable resistor as the input end of the resistance attenuation network 104, and is connected with the bypass output switch SB1 and the amplification output switch SB2. connection, the second end of the fourth switch S30 is connected to the second end of the variable resistor to serve as the output end of the resistance attenuation network 104, and is connected to the signal output end RFout.
  • variable resistor includes a first resistance group 31 , a second resistance group 32 and a third resistance group 33 .
  • the first resistor group 31 includes one or multiple first resistor branches connected in parallel. Each of the first resistor branches includes a connected first resistor R31 and a first resistance switch S31.
  • the second resistor The group 32 includes one or a plurality of second resistor branches connected in parallel, each of the second resistor branches includes a connected second resistor R32 and a second resistor switch S32, and the third resistor group 33 includes one or more second resistor branches connected in parallel.
  • a plurality of third resistance branches are connected in parallel, and each third resistance branch includes a connected third resistor R33 and a third resistance switching switch S33.
  • first end of the first resistance branch is connected to the first end of the second resistance branch as the first end of the variable resistor
  • the second end of the first resistance branch is The end is connected to the first end of the third resistance branch to serve as the second end of the variable resistor, the second end of the second resistance branch and the second end of the third resistance branch Both terminals are grounded.
  • the first resistor group 31 has a plurality of first resistor branches connected in parallel
  • the second resistor group 32 has a plurality of second resistor branches connected in parallel
  • the third resistor group 33 has a plurality of third resistors connected in parallel.
  • the first end of the parallel connection of the plurality of first resistance branches is connected to the first end of the parallel connection of the plurality of second resistance branches
  • the connection node serves as the first end of the variable resistor to communicate with the bypass
  • the output switch SB1 is connected to the amplification output switch SB2, the second end of a plurality of first resistance branches in parallel is connected to the first end of a plurality of third resistance branches in parallel, and the connection node serves as a variable resistor.
  • the second terminal is connected to the signal output terminal RFout.
  • the second ends of the parallel connection of the plurality of second resistance branches and the second ends of the parallel connection of the plurality of third resistance branches are both grounded. Therefore, by controlling the on or off resistance switching switches in each resistance branch, the resistance value of the variable resistor can be changed, and thus different insertion losses can be obtained.
  • the common source stage amplification unit further includes a first bias resistor R1 and a second bias resistor R2.
  • the first end of the first bias resistor R1 is connected to the gate of the first transistor M1, and the second end of the first bias resistor R1 is connected to the first bias signal BIAS1; the second The first end of the bias resistor R2 is connected to the gate of the second transistor M2, and the second end of the second bias resistor R2 is connected to the second bias signal BIAS2.
  • the three signal input terminals are RFin1 ⁇ RFin3 respectively.
  • the three input matching networks and switch switching units among which three input matching networks They are inductor L1, capacitor C1 and resistor R0 respectively, and the three switch switching units are switch switching units S1 to S3 respectively.
  • the variable capacitors of the output matching network 103 there are two capacitor branches in the first capacitor group, the second capacitor group, and the third capacitor group, as an example, that is, the second capacitor branch and the third capacitor branch.
  • each second capacitor branch includes a connected second capacitor C22 and a second capacitor switch S22
  • each third capacitor branch includes a connected third capacitor C23 and The third capacitance switching switch S23
  • each fourth capacitance branch includes a connected fourth capacitor C24 and a fourth capacitance switching switch S24.
  • the resistance branches in the first resistance group, the second resistance group and the third resistance group are each taken as an example, that is, the first resistance branch, the second resistance branch and the third resistance branch.
  • Each of the three resistance branches has one.
  • the first resistance branch includes a connected first resistor R31 and a first resistance switch S31.
  • the second resistance branch includes a connected second resistor R32 and a second resistance switch S32.
  • the third resistor branch includes a connected third resistor R33 and a third resistor switching switch S33.
  • Each first capacitor branch includes a connected first capacitor switching switch S11 and a first capacitor C11.
  • the inductor L1, capacitor C1 and resistor R0 can be used as input matching networks corresponding to different frequency bands.
  • the three first capacitor branches together form a switchable capacitance, thereby forming a switchable bypass matching network 102 .
  • the input matching network and the bypass matching network 102 work together to make the input impedance resonate in the target operating frequency band to avoid excessive return loss.
  • the input matching network, the feedback inductor LS, the gate-source parasitic capacitance of the first transistor M1 and the first inductor LG jointly determine the resonant frequency of the input impedance, and the output resonant frequency is jointly determined by the choke inductor LD and the output matching network 103 It is determined that by adjusting the capacitance switch in the output matching network 103, the output resonant frequency can be the same as the input resonant frequency.
  • the gain of the low-noise amplifier 100 reaches the highest level.
  • S31, S32, S33, R31, R32, and R33 form two resistance attenuation networks 104 with different levels of insertion loss, thereby further processing the amplified or bypassed output signal. Ground attenuation or pass-through output.
  • the signal input to one of the signal input terminals can be selected to be output after being processed by the low-noise amplifier.
  • the signal input to the signal input terminal RFin1 corresponds to the signal input terminal RFin1.
  • the third switch SH of the switch switching unit S1 is turned off, and the third switch SH of the switch switching units S2 and S3 corresponding to other signal input terminals is closed, so that the signal input terminal RFin2 and the signal input terminal RFin3 are connected to the ground, so that the signal input terminal RFin2 and the signal input terminal RFin3 can be connected to the ground. This prevents the signals from the two signal input terminals from interfering with the signal at the signal input terminal RFin1.
  • the first switch SA1 and the second switch SA2 in the switch switching units S2 and S3 are both in an off state, thereby blocking the signals from the signal input terminals RFin2 and RFin3 from entering the circuit.
  • the low noise amplifier 100 can be made to work in the bypass mode or the amplification mode, that is, the signal can be controlled to pass through the bypass matching network.
  • 102 direct output or amplified output from the common source stage amplification unit.
  • the first switch SA1 in the switch switching unit S1 is open, the second switch SA2 is closed, the bypass output switch SB2 is open, the amplification output switch SB1 is closed, and after the signal is amplified by the common source stage amplification unit, It is output to the resistance attenuation network 104 through the output matching network 103, wherein whether the amplified signal is attenuated can be controlled by controlling the on or off of the fourth switch S30.
  • the fourth switch S30 of the resistance attenuation network 104 is closed, , at this time, the amplified signal is not attenuated but is directly transmitted to the signal output terminal RFout for output.
  • the fourth switch S30 of the resistance attenuation network 104 is turned off, the amplified signal passes through the variable resistor of the resistance attenuation network 104 After further attenuation, it is output through the signal output terminal RFout.
  • the resistance value of the variable resistor can be changed, thereby changing the degree of signal attenuation.
  • the switches S31 and S32 can be controlled to be on and the switch S33 to be off, or the switches S31 and S33 can be controlled to be on and the switch S32 to be off, thereby obtaining the resistance values of the two gears.
  • the number of capacitive branches in the bypass matching network 102 and the output matching network 103 and the number of resistive branches in the resistance attenuation network 104 can be set according to actual needs, and are not specifically limited.
  • An embodiment of the present invention also provides an integrated circuit chip, including the multi-band low-noise amplifier described in any of the above embodiments.
  • An embodiment of the present invention also provides an electronic device, including the multi-band low-frequency device described in any of the above embodiments. Noise amplifier.

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Abstract

一种多频段低噪声放大器（100）、集成电路芯片及电子设备，多频段低噪声放大器（100）中，设置多个开关切换单元（S1-Sn）分别与多个信号输入端（RFin1～RFinn）一一对应连接，其中每个开关切换单元（S1-Sn）中包括有第一开关（SA1）和第二开关（SA2），第一开关（SA1）和第二开关（SA2）分别连接到旁路匹配网络（102）和共源级放大单元，由此通过控制第一开关（SA1）和第二开关（SA2）的导通和关断，可以使得信号从旁路匹配网络（102）输出或者经共源级放大单元放大后输出，并且通过设置多个信号输入端（RFin1～RFinn）可以输入多个不同频段的信号，而通过多个开关切换单元（S1-Sn）可以实现不同信号输入端（RFin1～RFinn）的切换，因此可以实现多输入多频段功能，并且多个信号输入端（RFin1～RFinn）共用一个共源级放大单元，可以大大减少所占用的面积。

Description

多频段低噪声放大器、集成电路芯片及电子设备 技术领域
本发明涉及电子技术领域，尤其涉及一种多频段低噪声放大器、集成电路芯片及电子设备。
背景技术
随着无线通信技术的发展，目前的射频功率放大器通常会工作在不同的频率状态下，从而使得无线通信设备支持多个频段。为了适应不同的频段，现有做法一般是为每个频段设计一个独立的功率放大器，因此多频段无线通信设备中都包括有多个功率放大器以支持多个频段，此种方式大大增加器件的芯片面积和成本；另外，现有的功率放大器中会设计输入阻抗匹配网络，输入阻抗匹配网络通常采用电感元件来实现，电感元件也会占用较大的面积，进一步增加了芯片面积。
发明内容
本发明实施例提供一种多频段低噪声放大器、集成电路芯片及电子设备，能够实现多频段的同时，减小器件的芯片面积，降低成本。
为了解决上述技术问题，第一方面，本发明提供一种多频段低噪声放大器，包括多个信号输入端、与所述多个信号输入端一一对应连接的多个输入匹配网络、与所述多个输入匹配网络一一对应连接的多个开关切换单元、旁路匹配网络、共源级放大单元、输出匹配网络、电阻衰减网络、旁路输出开关、放大输出开关以及信号输出端；
每个所述开关切换单元包括第一开关和第二开关，所述共源级放大单元包括第一晶体管、第二晶体管、第一电感、稳压电容、扼流电感以及反馈电感，所述旁路匹配网络包括第一电容组，所述第一电容组包括并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容和第一电容切换开关；
其中，至少一个所述输入匹配网络包含有电阻和电容中的至少一者；每个所述输入匹配网络的输入端连接至对应的信号输入端，每个所述开关切换单元的第一开关的第一端和第二开关的第一端均连接至对应的输入匹配网络的输出 端，每个所述开关切换单元的第一开关的第二端均与所述多个第一电容支路并联的第一端连接，每个所述开关切换单元的第二开关的第二端均连接至所述第一电感的第一端，所述第一电感的第二端连接至所述第一晶体管的栅极，所述第一晶体管的源极通过所述反馈电感接地，所述第一晶体管的漏极连接至所述第二晶体管的源极，所述第二晶体管的栅极通过所述稳压电容接地，所述第二晶体管的漏极通过所述扼流电感连接供电电压VDD，所述输出匹配网络的输入端连接至所述第二晶体管的漏极，所述输出匹配网络的输出端通过所述放大输出开关与所述电阻衰减网络的输入端连接，所述多个第一电容支路并联的第二端通过所述旁路输出开关与所述电阻衰减网络的输入端连接，所述电阻衰减网络的输出端连接至所述信号输出端。
进一步地，每个所述开关切换单元还包括第三开关，每个所述第三开关的第一端连接至对应的输入匹配网络的输出端，每个所述第三开关的第二端接地。
进一步地，所述输出匹配网络包括可变电容器；
所述可变电容器的第一端为所述输出匹配网络的输入端，与所述第二晶体管的漏极连接，所述可变电容器的第二端为所述输出匹配网络的输出端，与所述放大输出开关连接。
进一步地，所述可变电容器包括第二电容组、第三电容组以及第四电容组；
所述第二电容组包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容和第二电容切换开关，所述第三电容组包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容和第三电容切换开关，所述第四电容组包括一个或并联的多个第四电容支路，每个所述第四电容支路包括相连接的第四电容和第四电容切换开关；
其中，所述第二电容支路的第一端与所述第三电容支路的第一端相连接以作为所述可变电容器的第一端，所述第二电容支路的第二端与所述第四电容支路的第一端相连接以作为所述可变电容器的第二端，所述第三电容支路的第二端和所述第四电容支路的第二端均接地。
进一步地，所述电阻衰减网络包括第四开关和可变电阻器；
所述第四开关的第一端和所述可变电阻器的第一端相连接以作为所述电阻衰减网络的输入端，与所述旁路输出开关和所述放大输出开关连接，所述第四 开关的第二端和所述可变电阻器的第二端相连接以作为所述电阻衰减网络的输出端，与所述信号输出端连接。
进一步地，所述可变电阻器包括第一电阻组、第二电阻组以及第三电阻组；
所述第一电阻组包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻和第一电阻切换开关，所述第二电阻组包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻和第二电阻切换开关，所述第三电阻组包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻和第三电阻切换开关；
其中，所述第一电阻支路的第一端与所述第二电阻支路的第一端相连接以作为所述可变电阻器的第一端，所述第一电阻支路的第二端与所述第三电阻支路的第一端相连接以作为所述可变电阻器的第二端，所述第二电阻支路的第二端和所述第三电阻支路的第二端均接地。
进一步地，所述共源级放大单元还包括第一偏置电阻和第二偏置电阻；
所述第一偏置电阻的第一端与所述第一晶体管的栅极连接，所述第一偏置电阻的第二端连接第一偏置信号；所述第二偏置电阻的第一端与所述第二晶体管的栅极连接，所述第二偏置电阻的第二端连接第二偏置信号。
第二方面，本发明还提供一种集成电路芯片，包括上述任一项所述的多频段低噪声放大器。
第三发明，本发明还提供一种电子设备，包括上述任一项所述的多频段低噪声放大器。
有益效果：本发明的多频段低噪声放大器中，设置多个开关切换单元分别与多个信号输入端一一对应连接，其中每个开关切换单元中包括有第一开关和第二开关，第一开关和第二开关分别连接到旁路匹配网络和共源级放大单元，由此通过控制第一开关和第二开关的导通和关断，可以使得信号从旁路匹配网络输出或者经共源级放大单元放大后输出，并且通过设置多个信号输入端可以输入多个不同频段的信号，而通过多个开关切换单元可以实现不同信号输入端的切换，如当需要其中一个信号输入端输入信号时，可以将该信号输入端所连接的开关切换单元中的第一开关或第二开关导通，并使其他信号输入端所连接的开关切换单元的第一开关和第二开关均关闭，由此可使得低噪声放大器接入 一个信号输入端所输入的信号，并进行旁路输出或放大输出，因此通过本方案可以实现多输入多频段功能，并且多个信号输入端共用一个共源级放大单元，可以大大减少所占用的面积，有利于芯片小型化；此外，本方案中，至少一个所述输入匹配网络包含有电阻和电容中的至少一者，即输入匹配网络采用电阻或电容元件来实现，相比于电感的方式，电阻或电容所占用的面积更小，有利于进一步减小芯片面积。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其有益效果显而易见。
图1是本发明实施例提供的多频段低噪声放大器的结构示意图；
图2是本发明实施例提供的旁路匹配网络的结构示意图；
图3是本发明实施例提供的输出匹配网络的结构示意图；
图4是本发明实施例提供的电阻衰减网络的结构示意图；
图5是本发明实施例提供的多频段低噪声放大器的具体实现电路图。
具体实施方式
请参照图式，其中相同的组件符号代表相同的组件，本发明的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本发明具体实施例，其不应被视为限制本发明未在此详述的其它具体实施例。
参阅图1和图2，本发明实施例的多频段低噪声放大器100中，该低噪声放大器100包括多个信号输入端RFin1～RFinn、与所述多个信号输入端RFin1～RFinn一一对应连接的多个输入匹配网络1011～101n、与所述多个输入匹配网络1011～101n一一对应连接的多个开关切换单元S1～Sn、旁路匹配网络102、共源级放大单元、输出匹配网络103、电阻衰减网络104、旁路输出开关SB1、放大输出开关SB2以及信号输出端RFout。
每个所述开关切换单元Sn包括第一开关SA1和第二开关SA2，所述共源级放大单元包括第一晶体管M1、第二晶体管M2、第一电感LG、稳压电容CCG、扼流电感LD以及反馈电感LS。所述旁路匹配网络102包括第一电容组，所述第一电容组包括并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容C11和第一电容切换开关S11。
其中，至少一个所述输入匹配网络包含有电阻和电容中的至少一者。每个所述输入匹配网络101n的输入端连接至对应的信号输入端RFinn，每个所述开关切换单元Sn的第一开关SA1的第一端和第二开关SA2的第一端均连接至对应的输入匹配网络101n的输出端，每个所述开关切换单元Sn的第一开关SA1的第二端均与所述多个第一电容支路并联的第一端连接，每个所述开关切换单元Sn的第二开关SA2的第二端均连接至所述第一电感LG的第一端，所述第一电感LG的第二端连接至所述第一晶体管M1的栅极，所述第一晶体管M1的源极通过所述反馈电感LS接地，所述第一晶体管M1的漏极连接至所述第二晶体管M2的源极，所述第二晶体管M2的栅极通过所述稳压电容CCG接地，所述第二晶体管M2的漏极通过所述扼流电感LD连接供电电压VDD，所述输出匹配网络103的输入端连接至所述第二晶体管M2的漏极，所述输出匹配网络103的输出端通过所述放大输出开关SB2与所述电阻衰减网络104的输入端连接，所述多个第一电容支路并联的第二端通过所述旁路输出开关SB1与所述电阻衰减网络104的输入端连接，所述电阻衰减网络104的输出端连接至所述信号输出端RFout。
可以理解的是，本发明实施例中，多个输入匹配网络1011～101n分别作为多个信号输入端RFin1～RFinn的输入匹配，用于提供输入阻抗的匹配，各个输入匹配网络可以各不相同，在实际应用中可以根据不同输入信号的频段设置各个输入匹配网络的阻抗，从而可以使得整个低噪声放大器100的输入阻抗工作在多个频段。
本实施例的低噪声放大器100，通过控制第一开关SA1和第二开关SA2的导通和关断，可以使得信号从旁路匹配网络102输出或者经共源级放大单元放大后输出，并且通过设置多个信号输入端RFin1～RFinn可以输入多个不同频段的信号，而通过多个开关切换单元S1～Sn可以实现不同信号输入端的切换，例如当需要其中一个信号输入端输入信号时，可以将该信号输入端所连接的开关切换单元中的第一开关或第二开关导通，并使其他信号输入端所连接的开关切换单元的第一开关和第二开关均关闭，由此可使得低噪声放大器100接入一个信号输入端所输入的信号，并进行旁路输出或放大输出，因此通过本方案可以实现多输入多频段功能，并且多个信号输入端共用一个共源级放大单元，可以 大大减少所占用的面积，有利于芯片小型化。此外，本发明实施例中，至少一个所述输入匹配网络包含有电阻和电容中的至少一者，即输入匹配网络采用电阻或电容元件来实现，相比于电感的方式，电阻或电容所占用的面积更小，有利于进一步减小芯片面积。
如图1所示，信号输入端RFin1对应的开关切换单元S1中的第一开关SA1为断开状态，第二开关SA2为闭合状态，而其他信号输入端RFin2～RFinn对应的开关切换单元S2～Sn中的第一开关和第二开关均为断开状态，并且旁路输出开关SB1为断开状态，放大输出开关SB2为闭合状态，此时低噪声放大器100为放大模式，信号输入端RFin1所输入的信号经过输入匹配网络1011后，通过开关切换单元S1中的第二开关SA2传输至第一电感LG，从而共源级放大单元对信号进行放大后输出至输出匹配网络103，进而通过电阻衰减网络104输出至信号输出端RFout。其中，输入匹配网络、第一电感LG和反馈电感LS共同组成共源共栅的输入匹配的感性阻抗，与第一晶体管M1的栅源寄生电容产生谐振。
其中，当信号输入端RFin1对应的开关切换单元S1中的第一开关SA1为闭合状态，第二开关SA2为断开状态，其他信号输入端RFin2～RFinn对应的开关切换单元S2～Sn中的第一开关和第二开关均为断开状态，并且旁路输出开关SB1为闭合状态，放大输出开关SB2为断开状态，此时低噪声放大器100为旁路模式，信号输入端RFin1所输入的信号经过输入匹配网络1011后，通过开关切换单元S1中的第一开关SA1传输至旁路匹配网络102后被直接输出至电阻衰减网络104，然后经信号输出端RFout输出。
可以理解的是，本发明实施例中，各个输入匹配网络的阻抗可以各不相同，在实际应用中可以根据不同输入信号的频段设置各个输入匹配网络的阻抗，从而可以使得整个低噪声放大器100的输入阻抗工作在多个频段。
进一步地，本发明实施例的低噪声放大器100中，每个所述开关切换单元Sn还包括第三开关SH,每个所述第三开关SH的第一端连接至对应的输入匹配网络101n的输出端，每个所述第三开关SH的第二端接地。当需要接入其中一个信号输入端输入的信号时，例如需要接入信号输入端RFin1输入的信号时，将开关切换单元S1中的第三开关SH断开，将其他开关切换单元S2～Sn中的第 三开关SH闭合，由此使得其他信号输入端RFin2～RFinn通过对应的第三开关接地，从而可以进一步避免其他信号输入端RFin2～RFinn的信号干扰。
其中，本发明实施例中，所述输出匹配网络103包括可变电容器。所述可变电容器的第一端为所述输出匹配网络103的输入端，与所述第二晶体管M2的漏极连接，所述可变电容器的第二端为所述输出匹配网络103的输出端，与所述放大输出开关SB2连接。通过在输出匹配网络103中设置可变电容器，从而可以根据输入信号的频段调整输出匹配网络103的输出阻抗，以使得输出匹配网络103能够匹配不同频段的输入信号。
进一步地，参阅图3，所述可变电容器包括第二电容组22、第三电容组23以及第四电容组24；
所述第二电容组22包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容C22和第二电容切换开关S22，所述第三电容组23包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容C23和第三电容切换开关S23，所述第四电容组包括一个或并联的多个第四电容支路，每个所述第四电容支路包括相连接的第四电容C24和第四电容切换开关S24。其中，所述第二电容支路的第一端与所述第三电容支路的第一端相连接以作为所述可变电容器的第一端，所述第二电容支路的第二端与所述第四电容支路的第一端相连接以作为所述可变电容器的第二端，所述第三电容支路的第二端和所述第四电容支路的第二端均接地。
更具体地，当第二电容组22有并联的多个第二电容支路、第三电容组23有并联的多个第三电容支路以及第四电容组24有并联的多个第四电容支路时，多个第二电容支路并联的第一端与多个第三电容支路并联的第一端相连接，且该连接节点作为可变电容器的第一端以与第二晶体管M2的漏极连接，多个第二电容支路并联的第二端与多个第四电容支路并联的第一端相连接，且该连接节点作为可变电容器的第二端以与放大输出开关SB2连接。多个第三电容支路并联的第二端和多个第四电容支路并联的第二端均接地。
由此，通过控制各个电容支路中的电容切换开关的导通或关断，可以使得可变电容器的容值产生变化，进而实现输出匹配网络103的输出阻抗变化。因此，可以根据所需要的工作频段调整输出匹配网络103的输出阻抗。
参阅图4，本发明实施例的低噪声放大器100中，所述电阻衰减网络104包括第四开关S30和可变电阻器。
所述第四开关S30的第一端和所述可变电阻器的第一端相连接以作为所述电阻衰减网络104的输入端，与所述旁路输出开关SB1和所述放大输出开关SB2连接，所述第四开关S30的第二端和所述可变电阻器的第二端相连接以作为所述电阻衰减网络104的输出端，与所述信号输出端RFout连接。
进一步地，所述可变电阻器包括第一电阻组31、第二电阻组32以及第三电阻组33。所述第一电阻组31包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻R31和第一电阻切换开关S31，所述第二电阻组32包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻R32和第二电阻切换开关S32，所述第三电阻组33包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻R33和第三电阻切换开关S33。
其中，所述第一电阻支路的第一端与所述第二电阻支路的第一端相连接以作为所述可变电阻器的第一端，所述第一电阻支路的第二端与所述第三电阻支路的第一端相连接以作为所述可变电阻器的第二端，所述第二电阻支路的第二端和所述第三电阻支路的第二端均接地。
更具体地，当第一电阻组31有并联的多个第一电阻支路、第二电阻组32有并联的多个第二电阻支路以及第三电阻组33有并联的多个第三电阻支路时，多个第一电阻支路并联的第一端与多个第二电阻支路并联的第一端相连接，且该连接节点作为可变电阻器的第一端以与所述旁路输出开关SB1和所述放大输出开关SB2连接，多个第一电阻支路并联的第二端与多个第三电阻支路并联的第一端相连接，且该连接节点作为可变电阻器的第二端以与信号输出端RFout连接。多个第二电阻支路并联的第二端和多个第三电阻支路并联的第二端均接地。由此，通过控制各个电阻支路中的电阻切换开关的导通或关断，可以使得可变电阻器的阻值产生变化，进而可以得到不同的插入损耗。
其中，本发明实施例中，所述共源级放大单元还包括第一偏置电阻R1和第二偏置电阻R2。所述第一偏置电阻R1的第一端与所述第一晶体管M1的栅极连接，所述第一偏置电阻R1的第二端连接第一偏置信号BIAS1；所述第二 偏置电阻R2的第一端与所述第二晶体管M2的栅极连接，所述第二偏置电阻R2的第二端连接第二偏置信号BIAS2。
下面将结合具体的实施方式对本发明的多频段低噪声放大器的工作原理作进一步说明。
参阅图5，如图5所示，以三个信号输入端为例，三个信号输入端分别为RFin1～RFin3，相应地，输入匹配网络和开关切换单元也有三个，其中三个输入匹配网络分别为电感L1、电容C1以及电阻R0，三个开关切换单元分别为开关切换单元S1～S3。此外，输出匹配网络103的可变电容器中，第一电容组、第二电容组以及第三电容组中的电容支路均以两个为例，即第二电容支路、第三电容支路以及第四电容支路均有两个，每个第二电容支路包括相连接的第二电容C22和第二电容切换开关S22，每个第三电容支路包括相连接的第三电容C23和第三电容切换开关S23，每个第四电容支路包括相连接的第四电容C24和第四电容切换开关S24。电阻衰减网络104的可变电阻器中，第一电阻组、第二电阻组以及第三电阻组中的电阻支路均以一个为例，即第一电阻支路、第二电阻支路以及第三电阻支路均有一个，第一电阻支路包括相连接的第一电阻R31和第一电阻切换开关S31，第二电阻支路包括相连接的第二电阻R32和第二电阻切换开关S32，第三电阻支路包括相连接的第三电阻R33和第三电阻切换开关S33。旁路匹配网络102中的第一电容支路以三个为例，每个第一电容支路包括相连接的第一电容切换开关S11和第一电容C11。
继续参阅图5，电感L1、电容C1以及电阻R0可作为用于对应不同频段的输入匹配网络。三个第一电容支路共同组成可切变的电容，从而形成可切变的旁路匹配网络102。根据频段的不同，在旁路模式下，输入匹配网络与旁路匹配网络102共同作用可以使输入阻抗谐振在目标工作频段，避免回波损耗过大。在放大模式下，输入匹配网络、反馈电感LS、第一晶体管M1的栅源寄生电容以及第一电感LG共同决定输入阻抗的谐振频率，输出谐振频率则由扼流电感LD与输出匹配网络103共同决定，通过调整输出匹配网络103中的电容切换开关即可使得输出谐振频率达到与输入谐振频率相同，此时低噪声放大器100的增益达到最高。S31、S32、S33、R31、R32、R33组成了两个插入损耗不同档位的电阻衰减网络104，由此可以为放大后或者旁路输出的信号进行进一步 地衰减或直通输出。
如图5所示，通过开关切换单元可以选择其中一个信号输入端所输入的信号经过低噪声放大器的处理后进行输出，以选择信号输入端RFin1所输入的信号为例，与信号输入端RFin1对应的开关切换单元S1的第三开关SH断开，其他信号输入端对应的开关切换单元S2、S3的第三开关SH闭合，从而使得信号输入端RFin2和信号输入端RFin3接到地，由此可避免该两个信号输入端的信号对信号输入端RFin1的信号造成干扰。此外，开关切换单元S2和S3中的第一开关SA1、第二开关SA2均为断开状态，以此阻断信号输入端RFin2、RFin3的信号进入电路。而通过控制开关切换单元S1中的第一开关SA1和第二开关SA2的导通或断开，则可以使得低噪声放大器100工作在旁路模式或放大模式，即可以控制信号从旁路匹配网络102直通输出或者从共源级放大单元放大后输出。例如，在放大模式下，开关切换单元S1中的第一开关SA1断开、第二开关SA2闭合，旁路输出开关SB2断开，放大输出开关SB1闭合，信号经过共源级放大单元放大后，通过输出匹配网络103输出至电阻衰减网络104，其中，可以通过控制第四开关S30的导通或断开来控制对放大后的信号是否进行衰减，当电阻衰减网络104的第四开关S30闭合时，此时放大后的信号未进行衰减而是直接传输至信号输出端RFout进行输出，当电阻衰减网络104的第四开关S30断开时，放大后的信号经过电阻衰减网络104的可变电阻器进一步衰减后经信号输出端RFout输出。
其中，通过控制第一电阻切换开关S31、第二电阻切换开关S32以及第三电阻切换开关S33的导通或关闭，可以改变可变电阻器的电阻值，进而改变信号衰减的程度。例如，可以控制开关S31和S32导通，开关S33断开，或者可以控制开关S31和S33导通，开关S32断开，由此可得到两个档位的电阻值。
可以理解的是，旁路匹配网络102和输出匹配网络103中的电容支路的数量、电阻衰减网络104中的电阻支路的数量均可以根据实际需要进行设置，对此不做具体限定。
本发明实施例还提供一种集成电路芯片，包括上述任一实施例所述的多频段低噪声放大器。
本发明实施例还提供一种电子设备，包括上述任一实施例所述的多频段低 噪声放大器。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (9)

  1. 一种多频段低噪声放大器，其特征在于，包括多个信号输入端、与所述多个信号输入端一一对应连接的多个输入匹配网络、与所述多个输入匹配网络一一对应连接的多个开关切换单元、旁路匹配网络、共源级放大单元、输出匹配网络、电阻衰减网络、旁路输出开关、放大输出开关以及信号输出端；
    每个所述开关切换单元包括第一开关和第二开关，所述共源级放大单元包括第一晶体管、第二晶体管、第一电感、稳压电容、扼流电感以及反馈电感，所述旁路匹配网络包括第一电容组，所述第一电容组包括并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容和第一电容切换开关；
    其中，至少一个所述输入匹配网络包含有电阻和电容中的至少一者；每个所述输入匹配网络的输入端连接至对应的信号输入端，每个所述开关切换单元的第一开关的第一端和第二开关的第一端均连接至对应的输入匹配网络的输出端，每个所述开关切换单元的第一开关的第二端均与所述多个第一电容支路并联的第一端连接，每个所述开关切换单元的第二开关的第二端均连接至所述第一电感的第一端，所述第一电感的第二端连接至所述第一晶体管的栅极，所述第一晶体管的源极通过所述反馈电感接地，所述第一晶体管的漏极连接至所述第二晶体管的源极，所述第二晶体管的栅极通过所述稳压电容接地，所述第二晶体管的漏极通过所述扼流电感连接供电电压VDD，所述输出匹配网络的输入端连接至所述第二晶体管的漏极，所述输出匹配网络的输出端通过所述放大输出开关与所述电阻衰减网络的输入端连接，所述多个第一电容支路并联的第二端通过所述旁路输出开关与所述电阻衰减网络的输入端连接，所述电阻衰减网络的输出端连接至所述信号输出端。
  2. 根据权利要求1所述的多频段低噪声放大器，其特征在于，每个所述开关切换单元还包括第三开关，每个所述第三开关的第一端连接至对应的输入匹配网络的输出端，每个所述第三开关的第二端接地。
  3. 根据权利要求1所述的多频段低噪声放大器，其特征在于，所述输出匹配网络包括可变电容器；
    所述可变电容器的第一端为所述输出匹配网络的输入端，与所述第二晶体管的漏极连接，所述可变电容器的第二端为所述输出匹配网络的输出端，与所 述放大输出开关连接。
  4. 根据权利要求3所述的多频段低噪声放大器，其特征在于，所述可变电容器包括第二电容组、第三电容组以及第四电容组；
    所述第二电容组包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容和第二电容切换开关，所述第三电容组包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容和第三电容切换开关，所述第四电容组包括一个或并联的多个第四电容支路，每个所述第四电容支路包括相连接的第四电容和第四电容切换开关；
    其中，所述第二电容支路的第一端与所述第三电容支路的第一端相连接以作为所述可变电容器的第一端，所述第二电容支路的第二端与所述第四电容支路的第一端相连接以作为所述可变电容器的第二端，所述第三电容支路的第二端和所述第四电容支路的第二端均接地。
  5. 根据权利要求1所述的多频段低噪声放大器，其特征在于，所述电阻衰减网络包括第四开关和可变电阻器；
    所述第四开关的第一端和所述可变电阻器的第一端相连接以作为所述电阻衰减网络的输入端，与所述旁路输出开关和所述放大输出开关连接，所述第四开关的第二端和所述可变电阻器的第二端相连接以作为所述电阻衰减网络的输出端，与所述信号输出端连接。
  6. 根据权利要求5所述的多频段低噪声放大器，其特征在于，所述可变电阻器包括第一电阻组、第二电阻组以及第三电阻组；
    所述第一电阻组包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻和第一电阻切换开关，所述第二电阻组包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻和第二电阻切换开关，所述第三电阻组包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻和第三电阻切换开关；
    其中，所述第一电阻支路的第一端与所述第二电阻支路的第一端相连接以作为所述可变电阻器的第一端，所述第一电阻支路的第二端与所述第三电阻支路的第一端相连接以作为所述可变电阻器的第二端，所述第二电阻支路的第二端和所述第三电阻支路的第二端均接地。
  7. 根据权利要求1所述的多频段低噪声放大器，其特征在于，所述共源级放大单元还包括第一偏置电阻和第二偏置电阻；
    所述第一偏置电阻的第一端与所述第一晶体管的栅极连接，所述第一偏置电阻的第二端连接第一偏置信号；所述第二偏置电阻的第一端与所述第二晶体管的栅极连接，所述第二偏置电阻的第二端连接第二偏置信号。
  8. 一种集成电路芯片，其特征在于，包括权利要求1-7任一项所述的多频段低噪声放大器。
  9. 一种电子设备，其特征在于，包括权利要求1-7任一项所述的多频段低噪声放大器。
PCT/CN2023/109830 2022-09-16 2023-07-28 多频段低噪声放大器、集成电路芯片及电子设备 WO2024055760A1 (zh)

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