WO2024053486A1 - Semiconductor device - Google Patents

Abstract

This semiconductor device comprises: a chip having a first main surface on one side and a second main surface on the other side; a first terminal that is disposed on the first main surface; a second terminal that is disposed on the second main surface; and a protection circuit that includes a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal, and that forms a discharge path for overvoltage generated between the first terminal and the second terminal. The protection transistor includes a plurality of trench gate structures each having an upper electrode and a lower electrode buried in the vertical direction sandwiching an insulator inside a trench formed in the first main surface.

Description

semiconductor equipment

This application claims priority based on patent application No. 2022-142473 filed with the Japan Patent Office on September 7, 2022, and the entire contents of this application are incorporated herein by reference. The present disclosure relates to a semiconductor device.

US Pat. No. 6,274,908 (Patent Document 1) discloses a protection circuit including a lateral field effect transistor as a discharge path.

US Patent No. 6,274,908

[overview]
The present disclosure provides overvoltage protection with a novel layout.

The present disclosure provides a chip having a main surface, an output region provided on the main surface, a protection region provided on the main surface, and a protective region formed on the main surface at a first interval in the output region. a protection transistor including an output transistor having a plurality of first trench gate structures; and a protection transistor including a plurality of second trench gate structures formed on the main surface at second intervals larger than the first interval in the protection region. and a protection circuit that forms an overvoltage discharge path.

The present disclosure provides a chip having a main surface, an output region provided on the main surface, a protection region provided on the main surface, and a first conductivity type drift region formed in a surface layer portion of the main surface. a first conductivity type high concentration drift region formed in a surface layer of the drift region in the output region and having a higher impurity concentration than the drift region; and a first conductivity type high concentration drift region located within the high concentration drift region in the output region. an output transistor having a first trench gate structure formed in the main surface so as to be located within the drift region in the protection region; and a second trench gate structure formed in the main surface such that the protection region is located within the drift region. A protection circuit having a transistor and forming an overvoltage discharge path is provided.

The present disclosure provides a chip having a first main surface on one side and a second main surface on the other side, a first terminal arranged on the first main surface, and a chip arranged on the second main surface. a second terminal; a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal; a protection circuit that forms a discharge path for overvoltage generated during the process, and the protection transistor includes an upper electrode buried vertically in a trench formed on the first main surface with an insulator sandwiched therebetween; A semiconductor device is provided that includes a plurality of trench gate structures each having a bottom electrode.

The present disclosure provides a chip having a first principal surface on one side and a second principal surface on the other side, a first terminal disposed on the first principal surface, and a first terminal disposed on the first principal surface. a second terminal disposed on the second main surface; a third terminal formed on the first main surface so as to be electrically interposed between the first terminal and the third terminal; a first protection circuit including a first protection transistor configured to form a discharge path for an overvoltage generated between the first terminal and the third terminal; and an electrical connection between the second terminal and the third terminal. a second protection circuit including a second protection transistor formed on the first main surface so as to be interposed therein, and forming a discharge path for an overvoltage generated between the second terminal and the third terminal; The first protection transistor includes a plurality of first upper electrodes and first lower electrodes each having a first upper electrode and a first lower electrode buried in a first trench formed in the first main surface in a vertical direction with a first insulator interposed therebetween. The second protection transistor includes a second upper electrode and a second trench buried vertically in a second trench formed on the first main surface with a second insulator in between. A semiconductor device is provided that includes a plurality of second trench gate structures each having a bottom electrode.

The above-mentioned and further objects, features and advantages will become apparent from the detailed description with reference to the accompanying drawings.

FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a sectional view taken along the line II-II shown in FIG. FIG. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device shown in FIG. 1. FIG. 4 is a schematic circuit diagram showing the configuration of the output transistor. FIG. 5 is a circuit diagram showing the first overvoltage protection circuit shown in FIG. 3. FIG. 6 is a circuit diagram showing the second overvoltage protection circuit shown in FIG. 3. FIG. 7 is a plan view showing the output area shown in FIG. 1. FIG. FIG. 8 is an enlarged plan view showing a main part of the output area shown in FIG. 7. FIG. FIG. 9 is an enlarged plan view showing further essential parts of the output area shown in FIG. 7. FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. 8. FIG. 11 is a sectional view taken along the line XI-XI shown in FIG. 8. FIG. 12 is a sectional view taken along the line XII-XII shown in FIG. 8. FIG. 13 is a sectional view taken along the line XIII-XIII shown in FIG. 8. FIG. 14 is a sectional view taken along the line XIV-XIV shown in FIG. 8. FIG. 15 is a plan view showing the first protection area shown in FIG. 1. FIG. 16 is an enlarged plan view showing a main part of the first protection area shown in FIG. 15. FIG. 17 is an enlarged plan view showing further essential parts of the first protection area shown in FIG. 15. FIG. 18 is a sectional view taken along the line XVIII-XVIII shown in FIG. 16. FIG. 19 is a sectional view taken along the line XIX-XIX shown in FIG. 16. FIG. 20 is a sectional view taken along line XX-XX shown in FIG. 16. FIG. 21 is a sectional view taken along the line XXI-XXI shown in FIG. 16. FIG. 22 is a cross-sectional view comparing the output area and the first protection area. FIG. 23 is a first graph showing the results of the TLP test. FIG. 24 is a second graph showing the results of the TLP test. FIG. 25 is a graph showing test results of gate threshold voltage. FIG. 26 is a plan view showing a first modification of the first protection area. FIG. 27 is a sectional view showing a second modification of the first protection area.

[Detailed explanation]
Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. The attached drawings are all schematic diagrams and are not strictly illustrated, and relative positional relationships, scales, proportions, angles, etc. do not necessarily match. Corresponding structures among the accompanying drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the abbreviation or simplification applies.

When the word "substantially" is used in this specification, this word includes a numerical value (form) that is equal to the numerical value (form) to be compared, as well as a value based on the numerical value (form) to be compared. Also includes numerical errors (form errors) in the range of ±10%. In the following explanation, words such as "first," "second," and "third" are used, but these are symbols added to the name of each structure to clarify the order of explanation. It is not given for the purpose of limiting the name of the structure.

FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment. FIG. 2 is a sectional view taken along the line II-II shown in FIG. Referring to FIGS. 1 and 2, semiconductor device 1 includes a chip 2 formed in the shape of a rectangular parallelepiped. Chip 2 is, in this embodiment, a Si chip containing a Si single crystal.

Of course, the chip 2 may be made of a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor that has a bandgap larger than that of Si. GaN (gallium nitride), SiC (silicon carbide), C (diamond), and the like are exemplified as wide bandgap semiconductors. For example, chip 2 may be a SiC chip containing a SiC single crystal.

The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. ing. The first main surface 3 and the second main surface 4 are formed into a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as seen from the normal direction Z thereof. The normal direction Z is also the thickness direction of the chip 2.

The first main surface 3 is a circuit surface on which various circuit structures forming an electronic circuit are formed. The second main surface 4 is a non-circuit surface having no circuit structure. The first side surface 5A and the second side surface 5B extend in a first direction ing. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposed to the first direction X (backwards).

The semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output area 6 is an area having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In this embodiment, the output area 6 is divided into an area on the first side surface 5A side of the first main surface 3. The output area 6 is divided into a polygonal shape (quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in plan view.

The position, size, planar shape, etc. of the output area 6 are arbitrary and are not limited to a specific layout. The output region 6 may have a planar area of 25% or more and 80% or less of the planar area of the first main surface 3. The planar area of the output region 6 may be 30% or more of the planar area of the first main surface 3. The planar area of the output region 6 may be 40% or more of the planar area of the first main surface 3. The planar area of the output region 6 may be 50% or more of the planar area of the first main surface 3. The planar area of the output region 6 may be 75% or less of the planar area of the first main surface 3.

The semiconductor device 1 includes a control region 7 provided in a region different from the output region 6 on the first main surface 3 . The control area 7 is an area including a plurality of types of electronic circuits (circuit devices) configured to generate control signals for controlling the output area 6. In this embodiment, the control region 7 is divided into a region on the second side surface 5B side with respect to the output region 6, and faces the output region 6 in the second direction Y. In this form, the control region 7 is divided into a polygonal shape (quadrilateral in this form) having four sides parallel to the periphery of the first principal surface 3 in plan view.

The position, size, planar shape, etc. of the control area 7 are arbitrary and are not limited to a specific layout. The control region 7 may have a planar area of 25% or more and 80% or less of the planar area of the first main surface 3. The planar area of the control region 7 may be 30% or more of the planar area of the first main surface 3. The planar area of the control region 7 may be 40% or more of the planar area of the first main surface 3. The planar area of the control region 7 may be 50% or more of the planar area of the first main surface 3. The planar area of the control region 7 may be 75% or less of the planar area of the first main surface 3.

The planar area of the control region 7 may be approximately equal to the planar area of the output region 6. The planar area of the control region 7 may be larger than the planar area of the output region 6. The planar area of the control region 7 may be smaller than the planar area of the output region 6. The ratio of the planar area of the control region 7 to the planar area of the output region 6 may be 0.1 or more and 4 or less.

The semiconductor device 1 includes a first protection region 8 provided in a region different from the output region 6 on the first main surface 3 . The first protected area 8 is an area having an electronic circuit (circuit device) configured to protect the protected area from external overvoltage.

For example, the overvoltage may be a surge voltage caused by static electricity or the like. The first protection area 8 is also an area that protects the protected area from destruction caused by ESD (Electro Static Discharge). The first protection area 8 may be referred to as a "first ESD protection area". The protected area includes an output area 6 and a control area 7.

The position, size, planar shape, etc. of the first protection area 8 are arbitrary and are not limited to a specific layout. It is preferable that the first protection region 8 has a planar area that is less than the planar area of the output region 6 . In this embodiment, the first protection region 8 has a planar area that is less than the planar area of the control region 7 and is incorporated within the control region 7 . The first protection area 8 may be regarded as one component of the control area 7 . The first protection area 8 is arranged inward of the control area 7 in this embodiment.

The planar area of the first protection region 8 is preferably 1/10 or less of the planar area of the output region 6. It is particularly preferable that the planar area of the first protection region 8 is 1/25 or less of the planar area of the output region 6. The planar area of the first protection region 8 may be 1/50 or less of the planar area of the output region 6. The planar area of the first protection region 8 may be 1/100 or less of the planar area of the output region 6.

The semiconductor device 1 includes a second protection region 9 provided in a region different from the output region 6 on the first main surface 3 . The second protected area 9 is an area having an electronic circuit (circuit device) configured to protect the protected area from external overvoltage.

For example, the overvoltage may be a surge voltage caused by static electricity or the like. The second protected area 9 is also an area that protects the protected area from destruction due to ESD. The second protection area 9 may be referred to as a "second ESD protection area". The protected area includes an output area 6 and a control area 7.

The position, size, planar shape, etc. of the second protection area 9 are arbitrary and are not limited to a specific layout. It is preferable that the second protection region 9 has a planar area less than the planar area of the output region 6.

In this form, the second protection region 9 has a planar area smaller than the planar area of the control region 7 and is incorporated in a region different from the first protection region 8 within the control region 7 . The second protection area 9 may be considered as one component of the control area 7 . In this embodiment, the second protection area 9 is arranged at the periphery of the control area 7 . Specifically, the second protection area 9 is arranged closer to the peripheral edge of the first main surface 3 than the first protection area 8 is.

The planar area of the second protection region 9 is preferably 1/10 or less of the planar area of the output region 6. It is particularly preferable that the planar area of the second protection region 9 is 1/25 or less of the planar area of the output region 6. The planar area of the second protection region 9 may be 1/50 or less of the planar area of the output region 6. The planar area of the second protection region 9 may be 1/100 or less of the planar area of the output region 6.

In this form, the planar area of the second protection region 9 is larger than the planar area of the first protection region 8. Of course, the planar area of the second protection region 9 may be approximately equal to the planar area of the first protection region 8. Further, the planar area of the second protection region 9 may be less than the planar area of the first protection region 8.

Semiconductor device 1 includes an n-type (first conductivity type) drain region 10 formed in a surface layer portion of second main surface 4 . The n-type impurity concentration of the drain region 10 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The drain region 10 is formed in a layer shape extending along the second main surface 4 over the entire surface layer of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. .

The drain region 10 may have a thickness of 50 μm or more and 200 μm or less. The thickness of the drain region 10 is preferably 150 μm or less. In this embodiment, the drain region 10 is formed of an n-type semiconductor substrate (Si substrate).

Semiconductor device 1 includes an n-type drift region 11 formed in the surface layer of first main surface 3 . Drift region 11 has a lower n-type impurity concentration than drain region 10. The n-type impurity concentration of the drift region 11 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

The drift region 11 is formed in a layered manner extending along the first main surface 3 in the output region 6 , control region 7 , first protection region 8 , and second protection region 9 . Specifically, the drift region 11 is formed in a layered shape extending along the first main surface 3 over the entire surface layer portion of the first main surface 3, and includes the first main surface 3 and the first to fourth side surfaces 5A to 5D. exposed from.

The drift region 11 is electrically connected to the drain region 10 within the chip 2. Drift region 11 has a thickness less than the thickness of drain region 10 . The thickness of the drift region 11 may be 1 μm or more and 20 μm or less. The thickness of the drift region 11 is preferably 5 μm or more and 15 μm or less. It is particularly preferable that the thickness of the drift region 11 is 10 μm or less. In this embodiment, the drift region 11 is formed of an n-type epitaxial layer (Si epitaxial layer).

The semiconductor device 1 includes an interlayer insulating layer 12 covering the first main surface 3. The interlayer insulating layer 12 collectively covers the output region 6 , the control region 7 , the first protection region 8 , and the second protection region 9 . The interlayer insulating layer 12 may cover the entire first main surface 3 so as to be continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the interlayer insulating layer 12 may be formed at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.

In this form, the interlayer insulating layer 12 has a multilayer wiring structure having a laminated structure in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated. Each insulating layer may include at least one of a silicon oxide film and a silicon nitride film. Each wiring layer includes at least one of a pure Al layer (an Al layer with a purity of 99% or more), a Cu layer (a Cu layer with a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. May contain.

The semiconductor device 1 includes a plurality of terminals 13 to 15 arranged on either one or both (in this embodiment, both) of the first main surface 3 and the second main surface 4. The plurality of terminals 13 to 15 include a source terminal 13, a plurality of control terminals 14, and a drain terminal 15.

In this embodiment, the source terminal 13 is provided as an output terminal electrically connected to a load, and is arranged on a portion of the interlayer insulating layer 12 that covers the output region 6. The source terminal 13 may cover the entire output region 6 in plan view. The source terminal 13 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

The plurality of control terminals 14 are terminals that are electrically connected to various electronic circuits within the control region 7 , and are arranged on the portion of the interlayer insulating layer 12 that covers the control region 7 . The plurality of control terminals 14 each have a planar area less than the planar area of the source terminal 13, and are arranged at intervals along the peripheral edge of the control region 7 (the peripheral edge of the first main surface 3).

The planar area of each control terminal 14 is set within a range to which a bonding wire can be connected. The planar area of each control terminal 14 may be 1/10 or less of the planar area of the source terminal 13. The plurality of control terminals 14 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

The plurality of control terminals 14 include at least one ground terminal 14a that is fixed to a ground potential, and at least one input terminal 14b that applies an electrical signal to the control region 7. The location of the ground terminal 14a is arbitrary. The ground terminal 14a may be arranged inward of the control region 7, along one side of the first main surface 3, or along one side of the first main surface 3 in a plan view. It may be placed at a corner. The ground terminal 14a is connected to a bonding wire, and a ground potential is applied from the outside via the bonding wire.

The input terminal 14b can be placed at any location. The input terminal 14b may be disposed inward of the control region 7, along one side of the first principal surface 3, or along one side of the first principal surface 3 in plan view. It may be placed at a corner. In this embodiment, the input terminal 14b is arranged adjacent to the second protection region 9 in plan view. Of course, the input terminal 14b may cover the second protection area 9.

In this embodiment, an example is shown in which the input terminal 14b is a test terminal into which a test signal for testing the electrical characteristics of the control circuit 23 is input during the manufacturing process. The test terminal is a terminal that is provided as a contact target of a probe of an electrical property testing device and is configured to receive a test signal from the probe.

The input terminal 14b is a structure to which bonding wires are not connected in the semiconductor device 1 after manufacture. In other words, the input terminal 14b is formed as an open terminal (dummy terminal). An open terminal is a terminal that does not receive a signal (potential) from the outside and is formed in an electrically floating state.

For example, when the semiconductor device 1 is mounted on a semiconductor package, the entire input terminal 14b is covered with an insulator (for example, a sealing resin containing a plurality of fillers and a matrix resin) and is electrically insulated from other structures. Ru. Of course, the input terminal 14b may be electrically connected to a lead terminal of the semiconductor package via a bonding wire, so that the test signal can be input even after the semiconductor device 1 is mounted on the semiconductor package.

In this embodiment, the drain terminal 15 is provided as a power supply terminal and directly covers the second main surface 4 of the chip 2. That is, in this embodiment, the semiconductor device 1 is a high-side switching device that is electrically interposed between a power source and a load. Drain terminal 15 is electrically connected to drain region 10 on second main surface 4 . The drain terminal 15 covers the entire second main surface 4 so as to be continuous with the peripheral edge of the second main surface 4 (first to fourth side surfaces 5A to 5D).

FIG. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in FIG. 1. FIG. 4 is a schematic circuit diagram showing the configuration of the output transistor 20. FIG. 5 is a circuit diagram showing the first overvoltage protection circuit 39 shown in FIG. 3. FIG. 6 is a circuit diagram showing the second overvoltage protection circuit 49 shown in FIG. 3.

In FIG. 3, in order to show an example of the operation of the semiconductor device 1, an example is shown in which an inductive load L as an example of a load is electrically connected to the source terminal 13. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be referred to as an "inductive load drive device" or an "inductive load control device." Examples of the inductive load L include relays, solenoids, lamps, motors, and the like. The inductive load L may be a vehicle-mounted inductive load. That is, the semiconductor device 1 may be a vehicle-mounted semiconductor device.

Referring to FIGS. 3 and 4, semiconductor device 1 includes an output transistor 20 formed in output region 6. Output transistor 20, in this form, consists of a split-gate transistor including one main drain, one main source, and multiple main gates. The main drain is electrically connected to the drain terminal 15. The main source is electrically connected to the source terminal 13.

The plurality of main gates are configured so that a plurality of electrically independent gate signals (gate potentials) are individually input. Output transistor 20 generates a single output current Io (output signal) in response to multiple gate signals. In other words, the output transistor 20 is a multi-input single-output switching device. The output current Io is a drain-source current flowing between the main drain and the main source. The output current Io is output to the outside of the chip 2 (inductive load L) via the source terminal 13.

The output transistor 20 includes a plurality (two or more) of system transistors 21 that are electrically independently controlled. In this embodiment, the plurality of system transistors 21 include a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are collectively formed in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are individually inputted, and the system transistors 21 in an on state and the system transistors 21 in an off state coexist.

The plurality of system transistors 21 each include a system drain, a system source, and a system gate. The plurality of system drains are electrically connected to the main drain (drain terminal 15). The plurality of system sources are electrically connected to the main source (source terminal 13). Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.

The plurality of system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and system source of each system transistor 21. The plurality of system currents Is may have different values or may have substantially equal values. The plurality of system currents Is are added between the main drain and the main source. As a result, a single output current Io is generated from the sum of the plurality of system currents Is.

Referring to FIG. 4, the plurality of system transistors 21 each include a single or a plurality of unit transistors 22 that are systematized (grouped) as individual control targets. Specifically, the plurality of system transistors 21 are configured by a single unit transistor 22 or a parallel circuit including a plurality of unit transistors 22.

In this form, the plurality of unit transistors 22 are each of a trench gate vertical type. The plurality of system transistors 21 may be composed of the same number of unit transistors 22 or may be composed of different numbers of unit transistors 22.

Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

The plurality of unit transistors 22 each generate a unit current Iu in response to a corresponding gate signal. Each unit current Iu is a drain-source current flowing between the unit drain and unit source of each unit transistor 22. The plurality of unit currents Iu may have different values or may have substantially equal values. Multiple unit currents Iu are summed between corresponding system drains and system sources. As a result, a system current Is consisting of the sum of a plurality of unit currents Iu is generated.

In this way, the output transistor 20 is configured such that the first system transistor 21A and the second system transistor 21B are controlled to be turned on and off electrically independent of each other. That is, the output transistor 20 is configured such that both the first system transistor 21A and the second system transistor 21B are turned on at the same time. Further, the output transistor 20 is configured such that one of the first system transistor 21A and the second system transistor 21B is in an on state, and the other is in an off state.

When both the first system transistor 21A and the second system transistor 21B are turned on at the same time, the channel utilization rate of the output transistor 20 increases and the on-resistance decreases. When either the first system transistor 21A or the second system transistor 21B is turned on while the other is turned off, the channel utilization rate of the output transistor 20 decreases and the on-resistance increases. That is, the output transistor 20 is composed of a variable on-resistance switching device.

The semiconductor device 1 includes a control circuit 23 formed in the control region 7 so as to be electrically connected to the output transistor 20. The control circuit 23 may also be referred to as a "control IC." The control circuit 23 includes various functional circuits, and together with the output transistor 20 constitutes an IPD (Intelligent Power Device). IPDs may be referred to as "IPM (Intelligent Power Module)," "IPS (Intelligent Power Switch)," "smart power driver," "smart MISFET," or "protected MISFET." .

In this form, the control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, a low voltage malfunction avoidance circuit 28, a load open detection circuit 29, an active clamp circuit 30, and a power supply reverse circuit. It includes a connection protection circuit 31, a logic circuit 32, and a test circuit 33. The control circuit 23 does not necessarily need to include all of these functional circuits at the same time, but only needs to include at least one of these functional circuits.

The current monitor circuit 25 may be called a CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may be called an OCP circuit (Over Current Protection circuit). The overheat protection circuit 27 may be referred to as a TSD circuit (thermal shut down circuit). The low voltage malfunction avoidance circuit 28 may be referred to as a UVLO circuit (Under Voltage Lock Out circuit). The load open detection circuit 29 may be called an OLD circuit (Open Load Detection circuit). The power supply reverse connection protection circuit 31 may be called an RBP circuit (Reverse Battery Protection circuit).

The gate control circuit 24 is configured to generate a gate signal that controls on/off of the output transistor 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control on/off of the plurality of system transistors 21. That is, in this embodiment, the gate control circuit 24 provides a first gate signal that individually controls on/off of the first system transistor 21A, and a first gate signal that individually controls on/off of the first system transistor 21A, and a first gate signal that individually controls the second system transistor 21B electrically independently from the first system transistor 21A. A second gate signal is generated to perform on/off control.

The current monitor circuit 25 generates a monitor current that monitors the output current Io of the output transistor 20, and outputs it to other circuits. For example, the monitor circuit may include a transistor having a similar configuration to the output transistor 20, and may be configured to generate a monitor current linked to the output current Io by being turned on and off at the same time as the output transistor 20. . Of course, the current monitor circuit 25 may be configured to generate a monitor current linked to one or more system currents Is.

The overcurrent protection circuit 26 generates an electric signal to control the gate control circuit 24 based on the monitor current from the current monitor circuit 25, and controls the on/off of the output transistor 20 in cooperation with the gate control circuit 24.

For example, the overcurrent protection circuit 26 determines that the output transistor 20 is in an overcurrent state when the monitor current exceeds a predetermined threshold, and cooperates with the gate control circuit 24 to monitor the output transistor 20 (multiple system It may be configured to control part or all of the transistor 21) to be in an off state. Further, the overcurrent protection circuit 26 may be configured to shift the output transistor 20 to normal operation in cooperation with the gate control circuit 24 when the monitor current becomes less than a predetermined threshold value.

The overheat protection circuit 27 includes a first temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the output region 6 and a second temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the control region 7. The overheat protection circuit 27 generates an electric signal for controlling the gate control circuit 24 based on a first temperature detection signal from the first temperature sensing device and a second temperature detection signal from the second temperature sensing device, and controls the gate control circuit 24. 24 to control on/off of the output transistor 20.

For example, the overheating protection circuit 27 determines that the output region 6 is in an overheating state when the difference value between the first temperature detection signal and the second temperature detection signal exceeds a predetermined threshold value, and cooperates with the gate control circuit 24. The output transistor 20 (the plurality of system transistors 21) may be controlled to turn off some or all of the output transistors 20 (the plurality of system transistors 21). Further, the overheat protection circuit 27 may be configured to shift the output transistor 20 to normal operation in cooperation with the gate control circuit 24 when the difference value becomes less than a predetermined threshold value.

The low voltage malfunction avoidance circuit 28 is configured to prevent various functional circuits within the control circuit 23 from malfunctioning when the starting voltage for starting the control circuit 23 is less than a predetermined value. For example, the low voltage malfunction avoidance circuit 28 may be configured to start the control circuit 23 when the starting voltage becomes equal to or higher than a predetermined threshold voltage, and to stop the control circuit 23 when the starting voltage becomes less than the threshold voltage. . The threshold voltage may have hysteresis characteristics.

The load open detection circuit 29 determines the electrical connection state of the inductive load L. For example, the load open detection circuit 29 is configured to monitor the voltage between the terminals of the output transistor 20 and determine that the inductive load L is in an open state when the voltage between the terminals exceeds a predetermined threshold value. You can leave it there. For example, the load open detection circuit 29 may be configured to determine that the inductive load L is in the open state when the monitor current becomes equal to or less than a predetermined threshold.

The active clamp circuit 30 is electrically connected to the main drain of the output transistor 20 and at least one main gate (for example, the system gate of the first system transistor 21A). The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in reverse bias series to the Zener diode. The pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 20.

The active clamp circuit 30 cooperates with the gate control circuit 24 to turn on some or all of the output transistor 20 when a back electromotive voltage caused by the inductive load L is applied to the output transistor 20. It is composed of Specifically, the output transistor 20 is controlled in multiple types of operation modes including normal operation, first OFF operation, active clamp operation, and second OFF operation.

In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be on at the same time. This increases the channel utilization rate of the output transistor 20 and reduces the on-resistance. In the first off operation, both the first system transistor 21A and the second system transistor 21B are controlled from the on state to the off state at the same time. As a result, a back electromotive voltage caused by the inductive load L is applied to both the first system transistor 21A and the second system transistor 21B.

The active clamp operation is an operation in which the output transistor 20 absorbs (consumes) the energy stored in the inductive load L, and is executed when the back electromotive force caused by the inductive load L exceeds a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled from an off state to an on state, and at the same time, the second system transistor 21B is controlled (maintained) to an off state.

The channel utilization rate of the output transistor 20 during active clamp operation is less than the channel utilization rate of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is larger than the on-resistance of the output transistor 20 during normal operation. This suppresses a rapid temperature rise of the output transistor 20 during active clamp operation, and improves active clamp durability.

The second off operation is performed when the back electromotive voltage becomes less than a predetermined threshold voltage. In the second off operation, the first system transistor 21A is controlled from the on state to the off state, and at the same time, the second system transistor 21B is controlled (maintained) at the off state. In this way, the back electromotive voltage (energy) of the inductive load L is absorbed by a portion of the output transistor 20 (here, the first system transistor 21A). Of course, during the active clamp operation, the first system transistor 21A may be controlled (maintained) in the off state, and at the same time, the second system transistor 21B may be controlled in the on state.

The power supply reverse connection protection circuit 31 is configured to detect a reverse voltage when the power supply is reversely connected, and protect the control circuit 23 and the output transistor 20 from the reverse voltage (reverse current). The logic circuit 32 is configured to generate electrical signals that are supplied to various circuits within the control circuit 23.

The test circuit 33 is formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15, and is electrically connected to the input terminal 14b and the drain terminal 15. The test circuit 33 is formed to indirectly evaluate the electrical characteristics of the control circuit 23 during the manufacturing process. The test circuit 33 is preferably arranged in a region adjacent to the second protection region 9 and/or in a region adjacent to the input terminal 14b in plan view.

Referring to FIGS. 1, 3, and 5, semiconductor device 1 includes a first overvoltage protection circuit 39 formed in first protection region 8. The first overvoltage protection circuit 39 may be referred to as a "first ESD protection circuit." The first overvoltage protection circuit 39 may be considered as one component of the control circuit 23.

The first overvoltage protection circuit 39 is electrically interposed between the ground terminal 14a (control terminal 14) and the drain terminal 15, and is a discharge path ( The first discharge path is configured to form a first discharge path. Specifically, the first overvoltage protection circuit 39 forms a discharge path for the first overvoltage Vs1 generated at the drain terminal 15 with reference to the ground terminal 14a. A surge voltage caused by static electricity or the like from a power source is exemplified as the first overvoltage Vs1.

In this embodiment, the first overvoltage protection circuit 39 is configured to limit the first overvoltage Vs1 to a clamp voltage Vc that is less than the first overvoltage Vs1. Specifically, the first overvoltage protection circuit 39 includes a first protection transistor 40 and a clamp circuit 41. In this embodiment, the first protection transistor 40 is formed on the first main surface 3 in the first protection region 8 , and the clamp circuit 41 is formed on the first main surface 3 in a region outside the first protection region 8 . For example, the clamp circuit 41 may be formed in a region around the first protection region 8 so as to be adjacent to the first protection region 8 .

The first protection transistor 40 includes a drain, a source, a gate, and a back gate. Regarding the first protection transistor 40, the drain is electrically connected to the drain terminal 15, the source is electrically connected to the ground terminal 14a, the gate forms a node part for the clamp circuit 41, and the back gate is connected to the ground terminal 14a. electrically connected. In this embodiment, the source of the first protection transistor 40 is electrically connected to the ground terminal 14a via the power supply reverse connection protection circuit 31.

Clamp circuit 41 includes a first diode stage 42 and a second diode stage 43. First diode stage 42 includes a first anode portion and a first cathode portion. The first anode portion of the first diode stage 42 forms a node portion for the second diode stage 43 . A first cathode portion of the first diode stage 42 is electrically connected to the drain of the first protection transistor 40 (drain terminal 15).

The first diode stage 42 includes m Zener diodes (m≧1). The first diode stage 42 may be composed of a single Zener diode or a plurality of Zener diodes connected in series in the forward direction. The number of Zener diodes is adjusted by the voltage Vz×m across the first diode stage 42 to be achieved.

The second diode stage 43 includes a second anode section and a second cathode section. The second anode portion of the second diode stage 43 is electrically connected to the first anode portion of the first diode stage 42 . A second cathode portion of the second diode stage 43 is electrically connected to the gate of the first protection transistor 40 .

The second diode stage 43 includes n (n≧1) pn junction diodes. The second diode stage 43 may be composed of a single pn junction diode, or may be composed of a plurality of pn junction diodes connected in series in the forward direction. The number of pn junction diodes is adjusted by the voltage Vf×n across the second diode stage 43 to be achieved. The second diode stage 43 is an anti-backflow diode that prevents backflow from the first protection transistor 40 .

When the first overvoltage Vs1, which is equal to or higher than the breakdown voltage of the first diode stage 42, is applied to the drain terminal 15, the first diode stage 42 enters the breakdown state, and the gate voltage of the first protection transistor 40 becomes equal to or higher than the gate threshold voltage. become. As a result, the first protection transistor 40 is turned on, and an overcurrent (first overcurrent) flows from the drain terminal 15 to the ground terminal 14a via the first protection transistor 40. In other words, the overcurrent flows from the second main surface 4 to the first main surface 3 in the chip 2 .

In this manner, when the first overvoltage Vs1 occurs, the first overvoltage protection circuit 39 forms a bypass path (discharge path) for the overcurrent from the drain terminal 15 to the ground terminal 14a, and The voltage between the terminals is limited to the clamp voltage Vc.

As a result, the first overvoltage protection circuit 39 protects the control circuit 23 and the output transistor 20 from the first overvoltage Vs1. The clamp voltage Vc includes the sum of the gate threshold voltage Vgth of the first protection transistor 40 and the inter-terminal voltage Vz×m of the first diode stage 42.

The first protection transistor 40 has a configuration in which a bias voltage caused by the first overvoltage Vs1 is applied to the gate, while a gate signal from the control circuit 23 (gate control circuit 24) etc. is not input to the gate. In this respect, it has a different configuration from the output transistor 20.

Referring to FIGS. 1, 3, and 6, semiconductor device 1 includes a second overvoltage protection circuit 49 formed in second protection region 9. The second overvoltage protection circuit 49 may be referred to as a "second ESD protection circuit." The second overvoltage protection circuit 49 may be considered as one component of the control circuit 23.

The second overvoltage protection circuit 49 is electrically interposed between the input terminal 14b (control terminal 14) and the drain terminal 15, and the second overvoltage protection circuit 49 is a discharge path ( The second discharge path) is configured to form a second discharge path. Specifically, the second overvoltage protection circuit 49 forms a discharge path for the second overvoltage Vs2 generated at the input terminal 14b with the drain terminal 15 as a reference. A surge voltage caused by static electricity or the like that may occur when the input terminal 14b is brought into contact with the probe is exemplified as the second overvoltage Vs2.

The second overvoltage protection circuit 49 has a different circuit configuration from the first overvoltage protection circuit 39. In this embodiment, the second overvoltage protection circuit 49 includes a second protection transistor 50 . The second protection transistor 50 includes a drain, a source, a gate, and a back gate. Regarding the second overvoltage protection circuit 49, the drain is electrically connected to the drain terminal 15, the source is electrically connected to the input terminal 14b, the gate is electrically connected to the input terminal 14b, and the back gate is electrically connected to the input terminal 14b. electrically connected to.

In other words, the second protection transistor 50 has a gate that is diode-connected to the source. Therefore, in the second overvoltage protection circuit 49, the gate is fixed at the same potential as the source, so the gate voltage does not exceed the gate threshold voltage. The second protection transistor 50 functions as a diode connected between the input terminal 14b and the drain terminal 15 in the forward direction with respect to the drain terminal 15. Specifically, the diode is a body diode (pn junction diode) of the second protection transistor 50.

When the second overvoltage Vs2, which is higher than the forward threshold voltage of the second protection transistor 50 as a diode, is applied to the input terminal 14b, the second protection transistor 50 is turned on, and the second protection transistor 50 is connected to the input terminal via the second protection transistor 50. An overcurrent (second overcurrent) flows from 14b toward the drain terminal 15. In other words, the overcurrent flows from the first main surface 3 to the second main surface 4 in the chip 2 . The current direction related to the second protection transistor 50 is opposite to the current direction related to the first protection transistor 40 with respect to the thickness direction of the chip 2.

In this way, when the second overvoltage Vs2 occurs, the second overvoltage protection circuit 49 forms a bypass path (discharge path) for the overcurrent from the input terminal 14b to the drain terminal 15. As a result, the second overvoltage protection circuit 49 protects the control circuit 23 and the output transistor 20 from the second overvoltage Vs2.

The second protection transistor 50 has a configuration in which a bias voltage caused by the second overvoltage Vs2 is applied to the gate, but a gate signal from the control circuit 23 (gate control circuit 24) etc. is not input to the gate. In this respect, it has a different configuration from the output transistor 20.

5 and 6 show an example in which the first overvoltage protection circuit 39 and the second overvoltage protection circuit 49 have mutually different circuit configurations. However, the first overvoltage protection circuit 39 may have the same circuit configuration as the second overvoltage protection circuit 49 (see FIG. 6). Further, the second overvoltage protection circuit 49 may have the same circuit configuration as the first overvoltage protection circuit 39 (see FIG. 5).

Of course, overvoltage protection circuits such as the first overvoltage protection circuit 39 and the second overvoltage protection circuit 49 may be provided for other control terminals 14 where overvoltage may occur. Further, the second overvoltage protection circuit 49 does not necessarily need to be electrically connected to the test circuit 33, and may be used only as a discharge path for static electricity caused by the probe.

Hereinafter, the configuration on the output area 6 side will be explained with reference to FIGS. 7 to 14. FIG. 7 is a plan view showing the output area 6 shown in FIG. 1. FIG. 8 is an enlarged plan view showing a main part of the output area 6 shown in FIG. 7. FIG. FIG. 9 is an enlarged plan view showing further essential parts of the output area 6 shown in FIG. 7. As shown in FIG. FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. 8. FIG. 11 is a sectional view taken along the line XI-XI shown in FIG. 8. FIG. 12 is a sectional view taken along the line XII-XII shown in FIG. 8. FIG. 13 is a sectional view taken along the line XIII-XIII shown in FIG. 8. FIG. 14 is a sectional view taken along the line XIV-XIV shown in FIG. 8.

The semiconductor device 1 includes a first trench isolation structure 60 formed on the first main surface 3 to partition the output region 6. The first trench isolation structure 60 may be referred to as a "first region isolation structure." The first trench isolation structure 60 electrically isolates the output region 6 from the control region 7 , the first protection region 8 and the second protection region 9 within the chip 2 . A source potential is applied to the first trench isolation structure 60.

The first trench isolation structure 60 is formed in an annular shape surrounding the output region 6 in plan view. In this form, the first trench isolation structure 60 is formed into a polygonal ring shape (quadrangular ring shape in this form) having four sides parallel to the periphery of the first main surface 3 in plan view. The first trench isolation structure 60 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 interposed therebetween.

The first trench isolation structure 60 has a first width W1. The first width W1 is a width in a direction perpendicular to the extending direction of the first trench isolation structure 60. The first width W1 may be 0.4 μm or more and 2.5 μm or less. The first width W1 is 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1 It may have a value belonging to any one range of .75 μm or more and 2 μm or less. The first width W1 is preferably 1.25 μm or more and 1.75 μm or less.

The first trench isolation structure 60 has a first depth D1. The first depth D1 may be greater than or equal to 1 μm and less than or equal to 6 μm. The first depth D1 may have a value belonging to any one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, and 5 μm to 6 μm. The first depth D1 is preferably 3 μm or more and 5 μm or less.

The first trench isolation structure 60 includes a first isolation trench 61, a first isolation insulating film 62, and a first isolation electrode 63. That is, the first trench isolation structure 60 has a single electrode structure including a single electrode (first isolation electrode 63) buried in the first isolation trench 61 with an insulator (first isolation insulating film 62) in between. are doing.

The first isolation trench 61 is formed on the first main surface 3 and partitions the wall surface of the first trench isolation structure 60. The first isolation insulating film 62 covers the wall surface of the first isolation trench 61. The first isolation insulating film 62 may include a silicon oxide film. The first isolation insulating film 62 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The first isolation electrode 63 is buried in the first isolation trench 61 with the first isolation insulating film 62 interposed therebetween. The first separated electrode 63 may include conductive polysilicon.

The semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The following configuration will be explained as a component of the semiconductor device 1, but it is also a component of the output transistor 20.

Semiconductor device 1 includes an n-type high concentration drift region 64 formed in the surface layer of drift region 11 in output region 6 . High concentration drift region 64 has a higher n-type impurity concentration than drift region 11 . The n-type impurity concentration of the high concentration drift region 64 may be lower than the n-type impurity concentration of the drain region 10. The n-type impurity concentration of the high concentration drift region 64 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ^{−3 or} less. High concentration drift region 64 may be regarded as a high concentration portion of drift region 11 .

The high concentration drift region 64 forms a concentration gradient in which the n-type impurity concentration increases from the bottom side of the drift region 11 toward the first main surface 3 side. That is, the drift region 11 of the output region 6 has a concentration gradient formed by the high concentration drift region 64 such that the n-type impurity concentration increases from the bottom side toward the first main surface 3 side.

The high concentration drift region 64 is formed in the inner part of the output region 6 at a distance from the first trench isolation structure 60. Therefore, the heavily doped drift region 64 is surrounded by the drift region 11 in the output region 6 and is not in contact with the first trench isolation structure 60 . High concentration drift region 64 locally increases the n-type impurity concentration of drift region 11 in output region 6 .

The high concentration drift region 64 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 in between. High concentration drift region 64 has a bottom located closer to the bottom of drift region 11 than the bottom wall of first trench isolation structure 60 . The bottom of the high concentration drift region 64 meanders toward one side and the other side in the thickness direction in cross-sectional view.

Specifically, the bottom of the high concentration drift region 64 has a plurality of bulges 65 and a plurality of depressions 66 in cross-sectional view. The plurality of bulges 65 are portions that bulge out in an arc shape toward the bottom side of the drift region 11 . The plurality of bulges 65 are each formed in a band shape that is continuous in the first direction X and extends in the second direction Y when viewed from above. Each bulge 65 is formed wider than the first trench isolation structure 60 in the first direction X.

The plurality of depressions 66 are each formed in a band shape extending in the second direction Y in the region between the plurality of bulges 65. The plurality of depressions 66 are portions where the shallow parts of the plurality of bulges 65 are connected, and are located on the first main surface 3 side with respect to the deepest part of the plurality of bulges 65. Of course, the high concentration drift region 64 may have a flat bottom without meandering up and down in the thickness direction.

The high concentration drift region 64 may have a high concentration throughout the entire drift region 11 within the output region 6. According to such a configuration, the on-resistance of the drift region 11 can be reduced by increasing the concentration of the drift region 11. However, in this case, it should be noted that the increase in carrier density in the drift region 11 may cause electric field concentration to occur more easily, resulting in a decrease in breakdown voltage. Therefore, in order to reduce the on-resistance while suppressing a decrease in breakdown voltage, it is preferable to introduce the high concentration drift region 64 into a part of the output region 6.

The semiconductor device 1 includes a p-type (second conductivity type) first body region 67 formed in the surface layer of the drift region 11 in the output region 6 . The first body region 67 extends in a layered manner along the first main surface 3 throughout the output region 6 and is connected to the wall surface of the first trench isolation structure 60 . That is, the first body region 67 is not formed in a region outside the first trench isolation structure 60 in this embodiment.

The first body region 67 is formed shallower than the high concentration drift region 64. Specifically, the first body region 67 is formed shallower than the first trench isolation structure 60 and has a bottom portion located closer to the first main surface 3 than the bottom wall of the first trench isolation structure 60. There is. The bottom of the first body region 67 is preferably located closer to the first main surface 3 than the middle part of the depth range of the first trench isolation structure 60 .

The semiconductor device 1 includes a plurality of first trench gate structures 70 formed on the first main surface 3 in the output region 6. A plurality of first trench gate structures 70 are formed within the output region 6 and spaced apart from the first trench isolation structure 60 . The plurality of first trench gate structures 70 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the plurality of first trench gate structures 70 are arranged in a stripe shape extending in the second direction Y. The plurality of first trench gate structures 70 cross one end and the other end of the high concentration drift region 64 in the longitudinal direction (second direction Y).

The plurality of first trench gate structures 70 have a first end on one side in the longitudinal direction (second direction Y) and a second end on the other side in the longitudinal direction (second direction Y). . The first end portion is located in a region between the first trench isolation structure 60 and one end portion of the high concentration drift region 64 in plan view. The second end portion is located in a region between the first trench isolation structure 60 and the other end portion of the high concentration drift region 64 in plan view.

The plurality of first trench gate structures 70 penetrate the first body region 67 in cross-sectional view and are located within the high concentration drift region 64. The plurality of first trench gate structures 70 are formed at intervals from the bottom of the high concentration drift region 64 toward the first main surface 3 side, and are opposed to the drift region 11 with a part of the high concentration drift region 64 in between. There is.

The plurality of first trench gate structures 70 are formed to be shifted in the first direction X with respect to the plurality of depressions 66, and respectively face the plurality of bulges 65 in the thickness direction. It is preferable that the plurality of first trench gate structures 70 face the deepest parts of the plurality of bulges 65 . Such a configuration is obtained by introducing n-type impurities into the chip 2 from the wall surfaces of the plurality of first gate trenches 71 after the step of forming the plurality of first gate trenches 71.

The two first trench gate structures 70 located on both sides in the first direction X are preferably formed in a region outside the high concentration drift region 64. That is, the outermost first trench gate structure 70 penetrates the first body region 67 at a position spaced apart from the high concentration drift region 64 toward the first trench isolation structure 60 side, and is located within the drift region 11. Preferably. The outermost first trench gate structure 70 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 interposed therebetween.

The plurality of first trench gate structures 70 have a second width W2. The second width W2 is a width in a direction perpendicular to the extending direction of the first trench gate structure 70 (that is, the first direction X). The second width W2 may be approximately equal to the first width W1 of the first trench isolation structure 60. It is preferable that the second width W2 is less than or equal to the first width W1. It is particularly preferable that the second width W2 is less than the first width W1.

The second width W2 may be 0.4 μm or more and 2 μm or less. The second width W2 is 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1 It may have a value belonging to any one range of .75 μm or more and 2 μm or less. The second width W2 is preferably 0.8 μm or more and 1.2 μm or less.

The plurality of first trench gate structures 70 are arranged in the first direction X at a first interval I1. The first interval I1 is also the mesa width (first mesa width) of a mesa portion (first mesa portion) defined in a region between two first trench gate structures 70 adjacent to each other. The first interval I1 is preferably equal to or less than the first width W1 of the first trench isolation structure 60. It is preferable that the first interval I1 is less than or equal to the second width W2. It is particularly preferable that the first interval I1 is less than the second width W2.

The first interval I1 may be 0.4 μm or more and 0.8 μm or less. The first interval I1 is in the range of 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, and 0.7 μm or more and 0.8 μm or less. It may have a value to which it belongs. The first interval I1 is preferably 0.5 μm or more and 0.7 μm or less.

The first trench gate structure 70 has a second depth D2. The second depth D2 may be approximately equal to the first depth D1 of the first trench isolation structure 60. It is preferable that the second depth D2 is less than or equal to the first depth D1. It is particularly preferred that the second depth D2 is less than the first depth D1.

The second depth D2 may be 1 μm or more and 6 μm or less. The second depth D2 may have a value belonging to any one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, and 5 μm to 6 μm. The second depth D2 is preferably 2.5 μm or more and 4.5 μm or less.

The internal configuration of one first trench gate structure 70 will be described below. The first trench gate structure 70 includes a first gate trench 71 , a first insulating film 72 , a first upper electrode 73 , a first lower electrode 74 , and a first intermediate insulating film 75 . In other words, the first trench gate structure 70 includes a plurality of electrodes (a first upper electrode 73 and a first lower electrode 74).

The first gate trench 71 is formed on the first main surface 3 and partitions the wall surface of the first trench gate structure 70. The first insulating film 72 covers the wall surface of the first gate trench 71. The first insulating film 72 includes a first upper insulating film 76 and a first lower insulating film 77. The first upper insulating film 76 covers the bottom of the first body region 67 and the wall surface on the opening side of the first gate trench 71 .

The first upper insulating film 76 partially covers the bottom wall surface of the first gate trench 71 with respect to the bottom of the first body region 67 . The first upper insulating film 76 is thinner than the first isolation insulating film 62. The first upper insulating film 76 is formed as a gate insulating film. The first upper insulating film 76 may include a silicon oxide film. The first upper insulating film 76 preferably includes a silicon oxide film made of an oxide of the chip 2 .

The first lower insulating film 77 covers the bottom wall surface of the first gate trench 71 with respect to the bottom of the first body region 67 . The first lower insulating film 77 is thicker than the first upper insulating film 76 . The thickness of the first lower insulating film 77 may be approximately equal to the thickness of the first isolation insulating film 62. The first lower insulating film 77 may include a silicon oxide film. The first lower insulating film 77 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The first upper electrode 73 is buried on the opening side of the first gate trench 71 with the first insulating film 72 in between. Specifically, the first upper electrode 73 is buried on the opening side of the first gate trench 71 with the first upper insulating film 76 in between, and is buried in the first body region 67 and the high concentration region with the first upper insulating film 76 in between. It faces the drift region 64. The first upper electrode 73 may include conductive polysilicon.

The first lower electrode 74 is buried in the bottom wall side of the first gate trench 71 with the first insulating film 72 in between. Specifically, the first lower electrode 74 is buried in the bottom wall side of the first gate trench 71 with the first lower insulating film 77 in between, and faces the high concentration drift region 64 with the first lower insulating film 77 in between. are doing. The first lower electrode 74 of the outermost first trench gate structure 70 faces the drift region 11 with the first lower insulating film 77 interposed therebetween.

The first lower electrode 74 has an upper end portion that protrudes from the first lower insulating film 77 toward the first upper electrode 73 so as to be combined with the bottom portion of the first upper electrode 73 . The upper end of the first lower electrode 74 faces the first upper insulating film 76 across the lower end of the first upper electrode 73 in the lateral direction along the first main surface 3 . The first lower electrode 74 may include conductive polysilicon.

The first intermediate insulating film 75 is interposed between the first upper electrode 73 and the first lower electrode 74 and electrically insulates the first upper electrode 73 and the first lower electrode 74 within the first gate trench 71. There is. The first intermediate insulating film 75 is continuous with the first upper insulating film 76 and the first lower insulating film 77 . The first intermediate insulating film 75 is thinner than the first lower insulating film 77. The first intermediate insulating film 75 may include a silicon oxide film. The first intermediate insulating film 75 preferably includes a silicon oxide film made of the oxide of the first lower electrode 74 .

The semiconductor device 1 includes a plurality of first channel cells 78 formed on both sides of each first trench gate structure 70 to be controlled by each first trench gate structure 70. In this form, the two first channel cells 78 disposed on both sides of one first trench gate structure 70 are controlled by the one first trench gate structure 70 and are controlled by the other first trench gate structure 70. It is no longer controlled.

The plurality of first channel cells 78 are formed in a region along the inner part of the first trench gate structure 70 at intervals from both ends of the first trench gate structure 70 in the longitudinal direction (second direction Y). . The plurality of first channel cells 78 expose the first body region 67 from a region of the first main surface 3 sandwiched between both ends of the plurality of first trench gate structures 70 .

The plurality of first channel cells 78 face the high concentration drift region 64 across a part of the first body region 67 in the thickness direction. It is preferable that the plurality of first channel cells 78 be formed inward of the high concentration drift region 64 rather than the periphery of the high concentration drift region 64 in plan view.

Each first channel cell 78 includes a plurality of n-type first source regions 79 and a plurality of p-type first contact regions 80 . In FIG. 8, the first source region 79 is hatched for clarity. The first contact region 80 may be referred to as a "first back gate region." Each first source region 79 has a higher n-type impurity concentration than drift region 11 . Each first source region 79 may have a higher n-type impurity concentration than high concentration drift region 64. The n-type impurity concentration of each first source region 79 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

The plurality of first source regions 79 are arranged at intervals along each first trench gate structure 70. The plurality of first source regions 79 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3 side, and are located on the first upper side with the first insulating film 72 (first upper insulating film 76) in between. It faces the electrode 73.

Each first contact region 80 has a higher p-type impurity concentration than first body region 67. The p-type impurity concentration of each first contact region 80 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The plurality of first contact regions 80 are arranged alternately with the plurality of first source regions 79 along each first trench gate structure 70 . The plurality of first contact regions 80 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3 side, and are connected to the first upper insulating film 72 (first upper insulating film 76) with the first insulating film 72 (first upper insulating film 76) in between. It faces the electrode 73.

Regarding the two first channel cells 78 formed on both sides of one first trench gate structure 70, the plurality of first source regions 79 in one of the first channel cells 78 sandwich the first trench gate structure 70. and faces the plurality of first source regions 79 in the other first channel cell 78 . Further, the plurality of first contact regions 80 in one first channel cell 78 face the plurality of first contact regions 80 in the other first channel cell 78 with the first trench gate structure 70 in between. .

Of course, the plurality of first source regions 79 in one first channel cell 78 are opposed to the plurality of first contact regions 80 in the other first channel cell 78 with the first trench gate structure 70 in between. Good too. Further, the plurality of first contact regions 80 in one first channel cell 78 are opposed to the plurality of first source regions 79 in the other first channel cell 78 with the first trench gate structure 70 in between. Good too.

Regarding the two first channel cells 78 interposed between the two first trench gate structures 70, the plurality of first source regions 79 in one of the first channel cells 78 are arranged in the first direction It is connected to a plurality of first contact regions 80 within channel cell 78 . Further, the plurality of first contact regions 80 in one first channel cell 78 are connected in the first direction X to the plurality of first source regions 79 in the other first channel cell 78.

Of course, the plurality of first source regions 79 in one first channel cell 78 may be connected to the plurality of first source regions 79 in the other first channel cell 78 in the first direction X. Further, the plurality of first contact regions 80 in one first channel cell 78 may be connected to the plurality of first contact regions 80 in the other first channel cell 78 in the first direction X.

Of the two first channel cells 78 formed on both sides of the outermost first trench gate structure 70, the first channel cell 78 located on the inner side is located along a portion of the first body region 67 in the thickness direction. It faces the drift region 11 with a portion in between. On the other hand, the first channel cell 78 located on the outer side does not include the first source region 79 but only includes the first contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost first trench gate structure 70.

The output transistor 20 includes a plurality of unit transistors 22. The plurality of unit transistors 22 each include one first trench gate structure 70 and two first channel cells 78 formed on both sides of the one first trench gate structure 70. Regarding each unit transistor 22, one first trench gate structure 70 constitutes a unit gate, a plurality of first source regions 79 (two first channel cells 78) constitute a unit source, and a drain region 10 (drift region 11 and the high concentration drift region 64) constitute a unit drain.

The output transistor 20 includes a first system transistor 21A and a second system transistor 21B. The first system transistor 21A includes a plurality of unit transistors 22 that are systemized (grouped) as individual control targets. The second system transistor 21B includes a plurality of unit transistors 22 that are systemized (grouped) as individual control targets from a plurality of unit transistors 22 other than the first system transistor 21A.

In this form, the output transistor 20 includes a plurality of block regions 81 provided in the output region 6. The multiple block areas 81 include multiple first block areas 81A and multiple second block areas 81B. The plurality of first block regions 81A are regions in which one or more (in this embodiment, more than one) unit transistors 22 for the first system transistors 21A are arranged. The plurality of second block regions 81B are regions in which one or more (in this embodiment, more than one) unit transistors 22 for the second system transistors 21B are arranged.

The plurality of first block regions 81A are arranged at intervals in the first direction X. The number of unit transistors 22 in each first block region 81A is arbitrary. In this form, two unit transistors 22 are arranged in each first block region 81A. When the number of unit transistors 22 in each first block region 81A increases, the amount of heat generated in each first block region 81A increases. Therefore, the number of unit transistors 22 in each first block region 81A is preferably 2 or more and 5 or less.

The plurality of second block regions 81B are arranged alternately with the plurality of first block regions 81A along the first direction X so as to sandwich one first block region 81A. As a result, the heat generating parts caused by the plurality of first block regions 81A can be thinned out by the plurality of second block regions 81B, and at the same time, the heat generating parts caused by the plurality of second block regions 81B can be thinned out by the plurality of first block regions It can be thinned out by 81A.

The number of unit transistors 22 in each second block region 81B is arbitrary. In this form, two unit transistors 22 are arranged in each second block region 81B. When the number of unit transistors 22 in each second block region 81B increases, the amount of heat generated in each second block region 81B increases.

Therefore, the number of unit transistors 22 in each second block region 81B is preferably 2 or more and 5 or less. Considering in-plane temperature variations in the output region 6, it is preferable that the number of unit transistors 22 in the second block region 81B is the same as the number of unit transistors 22 in the first block region 81A.

The semiconductor device 1 includes a pair of first trench connection structures 90 that connect both ends of a plurality (two in this embodiment) of first trench gate structures 70 to be organized (grouped) in each block region 81. That is, the pair of first trench connection structures 90 respectively connect both ends of the plurality of first trench gate structures 70 to be systemized as system transistors 21.

The first trench connection structure 90 on one side connects the first ends of a plurality of (in this embodiment, two) corresponding first trench gate structures 70 in an arch shape in a plan view. The first trench connection structure 90 on the other side connects the second ends of a plurality of (in this embodiment, two) corresponding first trench gate structures 70 in an arch shape in a plan view.

Specifically, the first trench connection structure 90 on one side has a first portion extending in the first direction X and a plurality of (two in this form) second portions extending in the second direction Y. There is. The first portion faces the first ends of the plurality of first trench gate structures 70 in plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

The first trench connection structure 90 on the other side has a first portion extending in the first direction X and a plurality of (two in this form) second portions extending in the second direction Y. The first portion faces the second end portions of the plurality of first trench gate structures 70 in plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of first trench connection structures 90 constitute one annular or ladder-shaped trench structure with the plurality of first trench gate structures 70 in each block region 81 .

The plurality of first trench connection structures 90 are formed in a region between the first trench isolation structure 60 and the heavily doped drift region 64 and spaced apart from the first trench isolation structure 60 and the heavily doped drift region 64 . The plurality of first trench connection structures 90 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3 side, and face the drain region 10 with a part of the drift region 11 interposed therebetween.

The plurality of first trench connection structures 90 may be formed with approximately the same width and approximately the same depth as the first trench gate structure 70. Of course, the first portion and the second portion of the first trench connection structure 90 may have different widths. For example, the second portion of the first trench connection structure 90 may be formed narrower than the first portion of the first trench connection structure 90.

In this case, the first portion may have a width approximately equal to the width of the first trench isolation structure 60, and the second portion may have a width approximately equal to the width of the first trench gate structure 70. Further in this case, the first portion may have a depth approximately equal to the depth of the first trench isolation structure 60 and the second portion may have a depth approximately equal to the depth of the first trench gate structure 70.

The first trench connection structure 90 on the other side has the same structure as the first trench connection structure 90 on the one side, except that it is connected to the second end of the first trench gate structure 70. Hereinafter, the configuration of the first trench connection structure 90 on one side will be explained, and the description of the configuration of the first trench connection structure 90 on the other side will be omitted.

The first trench connection structure 90 includes a first connection trench 91, a first connection insulating film 92, and a first connection electrode 93. The first connection trench 91 is formed in the first main surface 3 and partitions the wall surface of the first trench connection structure 90. The first connection trench 91 is connected to the plurality of first gate trenches 71.

The first connection insulating film 92 covers the wall surface of the first connection trench 91. The first connection insulating film 92 is connected to the first upper insulating film 76 , the first lower insulating film 77 , and the first intermediate insulating film 75 at a communication portion between the first connection trench 91 and the first gate trench 71 . The first connection insulating film 92 is thicker than the first upper insulating film 76 . The thickness of the first connection insulating film 92 may be approximately equal to the thickness of the first lower insulating film 77. The first connection insulating film 92 may include a silicon oxide film. The first connection insulating film 92 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The first connection electrode 93 is buried in the first connection trench 91 with the first connection insulating film 92 in between, and faces the drift region 11 and the first body region 67 with the first connection insulating film 92 in between. The first connection electrode 93 is connected to the first lower electrode 74 at a communication portion between the first connection trench 91 and the first gate trench 71, and is electrically insulated from the first upper electrode 73 by the first intermediate insulating film 75. There is. The first connection electrode 93 consists of a drawn-out portion in which the first lower electrode 74 is drawn out from inside the first gate trench 71 into the first connection trench 91 . The first connection electrode 93 may include conductive polysilicon.

The semiconductor device 1 includes a first main surface insulating film 94 that selectively covers the first main surface 3 in the output region 6. The first main surface insulating film 94 is connected to the first insulating film 72 (first upper insulating film 76) and the first connection insulating film 92, and is connected to the first separation electrode 63, the first upper electrode 73, and the first connection electrode 93. is exposed.

The first main surface insulating film 94 is thinner than the first isolation insulating film 62. The first main surface insulating film 94 is thinner than the first lower insulating film 77 . The first main surface insulating film 94 is thinner than the first connecting insulating film 92 . The first main surface insulating film 94 may have approximately the same thickness as the first upper insulating film 76 . The first main surface insulating film 94 may include a silicon oxide film. The first main surface insulating film 94 preferably includes a silicon oxide film made of an oxide of the chip 2 .

The semiconductor device 1 includes a first field insulating film 95 that selectively covers the first main surface 3 inside and outside the output region 6. The first field insulating film 95 is thicker than the first main surface insulating film 94. The first field insulating film 95 is thicker than the first upper insulating film 76 . The first field insulating film 95 may have approximately the same thickness as the first isolation insulating film 62. The first field insulating film 95 may include a silicon oxide film. The first field insulating film 95 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The first field insulating film 95 covers the first main surface 3 along the inner wall of the first trench isolation structure 60 in the output region 6, and covers the first isolation insulating film 62, the first connection insulating film 92, and the first main surface 3. It is connected to the plane insulating film 94. The first field insulating film 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6 and is connected to the first isolation insulating film 62 .

The aforementioned interlayer insulating layer 12 covers the first trench isolation structure 60, the first trench gate structure 70, the first trench connection structure 90, the first main surface insulating film 94, and the first field insulating film 95 in the output region 6. are doing.

The semiconductor device 1 includes a plurality of first gate wirings 96 arranged within the interlayer insulating layer 12. The plurality of first gate wirings 96 are routed to the output region 6 and the control region 7, are electrically connected to the output transistor 20 in the output region 6, and are electrically connected to the control circuit 23 (gate control circuit 24) in the control region 7. connected. The plurality of first gate wirings 96 individually transmit a plurality of gate signals generated by the control circuit 23 (gate control circuit 24) to the output transistor 20.

The plurality of first gate wirings 96 include a first system gate wiring 96A and a second system gate wiring 96B. The first system gate wiring 96A individually transmits gate signals to the first system transistors 21A. The first system gate wiring 96A is electrically connected to a plurality of first trench gate structures 70 for the first system transistors 21A via a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the first system gate wiring 96A is electrically connected to the corresponding plurality of first upper electrodes 73 and plurality of first connection electrodes 93 via a plurality of via electrodes 97.

In other words, the first upper electrode 73 and the first lower electrode 74 for the first system transistor 21A are simultaneously controlled on and off by the same gate signal. Thereby, the voltage drop between the first upper electrode 73 and the first lower electrode 74 is suppressed, and undesired electric field concentration is suppressed. As a result, a decrease in withstand voltage (breakdown voltage) caused by the electric field concentration is suppressed.

The second system gate wiring 96B is electrically independent from the first system gate wiring 96A and individually transmits the gate signal to the second system transistor 21B. The second system gate wiring 96B is electrically connected to the plurality of first trench gate structures 70 for the second system transistors 21B via a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the second system gate wiring 96B is electrically connected to the corresponding plurality of first upper electrodes 73 and plurality of first connection electrodes 93 via a plurality of via electrodes 97.

In other words, the first upper electrode 73 and the first lower electrode 74 for the second system transistor 21B are simultaneously controlled on and off by the same gate signal. Thereby, the voltage drop between the first upper electrode 73 and the first lower electrode 74 is suppressed, and undesired electric field concentration is suppressed. As a result, a decrease in withstand voltage (breakdown voltage) caused by the electric field concentration is suppressed.

The semiconductor device 1 includes a first source wiring 98 arranged within the interlayer insulating layer 12. The first source wiring 98 is electrically connected to the source terminal 13, the first trench isolation structure 60, and the plurality of first channel cells 78. Specifically, the first source wiring 98 is electrically connected to the first trench isolation structure 60 and the plurality of first channel cells 78 via the plurality of via electrodes 97 arranged in the interlayer insulating layer 12. There is.

The via electrode 97 for each first channel cell 78 is arranged so as to straddle two adjacent first channel cells 78, and is formed in a band shape extending along each first channel cell 78 in plan view. Thereby, the source terminal 13 is electrically connected to the system sources of all the system transistors 21 (unit sources of the unit transistors 22).

Hereinafter, the configuration of the first protection region 8 (first protection transistor 40) side will be explained with reference to FIGS. 15 to 22. The configuration on the second protection area 9 (second protection transistor 50) side is the same as the configuration on the first protection area 8 side, except for electrical connection form, arrangement location, planar area, etc. (FIG. 1 ~See also Figure 6).

Therefore, the description of the configuration on the second protection area 9 side will be omitted as the description of the configuration on the first protection area 8 side will be applied. Regarding the configuration of the second protection region 9 side, in the following description, "first protection region 8" is replaced with "second protection region 9", and "first protection transistor 40" is replaced with "second protection transistor 50". obtained by.

In the accompanying drawings, in order to clarify that the configuration related to the first protection region 8 (first protection transistor 40) is also applied to the configuration related to the second protection region 9 (second protection transistor 50), the second protection region 8 (first protection transistor 40) is The code “9 (50)” related to region 9 (second protection transistor 50) is written together with the code “8 (40)” related to first protection region 8 (first protection transistor 40).

FIG. 15 is a plan view showing the first protection area 8 shown in FIG. 1. FIG. 16 is an enlarged plan view showing a main part of the first protection area 8 shown in FIG. 15. As shown in FIG. FIG. 17 is an enlarged plan view showing further essential parts of the first protection area 8 shown in FIG. 15. As shown in FIG. FIG. 18 is a sectional view taken along the line XVIII-XVIII shown in FIG. 16. FIG. 19 is a sectional view taken along the line XIX-XIX shown in FIG. 16. FIG. 20 is a sectional view taken along line XX-XX shown in FIG. 16. FIG. 21 is a sectional view taken along the line XXI-XXI shown in FIG. 16. FIG. 22 is a cross-sectional view for comparing the configuration on the output area 6 side and the configuration on the first protection area 8 side.

Referring to FIGS. 15 to 22, semiconductor device 1 includes a second trench isolation structure 100 formed on first main surface 3 to partition first protection region 8. The second trench isolation structure 100 may be referred to as a "second region isolation structure." The second trench isolation structure 100 electrically isolates the first protection region 8 from the output region 6 , the control region 7 and the second protection region 9 within the chip 2 . A source potential is applied to the second trench isolation structure 100. The second trench isolation structure 100 is formed in an annular shape surrounding the first protection region 8 in plan view.

In this form, the second trench isolation structure 100 is formed in a polygonal ring shape (quadrangular ring shape in this form) having four sides parallel to the periphery of the first main surface 3 in plan view. The second trench isolation structure 100 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 interposed therebetween.

The second trench isolation structure 100 has a third width W3. The third width W3 is a width in a direction perpendicular to the extending direction of the second trench isolation structure 100. The third width W3 is preferably larger than the first interval I1 between the plurality of first trench gate structures 70. The third width W3 is preferably larger than the second width W2 of the first trench gate structure 70. It is particularly preferred that the third width W3 is approximately equal to the first width W1 of the first trench isolation structure 60. Of course, the third width W3 may be larger than the first width W1 or may be smaller than the first width W1. Further, the third width W3 may be approximately equal to the second width W2.

The third width W3 may be 0.4 μm or more and 2.5 μm or less. The third width W3 is 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1 It may have a value belonging to any one range of .75 μm or more and 2 μm or less. The third width W3 is preferably 1.25 μm or more and 1.75 μm or less.

The second trench isolation structure 100 has a third depth D3. The third depth D3 is preferably greater than the second depth D2 of the first trench gate structure 70. It is particularly preferred that the third depth D3 is substantially equal to the first depth D1 of the first trench isolation structure 60. Of course, the third depth D3 may be larger than the first depth D1 or may be smaller than the first depth D1. Further, the third depth D3 may be approximately equal to the second depth D2.

The third depth D3 may be 1 μm or more and 6 μm or less. The third depth D3 may have a value belonging to any one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, and 5 μm to 6 μm. The third depth D3 is preferably 3 μm or more and 5 μm or less.

The second trench isolation structure 100 includes a second isolation trench 101, a second isolation insulating film 102, and a second isolation electrode 103. In other words, the second trench isolation structure 100 has a single electrode structure including a single electrode (second isolation electrode 103) buried in the second isolation trench 101 with an insulator (second isolation insulating film 102) in between. are doing.

The second isolation trench 101 is formed on the first main surface 3 and partitions the wall surface of the second trench isolation structure 100. The second isolation insulating film 102 covers the wall surface of the second isolation trench 101. The second isolation insulating film 102 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The second isolation insulating film 102 is thicker than the first upper insulating film 76. The thickness of the second isolation insulating film 102 is preferably approximately equal to the thickness of the first isolation insulating film 62. The second isolation electrode 103 is buried in the second isolation trench 101 with the second isolation insulating film 102 in between. The second separated electrode 103 may include conductive polysilicon.

The semiconductor device 1 includes a first protection transistor 40 formed on the first main surface 3 in the first protection region 8 . Although the following configuration will be explained as a component of the semiconductor device 1, it is also a component of the first protection transistor 40.

Unlike the configuration on the output region 6 side, the semiconductor device 1 does not have a high concentration drift region 64 in the surface layer portion of the drift region 11 of the first protection region 8. That is, unlike the configuration on the output region 6 side, the drift region 11 of the first protection region 8 does not have a concentration gradient in which the impurity concentration increases from the bottom side toward the first main surface 3 side.

In other words, the drift region 11 of the first protection region 8 does not have a concentration gradient in which the impurity concentration increases in the thickness range between the bottom of the drift region 11 and the first trench gate structure 70. Drift region 11 of first protection region 8 has a substantially constant n-type impurity concentration in the thickness direction.

The first protection region 8 is not a region that is always used, but is a region that is used when the first overvoltage Vs1 (first overvoltage Vs1) is generated (when applied). Therefore, unlike the output region 6, the first protection region 8 is required to withstand overvoltage. In other words, in the first protection region 8, there is a small demand for low on-resistance, and a large demand for high breakdown voltage.

In the first protection region 8, if the drift region 11 is highly concentrated by the high concentration drift region 64, undesirable electric field concentration due to overvoltage is caused, increasing the possibility that the breakdown voltage will decrease. Therefore, it is preferable that the first protection region 8 does not include the high concentration drift region 64. Of course, the present disclosure does not exclude a configuration in which the first protection region 8 includes the high concentration drift region 64.

The semiconductor device 1 includes a p-type (second conductivity type) second body region 107 formed in the surface layer of the drift region 11 in the first protection region 8 . Preferably, second body region 107 has approximately the same p-type impurity concentration as first body region 67. The second body region 107 extends in a layered manner along the first main surface 3 throughout the first protection region 8 and is connected to the wall surface of the second trench isolation structure 100 .

That is, in this form, the second body region 107 is not formed in a region outside the second trench isolation structure 100. The second body region 107 is formed shallower than the second trench isolation structure 100 and has a bottom portion located closer to the first main surface 3 than the bottom wall of the second trench isolation structure 100 . The bottom of the second body region 107 is preferably located closer to the first main surface 3 than the middle part of the depth range of the second trench isolation structure 100. Preferably, second body region 107 has approximately the same thickness as first body region 67.

The semiconductor device 1 includes a plurality of second trench gate structures 110 formed on the first main surface 3 in the first protection region 8 . The number of second trench gate structures 110 is less than the number of first trench gate structures 70 . Although specific illustration is omitted, the number of second trench gate structures 110 in the second protection region 9 may be different from the number of second trench gate structures 110 in the first protection region 8.

The number of second trench gate structures 110 in the second protection region 9 may be greater than the number of second trench gate structures 110 in the first protection region 8. The number of second trench gate structures 110 in the second protection region 9 may be less than the number of second trench gate structures 110 in the first protection region 8 . The number of second trench gate structures 110 in the second protection region 9 may be the same as the number of second trench gate structures 110 in the first protection region 8 .

A plurality of second trench gate structures 110 are formed inside the first protection region 8 at intervals from the second trench isolation structure 100. The plurality of second trench gate structures 110 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y.

In other words, the plurality of second trench gate structures 110 are arranged in a stripe shape extending in the second direction Y. The length of the plurality of second trench gate structures 110 is less than the length of the plurality of first trench gate structures 70. The plurality of second trench gate structures 110 have a first end on one side in the longitudinal direction (second direction Y) and a second end on the other side in the longitudinal direction (second direction Y). There is.

The plurality of second trench gate structures 110 penetrate the second body region 107 in cross-sectional view and are located within the drift region 11. The plurality of second trench gate structures 110 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3 side, and face the drain region 10 with a part of the drift region 11 interposed therebetween.

The plurality of second trench gate structures 110 have a fourth width W4 (see also FIG. 22). The fourth width W4 is a width in a direction perpendicular to the extending direction of the second trench gate structure 110 (that is, the first direction X). The fourth width W4 is preferably less than the first width W1 of the first trench isolation structure 60. The fourth width W4 is preferably less than the third width W3 of the second trench isolation structure 100.

The fourth width W4 is preferably larger than the first interval I1 between the plurality of first trench gate structures 70. Preferably, the fourth width W4 is approximately equal to the second width W2 of the first trench gate structure 70. Of course, the fourth width W4 may be larger than the second width W2 or may be smaller than the second width W2.

The fourth width W4 may be 0.4 μm or more and 2 μm or less. The fourth width W4 is 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1 It may have a value belonging to any one range of .75 μm or more and 2 μm or less. The fourth width W4 is preferably 0.8 μm or more and 1.2 μm or less.

The plurality of second trench gate structures 110 are arranged at a second interval I2 in the first direction X (see also FIG. 22). The second interval I2 is also the mesa width (second mesa width) of a mesa portion (second mesa portion) defined in a region between two mutually adjacent second trench gate structures 110.

The second interval I2 is preferably equal to or greater than the second width W2 of the first trench gate structure 70. It is particularly preferable that the second interval I2 is larger than the second width W2. The second interval I2 is preferably equal to or greater than the fourth width W4 of the second trench gate structure 110. It is particularly preferable that the second interval I2 is larger than the fourth width W4.

The second interval I2 is preferably equal to or less than the first width W1 of the first trench isolation structure 60 (less than the first width W1). It is preferable that the second interval I2 is less than the first width W1. The second interval I2 is preferably equal to or less than the third width W3 of the second trench isolation structure 100 (less than the third width W3). The second interval I2 is preferably less than the third width W3.

The second interval I2 is preferably greater than or equal to the first interval I1 of the plurality of first trench gate structures 70. It is particularly preferred that the second spacing I2 is larger than the first spacing I1. The second interval I2 is preferably at least 1.5 times and at most 4 times the first interval I1. It is particularly preferable that the second interval I2 is 2.5 times or less the first interval I1.

The second interval I2 may be 0.8 μm or more and 1.6 μm or less. The second interval I2 has a value belonging to any one of the following ranges: 0.8 μm to 1 μm, 1 μm to 1.2 μm, 1.2 μm to 1.4 μm, and 1.4 μm to 1.6 μm. You can leave it there. The second interval I2 is preferably 1 μm or more and 1.4 μm or less.

The second trench gate structure 110 has a fourth depth D4 (see also FIG. 22). The fourth depth D4 may be approximately equal to the first depth D1 of the first trench isolation structure 60. It is preferable that the fourth depth D4 is less than the first depth D1. The fourth depth D4 may be approximately equal to the third depth D3 of the second trench isolation structure 100. It is preferable that the fourth depth D4 is less than the third depth D3. It is particularly preferred that the fourth depth D4 is approximately equal to the second depth D2 of the first trench gate structure 70. Of course, the fourth depth D4 may be larger than the second depth D2, or may be smaller than the second depth D2.

The fourth depth D4 may be 1 μm or more and 6 μm or less. The fourth depth D4 may have a value belonging to any one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, and 5 μm to 6 μm. The fourth depth D4 is preferably 2.5 μm or more and 4.5 μm or less.

Although specific illustration is omitted, the fourth width W4 within the second protection area 9 may be different from the fourth width W4 within the first protection area 8. The fourth width W4 within the second protection area 9 may be larger than the fourth width W4 within the first protection area 8. The fourth width W4 within the second protection area 9 may be smaller than the fourth width W4 within the first protection area 8. Of course, the fourth width W4 within the second protection area 9 may be approximately equal to the fourth width W4 within the first protection area 8.

Furthermore, the second interval I2 within the second protection area 9 may be different from the second interval I2 within the first protection area 8. The second spacing I2 in the second protection area 9 may be larger than the second spacing I2 in the first protection area 8. The second spacing I2 in the second protection area 9 may be smaller than the second spacing I2 in the first protection area 8. Of course, the second spacing I2 in the second protection area 9 may be approximately equal to the second spacing I2 in the first protection area 8.

Furthermore, the fourth depth D4 within the second protection area 9 may be different from the fourth depth D4 within the first protection area 8. The fourth depth D4 within the second protection area 9 may be greater than the fourth depth D4 within the first protection area 8. The fourth depth D4 within the second protection area 9 may be smaller than the fourth depth D4 within the first protection area 8. Of course, the fourth depth D4 within the second protection area 9 may be approximately equal to the fourth depth D4 within the first protection area 8.

The internal configuration of one second trench gate structure 110 will be described below. The second trench gate structure 110 includes a second gate trench 111, a second insulating layer 112, a second upper electrode 113, a second lower electrode 114, and a second intermediate insulating layer 115. In other words, the second trench gate structure 110 includes a plurality of electrodes (a second upper electrode 113 and a second lower electrode 114).

The second gate trench 111 is formed on the first main surface 3 and partitions the wall surface of the second trench gate structure 110. The second insulating film 112 covers the wall surface of the second gate trench 111. The second insulating film 112 includes a second upper insulating film 116 and a second lower insulating film 117. The second upper insulating film 116 covers the bottom of the second body region 107 and the wall surface on the opening side of the second gate trench 111 . The second upper insulating film 116 partially covers the bottom wall surface of the second gate trench 111 with respect to the bottom of the second body region 107 .

The second upper insulating film 116 is thinner than the first isolation insulating film 62. The thickness of the second upper insulating film 116 is smaller than the thickness of the second isolation insulating film 102. The thickness of the second upper insulating film 116 is preferably approximately equal to the thickness of the first upper insulating film 76. The second upper insulating film 116 is formed as a gate insulating film. The second upper insulating film 116 may include a silicon oxide film. The second upper insulating film 116 preferably includes a silicon oxide film made of an oxide of the chip 2 .

The second lower insulating film 117 covers the bottom wall surface of the second gate trench 111 with respect to the bottom of the second body region 107 . The second lower insulating film 117 is thicker than the second upper insulating film 116. The thickness of the second lower insulating film 117 is preferably approximately equal to the thickness of the first lower insulating film 77.

The thickness of the second lower insulating film 117 may be approximately equal to the thickness of the first isolation insulating film 62 (second isolation insulating film 102). The second lower insulating film 117 may include a silicon oxide film. The second lower insulating film 117 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The second upper electrode 113 is buried on the opening side of the second gate trench 111 with the second insulating film 112 in between. Specifically, the second upper electrode 113 is buried in the opening side of the second gate trench 111 with the second upper insulating film 116 in between, and in the second body region 107 and the drift region with the second upper insulating film 116 in between. It is facing 11. The second upper electrode 113 may include conductive polysilicon.

The second lower electrode 114 is buried on the bottom wall side of the second gate trench 111 with the second insulating film 112 in between. Specifically, the second lower electrode 114 is buried in the bottom wall side of the second gate trench 111 with the second lower insulating film 117 in between, and is located opposite to the drift region 11 with the second lower insulating film 117 in between. There is.

The second lower electrode 114 has an upper end that protrudes from the second lower insulating film 117 toward the second upper electrode 113 so as to be combined with the bottom of the second upper electrode 113. The upper end of the second lower electrode 114 faces the second upper insulating film 116 across the lower end of the second upper electrode 113 in the lateral direction along the first main surface 3 . The second lower electrode 114 may include conductive polysilicon.

The second intermediate insulating film 115 is interposed between the second upper electrode 113 and the second lower electrode 114 and electrically insulates the second upper electrode 113 and the second lower electrode 114 within the second gate trench 111. There is. The second intermediate insulating film 115 is continuous with the second upper insulating film 116 and the second lower insulating film 117.

The second intermediate insulating film 115 is thinner than the second lower insulating film 117. The thickness of the second intermediate insulating film 115 is preferably approximately equal to the thickness of the first intermediate insulating film 75. The second intermediate insulating film 115 may include a silicon oxide film. The second intermediate insulating film 115 preferably includes a silicon oxide film made of an oxide of the second lower electrode 114.

The semiconductor device 1 includes a plurality of second channel cells 118 formed on both sides of each second trench gate structure 110 to be controlled by each second trench gate structure 110. That is, the two second channel cells 118 disposed on both sides of one second trench gate structure 110 are controlled by the one second trench gate structure 110.

The plurality of second channel cells 118 are formed in a region along the inner part of the second trench gate structure 110 at intervals from both ends of the second trench gate structure 110 in the longitudinal direction (second direction Y). . The plurality of second channel cells 118 expose the second body region 107 from a region of the first main surface 3 sandwiched between both ends of the plurality of second trench gate structures 110 . The plurality of second channel cells 118 face the drift region 11 with a part of the second body region 107 interposed therebetween in the thickness direction.

Each second channel cell 118 includes a plurality of n-type second source regions 119 and a plurality of p-type second contact regions 120. In FIG. 16, the second source region 119 is hatched for clarity. The second contact region 120 may be referred to as a "second back gate region."

Each second source region 119 has a higher n-type impurity concentration than drift region 11 . Each second source region 119 may have a higher n-type impurity concentration than high concentration drift region 64. The n-type impurity concentration of each second source region 119 is preferably approximately equal to the n-type impurity concentration of each first source region 79. The n-type impurity concentration of each second source region 119 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The plurality of second source regions 119 are arranged at intervals along the plurality of second trench gate structures 110. The plurality of second source regions 119 are formed at intervals from the bottom of the second body region 107 toward the first main surface 3 side, and are located on the second upper surface with the second insulating film 112 (second upper insulating film 116) in between. It faces the electrode 113. Each second source region 119 has a larger planar area than the planar area of each first source region 79.

Each second contact region 120 has a higher p-type impurity concentration than second body region 107. The p-type impurity concentration of each second contact region 120 is preferably approximately equal to the n-type impurity concentration of each first contact region 80. The p-type impurity concentration of each second contact region 120 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The plurality of second contact regions 120 are arranged alternately with the plurality of second source regions 119 along each second trench gate structure 110. The plurality of second contact regions 120 are formed at intervals from the bottom of the second body region 107 toward the first main surface 3 side, and are connected to the second upper insulating film 112 (second upper insulating film 116) with the second insulating film 112 (second upper insulating film 116) in between. It faces the electrode 113. Each second contact region 120 has a planar area larger than the planar area of each first contact region 80.

Regarding the two second channel cells 118 formed on both sides of one second trench gate structure 110, the plurality of second source regions 119 in one of the second channel cells 118 are located on both sides of the second trench gate structure 110. and faces the plurality of second source regions 119 in the other second channel cell 118. Further, the plurality of second contact regions 120 in one second channel cell 118 are opposed to the plurality of second contact regions 120 in the other second channel cell 118 with the second trench gate structure 110 in between. .

Of course, the plurality of second source regions 119 in one second channel cell 118 are opposed to the plurality of second contact regions 120 in the other second channel cell 118 with the second trench gate structure 110 in between. Good too. Further, the plurality of second contact regions 120 in one second channel cell 118 are opposed to the plurality of second source regions 119 in the other second channel cell 118 with the second trench gate structure 110 in between. Good too.

Regarding the two second channel cells 118 interposed between the two second trench gate structures 110, the plurality of second source regions 119 in one of the second channel cells 118 are arranged in the first direction It is connected to a plurality of second contact regions 120 within the channel cell 118 . Further, the plurality of second contact regions 120 in one second channel cell 118 are connected in the first direction X to the plurality of second source regions 119 in the other second channel cell 118.

Of course, the plurality of second source regions 119 in one second channel cell 118 may be connected to the plurality of second source regions 119 in the other second channel cell 118 in the first direction X. Further, the plurality of second contact regions 120 in one second channel cell 118 may be connected in the first direction X to the plurality of second contact regions 120 in the other second channel cell 118.

Of the two second channel cells 118 formed on both sides of the outermost second trench gate structure 110, the second channel cell 118 located on the inner side is located along a portion of the second body region 107 in the thickness direction. It faces the drift region 11 with a portion in between. On the other hand, the second channel cell 118 located on the outer side does not include the second source region 119 but only includes the second contact region 120. This suppresses the formation of a current path in the region between the second trench isolation structure 100 and the outermost second trench gate structure 110.

The semiconductor device 1 includes a pair of second trench connection structures 130 that connect both ends of a plurality (all in this form) of second trench gate structures 110 in the first protection region 8 . The second trench connection structure 130 on one side connects the first ends of a plurality (all in this form) of the second trench gate structures 110 in an arch shape in a plan view. The second trench connection structure 130 on the other side connects the second ends of a plurality (all in this form) of the second trench gate structures 110 in an arch shape in a plan view.

Specifically, the second trench connection structure 130 on one side has a first portion extending in the first direction X and a plurality of second portions extending in the second direction Y. The first portion faces the first ends of the plurality of second trench gate structures 110 in plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

The second trench connection structure 130 on the other side has a first portion extending in the first direction X and a plurality of second portions extending in the second direction Y. The first portion faces the second end portions of the plurality of second trench gate structures 110 in plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of second trench connection structures 130 constitute a ladder-like trench structure together with the plurality of second trench gate structures 110 within the first protection region 8 .

The plurality of second trench connection structures 130 are connected to the plurality of second trench gate structures 110 at intervals from the second trench isolation structure 100. The plurality of second trench connection structures 130 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3 side, and face the drain region 10 with a part of the drift region 11 interposed therebetween.

The plurality of second trench connection structures 130 may be formed with approximately the same width and approximately the same depth as the second trench gate structure 110. Of course, the first portion and the second portion of the second trench connection structure 130 may have different widths. For example, the second portion of the second trench connection structure 130 may be formed narrower than the first portion of the second trench connection structure 130.

In this case, the first portion may have a width approximately equal to the width of the second trench isolation structure 100, and the second portion may have a width approximately equal to the width of the second trench gate structure 110. Further in this case, the first portion may have a depth approximately equal to the depth of the second trench isolation structure 100 and the second portion may have a depth approximately equal to the depth of the second trench gate structure 110.

The first portion of the second trench connection structure 130 may have a width and depth approximately equal to the width and depth of the first portion of the first trench connection structure 90. The second portion of the second trench connection structure 130 may have a width and depth approximately equal to the width and depth of the second portion of the first trench connection structure 90.

The second trench connection structure 130 on the other side has the same structure as the second trench connection structure 130 on the one side, except that it is connected to the second end of the second trench gate structure 110. Hereinafter, the configuration of the second trench connection structure 130 on one side will be explained, and the description of the configuration of the second trench connection structure 130 on the other side will be omitted.

The second trench connection structure 130 includes a second connection trench 131, a second connection insulating film 132, and a second connection electrode 133. The second connection trench 131 is formed in the first main surface 3 and partitions the wall surface of the second trench connection structure 130. The second connection trench 131 is connected to the plurality of second gate trenches 111.

The second connection insulating film 132 covers the wall surface of the second connection trench 131. The second connection insulating film 132 is connected to the second upper insulating film 116 , the second lower insulating film 117 , and the second intermediate insulating film 115 at a communication portion between the second connection trench 131 and the second gate trench 111 .

The second connection insulating film 132 is thicker than the second upper insulating film 116. The thickness of the second connection insulating film 132 may be approximately equal to the thickness of the second lower insulating film 117. The thickness of the second connection insulating film 132 may be approximately equal to the thickness of the first connection insulating film 92. The second connection insulating film 132 may include a silicon oxide film. The second connection insulating film 132 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The second connection electrode 133 is buried in the second connection trench 131 with the second connection insulating film 132 in between, and faces the drift region 11 and the second body region 107 with the second connection insulating film 132 in between.

The second connection electrode 133 is connected to the second lower electrode 114 at a communication portion between the second connection trench 131 and the second gate trench 111, and is electrically insulated from the second upper electrode 113 by the second intermediate insulating film 115. There is. The second connection electrode 133 consists of a drawn-out portion in which the second lower electrode 114 is drawn out from inside the second gate trench 111 into the second connection trench 131 . The second connection electrode 133 may include conductive polysilicon.

The semiconductor device 1 includes a second main surface insulating film 134 that selectively covers the first main surface 3 in the first protection region 8 . The second main surface insulating film 134 is connected to the second insulating film 112 (second upper insulating film 116) and the second connection insulating film 132, and is connected to the second separation electrode 103, the second upper electrode 113, and the second connection electrode 133. is exposed.

The second main surface insulating film 134 is thinner than the second isolation insulating film 102. The second main surface insulating film 134 is thinner than the second lower insulating film 117. The second main surface insulating film 134 is thinner than the second connection insulating film 132. The second main surface insulating film 134 may have approximately the same thickness as the second upper insulating film 116. It is preferable that the second main surface insulating film 134 has approximately the same thickness as the first main surface insulating film 94. The second main surface insulating film 134 may include a silicon oxide film. The second main surface insulating film 134 preferably includes a silicon oxide film made of an oxide of the chip 2 .

The semiconductor device 1 includes a second field insulating film 135 that selectively covers the first main surface 3 inside and outside the first protection region 8 . The second field insulating film 135 is thicker than the second main surface insulating film 134. The second field insulating film 135 is thicker than the second upper insulating film 116 . The second field insulating film 135 may have approximately the same thickness as the second isolation insulating film 102.

It is preferable that the second field insulating film 135 has approximately the same thickness as the first field insulating film 95. The second field insulating film 135 may include a silicon oxide film. The second field insulating film 135 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

The second field insulating film 135 covers the first main surface 3 along the inner wall of the second trench isolation structure 100 in the first protection region 8 , and covers the second isolation insulating film 102 , the second connection insulating film 132 , and the second field insulating film 135 . 2 is connected to the main surface insulating film 134. The second field insulating film 135 covers the first main surface 3 along the outer wall of the second trench isolation structure 100 outside the first protection region 8 and is connected to the second isolation insulating film 102 .

The aforementioned interlayer insulating layer 12 includes a second trench isolation structure 100, a second trench gate structure 110, a second trench connection structure 130, a second main surface insulating film 134, and a second field insulating film 135 in the first protection region 8. is covered.

The semiconductor device 1 includes a second gate wiring 136 arranged within the interlayer insulating layer 12. The second gate wiring 136 is electrically connected to the connection target and all the second trench gate structures 110.

In the case of the first protection region 8, the second gate wiring 136 is electrically connected to the clamp circuit 41 as a connection target (see FIG. 5). That is, the plurality of second trench gate structures 110 are electrically connected to the drain terminal 15 via the second gate wiring 136 and the clamp circuit 41. In the first protection transistor 40, a bias voltage caused by the first overvoltage Vs1 is applied to the second trench gate structure 110 via the second gate wiring 136, and a gate signal from the control circuit 23 (gate control circuit 24) etc. The second trench gate structure 110 is configured not to be inputted thereto.

In the case of the second protection region 9, the second gate wiring 136 is electrically connected to the input terminal 14b as a connection target (see FIG. 6). That is, the plurality of second trench gate structures 110 are electrically connected to the input terminal 14b via the second gate wiring 136. In the second protection transistor 50, a bias voltage caused by the second overvoltage Vs2 is applied to the second trench gate structure 110 via the second gate wiring 136, and a gate signal from the control circuit 23 (gate control circuit 24) or the like is applied. The second trench gate structure 110 is configured not to be inputted thereto.

The second gate wiring 136 is electrically connected to the plurality of second trench gate structures 110 via the plurality of via electrodes 97 arranged within the interlayer insulating layer 12. Specifically, the second gate wiring 136 is electrically connected to the plurality of second upper electrodes 113 and the plurality of second connection electrodes 133 via the plurality of via electrodes 97.

In other words, the second upper electrode 113 and the second lower electrode 114 are simultaneously controlled on and off by the same bias voltage. Thereby, the voltage drop between the second upper electrode 113 and the second lower electrode 114 is suppressed, and undesired electric field concentration is suppressed. As a result, a decrease in withstand voltage (breakdown voltage) caused by the electric field concentration is suppressed.

The semiconductor device 1 includes a second source wiring 138 arranged within the interlayer insulating layer 12. The second source wiring 138 is electrically connected to the second trench isolation structure 100 and the plurality of second channel cells 118 .

In the case of the first protection region 8, the second source wiring 138 is electrically connected to the power supply reverse connection protection circuit 31 (ground terminal 14a) as a connection target (see FIG. 5). In the case of the second protection region 9, the second source wiring 138 is electrically connected to the input terminal 14b as a connection target (see FIG. 6). In the case of the second protection region 9, the second source wiring 138 and the second gate wiring 136 may be integrally formed as the same wiring.

The second source wiring 138 is electrically connected to the second trench isolation structure 100 and the plurality of second channel cells 118 via the plurality of via electrodes 97. The via electrode 97 for each second channel cell 118 is arranged so as to straddle two adjacent second channel cells 118, and is formed in a band shape extending along each second channel cell 118 in plan view.

FIG. 23 is a first graph showing the results of a known TLP (Transmission Line Pulse) test. In FIG. 23, the vertical axis is the TLP breakdown current (breakdown current), and the horizontal axis is the second interval I2 of the second trench gate structure 110. In the TLP test, an overvoltage (surge voltage) sufficient to cause breakdown was applied in a pulsed manner to the first protection transistor 40 (second protection transistor 50), and the current at breakdown was obtained. Here, the TLP breakdown current per unit area is shown. The unit area is a region including two adjacent second trench gate structures 110.

In FIG. 23, the first to fourth plot points P1 to P4 are shown as black circles, and the fifth to sixth plot points P5 to P6 are shown as white circles. The first to fourth plot points P1 to P4 show the characteristics when the fourth width W4 of the second trench gate structure 110 is fixed to 1 μm and the second interval I2 of the second trench gate structure 110 is changed. There is. The second interval I2 is 0.6 μm, 0.7 μm, 0.8 μm, and 1.2 μm in the order of the first to fourth plot points P1 to P4.

The fifth and sixth plot points P5 and P6 represent the characteristics when the fourth width W4 of the second trench gate structure 110 is fixed at 1.2 μm and the second interval I2 of the second trench gate structure 110 is varied. It shows. The second interval I2 is 0.6 μm and 1.2 μm in the order of the fifth and sixth plot points P5 and P6.

Referring to the first to sixth plot points P1 to P6, it was found that the TLP breakdown current increases by increasing the second interval I2, and decreases by decreasing the second interval I2. The TLP breakdown current associated with the fifth plot point P5 is approximately equal to the TLP breakdown current associated with the first plot point P1, and the TLP breakdown current associated with the sixth plot point P6 is the TLP breakdown current associated with the fourth plot point P4. was almost equal.

When the second interval I2 is reduced, the carrier density between the plurality of second trench gate structures 110 can be increased, so that the on-resistance can be reduced. However, when an overvoltage is applied, as a result of overcurrent flowing between the plurality of second trench gate structures 110, the temperature tends to rise in the region between the plurality of second trench gate structures 110. As a result, the breakdown current decreases.

Therefore, on the output transistor 20 side, the first interval I1 is preferably set to a relatively small value in order to reduce on-resistance (power consumption). On the other hand, on the first protection transistor 40 (second protection transistor 50) side, the second interval I2 is preferably set to a larger value than the first interval I1 in order to suppress a decrease in breakdown strength.

In such a configuration, the on-resistance of the first protection transistor 40 (second protection transistor 50) is higher than the on-resistance of the output transistor 20 per unit area. On the other hand, the breakdown current of the first protection transistor 40 (second protection transistor 50) is larger than the breakdown current of the output transistor 20 per unit area. This is because the temperature rise in the region between the plurality of second trench gate structures 110 is suppressed and the breakdown resistance is improved.

From the results shown in FIG. 23, it was found that the first interval I1 of the first trench gate structure 70 is preferably set to 0.8 μm or less (0.4 μm or more and 0.8 μm or less). Further, it has been found that the second interval I2 of the second trench gate structure 110 is preferably set to 0.8 μm or more (0.8 μm or more and 1.6 μm or less).

FIG. 24 is a second graph showing the results of the TLP test. FIG. 24 is a graph in which the horizontal axis in FIG. 23 is changed to the fourth width W4 of the second trench gate structure 110. Here, the TLP breakdown current (breakdown current) was investigated when the second interval I2 of the second trench gate structure 110 was fixed and the fourth width W4 of the second trench gate structure 110 was changed.

That is, here, the first plot point P1 (fourth width W4 = 1 μm) and the fifth plot point P5 (fourth width W4 = 1.2 μm), both of which have a second interval I2 of 0.6 μm, are compared, The fourth plot point P4 (fourth width W4=1 μm) and the sixth plot point P6 (fourth width W4=1.2 μm), both of which have a second interval I2 of 1.2 μm, are compared.

Comparing the first plot point P1 and the fifth plot point P5, the TLP breakdown current associated with the fifth plot point P5 was approximately equal to the TLP breakdown current associated with the first plot point P1. Further, when comparing the fourth plot point P4 and the sixth plot point P6, the current at TLP breakdown related to the sixth plot point P6 was almost equal to the current at TLP breakdown related to the fourth plot point P4.

From this result, it was found that the current at the time of TLP breakdown depends on the second interval I2 of the second trench gate structure 110, and almost does not depend on the fourth width W4 of the second trench gate structure 110. In other words, even if the fourth width W4 is increased or decreased, the current at the time of TLP breakdown does not increase or decrease significantly. From this, it has been found that the fourth width W4 of the second trench gate structure 110 can be set to a value approximately equal to the second width W2 of the first trench gate structure 70.

According to this configuration, the first trench gate structure 70 and the second trench gate structure 110 can be manufactured at the same time. Furthermore, since the second width W2 and the fourth width W4 are approximately equal, the amount of etching on the first trench gate structure 70 side with respect to the chip 2 (first main surface 3) and the amount of etching of the second trench with respect to the chip 2 (first main surface 3) The amount of etching on the gate structure 110 side becomes approximately equal. Accordingly, the second trench gate structure 110 having a fourth depth D4 substantially equal to the second depth D2 of the first trench gate structure 70 can be formed.

In other words, even if the second trench gate structure 110 having the same configuration as the first trench gate structure 70 is formed in the first protection region 8, a relatively high breakdown strength can be achieved. In other words, the breakdown resistance on the first protection region 8 side can be adjusted based on the configuration on the output region 6 side. Furthermore, since the same process conditions as those for the output area 6 can be applied to the first protection area 8 (second protection area 9), the manufacturing process can be easily managed.

FIG. 25 is a graph showing the test results of gate threshold voltage. The vertical axis of FIG. 25 shows the drain-source current Ids [A], and the horizontal axis shows the gate voltage Vgs [V]. "E" on the vertical axis represents an exponentiation of 10. FIG. 25 shows a first characteristic S1 and a second characteristic S2. The first characteristic S1 indicates the characteristic of the output transistor 20. The second characteristic S2 indicates the characteristic of the first protection transistor 40.

Referring to the first characteristic S1 and the second characteristic S2, the first gate threshold voltage Vth1 of the output transistor 20 was 1.46V, and the second gate threshold voltage Vth2 of the first protection transistor 40 was 1.87V. . The second gate threshold voltage Vth2 is higher than the first gate threshold voltage Vth1 by 0.4 V or more. From this, it can be said that the output transistor 20 has better switching response than the first protection transistor 40.

Here, the first gate threshold voltage Vth1 and the second gate threshold voltage Vth2 are defined by the voltage value at the point where the drain-source current Ids is 1×10 −6 A. The first gate threshold voltage Vth1 may be defined by the voltage value at the point where the slope of the tangent in the rising curve of the first characteristic S1 is maximum. Similarly, the second gate threshold voltage Vth2 may be defined by the voltage value at the point where the slope of the tangent in the rising curve of the second characteristic S2 is maximum.

The difference value (Vth1-Vth2) between the second gate threshold voltage Vth2 and the first gate threshold voltage Vth1 is preferably 0.1V or more and 1V or less. It is particularly preferable that the difference value (Vth1-Vth2) is 0.3V or more and 0.7V or less.

From the above results, it was found that the first protection transistor 40 had a second gate threshold voltage Vth2 higher than the first gate threshold voltage Vth1 of the output transistor 20. This is because the first protection transistor 40 has a larger on-resistance than the on-resistance of the output transistor 20.

As described above, the semiconductor device 1 includes the chip 2, the output region 6, the first protection region 8, the output transistor 20, and the first overvoltage protection circuit 39 (protection circuit). The chip 2 has a first main surface 3 . The output area 6 is provided on the first main surface 3. The first protected area 8 is provided on the first main surface 3. Output transistor 20 is formed in output region 6 . The output transistor 20 includes a plurality of first trench gate structures 70 formed on the first main surface 3 at a first interval I1.

The first overvoltage protection circuit 39 includes a first protection transistor 40 formed in the first protection region 8 . The first protection transistor 40 includes a plurality of second trench gate structures 110 formed on the first main surface 3 with a second interval I2 larger than the first interval I1. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 (see FIG. 5). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout.

From another perspective, it includes the chip 2, the output region 6, the second protection region 9, the output transistor 20, and the second overvoltage protection circuit 49 (protection circuit). The chip 2 has a first main surface 3 . The output area 6 is provided on the first main surface 3. The second protection area 9 is provided on the first main surface 3. Output transistor 20 is formed in output region 6 . The output transistor 20 includes a plurality of first trench gate structures 70 formed on the first main surface 3 at a first interval I1.

The second overvoltage protection circuit 49 includes a second protection transistor 50 formed in the second protection region 9. The second protection transistor 50 includes a plurality of second trench gate structures 110 formed on the first main surface 3 with a second interval I2 larger than the first interval I1. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 (see FIG. 6). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout.

From another perspective, the semiconductor device 1 includes the chip 2, the output region 6, the first protection region 8, the n-type drift region 11, the n-type high concentration drift region 64, the output transistor 20, and the first overvoltage protection circuit 39 (protection circuit). The chip 2 has a first main surface 3 . The output area 6 is provided on the first main surface 3. The first protected area 8 is provided on the first main surface 3.

The drift region 11 is formed in the surface layer portion of the first main surface 3 in both the output region 6 and the first protection region 8. High concentration drift region 64 is formed in the surface layer of drift region 11 in output region 6 and has a higher impurity concentration than drift region 11 . Output transistor 20 is formed in output region 6 . The output transistor 20 has a first trench gate structure 70 formed on the first main surface 3 so as to be located within the heavily doped drift region 64 .

The first overvoltage protection circuit 39 includes a first protection transistor 40 formed in the first protection region 8 . The first protection transistor 40 includes a second trench gate structure 110 formed on the first main surface 3 so as to be located within the drift region 11 . The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 (see FIG. 5). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout. Preferably, the high concentration drift region 64 is not formed in the first protection region 8 .

From a different perspective, the semiconductor device 1 includes the chip 2, the output region 6, the second protection region 9, the n-type drift region 11, the n-type high concentration drift region 64, the output transistor 20, and the second overvoltage protection circuit 49 (protection circuit). The chip 2 has a first main surface 3 . The output area 6 is provided on the first main surface 3. The first protected area 8 is provided on the first main surface 3.

The drift region 11 is formed in the surface layer portion of the first main surface 3 in both the output region 6 and the second protection region 9. High concentration drift region 64 is formed in the surface layer of drift region 11 in output region 6 and has a higher impurity concentration than drift region 11 . Output transistor 20 is formed in output region 6 . The output transistor 20 has a first trench gate structure 70 formed on the first main surface 3 so as to be located within the heavily doped drift region 64 .

The second overvoltage protection circuit 49 includes a second protection transistor 50 formed in the second protection region 9. The second protection transistor 50 includes a second trench gate structure 110 formed on the first main surface 3 so as to be located within the drift region 11 . The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 (see FIG. 6). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout. Preferably, the high concentration drift region 64 is not formed in the second protection region 9.

From another perspective, the semiconductor device 1 includes a chip 2, a ground terminal 14a (first terminal), a drain terminal 15 (second terminal), and a first overvoltage protection circuit 39 (protection circuit) (see FIG. 5). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The ground terminal 14a is arranged on the first main surface 3. Drain terminal 15 is arranged on second main surface 4 .

The first overvoltage protection circuit 39 includes a first protection transistor 40 formed on the first main surface 3 so as to be electrically interposed between the ground terminal 14a and the drain terminal 15. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 generated between the ground terminal 14a and the drain terminal 15 (see FIG. 5).

In such a configuration, the first protection transistor 40 has a second upper electrode 113 and a second lower electrode buried vertically in the second gate trench 111 formed in the first main surface 3 with an insulator in between. 114 (see FIG. 18). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout.

From another perspective, the semiconductor device 1 includes a chip 2, an input terminal 14b (first terminal), a drain terminal 15 (second terminal), and a second overvoltage protection circuit 49 (protection circuit) (see FIG. 6). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The input terminal 14b is arranged on the first main surface 3. Drain terminal 15 is arranged on second main surface 4 .

The second overvoltage protection circuit 49 includes a second protection transistor 50 formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 generated between the input terminal 14b and the drain terminal 15 (see FIG. 6).

In such a configuration, the second protection transistor 50 has a second upper electrode 113 and a second lower electrode buried vertically in the second gate trench 111 formed in the first main surface 3 with an insulator in between. 114 (see FIG. 18). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout.

From a different perspective, the semiconductor device 1 includes a chip 2, a ground terminal 14a (first terminal), an input terminal 14b (second terminal), a drain terminal 15 (third terminal), a first overvoltage protection circuit 39 (first protection circuit ) and a second overvoltage protection circuit 49 (second protection circuit) (see FIGS. 5 and 6). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The ground terminal 14a is arranged on the first main surface 3. The input terminal 14b is arranged on the first main surface 3. Drain terminal 15 is arranged on second main surface 4 .

The first overvoltage protection circuit 39 includes a first protection transistor 40 formed on the first main surface 3 so as to be electrically interposed between the ground terminal 14a and the drain terminal 15. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 generated between the ground terminal 14a and the drain terminal 15 (see FIG. 5).

In such a configuration, the first protection transistor 40 has a second upper electrode 113 and a second lower electrode buried vertically in the second gate trench 111 formed in the first main surface 3 with an insulator in between. 114 (see FIG. 18).

The second overvoltage protection circuit 49 includes a second protection transistor 50 formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 generated between the input terminal 14b and the drain terminal 15 (see FIG. 6).

In such a configuration, the second protection transistor 50 has a second upper electrode 113 and a second lower electrode buried vertically in the second gate trench 111 formed in the first main surface 3 with an insulator in between. 114 (see FIG. 18). According to this configuration, it is possible to provide the semiconductor device 1 that can realize overvoltage protection with a novel layout.

Preferably, the semiconductor device 1 includes a first protection region 8 and a second protection region 9. The first protected area 8 is provided on the first main surface 3. The second protection area 9 is provided in a different area from the first protection area 8 on the first main surface 3 . The first protection transistor 40 is formed in the first protection region 8 . The second protection transistor 50 is formed in the second protection region 9.

Preferably, the semiconductor device 1 includes an output region 6 and an output transistor 20. The output area 6 is provided on the first main surface 3. Output transistor 20 is formed in output region 6 . The output transistor 20 has a plurality of first gate trenches 71 formed in the first main surface 3, each having a first upper electrode 73 and a first lower electrode 74 buried vertically with an insulator in between. A trench gate structure 70 is included (see FIG. 10).

The output transistor is preferably a variable on-resistance type gate split transistor. That is, the output transistor 20 includes a plurality of system transistors 21 each formed on the first main surface 3 so as to be individually controllable, and generates a single output current Io (output signal) by selectively controlling the plurality of system transistors 21. It is preferable that the system is configured to do so. According to such a configuration, it is possible to provide the output transistor 20 whose on-resistance (channel utilization rate) changes by individually controlling the plurality of system transistors 21.

Hereinafter, modifications (first modification and second modification) applied to either or both of the first protection area 8 and the second protection area 9 will be shown. Although an example in which the modified example is applied to the first protected area 8 is shown below, the modified example is also applicable to the second protected area 9. The variant may be applied to both the first protection area 8 and the second protection area 9 at the same time. While the modification is applied to the first protection area 8 , it may not be applied to the second protection area 9 . While the modification is applied to the second protection area 9, it may not be applied to the first protection area 8.

FIG. 26 is a plan view showing a first modification of the first protection area 8. In the embodiment described above, an example was shown in which a pair of second trench connection structures 130 connecting both ends of all the second trench gate structures 110 in an arch shape were formed in the first protection region 8 . However, the plurality of second trench connection structures 130 may have a similar form to the plurality of first trench connection structures 90.

That is, the plurality of second trench connection structures 130 are provided on the first end side of the second trench gate structure 110, and at the same time, the plurality of second trench connection structures 130 are provided on the second end side of the second trench gate structure 110. may be provided.

Each second trench connection structure 130 on the first end side connects the first ends of a plurality of (two in this form) second trench gate structures 110 in an arch shape when viewed from above. Each second trench connection structure 130 on the first end side has a first portion extending in the first direction X, and a plurality of (two in this embodiment) second portions extending in the second direction Y. . The first portion faces the first ends of the plurality of second trench gate structures 110 in plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

Each of the second trench connection structures 130 on the second end side is connected to the second ends of a plurality of (two in this embodiment) second trench gate structures 110 to which each of the first trench connection structures 90 is connected in plan view. are connected in an arch shape. Each second trench connection structure 130 on the second end side has a first portion extending in the first direction X and a plurality of (two in this embodiment) second portions extending in the second direction Y. . The first portion faces the second end portions of the plurality of second trench gate structures 110 in plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends.

Thereby, the second trench connection structure 130 on the first end side and the second trench connection structure 130 on the second end side are connected to a plurality of corresponding second trench gate structures 110 and one annular or ladder-shaped trench structure. It consists of In other respects, the configuration of the second trench connection structure 130 is the same as in the previous embodiment.

FIG. 27 is a sectional view showing a second modification of the first protection area 8. In the embodiment described above, it has been explained that the configuration in which the first protection region 8 includes the high concentration drift region 64 is not excluded. Here, a configuration in which the first protection region 8 has a high concentration drift region 64 is shown. However, in such a configuration, while the second spacing I2 between the plurality of second trench gate structures 110 increases the breakdown voltage of the first protection region 8, the high concentration drift region 64 reduces the breakdown voltage of the first protection region 8. It should be noted that

Therefore, this configuration is preferably applied to reduce the on-resistance of the first protection region 8 when the withstand voltage of the first protection region 8 is sufficient. Hereinafter, in order to distinguish from the high concentration drift region 64 on the output region 6 side, the high concentration drift region 64 on the first protection region 8 side will be referred to as a second high concentration drift region 144.

The semiconductor device 1 includes an n-type second high concentration drift region 144 formed in the surface layer of the drift region 11 in the first protection region 8 . The second high concentration drift region 144 has a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the second high concentration drift region 144 may be lower than the n-type impurity concentration of the drain region 10.

Preferably, the second high concentration drift region 144 has approximately the same n-type impurity concentration as the high concentration drift region 64. The n-type impurity concentration of the second high concentration drift region 144 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ^{−3 or} less. The second high concentration drift region 144 may be regarded as a high concentration portion of the drift region 11.

The second high-concentration drift region 144 forms a concentration gradient in which the n-type impurity concentration increases from the bottom side of the drift region 11 toward the first main surface 3 side. That is, the drift region 11 of the first protection region 8 has a concentration gradient formed by the second high concentration drift region 144 such that the n-type impurity concentration increases from the bottom side toward the first main surface 3 side. ing. In other words, the drift region 11 of the first protection region 8 has a concentration gradient in which the impurity concentration increases in the thickness range between the bottom of the drift region 11 and the first trench gate structure 70 on the output region 6 side. .

The second high concentration drift region 144 is formed inside the first protection region 8 at a distance from the second trench isolation structure 100. Therefore, the second heavily doped drift region 144 is surrounded by the drift region 11 in the first protection region 8 and is not in contact with the second trench isolation structure 100 . The second high concentration drift region 144 locally increases the n-type impurity concentration of the drift region 11 in the first protection region 8 .

The second high concentration drift region 144 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 in between. The second heavily doped drift region 144 has a bottom located closer to the bottom of the drift region 11 than the bottom wall of the second trench isolation structure 100 . The bottom (deepest part) of the second high concentration drift region 144 is formed at a depth approximately equal to the bottom of the high concentration drift region 64. The bottom of the second high-concentration drift region 144 meanders toward one side and the other side in the thickness direction in a cross-sectional view.

Specifically, the bottom of the second high concentration drift region 144 has a plurality of second bulges 145 and a plurality of second recesses 146 in cross-sectional view. The plurality of second bulges 145 are portions that bulge out in an arc shape toward the bottom side of the drift region 11 . The plurality of second bulges 145 are formed continuously in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. Each second bulge 145 is formed wider than the second trench isolation structure 100 in the first direction X. The width of each second bulge 145 in the first direction X is larger than the width of each bulge 65 on the output area 6 side in the first direction X.

The plurality of second depressions 146 are each formed in a band shape extending in the second direction Y in the region between the plurality of second bulges 145. The plurality of second depressions 146 are parts where the shallow parts of the plurality of second bulges 145 are connected to each other, and are located on the first main surface 3 side with respect to the deepest part of the plurality of second bulges 145. positioned. Of course, the second high concentration drift region 144 may have a flat bottom without meandering up and down in the thickness direction.

The second high concentration drift region 144 may have a high concentration throughout the entire drift region 11 within the first protection region 8. According to such a configuration, the on-resistance of the drift region 11 can be reduced by increasing the concentration of the drift region 11. However, in this case, it should be noted that the increase in carrier density in the drift region 11 tends to cause electric field concentration, resulting in a trade-off in that the breakdown voltage decreases. Therefore, in order to reduce the on-resistance while suppressing a decrease in breakdown voltage, it is preferable to introduce the second high concentration drift region 144 into a part of the first protection region 8.

The second body region 107 described above is formed shallower than the second high concentration drift region 144. Specifically, the second body region 107 is formed shallower than the second trench isolation structure 100 and has a bottom portion located closer to the first main surface 3 than the bottom wall of the second trench isolation structure 100. There is. The bottom of the second body region 107 is preferably located closer to the first main surface 3 than the middle part of the depth range of the second trench isolation structure 100.

The plurality of second trench gate structures 110 described above penetrate the second body region 107 in cross-sectional view and are located within the second high concentration drift region 144. The plurality of second trench gate structures 110 are formed at intervals from the bottom of the second high concentration drift region 144 toward the first main surface 3 side, and are connected to the drift region 11 with a part of the second high concentration drift region 144 in between. is facing.

The plurality of second trench gate structures 110 are formed to be shifted in the first direction X with respect to the plurality of second recesses 146, and respectively face the plurality of second bulges 145 in the thickness direction. It is preferable that the plurality of second trench gate structures 110 face the deepest parts of the plurality of second bulges 145. Such a configuration is obtained by introducing n-type impurities into the chip 2 from the wall surfaces of the plurality of second gate trenches 111 after the step of forming the plurality of second gate trenches 111.

The two second trench gate structures 110 located on both sides in the first direction X are preferably formed in a region outside the second high concentration drift region 144. That is, the outermost second trench gate structure 110 penetrates the second body region 107 at a position spaced apart from the second high concentration drift region 144 toward the second trench isolation structure 100 and is located within the drift region 11. It is preferable that you do so.

The outermost second trench gate structure 110 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3 side, and faces the drain region 10 with a part of the drift region 11 in between. The plurality of second channel cells 118 described above are preferably formed inward of the second high concentration drift region 144 rather than the periphery of the second high concentration drift region 144 in plan view.

The embodiments described above can be implemented in other forms. For example, in the embodiments described above, an example was shown in which the output region 6, the control region 7, the first protection region 8, and the second protection region 9 were formed in one chip 2. However, the semiconductor device 1 that does not have the control region 7 but has the output region 6, the first protection region 8, and the second protection region 9 may be employed. Further, a semiconductor device 1 that does not have the output region 6 but has the control region 7, the first protection region 8, and the second protection region 9 may be employed. Further, a semiconductor device 1 having the first protection region 8 and the second protection region 9 without having the output region 6 and the control region 7 may be employed.

Of course, these semiconductor devices 1 only need to include at least one of the first protection area 8 and the second protection area 9, and do not necessarily need to include both the first protection area 8 and the second protection area 9 at the same time. There isn't. These semiconductor devices 1 may constitute an IPD as shown in FIG. 3 by being incorporated into a semiconductor module, a semiconductor circuit, or the like together with other semiconductor devices 1.

In the embodiments described above, multiple systems of output transistors 20 were shown. However, one system of output transistors 20 may be employed. In this case, the second system transistor 21B is formed as the first system transistor 21A, and all the first trench gate structures 70 for the output transistors 20 are simultaneously controlled on and off.

Of course, in the embodiment described above, three or more systems of output transistors 20 may be employed. In this case, a plurality of block regions 81 for system transistors constituting three or more systems are provided, and at the same time, first gate wirings 96 of three or more systems corresponding to the block regions 81 are provided.

In the embodiment described above, a configuration including the current monitor circuit 25 was shown. The current monitor circuit 25 may be formed using at least one unit transistor 22 among the plurality of unit transistors 22.

In the embodiment described above, an example was shown in which the first upper electrode 73 and the first lower electrode 74 were at the same potential. However, a source potential may be applied to the first lower electrode 74. In this case, the first source wiring 98 is electrically connected to the first connection electrode 93 via the via electrode 97.

In the embodiment described above, an example was shown in which the second upper electrode 113 and the second lower electrode 114 were at the same potential. However, a source potential may be applied to the second lower electrode 114. In this case, the second source wiring 138 is electrically connected to the second connection electrode 133 via the via electrode 97.

In the embodiments described above, an example was shown in which the second trench isolation structure 100 was electrically connected to the second source wiring 138. However, the second trench isolation structure 100 may be electrically connected to the first source line 98 instead of the second source line 138.

In the embodiment described above, the plurality of first trench gate structures 70 are arranged in a stripe shape extending in the second direction Y, and the plurality of second trench gate structures 110 are arranged in a stripe shape extending in the second direction Y. Shown. However, the plurality of second trench gate structures 110 may extend in a direction different from the extending direction of the plurality of first trench gate structures 70.

For example, the plurality of first trench gate structures 70 may be arranged in a stripe shape extending in the second direction Y, and the plurality of second trench gate structures 110 may be arranged in a stripe shape extending in the first direction X. For example, the plurality of first trench gate structures 70 may be arranged in a stripe shape extending in the first direction X, and the plurality of second trench gate structures 110 may be arranged in a stripe shape extending in the second direction Y.

In the embodiments described above, an example was shown in which the source terminal 13 is an output terminal and the drain terminal 15 is a power supply terminal. However, a configuration may also be adopted in which the source terminal 13 is a ground terminal and the drain terminal 15 is an output terminal. In this case, the semiconductor device 1 becomes a low-side switching device electrically interposed between a load (inductive load L) and ground.

In the above-described embodiments, examples were shown in which the first conductivity type was n-type and the second conductivity type was p-type. However, the first conductivity type may be p type and the second conductivity type may be n type. A specific configuration in this case can be obtained by replacing the n-type region with a p-type region and simultaneously replacing the p-type region with an n-type region in the above description and the accompanying drawings.

In the embodiment described above, the first direction X and the second direction Y were defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any direction as long as they maintain a mutually intersecting (specifically orthogonal) relationship. For example, the first direction X may be the direction in which the third side surface 5C (fourth side surface 5D) extends, and the second direction Y may be the direction in which the first side surface 5A (second side surface 5B) extends. Further, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

Examples of features extracted from this specification and the attached drawings are shown below. Hereinafter, alphanumeric characters in parentheses represent corresponding components in the embodiments described above, but this is not intended to limit the scope of each item (Clause) to the embodiments. "Semiconductor devices" related to the following items may be referred to as "semiconductor protection devices," "semiconductor overvoltage protection devices," "semiconductor switching devices," "semiconductor control devices," "semiconductor modules," "electronic circuits," or "semiconductor control devices," as appropriate. It may be replaced with "semiconductor circuit", "intelligent power device", "intelligent power module", "intelligent power switch", etc.

[A1] A chip (2) having a main surface (3), an output region (6) provided on the main surface (3), and a protection region (8, 9) provided on the main surface (3). an output transistor (20) having a plurality of first trench gate structures (70) formed on the main surface (3) at a first interval (I1) in the output region (6); In (8, 9), a protection transistor ( 40, 50) and a protection circuit (39, 49) forming a discharge path for overvoltage (Vs1, Vs2).

[A2] The semiconductor device (1) according to A1, wherein the second interval (I2) is four times or less the first interval (I1).

[A3] The semiconductor according to A1 or A2, wherein the first interval (I1) is 0.4 μm or more and 0.8 μm or less, and the second interval (I2) is 0.8 μm or more and 1.6 μm or less. Device (1).

[A4] The plurality of first trench gate structures (70) have a width (W2) of 0.4 μm or more and 2 μm or less, and the plurality of second trench gate structures (110) have a width (W2) of 0.4 μm or more and 2 μm or less. The semiconductor device (1) according to any one of A1 to A3, having a width (W4) of .

[A5] The first interval (I1) is less than the width (W2) of each of the first trench gate structures (70), and the second interval (I2) is less than the width (W2) of each of the first trench gate structures (110). The semiconductor device (1) according to any one of A1 to A4, which has a width (W4) or more.

[A6] The plurality of second trench gate structures (110) have a width (W4) approximately equal to the width (W2) of the plurality of first trench gate structures (70), any one of A1 to A5. The semiconductor device (1) according to any one of the above.

[A7] The plurality of first trench gate structures (70) have a depth (D2) of 1 μm or more and 6 μm or less, and the plurality of second trench gate structures (110) have a depth of 1 μm or more and 6 μm or less. (D4) The semiconductor device (1) according to any one of A1 to A6.

[A8] The plurality of second trench gate structures (110) have a depth (D4) approximately equal to the depth (D2) of the plurality of first trench gate structures (70), A1 to A7. A semiconductor device (1) according to any one of the above.

[A9] The output area (6) has a first planar area, and the protection area (8, 9) has a second planar area less than the first planar area, according to A1 to A8. The semiconductor device (1) according to any one of the above.

[A10] The semiconductor device (1) according to A9, wherein the second planar area is 1/10 or less of the first planar area.

[A11] The output transistor (20) has a first breakdown current per unit area, and the protection transistor (40, 50) has a second breakdown current per unit area that is larger than the first breakdown current. The semiconductor device (1) according to any one of A1 to A10, having a breakdown current.

[A12] The output transistor (20) has a first on-resistance per unit area, and the protection transistor (40, 50) has a second on-resistance larger than the first on-resistance per unit area. The semiconductor device (1) according to any one of A1 to A11, having:

[A13] The plurality of first trench gate structures (70) include a first upper electrode (73) and a first Each of the second trench gate structures (110) has an electrode structure including a lower electrode (74), and the plurality of second trench gate structures (110) are buried vertically in the second trench (111) with insulators (112, 115) in between. The semiconductor device (1) according to any one of A1 to A12, each having an electrode structure including a second upper electrode (113) and a second lower electrode (114).

[A14] A drift region (11) of a first conductivity type (n type) formed in a surface layer portion of the main surface (3) in both the output region (6) and the protection region (8, 9); a first conductivity type (n-type) high concentration drift region (64) formed in the surface layer of the drift region (11) in the output region (6) and having a higher impurity concentration than the drift region (11); , a plurality of the first trench gate structures (70) are formed on the main surface (3) so as to be located within the high concentration drift region (64), and a plurality of the second trench gate structures (70) are formed on the main surface (3) so as to be located within the high concentration drift region (64). The semiconductor device (1) according to any one of A1 to A13, wherein the structure (110) is formed on the main surface (3) so as to be located within the drift region (11).

[A15] The semiconductor device (1) according to A14, wherein the high concentration drift region (64) is not formed in the protection region (8, 9).

[A16] The high concentration drift region (64) is formed at intervals from the bottom of the drift region (11) toward the main surface (3), and the plurality of first trench gate structures (70) include: The semiconductor device (1) according to A14 or A15, wherein the semiconductor device (1) is formed at a distance from the bottom of the high concentration drift region (64) toward the main surface (3).

[A17] A chip (2) having a main surface (3), an output region (6) provided on the main surface (3), and a protection region (8, 9) provided on the main surface (3). a first conductivity type (n type) drift region (11) formed in the surface layer of the main surface (3); and a first conductivity type (n type) drift region (11) formed in the surface layer of the drift region (11) in the output region (6). , a high concentration drift region (64) of a first conductivity type (n type) having a higher impurity concentration than the drift region (11), and a high concentration drift region (64) located within the high concentration drift region (64) in the output region (6). an output transistor (20) having a first trench gate structure (70) formed in the main surface (3) so as to be located in the drift region (11) in the protection region (8, 9); A protection circuit (39) has protection transistors (40, 50) including a second trench gate structure (110) formed on the main surface (3) so as to form a discharge path for overvoltage (Vs1, Vs2). , 49).

[A18] The semiconductor device (1) according to A17, wherein the high concentration drift region (64) is not formed in the protection region (8, 9).

[A19] In A17 or A18, the output area (6) has a first planar area, and the protection area (8, 9) has a second planar area less than the first planar area. The semiconductor device (1) described above.

[A20] The high concentration drift region (64) is formed at a distance from the bottom of the drift region (11) toward the main surface (3), and the first trench gate structure (70) The second trench gate structure (110) is formed at intervals from the bottom of the concentration drift region (64) toward the main surface (3), and the second trench gate structure (110) extends from the bottom of the drift region (11) to the main surface (3). The semiconductor device (1) according to any one of A17 to A19, which is formed with a space between the sides.

[B1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, and a first terminal ( 14, 14a, 14b), a second terminal (15) disposed on the second main surface (4), and a protection transistor (40, 50) formed on the first main surface (3) so as to be electrically interposed between the first terminal (14, 14a, 14b) and the second terminal ( a protection circuit (39, 49) that forms a discharge path for the overvoltage (Vs1, Vs2) generated during A plurality of trench gate structures (110) each having an upper electrode (113) and a lower electrode (114) buried vertically in a formed trench (111) with insulators (112, 115) in between; Semiconductor device (1).

[B2] The semiconductor device (1) according to B1, wherein the plurality of trench gate structures (110) are arranged with an interval (I2) greater than or equal to the width (W4) of each trench gate structure (110). .

[B3] The semiconductor device (1) according to B1 or B2, wherein the plurality of trench gate structures (110) are arranged at intervals (I2) of 0.8 μm or more and 1.6 μm or less.

[B4] The semiconductor device (1) according to any one of B1 to B3, wherein each of the plurality of trench gate structures (110) has a width (W4) of 0.4 μm or more and 2 μm or less.

[B5] The protection transistor (40, 50) includes a first conductivity type (n-type) drift region (11) formed in a surface layer portion of the first main surface (3), and includes a plurality of the trench gates. The semiconductor device (1) according to any one of B1 to B4, wherein the structure (110) is formed on the first main surface (3) so as to be located within the drift region (11).

[B6] The semiconductor device (1) according to B5, wherein the drift region (11) does not have a concentration gradient in which the impurity concentration increases from the bottom side toward the first main surface (3) side.

[B7] The semiconductor device (1) according to B5, wherein the drift region (11) has a constant impurity concentration in the thickness direction.

[B8] The protection circuit (39) includes any one of B1 to B7 that forms a discharge path for the overvoltage (Vs1) generated at the second terminal (15) with the first terminal (14, 14a) as a reference. The semiconductor device (1) according to any one of the above.

[B9] The protection circuit (39) includes a clamp circuit (41) formed on the first main surface (3) so as to be electrically connected to the second terminal (15), and (40, 50) includes a drain electrically connected to the second terminal (15), a source electrically connected to the first terminal (14, 14a), and a clamp circuit (41). The semiconductor device (1) according to B8, comprising a plurality of the trench gate structures (110) as gates electrically connected to the second terminal (15) via.

[B10] The semiconductor device (1) according to B8 or B9, wherein the first terminal (14, 14a) is a ground terminal (14a).

[B11] The protection circuit (49) includes any one of B1 to B7 that forms a discharge path for the overvoltage (Vs2) generated at the first terminal (14, 14b) with the second terminal (15) as a reference. The semiconductor device (1) according to any one of the above.

[B12] The protection transistor (50) has a drain electrically connected to the second terminal (15), a source electrically connected to the first terminal (14, 14b), and a drain electrically connected to the first terminal (14, 14b). The semiconductor device (1) according to B11, comprising a plurality of the trench gate structures (110) as gates electrically connected to terminals (14, 14b).

[B13] An output area (6) provided on the first main surface (3), and a protection area (8, 9), an output terminal (13) arranged on the first main surface (3), and the output terminal so as to be electrically connected to the second terminal (15) and the output terminal (13). further comprising an output transistor (20) formed on the first main surface (3) of the region (6), the protection transistor (40, 50) being formed on the first main surface (3) of the protection region (8, 9). The semiconductor device (1) according to any one of B1 to B12, which is formed on the main surface (3).

[B14] The output transistor (20) includes a second trench (71) formed in the first main surface (3) that is buried vertically with a second insulator (72, 75) in between. The semiconductor device (1) according to B13, comprising a plurality of second trench gate structures (70) each having two upper electrodes (73) and a second lower electrode (74).

[B15] In B13 or B14, the output area (6) has a first planar area, and the protection area (8, 9) has a second planar area less than the first planar area. The semiconductor device (1) described above.

[B16] A control region (7) provided in a region different from the output region (6) on the first main surface (3) and the control region (7) so as to be electrically connected to the output transistor (20). The semiconductor device (1) according to any one of B13 to B15, further comprising a control circuit (23) formed in the region (7) and controlling the output transistor (20).

[B17] The semiconductor device (1) according to B16, wherein the protection region (8, 9) is provided within the control region (7).

[B18] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, and a first terminal ( 14, 14a), a second terminal (14, 14b) arranged on the first main surface (3), and a third terminal (15) arranged on the second main surface (4). and a first protection transistor (40) formed on the first main surface (3) so as to be electrically interposed between the first terminal (14, 14a) and the third terminal (15). a first protection circuit (39) forming a discharge path for the overvoltage (Vs1) generated between the first terminal (14, 14a) and the third terminal (15), and the second terminal (14). , 14b) and the third terminal (15). 14, 14b) and a second protection circuit (49) forming a discharge path for the overvoltage (Vs2) generated between the third terminal (15), and the first protection transistor (40) A first upper electrode (113) and a first lower electrode ( 114), and the second protection transistor (40, 50) is arranged in a second trench (111) formed in the first main surface (3). A semiconductor including a plurality of second trench gate structures (110) each having a second upper electrode (113) and a second lower electrode (114) buried in the vertical direction with second insulators (112, 115) in between. Device (1).

[B19] The first protection transistor (40) forms a discharge path for the overvoltage (Vs1) generated at the third terminal (15) with reference to the first terminal (14, 14a), and The semiconductor device (1) according to B18, wherein the protection transistor (50) forms a discharge path for the overvoltage (Vs2) generated at the second terminal (14, 14b) with the third terminal (15) as a reference. .

[B20] An output terminal (13) arranged on the first main surface (3), and the first terminal so as to be electrically connected to the third terminal (15) and the output terminal (13). further comprising an output transistor (20) formed on the main surface (3), the output transistor (20) being arranged in a third trench (71) formed on the first main surface (3). B18 or B19, including a plurality of third trench gate structures (70) each having a third upper electrode (73) and a third lower electrode (74) buried in the vertical direction with insulators (72, 75) in between. The semiconductor device (1) described in (1).

[B21] The output transistor (20) includes a plurality of system transistors (21, 21A, 21B) each formed on the first main surface (3) so as to be individually controllable; The semiconductor device (1) according to B20, wherein the semiconductor device (1) is configured to generate a single output signal (Io) by selectively controlling the signals 21A and 21B).

[B22] The semiconductor device (1) according to B21, wherein the output transistor (20) is configured to have an on-resistance changed by individual control of the plurality of system transistors (21, 21A, 21B).

Although specific forms have been described in detail above, these are only specific examples that clarify the technical content. Various technical ideas extracted from this specification and the accompanying drawings can be combined as appropriate without being limited to the order of explanation, the order of embodiments, the order of modifications, etc. in the specification.

1 Semiconductor device 2 Chip 3 First main surface 4 Second main surface 6 Output region 7 Control region 8 First protection region 9 Second protection region 11 Drift region 13 Source terminal (output terminal)
14 Control terminal 14a Ground terminal 14b Input terminal 15 Drain terminal 20 Output transistor 21 System transistor 21A First system transistor 21B Second system transistor 23 Control circuit 39 First overvoltage protection circuit (first protection circuit)
40 First protection transistor 41 Clamp circuit 49 Second overvoltage protection circuit (second protection circuit)
50 Second protection transistor 64 High concentration drift region 70 First trench gate structure 71 First gate trench 72 First insulating film 73 First upper electrode 74 Second lower electrode 75 First intermediate insulating film 110 Second trench gate structure 111 2 gate trench 112 second insulating film 113 second upper electrode 114 second lower electrode 115 second intermediate insulating film I1 first interval I2 of first trench gate structure second interval W2 of second trench gate structure first trench gate structure Second width W4 of the second trench gate structure Fourth width D2 of the first trench gate structure Second depth D4 of the first trench gate structure Fourth depth Io of the second trench gate structure Output current Vs1 First overvoltage Vs2 Second overvoltage

Claims (20)

1. a chip having a first main surface on one side and a second main surface on the other side;
   a first terminal disposed on the first main surface;
   a second terminal disposed on the second main surface;
   a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal, and an overvoltage generated between the first terminal and the second terminal; a protection circuit forming a discharge path for the
   The protection transistor includes a plurality of trench gate structures each having an upper electrode and a lower electrode buried vertically in a trench formed in the first main surface with an insulator interposed therebetween.
2. The semiconductor device according to claim 1, wherein the plurality of trench gate structures are arranged at intervals equal to or larger than the width of each trench gate structure.
3. 3. The semiconductor device according to claim 1, wherein the plurality of trench gate structures are arranged at intervals of 0.8 μm or more and 1.6 μm or less.
4. 4. The semiconductor device according to claim 1, wherein each of the plurality of trench gate structures has a width of 0.4 μm or more and 2 μm or less.
5. The protection transistor includes a first conductivity type drift region formed in a surface layer portion of the first main surface,
   5. The semiconductor device according to claim 1, wherein the plurality of trench gate structures are formed on the first main surface so as to be located within the drift region.
6. 6. The semiconductor device according to claim 5, wherein the drift region does not have a concentration gradient in which the impurity concentration increases from the bottom side toward the first main surface side.
7. 6. The semiconductor device according to claim 5, wherein the drift region has a constant impurity concentration in the thickness direction.
8. 8. The semiconductor device according to claim 1, wherein the protection circuit forms a discharge path for the overvoltage generated at the second terminal with reference to the first terminal.
9. The protection circuit includes a clamp circuit formed on the first main surface so as to be electrically connected to the second terminal,
   The protection transistor has a drain electrically connected to the second terminal, a source electrically connected to the first terminal, and an electrically connected to the second terminal via the clamp circuit. 9. The semiconductor device according to claim 8, comprising a plurality of said trench gate structures as gates.
10. The semiconductor device according to claim 8 or 9, wherein the first terminal is a ground terminal.
11. 8. The semiconductor device according to claim 1, wherein the protection circuit forms a discharge path for the overvoltage generated at the first terminal with reference to the second terminal.
12. The protection transistor has a drain electrically connected to the second terminal, a source electrically connected to the first terminal, and a plurality of gates electrically connected to the first terminal. The semiconductor device according to claim 11, having a trench gate structure.
13. an output area provided on the first main surface;
    a protection area provided in an area different from the output area on the first main surface;
    an output terminal disposed on the first main surface;
    further comprising an output transistor formed on the first main surface of the output region so as to be electrically connected to the second terminal and the output terminal,
    13. The semiconductor device according to claim 1, wherein the protection transistor is formed on the first main surface of the protection region.
14. The output transistor includes a plurality of second trench gates each having a second upper electrode and a second lower electrode buried vertically in a second trench formed in the first main surface with a second insulator in between. 14. The semiconductor device according to claim 13, comprising a structure.
15. The output area has a first planar area,
    15. The semiconductor device according to claim 13, wherein the protection region has a second planar area that is less than the first planar area.
16. a control region provided in a region different from the output region on the first main surface;
    16. The semiconductor device according to claim 13, further comprising: a control circuit formed in the control region so as to be electrically connected to the output transistor, and controlling the output transistor.
17. 17. The semiconductor device according to claim 16, wherein the protection region is provided within the control region.
18. a chip having a first main surface on one side and a second main surface on the other side;
    a first terminal disposed on the first main surface;
    a second terminal disposed on the first main surface;
    a third terminal disposed on the second main surface;
    a first protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the third terminal; a first protection circuit forming a discharge path for overvoltage;
    a second protection transistor formed on the first main surface so as to be electrically interposed between the second terminal and the third terminal; a second protection circuit forming an overvoltage discharge path;
    The first protection transistor includes a plurality of first transistors each having a first upper electrode and a first lower electrode buried in a first trench formed in the first main surface in a vertical direction with a first insulator interposed therebetween. including trench gate structure;
    The second protection transistor includes a plurality of second transistors each having a second upper electrode and a second lower electrode buried vertically in a second trench formed in the first main surface with a second insulator in between. A semiconductor device including a trench gate structure.
19. The first protection transistor forms a discharge path for the overvoltage generated at the third terminal with respect to the first terminal,
    19. The semiconductor device according to claim 18, wherein the second protection transistor forms a discharge path for the overvoltage generated at the second terminal with reference to the third terminal.
20. an output terminal disposed on the first main surface;
    further comprising an output transistor formed on the first main surface so as to be electrically connected to the third terminal and the output terminal,
    The output transistor includes a plurality of third trench gates each having a third upper electrode and a third lower electrode buried vertically in a third trench formed in the first main surface with a third insulator in between. The semiconductor device according to claim 18 or 19, comprising a structure.

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