WO2024053216A1 - 信号送信装置 - Google Patents

信号送信装置 Download PDF

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Publication number
WO2024053216A1
WO2024053216A1 PCT/JP2023/023588 JP2023023588W WO2024053216A1 WO 2024053216 A1 WO2024053216 A1 WO 2024053216A1 JP 2023023588 W JP2023023588 W JP 2023023588W WO 2024053216 A1 WO2024053216 A1 WO 2024053216A1
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WO
WIPO (PCT)
Prior art keywords
voltage
output
current
power supply
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/023588
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English (en)
French (fr)
Japanese (ja)
Inventor
信也 増田
将希 板坂
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024545455A priority Critical patent/JPWO2024053216A1/ja
Publication of WO2024053216A1 publication Critical patent/WO2024053216A1/ja
Priority to US19/063,813 priority patent/US20250219634A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines

Definitions

  • the present disclosure relates to a signal transmitting device.
  • a type of signal transmitting device needs to satisfy both the required performance regarding the slew rate of the output signal and the required performance regarding the radiation noise.
  • An object of the present disclosure is to provide a signal transmitting device that contributes to achieving both the required performance regarding the slew rate of an output signal and the required performance regarding radiation noise.
  • a signal transmitting device includes an output terminal configured to be connected to an application end of a power supply voltage via a pull-up resistor and a reverse current prevention diode, and an output transistor provided between the output terminal and ground. a capacitor connected between the gate of the output transistor and the output terminal; and a charging/discharging circuit configured to charge or discharge the gate of the output transistor according to an input signal, the output transistor An output signal corresponding to the input signal is generated at the output terminal by turning on or off the output transistor through charging or discharging of the gate of The charging/discharging circuit sets a charging current and a discharging current to the gate of the output transistor as a current to be adjusted, and nonlinearly changes the current to be adjusted in accordance with the power supply voltage.
  • FIG. 1 is an overall configuration diagram of a communication system according to an embodiment of the present disclosure.
  • FIG. 2 is an external perspective view of a transceiver according to an embodiment of the present disclosure.
  • FIG. 3 is a configuration diagram of a transmitting circuit in a transceiver according to an embodiment of the present disclosure.
  • FIG. 4 is a diagram for explaining signal output conditions according to the embodiment of the present disclosure.
  • FIG. 5 is a diagram schematically showing waveforms of a control input signal and an output voltage according to a reference method.
  • FIG. 6 is a diagram showing the relationship between power supply voltage and charging current or discharging current according to the reference method.
  • FIG. 1 is an overall configuration diagram of a communication system according to an embodiment of the present disclosure.
  • FIG. 2 is an external perspective view of a transceiver according to an embodiment of the present disclosure.
  • FIG. 3 is a configuration diagram of a transmitting circuit in a transceiver according to an embodiment of the present disclosure.
  • FIG. 4 is
  • FIG. 7 is a diagram showing how easily the output signal condition and the radiation noise condition are satisfied in the relationship between the power supply voltage and the charging current or the discharging current, according to the reference method.
  • FIG. 8 is a diagram schematically showing waveforms of the control input signal and output voltage when the power supply voltage is relatively high.
  • FIG. 9 is a diagram schematically showing the waveforms of the control input signal and output voltage when the power supply voltage is relatively low.
  • FIG. 10 is a relationship diagram between power supply voltage and charging current or discharging current according to an embodiment of the present disclosure.
  • FIG. 11 is a relationship diagram between power supply voltage and output slew rate according to an embodiment of the present disclosure.
  • FIG. 12 is a configuration diagram of a current generation circuit according to an embodiment of the present disclosure.
  • bus connection terminal BUS referred to by "BUS" below (see Figure 1) may be written as bus connection terminal BUS or may be abbreviated as terminal BUS, but all of them are refer to the same thing.
  • Line refers to wiring through which electrical signals are propagated or applied.
  • the ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself.
  • the reference conductive part may be formed using a conductor such as metal.
  • the potential of 0V is sometimes referred to as a ground potential.
  • voltages shown without particular reference represent potentials as seen from ground.
  • Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.
  • a signal or voltage being at a high level strictly means that the level of the signal or voltage is at a high level, and a signal or voltage being at a low level does not strictly mean that the level of the signal or voltage is at a high level. It means that the signal or voltage level is at low level.
  • the level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.
  • a switch from a low level to a high level in any signal or voltage of interest is called an up edge. You can read up edge as rising edge. Similarly, a transition from a high level to a low level in any signal or voltage of interest is referred to as a down edge. You can read down edge as falling edge.
  • an on state refers to a state in which the drain and source of the transistor are electrically connected
  • an off state refers to a state in which the drain and source of the transistor are electrically connected. Refers to the state where there is no conduction between the two (blocked state).
  • the MOSFET is understood to be an enhancement type MOSFET unless otherwise specified.
  • MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor.”
  • the back gate of any MOSFET may be considered to be short-circuited to the source.
  • the period during which the level of the signal is high level is referred to as the high level period
  • the period during which the level of the signal is at low level is referred to as the low level period.
  • Connections between multiple parts forming a circuit such as arbitrary circuit elements, wiring (lines), and nodes, may be understood to refer to electrical connections, unless otherwise specified.
  • FIG. 1 shows an overall configuration diagram of a communication system 1 according to an embodiment of the present disclosure.
  • the communication system 1 includes a transceiver 10, a microcomputer 20, and a counterpart device 30.
  • the bus line 51, pull-up resistor 52, backflow prevention diode 53, capacitor 54, data line 61, data line 62, and pull-up resistor 63 are also included in the components of the communication system 1.
  • FIG. 2 is an external perspective view of the transceiver 10.
  • the transceiver 10 includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed to the outside of the transceiver 10 from the housing. It is an electronic component equipped with The transceiver 10 is formed by enclosing a semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the transceiver 10 and the type of casing of the transceiver 10 shown in FIG. 2 are merely examples, and they can be designed arbitrarily. FIG.
  • a power supply terminal VIN shows a power supply terminal VIN, a bus connection terminal BUS, a ground terminal GND, a reception data output terminal RXD, and a transmission data input terminal TXD, which are included in the plurality of external terminals.
  • External terminals other than these may also be provided in the transceiver 10.
  • a power supply voltage VDD is supplied from a voltage source (not shown) to the power supply terminal VIN.
  • Power supply voltage VDD has a predetermined positive DC voltage value.
  • Transceiver 10 is driven based on power supply voltage VDD.
  • a ground terminal GND is connected to ground.
  • the bus connection terminal BUS is connected to one end of the bus line 51, and the other end of the bus line 51 is connected to the counterpart device 30. That is, the bus connection terminal BUS is connected to the counterpart device 30 via the bus line 51.
  • the counterpart device 30 also has a terminal receiving the power supply voltage VDD and a terminal connected to the ground, and is driven based on the power supply voltage VDD.
  • the bus line 51 is connected to the application end 50 of the power supply voltage VDD via a pull-up resistor 52 and a backflow prevention diode 53.
  • the application terminal 50 is a terminal to which the power supply voltage VDD is applied.
  • the backflow prevention diode 53 has a forward direction from the application end 50 toward the bus line 51 and the bus connection terminal BUS.
  • the backflow prevention diode 53 prevents current from flowing from the bus line 51 to the application end 50 . More specifically, the anode of the backflow prevention diode 53 is connected to the application terminal 50, the cathode of the backflow prevention diode 53 is connected to one end of the pull-up resistor 52, and the other end of the pull-up resistor 52 is connected to the bus line 51. connected to.
  • the application end 50 may be connected to the anode of the backflow prevention diode 53 via the pull-up resistor 52, and the cathode of the backflow prevention diode 53 may be connected to the bus line 51.
  • a capacitor 54 is connected between the bus line 51 and ground. That is, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. Note that the capacitor 54 may be composed of a plurality of capacitors separated from each other. Capacitor 54 may be omitted.
  • the received data output terminal RXD is connected to one end of the data line 61, and the other end of the data line 61 is connected to the microcomputer 20.
  • the transmission data input terminal TXD is connected to one end of the data line 62, and the other end of the data line 62 is connected to the microcomputer 20. That is, terminals RXD and TXD are connected to microcomputer 20 via data lines 61 and 62.
  • Data line 61 is connected to the application terminal of power supply voltage VCC via pull-up resistor 63.
  • Power supply voltage VCC has a predetermined positive DC voltage value. It does not matter whether the values of the power supply voltages VCC and VDD match or do not match.
  • the microcomputer 20 has a terminal receiving the power supply voltage VCC and a terminal connected to the ground, and is driven based on the power supply voltage VCC.
  • the transceiver 10 includes a receiving circuit RX and a transmitting circuit TX.
  • the receiving circuit RX is connected to a received data output terminal RXD and a bus connection terminal BUS.
  • the transmission circuit TX is connected to a transmission data input terminal TXD and a bus connection terminal BUS.
  • the transceiver 10 and the other device 30 perform bidirectional communication via the bus line 51 in a half-duplex manner.
  • the bidirectional communication assumed in this embodiment is serial communication using a single wire method (that is, serial communication using the bus line 51, which is one wire).
  • the transceiver 10 may function as a master and the other device 30 may function as a slave, or the other device 30 may function as a master and the transceiver 10 may function as a slave.
  • the two-way communication between the transceiver 10 and the other device 30 may be, for example, two-way communication based on the LIN (Local Interconnect Network) standard or the CXPI (Clock Extension Peripheral Interface) standard.
  • one of the transceiver 10 and the other device 30 operates as a transmitting device, and the other functions as a receiving device.
  • the transceiver 10 When the transceiver 10 functions as a receiving device, the counterpart device 30 transmits a signal (hereinafter referred to as signal S R ) via the bus line 51, and the receiving circuit RX transmits a signal to the counterpart device 30 via the bus connection terminal BUS. Receives the signal S R transmitted from the terminal. The receiving circuit RX transmits the received signal S R from the terminal RXD to the microcomputer 20 via the data line 61.
  • the bus connection terminal BUS functions as an input terminal (signal receiving terminal) that receives a signal transmitted from the counterpart device 30.
  • transceiver 10 When transceiver 10 functions as a transmitting device, microcomputer 20 transmits a signal (hereinafter referred to as signal S T ) to transceiver 10 via data line 62 . A signal S T from the microcomputer 20 is received at the terminal TXD.
  • the transmitting circuit TX transmits the signal S T received from the microcomputer 20 to the counterpart device 30 via the bus line 51.
  • the counterpart device 30 may be configured with a transceiver and microcomputer set equivalent to the transceiver 10 and the microcomputer 20, and in this case, the signal S T received from the transceiver 10 is transmitted from the transceiver in the counterpart device 30 to the counterpart device. The information is transmitted to the microcomputer in the side device 30.
  • the bus connection terminal BUS functions as an output terminal (signal transmission terminal) at which a signal to be transmitted from the transceiver 10 appears.
  • Transmission of a signal via the bus line 51 is realized by controlling the level of the bus line 51 to a high level or a low level.
  • the level of the bus line 51 and the level of the bus connection terminal BUS are the same.
  • the level of the bus line 51 is higher than 0V and lower than the power supply voltage VDD.
  • VDD ⁇ k H the level of the bus line 51 corresponds to a high level
  • VDD ⁇ k L the voltage (VDD ⁇ k L )
  • Level 51 corresponds to the low level.
  • the voltage V BUS corresponds to the output voltage (output voltage of the transmitting circuit TX). Therefore, the voltage V BUS when focusing on the configuration or operation of the transmitting circuit TX may be referred to as an output voltage hereinafter.
  • the signal indicated by the output voltage V BUS can be referred to as an output signal.
  • the transmission circuit TX in the transceiver 10 adjusts the slew rate of the output voltage V BUS in order to reduce radiation noise when the level of the bus line 51 changes between a high level and a low level when transmitting a signal via the bus line 51. It has the ability to control.
  • FIG. 3 shows the basic configuration of the transmitting circuit TX.
  • the transmission circuit TX according to the basic configuration includes an output transistor 111, a capacitor (feedback capacitor) 112, a backflow prevention diode 113, a charging/discharging circuit 120, a control input signal supply circuit 130, and a gate voltage limiting circuit 140. Be prepared.
  • the output transistor 111 is an N-channel MOSFET.
  • the output transistor 111 is provided between the bus connection terminal BUS functioning as an output terminal and the ground, and the transmission circuit TX transmits a signal using the output transistor 111 having an open drain configuration.
  • a backflow prevention diode 113 is provided between the output transistor 111 and the bus connection terminal BUS to prevent the flow of current from the ground toward the bus line 51 via the output transistor 111 and the bus connection terminal BUS.
  • the drain of the output transistor 111 is connected to the cathode of the backflow prevention diode 113, and the anode of the backflow prevention diode 113 is connected to the bus connection terminal BUS.
  • the source of output transistor 111 is connected to ground.
  • the gate voltage of the output transistor 111 (that is, the voltage applied to the gate of the output transistor 111) is represented by the symbol “V G ".
  • the gate threshold voltage of the output transistor 111 is represented by the symbol “V G_TH “.
  • the gate threshold voltage V G_TH has a positive voltage value that depends on the characteristics of the output transistor 111.
  • a capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. That is, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.
  • the charging/discharging circuit 120 charges or discharges the gate of the output transistor 111 according to the control input signal S IN .
  • the charging/discharging circuit 120 can control the output transistor 111 to turn on by charging the gate of the output transistor 111, and can control the output transistor 111 to turn off by discharging the gate of the output transistor 111.
  • the control input signal S IN is a binary signal having a high or low signal level.
  • the high level control input signal S IN has substantially the potential of the internal power supply voltage V REG
  • the low level control input signal S IN has substantially the ground potential.
  • a regulator (not shown) within transceiver 10 generates internal power supply voltage V REG , which is a positive DC voltage, from power supply voltage VDD.
  • the charging/discharging circuit 120 includes a charging circuit 121 and a discharging circuit 122.
  • the charging circuit 121 increases the gate voltage V G of the output transistor 111 by supplying a charging current to the gate of the output transistor 111 during the high level period of the control input signal S IN .
  • the gate voltage V G has an upper limit, and the gate voltage V G does not rise beyond the upper limit voltage.
  • the upper limit voltage of the gate voltage V G is the internal power supply voltage V REG or a predetermined voltage lower than the internal power supply voltage V REG .
  • the upper limit voltage of the gate voltage V G is higher than the gate threshold voltage V G_TH of the output transistor 111.
  • the output transistor 111 switches from the off state to the on state. Specifically, in the process of increasing the gate voltage V G from a sufficiently low voltage (for example, 0 V), when the gate voltage V G becomes equal to or higher than the gate threshold voltage V G_TH , the resistance value of the channel of the output transistor 111 sharply decreases. When the resistance value of the channel of the output transistor 111 becomes sufficiently smaller than the resistance value of the pull-up resistor 52, the voltage V BUS decreases to substantially 0V.
  • the resistance value of the channel of the output transistor 111 refers to the resistance value between the drain and source of the output transistor 111.
  • the discharging circuit 122 lowers the gate voltage V G of the output transistor 111 by drawing a discharge current from the gate of the output transistor 111 during the low level period of the control input signal S IN .
  • the gate voltage V G has a lower limit, and the gate voltage V G does not fall below the lower limit voltage.
  • the lower limit voltage of the gate voltage V G is 0V. In the process of decreasing the gate voltage V G from a voltage higher than the gate threshold voltage V G_TH , when the gate voltage V G becomes lower than the gate threshold voltage V G_TH , the output transistor 111 switches from the on state to the off state.
  • the resistance value of the channel of the output transistor 111 increases sharply.
  • the output voltage V BUS increases to near the power supply voltage VDD.
  • the charging circuit 121 is configured by a series circuit of a charging current source 121a and a switch 121b
  • the discharging circuit 122 is configured by a series circuit of a discharging current source 122a and a switch 122b.
  • the charging current source 121a is provided between the application end of the internal power supply voltage V REG and the switch 121b, and generates a current I C based on the internal power supply voltage V REG .
  • Switch 121b is provided between charging current source 121a and node 123.
  • the discharge current source 122a is provided between the ground and the switch 122b, and generates a current I D based on the internal power supply voltage V REG .
  • Switch 122b is provided between discharge current source 122a and node 123. Node 123 is connected to the gate of output transistor 111. Switches 121b and 122b are controlled to be turned on or off based on a control input signal S IN .
  • a current I C (hereinafter referred to as charging current I C ) for increasing the gate voltage V G is output from the charging current source 121a via the switch 121b and the node 123. It is supplied to the gate of transistor 111.
  • charging current I C a current I C for increasing the gate voltage V G is output from the charging current source 121a via the switch 121b and the node 123. It is supplied to the gate of transistor 111.
  • the low level period of the control input signal S IN there is no charge exchange between the gate of the output transistor 111 and the charging circuit 121.
  • the switch 121b is turned off while the switch 122b is turned on. Therefore, during the low level period of the control input signal S IN , the current I D (hereinafter referred to as discharge current I D ) for lowering the gate voltage V G is discharged from the gate of the output transistor 111 via the node 123 and the switch 122b. current source 122a.
  • discharge current I D for lowering the gate voltage V G is discharged from the gate of the output transistor 111 via the node 123 and the switch 122b. current source 122a.
  • the high level period of the control input signal S IN there is no charge exchange between the gate of the output transistor 111 and the discharge circuit 122.
  • the control input signal supply circuit 130 generates a control input signal S IN based on the signal S T received from the microcomputer 20 and supplies the control input signal S IN to the charging/discharging circuit 120 .
  • the control input signal supply circuit 130 may generate, for example, a binary signal obtained by shaping the waveform of the signal S T as the control input signal S IN .
  • the configuration of the charging circuit 121 is arbitrary as long as the charging current I C can be supplied to the gate of the output transistor 111 during the high level period of the control input signal S IN .
  • the charging circuit 121 may stop generating the charging current I C during the low level period of the control input signal S IN . In any case, the charging current I C flowing from the charging circuit 121 to the gate of the output transistor 111 is zero during the low level period of the control input signal S IN .
  • the configuration of the discharge circuit 122 is arbitrary as long as the discharge current ID can be drawn from the gate of the output transistor 111 during the low level period of the control input signal S IN .
  • the discharge circuit 122 may stop generating the discharge current ID during the high level period of the control input signal S IN . In any case, the discharge current ID flowing from the gate of the output transistor 111 to the discharge circuit 122 is zero during the high level period of the control input signal S IN .
  • Gate voltage limiting circuit 140 is connected to the gate of output transistor 111 and ground.
  • Gate voltage limiting circuit 140 has two diodes 141 and 142.
  • the anode of diode 141 is connected to the gate of output transistor 111
  • the cathode of diode 141 is connected to the anode of diode 142
  • the cathode of diode 142 is connected to ground.
  • the gate voltage limiting circuit 140 has a function of suppressing the gate voltage V G from exceeding a predetermined limit voltage V LIM , and may be any circuit having this function.
  • the limiting voltage V LIM here is higher than the gate threshold voltage V G_TH , and corresponds to the sum of the forward voltages of the diodes 141 and 142 in the configuration example of FIG.
  • the circuit 140 may be formed by a series circuit of three or more diodes.
  • the output transistor 111 In the process in which the output transistor 111 is switched from the OFF state to the ON state due to an increase in the gate voltage V G based on the charging current I C , the output voltage V BUS decreases, and the decrease in the output voltage V BUS is transferred to the output transistor 111 via the capacitor 112 . feedback to the gate. Conversely, in the process in which the output transistor 111 is switched from the on state to the off state due to a decrease in the gate voltage V G based on the discharge current ID, the output voltage V BUS increases, and the increase in the output voltage V BUS is caused through the capacitor 112. It is fed back to the gate of the output transistor 111. Therefore, to the charge/discharge circuit 120, the capacitance value of the capacitor 112 appears to be equivalently larger than the actual capacitance value of the capacitor 112 due to the Miller effect. In other words, the capacitor 112 functions as a Miller capacitance.
  • the slew rate of the output voltage V BUS includes a rising slew rate, which is the slew rate when the output voltage V BUS increases, and a falling slew rate, which is the slew rate when the output voltage V BUS decreases.
  • the rising slew rate refers to the maximum value or average value of the rate of change of the output voltage V BUS when the output voltage V BUS rises.
  • the falling slew rate refers to the maximum value or average value of the rate of change of the output voltage V BUS when the output voltage V BUS decreases.
  • the rising slew rate and the falling slew rate will be collectively referred to as the output slew rate.
  • the output slew rate is understood to refer to either the rising slew rate or the falling slew rate, or to both the rising slew rate and the falling slew rate.
  • the output signal conditions here may be, for example, conditions defined by the LIN standard or the CXPI standard.
  • FIG. 4 shows the waveforms of the control input signal S IN and the output voltage V BUS .
  • the control input signal S IN has an output high indication level, which indicates that the output voltage V BUS (i.e., the output signal) has a high level, and an output high instruction level, which indicates that the output voltage V BUS (i.e., the output signal) has a low level.
  • the output low indication level is taken alternately.
  • the charging/discharging circuit 120 controls the output transistor 111 to be in an on state by charging the gate of the output transistor 111 during a period in which the control input signal S IN has an output low instruction level, and controls the output transistor 111 to be in an on state while the control input signal S IN has an output high instruction level.
  • the output transistor 111 is controlled to be in an off state.
  • the output low instruction level in the control input signal S IN is a high level
  • the output high instruction level in the control input signal S IN is a low level
  • the output low instruction level in the control input signal S IN is a high level
  • the output high instruction level in the control input signal S IN is a low level
  • the output low instruction level in the control input signal S IN is a high level.
  • a modification is also possible in which the output signal is set to a low level and the output high instruction level is set to a high level.
  • the length of the low level period of the control input signal S IN (ie, the period in which the control input signal S IN has an output high instruction level) is represented by time T A .
  • the low level period and the high level period of the control input signal S IN occur alternately and repeatedly, but the length of one low level period of interest among the low level periods of the control input signal S IN is time T A .
  • the time from time t 1 to time t 3 is time T A.
  • time t 2 shown in FIG. 4 is after time t 1 and before time t 3 .
  • Time t 4 is a time after time t 3 .
  • the output voltage V BUS continues to rise after time t 2 .
  • the output signal condition is that the ratio of time T B to time T A , ie, the ratio (T B / TA ), is greater than or equal to a predetermined threshold value R TH .
  • the forward voltage of the reverse current prevention diode 53 is represented by the symbol "Vf".
  • Vf The forward voltage of the reverse current prevention diode 53.
  • the signal ST also takes an output high instruction level and an output low instruction level alternately, and the control input signal supply circuit 130 receives the signal ST of the output high instruction level and changes the level of the control input signal S IN to the output high instruction level. , and in response to the signal S T at the output low instruction level, sets the level of the control input signal S IN to the output low instruction level. Therefore, the time T A may be understood to correspond to the length of the period in which the signal S T has the output high indication level.
  • the control input signal S IN may be a binary signal obtained by shaping the waveform of the signal S T from the microcomputer 20, and the control input signal S IN may be a signal equivalent to the signal S T. It's good.
  • the signal S T itself may be understood as the control input signal S IN .
  • the power supply voltage VDD has a voltage within the power supply voltage range from the minimum voltage VDD MIN to the maximum voltage VDD MAX .
  • the minimum voltage VDD MIN and the maximum voltage VDD MAX have positive predetermined voltage values satisfying "0 ⁇ VDD MIN ⁇ VDD MAX ".
  • the transceiver 10 must also meet radiated noise conditions according to the standards applied to the communication system 1 (for example the LIN standard or the CXPI standard).
  • the radiated noise condition for the transceiver 10 is satisfied.
  • a radiation noise test is conducted to actually measure the amount of radiation noise from the communication system 1 when the transceiver 10 is operated as a transmitting device in a predetermined noise test environment, and based on the measured value, whether the radiation noise conditions are met or not. Sufficiency is determined.
  • the power supply voltage VDD in the noise test environment is a test voltage VDD TYP having a representative value within the power supply voltage range.
  • the test voltage VDD TYP is higher than the minimum voltage VDD MIN and lower than the maximum voltage VDD MAX .
  • VDD TYP (VDD MIN + VDD MAX )/2.
  • FIG. 5 schematically shows the waveforms of the control input signal S IN and the output voltage V BUS when the reference method is adopted.
  • a rectangular waveform 910 is the waveform of the control input signal S IN
  • the charging current I C and the discharging current ID are made proportional to the power supply voltage VDD, thereby making the output slew rate proportional to the power supply voltage VDD.
  • a solid line 920 represents the relationship between the power supply voltage VDD and the charging current I C or the discharging current ID according to the reference method.
  • output slew rate There is a trade-off relationship between output slew rate and radiation noise. That is, in the reference method, if the proportionality constant when making each value of the charging current I C and the discharging current I D proportional to the power supply voltage VDD is increased as shown by changing from the solid line 920 to the broken line 921 in FIG.
  • the output As the slew rate increases, it becomes easier to satisfy the output signal condition, but it becomes harder to satisfy the radiation noise condition.
  • the proportionality constant when making each value of charging current I C and discharging current I D proportional to power supply voltage VDD is decreased as shown by changing from solid line 920 to broken line 922 in FIG. 7, the output slew rate can be changed. As the radiated noise condition decreases, it becomes easier to satisfy the radiation noise condition, but it becomes difficult to satisfy the output signal condition.
  • the output signal condition is basically more difficult to satisfy as the power supply voltage VDD becomes lower.
  • it is necessary to increase the ratio (T B / TA ), but as the ratio of the forward voltage Vf (forward voltage Vf of the reverse current prevention diode 53) that occupies the power supply voltage VDD increases, This is because the ratio (T B / TA ) tends to decrease.
  • the time required for the output voltage V BUS to rise by about 0.814 times the voltage (VDD - Vf) is the time required for the output voltage V BUS to rise by about 0.719 times the voltage (VDD - Vf). longer than the time it takes to As a result, with the reference method, it becomes difficult to satisfy the output signal condition when the power supply voltage VDD matches or approximates the minimum voltage VDD MIN (on the contrary, if the output slew rate is increased to satisfy the output signal condition, it becomes difficult to satisfy the radiation noise condition) Become).
  • the transceiver 10 according to the present embodiment an improved method different from the reference method is adopted.
  • the charging current I C and the discharging current ID are changed nonlinearly according to the power supply voltage VDD. See FIG. 10.
  • a solid line 620 indicates the relationship between the power supply voltage VDD and the current to be adjusted according to the improved method, that is, the relationship between the power supply voltage VDD and the current to be adjusted in the transceiver 10.
  • the current to be adjusted refers to a current whose current value is adjusted according to the power supply voltage VDD, and the charging/discharging circuit 120 nonlinearly changes the current to be adjusted (the value of the current to be adjusted) according to the power supply voltage VDD.
  • the charging current I C during the high level period of the control input signal S IN and the discharging current I D during the low level period of the control input signal S IN correspond to the current to be adjusted.
  • the dashed line 920 in FIG. 10 refers to the same as the corresponding solid line 920 in FIG.
  • the voltage VDD MID shown in FIG. 10 is a predetermined boundary voltage, which is higher than the minimum voltage VDD MIN and lower than the maximum voltage VDD MAX .
  • the charging current source 121a is configured as a variable current source with a variable charging current I C value
  • the discharging current source 122a is configured as a variable current source with a variable discharging current ID value.
  • the charging/discharging circuit 120 sets the value of the charging current I C and the value of the discharging current ID according to the power supply voltage VDD, that is, sets the value of the current to be adjusted.
  • the charging/discharging circuit 120 sets the value of the current to be adjusted (each value of the charging current I C and the discharging current ID ) to a predetermined reference current value VAL. Set and maintain in REF .
  • the charging/discharging circuit 120 makes the value of the current to be adjusted (each value of the charging current I C and the discharging current ID ) larger than the reference current value VAL REF , and It is increased as the voltage VDD increases.
  • k P is a coefficient having a predetermined positive value.
  • the reference current value VAL REF for the charging current I C and the reference current value VAL REF for the discharging current ID may be the same or different.
  • the boundary voltage VDD MID may match the above-mentioned test voltage VDD TYP .
  • the boundary voltage VDD MID may be close to the test voltage VDD TYP but higher than the test voltage VDD TYP .
  • the current to be adjusted may be increased in accordance with the increase in the power supply voltage VDD so that the output signal condition is satisfied even when "VDD>VDD MID ".
  • values J1 and J2 are defined as follows.
  • the charging/discharging circuit 120 changes the current to be adjusted according to the power supply voltage VDD so that the value J1 becomes higher than the value J2.
  • “J1>J2” is an inequality that expresses part of the characteristics of FIGS. 10 and 11.
  • FIG. 12 shows a current generation circuit 200 as an example of a circuit that generates a current to be adjusted.
  • the current generating circuit 200 can be provided in the charging/discharging circuit 120.
  • the current to be adjusted generated by the current generation circuit 200 is referred to by the symbol "I ADJ ".
  • the current to be adjusted I ADJ is the charging current I C or the discharging current I D.
  • the current generation circuit 200 includes a transistor 201 that is a P-channel MOSFET, a clamper 202 that generates and outputs a clamp voltage V CLMP , resistors 203 to 206, an operational amplifier 207, and a V/I conversion circuit 208. .
  • a power supply voltage VDD is applied to the source of the transistor 201 and one end of the resistor 203.
  • the gate of the transistor 201 and the other end of the resistor 203 are connected to each other and receive a clamp voltage V CLMP supplied from the clamper 202 .
  • the clamp voltage V CLMP has a predetermined positive DC voltage value.
  • the above-mentioned boundary voltage VDD MID is determined depending on the clamp voltage V CLMP .
  • the drain of transistor 201 is connected to node 211 via resistor 204.
  • a constant positive voltage V CNST is applied to one end of the resistor 205, and the other end of the resistor 205 is connected to the node 211.
  • One end of resistor 206 is connected to node 211, and the other end of resistor 206 is connected to ground.
  • the voltage applied to node 211 is referred to as voltage Va.
  • the operational amplifier 207 constitutes an impedance conversion circuit that outputs the voltage Va at the node 211 to the node 212 at low impedance.
  • the voltage applied to node 212 is referred to as voltage Vb.
  • the operational amplifier 207 functions as a voltage follower, and the voltage Vb is equal to the voltage Va (ignoring errors).
  • the non-inverting input terminal of operational amplifier 207 is connected to node 211, and the inverting input terminal and output terminal of operational amplifier 207 are connected to node 212.
  • V/I conversion circuit 208 is connected to node 212 and converts voltage Vb into adjustment target current I ADJ .
  • the V/I conversion circuit 208 causes the current to be adjusted I ADJ to have a current value proportional to the value of the voltage Vb.
  • VDD>VDD MID the source potential of the transistor 201 becomes equal to or higher than the gate threshold voltage of the transistor 201 when viewed from the gate potential of the transistor 201, and the transistor 201 is turned on.
  • VDD>VDD MID a current corresponding to the power supply voltage VDD flows from the application terminal of the power supply voltage VDD to the node 211 via the transistor 201 and the resistor 204, and the current through the transistor 201 increases the voltages Va and Vb. Rise. Therefore, when "VDD>VDD MID ", the value of the current to be adjusted I ADJ becomes larger than the reference current value VAL REF and increases as the power supply voltage VDD rises.
  • a current generating circuit 200 that generates the charging current I C as the current to be adjusted I ADJ and a current generating circuit 200 that generates the discharging current I D as the current to be adjusted I ADJ may be separately provided in the charging/discharging circuit 120 .
  • two V/I conversion circuits 208 may be provided in a single current generation circuit 200.
  • the first V/I conversion circuit 208 is connected to the node 212 to convert the voltage Vb at the node 212 into a charging current I C
  • the second V/I conversion circuit 208 is connected to the node 212 to convert the voltage Vb at the node 212 to a charging current I C .
  • the voltage Vb at 212 may be converted into a discharge current ID .
  • the communication system 1 can be mounted on a vehicle such as an automobile.
  • the communication system 1 can be used as a system for performing bidirectional communication in accordance with the LIN standard or the CXPI standard. More specifically, for example, communication between the transceiver 10 and the other device 30 can be used to communicate signals for realizing body control of power windows, mirrors, electric seats, door locks, etc. installed in a car. can.
  • the communication system 1 is not limited to in-vehicle use.
  • the communication system 1 can be applied to any application where relatively low-speed communication is performed.
  • the transceiver 10 includes a signal transmitting device that generates an output signal corresponding to an input signal at a bus connection terminal BUS functioning as an output terminal (in other words, transmits it from the bus connection terminal BUS).
  • the components of the signal transmitting device include a transmitting circuit TX, and may also include a bus connection terminal BUS.
  • the input signal for the signal transmitting device can be understood as the control input signal S IN . Since the control input signal S IN is a signal based on the signal S T from the microcomputer 20, it may be understood that the input signal to the signal transmitting device is the signal S T .
  • a semiconductor device including the functions of the transceiver 10 and the microcomputer 20 may be formed, and in this case, a signal transmitting device will be provided within the semiconductor device.
  • channels of FETs field effect transistors
  • the channel type of any FET may be varied between P-channel and N-channel.
  • any transistor mentioned above may be any type of transistor as long as no inconvenience occurs.
  • any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience occurs.
  • Any transistor has a first electrode, a second electrode, and a control electrode.
  • a FET one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate.
  • an IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate.
  • a bipolar transistor that does not belong to an IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.
  • a signal transmitting device (10) is configured to be connected to an application terminal (50) of a power supply voltage (VDD) via a pull-up resistor (52) and a reverse current prevention diode (53).
  • An output terminal (BUS) an output transistor (111) provided between the output terminal and ground, a capacitor (112) connected between the gate of the output transistor and the output terminal, and an input signal (S a charging/discharging circuit (120) configured to charge or discharge the gate of the output transistor in response to IN ), turning the output transistor on or off through charging or discharging the gate of the output transistor.
  • the reverse current prevention diode has a forward direction from the application end of the power supply voltage to the output terminal
  • the charging/discharging circuit includes: A configuration (first configuration) in which a charging current (I C ) and a discharging current (I D ) for the gate of the output transistor are set as a current to be adjusted, and the current to be adjusted is nonlinearly changed according to the power supply voltage. be.
  • the charging circuit is configured such that the power supply voltage is a predetermined first voltage value, as compared to a case where the power supply voltage has a predetermined first voltage value (for example, VDD MIN or VDD MID ).
  • a predetermined first voltage value for example, VDD MIN or VDD MID
  • a configuration in which the current to be adjusted is set to be large and a nonlinear relationship is created between the power supply voltage and the current to be adjusted when the voltage has a predetermined second voltage value (for example, VDD MAX ) larger than the current value. (second configuration).
  • the charging circuit changes the value of the current to be adjusted to a predetermined reference current value ( VAL REF ), and when the power supply voltage exceeds the boundary voltage, the value of the current to be adjusted is made larger than the reference current value and increases as the power supply voltage increases (third configuration). It's okay.
  • the power supply voltage is within a voltage range from a predetermined minimum voltage (VDD MIN ) to a predetermined maximum voltage (VDD MAX ), and the The circuit makes the first value (J1) higher than the second value (J2) by changing the current to be adjusted according to the power supply voltage, and the first value is set when the power supply voltage is the minimum value.
  • the second value is a value obtained by dividing the slew rate of the output signal when the voltage matches the maximum voltage
  • the second value is the value obtained by dividing the slew rate of the output signal when the power supply voltage matches the maximum voltage.
  • the value may be obtained by dividing the slew rate by the maximum voltage (fourth configuration).
  • the charging/discharging circuit charges the gate of the output transistor to output the output when the input signal has a first level (for example, a high level).
  • the charging/discharging circuit turns on the transistor and turns off the output transistor by discharging the gate of the output transistor when the input signal has a second level (for example, a low level); a charging circuit (121) configured to supply the charging current to the gate of the output transistor during a period in which the input signal has a second level;
  • the drain of the output transistor is connected to the output terminal via another backflow prevention diode (113) having a forward direction from the output terminal to the ground.
  • the drain of the output transistor may be directly connected to the output terminal (sixth configuration).

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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
PCT/JP2023/023588 2022-09-08 2023-06-26 信号送信装置 Ceased WO2024053216A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05191241A (ja) * 1992-01-16 1993-07-30 Fujitsu Ltd 半導体集積回路
JP2011250345A (ja) * 2010-05-31 2011-12-08 Rohm Co Ltd トランスミッタ、インタフェイス装置、車載通信システム
JP2013247564A (ja) * 2012-05-28 2013-12-09 Yamaha Corp 出力バッファ回路
JP2017200103A (ja) * 2016-04-28 2017-11-02 ローム株式会社 信号処理装置及びバス通信システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05191241A (ja) * 1992-01-16 1993-07-30 Fujitsu Ltd 半導体集積回路
JP2011250345A (ja) * 2010-05-31 2011-12-08 Rohm Co Ltd トランスミッタ、インタフェイス装置、車載通信システム
JP2013247564A (ja) * 2012-05-28 2013-12-09 Yamaha Corp 出力バッファ回路
JP2017200103A (ja) * 2016-04-28 2017-11-02 ローム株式会社 信号処理装置及びバス通信システム

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