WO2024053022A1

WO2024053022A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2024053022A1
Application number: PCT/JP2022/033581
Authority: WO
Inventors: 皓洋小山; 俊明岩松
Original assignee: 三菱電機株式会社
Priority date: 2022-09-07
Filing date: 2022-09-07
Publication date: 2024-03-14

Abstract

A semiconductor device comprises a gate trench (22) formed in an active region (50); a gate insulating film (10) and a gate electrode layer (11) formed inside the gate trench (22); a gate wiring electrode (15) formed on an interlayer insulating film (13) that covers the gate electrode layer (11); and an external trench (6) formed in a drift layer (2) in an end region (60). A potential fixing layer (8) that covers an upper end corner section (6a) of the external trench (6), and an insulating layer (9) formed on the potential fixing layer (8), are formed inside the external trench (6). The gate insulating film (10) and the gate electrode layer (11) extend into the external trench (6), and the gate electrode layer (11) is connected to the gate wiring electrode (15) via a contact hole formed in the interlayer insulating film (13) inside the external trench (6).

Description

Semiconductor device and its manufacturing method

The present disclosure relates to a trench gate type semiconductor device and a method for manufacturing the same, and particularly relates to a structure of a gate electrode on the outer peripheral side of the semiconductor device.

Insulated gate bipolar transistors (IGBTs), insulated gate field effect transistors (MOSFETs), etc. with trench gate structures are used for power control applications in automotive equipment, industrial equipment, etc. Semiconductor devices are used.

A semiconductor device having a trench gate structure is provided with a "gate extension section" in which a trench in which a gate electrode is embedded (hereinafter referred to as "gate trench") extends from an active region through which a main current flows to a termination region outside the active region. . Although the drain voltage is low when the semiconductor device is on, a voltage is applied to the gate electrode, so the electric field generated in the gate insulating film increases, and the electric field tends to concentrate particularly at the upper corner of the gate trench.

Patent Document 1 below discloses that by forming a gate insulating film in contact with a thick field insulating film formed by LOCOS (Local Oxidation of Silicon) oxidation in a gate trench of a gate extension part, the upper corner of the gate trench is A technique for reducing electric field concentration has been disclosed.

Further, Patent Document 2 below discloses a technique in which a field plate electrode is provided together with a gate electrode in a gate trench of a gate extension portion, and the potential of the field plate electrode is set to the gate potential or the source potential.

Japanese Patent Application Publication No. 2001-102572 Japanese Patent Application Publication No. 2011-199109

Even if the field insulating film is used to improve the withstand voltage of the gate insulating film in the gate lead-out portion as in Patent Document 1, for example, if the upper end corner of the gate trench has an eave-like part that deviates from a right-angled shape, local Since a thin portion of the field insulating film is formed in the gate insulating film, the effect of improving the withstand voltage of the gate insulating film cannot be sufficiently obtained.

In the gate lead-out portion disclosed in Patent Document 2, when the potential of the field plate electrode is set to the gate potential, if the thickness of the gate insulating film is not sufficiently thick, there is a risk that the gate insulating film will be destroyed at the upper corner of the gate trench. There is. On the other hand, if the potential of the field plate electrode is set to the source potential, there is a risk that a leak current between the gate and the source may occur through the insulating film between the gate electrode and the field plate electrode. Further, depending on the shape of the field plate electrode, thin portions of the gate insulating film formed on the field plate electrode may be locally formed, leading to destruction of the gate insulating film.

The present disclosure has been made to solve the above-mentioned problems, and it is an object of the present disclosure to provide a semiconductor device that can prevent breakdown of the gate insulating film at the upper end corner of the gate trench of the gate extension portion.

A semiconductor device according to the present disclosure includes a drift layer of a first conductivity type, a well region of a second conductivity type formed in a surface layer portion of the drift layer, and a well region of a first conductivity type formed in a surface layer portion of the well region. a gate trench formed to penetrate the impurity region and the well region of the active region and reach the drift layer; a gate insulating film formed in contact with the inner surface of the gate trench; a gate electrode layer formed on a gate insulating film; an interlayer insulating film covering the gate electrode layer; a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer; an external trench formed in the drift layer in the outer termination region; a potential fixing layer formed in the external trench and covering the upper corner of the external trench; and an insulating layer formed on the potential fixing layer. and, the gate insulating film and the gate electrode layer extend into the external trench of the termination region, and the gate electrode layer is connected to a contact formed on the interlayer insulating film within the external trench. It is connected to the gate wiring electrode through the hole.

According to the present disclosure, since the upper end corner of the external trench is covered with the potential fixing layer and the insulating layer, the gate electrode and gate insulating film drawn out to the external trench are formed on the insulating layer, and the upper end corner of the external trench is covered with the potential fixing layer and the insulating layer. separated from the corner. Therefore, the gate insulating film is prevented from being destroyed due to electric field concentration caused by the shape of the upper corner of the external trench.

Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 1. FIG. 2 is a schematic diagram showing a schematic configuration of a boundary portion between an active region 50 and a termination region 60 in the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line A1-A2 in FIG. 2 in Embodiment 1. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 1. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 1. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line B1-B2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method of manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method for manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. 3 is a partial cross-sectional view showing a method of manufacturing a semiconductor device along line C1-C2 in FIG. 2 in Embodiment 2. FIG. FIG. 3 is a schematic plan view showing a schematic configuration of a semiconductor device according to a third embodiment. FIG. 3 is a schematic diagram showing a schematic configuration of a semiconductor device according to a third embodiment. 40 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 in FIG. 39 in Embodiment 3. FIG. FIG. 7 is a schematic diagram showing a schematic configuration of a semiconductor device according to a fourth embodiment. 42 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 in FIG. 41 in Embodiment 4. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 in FIG. 2 in Embodiment 5. FIG. 40 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 in FIG. 39 in Embodiment 5. FIG. 42 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line D1-D2 in FIG. 41 in Embodiment 5. FIG. 42 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line B1-B2 in FIG. 2, FIG. 39, or FIG. 41 in Embodiment 6. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line D1-D2 in FIG. 2 in Embodiment 6. FIG. 40 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line D1-D2 in FIG. 39 in Embodiment 6. FIG. 42 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device along line D1-D2 in FIG. 41 in Embodiment 6. FIG.

Hereinafter, embodiments of the technology according to the present disclosure will be described with reference to the drawings. The drawings are shown schematically, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily exactly described and may be changed as appropriate. Further, similar components are shown with the same reference numerals, and their names and functions are also the same. Therefore, detailed explanations thereof may be omitted.

In the description, terms such as "top," "bottom," "side," "bottom," "front," or "back" that mean specific positions and directions are sometimes used; It is used for convenience to facilitate understanding of the embodiment, and is not related to the position and direction in actual use.

Unless a contradiction occurs, a component described as being provided with "one" may be provided with "one or more". Further, a component is a conceptual unit, and one component may consist of a plurality of structures, and one component may correspond to a part of a certain structure.

In the following embodiments, the first conductivity type of the semiconductor will be described as n-type and the second conductivity type as p-type, but conversely, the first conductivity type is assumed to be p-type and the second conductivity type is assumed to be n-type. Good too. Further, although a MOSFET will be described as an example of a semiconductor device, the semiconductor device may be an IGBT. In addition, the material of the semiconductor substrate and the drift layer will be described as silicon carbide (SiC), which is a wide bandgap semiconductor with a larger bandgap than silicon, but they may also be silicon, for example, gallium nitride, diamond, etc. Other wide bandgap semiconductors or a combination thereof may be used.

Note that in the following description, "impurity concentration" indicates the peak value of impurity concentration in each region.

<Embodiment 1>
FIG. 1 is a schematic plan view showing a schematic configuration of a semiconductor device according to a first embodiment. FIG. 2 is a schematic diagram showing a schematic configuration of the boundary between the active region 50 and the termination region 60 in the semiconductor device according to the first embodiment, and shows the region 40 surrounded by the broken line in FIG. be. In FIG. 2, illustration of the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. is omitted to simplify the explanation. Furthermore, FIGS. 3 to 6 are schematic diagrams showing cross-sectional configurations of the semiconductor device according to the first embodiment, in which FIG. 3 is a cross-sectional view taken along line A1-A2 in FIG. 2, and FIG. 5 is a sectional view taken along line C1-C2 in FIG. 2, and FIG. 6 is a sectional view taken along line D1-D2 in FIG. 2.

The active region 50 is a region where a current flows due to the formation of a channel in the on state of the semiconductor device, and the termination region 60 is a region surrounding the active region 50. The termination region 60 is provided at the outer periphery of the semiconductor device chip so as to surround the active region 50, and within the termination region 60, there is a p-type termination electric field relaxation region 18 such as an FLR (Field Limiting Ring), An n-type channel stop region 31 is formed to suppress the spread of the depletion layer toward the end of the chip.

A gate trench 22 is provided in the drift layer 2 of the active region 50, and an external trench 6 corresponding to the gate trench of the gate extension portion is provided in the drift layer 2 of the termination region 60. As shown in FIG. 2, the gate trenches 22 are formed in a stripe shape when viewed from above. A cell is formed in each of a plurality of regions defined by gate trenches 22 in active region 50 . Although FIG. 2 shows an example in which a plurality of rectangular cells are arranged in a stripe pattern, the shape of the cells may be circular or polygonal such as a hexagonal shape, and the arrangement of the cells may be , a checkerboard pattern, a houndstooth pattern, etc. may be used.

As shown in FIGS. 3 to 6, a drift layer 2, a well region 3, an impurity region 4, a contact region 5, etc. are provided on the front side of a semiconductor substrate 1 constituting a semiconductor device. The active region 50 is provided with a gate trench 22, a trench bottom electric field relaxation region 16, a gate insulating film 10, and a gate electrode layer 11. The termination region 60 includes an external trench 6, a trench bottom electric field relaxation region 16, a trench bottom high concentration well region 17, a termination electric field relaxation region 18, an underlying insulating film 7, a potential fixing layer 8, an insulating layer 9, a gate insulating film 10, A gate electrode layer 11, a field insulating film 12, and a gate wiring electrode 15 are provided. Gate electrode layer 11 formed in external trench 6 of termination region 60 extends so as to surround gate trench 22 in plan view. On the surface of the semiconductor substrate 1, a surface ohmic electrode 19, an interlayer insulating film 13, and a surface electrode 14 are provided in common to the active region 50 and the termination region 60. On the back surface of the semiconductor substrate 1, a back ohmic electrode 20 and a back electrode 21 are provided in common to the active region 50 and the termination region 60.

Drift layer 2 is provided on semiconductor substrate 1 made of n-type silicon carbide, and is made of n-type silicon carbide. The n-type impurity of the drift layer 2 may be nitrogen or phosphorus, and the impurity concentration of the drift layer 2 may be approximately 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. The thickness of the drift layer 2 may be approximately 5 μm or more and 300 μm or less.

Well region 3 is a p-type region provided in the surface layer portion of drift layer 2, and is made of silicon carbide. The p-type impurity in the well region 3 may be aluminum, boron, or gallium, and the impurity concentration in the well region 3 may be approximately 1×10 ¹⁵ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. Here, the impurity concentration of the well region 3 may or may not be constant in the depth direction. The thickness of the well region 3 may be about 0.3 μm or more and 3 μm or less.

Impurity region 4 is an n-type region provided in the surface layer of well region 3, and is made of silicon carbide. The n-type impurity in the impurity region 4 may be nitrogen or phosphorus, and the impurity concentration in the impurity region 4 may be approximately 1×10 ¹⁷ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The thickness of impurity region 4 may be less than or equal to the thickness of well region 3.

Contact region 5 is provided in the surface layer of well region 3, is a p-type region having a higher impurity concentration than well region 3, and is made of silicon carbide. The p-type impurity in the contact region 5 may be aluminum, boron, or gallium, and the impurity concentration in the contact region 5 may be approximately 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. . The thickness of the contact region 5 may be equal to or less than the thickness of the well region 3.

A contact hole 25 (hereinafter referred to as "source contact hole 25") that reaches the impurity region 4 and the contact region 5 is formed in the interlayer insulating film 13, and at the bottom of the source contact hole 25, the impurity region 4 and the contact region A surface ohmic electrode 19 connected to 5 is formed. Impurity region 4 and contact region 5 are electrically connected to surface electrode 14 , which is a main electrode, through surface ohmic electrode 19 in source contact hole 25 .

Here, the contact region 5 is connected to the impurity region 4 by a surface ohmic electrode 19. When the contact region 5 is formed, a path is formed from the well region 3 to the surface ohmic electrode 19 via the contact region 5, and the electrical connection from the well region 3 to the surface ohmic electrode 19 is improved. Contact region 5 may be omitted.

The gate trench 22 extends from the surface of the impurity region 4 through the well region 3 and reaches the drift layer 2. As shown in FIG. 2, the gate trenches 22 are provided in the active region 50 in the form of stripes (that is, in the form of a plurality of parallel lines). When the gate trenches 22 are provided in a stripe shape, when the semiconductor device is a trench gate type silicon carbide MOSFET, a surface such as a (1-100) surface with high channel mobility can be used as a channel, and the semiconductor device can improve the characteristics of Furthermore, the gate trench 22 extends in the direction of the termination region 60 . Hereinafter, the direction in which the gate trench 22 extends will be referred to as the "extending direction" of the gate trench 22.

The width of the gate trench 22 may be, for example, approximately 0.5 μm or more and 10 μm or less. When the shape of the gate trench 22 is tapered in cross-sectional view, the width of the gate trench 22 refers to the width of the widest part of the tapered shape. The depth of the gate trench 22 may be, for example, approximately 0.5 μm or more and 6 μm or less.

Trench bottom electric field relaxation region 16 is a p-type region provided below the bottom surface of gate trench 22, and is made of silicon carbide. The trench bottom electric field relaxation region 16 has a conductivity type opposite to that of the drift layer 2, and is designed to relieve the electric field applied to the gate insulating film 10 formed at the bottom of the gate trench 22 in the operating state of the semiconductor device. The gate insulating film 10 is thereby prevented from being destroyed. The depth of the trench bottom electric field relaxation region 16 may be about 0.1 μm or more and 3.0 μm or less from the bottom of the gate trench 22 downward. The trench bottom electric field relaxation region 16 may be in contact with the bottom surface of the gate trench 22. The p-type impurity of the trench bottom electric field relaxation region 16 may be aluminum, boron, or gallium, and the impurity concentration of the trench bottom electric field relaxation region 16 is 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. It is sufficient to set it to a certain degree.

The external trench 6 is a wide trench formed in the termination region 60 to a depth comparable to that of the gate trench 22. Also below the external trench 6, a trench bottom electric field relaxation region 16 is provided.

The trench bottom high concentration well region 17 has a conductivity type opposite to that of the drift layer 2, and is provided in the trench bottom electric field relaxation region 16 below the external trench 6. Trench bottom high concentration well region 17 is a p-type region with higher concentration than trench bottom electric field relaxation region 16, and is made of silicon carbide. A contact hole 26 (hereinafter referred to as "outer well region contact hole 26") reaching the trench bottom high concentration well region 17 is formed in the interlayer insulating film 13. A surface ohmic electrode 19 connected to the trench bottom high concentration well region 17 is formed. The trench bottom electric field relaxation region 16 is electrically connected to the surface electrode 14 through the trench bottom high concentration well region 17 and the surface ohmic electrode 19 in the outer peripheral well region contact hole 26 .

The trench bottom high concentration well region 17 has the effect of lowering the contact resistance between the trench bottom electric field relaxation region 16 and the surface ohmic electrode 19, as well as the effect of lowering the sheet resistance of the surface of the trench bottom electric field relaxation region 16. The depth of the trench bottom high concentration well region 17 may be about 0.1 μm or more and 2.0 μm or less from the bottom of the external trench 6 downward. The trench bottom high concentration well region 17 may be in contact with the bottom of the external trench 6. The p-type impurity in the trench bottom high concentration well region 17 may be aluminum, boron, or gallium, and the impurity concentration in the trench bottom high concentration well region 17 is 1×10 ¹⁸ cm ⁻³ or more, 1×10 ²² cm ⁻ It may be about ³ or less.

The termination electric field relaxation region 18 is a p-type electric field relaxation region that is formed continuously or intermittently so as to surround the active region 50, and is, for example, an FLR (Field Limiting Ring). The terminal electric field relaxation region 18 is formed, for example, by ion-implanting aluminum, boron, gallium, etc. from the surface of the drift layer 2 to a depth of approximately 0.2 μm to 3 μm, which does not exceed the depth of the drift layer 2. The p-type impurity concentration of the termination electric field relaxation region 18 is set to exceed the impurity concentration of the drift layer 2, and may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less.

The field insulating film 12 is formed so as to be in contact with the surface of the drift layer 2 from inside the external trench 6 to the end of the chip. Field insulating film 12 can be made of an insulating material such as silicon dioxide. The thickness of the field insulating film 12 can be, for example, 0.1 μm or more and 5.0 μm or less.

The underlying insulating film 7 is formed to cover the inside of the external trench 6 and the upper end corner 6a of the external trench 6 (hereinafter referred to as "external trench upper end corner 6a"), and covers the well region 3, the drift layer 2, and the trench bottom electric field. It is in contact with the relaxation region 16 and the trench bottom high concentration well region 17 . A portion of the underlying insulating film 7 is also formed on the field insulating film 12. The underlying insulating film 7 is made of an insulating material such as silicon dioxide. The thickness of the underlying insulating film 7 is, for example, approximately 10 nm or more and 1000 nm or less.

The potential fixing layer 8 is a conductive layer such as polysilicon, and is formed on the underlying insulating film 7, and covers the inside of the external trench 6 and the upper end corner 6a of the external trench via the underlying insulating film 7. A portion of potential fixing layer 8 is also formed on field insulating film 12 . In this embodiment, potential fixing layer 8 is a first polysilicon layer made of polysilicon. A contact hole 27 (hereinafter referred to as "potential fixing layer connection contact hole 27") that reaches the potential fixing layer 8 on the field insulating film 12 is formed in the interlayer insulating film 13. It is connected to the surface electrode 14 through the contact hole 27 for layer connection. Since the potential of the surface electrode 14 becomes the source potential, the potential of the potential fixing layer 8 also becomes the source potential. Potential fixing layer 8 has a thickness exceeding gate insulating film 10 , preferably has a thickness exceeding three times that of gate insulating film 10 .

The insulating layer 9 is formed to cover the potential fixing layer 8. The insulating layer 9 suppresses gate leakage current from flowing between the potential fixing layer 8 and the gate electrode layer 11. The insulating layer 9 is made of an insulating material such as silicon dioxide. The thickness of the insulating layer 9 is, for example, about 10 nm or more and 1000 nm or less, and preferably has a thickness of the gate insulating film 10 or more.

The gate insulating film 10 is formed so as to be in contact with the inner surface of the gate trench 22, a part of the surface of the drift layer 2, the insulating layer 9, and the field insulating film 12, and is made of silicon dioxide. The thickness of the gate insulating film 10 can be, for example, approximately 10 nm or more and 200 nm or less.

The gate electrode layer 11 is formed on the gate insulating film 10 in the gate trench 22 and on the gate insulating film 10 formed on the insulating layer 9 in the external trench 6. In this way, the gate insulating film 10 and the gate electrode layer 11 extend from inside the gate trench 22 to inside the external trench 6. The height of the upper end of the gate electrode layer 11 in the gate trench 22 is preferably lower than the surface position of the drift layer 2 , and more preferably lower than the surface position of the drift layer 2 . In this embodiment, gate electrode layer 11 is a second polysilicon layer made of polysilicon. The gate electrode layer 11 formed in the termination region 60 has a thickness exceeding the gate insulating film 10, for example. A contact hole 28 (hereinafter referred to as "gate contact hole 28") that reaches the gate electrode layer 11 is formed in the interlayer insulating film 13, and the gate electrode layer 11 connects to the gate electrode pad 29 through the gate contact hole 28. It is connected to the gate wiring electrode 15 connected to.

The surface electrode 14, gate wiring electrode 15, and gate electrode pad 29 are formed on the interlayer insulating film 13, and are made of a metal material such as aluminum. The surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29 are arranged apart from each other.

The back ohmic electrode 20 is formed on the back surface of the semiconductor substrate 1 and is made of a reaction product of the semiconductor substrate 1 and a metal film containing nickel as a main component, such as nickel silicide. The back electrode 21 is formed in contact with the back ohmic electrode 20 and is made of titanium, nickel, silver, gold, aluminum, or the like.

The semiconductor device according to Embodiment 1 is composed of the above components.

Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 7 to 21. 7 to 21 are explanatory diagrams of each manufacturing stage of a semiconductor device, of which FIGS. 7 to 12 correspond to the cross section taken along the line B1-B2 in FIG. 2, and FIGS. This corresponds to the cross section along the D1-D2 line of No. 2.

First, an n-type silicon carbide semiconductor substrate 1 having a 4H polytype is prepared, and an n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD). At this time, the impurity concentration of the n-type drift layer 2 is in the range of 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ , and the thickness of the drift layer 2 is 5 μm to 300 μm.

Next, a p-type well region 3 is formed in the surface layer of the drift layer 2 by ion-implanting aluminum, boron, or gallium using a resist mask formed on the drift layer 2 by photolithography. Well region 3 may be formed by epitaxial growth.

Next, using a resist mask formed on the well region 3 by photolithography, nitrogen or phosphorus ions are implanted to form an n-type impurity region 4 in the surface layer of the well region 3.

Next, a silicon dioxide film with a thickness of about 1 μm to 2 μm is formed on the well region 3 and impurity region 4, and the formation regions of the gate trench 22 and external trench 6 are etched by reactive ion etching (RIE). An open etching mask is formed. Then, when the gate trench 22 and the external trench 6 are formed by RIE, the states shown in FIGS. 7 and 13 are obtained.

Next, with the etching mask left in place, a resist mask covering a part of the external trench 6 is formed by photolithography, and then aluminum, boron, or gallium is ion-implanted from the surface side of the drift layer 2 to form a gate. A trench bottom electric field relaxation region 16 is formed below the trench 22 and the external trench 6.

Subsequently, after removing the etching mask and resist mask and forming a resist mask by photolithography, ions of aluminum, boron, or gallium are implanted from the surface side of the drift layer 2 to form a termination in the termination region 60. An electric field relaxation region 18 is formed.

Subsequently, after forming a resist mask by photolithography, aluminum, boron, or gallium is ion-implanted to form a p-type contact region 5 in the surface layer of the well region 3 and to form a trench bottom electric field relaxation region 16. A trench bottom high concentration well region 17 is formed in the surface layer of the trench. The heating temperature of the semiconductor substrate 1 during this ion implantation is preferably 150° C. or higher. When the heating temperature is 150° C. or higher, the electrical resistance of the contact region 5 can be lowered, and resistance loss during the operating state of the semiconductor device can be reduced.

Next, after removing the etching mask, an annealing process is performed to activate the ion-implanted impurities. The annealing treatment is performed in an inert gas atmosphere such as argon or in vacuum at a temperature of approximately 1500° C. or higher and 1900° C. or lower for approximately 30 seconds or more and 1 hour or less. Here, in order to prevent silicon carbide from deteriorating due to high-temperature heating, that is, from surface roughening, a carbon film may be formed on semiconductor substrate 1 before the annealing treatment. In this way, the states shown in FIGS. 8 and 14 are achieved.

Next, an insulating film such as silicon dioxide, which will become the field insulating film 12, is formed by CVD or the like, and a resist mask is formed on this insulating film by photolithography. Then, this insulating film is opened by etching to form a field insulating film 12, and the resist mask is removed. In this way, the state shown in FIG. 15 is reached.

Next, the inside and upper end corners of the external trench 6 are covered by a thermal oxidation method or a CVD method, and an underlay is applied so as to be in contact with the well region 3, the drift layer 2, the trench bottom electric field relaxation region 16, and the trench bottom high concentration well region 17. An insulating film 7 is formed. A portion of the underlying insulating film 7 is also formed on the field insulating film 12.

Subsequently, a conductive material such as polysilicon that will become the potential fixing layer 8 is formed on the underlying insulating film 7 by CVD or the like, and a resist mask is formed on the polysilicon by photolithography. Then, the potential fixing layer 8 is formed in the termination region 60 by etching the polysilicon. A portion of potential fixing layer 8 is also formed on field insulating film 12 . At this time, all of the polysilicon in the active region 50 is removed by etching until the underlying insulating film 7 is exposed by an etch-back process. After that, the resist mask is removed. In this way, the state shown in FIG. 16 is achieved.

Next, a layer of silicon dioxide or the like, which will become the insulating layer 9, is formed to cover the potential fixing layer 8 by a CVD method or the like. When potential fixing layer 8 is made of polysilicon, this layer of silicon dioxide or the like may be formed by thermally oxidizing the surface of potential fixing layer 8. Next, a resist mask is formed by photolithography, and the insulating layer 9 is formed by etching. The underlying insulating film 7 and insulating layer 9 in the gate trench 22 in the active region 50 are completely removed by etching to expose the drift layer 2. In this way, the state shown in FIG. 17 is achieved.

Next, a gate insulating film 10 is formed on the surface of the drift layer 2, the inner surface of the gate trench 22, and the insulating layer 9 and field insulating film 12 in the termination region 60 by a thermal oxidation method, a CVD method, or the like. In this way, the states shown in FIGS. 9 and 18 are achieved.

Then, a conductive material such as polysilicon that will become the gate electrode layer 11 is formed by CVD or the like, and a resist mask is formed on the polysilicon by photolithography. Subsequently, the gate electrode layer 11 is formed by etching the polysilicon, and the resist mask is removed. At this time, the polysilicon in the active region 50 is etched by an etch-back process so that the upper end of the gate electrode layer 11 is below the surface position of the drift layer 2 in the gate trench 22. In this way, the states shown in FIGS. 10 and 19 are achieved.

Next, an interlayer insulating film 13 is formed by low pressure CVD or the like, and a resist mask is formed on the interlayer insulating film 13 by photolithography. Subsequently, by etching the interlayer insulating film 13, a source contact hole 25 reaching the impurity region 4 and the contact region 5, and an outer peripheral well region contact hole 26 reaching the trench bottom high concentration well region 17 are formed.

Then, a metal containing Ni or the like as a main component is applied over the impurity region 4 and contact region 5 exposed to the source contact hole 25 and over the trench bottom high concentration well region 17 exposed to the outer peripheral well region contact hole 26. A film is formed and annealing is performed to form a surface ohmic electrode 19. Then, the metal film on the interlayer insulating film 13 is removed by etching, and the resist mask is removed.

Furthermore, a metal film containing Ni or the like as a main component is formed on the back surface of the semiconductor substrate 1, and annealing treatment is performed to form the back ohmic electrode 20. Here, the heating temperature of each annealing treatment may be approximately 600° C. or higher and 1100° C. or lower.

Next, a resist mask is formed on the interlayer insulating film 13 by photolithography, and the interlayer insulating film 13 is etched to form a potential fixing layer connection contact hole 27 that reaches the potential fixing layer 8 and a gate electrode layer 11. A gate contact hole 28 is formed to reach the surface, and the resist mask is removed. In this way, the states shown in FIGS. 11 and 20 are achieved.

Then, a metal film such as aluminum is formed on the interlayer insulating film 13 and the surface ohmic electrode 19 and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28 by sputtering or vapor deposition. A resist mask is formed thereon by photolithography. Subsequently, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29, and then the resist mask is removed. In this way, the states shown in FIGS. 12 and 21 are achieved.

Finally, the structure of the semiconductor device shown in FIGS. 4 and 6 is completed by forming the back electrode 21 on the back ohmic electrode 20 by sputtering, vapor deposition, or the like.

As shown in FIG. 1, the termination region 60 may be provided with a channel stop region 31 that suppresses the expansion of the depletion layer toward the end of the semiconductor device. Channel stop region 31 is an n-type region provided on the outer peripheral side of external trench 6, and is made of silicon carbide. The n-type impurity of the channel stop region 31 may be nitrogen or phosphorus, and the impurity concentration of the channel stop region 31 may be approximately 1×10 ¹⁷ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The thickness of channel stop region 31 may be the same as the thickness of impurity region 4, or may be different. The channel stop region 31 may be formed by ion implantation, and may be formed simultaneously with the impurity region 4 using a resist mask for providing the impurity region 4, or may be formed before or after the formation of the impurity region 4. You may. When forming channel stop region 31 and impurity region 4 at the same time, channel stop region 31 and impurity region 4 may be formed, for example, after gate trench 22 and external trench 6 are formed.

Furthermore, the order of the step of forming the well region 3 and the step of forming the impurity region 4 may be reversed. The well region 3 and the impurity region 4 are formed by ion-implanting n-type impurities into the surface layer of the well region 3 to form the impurity region 4, and then forming a resist mask by photolithography on it to form the impurity region 4. The well region 3 may be formed by ion-implanting p-type impurities to a position other than the region 4.

In addition, in the manufacturing method described above, the thickness of the etching mask and the RIE process are adjusted so that the etching mask remains after forming the gate trench 22 and the external trench 6, and the remaining etching mask and the photolithography process are used to form the etching mask. A trench bottom electric field relaxation region 16 was formed by ion implantation using a resist mask. However, the trench bottom electric field relaxation region 16 may be formed by ion implantation using only a resist mask formed by photolithography and removing the etching mask without leaving it.

Further, the trench bottom electric field relaxation region 16 below the external trench 6 may be formed at the same time as the trench bottom electric field relaxation region 16 under the gate trench 22, or before the formation of the trench bottom electric field relaxation region 16 under the gate trench 22. Alternatively, it may be formed later. Furthermore, p-type impurity ions are implanted obliquely into the gate trench 22 to form a p-type semiconductor layer in the drift layer 2 in contact with the side surfaces of the gate trench 22, forming the trench bottom electric field relaxation region 16 and the well region. 3 may be electrically connected to each other through the semiconductor layer. When the trench bottom electric field relaxation region 16 and the well region 3 are electrically connected, the trench bottom electric field relaxation region 16 is connected to the surface electrode 14 via the well region 3, compared to the state where the trench bottom electric field relaxation region 16 is floating. Since it is grounded and grounded, the frequency characteristics of the semiconductor device are improved.

Further, in this embodiment, an example is shown in which the semiconductor device is a MOSFET, but when the semiconductor device is an IGBT, the conductivity type of the semiconductor substrate 1 may be p-type, and the semiconductor substrate 1 may be polished to have a thickness of You can make it thinner.

Next, the operation of the semiconductor device of this embodiment will be explained.

When a gate voltage equal to or higher than the threshold is applied between the gate electrode pad 29 and the surface electrode 14, a channel is formed in the well region 3 facing the gate electrode layer 11, and electrons are transferred from the impurity region 4 to the drift layer 2. flows. When a voltage is applied between the front electrode 14 and the back electrode 21 to generate an electric field, electrons reach the back electrode 21 via the drift layer 2 and the semiconductor substrate 1, that is, from the back electrode 21 to the front electrode 14. A current is generated toward the semiconductor device, and the semiconductor device is turned on.

Here, when the gate insulating film 10 is formed in contact with the surfaces and inside of the gate trench 22 and the external trench 6, the upper end corner 22a of the external trench 6 (hereinafter referred to as "gate trench upper end corner 22a") and An electric field is generated in the gate insulating film 10 near the upper end corner 6a of the external trench. However, in the active region 50, the gate electrode layer 11 is formed at a position lower than the gate trench top corner 22a, so that electric field concentration due to the shape of the gate trench top corner 22a is suppressed, and the gate insulating film 11 is destruction is prevented.

On the other hand, in the termination region 60, the gate insulating film 10 is formed on the insulating layer 9 and is spaced apart from the top corner 6a of the external trench, so that electric field concentration due to the shape of the top corner 6a of the external trench occurs. This prevents the gate insulating film 10 from being destroyed. The upper end corner 6a of the external trench is covered with an underlying insulating film 7, and the well region 3 and the potential fixing layer 8 are at the source potential, and the potential fixing layer 8 is connected to the gate electrode by the insulating layer 9 and the gate insulating film 10. Since it is insulated from the layer 11, the underlying insulating film 7 at the upper end corner 6a of the external trench is not destroyed by the gate voltage.

Here, if the thickness of the potential fixing layer 8 is sufficiently thick, the potential fixing layer 8 covers the upper end corner and the inside of the external trench 6 via the underlying insulating film 7. The curvature of the upper part can be increased. By increasing the curvature of the upper part of the potential fixing layer 8, it is possible to prevent the thickness of the insulating layer 9 and the gate insulating film 10 formed on the potential fixing layer 8 from becoming locally thinner, and the insulating layer 9 due to electric field concentration can be prevented. And the effect of preventing destruction of the gate insulating film 10 is further enhanced.

In addition, when the thickness of the insulating layer 9 is thin, the insulation between the potential fixing layer 8 and the gate electrode layer 11 becomes insufficient, and as in the case where the potential of the field plate electrode is set as the source potential in Patent Document 2, there is a difference between the gate and the source. Leakage increases, and the potential fixing layer 8 and gate electrode layer 11 may be destroyed by the electric field, resulting in a short circuit. In order to avoid this, it is preferable that the thickness of the insulating layer 9 be greater than the thickness of the gate insulating film 10, for example. By doing so, it is possible to insulate between the potential fixing layer 8 and the gate electrode layer 11 with a thickness at least twice that of the gate insulating film 10, and the insulation between the gate and the source in the termination region 60 can be made better than that in the active region 50. The leakage current between the gate and source in the termination region 60 is suppressed, and the effect of preventing breakdown of the insulating layer 9 and the gate insulating film 10 is further enhanced.

On the other hand, when a voltage below the threshold is applied between the gate electrode pad 29 and the front surface electrode 14 , no channel is formed in the well region 3 facing the gate electrode layer 11 , and the channel is no longer formed in the well region 3 facing the gate electrode layer 11 . No current is generated in that direction, and the semiconductor device is in an off state. In the OFF state of the semiconductor device, a voltage higher than that in the ON state is applied between the front electrode 14 and the back electrode 21, and a depletion layer spreads from the well region 3 to the drift layer 2.

At this time, the depletion layer also spreads from the trench bottom electric field relaxation region 16 to the drift layer 2. This suppresses breakdown of the gate insulating film 10 at the bottoms or bottom corners of the gate trenches 22 and external trenches 6 due to the electric field generated by the high voltage applied between the front electrode 14 and the back electrode 21 .

When the semiconductor device shifts from the off state to the on state, the voltage applied between the front electrode 14 and the back electrode 21 decreases, and the depletion layer that had spread to the drift layer 2 contracts. The semiconductor device operates so as to alternately repeat the above-described on state and off state.

According to the semiconductor device according to the first embodiment, it is possible to prevent the gate insulating film 10 from being destroyed at the gate trench top corner 22a and the external trench top corner 6a.

<Embodiment 2>
22 and 23 are diagrams showing the configuration of a semiconductor device according to the second embodiment, in which FIG. 22 is a cross-sectional view taken along line B1-B2 in FIG. 2, and FIG. 23 is a cross-sectional view taken along line C1-C2 in FIG. Each corresponds to a cross-sectional view along the line. In this embodiment, the cross-sectional configuration along lines A1-A2 and D1-D2 in FIG. 2 is the same as that in the first embodiment.

In the second embodiment, an underlying insulating film 7 and a potential fixing layer 8 are provided below the gate insulating film 10 and the gate electrode layer 11 in the gate trench 22 of the active region 50. In the gate trench 22, the underlying insulating film 7 is formed in contact with the inner surface of the gate trench 22, and the potential fixing layer 8 is formed on the underlying insulating film 7. The gate insulating film 10 is formed in contact with the inner surface of the gate trench 22 and the upper surface of the potential fixing layer 8 , and the gate electrode layer 11 is formed on the gate insulating film 10 .

In this embodiment, it is assumed that the potential of the potential fixing layer 8 formed in the gate trench is a floating potential. Further, the underlying insulating film 7 is formed thicker than the gate insulating film 10 in order to alleviate the influence of the electric field generated on the bottom surface of the gate trench 22 due to the drain voltage.

In FIG. 22, the trench bottom electric field relaxation region 16 is formed below the gate trench 22, but the trench bottom electric field relaxation region 16 may be omitted. When the trench bottom electric field relaxation region 16 is not formed, the electric field generated at the bottom of the gate trench 22 by the drain voltage when the semiconductor device is off is caused by the depletion layer formed between the well region 3 and the drift layer 2 and the underlying insulation. It is shared between the membrane 7 and the potential fixing layer 8. When the concentration of phosphorus in the polysilicon of the potential fixing layer 8 is lowered, depletion of the polysilicon increases and the electric field relaxation effect can be enhanced.

In addition, when the trench bottom electric field relaxation region 16 is not formed, the semiconductor device caused by the depletion layer extending from the well region 3 to the drift layer 2 and the depletion layer extending from the trench bottom electric field relaxation region 16 to the drift layer 2 is Since the current confinement is eliminated, it is also possible to improve the on-state characteristics.

Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 24 to 37. 24 to 37 are explanatory diagrams of each manufacturing stage of a semiconductor device, of which FIGS. 24 to 30 correspond to the cross section taken along the line B1-B2 in FIG. This corresponds to a cross section taken along the C1-C2 line.

First, as in the first embodiment, an n-type silicon carbide semiconductor substrate 1 having a 4H polytype is prepared, and an n-type drift layer 2 is deposited thereon by chemical vapor deposition (CVD). is epitaxially grown to form a well region 3, an impurity region 4, a gate trench 22, and a trench bottom electric field relaxation region 16. In this way, the states shown in FIGS. 24 and 31 are achieved.

Next, an insulating film such as silicon dioxide, which will become the field insulating film 12, is formed by CVD or the like, and a resist mask is formed on this insulating film by photolithography. Then, this insulating film is opened by etching to form a field insulating film 12, and the resist mask is removed.

Then, the underlying insulating film 7 is formed by a thermal oxidation method, a CVD method, or the like. In this way, the states shown in FIGS. 25 and 32 are achieved.

Subsequently, a conductive material such as polysilicon that will become the potential fixing layer 8 is formed on the underlying insulating film 7 by CVD or the like, and is etched by an etch-back process so that a desired thickness remains in the gate trench 22. Thereafter, a resist mask is formed by photolithography, and the potential fixing layer 8 in the active region 50 and the potential fixing layer 8 in the termination region 60 are etched so that the potential fixing layer 8 in the active region 50 has a floating potential. Separate and remove the resist mask. In this way, the states shown in FIGS. 26 and 33 are achieved.

Next, an insulating layer 9 made of silicon dioxide or the like is formed to cover the potential fixing layer 8 by a CVD method or the like. When the potential fixing layer 8 is made of polysilicon, the insulating layer 9 may be formed by thermally oxidizing the potential fixing layer 8. In this way, the states shown in FIGS. 27 and 34 are achieved.

Next, a resist mask is formed by photolithography, and etching is performed until the upper side and the upper end of the sidewall of the potential fixing layer 8 in the gate trench 22 are exposed. Thereafter, a gate insulating film 10 is formed on the surface of the drift layer 2, inside the gate trench 22, and on the insulating layer 9 by a thermal oxidation method, a CVD method, or the like. In this way, the states shown in FIGS. 28 and 35 are achieved.

Then, a conductive material such as polysilicon that will become the gate electrode layer 11 is formed by CVD or the like, and a resist mask is formed on the polysilicon by photolithography. Subsequently, the gate electrode layer 11 is formed by etching the polysilicon, and the resist mask is removed. At this time, the polysilicon in the active region 50 is etched by an etch-back process so that the upper end of the gate electrode layer 11 is below the surface position of the drift layer 2 in the gate trench 22. In this way, the states shown in FIGS. 29 and 36 are achieved.

Furthermore, a metal film containing Ni or the like as a main component is formed on the back surface of the semiconductor substrate 1, and annealing treatment is performed to form the back ohmic electrode 20. Here, the heating temperature of each annealing treatment may be approximately 600° C. or higher and 1100° C. or lower. In this way, the states shown in FIGS. 30 and 37 are achieved.

Then, a metal film such as aluminum is formed on the interlayer insulating film 13 and the surface ohmic electrode 19 and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28 by sputtering or vapor deposition. A resist mask is formed thereon by photolithography. Subsequently, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29, and then the resist mask is removed.

Finally, the structure of the semiconductor device shown in FIGS. 22 and 23 is completed by forming the back electrode 21 on the back ohmic electrode 20 by sputtering, vapor deposition, or the like.

In the second embodiment, an example was described in which the potential fixing layer 8 of the active region 50 and the potential fixing layer 8 of the termination region 60 are separated by etching so that the potential fixing layer 8 in the active region 50 has a floating potential. However, as described in Embodiment 4, in the case of a configuration in which the potential fixing layer 8 of the termination region 60 is set to a floating potential without being connected to an external electrode, the potential fixation layer 8 of the active region 50 and the potential fixing layer 8 of the termination region 60 are fixed. The layers 8 may be connected to each other.

The semiconductor device according to the second embodiment also provides the same effects as the first embodiment. Further, the thickness of the underlying insulating film 7 formed on the bottom surface of the gate trench 22 is thicker than the gate insulating film 10, so that the gate electrode layer 11 is not located on the bottom surface of the gate trench 22. Therefore, compared to the case where only the gate insulating film 10 is formed on the bottom surface of the gate trench 22, the insulating film (such as silicon dioxide) on the bottom surface of the gate trench 22 is The effect of the generated electric field is alleviated.

<Embodiment 3>
38 to 40 are diagrams showing the configuration of a semiconductor device according to the third embodiment. FIG. 38 is a schematic plan view showing the general structure of the semiconductor device according to the third embodiment, and FIG. 39 shows the structure of the region 41 surrounded by the broken line in FIG. 38. FIG. 40 is a cross-sectional view taken along line D1-D2 in FIG. 39. In FIG. 39, illustrations of the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted to simplify the explanation.

The semiconductor device according to the third embodiment includes a ground electrode pad 30 to which a ground potential of 0V is supplied and a ground wiring electrode 23 connected thereto. In the first and second embodiments, the potential fixing layer 8 is connected to the surface electrode 14, and the potential of the potential fixing layer 8 is used as the source potential. In the third embodiment, the potential fixing layer 8 is connected to the ground wiring electrode 23, and the potential of the potential fixing layer 8 is set to the ground potential. The configuration other than this is the same as that of the first embodiment.

Even when the potential fixing layer 8 is set to the ground potential, in the termination region 60, the gate insulating film 10 is formed separated from the top corner 6a of the external trench, so that the electric field due to the shape of the top corner 6a of the external trench is Concentration is suppressed and destruction of the gate insulating film 10 is prevented. The upper end corner 6a of the external trench is covered with an underlying insulating film 7, the well region 3 is at a source potential, the potential fixing layer 8 is at a ground potential, and the potential fixing layer 8 is connected to an insulating layer 9 and a gate insulating film 10. Since the underlying insulating film 7 at the upper corner portion 6a of the external trench is insulated from the gate electrode layer 11 by the gate voltage, the underlying insulating film 7 is not destroyed by the gate voltage.

<Embodiment 4>
41 and 42 are diagrams showing the configuration of a semiconductor device according to the fourth embodiment. FIG. 41 is a schematic diagram showing a schematic configuration of a semiconductor device according to Embodiment 4, and shows the configuration of a region 40 surrounded by a broken line in FIG. 1. In FIG. FIG. 42 is a cross-sectional view taken along line D1-D2 in FIG. 41. In FIG. 41, illustration of the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. is omitted to simplify the explanation.

In the fourth embodiment, the potential fixing layer connection contact hole 27 is not formed in the interlayer insulating film 13, and the potential fixing layer 8 is not connected to any other electrode. In other words, the potential of the potential fixing layer 8 is set to a floating potential. The configuration other than this is the same as in the first to third embodiments.

Even when the potential fixing layer 8 is set to a floating potential, the gate insulating film 10 is formed in the termination region 60 so as to be separated from the top corner 6a of the external trench, so that the electric field caused by the shape of the top corner 6a of the external trench is Concentration is suppressed and destruction of the gate insulating film 10 is prevented. The upper end corner 6a of the external trench is covered with an underlying insulating film 7, but the well region 3 is at a source potential, the potential fixing layer 8 is at a floating potential, and the potential fixing layer 8 is connected to the insulating layer 9 and the gate insulating film 10. Since the underlying insulating film 7 at the upper corner portion 6a of the external trench is insulated from the gate electrode layer 11 by the gate voltage, the underlying insulating film 7 is not destroyed by the gate voltage.

<Embodiment 5>
43 to 45 are diagrams showing the configuration of a semiconductor device according to the fifth embodiment. 43 is a sectional view taken along line D1-D2 in FIG. 2, FIG. 44 is a sectional view taken along line D1-D2 in FIG. 39, and FIG. 45 is a sectional view taken along line D1-D2 in FIG.

In the first to fourth embodiments, examples were shown in which the well region 3 and the trench bottom electric field relaxation region 16 were separated from each other in the termination region 60. In the fifth embodiment, the well region 3 and the trench bottom electric field relaxation region 16 are connected to each other by a p-type external trench side surface connection layer 24 formed on the side surface of the external trench 6. The configuration other than this is the same as in the first to fourth embodiments. 43 shows the configuration of FIG. 6 with an external trench side connection layer 24 provided, FIG. 44 shows the configuration of FIG. 40 with an external trench side connection layer 24 provided, and FIG. 45 shows the configuration of FIG. 42. This corresponds to a structure in which an external trench side surface connection layer 24 is provided.

The external trench side surface connection layer 24 is formed, for example, by ion implantation after the formation of the trench bottom electric field relaxation region 16, and the p-type impurity may be aluminum, boron, or gallium, and the impurity concentration is 1×10 ¹⁷ cm ⁻³ or more. , about 1×10 ²² cm ⁻³ or less.

By connecting the well region 3 and the trench bottom electric field relaxation region 16 on the side surface of the external trench 6, the number of paths through which the displacement current generated at turn-off flows to the surface electrode 14 increases. Therefore, an increase in the potential of the underlying insulating film 7 at the upper corner portion 6a of the external trench due to the displacement current is suppressed, and breakdown of the underlying insulating film 7 is prevented.

<Embodiment 6>
46 to 49 are diagrams showing the configuration of a semiconductor device according to the fifth embodiment. 46 is a cross-sectional view taken along line B1-B2 in FIG. 2, FIG. 39 or FIG. 41, FIG. 47 is a cross-sectional view taken along line D1-D2 in FIG. FIG. 49 is a cross-sectional view taken along line D1-D2 in FIG. 41.

In the sixth embodiment, the underlying insulating film 7 is not formed, and the potential fixing layer 8 is in contact with the inner surface of the external trench 6 and the upper end corner 6a of the external trench. The configuration other than this is the same as in the first to fifth embodiments. 47 shows the structure of FIG. 43 with the underlying insulating film 7 omitted, FIG. 48 shows the structure of FIG. 44 with the underlying insulating film 7 omitted, and FIG. 49 shows the structure of FIG. 45 with the underlying insulating film 7 removed. This corresponds to omitting 7.

Even when the underlying insulating film 7 is omitted, the gate insulating film 10 is formed in the termination region 60 so as to be separated from the top corner 6a of the external trench, so that electric field concentration due to the shape of the top corner 6a of the external trench is prevented. This suppresses the damage and prevents the gate insulating film 10 from being destroyed.

Similar to Embodiments 1 to 5, the potential of the potential fixing layer 8 is set to one of the source potential, ground potential, and floating potential. Even if the potential of the potential fixing layer 8 is the source potential or the ground potential, the drift layer 2 can be Due to the influence of the PN junction, it is difficult for current to flow from the back electrode 21 to the potential fixing layer 8, and the influence on loss is small.

Note that it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

The above description is understood to be illustrative in all aspects, and countless variations not exemplified can be envisioned.

1 Semiconductor substrate, 2 Drift layer, 3 Well region, 4 Impurity region, 5 Contact region, 6 External trench, 6a Upper corner of external trench, 7 Underlying insulating film, 8 Potential fixing layer, 9 Insulating layer, 10 Gate insulating film, 11 Gate electrode layer, 12 Field insulating film, 13 Interlayer insulating film, 14 Surface electrode, 15 Gate wiring electrode, 16 Trench bottom electric field relaxation region, 17 Trench bottom high concentration well region, 18 Termination electric field relaxation region, 19 Surface ohmic electrode, 20 Back ohmic electrode, 21 Back electrode, 22 Gate trench, 22a Gate trench top corner, 23 Ground wiring electrode, 24 External trench side surface connection layer, 25 Source contact hole, 26 Outer periphery well region contact hole, 27 Potential fixing layer connection 28 Gate contact hole, 29 Gate electrode pad, 30 Ground electrode pad, 31 Channel stop region, 50 Active region, 60 Termination region.

Claims

a first conductivity type drift layer;
a well region of a second conductivity type formed in a surface layer portion of the drift layer;
a first conductivity type impurity region formed in a surface layer portion of the well region;
a gate trench formed to penetrate the impurity region and the well region of the active region and reach the drift layer;
a gate insulating film formed in contact with the inner surface of the gate trench;
a gate electrode layer formed on the gate insulating film;
an interlayer insulating film covering the gate electrode layer;
a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer;
an external trench formed in the drift layer in a termination region outside the active region;
a potential fixing layer formed in the external trench and covering an upper corner of the external trench;
an insulating layer formed on the potential fixing layer;
Equipped with
The gate insulating film and the gate electrode layer extend into the external trench of the termination region, and the gate electrode layer connects to the gate wiring through a contact hole formed in the interlayer insulating film within the external trench. connect with the electrode,
Semiconductor equipment.
2. The semiconductor device according to claim 1, wherein the potential fixing layer has a thickness exceeding the thickness of the gate insulating film.
further comprising an underlying insulating film formed under the potential fixing layer;
The semiconductor device according to claim 1 or 2.
The thickness of the underlying insulating film is greater than or equal to the thickness of the gate insulating film,
The semiconductor device according to claim 3.
A part of the potential fixing layer is formed at the bottom of the gate trench, and the gate insulating film and the gate electrode layer in the gate trench are formed on the gate trench,
The potential fixing layer at the bottom of the gate trench is configured to have a floating potential.
The semiconductor device according to any one of claims 1 to 4.
a trench bottom electric field relaxation region of a second conductivity type formed below the external trench;
an external trench side surface connection layer of a second conductivity type formed on a side surface of the external trench and connecting the well region and the trench bottom electric field relaxation region;
further comprising,
The semiconductor device according to any one of claims 1 to 5.
further comprising a surface electrode formed on the interlayer insulating film and connected to the well region,
The potential fixing layer is connected to the surface electrode through a contact hole formed in the interlayer insulating film.
The semiconductor device according to any one of claims 1 to 6.
further comprising a ground wiring electrode formed on the interlayer insulating film,
The potential fixing layer is connected to the ground wiring electrode through a contact hole formed in the interlayer insulating film.
The semiconductor device according to any one of claims 1 to 6.
The potential fixing layer is configured to have a floating potential,
The semiconductor device according to any one of claims 1 to 6.
The gate electrode layer of the termination region surrounds the gate trench in plan view;
The semiconductor device according to any one of claims 1 to 9.
The thickness of the potential fixing layer is three times or more the thickness of the gate insulating film,
The semiconductor device according to any one of claims 1 to 10.
The thickness of the insulating layer is greater than or equal to the thickness of the gate insulating film,
The semiconductor device according to any one of claims 1 to 11.
The position of the upper end of the gate electrode layer of the gate trench is lower than the upper end of the gate trench.
The semiconductor device according to any one of claims 1 to 12.
forming a first conductivity type drift layer;
forming a second conductivity type well region in a surface layer portion of the drift layer;
forming an impurity region of a first conductivity type in a surface layer portion of the well region;
forming a gate trench that penetrates the impurity region and the well region of the active region and reaches the drift layer;
forming an external trench in the drift layer in a termination region outside the active region;
forming a potential fixing layer in the external trench to cover an upper corner of the external trench;
forming an insulating layer on the potential fixing layer;
forming a gate insulating film within the gate trench and the external trench;
forming a gate electrode layer on the gate insulating film in the gate trench and in the external trench;
forming an interlayer insulating film covering the gate electrode layer;
forming a contact hole reaching the gate electrode layer in the interlayer insulating film in the external trench;
forming a gate wiring electrode connected to the gate electrode layer through the contact hole on the interlayer insulating film;
Equipped with
A method for manufacturing a semiconductor device.
The potential fixing layer is formed to have a thickness exceeding the thickness of the gate insulating film.
The method for manufacturing a semiconductor device according to claim 14.
Before forming the potential fixing layer, further comprising the step of forming an underlay insulating film provided under the potential fixing layer.
The method for manufacturing a semiconductor device according to claim 14 or 15.
In the step of forming the potential fixing layer, a part of the potential fixing layer is formed within the gate trench.
The method for manufacturing a semiconductor device according to any one of claims 14 to 16.