Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/08—Oxides
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/16—Oxides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/051—Manufacture or treatment of FETs having PN junction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/061—Manufacture or treatment of FETs having Schottky gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/83—FETs having PN junction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/50—PIN diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/81—Bodies
  • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/80—Constructional details
  • H10N30/85—Piezoelectric or electrostrictive active materials
  • H10N30/853—Ceramic compositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials

Definitions

• the present invention relates to a laminated structure, an element, an electronic device, an electronic device, and a system.
• An object of the present invention is to provide a laminated structure having excellent crystallinity, and elements, electronic devices, electronic equipment, and systems using the same.
• the present inventors have found that at least an oxide film is formed on a crystal substrate, and then a crystalline metal oxide containing as a main component a metal oxide containing oxides of Hf and Zr is formed.
• a crystalline metal oxide containing as a main component a metal oxide containing oxides of Hf and Zr is formed.
• the lamination process is performed by forming the crystal film using oxygen atoms in the oxide film.
• the structure is easily obtained, it is particularly useful for crystal growth for producing soft crystal films, and when a conductive film, a semiconductor film, and a piezoelectric film are formed on the crystal, it has excellent crystallinity and improves electrode properties.
• a laminated structure comprising a crystal film containing: [2] The laminated structure according to [1], wherein the crystal film contains an oxide of Hf.
• the laminated structure of the present invention has excellent crystallinity, and elements, electronic devices, electronic equipment, and systems using the laminated structure have good characteristics of their respective functional films. be effective.
• FIG. 1 is a diagram schematically showing an example of a preferred embodiment of a laminated structure of the present invention.
• FIG. 3 is a diagram schematically showing an SOI island forming step in peeling and transfer, which is an example of a preferred application of the laminated structure of the present invention.
• FIG. 3 is a diagram schematically showing an HF etching step in peeling/transfer, which is an example of a preferred application of the laminated structure of the present invention.
• FIG. 2 is a diagram schematically showing a step of attaching the laminated structure of the present invention to a flexible substrate in peeling and transfer, which is an example of a preferred application example.
• FIG. 2 is a diagram schematically showing a peeling process in peeling/transfer, which is an example of a preferable application of the laminated structure of the present invention.
• FIG. 2 is a diagram schematically showing an example of a compound film forming step of a preferred method for manufacturing a laminated structure of the present invention.
• FIG. 3 is a diagram schematically showing an example of an insulating film forming step of a preferred method for manufacturing a laminated structure of the present invention.
• a cross-sectional STEM image observed in an example is shown.
• the XPS analysis results in Examples are shown.
• 1 is a diagram schematically showing a preferred example of an insulated gate bipolar transistor (IGBT) obtained in the present invention.
• IGBT insulated gate bipolar transistor
• FIG. 11 is a diagram schematically showing an example of a suitable manufacturing process for the insulated gate bipolar transistor (IGBT) of FIG. 10.
• FIG. 1 is a diagram schematically showing a preferred example of a power supply system.
• FIG. 2 is a diagram schematically showing a preferred example of a system device. It is a figure which shows typically a suitable example of the power supply circuit diagram of a power supply device.
• 1 is a diagram schematically showing a film forming apparatus suitably used in Examples.
• the laminated structure of the present invention is a laminated structure in which an epitaxial film made of a conductive metal oxide is formed on a buffer layer directly or via another layer, and the buffer layer contains Hf and/or It is characterized by including a crystal film containing an oxide of Zr.
• the crystal of the crystal film may be single crystal or polycrystal.
• the conductive metal oxide is usually conductive and is a crystalline metal oxide, but the crystalline metal oxide is not particularly limited as long as it contains a metal oxide as a main component. Further, the oxide is not particularly limited as long as it contains oxides of Hf and Zr, but preferably contains oxides of Hf and Zr as main components. Note that the term "main component" may be, for example, as long as the oxides of Hf and Zr are contained in an atomic ratio of oxides in the crystal of 0.5 or more. In the present invention, the atomic ratio of Hf and Zr to all metal elements in the oxide is preferably 0.7 or more, more preferably 0.8 or more.
• the oxide or the crystalline metal oxide has a cubic or hexagonal crystal structure, and has a (111), (100), (010) or (0001) orientation. is more preferable. Further, in the present invention, it is also preferable that the oxide contains 50 atomic % or more of an oxide of Hf and an oxide of Zr based on the crystalline metal oxide. According to such a preferable range, it can not only be used as an excellent buffer layer, but also exhibit good characteristics as a ferroelectric material, and further improve electrical properties (especially the relationship between the conductive layer and the insulating layer). This is preferable because it can improve the quality of the interface (interface).
• the crystal is in the form of a film (hereinafter also referred to as "crystal film"), and when it is in the form of a film, it is preferable that the film thickness is 1 ⁇ m or more in order to improve the breakdown voltage, etc.
• a preferable crystal is such that when at least an oxide film is formed on a crystal substrate and then a crystal film containing a crystal made of a crystalline metal oxide containing a metal oxide as a main component is laminated, the lamination is performed by: This can be easily obtained by forming the crystalline film using oxygen atoms in the oxide film.
• the method for forming the crystal film is not particularly limited, and may be any known method (eg, MBE method, ion plating method, etc.), and the crystal growth conditions can be set as appropriate.
• the present invention also includes a laminated structure obtained by the above method and a method for manufacturing the same.
• FIG. 1 shows a preferred example of the laminated structure, in which an oxide film 5 is laminated as a first epitaxial layer on a crystal substrate 9 using an oxide film, Furthermore, a conductive film, a semiconductor film, or a piezoelectric film 4 is laminated as a second epitaxial layer on the first epitaxial layer. Further, on the conductive film etc. 4, an epitaxial film 1 made of a compound piezoelectric material or a compound semiconductor is laminated. Note that in this specification, the terms “film” and “layer” may be interchanged depending on the case or the situation.
• the laminated structure is formed by forming an oxide film 5 of the crystal substrate 9 on a crystal substrate 9, and then using oxygen in the oxide film 5 to form the oxide film 5 on the crystal substrate 9. It can be easily manufactured by forming a crystal film (first epitaxial layer) made of a crystalline metal oxide.
• the laminated structure may have the oxide film 5 on the crystal substrate 9, but when forming the crystal film, all the oxygen in the oxide film 5 is taken in and the oxide film 5 may have disappeared.
• preferred embodiments of the present invention will be described in more detail, but the present invention is not limited to these specific examples.
• the crystal substrate (hereinafter also simply referred to as “substrate”) is not particularly limited, such as the substrate material, as long as it does not impede the purpose of the present invention, and may be any known crystal substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystal substrate contains an inorganic compound. In the present invention, it is preferable that the substrate has crystals on part or all of its surface, and it is preferable that the substrate has crystals on all or part of its main surface on the crystal growth side. More preferably, a crystal substrate having crystals on the entire main surface on the crystal growth side is most preferable.
• the crystal is not particularly limited as long as it does not impede the purpose of the present invention, and the crystal structure is also not particularly limited, but may be cubic, tetragonal, trigonal, hexagonal, orthorhombic, or monoclinic. It is preferable that it is a cubic crystal, more preferably a cubic or hexagonal crystal, and most preferably (111), (100) or (0001) oriented. Further, the crystal substrate may have an off-angle, and examples of the off-angle include an off-angle of 0.2° to 12.0°. Here, the "off angle” refers to the angle between the substrate surface and the crystal growth plane.
• the shape of the substrate is not particularly limited as long as it is plate-like and serves as a support for the insulating film.
• the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and (111) , (100) or (0001) oriented crystalline Si substrate.
• the substrate material include, in addition to the Si substrate, one or more metals belonging to Groups 3 to 15 of the periodic table, or oxides of these metals.
• the shape of the substrate is not particularly limited, and may be approximately circular (for example, circular, oval, etc.) or polygonal (for example, triangular, square, rectangular, pentagonal, hexagonal, heptagonal, etc.). , octagonal, nonagonal, etc.), and various shapes can be suitably used.
• the crystal substrate has a flat surface, but it is also preferable that the crystal substrate has an uneven shape on a part or all of the surface, which improves the quality of crystal growth of the crystal film. This is preferable because it can provide better results.
• the above-mentioned crystal substrate having an uneven shape may be used as long as an uneven part consisting of a recess or a convex part is formed on a part or all of the surface. It is not limited, and it may be an uneven part consisting of a convex part, an uneven part consisting of a concave part, or an uneven part consisting of a convex part and a concave part.
• the uneven portions may be formed from regular protrusions or recesses, or may be formed from irregular protrusions or recesses.
• the uneven portions are formed periodically, and more preferably that they are patterned periodically and regularly.
• the shape of the uneven portion is not particularly limited, and examples thereof include a stripe shape, a dot shape, a mesh shape, or a random shape, but in the present invention, a dot shape or a stripe shape is preferable, and a dot shape is more preferable. .
• the pattern shape of the uneven portions may be a polygonal shape such as a triangle, a quadrilateral (for example, a square, a rectangle, or a trapezoid), a pentagon, or a hexagon.
• the shape is circular or elliptical.
• the lattice shape of the dots is a lattice shape such as a square lattice, an orthorhombic lattice, a triangular lattice, a hexagonal lattice, etc., and a triangular lattice shape is used. is more preferable.
• the cross-sectional shape of the concave portion or convex portion of the uneven portion is not particularly limited, and includes, for example, a U-shape, a U-shape, an inverted U-shape, a wave shape, a triangle, a quadrilateral (for example, a square, a rectangle, a trapezoid, etc.). ), polygons such as pentagons and hexagons.
• the thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 ⁇ m, more preferably 100 to 1000 ⁇ m.
• the oxide film is not particularly limited as long as it is an oxide film that can incorporate oxygen atoms into the crystal film, and usually contains an oxide material.
• the oxidizing material is not particularly limited as long as it does not impede the object of the present invention, and may be any known oxidizing material. Examples of the oxidizing material include metal or metalloid oxides.
• the oxide film contains the oxidizing material of the crystal substrate, and examples of such an oxide film include a thermal oxide film, a natural oxide film, and the like of the crystal substrate.
• the oxide film may be a sacrificial layer in which part or all of the film disappears or is destroyed when oxygen atoms are taken in; It is preferable that the oxide layer is an oxygen-supplying sacrificial layer in which oxygen atoms are taken in and the oxide film itself disappears during crystal growth. Further, the oxide film may be patterned, for example, in a stripe shape, a dot shape, a mesh shape, or a random shape. Note that the thickness of the oxide film is not particularly limited, but is preferably greater than 1 nm and less than 100 nm.
• the crystal film includes an epitaxial film in which oxygen atoms in the oxide film are incorporated.
• an epitaxial film in which oxygen atoms in the oxide film are incorporated means that oxygen atoms in the oxide film are taken away by the epitaxial film during crystal growth of the epitaxial film.
• the crystal film contains a neutron absorbing material.
• the neutron absorbing material may be a known neutron absorbing material, and in the present invention, such a neutron absorbing material is used to improve adhesion, crystallinity, and functionality by incorporating oxygen from the oxide film. The properties of the film can be improved.
• a suitable example of the neutron absorbing material is hafnium (Hf).
• a second epitaxial layer made of a conductive film, a semiconductor film, or a piezoelectric film is laminated on the crystal film, either directly or via another layer.
• the first epitaxial layer is regularly formed at the interface between the first epitaxial layer and the second epitaxial layer so that the lattice constant is approximately the same as the lattice constant of the second epitaxial layer. It can be transformed into.
• a suitable example of the above-mentioned regular transformation is a transformation in which the shape deforms into a peak-to-valley structure, and in the present invention, the angles formed by adjacent apexes and bottom points of the peak-to-valley structure are Preferably, they are different, and more preferably, the angles are each within a range of 30° to 45°.
• the first epitaxial layer usually has a first crystal plane and a second crystal plane, but due to the transformation, the lattice constant of the first crystal plane and the second crystal plane becomes Since a difference may occur, it is preferable that the difference in lattice constant between the first crystal plane and the second crystal plane is within the range of 0.1% to 20%.
• the difference in lattice constant between the first epitaxial layer and the second epitaxial layer is 0.0.
• a range of 1% to 20% can be easily achieved.
• the conductive film when a conductive film is laminated on the crystal film, and when the conductive film is made of a single crystal film of a conductive metal, it is possible to easily obtain a defect-free film with a large area. Therefore, not only the function as an electrode but also the characteristics of the device etc. can be improved.
• the conductive metal is not particularly limited as long as it does not impede the purpose of the present invention, and examples thereof include gold, silver, platinum, palladium, silver palladium, copper, nickel, and alloys thereof. preferably contains platinum.
• the present invention it is possible to obtain as an electrode a single crystal film that is defect-free in an area of preferably 100 nm 2 or more, and more preferably defect-free in an area of 1000 nm 2 or more.
• a single crystal film can be easily obtained.
• a single crystal film having a thickness of preferably 100 nm or more can be easily obtained as an electrode.
• the laminated structure is preferably used as an electrode substrate in which a crystalline conductive film is laminated on the insulating film. It can be used for.
• the semiconductor film is not particularly limited as long as it contains a semiconductor, and may be any known semiconductor film, but in the present invention it is preferable that it contains a cubic semiconductor.
• the cubic semiconductor include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, and mixed crystal semiconductors thereof. It will be done.
• the piezoelectric film is not particularly limited as long as it is made of a piezoelectric material, and may be a film made of a known piezoelectric material, but in the present invention, a piezoelectric film having a trigonal or hexagonal crystal structure is used. Preferably, it is a material.
• the piezoelectric material include lead zirconate titanate (PZT), other types of ceramic materials having a so-called perovskite structure represented by ABO 3 type, such as barium titanate, lead titanate, and potassium niobate.
• each of the conductive film, the semiconductor film, and the piezoelectric film is not particularly limited, but is preferably 10 nm to 1000 ⁇ m, more preferably 10 nm to 100 ⁇ m.
• the laminated structure is produced in a method for manufacturing a laminated structure in which an insulating film is laminated on a crystal substrate via at least an oxide film, in which the lamination is performed at 350° C. to 700° C. to remove oxygen atoms in the oxide film.
• This can be easily obtained by forming a crystal film using the above method.
• the temperature is in the range of 350° C. to 700° C., oxygen atoms in the oxide film can be easily incorporated into the crystal film to cause crystal growth.
• the crystal film is formed using oxygen gas after the above-described lamination is performed using oxygen atoms in the oxide film.
• the means for forming the insulating film is usually suitably used, and the film forming means may be any known film forming means. In the present invention, it is preferable that the film forming means is vapor deposition or sputtering.
• the laminated structure obtained as described above can be used as an element as it is or after being further processed, if desired, according to a conventional method.
• the laminated structure when used in the element, it may be used as it is, or it may be used as it is, or it may be used with other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layer, etc.). ) etc. may be formed before use.
• a functional film for example, a semiconductor film, a piezoelectric film, etc.
• the above-mentioned element is used, for example, in an electronic device (preferably a piezoelectric device), etc., in accordance with a conventional method. More specifically, for example, various electronic devices can be constructed by connecting the element as a piezoelectric element to a power source or an electric/electronic circuit, mounting it on a circuit board, or packaging it.
• the electronic device is preferably a piezoelectric device, and more preferably a piezoelectric device in electronic equipment such as a gyroscope or a motion sensor.
• an amplifier and a rectifier circuit are connected and packaged, it can be used for various sensors such as magnetic sensors.
• the electronic device is suitably used in electronic equipment according to a conventional method.
• the electronic device can be applied to various electronic devices other than those described above, and more specifically includes, for example, a liquid ejection head, a liquid ejection device, a vibration wave motor, an optical device, a vibration device, an imaging device, Suitable examples include piezoelectric acoustic components and audio playback devices, audio recording devices, mobile phones, and various information terminals that include the piezoelectric acoustic components.
• the element is a semiconductor element
• the electronic device is a semiconductor device.
• the semiconductor element or the semiconductor device (hereinafter also collectively referred to as “semiconductor device”) is not particularly limited as long as it does not impede the purpose of the present invention, and may be a known semiconductor element or semiconductor device.
• the semiconductor device is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor device. Although the semiconductor device may be a vertical device or a horizontal device, it is preferable in the present invention that the semiconductor device is a vertical device.
• Examples of the semiconductor device include a diode or a transistor, and more specifically, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a high electron mobility transistor (HEMT), a metal Semiconductor field effect transistor (MESFET), metal oxide semiconductor field effect transistor (MOSFET), static induction transistor (SIT), junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), light emitting diode (LED) or Combinations of these may be cited as suitable examples.
• SBD Schottky barrier diode
• JBS junction barrier Schottky diode
• HEMT high electron mobility transistor
• MESFET metal Semiconductor field effect transistor
• MOSFET metal oxide semiconductor field effect transistor
• SIT static induction transistor
• JFET junction field effect transistor
• IGBT insulated gate bipolar transistor
• LED light emitting diode
• the laminated structure will be used as a semiconductor device, more specifically, the buffer layer in the laminated structure will be used as an ohmic junction or electron emitting electrode or a buffer layer of the semiconductor device, and Preferred examples in which the epitaxial film is applied to the semiconductor layer of the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these examples.
• other layers for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layer, etc.
• the crystal substrate, buffer layer, etc. may be omitted as appropriate.
• FIG. 3 shows an example of a Schottky barrier diode (SBD) according to the present invention.
• the SBD in FIG. 3 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.
• the material of the electrode such as the Schottky electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxide Examples include a metal oxide conductive film such as zinc indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• IZO zinc indium
• organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the electrodes can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and the layer made of Mo and the layer made of Al are patterned using a photolithography method. This can be done by
• Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2 or Si 3 N 4 . It will be done.
• the insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a.
• the insulating layer can be formed by a known method such as a sputtering method, a vacuum evaporation method, or a CVD method.
• FIG. 4 shows a junction barrier Schottky diode (JBS), which is one of the preferred embodiments of the present invention.
• the semiconductor device in FIG. 4 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106.
• the JBS is configured to have better thermal stability and adhesion, further reduce leakage current, and further have better semiconductor properties such as withstand voltage.
• FIG. 5 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention.
• the MESFET in FIG. 5 includes an n-type semiconductor layer 111a, an n+-type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c. ing.
• the material of the gate electrode, drain electrode, and source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Metals such as Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) , a metal oxide conductive film such as indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the gate electrode, drain electrode, and source electrode can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method.
• the semi-insulator layer 114 may be any material as long as it is made of a semi-insulator, and examples of the semi-insulator include those containing a semi-insulating dopant and those that are not subjected to doping treatment.
• a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled.
• FIG. 6 shows an example of a photoelectron mobility transistor (HEMT) according to the present invention.
• the HEMT in FIG. 6 includes a wide bandgap n-type semiconductor layer 121a, a narrow bandgap n-type semiconductor layer 121b, an n+ type semiconductor layer 121c, an electron transit layer 123, a semi-insulator layer 124, a gate electrode 125a, and a source electrode 125b. , a drain electrode 125c, a buffer layer 128, and a crystal substrate 129.
• the material of the gate electrode, drain electrode, and source electrode may be any known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) ), a metal oxide conductive film such as indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the gate electrode, drain electrode, and source electrode can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method.
• the n-type semiconductor layer under the gate electrode is composed of at least a wide bandgap layer 121a and a narrow bandgap layer 121b, and the semi-insulating layer 124 may be composed of a semi-insulating material.
• the semi-insulator include those containing a semi-insulating dopant and those that are not subjected to doping treatment.
• the electron transit layer 123 formed on the semi-insulator layer 124 i (intentionally undoped)-GaN or the like is used, for example, when GaN, which is a nitride semiconductor, is used as the semiconductor.
• a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled. Further, in the present invention, by further providing a recessed structure, normally-off operation can be realized.
• FIG. 7 shows an example in which the semiconductor device of the present invention is a MOSFET.
• FIG. 7 shows an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a,
• a suitable example of a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode 135b and a drain electrode 135c is shown.
• the p + -type semiconductor layer 132a may be a p-type semiconductor layer, or may be the same as the p-type semiconductor layer 132.
• An n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 ⁇ m is formed on the drain electrode 135c made of the conductive crystal film, and an n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 ⁇ m is formed on the n+ type semiconductor layer 131b.
• a - type semiconductor layer 131a is formed.
• a plurality of trenches are formed in the n-type semiconductor layer 131a and the p-type semiconductor layer 132, each having a depth that reaches halfway through the n-type semiconductor layer 131a.
• a gate electrode 135a is buried in the trench via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 ⁇ m.
• the n-type A channel layer is formed on the side surface of the semiconductor layer 131a, and electrons are injected into the n-type semiconductor layer to turn it on.
• the off state by setting the voltage of the gate electrode to 0V, a channel layer is no longer formed and the n-type semiconductor layer is filled with a depletion layer, resulting in turn-off.
• etching masks are provided in predetermined regions of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+-type semiconductor layer 131c, and using the etching mask as a mask, the MOSFET is further etched by reactive ion etching or the like.
• Directional etching is performed to form a trench groove having a depth that reaches from the surface of the n+ type semiconductor layer 131c to the middle of the n- type semiconductor layer 131a.
• a gate insulating film 134 having a thickness of, for example, 50 nm to 1 ⁇ m is formed on the side and bottom surfaces of the trench groove using a known method such as a thermal oxidation method, a vacuum evaporation method, a sputtering method, or a CVD method.
• a gate electrode material, such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n-type semiconductor layer using a vacuum evaporation method, a sputtering method, or the like.
• a power MOSFET can be manufactured by forming the source electrode 135b on the n+ type semiconductor layer 131c using a known method such as a vacuum evaporation method, a sputtering method, or a CVD method.
• the electrode material of the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, and Pt.
• metals such as Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide
• metal oxide conductive film such as indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• FIG. 7 shows an example of a trench-type vertical MOSFET
• the present invention is not limited thereto and can be applied to various MOSFET configurations.
• the series resistance may be reduced by digging the trench shown in FIG. 7 to a depth that reaches the bottom of the n-type semiconductor layer 131a.
• FIG. 8 shows an example in which the semiconductor device of the present invention is an SIT.
• the SIT in FIG. 8 includes an n-type semiconductor layer 141a, n+-type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
• An n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 ⁇ m is formed on the drain electrode 145c made of a conductive crystal film, and an n ⁇ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 ⁇ m is formed on the n+ type semiconductor layer 141b.
• a type semiconductor layer 141a is formed.
• an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.
• a plurality of trench grooves are formed in the n- type semiconductor layer 141a, penetrating the n+ type semiconductor layer 141c and having a depth reaching halfway through the n- type semiconductor layer 141a.
• a gate electrode 145a is formed on the n-type semiconductor layer in the trench groove.
• etching mask is provided in predetermined regions of the n- type semiconductor layer 141a and the n+-type semiconductor layer 141c, and using the etching mask as a mask, for example, a reactive ion etching method, etc.
• Anisotropic etching is performed to form a trench groove having a depth reaching from the surface of the n+ type semiconductor layer 141c to the middle of the n- type semiconductor layer.
• a gate electrode material such as polysilicon is formed in the trench by a CVD method, a vacuum evaporation method, a sputtering method, or the like to have a thickness equal to or less than the thickness of the n-type semiconductor layer. Then, by forming a source electrode 145b on the n+ type semiconductor layer 141c and a drain electrode 145c on the n+ type semiconductor layer 141b using a known method such as a vacuum evaporation method, a sputtering method, or a CVD method, The SIT shown in FIG. 8 can be manufactured.
• the electrode material of the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, and Pt. , V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, metals such as Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide Examples include a metal oxide conductive film such as indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• IZO indium
• organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• JFET junction field effect transistor
• FIG. 10 shows an insulator comprising an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.
• IGBT gated bipolar transistor
• FIG. 11 shows an example in which the semiconductor device of the present invention is a light emitting diode (LED).
• the semiconductor light emitting device of FIG. 11 includes an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161.
• a p-type semiconductor layer 162 is stacked on the light emitting layer 163.
• a light-transmitting electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the light-transmitting electrode 167.
• the semiconductor light emitting device in FIG. 11 may be covered with a protective layer except for the electrode portion.
• Examples of the material for the transparent electrode include conductive oxide materials containing indium (In) or titanium (Ti). More specifically, examples thereof include In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2 , a mixed crystal of two or more of these, or a doped material thereof. By providing these materials by known means such as sputtering, a transparent electrode can be formed. Further, after forming the light-transmitting electrode, thermal annealing may be performed for the purpose of making the light-transmitting electrode transparent.
• the first electrode 165a is used as a positive electrode
• the second electrode 165b is used as a negative electrode
• a current is passed through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 through them. This causes the light emitting layer 163 to emit light.
• Examples of the material of the first electrode 165a include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Metals such as Zn, In, Pd, Nd or Ag or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), polyaniline, polythiophene or an organic conductive compound such as polypyrrole, or a mixture thereof.
• metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), polyaniline, polythiophene or an organic conductive compound such as polypyrrole, or a mixture thereof.
• the electrode formation method is not particularly limited, and may include wet methods such as printing, spraying, and coating, physical methods such as vacuum evaporation, sputtering, and ion plating, CVD, and plasma CVD. It can be formed according to a method appropriately selected from chemical methods such as, etc., taking into consideration compatibility with the above-mentioned materials.
• the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, an inverter or a converter by using known means, and furthermore, the semiconductor device can be suitably used as a semiconductor device such as a power module, an inverter, or a converter. Suitable for use in systems, etc.
• the power supply device can be manufactured by connecting the semiconductor device to a wiring pattern or the like using a known method.
• FIG. 12 shows an example of a power supply system.
• FIG. 12 shows a power supply system using a plurality of the power supply devices and control circuits. The power supply system can be used in a system device in combination with an electronic circuit, as shown in FIG. Note that FIG.
• Figure 14 shows an example of a power supply circuit diagram of the power supply device.
• Figure 14 shows a power supply circuit of a power supply device consisting of a power circuit and a control circuit, in which DC voltage is switched at high frequency by an inverter (consisting of MOSFETAs to D) and converted to AC, and then insulation and transformation are performed by a transformer. , rectified by rectifier MOSFETs (A to B'), smoothed by DCL (smoothing coils L1, L2) and a capacitor, and outputs a DC voltage.
• a voltage comparator compares the output voltage with a reference voltage
• a PWM control circuit controls the inverter and rectifier MOSFET so that the desired output voltage is achieved.
• Example 1 After treating the crystal growth side of the Si substrate (100) with RIE and heating it in the presence of oxygen to form a thermal oxide film, the metal of the evaporation source and the Si An insulating film made of crystalline oxide was formed on the Si substrate by causing a thermal reaction with oxygen in the oxide film on the substrate. Next, an insulating film was further formed by a vapor deposition method by flowing oxygen, lowering the temperature, and increasing the pressure. The conditions of the vapor deposition method during this film formation were as follows.
• Vapor deposition source Hf, Zr Voltage: 3.5-4.75V Pressure: 3 ⁇ 10-2 to 6 ⁇ 10-2 Pa
• Substrate temperature 500-650°C
• An ITO film was further laminated on the insulating film of the obtained laminated structure according to the method described above, and a PZT film was laminated on the ITO film to obtain a laminated structure as shown in FIG. .
• Example 2 A laminated structure was obtained in the same manner as in Example 1 except that a Si substrate was used instead of (111).
• the vapor deposition film forming apparatus used in Example 1 is shown in FIG.
• the film forming apparatus in FIG. 15 includes metal sources 1101a to 1101b, earths 1102a to 1102h, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, It includes at least an Ar source 1108, a reactive gas source 1109, a power source 1110, a substrate holder 1111, a substrate 1112, a cut filter 1113, an ICP ring 1114, a vacuum chamber 1115, and a rotating shaft 1116.
• the ICP electrodes 1103a to 1103b in FIG. 15 have a substantially concave curved shape or a parabolic shape curved toward the center of the substrate 1112.
• the substrate 1112 is locked onto the substrate holder 1111.
• the rotation shaft 1116 is rotated using the power supply 1110 and a rotation mechanism (not shown), and the substrate 1112 is rotated.
• the substrate 112 is heated by lamps 1107a to 1107b, and the inside of the vacuum chamber 1115 is evacuated to a vacuum or reduced pressure by a vacuum pump (not shown).
• Ar gas is introduced into the vacuum chamber 1115 from the Ar source 1108, and the substrate is The surface of the substrate 1112 is cleaned by forming argon plasma on the substrate 1112.
• Ar gas is introduced into the vacuum chamber 1115, and a reactive gas is also introduced using the reactive gas source 1109.
• the lamps 1107a to 1107b which are lamp heaters, are alternately turned on and off to form a crystal growth film of better quality.
• the laminated structure of the present invention can be used in all fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic parts/electrical equipment parts, optical/electrophotography related equipment, industrial parts, etc., but it is preferably used in semiconductor devices. .

Landscapes

• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Materials Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Mechanical Engineering (AREA)
• Inorganic Chemistry (AREA)
• Crystallography & Structural Chemistry (AREA)
• Ceramic Engineering (AREA)
• Junction Field-Effect Transistors (AREA)
• Electrodes Of Semiconductors (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=90098007

Family Applications (1)

Country Status (3)

Cited By (1)

Citations (3)

• 2023
  • 2023-08-30 TW TW112132840A patent/TW202443887A/zh unknown
  • 2023-08-31 JP JP2024544595A patent/JP7847390B2/ja active Active
  • 2023-08-31 WO PCT/JP2023/032026 patent/WO2024048767A1/ja not_active Ceased

Patent Citations (3)

Also Published As

Similar Documents

Legal Events