Classifications

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  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/38—Nitrides
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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  • H10D64/00—Electrodes of devices having potential barriers
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  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/81—Bodies
  • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
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  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
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  • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
  • H10N30/076—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
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  • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
  • H10N30/079—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials

Definitions

• the present invention relates to crystals, laminated structures, elements, electronic devices, electronic equipment, and systems.
• An object of the present invention is to provide a crystal having excellent crystallinity, a laminated structure, and an element, electronic device, electronic equipment, and system using the same.
• the present inventors have found that a conductive crystal containing a crystalline nitride, the crystalline nitride containing nitrides of Hf and Zr, is an excellent crystal. Furthermore, they found that the crystals are useful for crystal growth of nitride functional films, and that the crystals solve the above-mentioned conventional problems. I found out that it can be solved all at once. Further, after obtaining the above knowledge, the present inventors conducted further studies and completed the present invention.
• [5] The crystal according to any one of [1] to [4], wherein the crystalline nitride contains 50 atomic % or more of Hf nitride and Zr nitride based on the crystalline nitride.
• [6] The crystal according to any one of [1] to [5] above, which is an electrode.
• [8] The crystal according to [7] above, which has a film thickness of 1 ⁇ m or more.
• [9] A laminated structure in which a crystal film is laminated directly or through another layer on a crystal substrate, the crystal film being the crystal according to any one of [1] to [8] above.
• An electronic device comprising a crystal or a laminated structure, wherein the crystal is the crystal according to any one of [1] to [8], or the laminated structure is the crystal according to any one of [9] or [8] above. 10].
• An electronic device characterized by being the laminated structure according to [10].
• the electronic device according to [13] above which is a piezoelectric device or a semiconductor device.
• the crystal and the laminated structure of the present invention have excellent crystallinity, and elements, electronic devices, electronic equipment, and systems using the crystal and the laminated structure have good characteristics of their respective functional films. It has the effect of becoming a thing.
• FIG. 1 is a diagram schematically showing an example of a preferred embodiment of a laminated structure of the present invention.
• FIG. 3 is a diagram schematically showing a step of forming a buffer layer.
• 1 is a diagram schematically showing an example of a Schottky barrier diode (SBD) according to the present invention.
• 1 is a diagram schematically showing a junction barrier Schottky diode (JBS) that is one of the preferred embodiments of the present invention.
• JBS junction barrier Schottky diode
• 1 is a diagram schematically showing an example of a metal semiconductor field effect transistor (MESFET) according to the present invention.
• MESFET metal semiconductor field effect transistor
• HEMT photoelectron mobility transistor
• FIG. 2 is a diagram schematically showing an example in which the semiconductor device of the present invention is a MOSFET.
• FIG. 1 is a diagram schematically showing an example in which the semiconductor device of the present invention is an SIT.
• a preferred example of a junction field effect transistor (JFET) of the present invention is schematically shown.
• 1 is a diagram schematically showing a preferred example of an insulated gate bipolar transistor (IGBT) of the present invention.
• FIG. 2 is a diagram schematically showing an example in which the semiconductor device is a light emitting diode (LED).
• 1 is a diagram schematically showing a preferred example of a power supply system.
• FIG. 2 is a diagram schematically showing a preferred example of a system device. It is a figure which shows typically a suitable example of the power supply circuit diagram of a power supply device.
• 1 is a diagram schematically showing a film forming apparatus suitably used in Examples.
• the crystal of the present invention is a conductive crystal containing a crystalline nitride, and is characterized in that the crystalline nitride contains nitrides of Hf and Zr.
• the laminated structure of the present invention is a laminated structure in which a crystal film is laminated on a crystal substrate directly or via another layer, and the crystal film is made of the crystal. do.
• a preferred example of the laminated structure is shown in FIG. In the laminated structure shown in FIG. 1, a buffer layer 5 made of the crystal described above is laminated on a crystal substrate 9, and an epitaxial film 1 made of a compound semiconductor is further laminated on the buffer layer 5. Note that in this specification, the terms “film” and “layer” may be interchanged depending on the case or the situation.
• the buffer layer 5 is preferably formed on a crystal substrate 9 using a known crystal growth method using nitrogen.
• the crystal growth means may be a known means, and may be either a vapor phase crystal growth means or a liquid phase crystal growth means. Examples of the crystal growth method include a vapor deposition method, a CVD method, and a sputtering method.
• the buffer layer 5 after forming the buffer layer 5, it is preferable to form an epitaxial film made of a compound semiconductor on the buffer layer using the crystal growth means, and in this way, the epitaxial film is formed. As a result, as shown in FIG.
• the buffer layer is transformed in the crystal growth direction to form a peak-to-valley structure at the interface with the epitaxial film, and this peak-to-valley structure allows the epitaxial film to be of good quality with excellent crystallinity. can be obtained easily.
• the crystal substrate (hereinafter also simply referred to as “substrate”) is not particularly limited, such as the substrate material, as long as it does not impede the purpose of the present invention, and may be any known crystal substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystal substrate contains an inorganic compound.
• the substrate preferably has crystals on a part or all of its surface, and is preferably a crystal substrate that has crystals on all or a part of its main surface on the crystal growth side. More preferably, a crystal substrate having crystals on the entire main surface on the crystal growth side is most preferable.
• the crystal is not particularly limited as long as it does not impede the purpose of the present invention, and the crystal structure is also not particularly limited, and may include cubic system, tetragonal system, trigonal system, hexagonal system, orthorhombic system, and monoclinic system. Although it may have any crystal structure, such as a cubic system or a hexagonal system, in the present invention, a cubic system or a hexagonal system crystal structure is preferable, and the crystal is oriented in a (100) or (200) direction. is more preferable. Further, the crystal substrate may have an off-angle, and examples of the off-angle include an off-angle of 0.2° to 12.0°. Here, the "off angle" refers to the angle between the substrate surface and the crystal growth plane.
• the shape of the substrate is not particularly limited as long as it is plate-like and serves as a support for the insulating film. Although it may be an insulating substrate or a semiconductor substrate, in the present invention, the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and (100) Most preferably, it is a crystalline Si substrate oriented in the direction of .
• the substrate material include, in addition to the Si substrate, one or more metals belonging to Groups 3 to 15 of the periodic table, or oxides of these metals.
• the shape of the substrate is not particularly limited, and may be approximately circular (for example, circular, oval, etc.) or polygonal (for example, triangular, square, rectangular, pentagonal, hexagonal, heptagonal, etc.). , octagonal, nonagonal, etc.), and various shapes can be suitably used.
• the crystal substrate has a flat surface, but it is also preferable that the crystal substrate has an uneven shape on part or all of the surface.
• the above-mentioned crystal substrate having an uneven shape may be used as long as an uneven part consisting of a recess or a convex part is formed on a part or all of the surface, and the uneven part is particularly suitable if the uneven part consists of a convex part or a recess. Without limitation, it may be an uneven part consisting of a convex part, an uneven part consisting of a concave part, or an uneven part consisting of a convex part and a concave part.
• the uneven portions may be formed from regular protrusions or recesses, or may be formed from irregular protrusions or recesses.
• the uneven portions are formed periodically, and more preferably that they are patterned periodically and regularly.
• the shape of the uneven portion is not particularly limited, and examples thereof include a stripe shape, a dot shape, a mesh shape, or a random shape, but in the present invention, a dot shape or a stripe shape is preferable, and a dot shape is more preferable. .
• the pattern shape of the uneven portions may be a polygonal shape such as a triangle, a quadrilateral (for example, a square, a rectangle, or a trapezoid), a pentagon, or a hexagon.
• the shape is circular or elliptical.
• the lattice shape of the dots is a lattice shape such as a square lattice, an orthorhombic lattice, a triangular lattice, a hexagonal lattice, etc., and a triangular lattice shape is used. is more preferable.
• the cross-sectional shape of the concave part or convex part of the uneven part is not particularly limited, but may be, for example, a U-shape, a U-shape, an inverted U-shape, a wave shape, a triangle, a quadrilateral (for example, a square, a rectangle, a trapezoid, etc.). ), polygons such as pentagons and hexagons.
• the thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 ⁇ m, more preferably 100 to 1000 ⁇ m.
• the buffer layer is a conductive crystal containing a crystalline nitride, and is not particularly limited as long as the crystalline nitride includes a crystal containing nitrides of Hf and Zr.
• the crystals Preferably, contain HfN and ZrN. Since the crystal contains HfN and ZrN, even when the epitaxial film is formed by crystal growth in two or more layers, transformation occurs in each layer, and the crystallinity of the epitaxial film can be further improved. Furthermore, the controllability of the properties of the functional film at the interface can be further improved.
• the crystal preferably has a cubic crystal structure or a hexagonal crystal structure, and preferably includes a (111), (100), (010) or (0001) oriented crystal.
• the crystal contains Hf nitride in an amount of 30 atomic % or more based on the crystalline nitride, and contains Hf nitride and Zr nitride in an amount of 50 atomic % or more based on the crystalline nitride. It is more preferable to include.
• the buffer layer can be suitably formed on the crystal substrate at 350° C. to 700° C. using a Hf source, a Zr source, and nitrogen gas by a known crystal growth method such as sputtering.
• the buffer layer may include a mixed crystal film.
• the mixed crystal film is not particularly limited as long as it is a crystal film consisting of a mixed crystal, and the mixed crystal may include one or two selected from Ti, Al, Y, and Ce in addition to nitrides of Hf and Zr. Suitable examples include mixed crystals containing more than one species of nitride, etc. According to such a preferable mixed crystal, it is possible not only to improve the stress relaxation effect of the buffer layer but also to improve the film quality of the epitaxial film.
• the epitaxial film is not particularly limited as long as it is a crystal grown film made of a compound semiconductor.
• the compound semiconductor is not particularly limited either, and may be a known compound semiconductor.
• the compound semiconductor include nitride semiconductors, carbide semiconductors (eg, SiC, etc.), oxide semiconductors, InP, and GaAs.
• the compound semiconductor is preferably a wide bandgap semiconductor, more preferably a nitride semiconductor.
• the nitride semiconductor include III-V group semiconductors (aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), etc.), boron nitride (BN), and the like.
• the epitaxial film preferably has a cubic crystal structure or a hexagonal crystal structure, and is more preferably a crystal grown film made of a cubic semiconductor or a hexagonal semiconductor.
• the cubic semiconductor or hexagonal semiconductor include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, or a mixed crystal thereof.
• Examples include semiconductors.
• the laminated structure obtained as described above can be used in a semiconductor device as it is or after being further processed, if desired, according to a conventional method.
• the buffer layer in the laminated structure is used as an ohmic junction or electron emitting electrode or buffer layer of the semiconductor device, and the epitaxial film in the laminated structure is used as a semiconductor layer of the semiconductor device. It can be suitably used.
• the laminated structure when used in a semiconductor device, it may be used as it is in the semiconductor device, or it may be used in other layers (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other layers). It may be used after forming an intermediate layer, etc.). Further, the crystal substrate may be peeled off using a known peeling means in the semiconductor device.
• the semiconductor device is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor device. Although the semiconductor device may be a vertical device or a horizontal device, it is preferable in the present invention that the semiconductor device is a vertical device.
• Examples of the semiconductor device include a diode or a transistor, and more specifically, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a high electron mobility transistor (HEMT), a metal Semiconductor field effect transistor (MESFET), metal oxide semiconductor field effect transistor (MOSFET), static induction transistor (SIT), junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), light emitting diode (LED) or Combinations of these may be cited as suitable examples.
• SBD Schottky barrier diode
• JBS junction barrier Schottky diode
• HEMT high electron mobility transistor
• MESFET metal Semiconductor field effect transistor
• MOSFET metal oxide semiconductor field effect transistor
• SIT static induction transistor
• JFET junction field effect transistor
• IGBT insulated gate bipolar transistor
• LED light emitting diode
• the laminated structure will be used as a semiconductor device, more specifically, the buffer layer in the laminated structure will be used as an ohmic junction or electron emitting electrode or a buffer layer of the semiconductor device, and Preferred examples in which the epitaxial film is applied to the semiconductor layer of the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these examples.
• other layers for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layer, etc.
• the crystal substrate, buffer layer, etc. may be omitted as appropriate.
• FIG. 3 shows an example of a Schottky barrier diode (SBD) according to the present invention.
• the SBD in FIG. 3 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.
• the material of the electrode such as the Schottky electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxide Examples include a metal oxide conductive film such as zinc indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• IZO zinc indium
• organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the electrodes can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and the layer made of Mo and the layer made of Al are patterned using a photolithography method. This can be done by
• Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2 or Si 3 N 4 . It will be done.
• the insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a.
• the insulating layer can be formed by a known method such as a sputtering method, a vacuum evaporation method, or a CVD method.
• FIG. 4 shows a junction barrier Schottky diode (JBS), which is one of the preferred embodiments of the present invention.
• the semiconductor device in FIG. 4 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106.
• the JBS is configured to have better thermal stability and adhesion, further reduce leakage current, and further have better semiconductor properties such as withstand voltage.
• FIG. 5 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention.
• the MESFET in FIG. 5 includes an n-type semiconductor layer 111a, an n+-type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c. ing.
• the material of the gate electrode, drain electrode, and source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Metals such as Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) , a metal oxide conductive film such as indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the gate electrode, drain electrode, and source electrode can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method.
• the semi-insulator layer 114 may be any material as long as it is made of a semi-insulator, and examples of the semi-insulator include those containing a semi-insulating dopant and those that are not subjected to doping treatment.
• a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled.
• FIG. 6 shows an example of a photoelectron mobility transistor (HEMT) according to the present invention.
• the HEMT in FIG. 6 includes a wide bandgap n-type semiconductor layer 121a, a narrow bandgap n-type semiconductor layer 121b, an n+ type semiconductor layer 121c, an electron transit layer 123, a semi-insulator layer 124, a gate electrode 125a, and a source electrode 125b. , a drain electrode 125c, a buffer layer 128, and a crystal substrate 129.
• the material of the gate electrode, drain electrode, and source electrode may be any known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) ), a metal oxide conductive film such as indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• the gate electrode, drain electrode, and source electrode can be formed by, for example, a known method such as a vacuum evaporation method or a sputtering method.
• the n-type semiconductor layer under the gate electrode is composed of at least a wide bandgap layer 121a and a narrow bandgap layer 121b, and the semi-insulating layer 124 may be composed of a semi-insulating material.
• the semi-insulator include those containing a semi-insulating dopant and those that are not subjected to doping treatment.
• the electron transit layer 123 formed on the semi-insulator layer 124 i (intentionally undoped)-GaN or the like is used, for example, when GaN, which is a nitride semiconductor, is used as the semiconductor.
• a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled. Further, in the present invention, by further providing a recessed structure, normally-off operation can be realized.
• FIG. 7 shows an example in which the semiconductor device of the present invention is a MOSFET.
• FIG. 7 shows an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a,
• a suitable example of a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode 135b and a drain electrode 135c is shown.
• the p + -type semiconductor layer 132a may be a p-type semiconductor layer, or may be the same as the p-type semiconductor layer 132.
• a plurality of trenches are formed in the n-type semiconductor layer 131a and the p-type semiconductor layer 132, each having a depth that reaches halfway through the n-type semiconductor layer 131a.
• a gate electrode 135a is buried in the trench via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 ⁇ m.
• the n-type A channel layer is formed on the side surface of the semiconductor layer 131a, and electrons are injected into the n-type semiconductor layer to turn it on.
• the off state by setting the voltage of the gate electrode to 0V, a channel layer is no longer formed and the n-type semiconductor layer is filled with a depletion layer, resulting in turn-off.
• etching masks are provided in predetermined regions of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+-type semiconductor layer 131c, and using the etching mask as a mask, the MOSFET is further etched by reactive ion etching or the like.
• Directional etching is performed to form a trench groove having a depth that reaches from the surface of the n+ type semiconductor layer 131c to the middle of the n- type semiconductor layer 131a.
• a gate insulating film 134 having a thickness of, for example, 50 nm to 1 ⁇ m is formed on the side and bottom surfaces of the trench groove using a known method such as a thermal oxidation method, a vacuum evaporation method, a sputtering method, or a CVD method.
• a gate electrode material, such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n-type semiconductor layer using a vacuum evaporation method, a sputtering method, or the like.
• a power MOSFET can be manufactured by forming the source electrode 135b on the n+ type semiconductor layer 131c using a known method such as a vacuum evaporation method, a sputtering method, or a CVD method.
• the electrode material of the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, and Pt.
• metals such as Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide
• metal oxide conductive film such as indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• FIG. 7 shows an example of a trench-type vertical MOSFET
• the present invention is not limited thereto and can be applied to various MOSFET configurations.
• the series resistance may be reduced by digging the trench shown in FIG. 7 to a depth that reaches the bottom of the n-type semiconductor layer 131a.
• FIG. 8 shows an example in which the semiconductor device of the present invention is an SIT.
• the SIT in FIG. 8 includes an n-type semiconductor layer 141a, n+-type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
• an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.
• a plurality of trench grooves are formed in the n- type semiconductor layer 141a, penetrating the n+ type semiconductor layer 141c and having a depth reaching halfway through the n- type semiconductor layer 141a.
• a gate electrode 145a is formed on the n-type semiconductor layer in the trench groove.
• etching mask is provided in predetermined regions of the n- type semiconductor layer 141a and the n+-type semiconductor layer 141c, and using the etching mask as a mask, for example, a reactive ion etching method, etc.
• Anisotropic etching is performed to form a trench groove having a depth reaching from the surface of the n+ type semiconductor layer 141c to the middle of the n- type semiconductor layer.
• a gate electrode material such as polysilicon is formed in the trench by a CVD method, a vacuum evaporation method, a sputtering method, or the like to have a thickness equal to or less than the thickness of the n-type semiconductor layer. Then, by forming a source electrode 145b on the n+ type semiconductor layer 141c and a drain electrode 145c on the n+ type semiconductor layer 141b using a known method such as a vacuum evaporation method, a sputtering method, or a CVD method, The SIT shown in FIG. 8 can be manufactured.
• the electrode material of the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, and Pt. , V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, metals such as Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc oxide Examples include a metal oxide conductive film such as indium (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• IZO indium
• organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
• JFET junction field effect transistor
• FIG. 10 shows an insulator comprising an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.
• IGBT gated bipolar transistor
• FIG. 11 shows an example in which the semiconductor device of the present invention is a light emitting diode (LED).
• the semiconductor light emitting device of FIG. 11 includes an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161.
• a p-type semiconductor layer 162 is stacked on the light emitting layer 163.
• a light-transmitting electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the light-transmitting electrode 167.
• the semiconductor light emitting device in FIG. 11 may be covered with a protective layer except for the electrode portion.
• Examples of the material for the transparent electrode include conductive oxide materials containing indium (In) or titanium (Ti). More specifically, examples thereof include In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2 , a mixed crystal of two or more of these, or a doped material thereof. By providing these materials by known means such as sputtering, a transparent electrode can be formed. Further, after forming the light-transmitting electrode, thermal annealing may be performed for the purpose of making the light-transmitting electrode transparent.
• the first electrode 165a is a positive electrode
• the second electrode 165b is a negative electrode
• a current is passed through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 through them. This causes the light emitting layer 163 to emit light.
• Examples of the material of the first electrode 165a include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Metals such as Zn, In, Pd, Nd or Ag or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), polyaniline, polythiophene or an organic conductive compound such as polypyrrole, or a mixture thereof.
• metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), polyaniline, polythiophene or an organic conductive compound such as polypyrrole, or a mixture thereof.
• the electrode formation method is not particularly limited, and may include wet methods such as printing, spraying, and coating, physical methods such as vacuum evaporation, sputtering, and ion plating, CVD, and plasma CVD. It can be formed according to a method appropriately selected from chemical methods such as, etc., taking into consideration compatibility with the above-mentioned materials.
• the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, an inverter or a converter by using known means, and furthermore, the semiconductor device can be suitably used as a semiconductor device such as a power module, an inverter, or a converter. Suitable for use in systems, etc.
• the power supply device can be manufactured by connecting the semiconductor device to a wiring pattern or the like using a known method.
• FIG. 12 shows an example of a power supply system.
• FIG. 12 shows a power supply system using a plurality of the power supply devices and control circuits. The power supply system can be used in a system device in combination with an electronic circuit, as shown in FIG. Note that FIG.
• Figure 14 shows an example of a power supply circuit diagram of the power supply device.
• Figure 14 shows a power supply circuit of a power supply device consisting of a power circuit and a control circuit, in which DC voltage is switched at high frequency by an inverter (consisting of MOSFETAs to D) and converted to AC, and then insulation and transformation are performed by a transformer. , rectified by rectifier MOSFETs (A to B'), smoothed by DCL (smoothing coils L1, L2) and a capacitor, and outputs a DC voltage.
• a voltage comparator compares the output voltage with a reference voltage
• a PWM control circuit controls the inverter and rectifier MOSFET so that the desired output voltage is achieved.
• Example 1 The crystal growth surface side of the Si substrate (100) was subjected to RIE treatment, and a single crystal of crystalline nitride was formed on the Si substrate by a vapor deposition method using nitrogen gas.
• the conditions of the vapor deposition method during this film formation were as follows. Vapor deposition source: Hf, Zr Voltage: 3.5-4.75V Pressure: 3 ⁇ 10-2 to 6 ⁇ 10-2 Pa
• the obtained laminated structure is a laminated structure containing a crystalline film having good adhesion and crystallinity, and the obtained crystalline film has a film thickness of 3 ⁇ m, and its electrical properties were examined using the four-terminal method. , had good conductivity.
• Example 2 A laminated structure was obtained in the same manner as in Example 1 except that a Si substrate was used instead of (111). The crystalline film of the obtained laminated structure had good conductivity as in Example 1.
• the vapor deposition film forming apparatus used in Example 1 is shown in FIG.
• the film forming apparatus in FIG. 15 includes metal sources 1101a to 1101b, earths 1102a to 1102h, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, It includes at least an Ar source 1108, a reactive gas source 1109, a power source 1110, a substrate holder 1111, a substrate 1112, a cut filter 1113, an ICP ring 1114, a vacuum chamber 1115, and a rotating shaft 1116.
• the ICP electrodes 1103a to 1103b in FIG. 15 have a substantially concave curved shape or a parabolic shape curved toward the center of the substrate 1112.
• the substrate 1112 is locked onto the substrate holder 1111.
• the rotation shaft 1116 is rotated using the power supply 1110 and a rotation mechanism (not shown), and the substrate 1112 is rotated.
• the substrate 112 is heated by lamps 1107a to 1107b, and the inside of the vacuum chamber 1115 is evacuated to a vacuum or reduced pressure by a vacuum pump (not shown).
• Ar gas is introduced into the vacuum chamber 1115 from the Ar source 1108, and the substrate is The surface of the substrate 1112 is cleaned by forming argon plasma on the substrate 1112.
• Ar gas is introduced into the vacuum chamber 1115, and a reactive gas is also introduced using the reactive gas source 1109.
• the lamps 1107a to 1107b which are lamp heaters, are alternately turned on and off to form a crystal growth film of better quality.
• the laminated structure of the present invention can be used in all fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic parts/electrical equipment parts, optical/electrophotography related equipment, industrial parts, etc., but it is preferably used in semiconductor devices. .

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