WO2024046070A9 - 阵列基板及其检测方法、显示装置 - Google Patents

阵列基板及其检测方法、显示装置 Download PDF

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Publication number
WO2024046070A9
WO2024046070A9 PCT/CN2023/111977 CN2023111977W WO2024046070A9 WO 2024046070 A9 WO2024046070 A9 WO 2024046070A9 CN 2023111977 W CN2023111977 W CN 2023111977W WO 2024046070 A9 WO2024046070 A9 WO 2024046070A9
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WO
WIPO (PCT)
Prior art keywords
lead
pixel
array substrate
touch
electrode
Prior art date
Application number
PCT/CN2023/111977
Other languages
English (en)
French (fr)
Other versions
WO2024046070A1 (zh
Inventor
王栋
李红敏
唐锋景
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024046070A1 publication Critical patent/WO2024046070A1/zh
Publication of WO2024046070A9 publication Critical patent/WO2024046070A9/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present invention relates to but is not limited to the field of display technology, and specifically to an array substrate and a detection method thereof, and a display device.
  • touch panels Touch Screen Panel
  • Touch panels can be divided into add-on mode, on-cell, and in-cell according to their composition structure.
  • the add-on touch panel is to produce the touch module and the display module separately, and then bond them together to become a touch panel with touch function. It has disadvantages such as high production cost, low light transmittance, and thicker module.
  • the in-cell touch panel is to embed the touch electrode of the touch module inside the display module, which not only greatly reduces the overall thickness of the module, but also greatly reduces the production cost, and gradually becomes the mainstream of capacitive touch panels.
  • the present disclosure provides an array substrate, including a display area, wherein the display area at least includes: a plurality of touch electrodes constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units constituting a plurality of pixel rows and a plurality of pixel columns, the orthographic projection of the touch unit on the array substrate at least partially overlaps with the orthographic projection of the plurality of pixel units on the array substrate, and the pixel unit includes a plurality of sub-pixels; a touch lead group is arranged between at least one adjacent pixel column, the touch lead group includes at least a first lead and a second lead arranged in parallel, the first lead is connected to a touch electrode in a touch row, and the second lead is connected to another touch electrode in an adjacent touch row.
  • At least one touch column includes N touch electrodes arranged in sequence along the pixel column direction, the orthographic projection of the touch column on the array substrate at least partially overlaps with the orthographic projection of N/2 pixel columns on the array substrate, a first lead located between the i-th pixel column and the i+1-th pixel column is connected to the touch electrode in the 2i-1-th touch row, and a second lead located between the i-th pixel column and the i+1-th pixel column is connected to the touch electrode in the 2i-th touch row, N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N/2.
  • At least one pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along the pixel row direction, the sub-pixels include a gate line, a data line, a thin film transistor and a pixel electrode, the thin film transistor is respectively connected to the gate line, the data line and the pixel electrode, the touch electrode is multiplexed as a common electrode, the first lead and the second lead are multiplexed as a common electrode line; the first lead is arranged on a side of the third sub-pixel away from the first sub-pixel, and the second lead is arranged on a side of the first lead away from the first sub-pixel.
  • a first connection block is disposed on the first lead line, and the first connection block is connected to a touch electrode through a first via hole.
  • the first lead in at least one pixel row, includes at least a first straight line segment, a second straight line segment, and a bending segment located between the first straight line segment and the second straight line segment, the first end of the bending segment is connected to the first straight line segment, the second end of the bending segment is connected to the second straight line segment, the middle portion of the bending segment protrudes in a direction away from the second lead, and the first connecting block is arranged in the area formed by the bending of the bending segment.
  • an orthographic projection of the first connection block on the array substrate at least partially overlaps with an orthographic projection of the gate line on the array substrate.
  • an orthographic projection of the first via hole on the array substrate at least partially overlaps with an orthographic projection of the gate line on the array substrate.
  • a second connection block is disposed on the second lead line, and the second connection block is connected to another touch electrode through a second via hole.
  • the first lead in at least one pixel row, includes at least a first straight line segment, a second straight line segment, and a bending segment located between the first straight line segment and the second straight line segment, the first end of the bending segment is connected to the first straight line segment, the second end of the bending segment is connected to the second straight line segment, the middle portion of the bending segment protrudes in a direction away from the second lead, and the second connecting block is arranged in the area formed by the bending of the bending segment.
  • an orthographic projection of the second connection block on the array substrate at least partially overlaps with an orthographic projection of the gate line on the array substrate.
  • an orthographic projection of the second via hole on the array substrate at least partially overlaps with an orthographic projection of the gate line on the array substrate.
  • the touch electrode in at least one pixel unit, includes an electrode portion and a connecting portion, the electrode portion is disposed in the pixel unit, and the connecting portion is disposed between adjacent pixel units and connected to the electrode portion in the adjacent pixel units.
  • the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the gate line on the array substrate, the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the first lead on the array substrate, and the orthographic projection of the electrode portion on the array substrate does not overlap with the orthographic projection of the second lead on the array substrate.
  • the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the gate line on the array substrate
  • the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the first lead on the array substrate
  • the orthographic projection of the connecting portion on the array substrate at least partially overlaps with the orthographic projection of the second lead on the array substrate.
  • connection portion in at least one pixel unit, is connected to the first lead through a first via hole, or at least one connection portion is connected to the second lead through a second via hole.
  • the array substrate further includes a binding area located on one side of the display area and an upper frame area located on a side of the display area away from the binding area; the binding area includes at least a plurality of pins, and the upper frame area includes at least a test circuit, the test circuit is connected to the plurality of pins of the binding area via a plurality of connecting lines, and the test circuit is configured to detect a short circuit defect of the array substrate.
  • the test circuit includes a plurality of test units corresponding to the positions of a plurality of touch columns; at least one test unit includes a first test line, a second test line, a switch control line, a first switch, and a second switch; the first test line is connected to a first lead in the display area through the first switch, the second test line is connected to a second lead in the display area through the second switch, and the switch control line is connected to control ends of the first switch and the second switch; the first test line is configured to transmit a first grayscale voltage to the first lead under the control of the switch control line, and the second test line is configured to transmit a second grayscale voltage to the second lead under the control of the switch control line; a voltage value of the first grayscale voltage is greater than a voltage value of the second grayscale voltage, or a voltage value of the first grayscale voltage is less than a voltage value of the second grayscale voltage.
  • the test unit further includes a first data lead, a second data lead, a third data lead,
  • the first data lead is connected to the data line of the first sub-pixel in the display area through the third switch
  • the second data lead is connected to the data line of the second sub-pixel in the display area through the fourth switch
  • the third data lead is connected to the data line of the third sub-pixel in the display area through the fifth switch
  • the switch control line is connected to the control ends of the third switch, the fourth switch and the fifth switch
  • the first data lead, the second data lead and the third data lead are configured to transmit a common reference voltage to the data lines in the display area under the control of the switch control line.
  • the present disclosure further provides a display device, comprising the aforementioned array substrate.
  • the present disclosure further provides a method for detecting an array substrate using the aforementioned array substrate, comprising:
  • a first grayscale voltage is provided to a first lead in the display area so that a plurality of touch electrodes connected to the first lead in the display area have the first grayscale voltage;
  • a second grayscale voltage is provided to a second lead in the display area so that a plurality of touch electrodes connected to the second lead in the display area have the second grayscale voltage;
  • a voltage value of the first grayscale voltage is greater than a voltage value of the second grayscale voltage, or a voltage value of the first grayscale voltage is less than a voltage value of the second grayscale voltage.
  • the touch electrodes in one touch row display a first gray scale
  • the touch electrodes in an adjacent touch row display a second gray scale
  • the display area presents a display screen with alternating light and dark vertically
  • at least one touch electrode in one touch row and at least one touch electrode in an adjacent touch row display the same gray scale.
  • FIG1 is a schematic cross-sectional view of a liquid crystal display device
  • FIG2 is a schematic diagram of a planar structure of a liquid crystal display device
  • FIG3 is a schematic diagram of a planar structure of an array substrate
  • FIG4 is a schematic diagram of the structure of a touch panel in a box
  • FIG5 is a schematic diagram of a planar structure of an array substrate according to an exemplary embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a planar structure of a display area according to an exemplary embodiment of the present disclosure.
  • FIG7a is an enlarged view of area A in FIG6 ;
  • FIG7 b is an enlarged view of area B in FIG6 ;
  • FIGS. 8a and 8b are schematic diagrams of the array substrate of the present disclosure after the first conductive layer pattern is formed;
  • 9a and 9b are schematic diagrams of the array substrate of the present disclosure after a semiconductor layer pattern is formed
  • 10a and 10b are schematic diagrams of the array substrate of the present disclosure after forming a second conductive layer pattern
  • FIG. 11a and 11b are schematic diagrams of the array substrate of the present disclosure after forming a second insulating layer pattern
  • 12a and 12b are schematic diagrams of the array substrate of the present disclosure after the third conductive layer pattern is formed;
  • FIG. 13a and 13b are schematic diagrams of the array substrate of the present disclosure after a third insulating layer pattern is formed;
  • FIG14 is a schematic diagram of the planar structure of the binding area and the frame area in the array substrate of the present disclosure.
  • 15 to 19 are schematic diagrams of a test circuit for preparing an array substrate according to the present disclosure.
  • 20 and 21 are schematic diagrams of the detection circuit of the present disclosure performing short circuit detection
  • FIG. 22 is a schematic diagram of the detection timing when the detection circuit of the present invention performs short-circuit detection.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the array substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • connection includes the case where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function There is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • Liquid crystal display has the characteristics of small size, low power consumption and no radiation, and has been widely used.
  • the liquid crystal array substrate includes a thin film transistor array (TFT) substrate and a color filter (CF) substrate of a cell.
  • Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate.
  • the electric field that drives the liquid crystal deflection is formed by controlling the common electrode and the pixel electrode to realize grayscale display.
  • FIG1 is a schematic diagram of a cross-sectional structure of a liquid crystal display device.
  • the liquid crystal display device may include a first substrate A1 and a second substrate A2 disposed opposite to each other, and a liquid crystal layer A3 disposed between the first substrate A1 and the second substrate A2, the first substrate A1 may include a first structural layer A1-2 disposed on the side of the first substrate A1-1 facing the second substrate A2, and the second substrate A2 may include a second structural layer A2-2 disposed on the side of the second substrate A2-1 facing the first substrate A1.
  • the liquid crystal display device can be divided into a twisted nematic (TN) display mode, an in-plane switching (IPS) display mode, a fringe field switching (FFS) display mode, and an advanced super-dimensional field switching (ADS) display mode.
  • TN twisted nematic
  • IPS in-plane switching
  • FFS fringe field switching
  • ADS advanced super-dimensional field switching
  • the first structural layer A1-2 may include a gate line, a data line, a thin film transistor, a pixel electrode, and a common electrode
  • the second structural layer A2-2 may include a black matrix and a filter unit.
  • FIG2 is a schematic diagram of a planar structure of a liquid crystal display device.
  • the liquid crystal display device may include a plurality of pixel units 60 arranged in a matrix manner, at least one of the plurality of pixel units 60 may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the three sub-pixels may each include a thin film transistor, a pixel electrode, and a common electrode.
  • the first sub-pixel P1 may be a red sub-pixel emitting a red (R) light
  • the second sub-pixel P2 may be a green sub-pixel emitting a green (G) light
  • the third sub-pixel P3 may be a blue sub-pixel emitting a blue (B) light.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon, etc., and the sub-pixels in the pixel unit may be arranged in horizontal parallel, vertical parallel, or in a triangular manner.
  • the pixel unit may include four sub-pixels, which are not limited in the present disclosure.
  • FIG3 is a schematic diagram of a planar structure of an array substrate.
  • the array substrate may include a display area and a frame area
  • the display area may include a plurality of gate lines (S1 to Sm) and a plurality of data lines (D1 to Dn)
  • the plurality of gate lines may extend in a horizontal direction and be arranged in sequence in a vertical direction
  • the plurality of data lines may extend in a vertical direction and be arranged in sequence in a horizontal direction
  • the plurality of gate lines and the plurality of data lines intersecting each other define a plurality of sub-pixels Pxij arranged regularly
  • m, n, i and j may be natural numbers.
  • at least one sub-pixel Pxij may include a thin film transistor, a pixel electrode and a common electrode, and the thin film transistor is connected to the gate line, the data line and the pixel electrode, respectively.
  • the array substrate may further include a plurality of common electrode lines (E1 to Eo), the plurality of common electrode lines may extend in the horizontal direction and be arranged in sequence in the vertical direction, or the plurality of common electrode lines may extend in the vertical direction and be arranged in sequence in the horizontal direction, and the plurality of common electrode lines are correspondingly connected to the common electrodes in the plurality of sub-pixels Pxij.
  • E1 to Eo common electrode lines
  • a plurality of gate lines are connected to the scan driver, a plurality of data lines are connected to the data driver, and at least a portion of the scan driver and the data driver may be formed on an array substrate.
  • an external control device may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and the data driver may generate a data voltage to be provided to the data lines D1, D2, D3, ... and Dn using the received grayscale value and control signal.
  • the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of pixel rows.
  • the external control device may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and the scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ...
  • the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm.
  • the scan driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal.
  • the liquid crystal display device with integrated touch function mainly includes an On Cell structure and an In Cell structure.
  • the On Cell structure generally sets the touch structure on the side of the color filter substrate away from the array substrate
  • the In Cell structure generally sets the touch structure in the first structural layer of the array substrate.
  • the In Cell structure can realize the thinness of the liquid crystal display device.
  • the In Cell structure is mainly divided into a mutual capacitance structure and a self capacitance structure.
  • the mutual capacitance structure is formed by the overlapping or close proximity of the driving electrode and the sensing electrode to form a mutual capacitance, and the change of the mutual capacitance is used for position detection.
  • the self capacitance structure is formed by the touch electrode and the human body to form a self capacitance, and the change of the self capacitance is used for position detection.
  • the self capacitance structure is a single-layer structure with the characteristics of low power consumption and simple structure.
  • FIG4 is a schematic diagram of the structure of an in-cell touch panel.
  • the in-cell touch panel (In-Cell Touch LCD) may include a plurality of regularly arranged touch electrodes 50 and a plurality of touch leads (also called sensing signal lines, Tx signal lines) 50A, each touch electrode 50 is connected to a touch driving circuit via a touch lead 50A. Touching will cause the self-capacitance of the corresponding touch electrode 50 to change, and the touch driving circuit determines the specific position of the finger according to the capacitance change of the touch electrode 50.
  • the in-box touch panel uses a common electrode layer that provides a common voltage as a touch layer, and the common electrode layer is "divided" to form block-shaped touch electrodes 50 as shown in FIG. 4.
  • the shape of the touch electrode can be a rectangle, a diamond, a triangle, or a polygon, etc., which is not limited in the present disclosure.
  • the in-box touch panel shown in FIG4 adopts a time-sharing driving mode, and the driving signals of the display period and the touch period are processed separately.
  • the data line is supplied with display signals by the data driver, the touch electrodes are multiplexed as common electrodes, the touch signal lines are multiplexed as common electrode lines, the touch signal lines provide common voltages to the touch electrodes, and no touch signal scanning is performed to ensure normal display.
  • the touch driving circuit performs touch signal scanning through the touch signal line. At this time, one frame of display has been completed, and the display state is basically not affected by the touch signal, and the two work independently in time-sharing.
  • a touch electrode may be a rectangle of approximately 4*4mm or 5*5mm, may cover a plurality of sub-pixels, and may be controlled by a touch lead, which may be disposed between adjacent sub-pixels. Since a touch electrode covers a plurality of sub-pixels, the number of touch leads is much smaller than the number of sub-pixels covered by the touch electrode.
  • conventional array substrates usually have leads disposed between each adjacent sub-pixel, and a portion of these leads are used as touch leads for controlling the touch electrodes, and the rest are dummy lines, which have no signal input.
  • the resolution of a display device is related to the pixel aperture ratio of the array substrate.
  • touch leads or dummy lines are set between adjacent sub-pixels of the existing array substrate, a large number of dummy lines occupy the space of the sub-pixels. Therefore, the existing array substrate has problems such as low pixel aperture ratio, which affects the improvement of the resolution of the display device.
  • An exemplary embodiment of the present disclosure provides an array substrate, comprising a display area, wherein the display area at least comprises: a plurality of touch electrodes constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units constituting a plurality of pixel rows and a plurality of pixel columns, wherein an orthographic projection of the touch unit on the array substrate at least partially overlaps with an orthographic projection of a plurality of pixel units on the array substrate, and the pixel unit comprises a plurality of sub-pixels; a touch lead group is arranged between at least one adjacent pixel column, the touch lead group comprises at least a first lead and a second lead arranged in parallel, the first lead being connected to a touch electrode in a touch row, and the second lead being connected to another touch electrode in an adjacent touch row.
  • At least one touch column includes N touch electrodes arranged in sequence along the pixel column direction, the orthographic projection of the touch column on the array substrate at least partially overlaps with the orthographic projection of N/2 pixel columns on the array substrate, a first lead located between the i-th pixel column and the i+1-th pixel column is connected to the touch electrode in the 2i-1-th touch row, and a second lead located between the i-th pixel column and the i+1-th pixel column is connected to the touch electrode in the 2i-th touch row, N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N/2.
  • At least one pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along the pixel row direction, the sub-pixels include a gate line, a data line, a thin film transistor and a pixel electrode, the thin film transistor is respectively connected to the gate line, the data line and the pixel electrode, the touch electrode is multiplexed as a common electrode, the first lead and the second lead are multiplexed as a common electrode line; the first lead is arranged on a side of the third sub-pixel away from the first sub-pixel, and the second lead is arranged on a side of the first lead away from the first sub-pixel.
  • the array substrate further includes a binding area located on one side of the display area and an upper frame area located on a side of the display area away from the binding area; the binding area includes at least a plurality of pins, and the upper frame area includes at least a test circuit, the test circuit is connected to the plurality of pins of the binding area via a plurality of connecting lines, and the test circuit is configured to detect a short circuit defect of the array substrate.
  • the test circuit includes a plurality of test units, the plurality of test units and the plurality of touch columns. corresponding to the position; at least one test unit includes a first test line, a second test line, a switch control line, a first switch and a second switch; the first test line is connected to the first lead in the display area through the first switch, the second test line is connected to the second lead in the display area through the second switch, and the switch control line is connected to the control ends of the first switch and the second switch; the first test line is configured to transmit a first grayscale voltage to the first lead under the control of the switch control line, and the second test line is configured to transmit a second grayscale voltage to the second lead under the control of the switch control line; the voltage value of the first grayscale voltage is greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage is less than the voltage value of the second grayscale voltage.
  • the test unit further includes a first data lead, a second data lead, a third data lead, a third switch, a fourth switch and a fifth switch
  • the first data lead is connected to the data line of the first sub-pixel in the display area through the third switch
  • the second data lead is connected to the data line of the second sub-pixel in the display area through the fourth switch
  • the third data lead is connected to the data line of the third sub-pixel in the display area through the fifth switch
  • the switch control line is connected to control ends of the third switch, the fourth switch and the fifth switch
  • the first data lead, the second data lead and the third data lead are configured to transmit a common reference voltage to the data lines of the display area under the control of the switch control line.
  • FIG5 is a schematic diagram of a planar structure of an array substrate of an exemplary embodiment of the present disclosure.
  • the array substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area, including a plurality of pixel units constituting a pixel array and a plurality of touch electrodes constituting a touch array, the plurality of pixel units being configured to display dynamic images or still images, and the plurality of touch electrodes being configured to implement touch control.
  • the display area 100 may be referred to as an active area (AA).
  • the binding area 200 may include at least a fan-out area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area.
  • the fan-out area may be connected to the display area 100, and may include at least a data transmission line and a touch transmission line.
  • a plurality of data transmission lines are configured to connect the data lines of the display area in a fan-out routing manner, and a plurality of touch transmission lines are configured to connect the touch routing lines of the display area.
  • the driver chip area may be connected to the fan-out area, and may include at least an integrated circuit (IC), which is configured to be connected to a plurality of data transmission lines and a plurality of touch transmission lines.
  • the binding pin area may be connected to the driver chip area, and may include at least a plurality of pins (PINs), which are configured to be bound and connected to an external flexible printed circuit (FPC).
  • PINs pins
  • the frame area 300 may include an upper frame area 310 located on one side of the display area 100 away from the binding area 200 and side frame areas 320 located on both sides of the display area 100.
  • the upper frame area 310 may include at least a test circuit, the test circuit is connected to a plurality of data lines and touch lines in the display area, and the test circuit is configured to detect a short circuit failure of the array substrate.
  • the side frame area 320 may include a circuit area and a lead area sequentially arranged in a direction away from the display area 100.
  • the circuit area may be connected to the display area 100, and may include at least a plurality of cascaded gate drive circuits (GOA), and the gate drive circuit is connected to a plurality of gate lines in the display area 100.
  • GOA cascaded gate drive circuits
  • the lead area may be connected to the circuit area, and may include at least a plurality of connecting lines, the first ends of the plurality of connecting lines may be connected to a plurality of pins of the binding area 200, and the second ends of the plurality of connecting lines may be connected to the test circuit of the upper frame area 310, so that an external test device transmits a test signal to the test circuit through the plurality of connecting lines.
  • FIG6 is a schematic diagram of a planar structure of a display area of an exemplary embodiment of the present disclosure.
  • the display area of the array substrate may at least include a plurality of touch electrodes 50 constituting a plurality of touch rows and a plurality of touch columns and a plurality of pixel units 60 constituting a plurality of pixel rows and a plurality of pixel columns, wherein the plurality of pixel units 60 constitute a pixel array configured to display dynamic images or still images, and the plurality of touch electrodes 50 constitute a touch array configured to implement touch control.
  • Each touch row may include a plurality of touch electrodes 50 sequentially arranged along a first direction X, and the plurality of touch rows may be spaced apart along a second direction Y, and each touch column may include a plurality of touch electrodes 50 sequentially arranged along the second direction Y, and the plurality of touch columns may be spaced apart along the first direction X.
  • Each pixel row may A plurality of pixel units 60 are sequentially arranged along a first direction X, a plurality of pixel rows may be spaced apart along a second direction Y, each pixel column may include a plurality of pixel units 60 sequentially arranged along the second direction Y, and a plurality of pixel columns may be spaced apart along the first direction X.
  • the first direction X intersects the second direction Y.
  • the orthographic projection of at least one touch electrode 50 on the array substrate may include the orthographic projections of multiple pixel units 60 on the array substrate, that is, one touch electrode 50 may cover multiple pixel units 60, and the pixel unit 60 may include multiple sub-pixels.
  • the display area may include N touch rows, that is, one touch column may include N touch electrodes 50 sequentially arranged along the second direction Y.
  • the orthographic projection of at least one touch column on the array substrate at least partially overlaps with the orthographic projection of N/2 pixel columns on the array substrate, that is, the positions of the N touch electrodes 50 of one touch column may correspond to the positions of the plurality of pixel units 60 of N/2 pixel columns, where N is an even number greater than 1.
  • a touch lead group is disposed between at least one adjacent pixel column.
  • the touch lead group may include a first lead 61 and a second lead 62.
  • the first lead 61 and the second lead 62 may be in the shape of a line extending along the second direction Y (pixel column direction), and the second lead 62 may be disposed on one side of the first lead 61 in the first direction X (pixel row direction).
  • the first lead 61 and the second lead 62 located between the i-th pixel column and the i+1-th pixel column can be connected to the touch electrode 50 in the 2i-1-th touch row, and the second lead 62 can be connected to the touch electrode 50 in the 2i-th touch row, where i is a positive integer greater than or equal to 1 and less than or equal to N/2.
  • the plurality of second leads 62 are connected to the touch electrodes 50 in the even-numbered touch rows.
  • the plurality of second leads 62 are connected to the touch electrodes 50 in the odd-numbered touch rows.
  • the touch column corresponds to N/2 pixel columns.
  • the first lead 61 and the second lead 62 between the first pixel column and the second pixel column the first lead 61 is connected to the first touch electrode 50 of the touch column (the touch electrode 50 of the first touch row), and the second lead 62 is connected to the second touch electrode 50 of the touch column (the touch electrode 50 of the second touch row).
  • the first lead 61 and the second lead 62 between the second pixel column and the third pixel column the first lead 61 is connected to the third touch electrode 50 of the touch column (the touch electrode 50 of the third touch row), and the second lead 62 is connected to the fourth touch electrode 50 of the touch column (the touch electrode 50 of the fourth touch row).
  • the first lead 61 and the second lead 62 between the (N/2)th pixel column and the (N/2+1)th pixel column the first lead 61 is connected to the (N-1)th touch electrode 50 of the touch column (the touch electrode 50 of the (N-1)th touch row), and the second lead 62 is connected to the (N)th touch electrode 50 of the touch column (the touch electrode 50 of the (N)th touch row).
  • the (N/2+1)th pixel column is the first pixel column corresponding to the second touch column.
  • one pixel unit 60 may include 3 sub-pixels or may include 4 sub-pixels. Taking the example that the pixel unit 60 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along the first direction X, the first lead 61 and the second lead 62 may be arranged between the third sub-pixel of the i-th pixel column and the first sub-pixel of the i+1-th pixel column, while neither the first lead nor the second lead is arranged between the first sub-pixel and the second sub-pixel, and between the second sub-pixel and the third sub-pixel in each pixel column.
  • the display area may include a plurality of touch columns, and the structures of each touch column and the corresponding plurality of pixel columns may be the same as the first touch column.
  • the array substrate may include a base and a plurality of conductive layers disposed on the base, the first lead 61 and the second lead 62 may be disposed in the same conductive layer, the touch electrode 50 may be disposed in another conductive layer, and the first lead 61 and the second lead 62 may be connected to the touch electrode 50 through a via.
  • the leads are usually arranged between each adjacent sub-pixel, that is, one including three sub-pixels
  • Three leads are set in the pixel unit, some of which are used as touch leads and others as dummy lines. Since each lead occupies the space of a sub-pixel, the array substrate of this structure has problems such as low pixel aperture ratio, which affects the improvement of the resolution of the display device.
  • the array substrate provided by the exemplary embodiment of the present disclosure sets two touch leads between adjacent pixel units, so that one pixel unit only includes two touch leads.
  • the present disclosure not only reduces the number of leads, increases the space of the sub-pixel, improves the pixel aperture ratio, and improves the light transmittance of the array substrate, which is beneficial to the improvement of the resolution of the display device, but also because each lead is connected to the corresponding touch electrode through a via, the consistency of the pixel structure and the uniformity of etching are guaranteed, which is beneficial to improving the quality of the preparation process.
  • the touch lead group may include three touch leads or a plurality of touch leads. Since the existing array substrate sets the three leads respectively between the sub-pixels, and the present disclosure sets the three touch leads between adjacent pixel units, it can also increase the space of the sub-pixels, improve the pixel aperture ratio, and help improve the resolution of the display device. For another example, two pixel units or multiple pixel units can be used as a repeating unit, and the touch lead group can be set between adjacent repeating units. The present disclosure does not limit this.
  • Fig. 7a is an enlarged view of the A region in Fig. 6, and Fig. 7b is an enlarged view of the B region in Fig. 6.
  • the pixel units in the A region are pixel units in the m1-th pixel row and the n-th pixel column
  • the pixel units in the B region are pixel units in the m2-th pixel row and the n-th pixel column.
  • the pixel units in the A region and the pixel units in the B region both include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 sequentially arranged along the first direction X.
  • the display area of the array substrate may include at least a plurality of gate lines 20 and a plurality of data lines 30, the gate lines 20 may be in the shape of a line extending along a first direction X, the plurality of gate lines 20 may be arranged in sequence along a second direction Y, the data lines 30 may be in the shape of a line extending along the second direction Y, the plurality of data lines 30 may be arranged in sequence along the first direction X, the plurality of gate lines 20 and the plurality of data lines 30 intersecting each other define a plurality of regularly arranged sub-pixels, a thin film transistor and a pixel electrode are provided in each sub-pixel, and the thin film transistor may be connected to the gate lines 20, the data lines 30 and the pixel electrode, respectively.
  • the display area of the array substrate may further include a plurality of touch lead groups multiplexed as common electrode lines, and a plurality of touch electrodes 50 multiplexed as common electrodes.
  • the touch lead groups may be arranged between adjacent pixel units in the first direction X, and at least one touch lead group may include at least a first lead 61 and a second lead 62 arranged in parallel, and the first lead 61 and the second lead 62 are respectively connected to corresponding touch electrodes 50.
  • the thin film transistor in each sub-pixel is configured to receive the data voltage transmitted by the data line 30 and output it to the pixel electrode under the control of the gate line 20, control the electric field formed between the pixel electrode and the common electrode to drive the liquid crystal deflection, and realize grayscale display.
  • the first lead 61 and the second lead 62 may be in the shape of a zigzag line extending along the second direction Y.
  • the first lead 61 may be connected to one touch electrode 50 through the first via K1.
  • the second lead 62 may be connected to another touch electrode 50 through the second via K2.
  • a first connection block 61 - 1 may be disposed on the first lead 61 , and the first connection block 61 - 1 may be connected to the corresponding touch electrode 50 through the first via hole K1 .
  • the first lead 61 may include a first straight line segment, a second straight line segment, and a bending segment located between the first straight line segment and the second straight line segment, the first end of the bending segment is connected to the first straight line segment, the second end of the bending segment is connected to the second straight line segment, the middle portion of the bending segment may protrude in a direction away from the second lead 62, and the first connecting block 61-1 may be disposed on a side of the bending segment close to the second lead 62, that is, the first connecting block 61-1 may be disposed in the area formed by the bending of the bending segment.
  • a second connection block 62 - 1 may be disposed on the second lead 62 , and the second connection block 62 - 1 may be connected to another touch electrode 50 through a second via hole K2 .
  • the first lead 61 may include a first straight line segment, a second straight line segment, and a bending segment located between the first straight line segment and the second straight line segment, the first end of the bending segment is connected to the first straight line segment, the second end of the bending segment is connected to the second straight line segment, and the middle portion of the bending segment may protrude in a direction away from the second lead 62, so that the second connecting block 62-1 may be set in the area formed by the bending of the bending segment.
  • the orthographic projection of the first connection block 61 - 1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate
  • the orthographic projection of the second connection block 62 - 1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate.
  • the touch electrode 50 in at least one pixel unit may include an electrode portion 51 and a connecting portion 52.
  • the electrode portion 51 may be arranged in the pixel unit, and the connecting portion 52 may be arranged between adjacent pixel units and connected to the electrode portion 51 in the adjacent pixel unit, so that multiple electrode portions 51 in multiple pixel units are connected into one.
  • connection portion 52 may be disposed between pixel units adjacent in the first direction X, or the connection portion 52 may be disposed between pixel units adjacent in the second direction Y, or the connection portion 52 may be disposed between pixel units adjacent in the first direction X and between pixel units adjacent in the second direction Y.
  • the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the second lead 62 on the substrate.
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the first lead 61 on the substrate
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the second lead 62 on the substrate.
  • connection portion 52 of one touch electrode 50 is connected to the first lead 61 through the first via hole K1
  • at least one connection portion 52 of another touch electrode 50 is connected to the second lead 62 through the second via hole K2 .
  • the orthographic projection of the first via hole K1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate
  • the orthographic projection of the second via hole K2 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate.
  • At least one opening 53 may be provided on the electrode portion 51 in the pixel unit, and the shape of the opening 53 may be a zigzag shape extending along the second direction Y, so that the electrode portion 51 forms a plurality of strip electrodes spaced apart along the first direction X, which can ensure that a horizontal electric field is formed between the planar pixel electrode 40 and the strip-shaped common electrode (touch electrode).
  • the following is an exemplary description of the preparation process of the array substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the array substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation of the array substrate may include the following operations.
  • forming the first conductive layer pattern may include: A first conductive film is deposited on a substrate, and the first conductive film is patterned through a patterning process to form a first conductive layer pattern on the substrate, wherein the first conductive layer pattern includes at least a gate line 20 and a gate electrode 21, as shown in FIGS. 8a and 8b, wherein FIG. 8a is an enlarged view of area A in FIG. 6, and FIG. 8b is an enlarged view of area B in FIG. 6.
  • the shape of the gate line 20 can be a straight line with a main portion extending along the first direction X, and the gate line 20 of each sub-pixel can be set on one side of the sub-pixel in the second direction Y (a position close to the next row of sub-pixels in the sub-pixel), and the gate line 20 is configured to be connected to the thin film transistor in the sub-pixel to provide a scanning signal to the thin film transistor.
  • the shape of the gate electrode 21 can be rectangular, and the gate electrode 21 can be arranged in each sub-pixel and connected to the gate line 20, which is equivalent to the gate line 20 being widened in the area where the transistor is formed, so that the overlapping area between the gate line 20 and the subsequently formed data line is smaller, which can reduce the parasitic capacitance between the gate line 20 and the data line, and improve the electrical performance of the array substrate.
  • the gate line 20 and the gate electrodes 21 in the plurality of sub-pixels may be an integral structure connected to each other.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor layer film on a substrate having the aforementioned pattern formed thereon, patterning the semiconductor layer film through a patterning process to form a first insulating layer covering the first conductive layer pattern, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 9a and 9b, wherein FIG. 9a is an enlarged view of region A in FIG. 6, and FIG. 9b is an enlarged view of region B in FIG. 6.
  • the semiconductor layer pattern includes at least an active layer 22 disposed in each sub-pixel, and an orthographic projection of the active layer 22 on the substrate may be located within a range of an orthographic projection of the gate electrode 21 on the substrate.
  • the shape and position of the active layer 22 in each sub-pixel may be the same, and the structure of the thin film transistor may be simplified.
  • forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer pattern, as shown in FIGS. 10a and 10b, where FIG. 10a is an enlarged view of region A in FIG. 6, and FIG. 10b is an enlarged view of region B in FIG. 6.
  • the second conductive layer pattern includes at least a source electrode 23 , a drain electrode 24 , a data line 30 , a first lead line 61 , and a second lead line 62 .
  • the data line 30 , the first lead line 61 , and the second lead line 62 may be shaped like a zigzag line with the main portion extending along the second direction Y, and the extension directions of the zigzag lines in the data line 30 , the first lead line 61 , and the second lead line 62 may be substantially the same.
  • a data line 30 is provided in each sub-pixel.
  • the data line 30 can be provided on a side (left side) opposite to the first direction X of each sub-pixel.
  • the data line 30 is configured to be connected to the thin film transistor in the sub-pixel to provide a data signal to the thin film transistor.
  • the source electrode 23 and the drain electrode 24 can be arranged in each sub-pixel, a portion of the data line 30 serves as the source electrode 23 of each sub-pixel, and the drain electrode 24 of each sub-pixel can be a separately arranged "L" shape, the source electrode 23 is connected to the active layer 22, the first end of the drain electrode 24 is connected to the active layer 22, and the second end of the drain electrode 24 extends in a direction away from the active layer 22 and is configured to be connected to a subsequently formed pixel electrode, and a conductive channel is formed between the source electrode 23 and the drain electrode 24.
  • the gate electrode 21 , the active layer 22 , the source electrode 23 and the drain electrode 24 in each sub-pixel constitute a thin film transistor, the gate electrode 21 is connected to the gate line, the source electrode 23 is connected to the data line 30 , and the drain electrode 24 is connected to the pixel electrode.
  • the first lead 61 and the second lead 62 can be arranged between adjacent pixel units in the first direction X, and the first lead 61 and the second lead 62 are configured to be connected to the subsequently formed touch electrodes (multiplexed as common electrodes) to provide touch signals or common voltage signals to the touch electrodes.
  • the first lead 61 and the second lead 62 may be disposed between the n-1th pixel column and the nth pixel column, and between the nth pixel column and the n+1th pixel column.
  • the first lead 61 may be disposed on a side of the third sub-pixel P3 away from the first sub-pixel P1
  • the second lead 62 may be disposed on a side of the first lead 61 away from the first sub-pixel P1.
  • the shape of the first lead 61 between the nth pixel column and the n+1th pixel column is different from the shape of the first lead 61 between other adjacent pixel columns, while the shape of the second lead 62 is basically the same as the shape of the second lead 62 between other adjacent pixel columns.
  • the first lead 61 may include a first straight line segment 61A, a second straight line segment 61B, and a bending segment 61C located between the first straight line segment 61A and the second straight line segment 61B, and a first connecting block 61-1 is provided on the first lead 61, and the first connecting block 61-1 is configured to be connected to a touch electrode formed subsequently through a via.
  • the first end of the bending segment 61C is connected to the first straight segment 61A, and the second end of the bending segment 61C is connected to the second straight segment 61B.
  • the middle portion of the bending segment 61C can protrude in the opposite direction of the first direction X (the direction away from the second lead 62), and the first connecting block 61-1 is arranged on one side of the first direction X (the direction close to the second lead 62) of the bending segment 61C, that is, the first connecting block 61-1 is arranged in the area formed by the bending of the bending segment 61C.
  • first straight segment 61A, the second straight segment 61B, the bent segment 61C, and the first connecting block 61 - 1 may be an integral structure connected to each other.
  • the orthographic projection of the bending section 61C on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate
  • the orthographic projection of the first connecting block 61-1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, so that the connection point between the first lead 61 and the touch electrode is located in the non-opening area of the sub-pixel to increase the opening ratio of the sub-pixel.
  • the shape of the first lead 61 between the n-th pixel column and the n+1-th pixel column is different from the shape of the first lead 61 between other adjacent pixel columns
  • the shape of the second lead 62 is different from the shape of the second lead 62 between other adjacent pixel columns.
  • the second lead 62 may be provided with a second connection block 62-1, and the second connection block 62-1 is configured to be connected to another touch electrode formed subsequently through a via hole.
  • the second connection block 62-1 may be provided on one side of the second lead 62 in the opposite direction of the first direction X (toward the direction of the first lead 61), and the shape of the second connection block 62-1 may be a trapezoid protruding toward the first lead 61.
  • the first lead 61 may include a first straight segment 61A, a second straight segment 61B, and a bent segment 61C located between the first straight segment 61A and the second straight segment 61B.
  • a first end of the bent segment 61C is connected to the first straight segment 61A
  • a second end of the bent segment 61C is connected to the second straight segment 61B
  • a middle portion of the bent segment 61C may protrude in the opposite direction of the first direction X, so that the second connection block 62-1 may be disposed in the region formed by the bending of the bent segment 61C.
  • the orthographic projection of the second connection block 62-1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, so that the connection point between the second lead 61 and the touch electrode is located in the non-opening area of the sub-pixel to improve the aperture ratio of the sub-pixel.
  • first straight segment 61A, the second straight segment 61B, and the bent segment 61C may be an integral structure connected to each other.
  • the second lead 62 and the second connection block 62 - 1 may be an integral structure connected to each other.
  • the shapes of the first straight line segment 61A, the second straight line segment 61B and the bent segment 61C in the m1th pixel row and the m2th pixel row may be substantially the same.
  • forming the second insulating layer pattern may include: depositing a second insulating film on the substrate having the aforementioned pattern, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the second conductive pattern, and forming a plurality of vias on the second insulating layer, as shown in FIG. 11a and 11b, FIG11a is an enlarged view of the A region in FIG6, and FIG11b is an enlarged view of the B region in FIG6.
  • the plurality of via holes may include at least a connection via hole K disposed in each sub-pixel.
  • the orthographic projection of the connection via hole K on the substrate may be located within the range of the orthographic projection of the drain electrode 24 on the substrate, the second insulating layer in the connection via hole K is etched away to expose the surface of the drain electrode 24, and the connection via hole K is configured to connect a subsequently formed pixel electrode to the drain electrode 24 through the via hole.
  • the shape of the connection via K may be any one or more of the following: square, rectangular, circular, and elliptical.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIGS. 12a and 12b, wherein FIG. 12a is an enlarged view of region A in FIG. 6, and FIG. 12b is an enlarged view of region B in FIG. 6.
  • the third conductive layer pattern may include at least a pixel electrode 40 disposed in each sub-pixel.
  • the shape of the pixel electrode 40 in each sub-pixel can be a solid surface, located in the area surrounded by the gate line 20 and the data line 30, and the positive projection of the pixel electrode 40 on the substrate at least partially overlaps with the positive projection of the drain electrode 24 on the substrate, and the pixel electrode 40 is connected to the drain electrode 24 of the thin film transistor through a connecting via K.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the third conductive pattern, wherein a plurality of vias are formed on the third insulating layer, as shown in FIGS. 13a and 13b, wherein FIG. 13a is an enlarged view of region A in FIG. 6, and FIG. 13b is an enlarged view of region B in FIG. 6.
  • the plurality of via holes may include at least a first via hole K1 disposed in an m1-th pixel row and an n-th pixel column and a second via hole K2 disposed in an m2-th pixel row and an n-th pixel column.
  • the orthographic projection of the first via K1 on the substrate can be located within the range of the orthographic projection of the first connecting block 61-1 of the first lead 61 on the substrate, the second insulating layer and the third insulating layer in the first via K1 are etched away to expose the surface of the first connecting block 61-1, and the first via K1 is configured to connect a subsequently formed touch electrode to the first connecting block 61-1 through the via.
  • the orthographic projection of the first via hole K1 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, so that the connection point between the first lead 61 and the touch electrode is located in the non-opening area of the sub-pixel to improve the aperture ratio of the sub-pixel.
  • the orthographic projection of the second via K2 on the substrate can be located within the range of the orthographic projection of the second connecting block 62-1 of the second lead 62 on the substrate, the second insulating layer and the third insulating layer in the second via K2 are etched away to expose the surface of the second connecting block 62-1, and the second via K2 is configured to connect another touch electrode formed subsequently to the second connecting block 62-1 through the via.
  • the orthographic projection of the second via hole K2 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate, so that the connection point between the second lead 62 and the touch electrode is located in the non-opening area of the sub-pixel to improve the aperture ratio of the sub-pixel.
  • the shapes of the first via hole K1 and the second via hole K2 may be any one or more of the following: square, rectangular, circular, and elliptical.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film through a patterning process, and forming the fourth conductive layer pattern on the third insulating layer, as shown in FIGS. 7a and 7b.
  • the fourth conductive layer pattern includes at least a plurality of regularly arranged touch electrodes 50 , and the plurality of touch electrodes 50 are multiplexed as a common electrode.
  • the touch electrode 50 covering the m1-th pixel row and the n-th pixel column passes through the first via hole.
  • K1 is connected to the first connection block 61 - 1 . Since the first connection block 61 - 1 is connected to the first lead 61 , the first lead 61 is connected to a touch electrode 50 .
  • the first lead 61 can provide a touch signal or a common voltage signal to the touch electrode 50 .
  • the touch electrode 50 covering the m2-th pixel row and the n-th pixel column is connected to the second connection block 62-1 through the second via K2. Since the second connection block 62-1 is connected to the second lead 62, the connection between the second lead 62 and another touch electrode 50 is realized, and the second lead 62 can provide a touch signal or a common voltage signal to the touch electrode 50.
  • the touch electrode 50 may include an electrode portion 51 and a connection portion 52, and the electrode portion 51 may be disposed in the pixel unit, that is, the electrode portion 51 may be disposed in a region surrounded by the first lead 61, the second lead 62, and the two gate lines 20.
  • the connection portion 52 may be disposed between adjacent pixel units and connected to the electrode portion 51 in the adjacent pixel unit, so that the plurality of electrode portions 51 in the plurality of pixel units are connected into one body to form a block-shaped touch electrode 50.
  • the connecting portion 52 may be disposed between pixel units adjacent in the first direction X to connect multiple electrode portions 51 in one pixel row as a whole, or the connecting portion 52 may be disposed between pixel units adjacent in the second direction Y to connect multiple electrode portions 51 in one pixel column as a whole, or the connecting portion 52 may be disposed between pixel units adjacent in the first direction X and between pixel units adjacent in the second direction Y to connect multiple electrode portions 51 in multiple pixel rows and multiple pixel columns as a whole.
  • the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the gate line 20 on the substrate, the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the first lead 61 on the substrate, and the orthographic projection of the electrode portion 51 on the substrate does not overlap with the orthographic projection of the second lead 62 on the substrate, so as to reduce the influence of the signals transmitted by the gate line 20, the first lead 61 and the second lead 62 on the touch electrode (common electrode).
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the gate line 20 on the substrate
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the first lead 61 on the substrate
  • the orthographic projection of the connecting portion 52 on the substrate at least partially overlaps with the orthographic projection of the second lead 62 on the substrate.
  • connection portion 52 of a touch electrode 50 can be connected to the first connection block 61-1 through a first via hole K1
  • at least one connection portion 52 of another touch electrode 50 can be connected to the second connection block 62-1 through a second via hole K2 so that the connection points of the first lead 61 and the second lead 62 with the touch electrodes are both located in the non-opening area of the sub-pixel to improve the opening ratio of the sub-pixel.
  • At least one opening 53 may be provided on the electrode portion 51 in the pixel unit, and the fourth conductive film in the opening 53 is etched away to expose the third insulating layer.
  • the opening 53 may be in the shape of a folded line extending along the second direction Y, so that the electrode portion 51 forms a plurality of strip electrodes spaced apart along the first direction X, which can ensure that a horizontal electric field is formed between the planar pixel electrode 40 and the strip common electrode (touch electrode).
  • the substrate may be made of glass or quartz.
  • the first conductive layer and the second conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the first conductive layer may be called a gate metal (GATE) layer
  • the second conductive layer may be called a source-drain metal (SD) layer.
  • the third conductive layer and the fourth conductive layer may be made of transparent conductive materials, such as indium tin oxide ITO or indium zinc oxide IZO, etc.
  • the first insulating layer, the second insulating layer and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be called a gate insulating (GI) layer
  • the second insulating layer may be called an interlayer insulating layer (ILD)
  • the third insulating layer may be called a passivation (PVX) layer.
  • the active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene or polythiophene and the like that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the array substrate may include a first conductive layer disposed on a substrate, a first insulating layer disposed on a side of the first conductive layer away from the substrate, a semiconductor layer disposed on a side of the first insulating layer away from the substrate, a second conductive layer disposed on a side of the semiconductor layer away from the substrate, a second insulating layer disposed on a side of the second conductive layer away from the substrate, a third conductive layer disposed on a side of the second insulating layer away from the substrate, a fourth insulating layer disposed on a side of the third conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the fourth insulating layer away from the substrate.
  • the array substrate may include a plurality of sub-pixels, each of which may include a thin film transistor, a pixel electrode, and a touch electrode multiplexed as a common electrode
  • the thin film transistor may include a gate electrode, an active layer, a first electrode, and a second electrode, the gate electrode is connected to a gate line, the first electrode is connected to a data line, the second electrode is connected to a pixel electrode, the touch electrode is connected to a first lead or a second lead, and a horizontal electric field is formed between the pixel electrode and the common electrode.
  • the touch lead group may include a first lead and a second lead set in parallel. This not only reduces the number of leads, increases the space for sub-pixels, and improves the pixel aperture ratio, which is beneficial to improving the resolution of the display device, but also because each lead is connected to the corresponding touch electrode through a via hole, the consistency of the pixel structure and the uniformity of etching are guaranteed, which is beneficial to improving the quality of the preparation process.
  • Fig. 14 is a schematic diagram of a planar structure of a binding area and a frame area of an exemplary embodiment of the present disclosure.
  • the array substrate may include a display area 100, a binding area 200 located on one side of the display area 100, an upper frame area 310 located on a side of the display area 100 away from the binding area 200, and side frame areas 320 located on both sides of the display area 100.
  • the display area 100 may include at least a plurality of touch electrodes 50 constituting a touch array and a plurality of pixel units 60 constituting a pixel array, at least one pixel unit 60 may include three sub-pixels, at least one sub-pixel may include a thin film transistor 10, a gate line 20, a data line 30 and a pixel electrode 40, the thin film transistor 10 is respectively connected to the gate line 20, the data line 30 and the pixel electrode 40, and the touch electrode 50 may be reused as a common electrode.
  • the display area 100 may further include a plurality of touch lead groups, and the plurality of touch lead groups are respectively arranged between adjacent pixel columns.
  • At least one touch lead group may include at least a first lead 61 and a second lead 62 arranged in parallel.
  • the first lead 61 and the second lead 62 are multiplexed as a common electrode line.
  • the first lead 61 may be connected to the touch electrodes 50 in odd-numbered touch rows, and the second lead 62 may be connected to the touch electrodes 50 in even-numbered touch rows.
  • the binding area 200 may include at least a driver chip 280 and a plurality of pins.
  • the driver chip 280 may be connected to a plurality of data lines and a plurality of touch leads (first leads and second leads) in the display area through a plurality of connection lines.
  • the driver chip 280 is configured to provide data signals and touch signals to the plurality of data lines and the plurality of touch leads, respectively.
  • the plurality of pins of the binding area 200 may include at least one or more of the following: a first test pin 210, a second test pin 220, a first data pin 230, a second data pin 240, a third data pin 250, a switch control pin 260, and a gate line control pin 270.
  • the plurality of pins are configured to be bound and connected with an external test device, so that the external test device outputs corresponding signals to corresponding signal lines.
  • the first test pin 210, the first data pin 230, the switch control pin 260 and the gate line control pin 270 can be set on the side of the binding area 200 in the opposite direction of the first direction X, and the second test pin 220, the second data pin 240, the third data pin 250 and the gate line control pin 270 can be set on the side of the first direction X of the binding area 200.
  • the first test pin 210, the first data pin 230, the switch control pin 260 and the gate line control pin 270 can be arranged in sequence along the first direction X
  • the gate line control pin 270, the second data pin 240, the third data pin 250 and the second test pin 220 can be arranged in sequence along the first direction X.
  • the upper frame area 310 may include at least a test circuit.
  • the disclosed array substrate sets the touch lead group between adjacent pixel units. Multiple leads in the touch lead group are adjacent. When the process or dust (Particle) causes the adjacent leads to short circuit, it may cause abnormal touch function. Defective components are screened out.
  • the present disclosure sets a test circuit in the upper frame area 310 , and the test circuit is configured to detect short circuit defects of the array substrate.
  • the test circuit may include a plurality of test units 70 , and the plurality of test units 70 may be sequentially arranged along the first direction X, and the plurality of test units 70 correspond one-to-one to the positions of the plurality of touch columns in the display area 100 .
  • At least one test unit may include at least a first test line 71, a second test line 72, a first data lead 73, a second data lead 74, a third data lead 75, a switch control line 76, a first switch 91, a second switch 92, a third switch 93, a fourth switch 94 and a fifth switch 95.
  • the switch control line 76, the first data lead 73, the second data lead 74, the third data lead 75, the second test line 72 and the first test line 71 can be arranged in sequence along the direction away from the display area, and the above signal lines are all in the shape of lines extending along the first direction X.
  • the third switch 93 , the fourth switch 94 , the fifth switch 95 , the first switch 91 , and the second switch 92 may be sequentially disposed along the first direction X.
  • the first pole of the first switch 91 is connected to the first test line 71
  • the second pole of the first switch 91 is connected to the first lead 61 in the display area 100
  • the control pole of the first switch 91 is connected to the switch control line 76
  • the first test line 71 is connected to the first lead 61 in the display area 100 through the first switch 91
  • the first test line 71 is configured to transmit a first test signal to the first lead 61 under the control of the switch control line 76 and the first switch 91.
  • a first pole of the second switch 92 is connected to the second test line 72
  • a second pole of the second switch 92 is connected to the second lead 62 in the display area 100
  • a control pole of the second switch 92 is connected to the switch control line 76, that is, the second test line 72 is connected to the second lead 62 in the display area 100 through the second switch 92
  • the second test line 72 is configured to transmit a second test signal to the second lead 62 under the control of the switch control line 76 and the second switch 92.
  • the voltage value of the first test signal is greater than the voltage value of the second test signal, or the voltage value of the first test signal is less than the voltage value of the second test signal, that is, the voltage value of the first test signal is not equal to the voltage value of the second test signal.
  • a first electrode of the third switch 93 is connected to the first data lead 73
  • a second electrode of the third switch 93 is connected to the data line 30 of the first sub-pixel in the display area 100
  • a control electrode of the third switch 93 is connected to the switch control line 76, that is, the first data lead 73 is connected to the data line 30 of the first sub-pixel in the display area 100 through the third switch 93
  • the first data lead 73 is configured to transmit a first data signal to the data line 30 of the first sub-pixel under the control of the switch control line 76 and the third switch 93.
  • a first electrode of the fourth switch 94 is connected to the second data lead 74
  • a second electrode of the fourth switch 94 is connected to the data line 30 of the second sub-pixel in the display area 100
  • a control electrode of the fourth switch 94 is connected to the switch control line 76, that is, the second data lead 74 is connected to the data line 30 of the second sub-pixel in the display area 100 through the fourth switch 94
  • the second data lead 74 is configured to transmit a second data signal to the data line 30 of the second sub-pixel under the control of the switch control line 76 and the fourth switch 94.
  • a first electrode of the fifth switch 95 is connected to the third data lead 75
  • a second electrode of the fifth switch 95 is connected to the data line 30 of the third sub-pixel in the display area 100
  • a control electrode of the fifth switch 95 is connected to the switch control line 76
  • the third data lead 75 is connected to the data line 30 of the third sub-pixel in the display area 100 through the fifth switch 95
  • the third data lead 75 is configured to transmit a third data signal to the data line 30 of the third sub-pixel under the control of the switch control line 76 and the fifth switch 95.
  • the first switch 91 , the second switch 92 , the third switch 93 , the fourth switch 94 , and the fifth switch 95 may be thin film transistors.
  • the side frame area 320 may include at least a gate driving circuit 330 and a plurality of connection lines, and the gate driving circuit 330 may be disposed on a side of the plurality of connection lines close to the display area.
  • the side frame area 320 may include a left frame and a right frame.
  • the left frame may be
  • the right side frame may at least include a gate driving circuit 330 , a first connecting line 81 , a third connecting line 83 and a sixth connecting line 86
  • the right side frame may at least include a gate driving circuit 330 , a second connecting line 82 , a fourth connecting line 84 and a fifth connecting line 85 .
  • test terminals of the gate driving circuit 330 disposed in the left frame and the right frame are respectively connected to the gate line control pins 270 in the binding area 200 through connecting wires, and the output terminals of the gate driving circuit 330 are respectively connected to the plurality of gate lines 20 in the display area 100.
  • the test terminal of the gate driving circuit 330 is connected to the output terminal, and the gate driving circuit 330 is configured to output a turn-on voltage to the plurality of gate lines 20 in the display area 100.
  • the first end of the first connecting line 81 is connected to the first test pin 210 in the binding area 200, and the second end of the first connecting line 81 extends toward the upper frame area 310 and is connected to the first test line 71 in the upper frame area 310, thereby realizing the connection between the first test line 71 and the first test pin 210.
  • the first end of the second connecting line 82 is connected to the second test pin 220 in the binding area 200, and the second end of the second connecting line 82 extends toward the upper frame area 310 and is connected to the second test line 72 in the upper frame area 310, thereby realizing the connection between the second test line 72 and the second test pin 220.
  • the first end of the third connection line 83 is connected to the first data pin 230 in the binding area 200, and the second end of the third connection line 83 extends toward the upper frame area 310 and is connected to the first data lead 73 in the upper frame area 310, thereby realizing the connection between the first data lead 73 and the first data pin 230.
  • the first end of the fourth connection line 84 is connected to the second data pin 240 in the binding area 200, and the second end of the fourth connection line 84 extends toward the upper frame area 310 and is connected to the second data lead 74 in the upper frame area 310, thereby realizing the connection between the second data lead 74 and the second data pin 240.
  • the first end of the fifth connection line 85 is connected to the third data pin 250 in the binding area 200, and the second end of the fifth connection line 85 extends toward the upper frame area 310 and is connected to the third data lead 75 in the upper frame area 310, thereby realizing the connection between the third data lead 75 and the third data pin 250.
  • the first end of the sixth connection line 86 is connected to the switch control pin 260 in the binding area 200, and the second end of the sixth connection line 86 extends toward the upper frame area 310 and is connected to the switch control line 76 in the upper frame area 310, thereby realizing the connection between the switch control line 76 and the switch control pin 260.
  • the preparation of the test circuit of the present disclosure may include the following operations.
  • the first conductive layer pattern When the first conductive layer pattern is formed in the display area, the first conductive layer pattern also includes a first test line 71, a second test line 72, a first data lead line 73, a second data lead line 74, a third data lead line 75 and a control line group located in the upper frame area, as shown in FIG. 15 .
  • control line group, the first data lead line 73 , the second data lead line 74 , the third data lead line 75 , the second test line 72 , and the first test line 71 may be sequentially disposed in a direction away from the display area.
  • control line group may include at least a first control line 76-1, a second control line 76-2, a third control line 76-3, a fourth control line 76-4, and a fifth control line 76-5 sequentially disposed in a direction away from the display area.
  • a plurality of first gate blocks 111 and a plurality of second gate blocks 112 may be arranged between the third control line 76-3 and the fifth control line 76-5, the first ends of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the third control line 76-3, the second ends of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the fifth control line 76-5, and the middle portions of the plurality of first gate blocks 111 and the plurality of second gate blocks 112 are connected to the fourth control line 76-4, so that the third control line 76-3, the fourth control line 76-4 and the fifth control line 76-5 are connected into an integrated structure through the plurality of first gate blocks 111 and the plurality of second gate blocks 112, the plurality of first gate blocks 111 are configured to serve as gate electrodes of the first switch 91, and the plurality of second gate blocks 112 are configured to serve as gate electrodes of the second switch 92.
  • a plurality of fourth gate blocks 114 may be disposed between the fourth control line 76-4 and the fifth control line 76-5, the first ends of the plurality of fourth gate blocks 114 being connected to the fourth control line 76-4, the second ends of the plurality of fourth gate blocks 114 being connected to the fifth control line 76-5, and the plurality of fourth gate blocks 114 being configured to serve as gate electrodes of the fourth switch 94.
  • a plurality of third gate blocks 113 and a plurality of fifth gate blocks 115 may be disposed between the first control line 76-1 and the second control line 76-2, and the first ends of the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115 are The plurality of third gate blocks 113 and the plurality of fifth gate blocks 115 are connected to the first control line 76-1, and the second ends of the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115 are connected to the second control line 76-2, so that the first control line 76-1 and the second control line 76-2 are connected into an integrated structure through the plurality of third gate blocks 113 and the plurality of fifth gate blocks 115, and the plurality of third gate blocks 113 are configured to serve as gate electrodes of the third switch 93, and the plurality of fifth gate blocks 115 are configured to serve as gate electrodes of the fifth switch 95.
  • the present disclosure adopts a plurality of control lines and a plurality of gate blocks to form a control line group, which can effectively reduce the occupied area of the switch and reduce the border width, thereby facilitating the realization of a narrow border.
  • the semiconductor layer pattern further includes a first active layer 121, a second active layer 122, a third active layer 123, a fourth active layer 124 and a fifth active layer 125 located in the upper frame area, as shown in FIG. 16 .
  • an orthographic projection of the first active layer 121 on the substrate may be located within a range of an orthographic projection of the first gate block 111 on the substrate, and the first active layer 121 is configured to serve as an active layer of the first switch 91 .
  • an orthographic projection of the second active layer 122 on the substrate may be located within a range of an orthographic projection of the second gate block 112 on the substrate, and the second active layer 122 is configured to serve as an active layer of the second switch 92 .
  • an orthographic projection of the third active layer 123 on the substrate may be located within a range of an orthographic projection of the third gate block 113 on the substrate, and the third active layer 123 is configured to serve as an active layer of the third switch 93 .
  • an orthographic projection of the fourth active layer 124 on the substrate may be located within a range of an orthographic projection of the fourth gate block 114 on the substrate, and the fourth active layer 124 is configured to serve as an active layer of the fourth switch 94 .
  • an orthographic projection of the fifth active layer 125 on the substrate may be located within a range of an orthographic projection of the fifth gate block 115 on the substrate, and the fifth active layer 125 is configured to serve as an active layer of the fifth switch 95 .
  • the second conductive layer pattern also includes a first source electrode 131, a second source electrode 132, a third source electrode 133, a fourth source electrode 134, a fifth source electrode 135, a first drain electrode 141, a second drain electrode 142, a third drain electrode 143, a fourth drain electrode 144, a fifth drain electrode 145, a first overlap block 151, a second overlap block 152, a third overlap block 153, a fourth overlap block 154 and a fifth overlap block 155 located in the upper frame area, as shown in FIG. 17 .
  • the first end of the first source electrode 131 is connected to the first active layer 121, and the second end of the first source electrode 131 is connected to the first bridge block 151 after extending in a direction away from the display area.
  • the first bridge block 151 can be arranged on a side of the first test line 71 close to the display area, and the first bridge block 151 is configured to be connected to the first bridge electrode formed later.
  • the first end of the first drain electrode 141 is connected to the first active layer 121, and the second end of the first drain electrode 141 is connected to the first lead of the display area after extending in a direction of the display area.
  • a conductive channel is formed between the first source electrode 131 and the first drain electrode 141, and the first gate block 111, the first active layer 121, the first source electrode 131 and the first drain electrode 141 constitute the first switch 91.
  • the first end of the second source electrode 132 is connected to the second active layer 122, and the second end of the second source electrode 132 is connected to the second bridge block 152 after extending in a direction away from the display area.
  • the second bridge block 152 can be arranged on a side of the second test line 72 close to the display area, and the second bridge block 152 is configured to be connected to the second bridge electrode formed later.
  • the first end of the second drain electrode 142 is connected to the second active layer 122, and the second end of the second drain electrode 142 is connected to the second lead of the display area after extending in a direction of the display area.
  • a conductive channel is formed between the second source electrode 132 and the second drain electrode 142, and the second gate block 112, the second active layer 122, the second source electrode 132 and the second drain electrode 142 constitute the second switch 92.
  • a first end of the third source electrode 133 is connected to the third active layer 123, and a second end of the third source electrode 133 is connected to the third bridge block 153 after extending in a direction away from the display area.
  • the third bridge block 153 may be disposed on a side of the first data lead 73 close to the display area, and the third bridge block 153 is configured to be connected to a third bridge electrode formed subsequently.
  • a first end of the third drain electrode 143 is connected to the third active layer 123, and a second end of the third drain electrode 143 is connected to the data line of the first sub-pixel in the display area after extending in a direction toward the display area.
  • a conductive channel is formed between the third source electrode 133 and the third drain electrode 143, and the third gate block 113, the third active layer 123, and the third source electrode 143 are connected to the third gate block 113.
  • the electrode 133 and the third drain electrode 143 constitute a third switch 93 .
  • the first end of the fourth source electrode 134 is connected to the fourth active layer 124, and the second end of the fourth source electrode 134 is connected to the fourth bridge block 154 after extending in a direction away from the display area.
  • the fourth bridge block 154 can be arranged on a side of the second data lead 74 close to the display area, and the fourth bridge block 154 is configured to be connected to the fourth bridge electrode formed later.
  • the first end of the fourth drain electrode 144 is connected to the fourth active layer 124, and the second end of the fourth drain electrode 144 is connected to the data line of the second sub-pixel in the display area after extending in a direction of the display area.
  • a conductive channel is formed between the fourth source electrode 134 and the fourth drain electrode 144, and the fourth gate block 114, the fourth active layer 124, the fourth source electrode 134 and the fourth drain electrode 144 constitute a fourth switch 94.
  • the first end of the fifth source electrode 135 is connected to the fifth active layer 125, and the second end of the fifth source electrode 135 is connected to the fifth strapping block 155 after extending in a direction away from the display area.
  • the fifth strapping block 155 can be arranged on a side of the third data lead 75 close to the display area, and the fifth strapping block 155 is configured to be connected to the fifth strapping electrode formed later.
  • the first end of the fifth drain electrode 145 is connected to the fifth active layer 125, and the second end of the fifth drain electrode 145 is connected to the data line of the third sub-pixel in the display area after extending in a direction of the display area.
  • a conductive channel is formed between the fifth source electrode 135 and the fifth drain electrode 145, and the fifth gate block 115, the fifth active layer 125, the fifth source electrode 135 and the fifth drain electrode 145 constitute the fifth switch 95.
  • the multiple via holes on the second insulating layer also include the eleventh via hole V11, the twelfth via hole V12, the thirteenth via hole V13, the fourteenth via hole V14, the fifteenth via hole V15, the sixteenth via hole V16, the seventeenth via hole V17, the eighteenth via hole V18, the nineteenth via hole V19, and the twentieth via hole V20 located in the upper frame area, as shown in FIG. 18 .
  • the orthographic projection of the eleventh via hole V11 on the substrate may be located within the range of the orthographic projection of the first strap block 151 on the substrate, the eleventh via hole V11 exposes the surface of the first strap block 151, and the eleventh via hole V11 is configured to connect a subsequently formed first strap electrode to the first strap block 151 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate may be located within the range of the orthographic projection of the second strap block 152 on the substrate, the twelfth via hole V12 exposes the surface of the second strap block 152, and the twelfth via hole V12 is configured to connect a subsequently formed second strap electrode to the second strap block 152 through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate may be located within the range of the orthographic projection of the third strap block 153 on the substrate, the thirteenth via hole V13 exposes the surface of the third strap block 153, and the thirteenth via hole V13 is configured to connect a subsequently formed third strap electrode to the third strap block 153 through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate may be located within the range of the orthographic projection of the fourth strap block 154 on the substrate, the fourteenth via hole V14 exposes the surface of the fourth strap block 154, and the fourteenth via hole V14 is configured to connect a subsequently formed fourth strap electrode to the fourth strap block 154 through the via hole.
  • the orthographic projection of the fifteenth via hole V15 on the substrate may be located within the range of the orthographic projection of the fifth strap block 155 on the substrate, the fifteenth via hole V15 exposes the surface of the fifth strap block 155, and the fifteenth via hole V15 is configured to connect a subsequently formed fifth strap electrode to the fifth strap block 155 through the via hole.
  • the orthographic projection of the sixteenth via V16 on the substrate may be within the range of the orthographic projection of the first test line 71 on the substrate, the sixteenth via V16 exposes the surface of the first test line 71, and the sixteenth via V16 is configured to connect a subsequently formed first bonding electrode to the first test line 71 through the via.
  • the orthographic projection of the seventeenth via V17 on the substrate may be within the range of the orthographic projection of the second test line 72 on the substrate, the seventeenth via V17 exposes the surface of the second test line 72, and the seventeenth via V17 is configured to connect a subsequently formed second bonding electrode to the second test line 72 through the via.
  • the orthographic projection of the eighteenth via hole V18 on the substrate may be located within the range of the orthographic projection of the first data lead 73 on the substrate, the eighteenth via hole V18 exposes the surface of the first data lead 73, and the eighteenth via hole V18 is configured to connect a subsequently formed third bonding electrode to the first data lead 73 through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate may be located at the second data lead line 74 Within the range of the orthographic projection on the substrate, the nineteenth via hole V19 exposes the surface of the second data lead 74 , and the nineteenth via hole V19 is configured to connect a fourth bonding electrode formed subsequently to the second data lead 74 through the via hole.
  • the orthographic projection of the twentieth via hole V20 on the substrate may be located within the range of the orthographic projection of the third data lead 75 on the substrate, the twentieth via hole V20 exposes the surface of the third data lead 75, and the twentieth via hole V20 is configured to connect a subsequently formed fifth bonding electrode to the third data lead 75 through the via hole.
  • the eleventh via hole V11 to the twentieth via hole V20 may be a plurality of via holes sequentially arranged along the first direction X to improve connection reliability.
  • the third conductive layer pattern further includes a first bonding electrode 161, a second bonding electrode 162, a third bonding electrode 163, a fourth bonding electrode 164 and a fifth bonding electrode 165 located in the upper frame area, as shown in FIG. 19 .
  • a first end of the first strapping electrode 161 is connected to the first strapping block 151 through an eleventh via hole V11 , and a second end of the first strapping electrode 161 is connected to the first test line 71 through a sixteenth via hole V16 .
  • a first end of the second strapping electrode 162 is connected to the second strapping block 152 through a twelfth via hole V12 , and a second end of the second strapping electrode 162 is connected to the second test line 72 through a seventeenth via hole V17 .
  • a first end of the third strapping electrode 163 is connected to the third strapping block 153 through a thirteenth via hole V13
  • a second end of the third strapping electrode 163 is connected to the first data lead 73 through an eighteenth via hole V18 .
  • a first end of the fourth strapping electrode 164 is connected to the fourth strapping block 154 through a fourteenth via hole V14 , and a second end of the fourth strapping electrode 164 is connected to the second data lead 74 through a nineteenth via hole V19 .
  • a first end of the fifth strapping electrode 165 is connected to the fifth strapping block 155 through a fifteenth via hole V15
  • a second end of the fifth strapping electrode 165 is connected to the third data lead 75 through a twentieth via hole V20 .
  • the first to fifth bonding electrodes 161 to 165 may be a plurality of bonding electrodes sequentially arranged along the first direction X to improve connection reliability.
  • the test circuit may include multiple test units.
  • the multiple test units may be arranged in sequence along the first direction X.
  • At least one test unit may include at least a first test line 71, a second test line 72, a first data lead 73, a second data lead 74, a third data lead 75, a switch control line 76, a first switch 91, a second switch 92, a third switch 93, a fourth switch 94 and a fifth switch 95.
  • the process of the test circuit detecting the plurality of touch electrodes in the display area may include:
  • the external test device After the external test device is bound and connected to the plurality of pins in the binding area, the external test device provides a start signal to the gate line control pin 270, provides a conduction signal to the switch control pin 260, and provides a data signal to the first data pin 230, the second data pin 240, and the third data pin 250.
  • the conduction signal and the start signal may be a high level voltage (VGH), and the data signal may be a common reference voltage (VCOM).
  • VGH high level voltage
  • VCOM common reference voltage
  • the start signal provided by the external test device causes the gate drive circuit 330 to output a start voltage to the plurality of gate lines 20 in the display area, and the thin film transistors of the plurality of sub-pixels in the display area are turned on.
  • the conduction signal provided by the external test device turns on the first switch 91, the second switch 92, the third switch 93, the fourth switch 94 and the fifth switch 95 of the multiple test units 70 in the upper frame area
  • the data signal provided by the external test device is respectively provided to the multiple data lines 30 in the display area through the first data lead 73 and the turned-on third switch 93, the second data lead 74 and the turned-on fourth switch 94, the third data lead 75 and the turned-on fifth switch 95, and is transmitted to the pixel electrodes 40 of the multiple sub-pixels through the turned-on thin film transistors, so that the pixel electrodes 40 of the multiple sub-pixels in the display area are charged with a common reference voltage.
  • This stage is opened in advance by the signal, and the pixel electrodes are charged with the common reference voltage before the first test signal and the second test signal arrive.
  • the external test device provides a first test signal to the first test pin 210 and a second test signal to the second test pin 220.
  • the first test signal may be a first grayscale voltage
  • the second test signal may be a second grayscale voltage.
  • the voltage value of the first grayscale voltage may be greater than the voltage value of the second grayscale voltage, or the voltage value of the first grayscale voltage may be less than the voltage value of the second grayscale voltage.
  • the first test signal provided by the external test device is provided to the first lead 61 of the display area through the first test line 71 and the turned-on first switch 91, and is transmitted to the first test pin 61 connected to the display area.
  • the first lead 61 is connected to the plurality of touch electrodes 50, so that the plurality of sub-pixels corresponding to the touch electrodes 50 display the first gray scale.
  • the second test signal provided by the external test device is provided to the second lead 62 of the display area through the second test line 72 and the turned-on second switch 92, and is transmitted to the plurality of touch electrodes 50 connected to the second lead 62, so that the plurality of sub-pixels corresponding to the touch electrodes 50 display the second gray scale.
  • the touch electrodes 50 multiplexed as common electrodes have a first grayscale voltage and a second grayscale voltage, respectively, and thus all sub-pixels in the display area display the first grayscale and the second grayscale, respectively.
  • Figures 20 and 21 are schematic diagrams of the detection circuit of the present disclosure performing short circuit detection
  • Figure 20 is a normal detection screen when there is no short circuit failure
  • Figure 21 is an abnormal detection screen when there is a short circuit failure.
  • the first lead is connected to the touch electrodes 50 of the odd touch rows
  • the second lead is connected to the touch electrodes 50 of the even touch rows.
  • the touch electrodes 50 of the odd touch rows display the first gray scale
  • the touch electrodes 50 of the even touch rows display the second gray scale
  • the display area realizes a display screen with uniform vertical light and dark alternations, as shown in FIG. 20 .
  • a touch electrode 50 in an odd row has the same voltage as a touch electrode 50 in an adjacent even row, and thus the area where the two adjacent touch electrodes 50 are located displays the same gray scale, which is different from the normal display image, thereby screening out defective substrates, as shown in FIG21.
  • FIG22 is a schematic diagram of the detection timing when the detection circuit of the present disclosure performs short circuit detection.
  • the first grayscale voltage and the second grayscale voltage provided to the first test line and the second test line are reversed between frames.
  • the first grayscale voltage +Lo is provided to the first test line
  • the second grayscale voltage +Le is provided to the second test line.
  • the first grayscale voltage -Lo is provided to the first test line
  • the second grayscale voltage -Le is provided to the second test line.
  • the present disclosure sets two touch leads between adjacent pixel units, one touch lead connects the touch electrodes of the odd touch rows, and the other touch lead connects the touch electrodes of the even touch rows.
  • two touch leads By providing different grayscale voltages to the two touch leads, when there is no short circuit failure in the array substrate, multiple touch rows present a vertical light and dark alternating display screen.
  • the vertically adjacent touch electrodes When there is a short circuit failure in the array substrate, the vertically adjacent touch electrodes will display the same grayscale, so that the array substrate short circuit failure can be screened out.
  • the test circuit of the present disclosure has a simple structure and a concise detection method, which can effectively screen out bad substrates, reduce module material loss, reduce production costs, and improve yield rate.
  • the exemplary embodiments of the present disclosure also provide a display device, which may include a first substrate and a second substrate arranged opposite to each other, a liquid crystal layer arranged between the first substrate and the second substrate, the first substrate may adopt the aforementioned array substrate, and the second substrate may include a black matrix and a filter unit.
  • the display device disclosed herein may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.
  • the exemplary embodiments of the present disclosure further provide a method for detecting an array substrate using the array substrate as described above, comprising:
  • a first grayscale voltage is provided to a first lead in the display area, so that a plurality of touch electrodes connected to the first lead in the display area have the first grayscale voltage;
  • a second grayscale voltage is provided to a second lead in the display area, so that a plurality of touch electrodes connected to the second lead in the display area have the second grayscale voltage;
  • a voltage value of the first grayscale voltage is greater than a voltage value of the second grayscale voltage, or a voltage value of the first grayscale voltage is less than The voltage value of the second gray scale voltage.
  • the touch electrodes in one touch row display a first gray scale
  • the touch electrodes in an adjacent touch row display a second gray scale
  • the display area presents a display screen with alternating light and dark vertically
  • at least one touch electrode in one touch row and at least one touch electrode in an adjacent touch row display the same gray scale.

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Abstract

一种阵列基板及其检测方法、显示装置，阵列基板包括构成多个触控行和多个触控列的多个触控电极（50），以及构成多个像素行和多个像素列的多个像素单元（60），触控电极（50）在阵列基板上的正投影与多个像素单元（60）在阵列基板上的正投影至少部分交叠，像素单元（60）包括多个子像素；至少一个相邻的像素列之间设置有触控引线组，触控引线组至少包括并列设置的第一引线（61）和第二引线（62），第一引线（61）与一个触控行中的一个触控电极（50）连接，第二引线（62）与相邻触控行中的另一个触控电极（50）连接。

Description

阵列基板及其检测方法、显示装置
本申请要求于2022年8月31日提交中国专利局、申请号为202211066508.2、发明名称为“阵列基板及其检测方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，具体涉及一种阵列基板及其检测方法、显示装置。
背景技术
随着显示技术的飞速发展，触摸面板(Touch Screen Panel)已经逐渐遍及人们的生活中。触摸面板按照组成结构可以分为外挂式(Add on Mode)、覆盖表面式(On Cell)、内嵌式(In Cell)等。其中，外挂式触摸面板是将触摸模组与显示模组分开生产，然后贴合到一起成为具有触摸功能的触摸面板，存在制作成本较高、光透过率较低、模组较厚等缺点。而内嵌式触摸面板是将触摸模组的触控电极内嵌在显示模组内部，不仅大大减小了模组整体厚度，而且大大降低了制作成本，逐渐成为电容式触摸面板的主流。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种阵列基板，包括显示区域，所述显示区域至少包括：构成多个触控行和多个触控列的多个触控电极，以及构成多个像素行和多个像素列的多个像素单元，所述触控单元在所述阵列基板上的正投影与多个像素单元在所述阵列基板上的正投影至少部分交叠，所述像素单元包括多个子像素；至少一个相邻的像素列之间设置有触控引线组，所述触控引线组至少包括并列设置的第一引线和第二引线，所述第一引线与一个触控行中的一个触控电极连接，所述第二引线与相邻触控行中的另一个触控电极连接。
在示例性实施方式中，至少一个触控列包括沿着所述像素列方向依次设置的N个触控电极，所述触控列在所述阵列基板上的正投影与N/2个像素列在所述阵列基板上的正投影至少部分交叠，位于第i像素列和第i+1像素列之间的第一引线与第2i-1触控行中的触控电极连接，位于第i像素列和第i+1像素列之间的第二引线与第2i触控行中的触控电极连接，N为大于1的偶数，i为大于或等于1、小于或等于N/2的正整数。
在示例性实施方式中，至少一个像素单元包括沿着所述像素行方向依次设置的第一子像素、第二子像素和第三子像素，所述子像素包括栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管分别与所述栅线、数据线和像素电极连接，所述触控电极复用为公共电极，所述第一引线和第二引线复用为公共电极线；所述第一引线设置在所述第三子像素远离所述第一子像素的一侧，所述第二引线设置在所述第一引线远离所述第一子像素的一侧。
在示例性实施方式中，至少一个像素行中，所述第一引线上设置有第一连接块，所述第一连接块通过第一过孔与一个触控电极连接。
在示例性实施方式中，至少一个像素行中，所述第一引线至少包括第一直线段、第二直线段以及位于所述第一直线段和第二直线段之间的弯折段，所述弯折段的第一端与所述第一直线段连接，所述弯折段的第二端与所述第二直线段连接，所述弯折段的中部向着远离所述第二引线的方向凸起，所述第一连接块设置在所述弯折段弯折形成的区域内。
在示例性实施方式中，所述第一连接块在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
在示例性实施方式中，所述第一过孔在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
在示例性实施方式中，至少一个像素行中，所述第二引线上设置有第二连接块，所述第二连接块通过第二过孔与另一个触控电极连接。
在示例性实施方式中，至少一个像素行中，所述第一引线至少包括第一直线段、第二直线段以及位于所述第一直线段和第二直线段之间的弯折段，所述弯折段的第一端与所述第一直线段连接，所述弯折段的第二端与所述第二直线段连接，所述弯折段的中部向着远离所述第二引线的方向凸起，所述第二连接块设置在所述弯折段弯折形成的区域内。
在示例性实施方式中，所述第二连接块在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
在示例性实施方式中，所述第二过孔在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
在示例性实施方式中，至少一个像素单元中，所述触控电极包括电极部和连接部，所述电极部设置在所述像素单元内，所述连接部设置在相邻的像素单元之间，且与相邻的像素单元内的电极部连接。
在示例性实施方式中，至少一个像素单元中，所述电极部在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影没有交叠，所述电极部在所述阵列基板上的正投影与所述第一引线在所述阵列基板上的正投影没有交叠，所述电极部在所述阵列基板上的正投影与所述第二引线在所述阵列基板上的正投影没有交叠。
在示例性实施方式中，至少一个像素单元中，所述连接部在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠，所述连接部在所述阵列基板上的正投影与所述第一引线在所述阵列基板上的正投影至少部分交叠，所述连接部在所述阵列基板上的正投影与所述第二引线在所述阵列基板上的正投影至少部分交叠。
在示例性实施方式中，至少一个像素单元中，至少一个连接部通过第一过孔所述第一引线连接，或者，至少一个连接部通过第二过孔与所述第二引线连接。
在示例性实施方式中，所述阵列基板还包括位于所述显示区域一侧的绑定区域以及位于所述显示区域远离所述绑定区域一侧的上边框区；所述绑定区域至少包括多个引脚，所述上边框区至少包括测试电路，所述测试电路通过多条连接线与所述绑定区域的多个引脚对应连接，所述测试电路被配置为对所述阵列基板的短路不良进行检测。
在示例性实施方式中，所述测试电路包括多个测试单元，多个测试单元与多个触控列的位置相对应；至少一个测试单元包括第一测试线、第二测试线、开关控制线、第一开关和第二开关；所述第一测试线通过所述第一开关与所述显示区域中的第一引线连接，所述第二测试线通过所述第二开关与所述显示区域中的第二引线连接，所述开关控制线与所述第一开关和第二开关的控制端连接；所述第一测试线被配置为在所述开关控制线的控制下向所述第一引线传输第一灰阶电压，所述第二测试线被配置为在所述开关控制线的控制下向所述第二引线传输第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述第二灰阶电压的电压值。
在示例性实施方式中，所述测试单元还包括第一数据引线、第二数据引线、第三数据 引线、第三开关、第四开关和第五开关，所述第一数据引线通过所述第三开关与所述显示区域中第一子像素的数据线连接，所述第二数据引线通过所述第四开关与所述显示区域中第二子像素的数据线连接，所述第三数据引线通过所述第五开关与所述显示区域中第三子像素的数据线连接，所述开关控制线与所述第三开关、第四开关和第五开关的控制端连接；所述第一数据引线、第二数据引线和第三数据引线被配置为在所述开关控制线的控制下向所述显示区域的数据线传输公共基准电压。
另一方面，本公开还提供了一种显示装置，包括前述的阵列基板。
又一方面，本公开还提供了一种采用前述阵列基板的阵列基板的检测方法，包括：
向显示区域中的多条栅线提供开启电压，使得显示区域中多个子像素的薄膜晶体管导通；向所述显示区域中的多条数据线提供公共基准电压，使得所述显示区域中多个子像素的像素电极具有公共基准电压；
向所述显示区域中的第一引线提供第一灰阶电压，使得显示区域中与所述第一引线连接的多个触控电极具有第一灰阶电压；向所述显示区域中的第二引线提供第二灰阶电压，使得显示区域中与所述第二引线连接的多个触控电极具有第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述第二灰阶电压的电压值。
在示例性实施方式中，当所述阵列基板上无短路不良时，一个触控行中的触控电极显示第一灰阶，相邻触控行中的触控电极显示第二灰阶，显示区域呈现纵向亮暗相间的显示画面；当所述阵列基板上有短路不良时，一个触控行中的至少一个触控电极与相邻触控行中的至少一个触控电极显示相同的灰阶。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种液晶显示装置的剖面结构示意图；
图2为一种液晶显示装置的平面结构示意图；
图3为一种阵列基板的平面结构示意图；
图4为一种盒内触摸面板的结构示意图；
图5为本公开示例性实施例一种阵列基板的平面结构示意图；
图6为本公开示例性实施例一种显示区域的平面结构示意图；
图7a为图6中A区域的放大图；
图7b为图6中B区域的放大图；
图8a和图8b为本公开阵列基板形成第一导电层图案后的示意图；
图9a和图9b为本公开阵列基板形成半导体层图案后的示意图；
图10a和图10b为本公开阵列基板形成第二导电层图案后的示意图；
图11a和图11b为本公开阵列基板形成第二绝缘层图案后的示意图；
图12a和图12b为本公开阵列基板形成第三导电层图案后的示意图；
图13a和图13b为本公开阵列基板形成第三绝缘层图案后的示意图；
图14为本公开阵列基板中绑定区域和边框区域的平面结构示意图；
图15至图19为本公开阵列基板制备测试电路的示意图；
图20和图21为本公开检测电路进行短路检测的示意图；
图22为本公开检测电路进行短路检测时的检测时序示意图。
附图标记说明:
10—薄膜晶体管；           20—栅线；                 21—栅电极；
22—有源层；               23—源电极；               24—漏电极；
30—数据线；               40—像素电极；             50—触控电极；
51—电极部；               52—连接部；               53—开口；
60—像素单元；             61—第一引线；             61-1—第一连接块；
62—第二引线；             62-1—第二连接块；         70—测试单元；
71—第一测试线；           72—第二测试线；           73—第一数据引线；
74—第二数据引线；         75—第三数据引线；         76—开关控制线；
76-1—第一控制线；         76-2—第二控制线；         76-3—第三控制线；
76-4—第四控制线；         76-5—第五控制线；         81—第一连接线；
82—第二连接线；           83—第三连接线；           84—第四连接线；
85—第五连接线；           91—第一开关；             92—第二开关；
93—第三开关；             94—第四开关；             95—第五开关；
100—显示区域；            111—第一栅极块；          112—第二栅极块；
113—第三栅极块；          114—第四栅极块；          115—第五栅极块；
121—第一有源层；          122—第二有源层；          123—第三有源层；
124—第四有源层；          125—第五有源层；          131—第一源电极；
132—第二源电极；          133—第三源电极；          134—第四源电极；
135—第五源电极；          141—第一漏电极；          142—第二漏电极；
143—第三漏电极；          144—第四漏电极；          145—第五漏电极；
151—第一搭接块；          152—第二搭接块；          153—第三搭接块；
154—第四搭接块；          155—第五搭接块；          161—第一搭接电极；
162—第二搭接电极；        163—第三搭接电极；        164—第四搭接电极；
165—第五搭接电极；        200—绑定区域；            210—第一测试引脚；
220—第二测试引脚；        230—第一数据引脚；        240—第二数据引脚；
250—第三数据引脚；        260—开关控制引脚；        270—栅线控制引脚；
280—驱动芯片；            300—边框区域；            310—上边框区；
320—侧边框区；            330—栅极驱动电路。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。阵列基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
液晶显示装置(Liquid Crystal Display，简称LCD)具有体积小、功耗低、无辐射等特点，已得到广泛应用。液晶阵列基板包括对盒(CELL)的薄膜晶体管阵列(Thin Film Transistor，简称TFT)基板和彩膜(Color Filter，简称CF)基板，液晶(Liquid Crystal，简称LC)分子设置在阵列基板和彩膜基板之间，通过控制公共电极和像素电极来形成驱动液晶偏转的电场，实现灰阶显示。
图1为一种液晶显示装置的剖面结构示意图。如图1所示，液晶显示装置可以包括相对设置的第一基板A1和第二基板A2，以及设置在第一基板A1与第二基板A2之间的液晶层A3，第一基板A1可以包括设置在第一基底A1-1朝向第二基板A2一侧的第一结构层A1-2，第二基板A2可以包括设置在第二基底A2-1朝向第一基板A1一侧的第二结构层A2-2。按照显示模式，液晶显示装置可以分为扭曲向列(Twisted Nematic，TN)显示模式、平面转换(In Plane Switching，IPS)显示模式、边缘场开关(Fringe Field Switching，FFS)显示模式和高级超维场转换(Advanced Super Dimension Switch，ADS)显示模式等。对于ADS显示模式，在示例性实施方式中，第一结构层A1-2可以包括栅线、数据线、薄膜晶体管、像素电极和公共电极，第二结构层A2-2可以包括黑矩阵和滤光单元。
图2为一种液晶显示装置的平面结构示意图。如图2所示，液晶显示装置可以包括以矩阵方式排布的多个像素单元60，多个像素单元60的至少一个可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，三个子像素可以均包括薄膜晶体管、像素电极和公共电极。在示例性实施方式中，第一子像素P1可以是出射红色(R)光线的红色子像素，第二子像素P2可以是出射绿色(G)光线的绿色子像素，第三子像素P3可以是出射蓝色(B)光线的蓝色子像素，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形等，像素单元中子像素可以采用水平并列、竖直并列或品字方式排列。在示例性实施方式中，像素单元可以包括四个子像素，本公开在此不做限定。
图3为一种阵列基板的平面结构示意图。如图3所示，在示例性实施方式中，阵列基板可以包括显示区域和边框区域，显示区域可以包括多条栅线(S1到Sm)和多条数据线(D1到Dn)，多条栅线可以沿着水平方向延伸并沿着竖直方向依次设置，多条数据线可以沿着竖直方向延伸并沿着水平方向依次设置，相互交叉的多条栅线和多条数据线限定出规则排布的多个子像素Pxij，m、n、i和j可以是自然数。在示例性实施方式中，至少一个子像素Pxij可以包括薄膜晶体管、像素电极和公共电极，薄膜晶体管分别与栅线、数据线和像素电极连接。
在示例性实施方式中，阵列基板还可以包括多条公共电极线(E1到Eo)，多条公共电极线可以沿着水平方向延伸并沿着竖直方向依次设置或者多条公共电极线可以沿着竖直方向延伸并沿着水平方向依次设置，多条公共电极线与多个子像素Pxij中的公共电极对应连接。
在示例性实施方式中，多条栅线与扫描驱动器连接，多条数据线与数据驱动器连接，扫描驱动器和数据驱动器的至少一部分可以形成在阵列基板上。
在示例性实施方式中，外部控制装置(如时序控制器)可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，数据驱动器可以利用接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn。外部控制装置可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，扫描驱动器可以利用时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。
在示例性实施方式中，集成触摸功能的液晶显示装置主要包括On Cell结构和In Cell结构。On Cell结构通常是将触摸结构设置在彩膜基板远离阵列基板的一侧，In Cell结构通常是将触摸结构设置在阵列基板的第一结构层中。与On Cell结构相比，In Cell结构能够实现液晶显示装置的轻薄化。
在示例性实施方式中，In Cell结构主要分为互容式(Mutual Capacitance)结构和自容式(Self Capacitance)结构，互容式结构是由驱动电极和感应电极相互重叠或者靠近构成互电容，利用互电容的变化进行位置检测，自容式结构是由触控电极与人体构成自电容，利用自电容的变化进行位置检测。与互容式结构相比，自容式结构为单层结构，具有功耗低和结构简单等特点。
图4为一种盒内触摸面板的结构示意图。如图4所示，盒内触摸面板(In-Cell Touch LCD)可以包括规则排布的多个触控电极50和多条触控引线(也称感测信号线，Tx信号线)50A，每个触控电极50通过触控引线50A与触控驱动电路连接。工作时，人手指的 触摸会导致相应触控电极50的自电容发生变化，触控驱动电路根据触控电极50的电容变化来判断手指的具体位置。在示例性实施方式中，盒内触摸面板采用提供公共电压的公共电极层作为触控层，将公共电极层进行“分割”形成图4所示块状的触控电极50。在示例性实施方式中，触控电极的形状可以是矩形、菱形、三角形或多边形等，本公开在此不做限定。
在示例性实施方式中，图4所示的盒内触摸面板采用分时驱动的工作方式，显示时段和触控时段的驱动信号分开处理。在显示时段内，数据线由数据驱动器供给显示信号，触控电极复用为公共电极，触控信号线复用为公共电极线，触控信号线向触控电极提供公共电压，不进行触控信号扫描，确保正常显示。在触控时段内，触控驱动电路通过触控信号线进行触控信号扫描，此时一帧显示已经完成，显示状态基本不受触控信号影响，两者分时独立工作。
在示例性实施方式中，一个触控电极可以约为4*4mm或5*5mm的矩形，可以覆盖多个子像素，由一根触控引线控制，触控引线可以设置在相邻的子像素之间。由于一个触控电极覆盖多个子像素，触控引线的数量远小于触控电极覆盖的子像素的数量，因而为了避免一些子像素之间设置有触控引线而另一些子像素之间没有设置触控引线，保证像素结构的一致性和刻蚀均一性，现有阵列基板通常是在每个相邻的子像素之间都设置了引线，这些引线的一部分作为控制触控电极的触控引线，其余部分均为虚设(dummy)线，虚设线无信号输入。
近年来，高分辨率显示装置逐渐成为行业发展趋势。显示装置的分辨率(Pixels Per Inch，简称PPI)与阵列基板的像素开口率有关，像素开口率越高，显示装置的分辨率越高。经研究发现，由于现有阵列基板的相邻子像素之间设置了触控引线或者虚设线，大量虚设线占用了子像素的空间，因而现有阵列基板存在像素开口率低等问题，影响了显示装置分辨率的提高。
本公开示例性实施例提供了一种阵列基板，包括显示区域，所述显示区域至少包括：构成多个触控行和多个触控列的多个触控电极，以及构成多个像素行和多个像素列的多个像素单元，所述触控单元在所述阵列基板上的正投影与多个像素单元在所述阵列基板上的正投影至少部分交叠，所述像素单元包括多个子像素；至少一个相邻的像素列之间设置有触控引线组，所述触控引线组至少包括并列设置的第一引线和第二引线，所述第一引线与一个触控行中的一个触控电极连接，所述第二引线与相邻触控行中的另一个触控电极连接。
在示例性实施方式中，至少一个触控列包括沿着所述像素列方向依次设置的N个触控电极，所述触控列在所述阵列基板上的正投影与N/2个像素列在所述阵列基板上的正投影至少部分交叠，位于第i像素列和第i+1像素列之间的第一引线与第2i-1触控行中的触控电极连接，位于第i像素列和第i+1像素列之间的第二引线与第2i触控行中的触控电极连接，N为大于1的偶数，i为大于或等于1、小于或等于N/2的正整数。
在示例性实施方式中，至少一个像素单元包括沿着所述像素行方向依次设置的第一子像素、第二子像素和第三子像素，所述子像素包括栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管分别与所述栅线、数据线和像素电极连接，所述触控电极复用为公共电极，所述第一引线和第二引线复用为公共电极线；所述第一引线设置在所述第三子像素远离所述第一子像素的一侧，所述第二引线设置在所述第一引线远离所述第一子像素的一侧。
在示例性实施方式中，所述阵列基板还包括位于所述显示区域一侧的绑定区域以及位于所述显示区域远离所述绑定区域一侧的上边框区；所述绑定区域至少包括多个引脚，所述上边框区至少包括测试电路，所述测试电路通过多条连接线与所述绑定区域的多个引脚对应连接，所述测试电路被配置为对所述阵列基板的短路不良进行检测。
在示例性实施方式中，所述测试电路包括多个测试单元，多个测试单元与多个触控列 的位置相对应；至少一个测试单元包括第一测试线、第二测试线、开关控制线、第一开关和第二开关；所述第一测试线通过所述第一开关与所述显示区域中的第一引线连接，所述第二测试线通过所述第二开关与所述显示区域中的第二引线连接，所述开关控制线与所述第一开关和第二开关的控制端连接；所述第一测试线被配置为在所述开关控制线的控制下向所述第一引线传输第一灰阶电压，所述第二测试线被配置为在所述开关控制线的控制下向所述第二引线传输第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述第二灰阶电压的电压值。
在示例性实施方式中，所述测试单元还包括第一数据引线、第二数据引线、第三数据引线、第三开关、第四开关和第五开关，所述第一数据引线通过所述第三开关与所述显示区域中第一子像素的数据线连接，所述第二数据引线通过所述第四开关与所述显示区域中第二子像素的数据线连接，所述第三数据引线通过所述第五开关与所述显示区域中第三子像素的数据线连接，所述开关控制线与所述第三开关、第四开关和第五开关的控制端连接；所述第一数据引线、第二数据引线和第三数据引线被配置为在所述开关控制线的控制下向所述显示区域的数据线传输公共基准电压。
图5为本公开示例性实施例一种阵列基板的平面结构示意图。如图5所示，阵列基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个像素单元和组成触控阵列的多个触控电极，多个像素单元被配置为显示动态图片或静止图像，多个触控电极被配置为实现触摸控制。在示例性实施方式中，显示区域100可以称为有效区域(AA)。
在示例性实施方式中，绑定区域200可以至少包括沿着远离显示区域方向依次设置的扇出区、驱动芯片区和绑定引脚区，扇出区可以连接到显示区域100，可以至少包括数据传输线和触控传输线，多条数据传输线被配置为以扇出走线方式连接显示区域的数据线，多条触控传输线被配置为连接显示区域的触控走线。驱动芯片区可以连接到扇出区，可以至少包括集成电路(Integrated Circuit，简称IC)，集成电路被配置为与多条数据传输线和多条触控传输线连接。绑定引脚区可以连接到驱动芯片区，可以至少包括多个引脚(PIN)，多个引脚被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括位于显示区域100远离绑定区域200一侧的上边框区310和位于显示区域100两侧的侧边框区320。上边框区310可以至少包括测试电路，测试电路与显示区域中的多条数据线和触控走线连接，测试电路被配置为对阵列基板的短路不良进行检测。侧边框区320可以包括沿着远离显示区域100的方向依次设置的电路区和引线区。电路区可以连接到显示区域100，可以至少包括多个级联的栅极驱动电路(GOA)，栅极驱动电路与显示区域100中的多条栅线连接。引线区可以连接到电路区，可以至少包括多条连接线，多条连接线的第一端可以与绑定区域200的多个引脚连接，多条连接线的第二端可以与上边框区310的测试电路连接，使得外部测试装置通过多条连接线将测试信号传输到测试电路。
图6为本公开示例性实施例一种显示区域的平面结构示意图。如图6所示，在示例性实施方式中，阵列基板的显示区域可以至少包括构成多个触控行和多个触控列的多个触控电极50以及构成多个像素行和多个像素列的多个像素单元60，多个像素单元60构成像素阵列，被配置为显示动态图片或静止图像，多个触控电极50构成触控阵列，被配置为实现触摸控制。每个触控行可以包括多个沿着第一方向X依次设置的多个触控电极50，多个触控行可以沿着第二方向Y间隔设置，每个触控列可以包括多个沿着第二方向Y依次设置的多个触控电极50，多个触控列可以沿着第一方向X间隔设置。每个像素行可以 包括多个沿着第一方向X依次设置的多个像素单元60，多个像素行可以沿着第二方向Y间隔设置，每个像素列可以包括多个沿着第二方向Y依次设置的多个像素单元60，多个像素列可以沿着第一方向X间隔设置。在示例性实施方式中，第一方向X与第二方向Y交叉。
在示例性实施方式中，至少一个触控电极50在阵列基板上的正投影可以包含多个像素单元60在阵列基板上的正投影，即一个触控电极50可以覆盖多个像素单元60，像素单元60可以包括多个子像素。
在示例性实施方式中，显示区域可以包括N个触控行，即一个触控列中可以包括沿着第二方向Y依次设置的N个触控电极50。至少一个触控列在阵列基板上的正投影与N/2个像素列在阵列基板上的正投影至少部分交叠，即一个触控列的N个触控电极50的位置可以与N/2个像素列的多个像素单元60的位置相对应，N为大于1的偶数。
在示例性实施方式中，与一个触控列相对应的N/2个像素列中，至少一个相邻的像素列之间设置有触控引线组。在示例性实施方式中，触控引线组可以包括第一引线61和第二引线62。第一引线61和第二引线62的形状可以为沿着第二方向Y(像素列方向)延伸的线形状，第二引线62可以设置在第一引线61第一方向X(像素行方向)的一侧。
在示例性实施方式中，对于位于第i像素列和第i+1像素列之间的第一引线61和第二引线62，第一引线61可以与第2i-1触控行中的触控电极50连接，第二引线62可以与第2i触控行中的触控电极50连接，i为大于或等于1、小于或等于N/2的正整数。
在示例性实施方式中，当多条第一引线61与奇数的触控行中的触控电极50连接时，多条第二引线62则与偶数的触控行中的触控电极50连接。当多条第一引线61与偶数的触控行中的触控电极50连接时，多条第二引线62则与奇数的触控行中的触控电极50连接。
在示例性实施方式中，对于图6所示左侧的第一触控列，该触控列与N/2个像素列相对应。对于第1像素列与第2像素列之间的第一引线61和第二引线62，第一引线61与该触控列的第1个触控电极50(第1触控行的触控电极50)连接，第二引线62与该触控列的第2个触控电极50(第2触控行的触控电极50)连接。对于第2像素列与第3像素列之间的第一引线61和第二引线62，第一引线61与该触控列的第3个触控电极50(第3触控行的触控电极50)连接，第二引线62与该触控列的第4个触控电极50(第4触控行的触控电极50)连接。对于第(N/2)像素列与第N/2+1像素列之间的第一引线61和第二引线62，第一引线61与该触控列的第N-1个触控电极50(第N-1触控行的触控电极50)连接，第二引线62与该触控列的第N个触控电极50(第N触控行的触控电极50)连接。其中，第N/2+1像素列是第2触控列所对应的第1像素列。
在示例性实施方式中，一个像素单元60可以包括3个子像素或者可以包括4个子像素。以像素单元60包括沿着第一方向X依次设置的第一子像素、第二子像素和第三子像素为例，第一引线61和第二引线62可以设置在第i像素列的第三子像素与第i+1像素列的第一子像素之间，而每个像素列中的第一子像素与第二子像素之间、第二子像素与第三子像素之间均没有设置第一引线，也没有设置第二引线。
在示例性实施方式中，显示区域可以包括多个触控列，每个触控列以及对应的多个像素列的结构可以与第一触控列相同。
在示例性实施方式中，在垂直于阵列基板的平面上，阵列基板可以包括基底和设置在基底上的多个导电层，第一引线61和第二引线62可以设置在相同的一个导电层中，触控电极50可以设置在另一个导电层中，第一引线61和第二引线62可以通过过孔与触控电极50连接。
一种阵列基板中，引线通常设置在每个相邻的子像素之间，即包括3个子像素的一个 像素单元中设置了3条引线，一些引线作为触控引线，另一些引线作为虚设线。由于每条引线均会占用子像素的空间，因而该结构的阵列基板存在像素开口率低等问题，影响了显示装置分辨率的提高。本公开示例性实施例所提供的阵列基板，通过在相邻的像素单元之间设置2条触控引线，因而一个像素单元仅包括2条触控引线。与像素单元中设置3条引线相比，本公开不仅减小了引线数量，增加了子像素的空间，提高了像素开口率，且提高了阵列基板的透光率，有利于显示装置分辨率的提高，而且由于每条引线均与相应的触控电极通过过孔连接，保证了像素结构的一致性和刻蚀均一性，有利于提高制备工艺的质量。
在示例性实施方式中，图6所示结构仅仅是一种示例性说明，可以根据实际需要变更相应结构。例如，触控引线组可以包括3条触控引线或者多条触控引线。由于现有阵列基板是将3条引线分别设置在子像素之间，而本公开将3条触控引线设置在相邻的像素单元之间，同样可以增加子像素的空间，提高像素开口率，有利于显示装置分辨率的提高。又如，可以将2个像素单元或者多个像素单元作为一个重复单元，触控引线组可以设置在相邻的重复单元之间，本公开在此不做限定
图7a为图6中A区域的放大图，图7b为图6中B区域的放大图。其中，A区域的像素单元是第m1像素行、第n像素列的像素单元，B区域的像素单元是第m2像素行、第n像素列的像素单元，A区域的像素单元和B区域的像素单元均包括沿着第一方向X依次设置的第一子像素P1、第二子像素P2和第三子像素P3。
在示例性实施方式中，阵列基板的显示区域可以至少包括多条栅线20和多条数据线30，栅线20的形状可以是沿着第一方向X延伸的线形状，多条栅线20可以沿着第二方向Y依次设置，数据线30的形状可以是沿着第二方向Y延伸的线形状，多条数据线30可以沿着第一方向X依次设置，相互交叉的多条栅线20和多条数据线30限定出规则排布的多个子像素，每个子像素中设置有薄膜晶体管和像素电极，薄膜晶体管可以分别与栅线20、数据线30和像素电极连接。
在示例性实施方式中，阵列基板的显示区域还可以包括复用为公共电极线的多个触控引线组，以及复用为公共电极的多个触控电极50。触控引线组可以设置在第一方向X上相邻的像素单元之间，至少一个触控引线组可以至少包括并列设置的第一引线61和第二引线62，第一引线61和第二引线62分别与相应的触控电极50连接。
在示例性实施方式中，每个子像素中的薄膜晶体管被配置为在栅线20的控制下，接收数据线30传输的数据电压并向像素电极输出，控制像素电极和公共电极之间形成驱动液晶偏转的电场，实现灰阶显示。
在示例性实施方式中，第一引线61和第二引线62的形状可以为沿着第二方向Y延伸的折线状。在一个像素行(如第m1像素行)中，第一引线61可以通过第一过孔K1与一个触控电极50连接。在另一个像素行(如第m2像素行)中，第二引线62可以通过第二过孔K2与另一个触控电极50连接。
在示例性实施方式中，在一个像素行中，第一引线61上可以设置有第一连接块61-1，第一连接块61-1可以通过第一过孔K1与相应的触控电极50连接。
在示例性实施方式中，在一个像素行中，第一引线61可以包括第一直线段、第二直线段以及位于第一直线段和第二直线段之间的弯折段，弯折段的第一端与第一直线段连接，弯折段的第二端与第二直线段连接，弯折段的中部可以向着远离第二引线62的方向凸起，第一连接块61-1可以设置在弯折段靠近第二引线62的一侧，即第一连接块61-1可以设置在弯折段弯折形成的区域内。
在示例性实施方式中，在另一个像素行中，第二引线62上可以设置有第二连接块62-1，第二连接块62-1可以通过第二过孔K2与另一个触控电极50连接。
在示例性实施方式中，在另一个像素行中，第一引线61可以包括第一直线段、第二直线段以及位于第一直线段和第二直线段之间的弯折段，弯折段的第一端与第一直线段连接，弯折段的第二端与第二直线段连接，弯折段的中部可以向着远离第二引线62的方向凸起，使得第二连接块62-1可以设置在弯折段弯折形成的区域内。
在示例性实施方式中，第一连接块61-1在基底上的正投影与栅线20在基底上的正投影至少部分交叠，第二连接块62-1在基底上的正投影与栅线20在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个像素单元中的触控电极50可以包括电极部51和连接部52，电极部51可以设置在像素单元内，连接部52可以设置在相邻的像素单元之间，并与相邻的像素单元内的电极部51连接，将多个像素单元内的多个电极部51连接成一体。
在示例性实施方式中，连接部52可以设置在第一方向X相邻的像素单元之间，或者，连接部52可以设置在第二方向Y相邻的像素单元之间，或者，连接部52可以设置在第一方向X相邻的像素单元之间以及第二方向Y相邻的像素单元之间。
在示例性实施方式中，电极部51在基底上的正投影与栅线20在基底上的正投影没有交叠，电极部51在基底上的正投影与第一引线61在基底上的正投影没有交叠，电极部51在基底上的正投影与第二引线62在基底上的正投影没有交叠。
在示例性实施方式中，连接部52在基底上的正投影与栅线20在基底上的正投影至少部分交叠，连接部52在基底上的正投影与第一引线61在基底上的正投影至少部分交叠，连接部52在基底上的正投影与第二引线62在基底上的正投影至少部分交叠。
在示例性实施方式中，一个触控电极50的至少一个连接部52通过第一过孔K1与第一引线61连接，另一个触控电极50的至少一个连接部52通过第二过孔K2与第二引线62连接。
在示例性实施方式中，第一过孔K1在基底上的正投影与栅线20在基底上的正投影至少部分交叠，第二过孔K2在基底上的正投影与栅线20在基底上的正投影至少部分交叠。
在示例性实施方式中，像素单元中的电极部51上可以设置有至少一个开口53，开口53的形状可以为沿着第二方向Y延伸的折线状，使得电极部51形成沿着第一方向X间隔设置的多个条形电极，可以保证面状的像素电极40和条形的公共电极(触控电极)之间形成水平电场。
下面通过阵列基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于阵列基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，阵列基板的制备可以包括如下操作。
(1)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括： 在基底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，在基底上形成第一导电层图案，第一导电层图案至少包括栅线20和栅电极21，如图8a和图8b所示，图8a为图6中A区域的放大图，图8b为图6中B区域的放大图。
在示例性实施方式中，栅线20的形状可以为主体部分沿着第一方向X延伸的直线状，每个子像素的栅线20可以设置在子像素第二方向Y的一侧(子像素中靠近下一行子像素的位置)，栅线20被配置为与子像素中的薄膜晶体管连接，向薄膜晶体管提供扫描信号。
在示例性实施方式中，栅电极21的形状可以为矩形状，栅电极21可以设置在每个子像素中，且与栅线20连接，相当于栅线20在形成晶体管的区域进行了加宽设计，使得栅线20与后续形成的数据线的交叠区域较小，可以减小栅线20与数据线之间的寄生电容，提高阵列基板的电学性能。
在示例性实施方式中，栅线20和多个子像素中的栅电极21可以为相互连接的一体结构。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在形成有前述图案的基底上依次沉积第一绝缘薄膜和半导体层薄膜，通过图案化工艺对半导体层薄膜进行图案化，形成覆盖第一导电层图案的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图9a和图9b所示，图9a为图6中A区域的放大图，图9b为图6中B区域的放大图。
在示例性实施方式中，半导体层图案至少包括设置在每个子像素内的有源层22，有源层22在基底上的正投影可以位于栅电极21在基底上的正投影的范围之内。
在示例性实施方式中，每个子像素中有源层22的形状和位置可以相同，可以简化薄膜晶体管的结构。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成有前述图案的基底上沉积第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成第二导电层图案，如图10a和图10b所示，图10a为图6中A区域的放大图，图10b为图6中B区域的放大图。
在示例性实施方式中，第二导电层图案至少包括：源电极23、漏电极24、数据线30、第一引线61和第二引线62。
在示例性实施方式中，数据线30、第一引线61和第二引线62的形状可以为主体部分沿着第二方向Y延伸的折线状，数据线30、第一引线61和第二引线62中各个折线的延伸方向可以基本上相同。
在示例性实施方式中，每个子像素中均设置有数据线30，数据线30可以设置在每个子像素第一方向X的反方向的一侧(左侧)，数据线30被配置为与子像素中的薄膜晶体管连接，向薄膜晶体管提供数据信号。
在示例性实施方式中，源电极23和漏电极24可以设置在每个子像素中，数据线30的一部分作为每个子像素的源电极23，每个子像素的漏电极24可以为单独设置的“L”形状，源电极23与有源层22连接，漏电极24的第一端与有源层22连接，漏电极24的第二端向着远离有源层22的方向延伸，被配置为与后续形成的像素电极连接，源电极23与漏电极24之间形成导电沟道。
在示例性实施方式中，每个子像素中的栅电极21、有源层22、源电极23和漏电极24构成薄膜晶体管，栅电极21与栅线连接，源电极23与数据线30连接，漏电极24与像素电极连接。
在示例性实施方式中，第一引线61和第二引线62可以设置在第一方向X上相邻的像素单元之间，第一引线61和第二引线62被配置为与后续形成的触控电极(复用为公共电极)连接，向触控电极提供触控信号或者公共电压信号。
在示例性实施方式中，第一引线61和第二引线62可以设置在第n-1像素列与第n像素列之间，以及设置在第n像素列与第n+1像素列之间。对于第n像素列，第一引线61可以设置在第三子像素P3远离第一子像素P1的一侧，第二引线62可以设置在第一引线61远离第一子像素P1的一侧。
如图10a所示，第m1像素行中，第n像素列与第n+1像素列之间的第一引线61的形状与其它相邻像素列之间的第一引线61的形状不同，而第二引线62的形状与其它相邻像素列之间的第二引线62的形状基本上相同。
在示例性实施方式中，第一引线61可以包括第一直线段61A、第二直线段61B以及位于第一直线段61A和第二直线段61B之间的弯折段61C，且第一引线61上设置有第一连接块61-1，第一连接块61-1被配置为通过过孔与后续形成的一个触控电极连接。
在示例性实施方式中，弯折段61C的第一端与第一直线段61A连接，弯折段61C的第二端与第二直线段61B连接，弯折段61C的中部可以向着第一方向X的反方向(远离第二引线62的方向)凸起，第一连接块61-1设置在弯折段61C第一方向X(靠近第二引线62的方向)的一侧，即第一连接块61-1设置在弯折段61C弯折形成的区域内。
在示例性实施方式中，第一直线段61A、第二直线段61B、弯折段61C和第一连接块61-1可以为相互连接的一体结构。
在示例性实施方式中，弯折段61C在基底上的正投影与栅线20在基底上的正投影至少部分交叠，第一连接块61-1在基底上的正投影与栅线20在基底上的正投影至少部分交叠，使得第一引线61与触控电极的连接点位于子像素的非开口区域，以提高子像素的开口率。
如图10b所示，第m2像素行中，第n像素列与第n+1像素列之间的第一引线61的形状与其它相邻像素列之间的第一引线61的形状不同，且第二引线62的形状与其它相邻像素列之间的第二引线62的形状不同。
在示例性实施方式中，第二引线62可以设置有第二连接块62-1，第二连接块62-1被配置为通过过孔与后续形成的另一个触控电极连接。第二连接块62-1可以设置在第二引线62第一方向X的反方向的一侧(朝向第一引线61的方向)，第二连接块62-1的形状可以为向着第一引线61方向凸起的梯形。
在示例性实施方式中，第一引线61可以包括第一直线段61A、第二直线段61B以及位于第一直线段61A和第二直线段61B之间的弯折段61C。弯折段61C的第一端与第一直线段61A连接，弯折段61C的第二端与第二直线段61B连接，弯折段61C的中部可以向着第一方向X的反方向凸起，使得第二连接块62-1可以设置在弯折段61C弯折形成的区域内。
在示例性实施方式中，第二连接块62-1在基底上的正投影与栅线20在基底上的正投影至少部分交叠，使得第二引线61与触控电极的连接点位于子像素的非开口区域，以提高子像素的开口率。
在示例性实施方式中，第一直线段61A、第二直线段61B和弯折段61C可以为相互连接的一体结构。
在示例性实施方式中，第二引线62和第二连接块62-1可以为相互连接的一体结构。
在示例性实施方式中，位于第n像素列与第n+1像素列之间的第一引线61中，第m1像素行和第m2像素行中的第一直线段61A、第二直线段61B和弯折段61C的形状可以基本上相同。
(4)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成有前述图案的基底上，沉积第二绝缘薄膜，通过图案化工艺对第二绝缘薄膜进行图案化，形成覆盖第二导电图案的第二绝缘层图案，第二绝缘层上形成有多个过孔，如图 11a和图11b所示，图11a为图6中A区域的放大图，图11b为图6中B区域的放大图。
在示例性实施方式中，多个过孔可以至少包括设置在每个子像素的连接过孔K。连接过孔K在基底上的正投影可以位于漏电极24在基底上的正投影的范围之内，连接过孔K内的第二绝缘层被刻蚀掉，暴露出漏电极24的表面，连接过孔K被配置为使后续形成的像素电极通过该过孔与漏电极24连接。
在示例性实施方式中，连接过孔K的形状可以为如下任意一种或多种：正方形、矩形、圆形和椭圆形。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成有前述图案的基底上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第二绝缘层上形成第三导电层图案，如图12a和图12b所示，图12a为图6中A区域的放大图，图12b为图6中B区域的放大图。
在示例性实施方式中，第三导电层图案可以至少包括设置在每个子像素中的像素电极40。
在示例性实施方式中，每个子像素中的像素电极40的形状可以为整面状，位于栅线20和数据线30围成的区域内，且像素电极40在基底上的正投影与漏电极24在基底上的正投影至少部分交叠，像素电极40通过连接过孔K与薄膜晶体管的漏电极24连接。
(6)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第三导电图案的第三绝缘层图案，第三绝缘层上形成有多个过孔，如图13a和图13b所示，图13a为图6中A区域的放大图，图13b为图6中B区域的放大图。
在示例性实施方式中，多个过孔可以至少包括设置在第m1像素行、第n像素列中的第一过孔K1和设置在第m2像素行、第n像素列中的第二过孔K2。
在示例性实施方式中，第一过孔K1在基底上的正投影可以位于第一引线61的第一连接块61-1在基底上的正投影的范围之内，第一过孔K1内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第一连接块61-1的表面，第一过孔K1被配置为使后续形成的一个触控电极通过该过孔与第一连接块61-1连接。
在示例性实施方式中，第一过孔K1在基底上的正投影与栅线20在基底上的正投影至少部分交叠，使得第一引线61与触控电极的连接点位于子像素的非开口区域，以提高子像素的开口率。
在示例性实施方式中，第二过孔K2在基底上的正投影可以位于第二引线62的第二连接块62-1在基底上的正投影的范围之内，第二过孔K2内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第二连接块62-1的表面，第二过孔K2被配置为使后续形成的另一个触控电极通过该过孔与第二连接块62-1连接。
在示例性实施方式中，第二过孔K2在基底上的正投影与栅线20在基底上的正投影至少部分交叠，使得第二引线62与触控电极的连接点位于子像素的非开口区域，以提高子像素的开口率。
在示例性实施方式中，第一过孔K1和第二过孔K2的形状可以为如下任意一种或多种：正方形、矩形、圆形和椭圆形。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成有前述图案的基底上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，在第三绝缘层上形成第四导电层图案，如图7a和图7b所示。
在示例性实施方式中，第四导电层图案至少包括规则排布的多个触控电极50，多个触控电极50复用为公共电极。
在示例性实施方式中，覆盖第m1像素行、第n像素列的触控电极50通过第一过孔 K1与第一连接块61-1连接。由于第一连接块61-1与第一引线61连接，因而实现了第一引线61与一个触控电极50的连接，第一引线61可以向该触控电极50提供触控信号或者公共电压信号。
在示例性实施方式中，覆盖第m2像素行、第n像素列的触控电极50通过第二过孔K2与第二连接块62-1连接。由于第二连接块62-1与第二引线62连接，因而实现了第二引线62与另一个触控电极50的连接，第二引线62可以向该触控电极50提供触控信号或者公共电压信号。
在示例性实施方式中，至少一个像素单元中，触控电极50可以包括电极部51和连接部52，电极部51可以设置在像素单元内，即电极部51可以设置在由第一引线61、第二引线62和两条栅线20围成的区域内。连接部52可以设置在相邻的像素单元之间，并与相邻的像素单元内的电极部51连接，将多个像素单元内的多个电极部51连接成一体构成块状的触控电极50。
在示例性实施方式中，连接部52可以设置在第一方向X相邻的像素单元之间，将一个像素行中的多个电极部51连接成一体，或者，连接部52可以设置在第二方向Y相邻的像素单元之间，将一个像素列中的多个电极部51连接成一体，或者，连接部52可以设置在第一方向X相邻的像素单元之间以及第二方向Y相邻的像素单元之间，将多个像素行和多个像素列中的多个电极部51连接成一体。
在示例性实施方式中，电极部51在基底上的正投影与栅线20在基底上的正投影没有交叠，电极部51在基底上的正投影与第一引线61在基底上的正投影没有交叠，电极部51在基底上的正投影与第二引线62在基底上的正投影没有交叠，以减少栅线20、第一引线61和第二引线62传输的信号对触控电极(公共电极)的影响。
在示例性实施方式中，连接部52在基底上的正投影与栅线20在基底上的正投影至少部分交叠，连接部52在基底上的正投影与第一引线61在基底上的正投影至少部分交叠，连接部52在基底上的正投影与第二引线62在基底上的正投影至少部分交叠。
在示例性实施方式中，一个触控电极50的至少一个连接部52可以通过第一过孔K1与第一连接块61-1连接，另一个触控电极50的至少一个连接部52可以通过第二过孔K2与第二连接块62-1连接，使得第一引线61和第二引线62与触控电极的连接点均位于子像素的非开口区域，以提高子像素的开口率。
在示例性实施方式中，像素单元中的电极部51上可以设置有至少一个开口53，开口53内的第四导电薄膜被刻蚀掉，暴露出第三绝缘层。开口53的形状可以为沿着第二方向Y延伸的折线状，使得电极部51形成沿着第一方向X间隔设置的多个条形电极，可以保证面状的像素电极40和条形的公共电极(触控电极)之间形成水平电场。
在示例性实施方式中，基底可以采用玻璃或石英等。第一导电层和第二导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等，第一导电层可以称为栅金属(GATE)层，第二导电层可以称为源漏金属(SD)层。第三导电层和第四导电层可以采用透明导电材料，如氧化铟锡ITO或氧化铟锌IZO等。第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为栅绝缘(GI)层，第二绝缘层可以称为层间绝缘层(ILD)，第三绝缘层可以称为钝化(PVX)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
至此，完成本公开示例性实施例阵列基板的制备。在垂直于阵列基板的平面上，阵列基板可以包括设置在基底上的第一导电层、设置在第一导电层远离基底一侧的第一绝缘层、设置在第一绝缘层远离基底一侧的半导体层、设置在半导体层远离基底一侧的第二导电层、设置在第二导电层远离基底一侧的第二绝缘层、设置在第二绝缘层远离基底一侧的第三导电层、设置在第三导电层远离基底一侧的第四绝缘层、设置在第四绝缘层远离基底一侧的第四导电层。在平行于阵列基板的平面上，阵列基板可以包括多个子像素，每个子像素可以包括薄膜晶体管、像素电极和复用为公共电极的触控电极，薄膜晶体管可以包括栅电极、有源层、第一极和第二极，栅电极与栅线连接，第一极与数据线连接，第二极与像素电极连接，触控电极与第一引线或者第二引线连接，像素电极和公共电极之间形成水平电场。
通过本公开示例性实施例阵列基板的结构和制备过程可以看出，本公开通过在相邻的像素单元之间设置触控引线组，触控引线组可以包括并列设置的第一引线和第二引线，不仅减小了引线数量，增加了子像素的空间，提高了像素开口率，有利于显示装置分辨率的提高，而且由于每条引线均与相应的触控电极通过过孔连接，保证了像素结构的一致性和刻蚀均一性，有利于提高制备工艺的质量。
图14为本公开示例性实施例一种绑定区域和边框区域的平面结构示意图。如图14所示，阵列基板可以包括显示区域100、位于显示区域100一侧的绑定区域200、位于显示区域100远离绑定区域200一侧的上边框区310以及位于显示区域100两侧的侧边框区320。
在示例性实施方式中，显示区域100可以至少包括构成触控阵列的多个触控电极50和构成像素阵列的多个像素单元60，至少一个像素单元60可以包括三个子像素，至少一个子像素可以包括薄膜晶体管10、栅线20、数据线30和像素电极40，薄膜晶体管10分别与栅线20、数据线30和像素电极40连接，触控电极50可以复用为公共电极。
在示例性实施方式中，显示区域100还可以包括多个触控引线组，多个触控引线组分别设置在相邻的像素列之间，至少一个触控引线组可以至少包括并列设置的第一引线61和第二引线62，第一引线61和第二引线62复用为公共电极线，第一引线61可以与奇数的触控行中的触控电极50连接，第二引线62可以与偶数的触控行中的触控电极50连接。
在示例性实施方式中，绑定区域200可以至少包括驱动芯片280和多个引脚。驱动芯片280可以通过多条连接线分别与显示区域中的多条数据线和多条触控引线(第一引线和第二引线)对应连接。在正常显示时，驱动芯片280被配置为向多条数据线和多条触控引线分别提供数据信号和触控信号。
在示例性实施方式中，绑定区域200的多个引脚可以至少包括如下任意一种或多种：第一测试引脚210、第二测试引脚220、第一数据引脚230、第二数据引脚240、第三数据引脚250、开关控制引脚260和栅线控制引脚270。在进行测试时，多个引脚被配置为与外部测试装置绑定连接，使外部测试装置向相应的信号线输出相应的信号。
在示例性实施方式中，第一测试引脚210、第一数据引脚230、开关控制引脚260和栅线控制引脚270可以设置在绑定区域200第一方向X的反方向的一侧，第二测试引脚220、第二数据引脚240、第三数据引脚250和栅线控制引脚270可以设置在绑定区域200的第一方向X的一侧。
在示例性实施方式中，第一测试引脚210、第一数据引脚230、开关控制引脚260和栅线控制引脚270可以沿着第一方向X依次设置，栅线控制引脚270、第二数据引脚240、第三数据引脚250和第二测试引脚220可以沿着第一方向X依次设置。
在示例性实施方式中，上边框区310可以至少包括测试电路。本公开阵列基板将触控引线组设置在相邻的像素单元之间，触控引线组中的多条引线相邻，当工艺制程或者灰尘(Particle)等原因导致相邻引线短路时，或导致触控功能异常。为了在模组之前将此类 不良筛选出来，本公开在上边框区310设置了测试电路，测试电路被配置为对阵列基板的短路不良进行检测。
在示例性实施方式中，测试电路可以包括多个测试单元70，多个测试单元70可以沿着第一方向X依次设置，且多个测试单元70与显示区域100中多个触控列的位置一一对应。
在示例性实施方式中，至少一个测试单元可以至少包括第一测试线71、第二测试线72、第一数据引线73、第二数据引线74、第三数据引线75、开关控制线76、第一开关91、第二开关92、第三开关93、第四开关94和第五开关95。
在示例性实施方式中，开关控制线76、第一数据引线73、第二数据引线74、第三数据引线75、第二测试线72和第一测试线71可以沿着远离显示区域的方向依次设置，且上述信号线均为沿着第一方向X延伸的线形状。
在示例性实施方式中，第三开关93、第四开关94、第五开关95、第一开关91和第二开关92可以沿着第一方向X依次设置。
在示例性实施方式中，第一开关91的第一极与第一测试线71连接，第一开关91的第二极与显示区域100中的第一引线61连接，第一开关91的控制极与开关控制线76连接，即第一测试线71通过第一开关91与显示区域100中的第一引线61连接，第一测试线71被配置为在开关控制线76和第一开关91的控制下向第一引线61传输第一测试信号。
在示例性实施方式中，第二开关92的第一极与第二测试线72连接，第二开关92的第二极与显示区域100中的第二引线62连接，第二开关92的控制极与开关控制线76连接，即第二测试线72通过第二开关92与显示区域100中的第二引线62连接，第二测试线72被配置为在开关控制线76和第二开关92的控制下向第二引线62传输第二测试信号。
在示例性实施方式中，第一测试信号的电压值大于第二测试信号的电压值，或者，第一测试信号的电压值小于第二测试信号的电压值，即第一测试信号的电压值与第二测试信号的电压值不相等。
在示例性实施方式中，第三开关93的第一极与第一数据引线73连接，第三开关93的第二极与显示区域100中第一子像素的数据线30连接，第三开关93的控制极与开关控制线76连接，即第一数据引线73通过第三开关93与显示区域100中的第一子像素的数据线30连接，第一数据引线73被配置为在开关控制线76和第三开关93的控制下向第一子像素的数据线30传输第一数据信号。
在示例性实施方式中，第四开关94的第一极与第二数据引线74连接，第四开关94的第二极与显示区域100中第二子像素的数据线30连接，第四开关94的控制极与开关控制线76连接，即第二数据引线74通过第四开关94与显示区域100中的第二子像素的数据线30连接，第二数据引线74被配置为在开关控制线76和第四开关94的控制下向第二子像素的数据线30传输第二数据信号。
在示例性实施方式中，第五开关95的第一极与第三数据引线75连接，第五开关95的第二极与显示区域100中第三子像素的数据线30连接，第五开关95的控制极与开关控制线76连接，即第三数据引线75通过第五开关95与显示区域100中的第三子像素的数据线30连接，第三数据引线75被配置为在开关控制线76和第五开关95的控制下向第三子像素的数据线30传输第三数据信号。
在示例性实施方式中，第一开关91、第二开关92、第三开关93、第四开关94和第五开关95可以为薄膜晶体管。
在示例性实施方式中，侧边框区320可以至少包括栅极驱动电路330和多条连接线，栅极驱动电路330可以设置在多条连接线靠近显示区域的一侧。
在示例性实施方式中，侧边框区320可以包括左侧边框和右侧边框。左侧边框可以至 少包括栅极驱动电路330、第一连接线81、第三连接线83和第六连接线86，右侧边框可以至少包括栅极驱动电路330、第二连接线82、第四连接线84和第五连接线85。
在示例性实施方式中，设置在左侧边框和右侧边框内的栅极驱动电路330的测试端分别通过连接线与绑定区域200中的栅线控制引脚270连接，栅极驱动电路330的输出端分别与显示区域100中的多条栅线20连接。在进行测试时，栅极驱动电路330的测试端与输出端连通，栅极驱动电路330被配置为向显示区域100中的多条栅线20输出开启电压。
在示例性实施方式中，第一连接线81的第一端与绑定区域200中的第一测试引脚210连接，第一连接线81的第二端向着上边框区310延伸后，与上边框区310中的第一测试线71连接，实现了第一测试线71与第一测试引脚210的连接。
在示例性实施方式中，第二连接线82的第一端与绑定区域200中的第二测试引脚220连接，第二连接线82的第二端向着上边框区310延伸后，与上边框区310中的第二测试线72连接，实现了第二测试线72与第二测试引脚220的连接。
在示例性实施方式中，第三连接线83的第一端与绑定区域200中的第一数据引脚230连接，第三连接线83的第二端向着上边框区310延伸后，与上边框区310中的第一数据引线73连接，实现了第一数据引线73与第一数据引脚230的连接。
在示例性实施方式中，第四连接线84的第一端与绑定区域200中的第二数据引脚240连接，第四连接线84的第二端向着上边框区310延伸后，与上边框区310中的第二数据引线74连接，实现了第二数据引线74与第二数据引脚240的连接。
在示例性实施方式中，第五连接线85的第一端与绑定区域200中的第三数据引脚250连接，第五连接线85的第二端向着上边框区310延伸后，与上边框区310中的第三数据引线75连接，实现了第三数据引线75与第三数据引脚250的连接。
在示例性实施方式中，第六连接线86的第一端与绑定区域200中的开关控制引脚260连接，第六连接线86的第二端向着上边框区310延伸后，与上边框区310中的开关控制线76连接，实现了开关控制线76与开关控制引脚260的连接。
在示例性实施方式中，本公开测试电路的制备可以包括如下操作。
(11)在显示区域形成第一导电层图案时，第一导电层图案还包括位于上边框区的第一测试线71、第二测试线72、第一数据引线73、第二数据引线74、第三数据引线75和控制线组，如图15所示。
在示例性实施方式中，控制线组、第一数据引线73、第二数据引线74、第三数据引线75、第二测试线72和第一测试线71可以沿着远离显示区域的方向依次设置。
在示例性实施方式中，控制线组可以至少包括沿着远离显示区域的方向依次设置的第一控制线76-1、第二控制线76-2、第三控制线76-3、第四控制线76-4和第五控制线76-5。
在示例性实施方式中，第三控制线76-3和第五控制线76-5之间可以设置有多个第一栅极块111和多个第二栅极块112，多个第一栅极块111和多个第二栅极块112的第一端与第三控制线76-3连接，多个第一栅极块111和多个第二栅极块112的第二端与第五控制线76-5，多个第一栅极块111和多个第二栅极块112的中部与第四控制线76-4连接，使得第三控制线76-3、第四控制线76-4和第五控制线76-5通过多个第一栅极块111和多个第二栅极块112连接成一体结构，多个第一栅极块111被配置为作为第一开关91的栅电极，多个第二栅极块112被配置为作为第二开关92的栅电极。
在示例性实施方式中，第四控制线76-4和第五控制线76-5之间可以设置有多个第四栅极块114，多个第四栅极块114的第一端与第四控制线76-4连接，多个第四栅极块114的第二端与第五控制线76-5，多个第四栅极块114被配置为作为第四开关94的栅电极。
在示例性实施方式中，第一控制线76-1和第二控制线76-2之间可以设置有多个第三栅极块113和多个第五栅极块115，多个第三栅极块113和多个第五栅极块115的第一端 与第一控制线76-1连接，多个第三栅极块113和多个第五栅极块115的第二端与第二控制线76-2连接，使得第一控制线76-1和第二控制线76-2通过多个第三栅极块113和多个第五栅极块115连接成一体结构，多个第三栅极块113被配置为作为第三开关93的栅电极，多个第五栅极块115被配置为作为第五开关95的栅电极。
本公开通过采用多条控制线和多个栅极块组成控制线组，可以有效减小开关的占用面积，减小边框宽度，有利于实现窄边框。
(12)在显示区域形成半导体层图案时，半导体层图案还包括位于上边框区的第一有源层121、第二有源层122、第三有源层123、第四有源层124和第五有源层125，如图16所示。
在示例性实施方式中，第一有源层121在基底上的正投影可以位于第一栅极块111在基底上的正投影的范围之内，第一有源层121被配置为作为第一开关91的有源层。
在示例性实施方式中，第二有源层122在基底上的正投影可以位于第二栅极块112在基底上的正投影的范围之内，第二有源层122被配置为作为第二开关92的有源层。
在示例性实施方式中，第三有源层123在基底上的正投影可以位于第三栅极块113在基底上的正投影的范围之内，第三有源层123被配置为作为第三开关93的有源层。
在示例性实施方式中，第四有源层124在基底上的正投影可以位于第四栅极块114在基底上的正投影的范围之内，第四有源层124被配置为作为第四开关94的有源层。
在示例性实施方式中，第五有源层125在基底上的正投影可以位于第五栅极块115在基底上的正投影的范围之内，第五有源层125被配置为作为第五开关95的有源层。
(13)在显示区域形成第二导电层图案时，第二导电层图案还包括位于上边框区的第一源电极131、第二源电极132、第三源电极133、第四源电极134、第五源电极135、第一漏电极141、第二漏电极142、第三漏电极143、第四漏电极144、第五漏电极145、第一搭接块151、第二搭接块152、第三搭接块153、第四搭接块154和第五搭接块155，如图17所示。
在示例性实施方式中，第一源电极131的第一端与第一有源层121连接，第一源电极131的第二端向着远离显示区域的方向延伸后，与第一搭接块151连接，第一搭接块151可以设置在第一测试线71靠近显示区域的一侧，第一搭接块151被配置为与后续形成第一搭接电极连接。第一漏电极141的第一端与第一有源层121连接，第一漏电极141的第二端向着显示区域的方向延伸后，与显示区域的第一引线连接。第一源电极131和第一漏电极141之间形成导电沟道，第一栅极块111、第一有源层121、第一源电极131和第一漏电极141构成第一开关91。
在示例性实施方式中，第二源电极132的第一端与第二有源层122连接，第二源电极132的第二端向着远离显示区域的方向延伸后，与第二搭接块152连接，第二搭接块152可以设置在第二测试线72靠近显示区域的一侧，第二搭接块152被配置为与后续形成第二搭接电极连接。第二漏电极142的第一端与第二有源层122连接，第二漏电极142的第二端向着显示区域的方向延伸后，与显示区域的第二引线连接。第二源电极132和第二漏电极142之间形成导电沟道，第二栅极块112、第二有源层122、第二源电极132和第二漏电极142构成第二开关92。
在示例性实施方式中，第三源电极133的第一端与第三有源层123连接，第三源电极133的第二端向着远离显示区域的方向延伸后，与第三搭接块153连接，第三搭接块153可以设置在第一数据引线73靠近显示区域的一侧，第三搭接块153被配置为与后续形成第三搭接电极连接。第三漏电极143的第一端与第三有源层123连接，第三漏电极143的第二端向着显示区域的方向延伸后，与显示区域中第一子像素的数据线连接。第三源电极133和第三漏电极143之间形成导电沟道，第三栅极块113、第三有源层123、第三源 电极133和第三漏电极143构成第三开关93。
在示例性实施方式中，第四源电极134的第一端与第四有源层124连接，第四源电极134的第二端向着远离显示区域的方向延伸后，与第四搭接块154连接，第四搭接块154可以设置在第二数据引线74靠近显示区域的一侧，第四搭接块154被配置为与后续形成第四搭接电极连接。第四漏电极144的第一端与第四有源层124连接，第四漏电极144的第二端向着显示区域的方向延伸后，与显示区域中第二子像素的数据线连接。第四源电极134和第四漏电极144之间形成导电沟道，第四栅极块114、第四有源层124、第四源电极134和第四漏电极144构成第四开关94。
在示例性实施方式中，第五源电极135的第一端与第五有源层125连接，第五源电极135的第二端向着远离显示区域的方向延伸后，与第五搭接块155连接，第五搭接块155可以设置在第三数据引线75靠近显示区域的一侧，第五搭接块155被配置为与后续形成第五搭接电极连接。第五漏电极145的第一端与第五有源层125连接，第五漏电极145的第二端向着显示区域的方向延伸后，与显示区域中第三子像素的数据线连接。第五源电极135和第五漏电极145之间形成导电沟道，第五栅极块115、第五有源层125、第五源电极135和第五漏电极145构成第五开关95。
(14)在显示区域形成第二绝缘层图案时，第二绝缘层上的多个过孔还包括位于上边框区的第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17、第十八过孔V18、第十九过孔V19、第二十过孔V20，如图18所示。
在示例性实施方式中，第十一过孔V11在基底上的正投影可以位于第一搭接块151在基底上的正投影的范围之内，第十一过孔V11暴露出第一搭接块151的表面，第十一过孔V11被配置为使后续形成的第一搭接电极通过该过孔与第一搭接块151连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影可以位于第二搭接块152在基底上的正投影的范围之内，第十二过孔V12暴露出第二搭接块152的表面，第十二过孔V12被配置为使后续形成的第二搭接电极通过该过孔与第二搭接块152连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影可以位于第三搭接块153在基底上的正投影的范围之内，第十三过孔V13暴露出第三搭接块153的表面，第十三过孔V13被配置为使后续形成的第三搭接电极通过该过孔与第三搭接块153连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影可以位于第四搭接块154在基底上的正投影的范围之内，第十四过孔V14暴露出第四搭接块154的表面，第十四过孔V14被配置为使后续形成的第四搭接电极通过该过孔与第四搭接块154连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影可以位于第五搭接块155在基底上的正投影的范围之内，第十五过孔V15暴露出第五搭接块155的表面，第十五过孔V15被配置为使后续形成的第五搭接电极通过该过孔与第五搭接块155连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影可以位于第一测试线71在基底上的正投影的范围之内，第十六过孔V16暴露出第一测试线71的表面，第十六过孔V16被配置为使后续形成的第一搭接电极通过该过孔与第一测试线71连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影可以位于第二测试线72在基底上的正投影的范围之内，第十七过孔V17暴露出第二测试线72的表面，第十七过孔V17被配置为使后续形成的第二搭接电极通过该过孔与第二测试线72连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影可以位于第一数据引线73在基底上的正投影的范围之内，第十八过孔V18暴露出第一数据引线73的表面，第十八过孔V18被配置为使后续形成的第三搭接电极通过该过孔与第一数据引线73连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影可以位于第二数据引线74 在基底上的正投影的范围之内，第十九过孔V19暴露出第二数据引线74的表面，第十九过孔V19被配置为使后续形成的第四搭接电极通过该过孔与第二数据引线74连接。
在示例性实施方式中，第二十过孔V20在基底上的正投影可以位于第三数据引线75在基底上的正投影的范围之内，第二十过孔V20暴露出第三数据引线75的表面，第二十过孔V20被配置为使后续形成的第五搭接电极通过该过孔与第三数据引线75连接。
第十一过孔V11至第二十过孔V20可以为沿着第一方向X依次设置的多个过孔，以提高连接可靠性。
(15)在显示区域形成第三导电层图案时，第三导电层图案还包括位于上边框区的第一搭接电极161、第二搭接电极162、第三搭接电极163、第四搭接电极164和第五搭接电极165，如图19所示。
在示例性实施方式中，第一搭接电极161的第一端通过第十一过孔V11与第一搭接块151连接，第一搭接电极161的第二端通过第十六过孔V16与第一测试线71连接。
在示例性实施方式中，第二搭接电极162的第一端通过第十二过孔V12与第二搭接块152连接，第二搭接电极162的第二端通过第十七过孔V17与第二测试线72连接。
在示例性实施方式中，第三搭接电极163的第一端通过第十三过孔V13与第三搭接块153连接，第三搭接电极163的第二端通过第十八过孔V18与第一数据引线73连接。
在示例性实施方式中，第四搭接电极164的第一端通过第十四过孔V14与第四搭接块154连接，第四搭接电极164的第二端通过第十九过孔V19与第二数据引线74连接。
在示例性实施方式中，第五搭接电极165的第一端通过第十五过孔V15与第五搭接块155连接，第五搭接电极165的第二端通过第二十过孔V20与第三数据引线75连接。
第一搭接电极161至第五搭接电极165可以为沿着第一方向X依次设置的多个搭接电极，以提高连接可靠性。
至此，完成本公开示例性实施例测试电路的制备，测试电路可以包括多个测试单元，多个测试单元可以沿着第一方向X依次设置，至少一个测试单元可以至少包括第一测试线71、第二测试线72、第一数据引线73、第二数据引线74、第三数据引线75、开关控制线76、第一开关91、第二开关92、第三开关93、第四开关94和第五开关95。
在示例性实施方式中，测试电路对显示区域中多个触控电极进行检测的过程可以包括：
(1)将外部测试装置与绑定区域的多个引脚绑定连接后，外部测试装置分别向栅线控制引脚270提供开启信号，向开关控制引脚260提供导通信号，向第一数据引脚230、第二数据引脚240和第三数据引脚250提供数据信号。在示例性实施方式中，导通信号和开启信号可以是高电平电压(VGH)，数据信号可以是公共基准电压(VCOM)。外部测试装置提供的开启信号使栅极驱动电路330向显示区域中的多条栅线20输出开启电压，显示区域中多个子像素的薄膜晶体管导通。外部测试装置提供的导通信号使上边框区多个测试单元70的第一开关91、第二开关92、第三开关93、第四开关94和第五开关95导通，外部测试装置提供的数据信号分别通过第一数据引线73和导通的第三开关93、第二数据引线74和导通的第四开关94、第三数据引线75和导通的第五开关95分别提供给显示区域的多条数据线30，并通过导通的薄膜晶体管传输到多个子像素的像素电极40，使显示区域中多个子像素的像素电极40充上公共基准电压。本阶段是通过信号提前打开，在第一测试信号和第二测试信号到来之前将像素电极充上公共基准电压。
(2)外部测试装置向第一测试引脚210提供第一测试信号，向第二测试引脚220提供第二测试信号。在示例性实施方式中，第一测试信号可以是第一灰阶电压，第二测试信号可以是第二灰阶电压，第一灰阶电压的电压值可以大于第二灰阶电压的电压值，或者，第一灰阶电压的电压值可以小于第二灰阶电压的电压值。外部测试装置提供的第一测试信号通过第一测试线71和导通的第一开关91提供给显示区域的第一引线61，并传输到与 第一引线61连接的多个触控电极50上，使得与这些触控电极50相对应的多个子像素显示第一灰阶。外部测试装置提供的第二测试信号通过第二测试线72和导通的第二开关92提供给显示区域的第二引线62，并传输到与第二引线62连接的多个触控电极50上，使得与这些触控电极50相对应的多个子像素显示第二灰阶。
在示例性实施方式中，由于显示区域中所有子像素的像素电极40具有公共基准电压，复用为公共电极的触控电极50分别具有第一灰阶电压和第二灰阶电压，因而显示区域中所有子像素分别显示第一灰阶和第二灰阶。
图20和图21为本公开检测电路进行短路检测的示意图，图20为无短路不良时的正常检测画面，图21为有短路不良时的异常检测画面。在示例性实施方式中，第一引线与奇数触控行的触控电极50连接，第二引线与偶数触控行的触控电极50连接。
在示例性实施方式中，当阵列基板上无短路不良时，奇数触控行的触控电极50显示第一灰阶，偶数触控行的触控电极50显示第二灰阶，显示区域实现纵向亮暗相间均匀的显示画面，如图20所示。
在示例性实施方式中，当阵列基板上有短路不良时，如相邻的第一引线和第二引线出现短路点Q，由于此时短路的第一引线和第二引线的电压相同，因而一个奇数行的一个触控电极50与相邻的偶数行的一个触控电极50电压相同，因而相邻的两个触控电极50所在区域显示相同的灰阶，与正常显示画面存在差异，从而可以筛选出不良基板，如图21所示。
图22为本公开检测电路进行短路检测时的检测时序示意图。如图22所示，在示例性实施方式中，为了防止液晶同一方向偏转极化导致画面残像，提供给第一测试线和第二测试线的第一灰阶电压和第二灰阶电压在帧与帧之间进行正负极性翻转。例如，在第M帧，给第一测试线提供第一灰阶电压+Lo，给第二测试线提供第二灰阶电压+Le。在第M+1帧，给第一测试线提供第一灰阶电压-Lo，给第二测试线提供第二灰阶电压-Le。
通过本公开示例性实施例测试电路的结构、制备过程和测试过程可以看出，本公开在相邻的像素单元之间设置2条触控引线，一条触控引线连接奇数触控行的触控电极，另一条触控引线连接偶数触控行的触控电极，通过向2条触控引线分别提供不同的灰阶电压，在阵列基板无短路不良时，多个触控行呈现纵向亮暗相间的显示画面，在阵列基板有短路不良时，纵向相邻的触控电极会显示相同的灰阶，从而可以筛选出阵列基板短路不良。本公开测试电路的结构简单，检测方法简洁，可以有效筛选出不良基板，减少了模组资材损耗，降低了生产成本，提高了良品率。
本公开示例性实施例还提供一种显示装置，显示装置可以包括相对设置的第一基板和第二基板，液晶层设置在第一基板和第二基板之间，第一基板可以采用前述的阵列基板，第二基板可以包括黑矩阵和滤光单元。
在示例性实施方式中，本公开显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
本公开示例性实施例还提供一种采用如上所述阵列基板的阵列基板的检测方法，包括：
向显示区域中的多条栅线提供开启电压，使得显示区域中多个子像素的薄膜晶体管导通；向所述显示区域中的多条数据线提供公共基准电压，使得所述显示区域中多个子像素的像素电极具有公共基准电压；
向所述显示区域中的第一引线提供第一灰阶电压，使得显示区域中与所述第一引线连接的多个触控电极具有第一灰阶电压；向所述显示区域中的第二引线提供第二灰阶电压，使得显示区域中与所述第二引线连接的多个触控电极具有第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述 第二灰阶电压的电压值。
在示例性实施方式中，当所述阵列基板上无短路不良时，一个触控行中的触控电极显示第一灰阶，相邻触控行中的触控电极显示第二灰阶，显示区域呈现纵向亮暗相间的显示画面；当所述阵列基板上有短路不良时，一个触控行中的至少一个触控电极与相邻触控行中的至少一个触控电极显示相同的灰阶。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种阵列基板，包括显示区域，所述显示区域至少包括：构成多个触控行和多个触控列的多个触控电极，以及构成多个像素行和多个像素列的多个像素单元，所述触控单元在所述阵列基板上的正投影与多个像素单元在所述阵列基板上的正投影至少部分交叠，所述像素单元包括多个子像素；至少一个相邻的像素列之间设置有触控引线组，所述触控引线组至少包括并列设置的第一引线和第二引线，所述第一引线与一个触控行中的一个触控电极连接，所述第二引线与相邻触控行中的另一个触控电极连接。
  2. 根据权利要求1所述的阵列基板，其中，至少一个触控列包括沿着所述像素列方向依次设置的N个触控电极，所述触控列在所述阵列基板上的正投影与N/2个像素列在所述阵列基板上的正投影至少部分交叠，位于第i像素列和第i+1像素列之间的第一引线与第2i-1触控行中的触控电极连接，位于第i像素列和第i+1像素列之间的第二引线与第2i触控行中的触控电极连接，N为大于1的偶数，i为大于或等于1、小于或等于N/2的正整数。
  3. 根据权利要求1所述的阵列基板，其中，至少一个像素单元包括沿着所述像素行方向依次设置的第一子像素、第二子像素和第三子像素，所述子像素包括栅线、数据线、薄膜晶体管和像素电极，所述薄膜晶体管分别与所述栅线、数据线和像素电极连接，所述触控电极复用为公共电极，所述第一引线和第二引线复用为公共电极线；所述第一引线设置在所述第三子像素远离所述第一子像素的一侧，所述第二引线设置在所述第一引线远离所述第一子像素的一侧。
  4. 根据权利要求3所述的阵列基板，其中，至少一个像素行中，所述第一引线上设置有第一连接块，所述第一连接块通过第一过孔与一个触控电极连接。
  5. 根据权利要求4所述的阵列基板，其中，至少一个像素行中，所述第一引线至少包括第一直线段、第二直线段以及位于所述第一直线段和第二直线段之间的弯折段，所述弯折段的第一端与所述第一直线段连接，所述弯折段的第二端与所述第二直线段连接，所述弯折段的中部向着远离所述第二引线的方向凸起，所述第一连接块设置在所述弯折段弯折形成的区域内。
  6. 根据权利要求4所述的阵列基板，其中，所述第一连接块在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
  7. 根据权利要求4所述的阵列基板，其中，所述第一过孔在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
  8. 根据权利要求3所述的阵列基板，其中，至少一个像素行中，所述第二引线上设置有第二连接块，所述第二连接块通过第二过孔与另一个触控电极连接。
  9. 根据权利要求8所述的阵列基板，其中，至少一个像素行中，所述第一引线至少包括第一直线段、第二直线段以及位于所述第一直线段和第二直线段之间的弯折段，所述弯折段的第一端与所述第一直线段连接，所述弯折段的第二端与所述第二直线段连接，所述弯折段的中部向着远离所述第二引线的方向凸起，所述第二连接块设置在所述弯折段弯折形成的区域内。
  10. 根据权利要求8所述的阵列基板，其中，所述第二连接块在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
  11. 根据权利要求8所述的阵列基板，其中，所述第二过孔在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠。
  12. 根据权利要求3所述的阵列基板，其中，至少一个像素单元中，所述触控电极包括电极部和连接部，所述电极部设置在所述像素单元内，所述连接部设置在相邻的像素单元之间，且与相邻的像素单元内的电极部连接。
  13. 根据权利要求12所述的阵列基板，其中，至少一个像素单元中，所述电极部在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影没有交叠，所述电极部在所述阵列基板上的正投影与所述第一引线在所述阵列基板上的正投影没有交叠，所述电极部在所述阵列基板上的正投影与所述第二引线在所述阵列基板上的正投影没有交叠。
  14. 根据权利要求12所述的阵列基板，其中，至少一个像素单元中，所述连接部在所述阵列基板上的正投影与所述栅线在所述阵列基板上的正投影至少部分交叠，所述连接部在所述阵列基板上的正投影与所述第一引线在所述阵列基板上的正投影至少部分交叠，所述连接部在所述阵列基板上的正投影与所述第二引线在所述阵列基板上的正投影至少部分交叠。
  15. 根据权利要求12所述的阵列基板，其中，至少一个像素单元中，至少一个连接部通过第一过孔所述第一引线连接，或者，至少一个连接部通过第二过孔与所述第二引线连接。
  16. 根据权利要求1至15任一项所述的阵列基板，其中，所述阵列基板还包括位于所述显示区域一侧的绑定区域以及位于所述显示区域远离所述绑定区域一侧的上边框区；所述绑定区域至少包括多个引脚，所述上边框区至少包括测试电路，所述测试电路通过多条连接线与所述绑定区域的多个引脚对应连接，所述测试电路被配置为对所述阵列基板的短路不良进行检测。
  17. 根据权利要求16所述的阵列基板，其中，所述测试电路包括多个测试单元，多个测试单元与多个触控列的位置相对应；至少一个测试单元包括第一测试线、第二测试线、开关控制线、第一开关和第二开关；所述第一测试线通过所述第一开关与所述显示区域中的第一引线连接，所述第二测试线通过所述第二开关与所述显示区域中的第二引线连接，所述开关控制线与所述第一开关和第二开关的控制端连接；所述第一测试线被配置为在所述开关控制线的控制下向所述第一引线传输第一灰阶电压，所述第二测试线被配置为在所述开关控制线的控制下向所述第二引线传输第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述第二灰阶电压的电压值。
  18. 根据权利要求17所述的阵列基板，其中，所述测试单元还包括第一数据引线、第二数据引线、第三数据引线、第三开关、第四开关和第五开关，所述第一数据引线通过所述第三开关与所述显示区域中第一子像素的数据线连接，所述第二数据引线通过所述第四开关与所述显示区域中第二子像素的数据线连接，所述第三数据引线通过所述第五开关与所述显示区域中第三子像素的数据线连接，所述开关控制线与所述第三开关、第四开关和第五开关的控制端连接；所述第一数据引线、第二数据引线和第三数据引线被配置为在所述开关控制线的控制下向所述显示区域的数据线传输公共基准电压。
  19. 一种显示装置，包括如权利要求1至18任一项所述的阵列基板。
  20. 一种采用如权利要求1至18任一项所述阵列基板的阵列基板的检测方法，包括：
    向显示区域中的多条栅线提供开启电压，使得显示区域中多个子像素的薄膜晶体管导通；向所述显示区域中的多条数据线提供公共基准电压，使得所述显示区域中多个子像素的像素电极具有公共基准电压；
    向所述显示区域中的第一引线提供第一灰阶电压，使得显示区域中与所述第一引线连接的多个触控电极具有第一灰阶电压；向所述显示区域中的第二引线提供第二灰阶电压，使得显示区域中与所述第二引线连接的多个触控电极具有第二灰阶电压；所述第一灰阶电压的电压值大于所述第二灰阶电压的电压值，或者，所述第一灰阶电压的电压值小于所述第二灰阶电压的电压值。
  21. 根据权利要求20所述的检测方法，其中，当所述阵列基板上无短路不良时，一 个触控行中的触控电极显示第一灰阶，相邻触控行中的触控电极显示第二灰阶，显示区域呈现纵向亮暗相间的显示画面；当所述阵列基板上有短路不良时，一个触控行中的至少一个触控电极与相邻触控行中的至少一个触控电极显示相同的灰阶。
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