WO2024045262A1 - 半导体结构以及存储器 - Google Patents

半导体结构以及存储器 Download PDF

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Publication number
WO2024045262A1
WO2024045262A1 PCT/CN2022/123987 CN2022123987W WO2024045262A1 WO 2024045262 A1 WO2024045262 A1 WO 2024045262A1 CN 2022123987 W CN2022123987 W CN 2022123987W WO 2024045262 A1 WO2024045262 A1 WO 2024045262A1
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Prior art keywords
gate
bit line
active area
active
along
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English (en)
French (fr)
Inventor
高毅成
车载龙
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/451,154 priority Critical patent/US12575092B2/en
Publication of WO2024045262A1 publication Critical patent/WO2024045262A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a memory.
  • Dynamic Random Access Memory includes storage cells (storage bits) arranged in an array. Each memory cell includes a transistor and a capacitor. The transistor acts as a switch between the capacitor and the bit line and can be activated by the word line (WL, Word Line) coupled to the control end of the transistor. The memory cell can store binary information as a capacitor. of charge.
  • Dynamic random access memory not only includes multiple memory cells arranged in a repeated array, but also includes a bit line selection unit used to select the bit line (BL, Bit Line) that performs read and write operations.
  • the bit line selection unit controls the bit line BL to turn on or Close, that is, control whether to perform read and write operations on the memory cell through this bit line.
  • the design of bit line selection cells faces many challenges.
  • embodiments of the present disclosure provide a semiconductor structure and a memory.
  • a semiconductor structure including:
  • a plurality of active areas are arranged in an array along an orthogonal first direction and a second direction, the first direction being parallel to the direction in which the active areas extend;
  • the bit line selection unit includes a first gate, a second gate, a third gate and a fourth gate respectively located on the four active regions adjacent to each other, the first gate and the The second gate extends along the second direction and intersects the first node, the third gate and the fourth gate extend along the second direction and intersects the second node; and a connecting line, the A connecting line connects the first node and the second node and extends along the first direction;
  • each bit line including a first part and a second part extending along the second direction and offset in the first direction, and connecting the first part and the connection part of the second part, each bit line is connected to one of the active areas, the active areas connected to different bit lines are different, and the first part of any one of the bit lines is connected to the adjacent bit line.
  • the second part of the line lies on the same straight line parallel to said second direction.
  • the bit line selection unit further includes: a conductive contact located on any one of the first gate, the second gate, the third gate and the fourth gate and close to the connection line .
  • the orthographic projection of the conductive contact on the plane where the active area is located is in the shape of a strip.
  • the orthographic projection of the conductive contact on the plane of the active area is located within the orthographic projection of any gate on the plane of the active area and is in contact with the bit line on the active area.
  • the orthographic projections of the planes are separated from each other.
  • the bit line selection unit further includes: a bit line selection line connected to the conductive contact and extending along the second direction, the orthographic projection of the bit line selection line on the plane where the active area is located The orthographic projections of the bit lines on the plane of the active area are separated from each other.
  • four active areas adjacent to each other among the plurality of active areas include a first active area, a second active area, a third active area and a fourth active area, and the first active area
  • the gate electrode is located on the first active area
  • the second gate electrode is located on the second active area
  • the third gate electrode is located on the third active area
  • the fourth gate electrode located on the fourth active area
  • the first node is located between the first active area and the second active area, and the second node is located between the third active area and the fourth active area.
  • the plurality of bit lines include a first bit line, a second bit line, a third bit line and a fourth bit line arranged sequentially along the first direction.
  • the first part of the first bit line and the first bit line are The second part of the second bit line is on the same straight line parallel to the second direction, and the first part of the third bit line and the second part of the fourth bit line are on the same straight line parallel to the second direction. on the same straight line.
  • the spacing between the first bit line, the second bit line, the third bit line and the fourth bit line is equal.
  • the bit line selection unit further includes: a source region and a drain region located on both sides of the gate corresponding to each of the four adjacent active regions; the first bit line and the The first gate is connected to the source region or the drain region on the side close to the connection line, and the second bit line is connected to the source region or the drain region on the side of the second gate close to the connection line, so The third bit line is connected to the source region or the drain region on a side of the third gate close to the connection line, and the fourth bit line is connected to a side of the fourth gate close to the connection line.
  • Source or drain connection is
  • the total size of the orthographic projection of the first bit line, the second bit line, the third bit line and the fourth bit line on the plane where the active area is located along the first direction is smaller than the first bit line.
  • the first gate, the second gate, the third gate and the fourth gate all have the same size along the second direction.
  • the gate electrode and the fourth gate electrode have the same size along the first direction.
  • the size of the connecting line along the second direction is greater than or equal to the size of the first gate, the second gate, the third gate and the fourth gate along the first direction.
  • the semiconductor structure includes a plurality of bit line selection units, and two bit line selection units adjacent along the first direction share two active regions adjacent along the second direction.
  • a memory including:
  • Embodiments of the present disclosure provide a semiconductor structure and a memory.
  • the semiconductor structure formed includes a plurality of active regions, a bit line selection unit and a plurality of bit lines; wherein, the bit line selection unit includes a first gate, a second gate, both extending in the second direction. electrode, the third gate electrode and the fourth gate electrode and the connection line extending along the first direction perpendicular to the second direction, and the first gate electrode and the second gate electrode are connected to the first node, the third gate electrode and the fourth gate electrode are connected to the first node.
  • the gate is connected to the second node; one end of the connection line is connected to the first node, and the other end is connected to the second node.
  • each gate and connection line included in the bit line selection unit in the embodiment of the present disclosure constitute a " H"-shaped
  • the "H"-shaped bit line selection unit can effectively reduce the difficulty of process production, especially it is helpful to help optical proximity correction (OPC, Optical Proximity Correction) improve the actual shape of the bit line selection unit , effectively improving product output and yield;
  • OPC optical proximity correction
  • multiple bit lines are arranged along the first direction; each bit line includes a first part and a second part that extend along the second direction and are misaligned along the first direction
  • each bit line is connected to an active area, and the active areas connected to different bit lines are different.
  • bit lines in each embodiment of the present disclosure is flipped 90 degrees. "Z" shape, and the main body of the bit line in each active area is straight.
  • the straight main body of the bit line can effectively reduce the coupling effect and noise between adjacent bit lines, thereby improving the performance of the semiconductor structure .
  • Figure 1 is a partial circuit schematic diagram of a memory provided by an embodiment of the present disclosure
  • Figure 2 is a schematic layout diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3a is a schematic layout diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 3b is a schematic plan view of the semiconductor structure provided in Figure 3a after optical proximity effect correction and etching processes;
  • Figure 3c is another plan view of the semiconductor structure provided in Figure 3a after optical proximity effect correction and etching processes;
  • FIGS. 4a-4d are four layout schematic diagrams of another semiconductor structure provided by embodiments of the present disclosure.
  • Figure 4e is a schematic plan view of the semiconductor structure provided in Figure 4a after optical proximity effect correction and etching processes.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • first and second are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or two and unless otherwise expressly and specifically limited.
  • connection In the embodiments of the present disclosure, unless otherwise explicitly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a removable connection. Detachable connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.
  • Figure 1 is a partial circuit schematic diagram of a memory provided by an embodiment of the present disclosure.
  • the memory 100 includes a word line (WL, Word Line), a bit line (BL, Bit Line), a complementary bit line (BLB, Bit Line Bar), storage unit 110, sense amplifier (SA, Sense Amplifier) 120, equalizer 130 and bit line selection unit 140 (or column selector).
  • WL word line
  • BL bit line
  • B complementary bit line
  • SA sense amplifier
  • equalizer 130 equalizer
  • bit line selection unit 140 or column selector
  • the memory unit 110 has been described before and will not be described again;
  • the sense amplifier 120 is connected between the bit line BL and the complementary bit line BLB, and is used to detect and amplify the voltage difference on a pair of bit lines BL and complementary bit lines BLB;
  • the equalizer 130 is located between the bit line BL and the complementary bit line BLB, where the equalizing unit (EQ, Equalizer) is configured to equalize the voltages of the bit line and the complementary bit line, and the isolation unit (ISO, Isolater) is configured to isolate the bit line and the complementary bit.
  • the offset cancellation unit (OC, Offset Cancel) is configured to eliminate the characteristic difference of different transistors connected to the bit line and the reference bit line;
  • the bit line selection unit 140 is configured to select the bit line BL that performs read and write operations, and controls The bit line BL is turned on or off, that is, it controls whether to perform read or write operations on the memory cell 110 through this bit line.
  • FIG. 2 is a schematic layout diagram of a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 2, the number of transistors corresponding to the bit line selection unit is 4, and the gates of the four transistors are connected to the bit line selection line (CSL, Column Select Line). The transistors corresponding to the bit line selection unit in Figure 2 The number is only used as an example and is not used to limit the number of transistors corresponding to the bit line selection unit in the embodiment of the present disclosure.
  • the active areas of the transistors corresponding to the bit line selection units are arranged in an array along the orthogonal first direction and the second direction, and the first direction is parallel to the direction in which the active areas extend.
  • the first direction mentioned here may be the X-axis direction
  • the second direction mentioned here may be the Y-axis direction, where the four active areas 201, 202, 203, and 204 are adjacent to each other.
  • the bit line selection unit includes a first part 205 located on the active area 201 and the active area 202, a second part 206 located on the active area 203 and the active area 204, and a second part 206 located outside the active area. And there is a third part 207 that is only close to one side of the active area.
  • the third part shown in Figure 2 is located on one side close to the active area 201 and active area 203.
  • the bit line selection unit forms an inverted "U" shape.
  • the third part can also be located close to one side of the active area 202 and the active area 204. At this time, the bit line selection unit forms a "U" shape.
  • both the first part 205 and the second part 206 include two gates connected together
  • the third part includes a conductive connection line
  • the bit line selection unit also includes a conductive contact 208 located in the middle of the third part 207.
  • the contact 208 is connected to the bit line select line CSL and provides an electrical signal to the bit line select unit through the bit line select line.
  • the four bit lines 209, 210, 211, and 212 connected to the transistors corresponding to the bit line selection unit are arranged along the X-axis direction and extend along the Y-axis direction.
  • the bit lines 209 include strip-shaped graphics and protrusions extending along the Y-axis direction. Part 209a, the orthographic projection of the protruding part 209a of the bit line 209 on the plane where the active area is located falls into the active area 202; the bit line 210 includes a long strip shape extending along the Y-axis direction and a staggered bent part 210a.
  • the orthographic projection of the line 210 on the plane where the active area is located falls into the active area 201, and the orthographic projection of the offset bending part 210a on the plane where the active area is located is offset from the protruding part 209a of the bit line 209 in the X-axis direction, or That is to say, the orthographic projection of the offset and bent portion 210a on the plane where the active area is located does not coincide with the active area;
  • the bit line 212 includes a long strip shape extending along the Y-axis direction and a protruding portion 212a.
  • the protruding portion 212a of the bit line 212 is in The orthographic projection of the plane where the active area is located falls into the active area 203; the bit line 211 includes a long strip shape extending along the Y-axis direction and a staggered bent portion 211a.
  • the orthographic projection of the bit line 211 on the plane where the active area is located Part of it falls into the active area 204.
  • the projection of the offset and bent portion 211a in the plane where the active area is located is offset from the protruding portion 212a of the bit line 212 in the X-axis direction. In other words, the offset and bent portion 211a is located in the active area.
  • the orthographic projection of the plane does not coincide with the active area.
  • the distance between the conductive contact and the transistor close to the third part and the transistor far away from the third part are different. At this time, the distance between the conductive contact and the transistor far away from the third part is different.
  • the resistance between the transistors in the third part of the line selection unit is large, which will cause a voltage drop problem, that is to say, the voltage on the transistors close to the third part will be greater than the voltage on the transistors far away from the third part; with this At the same time, the difference in distance between the conductive contact and the transistor will also cause time delay, which is not conducive to the precise control of the bit line selection unit.
  • bit lines with protruding parts or bit lines with dislocated and bent parts and adjacent bit lines is relatively close, which may easily cause coupling phenomena and noise phenomena between bit lines.
  • the performance of the bit line selection cells thus produced is poor.
  • embodiments of the present disclosure disclose a slant "H" shaped bit line selection unit, as shown in Figure 3a, which is a schematic layout diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • the active areas in the multiple transistors corresponding to the bit line selection unit are arranged in an array.
  • the active areas when the active areas are arranged, two adjacent active areas are arranged in rows. There is a certain dislocation along the X-axis direction.
  • the four active areas 401, 402, 403, and 404 are adjacent to each other, and there is a certain gap between the active areas 402, 404 and the active areas 401, 403 in the positive direction of the X-axis. dislocation.
  • the staggered arrangement of the active areas along the positive direction of the X-axis in Figure 3a is only used as an example and is not used to limit the staggered arrangement of the active areas along the positive or negative direction of the X-axis.
  • the bit line selection unit includes a first gate 406 located in the first active region 401, a second gate 407 located in the second active region 402, and a third gate located in the third active region 403.
  • electrode 408 the fourth gate electrode 409 located in the fourth active region 404, the first connection line 410 connecting the first gate electrode 406 and the second gate electrode 407, the third gate electrode 408 and the fourth gate electrode 409 connecting.
  • the bit line selection unit Since the first gate 406, the second gate 407, the third gate 408 and the fourth gate 409 of the bit line selection unit all extend along the Y-axis direction, and the first gate 406 and the second gate 407 The third gate 408 and the fourth gate 409 are misaligned along the positive direction of the X-axis. The misalignment direction is the same as the misalignment direction between the active regions.
  • the bit line selection unit also includes a first connection line 410 connecting the first gate 406 and the second gate 407, and a third gate 408 and the fourth gate 409.
  • the gates and connection lines included in the bit line selection unit form an "H" shape with a certain tilt angle.
  • bit line selection unit also includes a conductive contact 417 located on the first connection line 410 or the second connection line 411 to provide an electrical signal to the bit line selection unit.
  • the four bit lines 413, 414, 415, and 416 connected to the transistors corresponding to the bit line selection unit are arranged along the X-axis direction and extend along the Y-axis direction to form a straight line.
  • the orthographic projection of the part of the bit line 413 close to the first gate 406 on the plane where the active area is located falls on the first active area 401; the orthographic projection of the part of the bit line 414 close to the second gate 407 on the plane of the active area.
  • the orthographic projection of a part of the bit line 415 close to the third gate 408 on the plane of the active area falls on the third active area 403; the part of the bit line 415 close to the fourth gate 407 A part of the orthographic projection on the plane where the active area is located falls on the fourth active area 404 .
  • the special shape of the inclination angle in this embodiment brings great difficulty to the manufacturing process. It is difficult to accurately connect the first connection line 410, the second connection line 411 and the third connection line 412. Moreover, the "H"-shaped bit line selection unit formed with a certain tilt angle is still somewhat different from its actual shape after OPC correction, which affects the device performance.
  • Figure 3b is a schematic plan view of the semiconductor structure provided in Figure 3a after optical proximity effect correction and etching processes; as shown in Figure 3a, the first connection line 410 in the bit line selection unit is on the plane where the first active area 401 is located The orthographic projection of does not intersect with the first active area 401, but the first connection line after optical proximity effect correction and etching process is shown in Figure 3b. It can be seen that the first connection line 410 is in the first active area. The orthographic projection of the plane where the area 401 is located overlaps with the first active area 401, and the overlapping part is shown as 418 in Figure 3b. This overlapping part causes the transistor channel where the first gate 406 of the bit line selection line is located to become wider and the performance to deteriorate. .
  • the conductive contacts located on the first connection line or the second connection line of the bit line selection unit may slip out.
  • the conductive contacts may be offset.
  • FIG 3b although most of the conductive contacts 417 are located on the second connection line of the bit line selection unit, there are still a few parts that are not on the bit line selection unit.
  • the portion located between the third active region 403 and the fourth active region 404 is prone to leakage. What is worse is that if the offset part of the conductive contact 417 is not only between the active area 403 and the active area 404, but also offsets some in the direction of the fourth active area, as shown in Figure 3c, it falls to the fourth active area. In the active area 404, not only current leakage may occur, but also a short circuit may occur, thus causing a greater problem.
  • Semiconductor structures include:
  • a plurality of active areas are arranged in an array along an orthogonal first direction and a second direction, and the first direction is parallel to the direction in which the active areas extend;
  • the bit line selection unit includes a first gate, a second gate, a third gate and a fourth gate respectively located on four active areas adjacent to each other.
  • the first gate and the second gate are along the Two directions extend and intersect at the first node, the third gate and the fourth gate extend along the second direction and intersect at the second node; and a connection line, the connection line connects the first node and the second node and extends along the first direction. ;
  • a plurality of bit lines are arranged along the first direction, each bit line includes a first part and a second part that extend along the second direction and are offset in the first direction, and a connection part connecting the first part and the second part, each The bit lines are connected to an active area. Different bit lines are connected to different active areas. The first part of any bit line and the second part of an adjacent bit line are on the same straight line parallel to the second direction.
  • Figures 4a-4d are four layout schematic diagrams of another semiconductor structure provided by embodiments of the present disclosure.
  • Figure 4e is a plan view of the semiconductor structure provided in Figure 4a after optical proximity effect correction and etching processes.
  • the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to Figures 4a-4e.
  • the first direction is parallel to the direction in which each active area extends
  • the second direction is perpendicular to the first direction and parallel to the plane where the active areas are located.
  • the first direction may be a direction extending along the X-axis
  • the second direction may be a direction extending along the Y-axis.
  • bit line selection unit in the embodiment of the present disclosure may correspond to four transistors or a greater number of transistors, such as eight.
  • Figures 4a to 4e only show the case where the bit line selection unit corresponds to four transistors. The illustrations in Figures 4a to 4e are not used to limit the number of transistors corresponding to the bit line selection unit in the embodiment of the present disclosure.
  • the active area and the bit line selection unit are described side by side. However, in actual applications, the active area may actually be classified into the bit line selection unit.
  • each active area may be arranged in an array along the first direction and the second direction, and different active areas are separated by an insulating structure (such as a shallow trench isolation structure, STI), and each active area Extending along the first direction, the shape of each active area includes a strip shape, and the strip shape may be a right-angled strip shape or a rounded strip shape.
  • each active area extends along the X-axis direction, and the shape of each active area is a right-angled strip.
  • the bit line selection unit includes a plurality of gates corresponding to the transistors, each gate is along the Y-axis direction and each gate spans an active region.
  • the plurality of gates may include a first gate 506, a second gate 507, a third gate 508, and a fourth gate 509.
  • One end of the first gate 506 is in contact with the second gate.
  • One end of the electrode 507 intersects at a first intersection point, and one end of the third gate electrode 508 intersects one end of the fourth gate electrode 509 at a second intersection point.
  • the first gate 506 , the second gate 507 , the third gate 508 and the fourth gate 509 all have the same size along the second direction.
  • the first gate 506 , the second gate 507 , The sizes of the third gate 508 and the fourth gate 509 along the first direction are the same.
  • one end of the first gate 506 away from the second gate 507 is flush with an end of the third gate 508 away from the fourth gate 509 along the first direction, and the second gate 507 is away from the first gate 506
  • One end of the fourth gate 509 is flush with an end of the fourth gate 509 away from the third gate 508 along the first direction.
  • the bit line selection unit further includes a connection line 510 extending along the X-axis direction, specifically a conductive connection line, and the connection line 510 electrically connects the first intersection point and the second intersection point.
  • the size of the connecting line 510 along the second direction is greater than or equal to the size of the first gate 506 , the second gate 507 , the third gate 508 and the fourth gate 509 along the first direction.
  • the materials of the first gate 506 , the second gate 507 , the third gate 508 and the fourth gate 509 and the connection line 510 include but are not limited to polysilicon (Poly).
  • four adjacent active areas among the plurality of active areas include a first active area 501, a second active area 502, a third active area 503, and a fourth active area 504,
  • the first gate 506 is located on the first active region 501
  • the second gate 507 is located on the second active region 502
  • the third gate 508 is located on the third active region 503
  • the fourth gate 509 is located on the fourth Active area 504 on;
  • the first node is located between the first active area 501 and the second active area 502
  • the second node is located between the third active area 503 and the fourth active area 504 .
  • the first node is located on the insulating structure between the first active area 501 and the second active area 502
  • the second node is located on the insulating structure between the third active area 503 and the fourth active area 504 .
  • the arrangement of the first gate 506 , the second gate 507 , the third gate 508 and the fourth gate 509 as well as the connection lines 510 form a positive "H" shape, and the layout shape is straight and symmetrical. It can be understood that during manufacturing, the first gate 506 spanning the first active region 501 and the second gate 507 spanning the second active region 502 are on the same straight line along the second direction and may be formed together; The third gate 506 spanning the third active region 503 and the fourth gate 507 spanning the fourth active region 504 are on the same straight line along the second direction and can be formed together; the connecting line 510 is straight along the first direction. Line, manufacturing is also relatively simple. Obviously, the manufacturing process corresponding to the "H"-shaped arrangement is less difficult and the process is relatively simple compared to the manufacturing process corresponding to the "H"-shaped arrangement with a certain tilt angle in the bit line selection unit in Figure 4a.
  • FIG. 4e the plan view of the semiconductor structure after optical proximity effect correction and etching process is shown in Figure 4e.
  • the gates and connecting lines in the bit line selection unit have been corrected by OPC, they are somewhat different from the actual shapes in Figure 4a.
  • the orthographic projection of the connection line between the third gate 508 and the fourth gate 509 on the plane where the third active region 503 is located does not overlap with the third active region 503.
  • the linear shape of the third gate 508 is still maintained. Therefore, as shown in FIG. 3b , the orthographic projection of the first connection line 410 of the bit line selection unit on the plane where the first active area 401 is located does not overlap with the first active area 401 .
  • the source regions 401 overlap, resulting in channel widening that affects device performance.
  • each of the plurality of bit lines may include three parts, namely, a first part, a second part, and a connection part connecting the first part and the second part.
  • the plurality of bit lines include a first bit line, a second bit line, a third bit line and a fourth bit line sequentially arranged along the first direction.
  • the plurality of bit lines include a first bit line 511, a second bit line 512, a third bit line 513 and a fourth bit line 514 arranged sequentially along the X-axis direction;
  • the first bit line 511 It includes a first portion 511a and a second portion 511b that both extend along the Y-axis direction and are offset in the X-axis direction, and a first connecting portion 511c that connects the first portion 511a and the second portion 511b;
  • the second bit line 512 includes The first part 512a and the second part 512b extend and are offset in the X-axis direction, and the second connecting part 512c connects the first part 512a and the second part 512b;
  • the third bit line 513 includes both extending in the Y-axis direction and in the X-axis direction.
  • the first portion 513a and the second portion 513b are offset and the third connection portion 513c connects the first portion 513a and the second portion 513b;
  • the fourth bit line 514 includes a first portion 514a and an offset portion 513a and 513b that both extend along the Y-axis direction and are offset in the X-axis direction.
  • the second part 514b and the fourth connecting part 514c connecting the first part 514a and the second part 514b.
  • the connection portion in each bit line may extend along the first direction or may extend along the third direction.
  • the third direction may be any direction that intersects both the first direction and the second direction.
  • the first portion 511a of the first bit line 511 and the second portion 512b of the second bit line 512 are on the same straight line parallel to the second direction
  • the first portion 511a of the third bit line 513 is on the same straight line parallel to the second direction
  • the portion 513a and the second portion 514b of the fourth bit line 514 are on the same straight line parallel to the second direction.
  • the first portion 512a of the second bit line 512 and the second portion 513b of the third bit line 513 are also on the same straight line parallel to the second direction.
  • the orthographic projection of one of the first part or the second part of each bit line on the plane where the active area is located falls within the corresponding active area. Therefore, when the active areas are aligned along the first direction and the second direction, , each bit line can connect to the same corresponding position in the active area.
  • the first part 511a of the first bit line 511 and the second part 512b of the second bit line 512 may not be on the same straight line parallel to the second direction, but may be slightly offset; the third bit line The first part 513a of 513 and the second part 514b of the fourth bit line 514 are not on the same straight line parallel to the second direction, but are slightly misaligned.
  • each bit line can connect to a slightly misaligned corresponding position in the active area.
  • each bit line since the first part and the second part, the main components of each bit line, are straight lines, there are no protruding parts and misaligned bent parts as shown in Figure 2, and the coupling phenomenon between two adjacent bit lines does not exist. And the noise phenomenon will be greatly reduced.
  • the performance of the transistor where each gate is located can be guaranteed to be basically the same as much as possible, which is beneficial to each memory cell reading data. The differences tend to be smaller.
  • the first bit line, the second bit line, the third bit line, and the fourth bit line are all equally spaced.
  • the distance between two adjacent bit lines is equal, which can ensure that the parameters of each bit line, such as parasitic capacitance, are more consistent, which is beneficial to the uniformity of the read and write operations of each memory cell.
  • the total size of the orthographic projection of the first bit line, the second bit line, the third bit line and the fourth bit line on the plane where the active area is located along the first direction is smaller than the first gate electrode, the second gate electrode and the fourth bit line.
  • the total size of the orthographic projection of the first bit line, the second bit line, the third bit line and the fourth bit line on the plane where the active area is located along the first direction can be understood with reference to L1 in Figure 4a.
  • the first gate The total size along the first direction of the orthographic projection of the electrode, the second gate electrode, the third gate electrode and the fourth gate electrode on the plane where the active area is located can be understood with reference to L2 in Figure 4a.
  • L1 is smaller than L2 to ensure that in each bit line corresponding to a bit line selection unit, the orthographic projection of the part not connected to the active area falls within the orthographic projection corresponding to each gate of the bit line selection unit or Falling within the insulating structure between adjacent active regions, such that the bit line does not affect the outside 527 of each gate of the bit line selection unit (such as the first gate, the second gate, the third gate and the fourth gate) The active area on the side far away from the connection line) the connection between the active area and the LIO.
  • the bit line selection unit further includes: a source region and a drain region located on both sides of the corresponding gate in each of the four adjacent active regions; the first bit line and the first gate
  • the source area or the drain area on the side close to the connection line is connected, the second bit line is connected to the source area or the drain area on the side of the second gate close to the connection line, the third bit line is connected to the third gate electrode close to the connection line.
  • the source region or the drain region on one side is connected, and the fourth bit line is connected to the source region or the drain region on the side of the fourth gate close to the connection line.
  • bit lines are respectively connected to the source area or the active area on the side of the first gate, the second gate, the third gate and the fourth gate close to the connection line inside each gate of the bit line selection unit.
  • the drain area is connected.
  • the source in the active area outside each gate of the bit line selection unit that is, the side of the first gate, the second gate, the third gate and the fourth gate away from the connection line.
  • the area or drain area is connected to the LIO.
  • the semiconductor structure includes a plurality of bit line selection units, and two bit line selection units adjacent along the first direction share two active regions adjacent along the second direction.
  • the semiconductor structure may include a plurality of bit line selection units, the plurality of bit line selection units are arranged in an array, and the gate electrodes of two adjacent bit line selection units along the first direction share a common active region.
  • the bit line selection unit where the fifth gate 526 is located is adjacent to the bit line selection unit where the first gate 506 is located in the X-axis direction, and the two bit line selection units share the first active In area 501, the transistor where the fifth gate electrode 526 is located and the transistor where the first gate electrode 506 is located share the source or drain electrode in the active area 507 in the fifth gate electrode 526 and the first gate electrode 506, which can effectively To shrink the area occupied by transistors and reduce the size of semiconductor structures.
  • the bit line selection unit further includes: a conductive contact 523 located on any one of the first gate, the second gate, the third gate and the fourth gate and close to the connection line.
  • the conductive contact 523 in Figure 4a is located at the first gate and close to the connection line; the conductive contact 523 in Figure 4b is located at the second gate and close to the connection line; the conductive contact in Figure 4c 523 is located at the third gate and close to the connection line; the conductive contact 523 in Figure 4d is located at the fourth gate and close to the connection line.
  • the conductive contact 523 is located at the first gate and close to the connecting line.
  • the relative distance between the conductive contact 523 and the gates of the four transistors is relatively balanced, which can effectively avoid the problem shown in Figure 2.
  • the position of the conductive contact is such that the distance between the conductive contact and the gate electrodes of two of the transistors is significantly further than that of the gate electrodes of the other two transistors.
  • the conductive contact when the conductive contact supplies power to the four transistors, it does not pass through the gates of other transistors, which is beneficial to reducing the voltage drop and delay problems caused by the operation of other transistors.
  • the conductive contact 523 it is better for the conductive contact 523 to be a little further down as shown in Figure 4a, right in the middle of the first gate and the second gate, so that the relative distance from the gates of the four transistors is further. balanced.
  • the bit line located in the "H" type bit line selection unit has a connecting portion connecting the first part and the second part.
  • the bending of this part is related to the position of the conductive contact 523.
  • the conductive contact 523 is located The position of the first gate and close to the connecting line, then the first part 511a of the first bit line 511 close to the conductive contact 523 is located in the active area in the orthographic projection of the plane where the active area is located, and the second part of the first bit line 511
  • the orthographic projection of 511b on the plane where the active area is located is located within the orthographic projection of the second gate 507 on the plane where the active area is located.
  • the bending of the first connecting portion 511c connecting the first part 511a and the second part 511b of the bit line is just such that The second part 511b of the first bit line 511 is closer to the second gate 507.
  • the connecting parts of the first part and the second part of each bit line are parallel to each other, so that each bit line is flipped 90 degrees "Z"
  • the fonts are arranged in sequence. If the conductive contact 523 is moved downward to a position right between the first gate and the second gate, and the position of the bit line remains unchanged, there is a gap between the conductive contact 523 and the first connection portion of the first bit line. The space is too small, short circuit and other problems may occur.
  • the bit line position will be moved downward as a whole, then most of the orthographic projections of the third connection portion 513c of the third bit line 513 and the fourth connection portion 514c of the fourth bit line 514 on the plane where the active area is located are It will fall in the fourth active area 504, which will intensify the coupling effect between bit lines and the noise effect. thereby reducing the performance of the semiconductor structure.
  • the orthographic projection of the conductive contact on the plane where the active area is located is in the shape of a strip.
  • the strip shape of the conductive contact 523 is such that the size along the Y-axis direction is larger than the size along the X-axis direction, because the narrow size in the X-axis direction is conducive to the arrangement of the conductive contact.
  • the front projection can more conveniently fall within the front projection of the first gate in the active area, effectively reducing the risk of the conductive contact slipping out as shown in Figure 3b; at the same time, it also reduces the distance between the conductive contact and the active area. area contact, causing the risk of short circuit.
  • the orthographic projection of the conductive contact on the plane of the active area is located within the orthographic projection of any gate on the plane of the active area and is separated from the orthographic projection of the bit line on the plane of the active area.
  • the orthographic projection of the conductive contact on the plane of the active area is located within the orthographic projection of any gate on the plane of the active area, which can ensure good contact between the conductive contact and the corresponding gate, while avoiding the risk of short circuit and leakage.
  • the orthographic projection of the conductive contact 523 on the plane of the active area is located within the orthographic projection of any gate on the plane of the active area, and the orthographic projection of the conductive contact 523 is different from the orthographic projection of any active area. coincide.
  • the bit line selection unit further includes: a bit line selection line 524, which is connected to the conductive contact and extends along the second direction.
  • the orthographic projection of the bit line selection line on the plane where the active area is located is the same as the bit line on the active area.
  • the orthographic projections of the planes are separated from each other.
  • bit line selection line 524 is used to transmit the bit line selection signal to each gate in the bit line selection unit.
  • the orthographic projection of the bit line selection line 524 on the plane where the active area is located and the orthographic projection of the bit line on the plane where the active area is located are separated from each other to avoid the intersection of the two and a short circuit.
  • the conductive contact lead is along the first The two-direction extension indicates that the conductive contact lead is parallel to the first part of the bit line, and the conductive contact lead is linear, which reduces the coupling effect and noise effect between the conductive contact lead and the bit line.
  • an embodiment of the present disclosure also provides a memory, including any one of the semiconductor structures in the above embodiments.
  • a memory including any one of the semiconductor structures in the above embodiments.
  • the gates and connection lines included in the bit line selection unit form an "H" shape.
  • the "H" shape bit line selection unit can effectively reduce the difficulty of process production, and is especially beneficial to Helps Optical Proximity Correction (OPC) to improve the actual shape of the bit line selection unit, effectively improving product output and yield; at the same time, multiple bit lines are arranged along the first direction; each bit line includes The first part and the second part both extend along the second direction and are offset along the first direction, and the connection part connects the first part and the second part.
  • Each bit line is connected to an active area, and the active areas connected to different bit lines are Areas are different.
  • bit lines form a "Z" shape that is flipped 90 degrees, and the main body of the bit line in each active area is a straight line.
  • the straight line main body of the bit line can effectively Reduce coupling effects and noise between adjacent bit lines, thereby improving the performance of the semiconductor structure.

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Abstract

本公开实施例公开了一种半导体结构以及存储器，其中，所述半导体结构包括：多个有源区；位线选择单元，包括分别位于彼此相邻的四个所述有源区上的第一栅极、第二栅极、第三栅极、第四栅极以及连接线，所述第一栅极和所述第二栅极相交于第一节点，所述第三栅极和所述第四栅极相交于所述第二节点，所述连接线连接所述第一节点和第二节点；多条位线，每一所述位线包括第一部分和第二部分以及连接所述第一部分和第二部分的连接部；每一所述位线与一所述有源区连接，不同所述位线连接的所述有源区不同，任意一条所述位线的第一部分与相邻位线的第二部分平行。

Description

半导体结构以及存储器
相关申请的交叉引用
本公开基于申请号为202211067383.5、申请日为2022年09月01日、发明名称为“半导体结构以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种半导体结构以及存储器。
背景技术
动态随机存储器(DRAM，Dynamic Random Access Memory)包括阵列排布的存储单元(存储位)。每个存储单元包括一个晶体管和一个电容器，晶体管作为电容器和位线之间的开关，可以被耦合到晶体管的控制端的字线(WL，Word Line)激活，存储单元能够将二进制信息存储为电容器上的电荷。
动态随机存储器不仅包括多个重复阵列排布的存储单元，还包括用于选择执行读写操作的位线(BL，Bit Line)的位线选择单元，该位线选择单元控制位线BL开启或关闭，即控制是否通过该条位线对存储单元进行读写操作。然而，位线选择单元的设计面临诸多挑战。
发明内容
有鉴于此，本公开实施例提出一种半导体结构以及存储器。
根据本公开的一个方面，提供了一种半导体结构，包括：
多个有源区，沿正交的第一方向和第二方向呈阵列排布，所述第一方向与所述有源区延伸的方向平行；
位线选择单元，包括分别位于彼此相邻的四个所述有源区上的第一栅极、第二栅极、第三栅极以及第四栅极，所述第一栅极和所述第二栅极沿所述第二方向延伸并相交于第一节点，所述第三栅极和所述第四栅极沿所述第二方向并相交于第二节点；以及连接线，所述连接线连接所述第一节点和所述第二节点且沿所述第一方向延伸；
多条位线，沿所述第一方向排布，每一所述位线包括均沿所述第二方向延伸且在所述第一方向错位的第一部分和第二部分以及连接所述第一部 分和第二部分的连接部，每一所述位线与一所述有源区连接，不同所述位线连接的所述有源区不同，任意一条所述位线的第一部分与相邻位线的第二部分处于平行于所述第二方向的同一直线上。
上述方案中，所述位线选择单元还包括：导电接触，位于所述第一栅极、第二栅极、第三栅极以及第四栅极中任意一个栅极上且靠近所述连接线。
上述方案中，所述导电接触在所述有源区所在平面的正投影为长条状。
上述方案中，所述导电接触在所述有源区所在平面的正投影位于所述任意一个栅极在所述有源区所在平面的正投影内且与所述位线在所述有源区所在平面的正投影相互分离。
上述方案中，所述位线选择单元还包括：位线选择线，与所述导电接触连接且沿所述第二方向延伸，所述位线选择线在所述有源区所在平面的正投影与所述位线在所述有源区所在平面的正投影相互分离。
上述方案中，所述多个有源区中相互相邻的四个有源区包括第一有源区、第二有源区、第三有源区和第四有源区，所述第一栅极位于所述第一有源区上，所述第二栅极位于所述第二有源区上，所述第三栅极位于所述第三有源区上，所述第四栅极位于所述第四有源区上；
所述第一节点位于所述第一有源区和所述第二有源区之间，第二节点位于所述第三有源区和所述第四有源区之间。
上述方案中，多条位线包括沿所述第一方向依次排布的第一位线、第二位线、第三位线及第四位线，所述第一位线的第一部分和所述第二位线的第二部分处于平行于所述第二方向的同一直线上，所述第三位线的第一部分和所述第四位线的第二部分处于平行于所述第二方向的同一直线上。
上述方案中，所述第一位线、所述第二位线、所述第三位线以及所述第四位线之间的间距均相等。
上述方案中，所述位线选择单元还包括：位于相互相邻的四个有源区中每个有源区对应栅极两侧的源区和漏区；所述第一位线与所述第一栅极靠近所述连接线的一侧的源区或漏区连接，所述第二位线与所述第二栅极靠近所述连接线的一侧的源区或漏区连接，所述第三位线与所述第三栅极靠近所述连接线的一侧的源区或漏区连接，所述第四位线与所述第四栅极靠近所述连接线的一侧的源区或漏区连接。
上述方案中，所述第一位线、第二位线、第三位线及第四位线在所述有源区所在平面的正投影沿所述第一方向的总尺寸小于所述第一栅极、第二栅极、第三栅极和第四栅极在所述有源区所在平面的正投影沿所述第一方向的总尺寸。
上述方案中，所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第二方向的尺寸均相同，所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第一方向的尺寸均相同。
上述方案中，所述连接线沿所述第二方向的尺寸大于或等于所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第一方向的尺寸。
上述方案中，所述半导体结构包括多个位线选择单元，沿所述第一方向相邻的两个位线选择单元共用沿所述第二方向相邻的两个有源区。
根据本公开的另一方面，提供了一种存储器，包括：
上述任意一种半导体结构。
本公开实施例提出了一种半导体结构以及存储器。本公开各实施例中，形成的半导体结构包括多个有源区、位线选择单元以及多条位线；其中，位线选择单元包括均沿第二方向延伸的第一栅极、第二栅极、第三栅极和第四栅极以及沿与第二方向垂直的第一方向延伸的连接线，并且第一栅极与第二栅极连接于第一节点，第三栅极与第四栅极连接于第二节点；连接线一端与第一节点连接，另一端与第二节点连接，可以理解的是，本公开实施例中位线选择单元包含的各栅极和连接线构成了“H”字型，该“H”字型的位线选择单元可以有效地减小工艺生产的难度，特别是有利于帮助光学邻近效应修正(OPC，Optical Proximity Correction)改善位线选择单元实际的形状，有效地提高了产品产量以及良率；同时，多条位线，沿第一方向排布；每一位线包括均沿第二方向延伸且沿第一方向存在错位的第一部分和第二部分以及连接第一部分和第二部分的连接部，每一位线与一有源区连接，不同位线连接的有源区不同，可以理解的是，本公开各实施例中位线构成翻转90度的“Z”字型，且位线在每个有源区中的主体呈直线，位线的直线主体可以有效地降低相邻的位线之间的耦合效应、噪声，从而提高半导体结构的性能。
附图说明
图1为本公开实施例提供的一种存储器的局部电路示意图；
图2为本公开实施例提供的一种半导体结构的布局示意图；
图3a为本公开实施例提供的另一种半导体结构的布局示意图；
图3b为图3a提供的半导体结构经过光学邻近效应修正和刻蚀工艺后的一种平面示意图；
图3c为图3a提供的半导体结构经过光学邻近效应修正和刻蚀工艺后的另一种平面示意图；
图4a-图4d为本公开实施例提供的另一种半导体结构的四种布局示意图；
图4e为图4a提供的半导体结构经过光学邻近效应修正和刻蚀工艺后的平面示意图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以及，除非另有明确具体的限定。
在本公开实施例中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
图1本公开实施例提供的一种存储器的局部电路示意图，参照图1所示，存储器100包括字线(WL，Word Line)、位线(BL，Bit Line)、互补位线(BLB，Bit Line Bar)、存储单元110、感应放大器(SA，Sense Amplifier)120、均衡器130和位线选择单元140(或者称为列选择器)。其中，存储 单元110前已述及，不再赘述；感应放大器120连接在位线BL和互补位线BLB之间，用于检测和放大一对位线BL和互补位线BLB上的电压差；均衡器130位于位线BL和互补位线BLB之间，其中均衡单元(EQ，Equalizer)配置为均衡位线和互补位线的电压，隔离单元(ISO，Isolater)配置为隔离位线和互补位线，偏置消除单元(OC，Offset Cancel)配置为消除与位线和参考位线连接的不同晶体管的特性差异；位线选择单元140配置为选择执行读、写操作的位线BL，并控制位线BL开启或关闭，即控制是否通过该条位线对存储单元110进行读、写操作。
为了保证感应放大器放大的数据能够有效的、快速的读取，传输到本地输入、输出(LIO，Local Input Output)的数据需要位线选择单元具有良好的开关特性。图2为本公开实施例提供的一种半导体结构的布局示意图。如图2所示，位线选择单元对应的晶体管的数量为4个，4个晶体管的栅极均连接到位线选择线(CSL，Column Select Line)，图2中位线选择单元所对应的晶体管的数量仅用于作为示例，不用于限制本公开实施例中位线选择单元所对应的晶体管的数量。
这里，位线选择单元所对应的晶体管的有源区沿正交的第一方向和第二方向呈阵列排布，第一方向与有源区延伸的方向平行，以图2为例，这里所说的第一方向可以为X轴方向，这里所说的第二方向可以为Y轴方向，其中，四个有源区201、202、203、204彼此相邻。
以图2为例，位线选择单元包括位于有源区201和有源区202上的第一部分205、位于有源区203和有源区204上的第二部分206以及位于有源区之外且有且仅靠近一侧有源区的第三部分207，图2所示的第三部分位于靠近有源区201和有源区203的一侧，此时的位线选择单元构成了一个倒“U”字型。实际上，第三部分还可以靠近位于有源区202和有源区204的一侧，此时的位线选择单元构成了一个“U”字型。事实上，第一部分205和第二部分206均包括两条连接在一起的栅极，第三部分包括可以导电的连接线，位线选择单元还包括位于第三部分207中间的导电接触208，导电接触208与位线选择线CSL相连，通过位线选择线，以为位线选择单元提供电信号。
位线选择单元所对应的晶体管连接的四条位线209、210、211、212沿X轴方向排布，且沿Y轴方向延伸，位线209包括沿Y轴方向延伸的长条状图形以及突出部分209a，位线209的突出部分209a在有源区所在平面的正投影落入到了有源区202内；位线210包括沿Y轴方向延伸的长条状图形以及错位弯折部分210a，位线210在有源区所在平面的正投影部分落入到了有源区201内，错位弯折部分210a在有源区所在平面的正投影与位线209的突出部分209a在X轴方向错开，或者说，错位弯折部分210a在有源区所在平面的正投影与有源区不重合；位线212包括沿Y轴方向延伸的长条状图形以及突出部分212a，位线212的突出部分212a在有源区所在平面 的正投影落入到了有源区203内；位线211包括沿Y轴方向延伸的长条状图形以及错位弯折部分211a，位线211在有源区所在平面的正投影部分落入到了有源区204内，错位弯折部分211a在有源区所在的平面投影与位线212的突出部分212a在X轴方向错开，或者说，错位弯折部分211a在有源区所在平面的正投影与有源区不重合。
可以理解的是，无论是“U”字型、倒“U”字型，导电接触与靠近第三部分的晶体管和远离第三部分的晶体管之间的距离不同，此时，导电接触与远离位线选择单元的第三部分的晶体管之间的电阻较大，会产生电压下降的问题，也就是说，靠近第三部分的晶体管上的电压会大于远离第三部分的晶体管上的电压；与此同时，导电接触与晶体管之间距离的不同也会造成时延，不利于位线选择单元的精准控制。
进一步可以理解的是，带有突出部分的位线或者带有错位弯折部分的位线与相邻的位线之间的距离较近，容易产生位线之间的耦合现象以及噪声现象，由此所生产的位线选择单元的性能较差。
为了降低位线之间的耦合现象、噪声现象，以及导电接触所在位置带来的电压不均衡以及时延，本公开实施例公开了一种斜“H”字型的位线选择单元，如图3a所示，图3a为本公开实施例提供的另一种半导体结构的布局示意图。
为了使位线呈直线，位线选择单元对应的多个晶体管中的有源区呈阵列排布，以如图3a为例，有源区在排布的时候，相邻两个有源区行沿X轴方向存在一定的错位，其中，四个有源区401、402、403、404彼此相邻的，且有源区402、404与有源区401、403在沿X轴正方向上有一定的错位。图3a中有源区沿X轴正方向错位排列仅用于作为示例，不用于限制有源区沿X正方向或者负方向进行错位排列。
以图3a为例，位线选择单元包括位于第一有源区401的第一栅极406、位于第二有源区402的第二栅极407、位于第三有源区403的第三栅极408、位于第四有源区404的第四栅极409、连接第一栅极406与第二栅极407的第一连接线410、连接第三栅极408与第四栅极409的第二连接线411以及连接第一连接线410与第二连接线411的第三连接线412。
由于位线选择单元的第一栅极406、第二栅极407、第三栅极408、第四栅极409均沿Y轴方向沿伸，且第一栅极406、第二栅极407之间沿X轴正方向错位，第三栅极408、第四栅极409之间沿X轴正方向错位，错位的方向与有源区之间的错位方向相同。为了使位线选择单元的四个部分连接起来，位线选择单元还包括连接第一栅极406与第二栅极407的第一连接线410、连接第三栅极408与第四栅极409的第二连接线411以及连接第一连接线410与第二连接线411的第三连接线412。此时的位线选择单元包含的各栅极和各连接线构成了一个带有一定倾斜角的“H”字型。
除此之外，位线选择单元还包括位于第一连接线410、或者第二连接线 411上的导电接触417，以给位线选择单元电信号。
位线选择单元所对应的晶体管连接的四条位线413、414、415、416沿X轴方向排布，沿Y轴方向延伸形成一条直线。位线413靠近第一栅极406的一部分在有源区所在平面的正投影落在第一有源区401上；位线414靠近第二栅极407的一部分在有源区所在平面的正投影落在第二有源区402上；位线415靠近第三栅极408的一部分在有源区所在平面的正投影落在第三有源区403上；位线415靠近第四栅极407的一部分在有源区所在平面的正投影落在第四有源区404上。
可以理解的是，上述实施例中由于有源区的错位式的阵列排布、以及位线选择单元包含的各栅极和各连接线构成了一个带有一定倾斜角的“H”字型，使得每条位线在呈一条直线时可以分别与且仅一个有源区相连。此时，呈直线的位线有效地降低了位线之间的耦合效应以及噪声效应。与此同时，导电接触417距离四个晶体管的距离均较近，有效地缓解了上一实施例中电压降以及迟延的问题。
但是，此实施例中的倾斜角的异型形状给工艺制造生产带来不小的难度，第一连接线410、第二连接线411以及第三连接线412之间准确连接的工艺难度大，而且形成的带有一定倾斜角的“H”字型的位线选择单元在经过OPC矫正后仍因其实际形状有些出入，导致影响了器件性能。
图3b为图3a提供的半导体结构经过光学邻近效应修正和刻蚀工艺后的一种平面示意图；如图3a所示，位线选择单元中第一连接线410在第一有源区401所在平面的正投影与第一有源区401并未发生交集，但经过光学邻近效应修正和刻蚀工艺后的第一连接线如图3b所示，可以看出第一连接线410在第一有源区401所在平面的正投影与第一有源区401发生重叠，重叠部分如图3b中418所示，该重叠部分导致位线选择线第一栅极406所在晶体管沟道变宽，性能变差。
此外，位于位线选择单元的第一连接线、或者第二连接线上的导电接触会有滑出风险。在实际生产时，导电接触可能会发生偏移，如图3b所示，导电接触417虽然大部分均位于位线选择单元的第二连接线上，但是还是有少部分不在位线选择单元上，而位于第三有源区403和第四有源区404之间的部分，容易发生漏电的现象。更糟糕的是，如果导电接触417偏移的部分不仅在有源区403和有源区404之间，还往第四有源区的方向偏移一些，如图3c所示，落到了第四有源区404上，此时不仅会发生漏电，还可能发生短路的现象，从而引发更大的问题。
基于此，为解决上述问题中的一个或多个，本公开实施例提供了一种半导体结构。半导体结构包括：
多个有源区，沿正交的第一方向和第二方向呈阵列排布，第一方向与有源区延伸的方向平行；
位线选择单元，包括分别位于彼此相邻的四个有源区上的第一栅极、 第二栅极、第三栅极以及第四栅极，第一栅极和第二栅极沿第二方向延伸并相交于第一节点，第三栅极和第四栅极沿第二方向并相交于第二节点；以及连接线，连接线连接第一节点和第二节点且沿第一方向延伸；
多条位线，沿第一方向排布，每一位线包括均沿第二方向延伸且在第一方向错位的第一部分和第二部分以及连接第一部分和第二部分的连接部，每一位线与一有源区连接，不同位线连接的有源区不同，任意一条位线的第一部分与相邻位线的第二部分处于平行于第二方向的同一直线上。
图4a-图4d为本公开实施例提供的另一种半导体结构的四种布局示意图，图4e为图4a提供的半导体结构经过光学邻近效应修正和刻蚀工艺后的平面示意图。下面将结合图4a-图4e对本公开实施例提供的半导体结构进行详细的说明。
这里，第一方向与每一有源区延伸的方向均平行，第二方向与第一方向垂直且与有源区所在的平面平行。在一些具体实施例中，第一方向可以为X轴延伸的方向，第二方向可以为沿Y轴延伸的方向。
需要说明的是，本公开实施例中的位线选择单元可以对应四个晶体管或者更多数量的晶体管，如八个等。图4a至图4e中仅示出了位线选择单元对应四个晶体管的情况，图4a至图4e中的展示不用于限制本公开实施例中位线选择单元对应的晶体管的数量。
需要说明的是，在本公开实施例中为了方便描述，将有源区与位线选择单元进行了并列描述，但是实际应用中，有源区实际也可以划归到位线选择单元中。
这里，多个有源可以沿第一方向和第二方向呈阵列排布，并且不同的有源区之间通过绝缘结构(例如浅沟槽隔离结构，STI)进行间隔，每个有源区均沿第一方向延伸，每个有源区的形状包括长条状，长条状可以是直角长条状或者圆角长条状。示例性地，参考图4a，每个有源区均沿X轴方向延伸，每个有源区的形状为直角长条状。
这里，位线选择单元包括对应晶体管的多个栅极，每个栅极均沿Y轴方向且每个栅极均跨越一个有源区。示例性地，参考图4a，多个栅极具体可以包括第一栅极506、第二栅极507、第三栅极508以及第四栅极509，第一栅极506的一端与第二栅极507的一端相交于第一交点，第三栅极508的一端与第四栅极509的一端相交于第二交点。
在一些实施例中，第一栅极506、第二栅极507、第三栅极508和第四栅极509沿第二方向的尺寸均相同，第一栅极506、第二栅极507、第三栅极508和第四栅极509沿第一方向的尺寸均相同。
可以理解的是，第一栅极506、第二栅极507、第三栅极508和第四栅极509的尺寸均相同时可以尽可能的保证每个栅极所在的晶体管的性能基本相同，从而有利于每个存储单元读写操作的差异趋向于更小。
在该情况下，第一栅极506远离第二栅极507的一端与第三栅极508 远离第四栅极509的一端沿第一方向齐平，第二栅极507远离第一栅极506的一端与第四栅极509远离第三栅极508的一端沿第一方向齐平。
示例性地，参考图4a，位线选择单元还包括沿X轴方向延伸的连接线510，具体为导电连接线，连接线510电连接第一交点和第二交点。
在一些实施例中，连接线510沿第二方向的尺寸大于或等于第一栅极506、第二栅极507、第三栅极508和第四栅极509沿第一方向的尺寸。
可以理解的是，当连接线510的线宽(沿第二方向的尺寸)与第一栅极506、第二栅极507、第三栅极508和第四栅极509的线宽(沿第一方向的尺寸)相同时，栅极与连接线之间的线宽没有跳变，信号传输顺畅，制造工艺也比较简单；当连接线510的线宽大于第一栅极506、第二栅极507、第三栅极508和第四栅极509的线宽时，较宽的连接线的电阻更低，可以降低位线选择信号的电阻电容(RC)延迟。
在一些实施例中，第一栅极506、第二栅极507、第三栅极508和第四栅极509以及连接线510的材料包括但不限于多晶硅(Poly)。
在一些实施例中，多个有源区中相互相邻的四个有源区包括第一有源区501、第二有源区502、第三有源区503和第四有源区504，第一栅极506位于第一有源区501上，第二栅极507位于第二有源区502上，第三栅极508位于第三有源区503上，第四栅极509位于第四有源区504上；
第一节点位于第一有源区501和第二有源区502之间，第二节点位于第三有源区503和第四有源区504之间。
这里，第一节点位于第一有源区501和第二有源区502之间的绝缘结构上，第二节点位于第三有源区503和第四有源区504之间的绝缘结构上。
这里，第一栅极506、第二栅极507、第三栅极508和第四栅极509以及连接线510的排布形成正“H”字形，布局形状周正、对称性好。可以理解的是，在制造时，跨越第一有源区501的第一栅极506与跨越第二有源区502的第二栅极507处于沿第二方向的同一直线上，可以一起形成；跨越第三有源区503的第三栅极506与跨越第四有源区504的第四栅极507处于沿第二方向的同一直线上，可以一起形成；连接线510沿第一方向呈一直线，制造也比较简单。显然，“H”字形的排布方式对应的制造工艺相较于图4a中位线选择单元中具有一定倾斜角的“H”字型的排布对应的制造工艺难度小，流程相对简单。
进一步，该半导体结构经过光学邻近效应修正和刻蚀工艺后的平面示意图如图4e所示，位线选择单元中的各栅极及连接线在经过OPC矫正后与图4a中的实际形状虽然有些出入，相较于图3b，第三栅极508和第四栅极509之间的连接线在第三有源区503所在平面的正投影与第三有源区503并未发生重叠，基本上还是保持了第三栅极508的直线的形状，因此，不会发生如图3b所示的位线选择单元的第一连接线410在第一有源区401所在平面的正投影与第一有源区401有重叠，从而产生沟道变宽影响器件性能 的现象。
这里，多条位线中的每条位线均可以包括三个部分即第一部分、第二部分以及连接第一部分与第二部分的连接部。在一些实施例中，多条位线包括沿第一方向依次排布的第一位线、第二位线、第三位线及第四位线。示例性地，参考图4a，多条位线包括沿X轴方向依次排布的第一位线511、第二位线512、第三位线513及第四位线514；第一位线511包括均沿Y轴方向延伸且在X轴方向错位的第一部分511a和第二部分511b以及连接第一部分511a和第二部分511b的第一连接部511c；第二位线512包括均沿Y轴方向延伸且在X轴方向错位的第一部分512a和第二部分512b以及连接第一部分512a和第二部分512b的第二连接部512c；第三位线513包括均沿Y轴方向延伸且在X轴方向错位的第一部分513a和第二部分513b以及连接第一部分513a和第二部分513b的第三连接部513c；第四位线514包括均沿Y轴方向延伸且在X轴方向错位的第一部分514a和第二部分514b以及连接第一部分514a和第二部分514b的第四连接部514c。需要说明的是，每条位线中的连接部可以沿第一方向延伸，也可以沿第三方向延伸。这里，第三方向可以是与第一方向和第二方向均相交的任意一个方向。
在一些实施例中，如图4a所示，第一位线511的第一部分511a和第二位线512的第二部分512b处于平行于第二方向的同一直线上，第三位线513的第一部分513a和第四位线514的第二部分514b处于平行于第二方向的同一直线上。
在实际应用中，第二位线512的第一部分512a和第三位线513的第二部分513b也处于平行于第二方向的同一直线上。每条位线的第一部分或第二部分中的一者在有源区所在平面的正投影落在相应有源区内，从而，当有源区沿第一方向和第二方向对齐排布时，每条位线可以连接一个有源区相同的对应位置。
在另一些实施例中，第一位线511的第一部分511a和第二位线512的第二部分512b可以不处于平行于第二方向的同一直线上，而是稍有错位；第三位线513的第一部分513a和第四位线514的第二部分514b也不处于平行于第二方向的同一直线上，而是稍有错位，该种情况下，当有源区沿第一方向和第二方向对齐排布时，每条位线可以连接一个有源区稍有错位的对应位置。
可以理解的是，由于每条位线的主要组成部分第一部分和第二部分均呈直线，不存在图2所示的突出部分以及错位弯折部分，相邻两条位线之间的耦合现象以及噪声现象会大大降低。同时，当每条位线有且仅可以控制连接一个有源区相同的对应位置时，可以尽可能的保证每个栅极所在的晶体管的性能基本相同，从而有利于每个存储单元读取数据的差异趋向于更小。
在一些实施例中，第一位线、第二位线、第三位线以及第四位线之间 的间距均相等。
可以理解的是，相邻的两条位线之间的距离相等，可以保证各位线的参数如寄生电容等的一致性较好，从而有利于每个存储单元读写操作的均匀性。
在一些实施例中，第一位线、第二位线、第三位线及第四位线在有源区所在平面的正投影沿第一方向的总尺寸小于第一栅极、第二栅极、第三栅极和第四栅极在有源区所在平面的正投影沿第一方向的总尺寸。
这里，第一位线、第二位线、第三位线及第四位线在有源区所在平面的正投影沿第一方向的总尺寸可以参照图4a中的L1进行理解，第一栅极、第二栅极、第三栅极和第四栅极在有源区所在平面的正投影沿第一方向的总尺寸可以参照图4a中的L2进行理解。
可以理解的是，L1小于L2可以保证与一个位线选择单元对应的各位线中，不与有源区连接的部分的正投影均落在位线选择单元的各栅极对应的正投影内或者落在相邻有源区之间的绝缘结构内，这样位线不会影响位线选择单元的各栅极外侧527(如第一栅极、第二栅极、第三栅极和第四栅极远离连接线的一侧的有源区)有源区与LIO的连接。
在一些实施例中，位线选择单元还包括：位于相互相邻的四个有源区中每个有源区对应栅极两侧的源区和漏区；第一位线与第一栅极靠近连接线的一侧的源区或漏区连接，第二位线与第二栅极靠近连接线的一侧的源区或漏区连接，第三位线与第三栅极靠近连接线的一侧的源区或漏区连接，第四位线与第四栅极靠近连接线的一侧的源区或漏区连接。
这里，位线分别与位线选择单元的各栅极内侧即第一栅极、第二栅极、第三栅极和第四栅极靠近连接线的一侧的有源区中的源区或漏区连接，实际应用中，位线选择单元的各栅极外侧即第一栅极、第二栅极、第三栅极和第四栅极远离连接线的一侧的有源区中的源区或漏区与LIO连接。
在一些实施例中，半导体结构包括多个位线选择单元，沿第一方向相邻的两个位线选择单元共用沿第二方向相邻的两个有源区。
这里，半导体结构可以包括多个位线选择单元，多个位线选择单元呈阵列排布，沿第一方向相邻的两个位线选择单元的栅极共同有源区。示例性地，参考图4a，第五栅极526所在的位线选择单元与第一栅极506所在的位线选择单元在X轴方向上相邻，两个位线选择单元共用第一有源区501，第五栅极526所在的晶体管与第一栅极506所在的晶体管共用位于第五栅极526和第一栅极506中的有源区507中的源极或者漏极，这样可以有效地微缩晶体管所占的面积，减小半导体结构的尺寸。
在一些实施例中，位线选择单元还包括：导电接触523，位于第一栅极、第二栅极、第三栅极以及第四栅极中任意一个栅极上且靠近连接线。
这里，示例性地，图4a中的导电接触523位于第一栅极且靠近连接线的位置；图4b中的导电接触523位于第二栅极且靠近连接线的位置；图4c 中的导电接触523位于第三栅极且靠近连接线的位置；图4d中的导电接触523位于第四栅极且靠近连接线的位置。
下面以图4a进行说明，导电接触523位于第一栅极且靠近连接线的位置，导电接触523距离四个晶体管的栅极所在位置的相对距离较为均衡，可以有效地避免如图2所示的导电接触所在位置使导电接触距离其中的两个晶体管的栅极明显的远于另两个晶体管的栅极的情况。同时，本公开中导电接触在对四个晶体管进行供电的时候，没有经过别的晶体管的栅极，这样有利于减少别的晶体管工作时带来的电压降以及迟延问题。
理论上导电接触523在如图4a所示位置再往下一点，位于在第一栅极和第二栅极正中间的位置更好，这样距离四个晶体管的栅极所在位置的相对距离更为均衡。
但是位于“H”型位线选择单元的位线，存在连接第一部分和第二部分的连接部，该部分的弯折与导电接触523所在的位置相关，如图4a所示，导电接触523位于第一栅极且靠近连接线的位置，则靠近导电接触523的第一位线511的第一部分511a在有源区所在平面的正投影位于有源区内，第一位线511的第二部分511b在有源区所在平面的正投影位于第二栅极507在有源区所在平面的正投影内，连接位线的第一部分511a和第二部分511b的第一连接部511c的弯折正好使得第一位线511的第二部分511b更靠近第二栅极507，每一条位线的连接第一部分和第二部分的连接部都相互平行，使得每条位线都呈翻转90度“Z”字型依次排列。如果将导电接触523向下移，移到第一栅极和第二栅极正中间的位置，在位线位置不变的情况下，导电接触523与第一位线的第一连接部之间的空间太小，可能发生短接等问题。
如果将导电接触523向下移，移到第一栅极和第二栅极正中间的位置，保证导电接触523与第一位线511的第一连接部511c之间的空间，以配合当前的工艺，此时，位线位置就要整体下移，那么第三位线513的第三连接部513c以及第四位线514的第四连接部514c在有源区所在平面的正投影大部分就会落在第四有源区504内，就会加剧位线之间的耦合效应以及噪声效应。从而降低半导体结构的性能。
在一些实施例中，导电接触在有源区所在平面的正投影为长条状。
这里，导电接触523的长条状为沿Y轴方向的尺寸大于沿X轴方向的尺寸，因为在X轴方向上的尺寸较窄有利于导电接触的设置，导电接触523在有源区所在平面的正投影可以更方便地落在在第一栅极在有源区所在的正投影内，有效地降低如图3b所示的导电接触滑出的风险；同时，也降低了导电接触与有源区接触，造成短路的风险。在一些实施例中，导电接触在有源区所在平面的正投影位于任意一个栅极在有源区所在平面的正投影内且与位线在有源区所在平面的正投影相互分离。
这里，导电接触在有源区所在平面的正投影位于任意一个栅极在有源 区所在平面的正投影内可以保证导电接触与相应栅极的良好接触，同时避免短路、漏电的风险。
在一些实施例中，导电接触523在有源区所在平面的正投影位于任意一个栅极在有源区所在平面的正投影内，且导电接触的正投影与任意一个有源区的正投影不重合。
这里，导电接触在有源区所在平面的正投影与位线在有源区所在平面的正投影相互分离需要配合考虑导电接触的位置与位线的弯折方向。图4a至图4d中分别示意了不同导电接触设置在不同位置时，对应位线的弯折方向的设置。
在一些实施例中，位线选择单元还包括：位线选择线524，与导电接触连接且沿第二方向延伸，位线选择线在有源区所在平面的正投影与位线在有源区所在平面的正投影相互分离。
这里，位线选择线524用于将位线选择信号传递到位线选择单元中的各栅极上。
可以理解的是，位线选择线524在有源区所在平面的正投影与位线在有源区所在平面的正投影相互分离避免了两者相交而一起的短路，同时，导电接触引线沿第二方向延伸表明了导电接触引线与位线的第一部分平行，且导电接触引线呈直线型，这样减小了导电接触引线与位线之间的耦合效应与噪声效应。
根据本公开的另一方面，本公开实施例还提供了一种存储器，包括上述实施例中的任意一种半导体结构。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中位线选择单元包含的各栅极和连接线构成了“H”字型，该“H”字型的位线选择单元可以有效地减小工艺生产的难度，特别是有利于帮助光学邻近效应修正(OPC，Optical Proximity Correction)改善位线选择单元实际的形状，有效地提高了产品产量以及良率；同时，多条位线，沿第一方向排布；每一位线包括均沿第二方向延伸且沿第一方向存在错位的第一部分和第二部分以及连接第一部分和第二部分的连接部，每一位线与一有源区连接，不同位线连接的有源区不同，可以理解的是，本公开各实施例中位线构成翻转90度的“Z”字型，且位线在每个有源区中的主体 呈直线，位线的直线主体可以有效地降低相邻的位线之间的耦合效应、噪声，从而提高半导体结构的性能。

Claims (14)

  1. 一种半导体结构，包括：
    多个有源区，沿正交的第一方向和第二方向呈阵列排布，所述第一方向与所述有源区延伸的方向平行；
    位线选择单元，包括分别位于彼此相邻的四个所述有源区上的第一栅极、第二栅极、第三栅极以及第四栅极，所述第一栅极和所述第二栅极沿所述第二方向延伸并相交于第一节点，所述第三栅极和所述第四栅极沿所述第二方向并相交于第二节点；以及连接线，所述连接线连接所述第一节点和所述第二节点且沿所述第一方向延伸；
    多条位线，沿所述第一方向排布，每一所述位线包括均沿所述第二方向延伸且在所述第一方向错位的第一部分和第二部分以及连接所述第一部分和第二部分的连接部，每一所述位线与一所述有源区连接，不同所述位线连接的所述有源区不同，任意一条所述位线的第一部分与相邻位线的第二部分处于平行于所述第二方向的同一直线上。
  2. 根据权利要求1所述的半导体结构，其中，所述位线选择单元还包括：导电接触，位于所述第一栅极、第二栅极、第三栅极以及第四栅极中任意一个栅极上且靠近所述连接线。
  3. 根据权利要求2所述的半导体结构，其中，所述导电接触在所述有源区所在平面的正投影为长条状。
  4. 根据权利要求2所述的半导体结构，其中，所述导电接触在所述有源区所在平面的正投影位于所述任意一个栅极在所述有源区所在平面的正投影内且与所述位线在所述有源区所在平面的正投影相互分离。
  5. 根据权利要求2所述的半导体结构，其中，所述位线选择单元还包括：位线选择线，与所述导电接触连接且沿所述第二方向延伸，所述位线选择线在所述有源区所在平面的正投影与所述位线在所述有源区所在平面的正投影相互分离。
  6. 根据权利要求1所述的半导体结构，其中，所述多个有源区中相互相邻的四个有源区包括第一有源区、第二有源区、第三有源区和第四有源区，所述第一栅极位于所述第一有源区上，所述第二栅极位于所述第二有源区上，所述第三栅极位于所述第三有源区上，所述第四栅极位于所述第四有源区上；
    所述第一节点位于所述第一有源区和所述第二有源区之间，第二节点位于所述第三有源区和所述第四有源区之间。
  7. 根据权利要求6所述的半导体结构，其中，多条位线包括沿所述第一方向依次排布的第一位线、第二位线、第三位线及第四位线，所述第一位线的第一部分和所述第二位线的第二部分处于平行于所述第二方向的同一 直线上，所述第三位线的第一部分和所述第四位线的第二部分处于平行于所述第二方向的同一直线上。
  8. 根据权利要求7所述的半导体结构，其中，所述第一位线、所述第二位线、所述第三位线以及所述第四位线之间的间距均相等。
  9. 根据权利要求7所述的半导体结构，其中，所述位线选择单元还包括：位于相互相邻的四个有源区中每个有源区对应栅极两侧的源区和漏区；所述第一位线与所述第一栅极靠近所述连接线的一侧的源区或漏区连接，所述第二位线与所述第二栅极靠近所述连接线的一侧的源区或漏区连接，所述第三位线与所述第三栅极靠近所述连接线的一侧的源区或漏区连接，所述第四位线与所述第四栅极靠近所述连接线的一侧的源区或漏区连接。
  10. 根据权利要求7所述的半导体结构，其中，所述第一位线、第二位线、第三位线及第四位线在所述有源区所在平面的正投影沿所述第一方向的总尺寸小于所述第一栅极、第二栅极、第三栅极和第四栅极在所述有源区所在平面的正投影沿所述第一方向的总尺寸。
  11. 根据权利要求1所述的半导体结构，其中，所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第二方向的尺寸均相同，所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第一方向的尺寸均相同。
  12. 根据权利要求9所述的半导体结构，其中，所述连接线沿所述第二方向的尺寸大于或等于所述第一栅极、第二栅极、第三栅极和第四栅极沿所述第一方向的尺寸。
  13. 根据权利要求1所述的半导体结构，其中，所述半导体结构包括多个位线选择单元，沿所述第一方向相邻的两个位线选择单元共用沿所述第二方向相邻的两个有源区。
  14. 一种存储器，包括：
    如权利要求1至13任一项所述的半导体结构。
PCT/CN2022/123987 2022-09-01 2022-10-09 半导体结构以及存储器 Ceased WO2024045262A1 (zh)

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US6380576B1 (en) * 2000-08-31 2002-04-30 Micron Technology, Inc. Selective polysilicon stud growth
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