WO2024040771A1 - Structure semi-conductrice et son procédé de formation - Google Patents

Structure semi-conductrice et son procédé de formation Download PDF

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Publication number
WO2024040771A1
WO2024040771A1 PCT/CN2022/134057 CN2022134057W WO2024040771A1 WO 2024040771 A1 WO2024040771 A1 WO 2024040771A1 CN 2022134057 W CN2022134057 W CN 2022134057W WO 2024040771 A1 WO2024040771 A1 WO 2024040771A1
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layer
gate
dielectric layer
gate dielectric
gate structure
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PCT/CN2022/134057
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English (en)
Chinese (zh)
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王蒙蒙
沈宇桐
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长鑫存储技术有限公司
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Publication of WO2024040771A1 publication Critical patent/WO2024040771A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate electrode of the transistor is electrically connected to the word line
  • the source electrode is electrically connected to the bit line
  • the drain electrode is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • HKMG High-K Metal Gate
  • HKMG technology includes First Gate technology and Last Gate technology.
  • First Gate technology in thick oxide devices, because the presence of thicker gate dielectric materials will affect the diffusion of dipoles in the high-K dielectric layer, the work function metal cannot play a good role.
  • the threshold voltage adjustment effect causes the threshold voltage of the gate of the thick oxide device to be too high, causing the performance degradation of the thick oxide device.
  • the technical problem to be solved by this disclosure is to provide a semiconductor structure and a method for forming the same, which can improve the stability of the semiconductor device.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure, including: forming a substrate, the substrate includes a substrate, the substrate has a first device region and a second device region, and in the In a device area, the substrate surface is covered with a first gate dielectric layer. In the second device area, the substrate surface is covered with a second gate dielectric layer. The thickness of the first gate dielectric layer is less than the thickness of the first gate dielectric layer. The thickness of the second gate dielectric layer, the surfaces of the first gate dielectric layer and the second gate dielectric layer are covered with a high-K dielectric layer, wherein the first mask is used to form the third gate dielectric layer through a positive development or negative development process.
  • Two gate dielectric layers use the first photomask to remove the high-K dielectric layer in the second device area through a negative development or positive development process to expose the second gate dielectric layer;
  • a first gate structure is formed on the surface of the high-K dielectric layer, and in the second device region, a second gate structure is formed on the surface of the second gate dielectric layer.
  • the step of forming a substrate includes: providing the substrate; forming a second gate dielectric layer on the surface of the substrate in the second device region; and forming a second gate dielectric layer on the surface of the substrate in the first device region.
  • a first gate dielectric layer is formed on the surface of the substrate; a high-K dielectric layer is formed, and the high-K dielectric layer covers the first gate dielectric layer and the second gate dielectric layer.
  • the step of forming a second gate dielectric layer on the surface of the substrate includes: forming a second gate dielectric material layer on the substrate; using the first light The mask passes a positive development or negative development process to form a first mask layer on the second gate dielectric material layer in the second device area; using the first mask layer as a shield, a first mask layer is formed on the first gate dielectric material layer in the second device area.
  • remove the second gate dielectric material layer In the second device region, the second gate dielectric material layer serves as the second gate dielectric layer; remove the first mask layer.
  • the step of forming a first gate dielectric layer on the surface of the substrate includes: forming a first gate dielectric material layer, and in the first device region, the first A gate dielectric material layer covers the substrate surface, and the first gate dielectric material layer serves as the first gate dielectric layer.
  • the first gate dielectric material layer in the second device region, also covers the surface of the second gate dielectric material layer, and the first gate dielectric material layer and the second gate dielectric material layer The material layers together serve as the second gate dielectric layer.
  • the step of removing the high-K dielectric layer and exposing the second gate dielectric layer includes: using the first photomask through a negative development or positive development process, In the first device area, a second mask layer is formed on the surface of the high-K dielectric layer; using the second mask layer as a shield, in the second device area, the high-K dielectric layer is removed, Expose the second gate dielectric layer; remove the second mask layer.
  • the method before the step of removing the high-K dielectric layer, the method further includes: forming a protective layer on the surface of the high-K dielectric layer; during the step of removing the high-K dielectric layer, in the first device area, the protective layer is used to protect the high-K dielectric layer; before the step of forming the first gate structure, the protective layer is removed.
  • the first device region includes a first N-well region and a first P-well region
  • the second device region includes a second N-well region and a second P-well region
  • the step of forming the substrate It also includes: forming a silicon germanium layer on the surface of the substrate in the first N-well region, and the first gate dielectric layer covering the silicon germanium layer.
  • the first gate structure includes a first NMOS transistor gate structure and a first PMOS transistor gate structure
  • the second gate structure includes a second NMOS transistor gate structure and a second PMOS transistor.
  • Gate structure, the steps of forming the first gate structure and the second gate structure include: forming a first NMOS transistor gate structure in the first P-well region, forming a first N-well region A first PMOS transistor gate structure, a second NMOS transistor gate structure formed in the second P-well region, and a second PMOS transistor gate structure formed in the second N-well region.
  • the step of forming the first gate structure and the second gate structure includes: forming an NMOS transistor metal gate layer in the first P-well region and the second P-well region; A PMOS transistor metal gate layer is formed in the first N-well region and the second N-well region; a gate composite material layer is formed, and the gate composite material layer covers the NMOS transistor metal gate layer and the PMOS transistor.
  • An embodiment of the present disclosure also provides a semiconductor structure, which includes: a substrate having a first device region and a second device region; in the first device region, a first gate dielectric layer covers the substrate surface; in the second device area, a second gate dielectric layer covers the substrate surface, and the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer; a high-K dielectric layer covers all The surface of the first gate dielectric layer; the first gate structure is located on the surface of the high-K dielectric layer; the second gate structure is located on the surface of the second gate dielectric layer.
  • the first device region includes a first N-well region and a first P-well region
  • the first gate structure includes a first NMOS transistor gate structure and a first PMOS transistor gate structure, so The first NMOS transistor gate structure is disposed on the first P-well region, and the first PMOS transistor gate structure is disposed on the first N-well region
  • the second device region includes a second N-well region and a second P-well region
  • the second gate structure includes a second NMOS transistor gate structure and a second PMOS transistor gate structure
  • the second NMOS transistor gate structure is disposed in the second P-well region above
  • the second PMOS transistor gate structure is disposed on the second N-well region.
  • the semiconductor structure in the first N-well region, further includes a silicon germanium layer, and the silicon germanium layer is disposed between the first gate dielectric layer and the substrate.
  • first NMOS transistor gate structure and the second NMOS transistor gate structure have the same structure
  • first PMOS transistor gate structure and the second PMOS transistor gate structure have the same structure. structure.
  • the first NMOS transistor gate structure and the second NMOS transistor gate structure each include an NMOS transistor metal gate layer and a first gate composite layer covering the NMOS transistor metal gate layer.
  • the first PMOS transistor gate structure and the second PMOS transistor gate structure both include a PMOS transistor metal gate layer and a second gate composite layer covering the PMOS transistor metal gate layer.
  • the high-K dielectric layer in the second device region where the thicker second gate dielectric layer is located is removed, leaving only the second gate dielectric layer.
  • the layer serves as an isolation layer between the subsequently formed second gate structure and the substrate, that is, there is no high-K dielectric layer in the second device area, and there will be no impact on the high-K dielectric layer due to the presence of the thicker second gate dielectric layer.
  • the problem of dipole diffusion in the K dielectric layer enables the second gate structure to play a good role in regulating the threshold voltage, avoids the threshold voltage of the second device area being too high, and improves the stability of the semiconductor device in the second device area.
  • the formation method provided by the embodiment of the present disclosure will not affect the high-K dielectric layer in the first device region due to the removal of the high-K dielectric layer in the second device region.
  • the high-K dielectric layer is still formed in the first device region, which further ensures the stability of the semiconductor structure in the first device region.
  • the formation method provided by the embodiment of the present disclosure uses a first mask to form the second gate dielectric layer through a positive development or a negative development process, and uses the first mask to use a negative development or a positive development process.
  • the high-K dielectric layer is removed, that is, the same photomask is used to form the second gate dielectric layer and remove the high-K dielectric layer.
  • the cost is low, the preparation process is simple, and the second gate dielectric layer can be avoided without complicated processes.
  • the second gate structure in the device area cannot adjust the threshold voltage well, which greatly improves the practicality of the semiconductor process.
  • the semiconductor structure provided by the embodiment of the present disclosure provides a high-K dielectric layer between the first gate structure and the substrate in the first device region (thin oxygen device region) to reduce the leakage current of the first gate structure, and in the In the second device area (thick oxide device area), only a thicker second gate dielectric layer is used as an isolation layer between the second gate structure and the substrate, and there is no high-K dielectric layer. This reduces the cost of the second gate structure.
  • the second gate structure While leaking current, it also avoids the problem of diffusion of dipoles in the high-K dielectric layer caused by the second gate dielectric layer being too thick, so that the second gate structure can play a good role in regulating the threshold voltage and avoid the second device
  • the threshold voltage of the region is too high, which improves the stability of the semiconductor device in the second device region.
  • Figure 1 is a schematic diagram of the steps of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS 2 to 14 are schematic diagrams of semiconductor structures formed by the main steps of the formation method provided by embodiments of the present disclosure.
  • FIG. 1 is a schematic diagram of the steps of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • the formation method includes: step S10, forming a substrate, the substrate including a substrate having a first device. region and the second device region, in the first device region, the substrate surface is covered with a first gate dielectric layer, in the second device region, the substrate surface is covered with a second gate dielectric layer, so The thickness of the first gate dielectric layer is smaller than the thickness of the second gate dielectric layer, and the surfaces of the first gate dielectric layer and the second gate dielectric layer are covered with a high-K dielectric layer, wherein a first photomask is used
  • the second gate dielectric layer is formed through a positive development or a negative development process; step S11, using the first photomask to remove the high-K dielectric layer in the second device area through a negative development or positive development process, Exposing the second gate dielectric layer; step S12, in the first device area, form a first gate structure on the surface
  • the high-K dielectric layer in the second device region where the thicker second gate dielectric layer is located is removed, leaving only the second gate dielectric layer.
  • the dielectric layer serves as an isolation layer between the subsequently formed second gate structure and the substrate. That is, there is no high-K dielectric layer in the second device area, and there is no influence due to the presence of the thicker second gate dielectric layer.
  • the problem of diffusion of dipoles in the high-K dielectric layer allows the second gate structure to play a good role in adjusting the threshold voltage, avoid excessively high threshold voltage in the second device area, and improve the performance of the semiconductor device in the second device area. stability.
  • the formation method provided by the embodiment of the present disclosure will not affect the high-K dielectric layer in the first device region due to the removal of the high-K dielectric layer in the second device region.
  • the high-K dielectric layer is still formed in the first device region, which further ensures the stability of the semiconductor structure in the first device region.
  • the formation method provided by the embodiment of the present disclosure uses a first mask to form the second gate dielectric layer through a positive development or a negative development process, and uses the first mask to pass a negative development or a positive development process. In the device area, remove the high-K dielectric layer, that is, use the same photomask to form the second gate dielectric layer and remove the high-K dielectric layer. The cost is low, the preparation process is simple, and the second device can be avoided without complicated processes.
  • the second gate structure in the region cannot adjust the threshold voltage well, which greatly improves the practicality of the semiconductor process.
  • FIGS. 2 to 14 are schematic diagrams of semiconductor structures formed by the main steps of the formation method provided by embodiments of the disclosure.
  • step S10 is to form a substrate 200.
  • the substrate 200 includes a substrate 201.
  • the substrate 201 has a first device area A1 and a second device area A2.
  • the first In the device area A1 the surface of the substrate 201 is covered with the first gate dielectric layer 210.
  • the second device area A2 the surface of the substrate 201 is covered with the second gate dielectric layer 220.
  • the first gate dielectric layer The thickness of 210 is smaller than the thickness of the second gate dielectric layer 220.
  • the surfaces of the first gate dielectric layer 210 and the second gate dielectric layer 220 are covered with a high-K dielectric layer 230, in which the first photomask is used to pass through
  • the second gate dielectric layer 220 is formed through a positive development or negative development process.
  • the substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate or an SOI substrate, etc.; the substrate may also be a substrate including other element semiconductors or compound semiconductors, For example, gallium arsenide, indium phosphide or silicon carbide, etc., the substrate can also be a stacked structure, such as a silicon/silicon germanium stack, etc.; in addition, the substrate 201 can be an ion-doped substrate. , P-type doping or N-type doping can be performed; multiple peripheral devices, such as field effect transistors, capacitors, inductors and/or diodes, etc., can also be formed in the substrate 201 . In this embodiment, the substrate 201 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc., but these are not shown as they have nothing to do with the present invention.
  • the first device region A1 refers to a region where a first type transistor is formed
  • the second device region A2 refers to a region where a second type transistor is formed.
  • the first type transistor may be a thin oxygen transistor
  • the second type transistor may be a thick oxygen transistor.
  • the first type of transistor includes a logic transistor and the second type of transistor includes an input/output transistor.
  • the first device region A1 includes a first N-well region 202 and a first P-well region 203
  • the second device region A2 includes a second N-well region 204 and a second P-well region 205.
  • the first N-well region 202 , the first P-well region 203 , the second N-well region 204 and the second P-well region 205 are isolated by a shallow trench isolation structure 300 .
  • the first N-well region 202 and the second N-well region 204 can be formed by implanting arsenic and/or phosphorus ions into the substrate 201
  • the first P-well region 203 and the second P-well region 205 can be formed by implanting arsenic and/or phosphorus ions into the substrate 201. Boron ions are implanted into the substrate 201 to form.
  • the first gate dielectric layer 210 only covers the surface of the substrate 201 in the first device region A1, and the second gate dielectric layer 220 only covers the surface of the substrate 201 in the second device region A2,
  • the high-K dielectric layer 230 covers both the first gate dielectric layer 210 and the second gate dielectric layer 220 . That is, in the first device region A1, the first gate dielectric layer 210 is provided on the surface of the substrate 201, and the surface of the first gate dielectric layer 210 is covered with the high-K dielectric layer 230. In the second device In area A2, the surface of the substrate 201 is covered with the second gate dielectric layer 220, and the surface of the second gate dielectric layer 220 is covered with the high-K dielectric layer 230.
  • a silicon germanium layer 206 is formed on the surface of the substrate 201, then in the first device region A1, in the first N-well region 202, The first gate dielectric layer 210 covers the surface of the silicon germanium layer 206 .
  • embodiments of the present disclosure also provide a method of forming the substrate 200 .
  • the methods include:
  • the substrate 201 is provided, and in the second device region A2 , a second gate dielectric layer 220 is formed on the surface of the substrate 201 .
  • This embodiment provides a method of forming the second gate dielectric layer 220 .
  • the specific instructions are as follows:
  • a second gate dielectric material layer 221 is formed on the substrate 201 .
  • the second gate dielectric material layer 221 not only covers the surface of the substrate 201 in the second device region A2, but also covers the surface of the substrate 201 in the first device region A1.
  • the second gate dielectric material layer 221 is an oxide layer, including but not limited to silicon oxide or silicon oxynitride.
  • the second gate dielectric material layer 221 can be formed on the surface of the substrate 201 by thermal oxidation, chemical vapor deposition, atomic layer deposition, or other methods.
  • a step of forming a silicon germanium layer 206 in the first N-well region 202 is also included.
  • the silicon germanium layer may be formed using processes such as chemical vapor deposition.
  • the second gate dielectric material layer 221 covers the surface of the silicon germanium layer 206.
  • the first mask is used to form a first mask layer 310 on the second gate dielectric material layer 221 in the second device area A2 through a positive development or negative development process.
  • the first mask layer 310 only covers the second gate dielectric material layer 221 in the second device region A2, and the surface of the second gate dielectric material layer 221 in the first device region A1 is exposed.
  • the first mask layer 310 is a photoresist layer.
  • the first photomask is used to retain the surface of the second gate dielectric material layer 221 located in the second device area A2 through a positive development or negative development process.
  • the photoresist layer serves as the first mask layer 310 .
  • the first mask layer 310 is formed through a positive development process using the first photomask.
  • the second gate dielectric material layer 221 is removed in the first device area A1, and in the second device area A2, the second gate dielectric material layer 221 is removed.
  • the gate dielectric material layer 221 serves as the second gate dielectric layer 220 .
  • the second gate dielectric material layer 221 is removed using an etching process, such as a dry etching process.
  • the first mask layer 310 only blocks the second gate dielectric material layer 221 in the second device region A2, the second gate dielectric material layer 221 in the second device region A2 is retained as The second gate dielectric layer 220 and the second gate dielectric material layer 221 located in the first device region A1 are removed, exposing the substrate 201 and the silicon germanium layer 206 .
  • the first mask layer 310 is removed to expose the second gate dielectric layer 220 .
  • the first mask layer 310 can be removed using an ashing process or other methods.
  • a first gate dielectric layer 210 is formed on the surface of the substrate 201 in the first device region A1.
  • This embodiment provides a method of forming the first gate dielectric layer 210 .
  • the specific instructions are as follows:
  • a first gate dielectric material layer is formed.
  • the first gate dielectric material layer covers the surface of the substrate 201 and the silicon germanium layer 206 .
  • the gate dielectric material layer serves as the first gate dielectric layer 210 .
  • the first gate dielectric material layer may be formed on the surface of the substrate 201 using methods such as thermal oxidation, chemical vapor deposition, and atomic layer deposition.
  • the first gate dielectric material layer is only formed on the surface of the substrate 201 and the silicon germanium layer 206 in the first device region A1, and is not formed on the second gate of the second device region A2.
  • the surface of the dielectric material layer 221, then the thickness of the second gate dielectric material layer 221 formed in the step of forming the second gate dielectric material layer 221 (see FIG. 2) is greater than the thickness of the first gate dielectric material layer. thickness, so that the thickness of the finally formed second gate dielectric layer 220 is greater than the thickness of the first gate dielectric layer 210 .
  • the first gate dielectric material layer is also formed on the surface of the second gate dielectric material layer 221, and the first gate dielectric material layer
  • the material layer and the second gate dielectric material layer 221 together serve as the second gate dielectric layer 220 . Since the thickness of the second gate dielectric layer 220 is the sum of the thicknesses of the first gate dielectric material layer and the second gate dielectric material layer 221 , it can be ensured that the thickness of the second gate dielectric layer 220 is greater than the thickness of the second gate dielectric layer 220 .
  • a high-K dielectric layer 230 is formed.
  • the high-K dielectric layer 230 covers the first gate dielectric layer 210 and the second gate dielectric layer 220 .
  • the high-K dielectric layer 230 is made of a material with a dielectric constant greater than that of silicon dioxide, such as hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO2), hafnium silicon oxynitride (HfSiON), etc.
  • the high-K dielectric layer 230 may be formed using processes such as chemical vapor deposition or atomic layer deposition.
  • step S11 the first photomask is used to remove the high-K dielectric layer 230 in the second device area A2 through a negative development or positive development process to expose the second gate dielectric layer 220 .
  • the high-K dielectric layer 230 located in the second device region A2 is removed, and the high-K dielectric layer 230 located in the first device region A1 is retained.
  • removing the high-K dielectric layer 230 includes:
  • the first photomask is used to form a second mask layer 320 on the surface of the high-K dielectric layer 230 in the first device area A1 through a negative development or positive development process.
  • the second mask layer 320 only covers the high-K dielectric layer 230 in the first device region A1, and the surface of the high-K dielectric layer 230 in the second device region A2 is exposed.
  • the second mask layer 320 is a photoresist layer.
  • the photoresist layer located in the first device area A1 can be retained through negative development or positive development as the second mask layer.
  • Film layer 320 is a photoresist layer.
  • the purpose of forming the second gate dielectric layer and removing the high-K dielectric layer can be achieved through the same first photomask, which greatly reduces the cost and simplifies the preparation process. It can be understood that since the positions of the first mask layer 310 and the second mask layer 320 are complementary, if a positive development process is used when forming the first mask layer 310, the second mask layer 320 will be formed. If the negative development process is used to form the first mask layer 310, then the positive development process is used to form the second mask layer 320.
  • the following steps are also included: forming a protective layer 330 on the surface of the high-K dielectric layer 230.
  • the protective layer 330 is used to protect the high-K dielectric layer 230 located in the first device region A1 in subsequent processes.
  • the protective layer 330 may be a SiN layer or a SiON layer.
  • the protective layer 330 is formed through a chemical vapor deposition process. It can be understood that in this embodiment, in the first device area A1, the second mask layer 320 is formed on the surface of the protective layer 330.
  • the step of forming the protective layer 330 is an optional step. In other embodiments, the protective layer 330 may not be formed, but the second mask layer 320 may be formed directly on the surface of the high-K dielectric layer 230 .
  • the high-K dielectric layer 230 is removed in the second device area A2 to expose the second gate dielectric layer 220 .
  • the high-K dielectric layer 230 is removed using an etching process, such as a wet etching process. Since the second mask layer 320 only blocks the high-K dielectric layer 230 in the first device region A1, the high-K dielectric layer 230 in the first device region A1 is retained, and the high-K dielectric layer 230 in the first device region A1 is retained.
  • the high-K dielectric layer 230 in the second device region A2 is removed, exposing the second gate dielectric layer 220 .
  • the protective layer 330 is also removed in the second device area A2.
  • the protective layer 330 and the second mask layer 320 together serve as a mask to protect the high-K dielectric layer 230 in the first device region A1.
  • the second mask layer 320 is removed to expose the high-K dielectric layer 230 .
  • the protective layer 330 on the surface of the high-K dielectric layer 230 is also removed.
  • the second mask layer 320 and the protective layer 330 can be removed using ashing and etching processes.
  • step S12 in the first device region A1, a first gate structure 240 is formed on the surface of the high-K dielectric layer 230.
  • a second gate structure 250 is formed on the surface of the second gate dielectric layer 220 .
  • the first gate dielectric layer 210 and the high-K dielectric layer 230 are used as insulating isolation layers between the first gate structure 240 and the substrate 201.
  • the second gate dielectric layer 220 is used as an insulating isolation layer between the second gate structure 250 and the substrate 201, that is, there is no high-K dielectric in the second device region A2.
  • layer 230 so that the diffusion of dipoles in the high-K dielectric layer 230 will not be affected by the presence of the thicker second gate dielectric layer 220.
  • the second gate structure 250 can play a good role in regulating the threshold voltage and avoid the third The threshold voltage of the second device region A2 is too high, which improves the stability of the semiconductor device in the second device region A2.
  • the first gate structure 240 includes a first NMOS transistor gate structure 241 and a first PMOS transistor gate structure 242.
  • the first NMOS transistor gate structure 241 and the first P-well Region 203 is provided correspondingly, and the first PMOS transistor gate structure 242 is provided correspondingly to the first N-well region 202;
  • the second gate structure 250 includes a second NMOS transistor gate structure 251 and a second PMOS transistor gate.
  • the second NMOS transistor gate structure 252 is provided correspondingly to the second P-well region 205
  • the second PMOS transistor gate structure 252 is provided correspondingly to the second N-well region 204 .
  • the steps of forming the first gate structure 240 and the second gate structure 250 include: forming a first NMOS transistor gate structure 241 in the first P-well region 203 , and forming a first N-well region 202 in the first N-well region 202 .
  • a first PMOS transistor gate structure 242 is formed, a second NMOS transistor gate structure 251 is formed in the second P-well region 205 , and a second PMOS transistor gate structure 252 is formed in the second N-well region 204 .
  • embodiments of the present disclosure also provide a method of forming the first gate structure 240 and the second gate structure 250 .
  • the method of forming the first gate structure 240 and the second gate structure 250 includes:
  • a PMOS transistor metal gate layer 260 is formed in the first N-well region 202 and the second N-well region 204 .
  • the PMOS transistor metal gate layer 260 includes a work function metal layer and/or a TiN layer.
  • the work function metal layer may be an Al 2 O 3 layer.
  • the PMOS transistor metal gate layer 260 includes a TiN layer, an Al 2 O 3 layer, and a TiN layer arranged in sequence.
  • an NMOS transistor metal gate layer 261 is formed in the first P-well region 203 and the second P-well region 205 .
  • the NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer.
  • the work function metal layer may be a La 2 O 3 layer.
  • the NMOS transistor metal gate layer 261 includes a La 2 O 3 layer and a TiN layer arranged in sequence.
  • the NMOS transistor metal gate layer 261 is also formed on the surface of the PMOS transistor metal gate layer 260 , that is, in the first N-well region 202 and the second N-well region. 204, a PMOS transistor metal gate layer 260 and an NMOS transistor metal gate layer 261 are formed.
  • a gate composite material layer 262 is formed.
  • the gate composite material layer 262 covers the NMOS transistor metal gate layer 261 and the PMOS transistor metal gate layer 260 .
  • the gate composite material layer 262 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer arranged in sequence. Only one layer is schematically shown in the drawing.
  • the gate composite material layer 262, the NMOS transistor metal gate layer 261 and the PMOS transistor metal gate layer 260 are patterned to form the first NMOS transistor gate structure 241, the first PMOS transistor gate structure 242, the second NMOS transistor gate structure 251 and the second PMOS transistor gate structure 252.
  • photolithography and etching processes may be used to pattern the gate composite material layer 262 , the NMOS transistor metal gate layer 261 and the PMOS transistor metal gate layer 260 .
  • the gate composite material layer 262 located on the metal gate layer 261 of the NMOS transistor forms a first gate composite layer 263, and the gate composite material layer 262 located on the metal gate layer 260 of the PMOS transistor forms a second gate composite layer 263.
  • Gate composite layer 264 is patterned to form the first NMOS transistor gate structure 241, the first PMOS transistor gate structure 242, the second NMOS transistor gate structure 251 and the second PMOS transistor gate structure 252.
  • the first gate dielectric layer 210, the high-K dielectric layer 230, and the second gate dielectric layer 220 are also patterned.
  • the substrate 201 on both sides of the first NMOS transistor gate structure 241, the first PMOS transistor gate structure 242, the second NMOS transistor gate structure 251 and the second PMOS transistor gate structure 252 is Exposed, doping can be performed to form source and drain regions.
  • part of the silicon germanium layer 206 is removed, leaving only the silicon germanium layer 206 located under the first PMOS transistor gate structure 242 .
  • the formation method of the semiconductor structure provided by the embodiment of the present disclosure will not affect the high-K dielectric layer 230 of the first device region A1 due to the removal of the high-K dielectric layer 230 of the second device region A2.
  • the high-K dielectric layer 230 is still formed in A1, which further ensures the stability of the semiconductor structure of the first device region A1.
  • the formation method provided by the embodiment of the present disclosure has a simple process and can avoid the defect that the second gate structure 250 of the second device region A2 cannot adjust the threshold voltage well without complicated processes, which greatly improves the practicality of the semiconductor process.
  • Embodiments of the present disclosure also provide a semiconductor structure formed using the above forming method.
  • the semiconductor structure includes a substrate 201 , a first gate dielectric layer 210 , a second gate dielectric layer 220 , a high-K dielectric layer 230 , a first gate structure 240 and a second gate structure 250 .
  • the substrate 201 has a first device region A1 and a second device region A2.
  • the first gate dielectric layer 210 covers the surface of the substrate 201
  • the high-K dielectric layer 230 covers the surface of the first gate dielectric layer 210
  • the first gate structure 240 is located on the surface of the high-K dielectric layer 230.
  • the second gate dielectric layer 220 covers the surface of the substrate 201
  • the second gate structure 250 is located on the surface of the second gate dielectric layer 220
  • the first gate dielectric layer 210 The thickness is less than the thickness of the second gate dielectric layer 220 .
  • the first gate dielectric layer 210 in the first device region A1 is thinner and is a thin oxygen device region
  • the second gate dielectric layer 220 in the second device region A2 is thicker. , which is the thick oxygen device region.
  • the first device region A1 includes a first N-well region 202 and a first P-well region 203
  • the first gate structure 240 includes a first NMOS transistor gate structure 241 and a first PMOS transistor.
  • Gate structure 242 , the first NMOS transistor gate structure 241 is disposed on the first P-well region 203
  • the first PMOS transistor gate structure 242 is disposed on the first N-well region 202 .
  • the semiconductor structure further includes a silicon germanium layer 206.
  • the silicon germanium layer 206 is disposed between the first gate dielectric layer 210 and the substrate 201. between.
  • the lattice constant of silicon is 0.543nm
  • the lattice constant of germanium is 0.567nm. The difference between the two is 4.17%. Therefore, the introduction of germanium element into pure silicon will form a silicon germanium (SiGe) material with stress.
  • SiGe silicon germanium
  • the bandgap width of the silicon germanium material can change and it is easy to form a heterostructure.
  • the electron and hole mobility of the silicon germanium material are higher than that of silicon. Using silicon germanium material as a channel can help improve Hole Mobility in Channels of Semiconductor Structures.
  • the first NMOS transistor gate structure 241 includes an NMOS transistor metal gate layer 261 and a first gate composite layer 263 covering the NMOS transistor metal gate layer 261 .
  • the NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer.
  • the work function metal layer may be a La 2 O 3 layer.
  • the NMOS transistor metal gate layer 261 includes a La 2 O 3 layer and a TiN layer arranged in sequence.
  • the first gate composite layer 263 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer arranged in sequence.
  • the first PMOS transistor gate structure 242 includes a PMOS transistor metal gate layer 260 and a second gate composite layer 264 covering the PMOS transistor metal gate layer 260 .
  • the PMOS transistor metal gate layer 260 includes a work function metal layer and/or a TiN layer.
  • the work function metal layer may be an Al2O3 layer.
  • the PMOS transistor metal gate layer 260 includes a TiN layer, an Al2O3 layer and a TiN layer arranged in sequence.
  • the second gate composite layer 264 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer arranged in sequence.
  • the second device region A2 includes a second N-well region 204 and a second P-well region
  • the second gate structure 250 includes a second NMOS transistor gate structure 251 and a second PMOS transistor gate.
  • the second NMOS transistor gate structure 252 is provided on the second P-well region 205
  • the second PMOS transistor gate structure 252 is provided on the second N-well region 204 .
  • the second NMOS transistor gate structure 251 includes an NMOS transistor metal gate layer 261 and a first gate composite layer 263 covering the NMOS transistor metal gate layer 261 .
  • the NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer.
  • the second NMOS transistor gate structure 251 is the same as the first NMOS transistor gate structure 241 and will not be described again here.
  • the second PMOS transistor gate structure 252 includes a PMOS transistor metal gate layer 260, an NMOS transistor metal gate layer 261 covering the PMOS transistor metal gate layer 260, and a third NMOS transistor metal gate layer 261 covering the NMOS transistor metal gate layer 260. Two-gate composite layer 264. In this embodiment, the second PMOS transistor gate structure 252 is the same as the first PMOS transistor gate structure 242 and will not be described again here.
  • the semiconductor structure provided by the embodiment of the present disclosure provides a high-K dielectric layer 230 between the first gate structure 240 and the substrate 201 in the first device region A1 (thin oxygen device region) to reduce the The first gate structure 240 leaks current, and in the second device region A2 (thick oxide device region), only the larger thickness of the gate electrode structure 250 is used between the second gate structure 250 and the substrate 201 .
  • the second gate dielectric layer 220 serves as an isolation layer without the high-K dielectric layer 230, which not only reduces the leakage current of the second gate structure 250 but also avoids high voltage caused by the thickness of the second gate dielectric layer 220 being too thick.
  • the problem of dipole diffusion of the K dielectric layer 230 enables the second gate structure 250 to play a good threshold voltage adjustment role, avoid the threshold voltage of the second device region A2 from being too high, and improve the Stability of the semiconductor device in the second device region A2.

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Abstract

Procédé de formation d'une structure semi-conductrice consistant à : former un substrat, le substrat comprenant une base, la base ayant une première région de dispositif et une seconde région de dispositif, la surface de la base dans la première région de dispositif étant recouverte par une première couche diélectrique de grille, et la surface de la base dans la seconde région de dispositif étant recouverte par une seconde couche diélectrique de grille, l'épaisseur de la première couche diélectrique de grille étant inférieure à l'épaisseur de la seconde couche diélectrique de grille, la surface de la première couche diélectrique de grille et la surface de la seconde couche diélectrique de grille étant recouvertes par une couche diélectrique à constante K élevée et la seconde couche diélectrique de grille étant formée au moyen d'un processus de développement positif ou de développement négatif en utilisant un premier photomasque ; retirer la couche diélectrique à constante K élevée dans la seconde région de dispositif au moyen d'un processus de développement négatif ou de développement positif en utilisant le premier photomasque de façon à exposer la seconde couche diélectrique de grille ; et former une première structure de grille sur la surface de la couche diélectrique à constante K élevée dans la première région de dispositif et former une seconde structure de grille sur la surface de la seconde couche diélectrique de grille dans la seconde région de dispositif. Le procédé de formation a un processus simple, permet de réduire les coûts et d'assurer la stabilité du dispositif.
PCT/CN2022/134057 2022-08-26 2022-11-24 Structure semi-conductrice et son procédé de formation WO2024040771A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074664B1 (en) * 2005-03-29 2006-07-11 Freescale Semiconductor, Inc. Dual metal gate electrode semiconductor fabrication process and structure thereof
US20060246651A1 (en) * 2005-04-29 2006-11-02 Texas Instruments Incorporated Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
CN104217935A (zh) * 2013-06-05 2014-12-17 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105226023A (zh) * 2014-06-26 2016-01-06 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7074664B1 (en) * 2005-03-29 2006-07-11 Freescale Semiconductor, Inc. Dual metal gate electrode semiconductor fabrication process and structure thereof
US20060246651A1 (en) * 2005-04-29 2006-11-02 Texas Instruments Incorporated Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
CN104217935A (zh) * 2013-06-05 2014-12-17 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105226023A (zh) * 2014-06-26 2016-01-06 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法

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