WO2024040758A1 - 电压生成电路及存储器 - Google Patents

电压生成电路及存储器 Download PDF

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Publication number
WO2024040758A1
WO2024040758A1 PCT/CN2022/132407 CN2022132407W WO2024040758A1 WO 2024040758 A1 WO2024040758 A1 WO 2024040758A1 CN 2022132407 W CN2022132407 W CN 2022132407W WO 2024040758 A1 WO2024040758 A1 WO 2024040758A1
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Prior art keywords
voltage
power supply
output
generation circuit
operational amplifier
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Ceased
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PCT/CN2022/132407
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English (en)
French (fr)
Inventor
秦建勇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/364,481 priority Critical patent/US12362001B2/en
Publication of WO2024040758A1 publication Critical patent/WO2024040758A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the present disclosure relates to, but is not limited to, a voltage generation circuit and a memory.
  • DRAM Dynamic Random Access Memory
  • semiconductor technology With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of memory cells is getting higher and higher. At the same time, various applications have higher and higher requirements on the performance, power consumption and reliability of DRAM.
  • Embodiments of the present disclosure provide a voltage generation circuit and a memory, which can at least improve the accuracy of the voltage generation circuit.
  • an embodiment of the present disclosure provides a voltage generation circuit, including: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node. , and the power supply node is used to connect with the load to supply power to the load; the voltage stabilizing module is configured to receive the reference voltage, generate and output a control signal; the compensation module is configured to receive the power supply voltage, flag signal and the control signal, and is turned on in response to the flag signal, and in response to providing a second output voltage to the power supply node based on the voltage value of the control signal, so that the voltage of the power supply node is restored to the desired
  • the first output voltage and the flag signal indicate that the load is in operation.
  • the compensation module includes: a switching unit for receiving the flag signal and outputting the power supply voltage based on the flag signal; an adjustment unit connected to the switching unit for receiving the The power supply voltage and the control signal are used to adjust the output amplitude of the compensation module based on the voltage value of the control signal.
  • the switching unit includes: a first PMOS transistor, the gate of the first PMOS transistor receives the flag signal, and the source is connected to the working power supply;
  • the adjustment unit includes: a first NMOS transistor, so The gate of the first NMOS transistor receives the control signal, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the source of the first NMOS transistor is connected to the power supply node to provide the second output voltage.
  • the voltage stabilizing module includes: a first operational amplifier, a non-inverting input terminal of the first operational amplifier receives the reference voltage, and an output terminal of the first operational amplifier outputs the control signal; A first resistor, one end of the first resistor is connected to ground, and the other end is connected to the inverting input end of the first operational amplifier; a second PMOS transistor, the source of the second PMOS transistor is connected to the power supply voltage; a second NMOS tube, the gate of the second NMOS tube is connected to the output terminal of the first operational amplifier, the drain of the second NMOS tube is connected to the drain of the second PMOS tube; the second resistor, the One end of the second resistor is connected to the inverting input end of the first operational amplifier, and the other end is connected to the source of the second NMOS transistor.
  • the width-to-length ratio of the first NMOS transistor channel is equal to the width-to-length ratio of the second NMOS transistor channel.
  • the voltage generation circuit further includes: a first voltage generation module that receives the reference voltage and generates a driving voltage for driving the first operational amplifier to operate.
  • the voltage value of the driving voltage is greater than the sum of the voltage value corresponding to the control signal and the voltage value of the turn-on voltage of the second NMOS transistor.
  • a flag signal generation module is further included, configured to generate the flag signal based on an enable signal, where the enable signal is used to control the load operation.
  • the voltage output module includes: a second operational amplifier, an inverting input terminal of the second operational amplifier receives the reference voltage; a third resistor, one end of the third resistor is grounded, and the other end Connect the non-inverting input terminal of the second operational amplifier; a third PMOS tube, the gate of the third PMOS tube is connected to the output terminal of the second operational amplifier, the source is connected to the working power supply, the third PMOS tube The drain of the tube outputs the first output voltage; a fourth resistor, one end of the fourth resistor is connected to the non-inverting input end of the second operational amplifier, and the other end is connected to the drain of the third PMOS tube.
  • the voltage value of the working power supply connected to the source of the third PMOS tube is equal to the voltage value of the driving voltage of the second operational amplifier.
  • a second voltage generation module is further included, and the second voltage generation module is used to provide the reference voltage.
  • it further includes: a capacitor, one end of the capacitor is connected to the output end of the voltage output module, and the other end is connected to ground.
  • another aspect of the present disclosure further provides a memory, including: the above-mentioned voltage generation circuit; a load, the load is connected to the power supply node, and the load operates in response to an enable signal.
  • Figure 1 is a schematic structural diagram of a voltage generation circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a voltage generation circuit provided by another embodiment of the present disclosure.
  • Figure 3 is a specific structural schematic diagram of a voltage generation circuit provided by another embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a voltage output module provided by another embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a flag signal generation module provided by another embodiment of the present disclosure.
  • Figure 6 is a signal fluctuation diagram provided by another embodiment of the present disclosure.
  • the circuit provided in Figure 1 is a voltage generation circuit provided in the prior art.
  • the voltage generation circuit provided in the prior art includes: a bandgap reference voltage generation module 100 and a reference
  • the voltage generation module 110 provides a reference voltage; a plurality of voltage stabilizing circuit modules 120, and a load module 130 connected to each voltage stabilizing circuit module 120 in a one-to-one correspondence, wherein the plurality of voltage stabilizing circuit modules 120 include: an operational amplifier 140, The inverting input terminal of the operational amplifier 140 receives the reference voltage; the fifth resistor 150 has one end connected to ground, and the other end is connected to the non-inverting input terminal of the operational amplifier 140; the PMOS tube 160, the gate of the PMOS tube 160 and the operational amplifier The output end of 140 is connected, and the source is connected to the working power supply; the sixth resistor 170, one end of the sixth resistor 170 is connected to the non-inverting input end of the operational amplifier 140, and the other end is connected to the drain of
  • the bandgap reference voltage is generated by the bandgap reference voltage generation module 100 and is output to the reference voltage generation module 110.
  • the reference voltage generation module 110 receives the bandgap reference voltage and generates and outputs the reference voltage.
  • the voltage stabilizing circuit Module 120 receives the reference voltage and outputs the target output voltage to load module 130 .
  • the load module 130 consumes part of the output voltage, so that the output voltage provided by the connection node between the load module 130 and the voltage stabilizing circuit module 120 is reduced, causing the voltage provided to the load module 130 to be lower than
  • the default value may result in some components of the load module 130 not working properly.
  • the implementation of the present disclosure provides a voltage generation circuit and memory, which receives a reference voltage through a voltage output module to provide a first output voltage to a power supply node, supplies power to the load through the power supply node, and outputs a control signal to a compensation module through a voltage stabilizing module. Receive the power supply voltage, the flag signal and the control signal and provide the second output voltage to the power supply node to restore the voltage of the power supply node to the first output voltage, so that when the load is operating, the voltage provided by the power supply node to the load can be stabilized as the first output voltage, thereby improving the accuracy of the voltage generation circuit.
  • Figure 2 is a schematic structural diagram of a circuit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a voltage stabilizing module, a compensation module and a second voltage generating module provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of a voltage output module provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of a sign signal generation module provided by an embodiment of the present disclosure
  • Figure 6 is a signal fluctuation diagram provided by an embodiment of the present disclosure.
  • Voltage generation circuit including:
  • the voltage output module 200 is configured to receive the reference voltage Vref, generate the first output voltage Vout1 and provide the first output voltage Vout1 to the power supply node, and the power supply node is used to connect with the load to supply power to the load.
  • the voltage stabilizing module 210 is configured to receive the reference voltage Vref, generate and output the control signal Vctrl.
  • the compensation module 220 is configured to receive the power supply voltage VPwr, the flag signal Reg and the control signal Vctrl, and to be turned on in response to the flag signal Reg, and to provide the second output voltage Vout2 to the power supply node in response to a voltage value based on the control signal Vctrl, In order to restore the voltage of the power supply node to the first output voltage Vout1, the flag signal Reg indicates that the load is in operation.
  • the load when the load is in operation, it receives the first output voltage Vout1 from the voltage output module 200 and is turned on. Since the load is turned on, the first output voltage Vout1 of the power supply node is consumed, resulting in the first output voltage Vout1 of the power supply node. The voltage value drops.
  • the voltage stabilizing module 210 works and receives the reference voltage Vref to provide the control signal Vctrl to the compensation module 220.
  • the compensation module 220 receives the power supply voltage VPwr, the flag signal Reg and the control signal Vctrl, and is turned on in response to the flag signal Reg. , and generate and output the second output voltage Vout2 according to the voltage value of the control signal Vctrl.
  • the power supply node receives the second output voltage Vout2 from the compensation module to compensate the first output voltage Vout1 consumed by the load, so that the voltage provided by the power supply node to the load Stable at the first output voltage Vout1, so that the voltage signal received by the load will not fluctuate due to its own turning on, and the voltage provided by the voltage generation circuit to the load can be stabilized at the first output voltage Vout1, thereby improving the voltage generation circuit accuracy.
  • the compensation module 220 in the above embodiment is turned on in response to the flag signal, and the flag signal Reg can be generated based on the enable signal En.
  • the compensation module 220 can also be configured to be directly based on the enable signal En. En conduction.
  • the compensation module 220 may include: a switch unit 221 for receiving the flag signal Reg and outputting the power supply voltage VPwr based on the flag signal Reg; an adjustment unit 222 connected to the switch unit 221 for The power supply voltage VPwr and the control signal Vctrl are received to adjust the output amplitude of the compensation module 220 based on the voltage value of the control signal Vctrl. Whether the compensation module 220 works can be controlled through the switch unit 221. That is to say, when the load is working, the switch unit 221 receives the flag signal Reg and outputs the power supply voltage VPwr to the adjustment unit 222. The adjustment unit 222 can always be turned on.
  • the switching unit 221 may include: a first PMOS transistor 223, the gate of the first PMOS transistor 223 receives the flag signal Reg, and the source is connected to the working power supply;
  • the adjustment unit 222 includes: a first NMOS transistor 224, a first The gate of the NMOS transistor 224 receives the control signal Vctrl, the drain of the first NMOS transistor 224 is connected to the drain of the first PMOS transistor 223, and the source of the first NMOS transistor 224 is connected to the power supply node to provide the second output voltage Vout2.
  • the working power supply can be used to provide the power supply voltage VPwr
  • the flag signal Reg can include two states, one of which is a high level state and the other is a low level state.
  • the gate When the drain of the first NMOS transistor 224 After receiving the power supply voltage VPwr, the gate receives the control signal Vctrl, the first NMOS transistor 224 is turned on, and provides the second output voltage Vout2 to the power supply node through the source, thereby restoring the voltage value of the power supply node to the first output voltage Vout1 , thereby improving the accuracy of the voltage value provided by the voltage generation circuit.
  • the voltage generation circuit may include multiple compensation modules 220 and multiple power supply nodes, and each compensation module 220 is connected to a power supply node to provide the second output voltage to different loads 280 through the multiple power supply nodes. Vout2, so that each load 280 has a corresponding compensation module 220, and by connecting multiple compensation modules 220 in parallel, the layout area of the voltage generation circuit can be reduced, and the voltage generation circuit has a faster response speed.
  • the voltage stabilizing module 210 may include: a first operational amplifier 211, the non-inverting input terminal of the first operational amplifier 211 receives the reference voltage Vref, and the output terminal of the first operational amplifier 211 outputs the control signal Vctrl; a first resistor 212, one end of the first resistor 212 is connected to ground, and the other end is connected to the inverting input end of the first operational amplifier 211; the second PMOS transistor 213, the source of the second PMOS transistor 213 is connected to the power supply voltage VPwr; the second NMOS transistor 214, The gate of the second NMOS transistor 214 is connected to the output terminal of the first operational amplifier 211, and the drain of the second NMOS transistor 214 is connected to the drain of the second PMOS transistor 213; the second resistor 215 has one end of the second resistor 215 and The inverting input end of the first operational amplifier 211 is connected, and the other end is connected to the source of the second NMOS transistor 214 .
  • the voltage stabilizing principle of the voltage stabilizing module 210 is: when the output voltage decreases, the voltage provided to the inverting input terminal of the first operational amplifier 211 decreases through the voltage dividing effect of the first resistor 212 and the second resistor 215. However, The voltage value of the reference voltage Vref connected to the non-inverting input terminal of the first operational amplifier 211 is stable. Therefore, the output voltage of the output terminal of the first operational amplifier 211 increases accordingly, and the gate voltage of the second NMOS transistor 214 increases, stabilizing the voltage. The output voltage of the module 210 increases accordingly, suppressing the decrease in the output voltage, thereby maintaining a stable output.
  • the source of the second PMOS transistor 213 is connected to the power supply voltage VPwr, and the gate can be grounded. Therefore, the second PMOS transistor 213 is always turned on, from the drain of the second PMOS transistor 213 to the second NMOS.
  • the drain of the tube provides the power supply voltage VPwr, and the gate of the second NMOS tube 214 is connected to the output terminal of the first operational amplifier 211.
  • the reference voltage Vref is provided to the first operational amplifier 211, the second NMOS tube 214 is turned on, and the entire The voltage stabilizing module 210 starts working.
  • Vout3 represents the voltage of the third output voltage that the voltage stabilizing module 210 can provide.
  • the value, Vth represents the threshold voltage of the second NMOS transistor 214 .
  • the width-to-length ratio of the channel of the first NMOS transistor 224 is equal to the width-to-length ratio of the channel of the second NMOS transistor 214. It can be understood that the width-to-length ratio of the channel of the first NMOS transistor 224 is equal to the width-to-length ratio of the channel of the second NMOS transistor 214. The width-to-length ratio of the channel of the NMOS transistor 214 is equal, which means that the threshold voltage of the first NMOS transistor 224 is equal to the threshold voltage of the second NMOS transistor 214.
  • the voltage value output through the source of the first NMOS transistor 224 is Vctrl minus the threshold voltage of the first NMOS transistor 224, that is, the voltage value equal to the third output voltage Vout3, that is, the second
  • the voltage value of the output voltage Vout2 is equal to the voltage value of the third output voltage Vout3.
  • the voltage value of the third output voltage Vout3 is equal to the voltage value of the first output voltage Vout1.
  • the width-to-length ratio is equal to the width-to-length ratio of the channel of the second NMOS transistor 214, which can control the voltage value of the second output voltage Vout2 to be equal to the voltage value of the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit and allowing the voltage to be generated.
  • the voltage value provided by the circuit to the power supply node is stabilized at the first output voltage Vout1.
  • the width-to-length ratio of the channel of the first NMOS transistor 224 is equal to the width-to-length ratio of the channel of the second NMOS transistor 214, which means they are ideally equal. In fact, the width-to-length ratio of the channel of the first NMOS transistor 224 is equal to There may be a certain deviation from the width-to-length ratio of the channel of the second NMOS transistor 214. However, the bias voltage needs to be within the preset deviation range, that is to say, the actual output voltage of the compensation module 220 and the ideal second output voltage Vout2 The voltage difference between them is within the preset range; in other words, the actual output voltage of the compensation module 220 may be slightly larger or slightly smaller than the ideal second output voltage Vout2.
  • the compensation module 220 may generate greater noise.
  • the actual output voltage of the compensation module 220 is much lower than the ideal second output voltage Vout2
  • the ability of the voltage of the stable power supply node to recover to the first output voltage Vout1 is relatively low. Poor, poor improvement effect.
  • the voltage generation circuit further includes: a first voltage generation module 230 that receives the reference voltage Vref and generates a driving voltage Vhv for driving the first operational amplifier 211 to operate.
  • the voltage value of the driving voltage Vhv is greater than the sum of the voltage value corresponding to the control signal Vctrl and the threshold voltage of the NMOS transistor internally connected in series between the power supply terminal of the first operational amplifier 211 and the output terminal of the first operational amplifier 211 .
  • the voltage of the driving voltage Vhv should be greater than the voltage value corresponding to the control signal Vctrl and the corresponding threshold values of the multiple MOS tubes.
  • the sum of the voltages, that is, the maximum value of the output voltage of the first operational amplifier 211 is greater than the voltage value corresponding to the control signal Vctrl.
  • the voltage generation circuit may further include: a flag signal generation module 240 configured to generate a flag signal Reg based on the enable signal En, which is used to control the load 280 to operate.
  • the flag signal generation module 240 can convert the enable signal En into the corresponding flag signal Reg.
  • the flag signal generation module 240 provides the first enable signal En1, the second enable signal En2 and the third enable signal En2.
  • the enable signal En3 can generate the corresponding first flag signal Reg1, the second flag signal Reg2 and the third flag signal Reg3 through the flag signal generation module 240, and different enable signals En can be provided to different loads.
  • the enable signal The flag signal Reg corresponding to En can be provided to the compensation module 220 connected to the corresponding load 280, so that when the first enable signal En1 corresponding to the load 280 is turned on, the compensation module 220 that receives the first flag signal Reg1 starts to work to provide the signal to the load. 280 provides the second output voltage Vout2, so that the voltage of the power supply node corresponding to the load 280 can be compensated.
  • the voltage output module 200 may include: a second operational amplifier 201, the inverting input terminal of the second operational amplifier 201 receives the reference voltage Vref; a third resistor 202, one end of the third resistor 202 is grounded , the other end is connected to the non-inverting input terminal of the second operational amplifier 201; the third PMOS tube 203, the gate of the third PMOS tube 203 is connected to the output terminal of the second operational amplifier 201, the source is connected to the working power supply, the third PMOS tube 203 The drain of 203 outputs the first output voltage Vout1; the fourth resistor 204 has one end connected to the non-inverting input end of the second operational amplifier 201 and the other end connected to the drain of the third PMOS transistor 203.
  • the working principle of the voltage output module 200 is: when the output voltage of the voltage output module 200 decreases, the non-inverting input of the second operational amplifier 201 is provided through the voltage dividing effect of the third resistor 202 and the fourth resistor 204 The voltage at the terminal decreases, but the voltage value of the reference voltage Vref connected to the inverting input terminal of the second operational amplifier 201 is stable. Therefore, the voltage at the output terminal of the second operational amplifier 201 decreases accordingly, and the voltage of the third PMOS tube 203 As the gate voltage decreases, the output voltage of the voltage output module 200 increases accordingly, suppressing the decrease in the output voltage, thereby maintaining stable output.
  • the voltage value of the working power supply connected to the source of the third PMOS transistor 203 is equal to the voltage value of the driving voltage of the second operational amplifier 201.
  • the source of the third PMOS transistor 203 is connected to the voltage of the second operational amplifier 201.
  • 201 can be connected to the same working power supply, reducing the complexity caused by setting different power supplies.
  • the specifications of the first operational amplifier 211 can also be the same as the specifications of the second operational amplifier 201, so that the difference between the third output voltage Vout3 and the first output voltage Vout1 can be reduced, so that the difference based on the control signal can be reduced.
  • the difference between the second output voltage Vout2 generated by Vctrl and the first output voltage Vout1 causes the voltage of the power supply node to return to the first output voltage Vout1.
  • the voltage generation circuit may further include: a second voltage generation module 250.
  • the second voltage generation module 250 is used to provide the reference voltage Vref.
  • the second voltage generation module 250 can provide the voltage output module 200 and the voltage stabilizing module. 210 and the first voltage generation module 230 provide the reference voltage Vref.
  • the second voltage generation module 250 may include: a first voltage generation unit 251 and a second voltage generation unit 252.
  • the first voltage generation unit 251 may generate the bandgap reference voltage Vbgr.
  • the second voltage generation unit 252 The band gap reference voltage Vbgr can be received to generate the reference voltage Vref.
  • the band gap reference voltage Vbgr is a stable voltage signal, and the magnitude of the voltage value is not affected by temperature. Therefore, the band gap provided by the first voltage generation unit 251 The reference voltage Vbgr is not affected by temperature, thereby generating a stable reference voltage Vref.
  • the voltage generation circuit may further include: a capacitor 260, one end of the capacitor is connected to the output end of the voltage output module 200, and the other end is connected to ground.
  • a capacitor 260 By providing the capacitor 260, it can play a filtering role, thereby reducing the reliability of the voltage provided by the voltage generating circuit.
  • the voltage generation circuit may also include: a resistor 270.
  • One end of the resistor 270 is connected to the output end of the voltage output module 200, and the other end is connected to the power supply node.
  • Figure 6 is a signal fluctuation diagram of the voltage generation circuit.
  • a high-level power supply voltage VPwr is always provided to enable the voltage stabilizing module 210 and the flag signal generation module 240 to start working, and to The load 280 and the flag signal generation module 240 provide the enable signal En.
  • the enable signal En is high level
  • the load 280 is turned on, causing the voltage of the power supply node connected to the load 280 to fluctuate
  • the synchronization flag signal generation module 240 provides the flag signal Reg to the compensation module 220, so that the compensation module 220 works and provides the second output voltage Vout2 to the power supply node to compensate the voltage of the power supply node.
  • the power supply node receives the first output voltage Vout1 from the voltage output module 200, the voltage rises, the enable signal En becomes high level, the load 280 is turned on, causing the voltage of the power supply node to be consumed , begins to decrease, and the power supply node is compensated through the work of the compensation module 220, slowing down the voltage drop of the power supply node.
  • the enable signal En becomes low level again, the load is turned off, and the flag signal
  • the compensation module 220 is turned off, the power supply node receives the first output voltage Vout1 from the voltage output module 200, and the voltage rises.
  • the embodiment of the present disclosure has a smaller layout area, a smaller power margin range from the power supply voltage VPwr to the first output voltage Vout1, and consumes less power consumption. , faster response speed and higher accuracy.
  • the embodiment of the present disclosure provides the first output voltage Vout1 to the power supply node through the voltage output module 200.
  • the voltage stabilizing module 210 works and receives the reference voltage Vref to provide the control signal Vctrl to the compensation module 220.
  • the module 220 receives the power supply voltage VPwr, the flag signal Reg and the control signal Vctrl, and is turned on in response to the flag signal Reg, and generates and outputs the second output voltage Vout2 according to the voltage value of the control signal Vctrl to the power supply node, thereby compensating the power supply node for being damaged.
  • the first output voltage Vout1 consumed by the load causes the voltage provided by the voltage generation circuit to the load to be stabilized at the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit.
  • each unit involved in this embodiment is a logical unit.
  • a logical unit can be a physical unit, or a part of a physical unit, or it can be multiple physical units. The combination of units is realized.
  • units that are not closely related to solving the technical problems raised in this application are not introduced in this embodiment, but this does not mean that other units do not exist in this embodiment.
  • Another embodiment of the present disclosure also provides a memory, which may include the above-mentioned voltage generation circuit.
  • the memory provided by the embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the previous embodiment can be referred to The response description of the foregoing embodiment will not be described in detail below.
  • the memory provided by the embodiment of the present disclosure includes: the voltage generation circuit as described above; a load 280, the load 280 is connected to the power supply node, and the load 280 operates in response to the enable signal En.
  • the embodiment of the present disclosure provides the first output voltage Vout1 to the power supply node through the voltage output module 200.
  • the voltage stabilizing module 210 works and receives the reference voltage Vref to provide the control signal Vctrl to the compensation module 220.
  • the compensation module 220 receives the power supply voltage VPwr, the flag signal Reg and the control signal Vctrl, and is turned on in response to the flag signal Reg, and generates and outputs the second output voltage Vout2 according to the voltage value of the control signal Vctrl to the power supply node, thereby compensating the voltage on the power supply node.
  • the first output voltage Vout1 consumed by the load 280 causes the voltage provided by the voltage generation circuit to the load 280 to be stabilized at the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit.
  • the number of loads 280 is multiple, and different loads 280 work in response to different enable signals En; the voltage generation circuit has multiple power supply nodes, and each power supply node is connected to a load 280; voltage The generation circuit includes a plurality of compensation modules 220, and each compensation module 220 provides the second output voltage Vout2 to the corresponding power supply node in response to the corresponding flag signal Reg.
  • the three loads 280 can be divided into a first load, a second load and a third load.
  • the first load, the second load and the third load are connected to different power supply nodes, and Each power supply node is connected to a different compensation module 220, and the second output voltage Vout2 is provided to different loads through the different compensation modules 220, so that each load 280 can be compensated by a corresponding compensation module 220.
  • multiple loads 280 can be turned on at the same time, and correspondingly multiple compensation modules 220 can also be turned on at the same time; in other embodiments, multiple loads 280 can be selectively turned on, correspondingly, with the The compensation module 220 connected to the load is correspondingly turned on.
  • the working principle of the memory is: when the load 280 is in the working state, the load 280 will consume part of the first output voltage Vout1 provided by the voltage output module 200 to the power supply node, which will cause the voltage of the power supply node to drop.
  • the compensation module 220 receives the flag signal Reg, generates the second output voltage Vout2 based on the control signal Vctrl, and provides the second output voltage Vout2 to the power supply node, thereby reducing the first output voltage Vout1 consumed by the load 280 Compensation is performed to restore the voltage of the power supply node, thereby ensuring the stability and accuracy of the voltage provided by the voltage generation circuit to the power supply node.
  • the enable signal En when the enable signal En is provided to the load 280, that is, when the enable signal En in Figure 6 is high level, the load 280 starts to work. The moment the load 280 works, due to the load The 280 operation consumes part of the voltage of the power supply node, causing the voltage of the power supply node to drop. While providing the enable signal En to the load 280, it simultaneously provides the enable signal En to the flag signal generation module 240, and the flag signal generation module 240 generates the flag signal Reg. , and provides the flag signal Reg to the compensation module 220.
  • the compensation module 220 receives the flag signal Reg and starts to work, so that the compensation module 220 outputs the second output voltage Vout2 to compensate the power supply node, so that the voltage drop of the power supply node can be reduced. Small, which can improve the accuracy of the voltage generation circuit.
  • the load 280 stops working, that is, the enable signal En changes from high level to low level, the voltage of the power supply node is no longer consumed, and the compensation module 220 no longer receives the flag.
  • Signal Reg the compensation module stops working, and the voltage of the power supply node receiving the first output voltage Vout1 provided by the voltage output module 200 rises.
  • the signal fluctuation diagram shown in FIG. 6 can be the enable signal En received by a certain load 280 within a certain period of time and the compensation module 220 corresponding to the load 280 receives the flag signal Reg, that is, Say, the load 280 is turned on once at a certain interval within a certain period of time; in other embodiments, the signal fluctuation diagram shown in Figure 6 can also be the signal fluctuation diagram of the entire memory, that is to say, the load 280 in the memory Select one of them to be turned on, the loads 280 in the memory receive the enable signal En in turn, and turn on in response to the enable signal En, and when one of the loads 280 in the memory is turned on, the other loads 280 are in a closed state. .
  • the memory may be a storage unit or device based on a semiconductor device or component.
  • the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory Access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, dual Double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, thyristor random access memory TRAM, etc.; or it can be a non-volatile memory, such as phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory Access memory RRAM, etc.
  • Embodiments of the present disclosure provide power through the voltage generation circuit provided in the above embodiments to provide a more stable first output voltage Vout1 to the load 280, and the first output voltage Vout1 is more accurate, thereby improving the response speed and accuracy of the memory.
  • the first output voltage is provided to the power supply node through the voltage output module and then supplies power to the load.
  • the control signal can be output through the voltage stabilizing module, and the power supply voltage and flag signal are received through the compensation module. and the control signal, and is turned on corresponding to the flag signal, and provides the second output voltage to the power supply node in response to the voltage value based on the control signal, so that the voltage of the power supply node is restored to the first output voltage, thereby improving the efficiency of the voltage generation circuit. Accuracy.

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Abstract

本公开提供一种电压生成电路及存储器，涉及半导体电路设计技术领域，电压生成电路包括：电压输出模块，被配置为，接收参考电压，生成第一输出电压并向供电节点提供第一输出电压，且供电节点用于与负载连接以向负载供电；稳压模块，被配置为，接收参考电压，生成并输出控制信号；补偿模块，被配置为，接收电源电压、标志信号和控制信号，并响应于标志信号导通，以及响应于基于控制信号的电压值向供电节点提供第二输出电压，以使供电节点的电压恢复至第一输出电压，标志信号表征负载处于工作期间，可以提高电压生成电路的精确度。

Description

电压生成电路及存储器
本公开基于申请号为202211037861.8、申请日为2022年08月26日、申请名称为“电压生成电路及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种电压生成电路及存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)由于其存储密度高、传输速度快等特点，广泛应用于现代电子系统中。随着半导体技术的发展，DRAM技术越来越先进，存储单元的集成度越来越高；同时，各种不同的应用对DRAM的性能、功耗和可靠性等也都要求越来越高。
由于存储单元的集成度越来越高，存储单元对应的控制电路中需要连接更多的元器件以实现对存储单元的逐一控制，然而随着存储单元的导通，控制电路会产生电压波动，导致提供给存储单元的电压不够精确，因此有必要提供一种电压生成电路以提高电压生成电路的精确度。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种电压生成电路及存储器，至少可以提高电压生成电路的精确度。
根据本公开一些实施例，本公开实施例一方面提供一种电压生成电路，包括：电压输出模块，被配置为，接收参考电压，生成第一输出电压并向供电节点提供所述第一输出电压，且所述供电节点用于与负载连接以向所述负载供电；稳压模块，被配置为，接收所述参考电压，生成并输出控制信号；补偿模块，被配置为，接收电源电压、标志信号和所述控制信号，并响应于所述标志信号导通，以及响应于基于所述控制信号的电压值向所述供电节点提供第二输出电压，以使所述供电节点的电压恢复至所述第一输出电压，所述标志信号表征所述负载处于工作期间。
在一些实施例中，所述补偿模块包括：开关单元，用于接收所述标志信号，并基于所述标志信号输出所述电源电压；调节单元，与所述开关单元连接，用于接收所述电源电压和所述控制信号，以基于所述控制信号的电压值调整所述补偿模块的输出幅值。
在一些实施例中，所述开关单元包括：第一PMOS管，所述第一PMOS管的栅极接收所述标志信号，源极连接工作电源；所述调节单元包括：第一NMOS管，所述第一NMOS管的栅极接收所述控制信号，所述第一NMOS管的漏极连接所述第一PMOS管的漏极，所述第一NMOS管的源极连接所述供电节点以提供所述第二输出电压。
在一些实施例中，所述稳压模块包括：第一运算放大器，所述第一运算放大器的正相输入端接收所述参考电压，所述第一运算放大器的输出端输出所述控制信号；第一电阻，所述第一电阻的一端接地，另一端连接所述第一运算放大器的反相输入端；第二PMOS管，所述第二PMOS管的源极与电源电压连接；第二NMOS管，所述第二NMOS管的栅极与所述第一运算放大器的输出端连接，所述第二NMOS管的漏极与所述第二PMOS管的漏极连接；第二电阻，所述第二电阻的一端与所述第一运算放大器的反相输入端连接，另一端与所述第二NMOS管的源极连接。
在一些实施例中，所述第一NMOS管沟道的宽长比与所述第二NMOS管沟道的宽长比相等。
在一些实施例中，所述电压生成电路还包括：第一电压生成模块，接收所述参考电压并生成用于驱动所述第一运算放大器工作的驱动电压。
在一些实施例中，所述驱动电压的电压值大于所述控制信号对应的电压值与所述第二NMOS管的开启电压的电压值之和。
在一些实施例中，还包括：标志信号生成模块，被配置为，基于使能信号生成所述标志信号，所述使能信号用于控制所述负载工作。
在一些实施例中，所述电压输出模块包括：第二运算放大器，所述第二运算放大器的反相输入端接收所述参考电压；第三电阻，所述第三电阻的一端接地，另一端连接所述第二运算放大器的正相输入端；第三PMOS管，所述第三PMOS管的栅极与所述第二运算放大器的输出端连接，源极连接工作电源，所述第三PMOS管的漏极输出所述第一输出电压；第四电阻，所述第四电阻的一端连接所述第二运算放大器的正相输入端，另一端与所述第三PMOS管的漏极连接。
在一些实施例中，所述第三PMOS管源极连接的工作电源的电压值与所述第二运算放大器的驱动电压的电压值相等。
在一些实施例中，还包括：第二电压生成模块，所述第二电压生成模块用于提供所述参考电压。
在一些实施例中，还包括：电容，所述电容一端与所述电压输出模块的输出端连接，另一端接地。
根据本公开一些实施例，本公开实施例另一方面还提供一种存储器，包括：上述电压生成电路；负载，所述负载与所述供电节点连接，所述负载响应于使能信号工作。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种电压生成电路的结构示意图；
图2为本公开另一实施例提供的一种电压生成电路的结构示意图；
图3为本公开另一实施例提供的一种电压生成电路的具体结构示意图；
图4为本公开另一实施例提供的一种电压输出模块的具体结构示意图；
图5为本公开另一实施例提供的一种标志信号生成模块的结构示意图；
图6为本公开另一实施例提供的一种信号波动图。
附图标记：
100、带隙基准电压生成模块；110、参考电压生成模块；120、稳压电路模块；130、负载模块；140、运算放大器；150、第五电阻；160、PMOS管；
200、电压输出模块；201、第二运算放大器；202、第三电阻；203、第三PMOS管；204、第四电阻；210、稳压模块；211、第一运算放大器；212、第一电阻；213、第二PMOS管；214、第二NMOS管；220、补偿模块；221、开关单元；222、调节单元；223、第一PMOS管；224、第一NMOS管；230、第一电压生成模块；240、标志信号生成模块；250、第二电压生成模块；251、第一电压生成单元；252、第二电压生成单元；260、电容；270、电阻；280、负载。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，参考图1，图1中提供的电路为现有技术中提供的一种电压生成电路，其中，现有技术中提供的电压生成电路包括：带隙基准电压生成模块100及参考电压生成模块110以提供参考电压；多个稳压电路模块120，及与每一稳压电路模块120一一对应连接的负载模块130，其中，多个稳压电路模块120包括：运算放大器140，运算放大器140的反相输入端接收参考电压；第五电阻150，第五电阻150的一端接地，另一端连接运算放大器140的正相输入端；PMOS管160，PMOS管160的栅极与运算放大器140的输出端连接，源极连接工作电源；第六电阻170，第六电阻170的一端连接运算放大器140的正相输入端，另一端与PMOS管160的漏极连接，通过稳压电路模块120可以向负载模块130提供输出电压，进而控制负载模块130的导通。
总的来说，通过带隙基准电压生成模块100生成带隙基准电压并向参考电压生成模块110输出带隙基准电压，参考电压生成模块110接收带隙基准电压生成并输出参考电压，稳压电路模块120接收参考电压并向负载模块130输出目标输出电压。
然而，当负载模块130导通的时候，负载模块130消耗一部分的输出电压，使得负载模块130与稳压电路模块120的连接节点提供的输出电压减小，导致提供给负载模块130的电压低于预设值，进而导致负载模块130的部分器件可能无法正常工作。
本公开实施提供一种电压生成电路及存储器，通过电压输出模块接收参考电压向供电节点提供第一输出电压，并通过供电节点向负载供电，通过稳压模块向补偿模块输出控制信号，通过补偿模块向接收电源电压、标志信号及控制信号向供电节点提供第二输出电压以使供电节点的电压恢复至第一输出电压，从而可以使得负载工作时，供电节点向负载提供的电压稳定为第一输出电压，从而可以提高电压生成电路的精确度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图2至图6，其中图2为本公开实施例提供的一种电路结构示意图，图3为本公开实施例提供的一种稳压模块、补偿模块及第二电压生成模块的具体结构示意图，图4为本公开实施例提供的电压输出模块的具体结构示意图，图5为本公开实施例提供的标志信号生成模块的结构示意图，图6为本公开实施例提供的一种信号波动图，电压生成电路，包括：
电压输出模块200，被配置为，接收参考电压Vref，生成第一输出电压Vout1并向供电节点提供第一输出电压Vout1，且供电节点用于与负载连接以向负载供电。
稳压模块210，被配置为，接收参考电压Vref，生成并输出控制信号Vctrl。
补偿模块220，被配置为，接收电源电压VPwr、标志信号Reg和控制信号Vctrl，并响应于标志信号Reg导通，以及响应于基于控制信号Vctrl的电压值向供电节点提供第二输出电压Vout2，以使供电节点的电压恢复至第一输出电压Vout1，标志信号Reg表征负载处于工作期间。
具体的，当负载处于工作期间，接收来自电压输出模块200的第一输出电压Vout1并导通，由于负载导通导致供电节点的第一输出电压Vout1被消耗，导致供电节点的 第一输出电压Vout1的电压值下降，同时，稳压模块210工作并接收参考电压Vref向补偿模块220提供控制信号Vctrl，补偿模块220接收电源电压VPwr、标志信号Reg和控制信号Vctrl，并响应于标志信号Reg导通，且根据控制信号Vctrl的电压值生成并输出第二输出电压Vout2，供电节点接收来自补偿模块的第二输出电压Vout2从而补偿被负载消耗的第一输出电压Vout1，使得供电节点向负载提供的电压稳定在第一输出电压Vout1，从而使负载接收的电压信号不会因为自身的开启导致的波动，且可以使得电压生成电路向负载提供的电压稳定在第一输出电压Vout1，从而可以提高电压生成电路的精确性。
需要说明的是，上述实施例中的补偿模块220响应于标志信号导通，标志信号Reg可以基于使能信号En生成，在另一些实施例中，补偿模块220还可以设置为直接基于使能信号En导通。
对于补偿模块220，在一些实施例中，补偿模块220可以包括：开关单元221，用于接收标志信号Reg，并基于标志信号Reg输出电源电压VPwr；调节单元222，与开关单元221连接，用于接收电源电压VPwr和控制信号Vctrl，以基于控制信号Vctrl的电压值调整补偿模块220的输出幅值。通过开关单元221可以控制补偿模块220是否工作，也就是说，当负载处于工作的时候，开关单元221才接收标志信号Reg，并向调节单元222输出电源电压VPwr，调节单元222可以始终处于待开启状态，当接收到调节单元222提供的电源电压VPwr时导通，并根据控制信号Vctrl的电压值调整补偿模块220的输出幅值，从而可以向供电节点提供第二输出电压Vout2，从而使得供电节点的电压值恢复至第一输出电压Vout1，进而可以提高电压生成电路提供的电压值的精确性。
在一些实施例中，开关单元221可以包括：第一PMOS管223，第一PMOS管223的栅极接收标志信号Reg，源极连接工作电源；调节单元222包括：第一NMOS管224，第一NMOS管224的栅极接收控制信号Vctrl，第一NMOS管224的漏极连接第一PMOS管223的漏极，第一NMOS管224的源极连接供电节点以提供第二输出电压Vout2。
可以理解的是，工作电源可以用于提供电源电压VPwr，标志信号Reg可以包括两种状态，其中一者为高电平状态，另一者为低电平状态，当第一PMOS管223的栅极接收到的标志信号Reg为低电平状态时，第一PMOS管223导通，第一PMOS管223向第一NMOS管224的漏极提供电源电压VPwr，当第一NMOS管224的漏极接收到电源电压VPwr，栅极接收到控制信号Vctrl，第一NMOS管224导通，并通过源极向供电节点提供第二输出电压Vout2，从而使得供电节点的电压值恢复至第一输出电压Vout1，进而可以提高电压生成电路提供的电压值的精确性。
在一些实施例中，电压生成电路可以包括多个补偿模块220及多个供电节点，且每一补偿模块220与一供电节点对应连接，通过多个供电节点向不同的负载280提供第二输出电压Vout2，从而使得每一负载280都有与之对应的补偿模块220，且通过多个补偿模块220并联可以减小电压生成电路的版图面积，且电压生成电路具有更快的响应速度。
在一些实施例中，稳压模块210可以包括：第一运算放大器211，第一运算放大器211的正相输入端接收参考电压Vref，第一运算放大器211的输出端输出控制信号Vctrl；第一电阻212，第一电阻212的一端接地，另一端连接第一运算放大器211的反相输入端；第二PMOS管213，第二PMOS管213的源极与电源电压VPwr连接；第二NMOS管214，第二NMOS管214的栅极与第一运算放大器211的输出端连接，第二NMOS管214的漏极与第二PMOS管213的漏极连接；第二电阻215，第二电阻215的一端与第一运算放大器211的反相输入端连接，另一端与第二NMOS管214的 源极连接。
具体的，稳压模块210的稳压原理为：当输出电压降低时，通过第一电阻212及第二电阻215的分压作用，提供给第一运算放大器211反相输入端的电压减小，然而第一运算放大器211的正相输入端连接的参考电压Vref的电压值是稳定的，因此，第一运算放大器211的输出端输出电压相应增加，第二NMOS管214的栅极电压增加，稳压模块210的输出电压相应增加，抑制了输出电压的降低，从而保持稳定的输出。
本公开实施例中，第二PMOS管213的源极与电源电压VPwr连接，栅极可以接地，因此，第二PMOS管213始终导通，从通过第二PMOS管213的漏极向第二NMOS管的漏极提供电源电压VPwr，第二NMOS管214的栅极与第一运算放大器211的输出端连接，当向第一运算放大器211提供参考电压Vref时，第二NMOS管214导通，整个稳压模块210开始工作。
可以理解的是，稳压模块210的输出电压可以是第三输出电压Vout3，第三输出电压Vout3的电压值可以是Vout3＝Vref*(R1+R2)/R1，其中Vref表示参考电压Vref的电压值，R1表示第一电阻212的阻值，R2表示第二电阻215的阻值，*表示数学中的相乘运算，/表示数学中的除以运算。
稳压模块210提供的控制信号Vctrl与第二NMOS管214的栅极相连，因此，控制信号Vctrl的电压值Vctrl＝Vout3+Vth，其中Vout3表示稳压模块210可以提供的第三输出电压的电压值，Vth表示第二NMOS管214的阈值电压。
在一些实施例中，第一NMOS管224沟道的宽长比与第二NMOS管214沟道的宽长比相等，可以理解的是，第一NMOS管224沟道的宽长比与第二NMOS管214沟道的宽长比相等也就是说第一NMOS管224的阈值电压与第二NMOS管214的阈值电压相等，也就是说，当第一NMOS管224的栅极接收稳压模块210提供的控制信号Vctrl时，通过第一NMOS管224的源极输出的电压值为Vctrl减去第一NMOS管224的阈值电压，也就是等于第三输出电压Vout3的电压值，也就说第二输出电压Vout2的电压值与第三输出电压Vout3的电压值相等，然而第三输出电压Vout3的电压值与第一输出电压Vout1的电压值相等，也就是说通过控制第一NMOS管224沟道的宽长比与第二NMOS管214沟道的宽长比相等可以控制第二输出电压Vout2的电压值与第一输出电压Vout1的电压值相等，从而可以提高电压生成电路的精确性，使得电压生成电路提供给供电节点的电压值稳定在第一输出电压Vout1。
需要说明的是，上述第一NMOS管224沟道的宽长比与第二NMOS管214沟道的宽长比相等，指的是理想相等，实际上来说第一NMOS管224沟道的宽长比与第二NMOS管214沟道的宽长比可能存在一定的偏差，然而该偏压需要在预设偏差范围内，也就是说补偿模块220的实际输出电压与理想的第二输出电压Vout2之间的电压差在预设范围内；换句话说，补偿模块220的实际输出电压可以略大于或者略小于理想的第二输出电压Vout2，当补偿模块220的实际输出电压高于理想的第二输出电压Vout2较多时，补偿模块220可能产生较大的噪声，当补偿模块220的实际输出电压低于理想的第二输出电压Vout2较多时，稳定供电节点的电压恢复至第一输出电压Vout1的能力较差，改善效果不佳。
在一些实施例中，电压生成电路还包括：第一电压生成模块230，接收参考电压Vref并生成用于驱动第一运算放大器211工作的驱动电压Vhv。驱动电压Vhv的电压值大于控制信号Vctrl对应的电压值与第一运算放大器211内部串接于驱动电压所在的电源端和第一运算放大器211输出端之间的NMOS管的阈值电压之和。通过向第一运算放大器211提供上述驱动电压以作为电源电压，可以保证第一运算放大器211能够有效所需的控制信号Vctrl。可以理解的是，当第一运算放大器的输出端与电源端之间串接有多个MOS管时，驱动电压Vhv的电压应当大于控制信号Vctrl对应的电 压值和该多个MOS管对应的阈值电压的总和，即，使得第一运算放大器211的输出电压的最大值大于控制信号Vctrl对应的电压值。
在一些实施例中，电压生成电路还可以包括：标志信号生成模块240，被配置为，基于使能信号En生成标志信号Reg，使能信号En用于控制负载280工作。本公开实施例中，标志信号生成模块240可以将使能信号En转换为对应的标志信号Reg，例如，向标志信号生成模块240提供第一使能信号En1、第二使能信号En2及第三使能信号En3，通过标志信号生成模块240可以生成对应的第一标志信号Reg1、第二标志信号Reg2及第三标志信号Reg3，且不同的使能信号En可以提供给不同的负载，使能信号En对应的标志信号Reg可以提供给与对应负载280连接的补偿模块220，从而当第一使能信号En1对应负载280导通时，接收第一标志信号Reg1的补偿模块220开始工作，以向负载280提供第二输出电压Vout2，从而可以补偿与负载280对应的供电节点的电压。
在一些实施例中，参考图4，电压输出模块200可以包括：第二运算放大器201，第二运算放大器201的反相输入端接收参考电压Vref；第三电阻202，第三电阻202的一端接地，另一端连接第二运算放大器201的正相输入端；第三PMOS管203，第三PMOS管203的栅极与第二运算放大器201的输出端连接，源极连接工作电源，第三PMOS管203的漏极输出第一输出电压Vout1；第四电阻204，第四电阻204的一端连接第二运算放大器201的正相输入端，另一端与第三PMOS管203的漏极连接。
可以理解的是，电压输出模块200的工作原理为：当电压输出模块200的输出电压降低时，通过第三电阻202及第四电阻204的分压作用，提供给第二运算放大器201正相输入端的电压减小，然而第二运算放大器201的反相输入端接入的参考电压Vref的电压值是稳定的，因此，第二运算放大器201的输出端的电压相应减小，第三PMOS管203的栅极电压减小，电压输出模块200的输出电压相应增加，抑制了输出电压的降低，从而保持稳定的输出。
在一些实施例中，第三PMOS管203源极连接的工作电源的电压值与第二运算放大器201的驱动电压的电压值相等，换句话说，第三PMOS管203源极与第二运算放大器201可以与同一工作电源连接，降低设置不同电源造成的复杂度。
在一些实施例中，第一运算放大器211的规格还可以与第二运算放大器201的规格相同，从而可以减少第三输出电压Vout3和第一输出电压Vout1之间的差异，从而可以减少基于控制信号Vctrl生成的第二输出电压Vout2与第一输出电压Vout1之间的差异，从而使得供电节点的电压恢复至第一输出电压Vout1。
在一些实施例中，电压生成电路还可以包括：第二电压生成模块250，第二电压生成模块250用于提供参考电压Vref，通过第二电压生成模块250可以向电压输出模块200、稳压模块210及第一电压生成模块230提供参考电压Vref。
在一些实施例中，第二电压生成模块250可以包括：第一电压生成单元251及第二电压生成单元252，通过第一电压生成单元251可以生成带隙基准电压Vbgr，第二电压生成单元252可以接收带隙基准电压Vbgr生成参考电压Vref，在存储器中，带隙基准电压Vbgr为稳定的电压信号，电压值的大小不受温度的影响，因此，通过第一电压生成单元251提供的带隙基准电压Vbgr，不受温度的影响，从而生成稳定的参考电压Vref。
在一些实施例中，电压生成电路还可以包括：电容260，电容一端与电压输出模块200的输出端连接，另一端接地。通过设置电容260可以起到滤波的作用，从而可以减少电压生成电路提供的电压的可靠性。
在一些实施例中，电压生成电路还可以包括：电阻270，电阻270的一端与电压输出模块200的输出端连接，另一端与供电节点连接，通过设置电阻270可以提高电 压生成电路的安全性，降低电源网络中不同电压节点之间的影响。
参考图3及图6，其中图6为电压生成电路的信号波动图，具体的，始终提供依据具有高电平的电源电压VPwr以使稳压模块210及标志信号生成模块240开始工作，并向负载280及标志信号生成模块240提供使能信号En，当使能信号En为高电平，负载280导通，使得与负载280连接的供电节点的电压产生波动，且当使能信号En为高电平，同步标志信号生成模块240向补偿模块220提供标志信号Reg，以使补偿模块220工作，并向供电节点提供第二输出电压Vout2，补偿供电节点的电压，可以参考供电节点的电压波动图，当使能信号为低电平时，供电节点接收来自电压输出模块200的第一输出电压Vout1，电压上升，使能信号En变为高电平，负载280导通，导致供电节点的电压被消耗，开始下降，通过补偿模块220工作对供电节点进行补偿，减缓供电节点的电压下降，当使能信号En重新变为低电平时，负载关闭，标志信号
Reg变低，补偿模块220关闭，供电节点接收自电压输出模块200的第一输出电压Vout1，电压上升。
本公开实施例相较于图1对应的现有技术而言，具有更小的版图面积、更小的电源电压VPwr到第一输出电压Vout1的电源容限幅度、且消耗更少的电源功耗、更快的响应速度及更高的精确度。
本公开实施例通过电压输出模块200向供电节点提供第一输出电压Vout1，当负载工作导致供电节点电压下降，通过稳压模块210工作并接收参考电压Vref向补偿模块220提供控制信号Vctrl，通过补偿模块220接收电源电压VPwr、标志信号Reg和控制信号Vctrl，并响应于标志信号Reg导通，且根据控制信号Vctrl的电压值生成并向供电节点输出第二输出电压Vout2，从而补偿供电节点上被负载消耗的第一输出电压Vout1，使得电压生成电路向负载提供的电压稳定在第一输出电压Vout1，从而可以提高电压生成电路的精确性。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
需要说明的是，上述实施例所提供的电源提供电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的电源提供电路实施例。
本公开另一实施例还提供一种存储器，可以包括上述电压生成电路，以下将结合附图对本公开实施例提供的存储器进行说明，需要说明的是，与前述实施例相同或者相应的部分可以参考前述实施例的响应说明，以下将不做赘述。
参考图2至图6，本公开实施例提供的存储器包括：如上述的电压生成电路；负载280，负载280与供电节点连接，负载280响应于使能信号En工作。
本公开实施例通过电压输出模块200向供电节点提供第一输出电压Vout1，当负载280工作导致供电节点电压下降，通过稳压模块210工作并接收参考电压Vref向补偿模块220提供控制信号Vctrl，通过补偿模块220接收电源电压VPwr、标志信号Reg和控制信号Vctrl，并响应于标志信号Reg导通，且根据控制信号Vctrl的电压值生成并向供电节点输出第二输出电压Vout2，从而补偿供电节点上被负载280消耗的第一输出电压Vout1，使得电压生成电路向负载280提供的电压稳定在第一输出电压Vout1，从而可以提高电压生成电路的精确性。
在一些实施例中，负载280的数量为多个，且不同的负载280响应于不同的使能信号En工作；电压生成电路具有多个供电节点，且每一供电节点与一负载280连接；电压生成电路包括多个补偿模块220，且每一补偿模块220响应于相应的标志信号Reg 向相应的供电节点提供第二输出电压Vout2。以负载280的数量为3个为例，3个负载280可以分为第一负载、第二负载及第三负载，第一负载、第二负载及第三负载连接在不同的供电节点上，且每一供电节点与不同的补偿模块220对应连接，通过不同的补偿模块220向不同的负载分别提供第二输出电压Vout2，从而可以使每一负载280都有对应的补偿模块220进行补偿。
在一些实施例中，多个负载280可以同时导通，相应的多个补偿模块220也同时导通；在另一些实施例中，多个负载280可以择一导通，相应的，与导通负载连接的补偿模块220对应导通。
总的来说，存储器的工作原理为：当负载280处于工作状态时，负载280会消耗部分电压输出模块200提供给供电节点的第一输出电压Vout1，从而会导致供电节点的电压下降，当负载280处于工作状态时，同时补偿模块220接收到标志信号Reg，并基于控制信号Vctrl生成第二输出电压Vout2，并向供电节点提供第二输出电压Vout2，从而对负载280消耗的第一输出电压Vout1进行补偿，使得供电节点的电压恢复，从而保证电压生成电路向供电节点提供电压的稳定性及精确性。
参考图6所示的信号波动图，当向负载280提供使能信号En时，也就是图6中的使能信号En为高电平时，负载280开始工作，负载280工作的一瞬间，由于负载280工作消耗供电节点的部分电压，导致供电节点的电压下降，向负载280提供使能信号En的同时，同步向标志信号生成模块240提供使能信号En，通过标志信号生成模块240生成标志信号Reg，并将标志信号Reg提供给补偿模块220，补偿模块220接收到标志信号Reg开始工作，从而使得补偿模块220输出第二输出电压Vout2，对供电节点进行补偿，从而可以供电节点的电压下降幅度减小，可以提高电压生成电路的精确性，当负载280停止工作，也就是使能信号En从高电平变为低电平，供电节点的电压不再被消耗，补偿模块220不再接收到标志信号Reg，补偿模块停止工作，供电节点的电压接收电压输出模块200提供的第一输出电压Vout1电压上升。
在一些实施例中，图6所示的信号波动图可以是某一负载280在一定时间内接收到的使能信号En及与该负载280对应连接的补偿模块220接收到标志信号Reg，也就是说，该负载280在一定时间内间隔一定的时间开启一次；在另一些实施例中，图6所示的信号波动图还可以是存储器整体的信号波动图，也就是说，存储器内的负载280择一导通，存储器内的负载280依次接收到使能信号En，并响应于使能信号En导通，且存储器内的负载280在其中一者导通时，其余的负载280均处于关闭状态。
需要说明的是，存储器可以是基于半导体装置或组件的存储单元或装置。例如，存储器装置可以是易失性存储器，例如动态随机存取存储器DRAM、同步动态随机存取存储器SDRAM、双倍数据速率同步动态随机存取存储器DDR SDRAM、低功率双倍数据速率同步动态随机存取存储器LPDDR SDRAM、图形双倍数据速率同步动态随机存取存储器GDDR SDRAM、双倍数据速率类型双同步动态随机存取存储器DDR2 SDRAM、双倍数据速率类型三同步动态随机存取存储器DDR3 SDRAM、双倍数据速率第四代同步动态随机存取存储器DDR4 SDRAM、晶闸管随机存取存储器TRAM等；或者可以是非易失性存储器，例如相变随机存取存储器PRAM、磁性随机存取存储器MRAM、电阻式随机存取存储器RRAM等。
本公开实施例通过上述实施例提供的电压生成电路进行供电，以向负载280提供更稳定的第一输出电压Vout1，且第一输出电压Vout1更精确，从而可以提高存储器的响应速度及精确性。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作 各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。
工业实用性
本公开实施例所提供的电压生成电路及存储器中，通过电压输出模块向供电节点提供第一输出电压，进而向负载供电，通过稳压模块可以输出控制信号，通过补偿模块接收电源电压、标志信号和控制信号，并相应于标志信号导通，以及响应于基于控制信号的电压值向供电节点提供第二输出电压，以使供电节点的电压恢复至第一输出电压，从而可以提高电压生成电路的精确度。

Claims (14)

  1. 一种电压生成电路，包括：
    电压输出模块，被配置为，接收参考电压，生成第一输出电压并向供电节点提供所述第一输出电压，且所述供电节点用于与负载连接以向所述负载供电；
    稳压模块，被配置为，接收所述参考电压，生成并输出控制信号；
    补偿模块，被配置为，接收电源电压、标志信号和所述控制信号，并响应于所述标志信号导通，以及响应于基于所述控制信号的电压值向所述供电节点提供第二输出电压，以使所述供电节点的电压恢复至所述第一输出电压，所述标志信号表征所述负载处于工作期间。
  2. 根据权利要求1所述的电压生成电路，其中，所述补偿模块包括：
    开关单元，用于接收所述标志信号，并基于所述标志信号输出所述电源电压；
    调节单元，与所述开关单元连接，用于接收所述电源电压和所述控制信号，以基于所述控制信号的电压值调整所述补偿模块的输出幅值。
  3. 根据权利要求2所述的电压生成电路，其中，所述开关单元包括：第一PMOS管，所述第一PMOS管的栅极接收所述标志信号，源极连接工作电源；
    所述调节单元包括：第一NMOS管，所述第一NMOS管的栅极接收所述控制信号，所述第一NMOS管的漏极连接所述第一PMOS管的漏极，所述第一NMOS管的源极连接所述供电节点以提供所述第二输出电压。
  4. 根据权利要求3所述的电压生成电路，其中，所述稳压模块包括：
    第一运算放大器，所述第一运算放大器的正相输入端接收所述参考电压，所述第一运算放大器的输出端输出所述控制信号；
    第一电阻，所述第一电阻的一端接地，另一端连接所述第一运算放大器的反相输入端；
    第二PMOS管，所述第二PMOS管的源极与电源电压连接；
    第二NMOS管，所述第二NMOS管的栅极与所述第一运算放大器的输出端连接，所述第二NMOS管的漏极与所述第二PMOS管的漏极连接；
    第二电阻，所述第二电阻的一端与所述第一运算放大器的反相输入端连接，另一端与所述第二NMOS管的源极连接。
  5. 根据权利要求4所述的电压生成电路，其中，所述第一NMOS管沟道的宽长比与所述第二NMOS管沟道的宽长比相等。
  6. 根据权利要求4所述的电压生成电路，还包括：第一电压生成模块，接收所述参考电压并生成用于驱动所述第一运算放大器工作的驱动电压。
  7. 根据权利要求6所述的电压生成电路，其中，所述驱动电压的电压值大于所述控制信号对应的电压值与所述第二NMOS管的开启电压的电压值之和。
  8. 根据权利要求1所述的电压生成电路，还包括：标志信号生成模块，被配置为，基于使能信号生成所述标志信号，所述使能信号用于控制所述负载工作。
  9. 根据权利要求1所述的电压生成电路，其中，所述电压输出模块包括：
    第二运算放大器，所述第二运算放大器的反相输入端接收所述参考电压；
    第三电阻，所述第三电阻的一端接地，另一端连接所述第二运算放大器的正相输入端；
    第三PMOS管，所述第三PMOS管的栅极与所述第二运算放大器的输出端连接，源极连接工作电源，所述第三PMOS管的漏极输出所述第一输出电压；
    第四电阻，所述第四电阻的一端连接所述第二运算放大器的正相输入端，另一端与所述第三PMOS管的漏极连接。
  10. 根据权利要求9所述的电压生成电路，其中，所述第三PMOS管源极连接的工作电源的电压值与所述第二运算放大器的驱动电压的电压值相等。
  11. 根据权利要求1所述的电压生成电路，还包括：第二电压生成模块，所述第二电压生成模块用于提供所述参考电压。
  12. 根据权利要求1所述的电压生成电路，还包括：电容，所述电容一端与所述电压输出模块的输出端连接，另一端接地。
  13. 一种存储器，包括：
    如权利要求1-12任一项所述的电压生成电路；
    负载，所述负载与所述供电节点连接，所述负载响应于使能信号工作。
  14. 根据权利要求13所述的存储器，其中，所述负载的数量为多个，且不同的所述负载响应于不同的所述使能信号工作；
    所述电压生成电路具有多个所述供电节点，且每一所述供电节点与一所述负载连接；
    所述电压生成电路包括多个所述补偿模块，且每一所述补偿模块响应于相应的所述标志信号向相应的所述供电节点提供所述第二输出电压。
PCT/CN2022/132407 2022-08-26 2022-11-17 电压生成电路及存储器 Ceased WO2024040758A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN102385910A (zh) * 2011-09-01 2012-03-21 上海宏力半导体制造有限公司 位反转电路
CN109270978A (zh) * 2017-07-18 2019-01-25 中航（重庆）微电子有限公司 低压差线性稳压电路、电压调整率补偿单元及方法
WO2022105890A1 (zh) * 2020-11-20 2022-05-27 唯捷创芯(天津)电子技术股份有限公司 一种输出可调的电压偏置电路、芯片及通信终端

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102385910A (zh) * 2011-09-01 2012-03-21 上海宏力半导体制造有限公司 位反转电路
CN109270978A (zh) * 2017-07-18 2019-01-25 中航（重庆）微电子有限公司 低压差线性稳压电路、电压调整率补偿单元及方法
WO2022105890A1 (zh) * 2020-11-20 2022-05-27 唯捷创芯(天津)电子技术股份有限公司 一种输出可调的电压偏置电路、芯片及通信终端

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