WO2024040523A1 - 液晶显示面板的驱动方法和液晶显示面板 - Google Patents

液晶显示面板的驱动方法和液晶显示面板 Download PDF

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Publication number
WO2024040523A1
WO2024040523A1 PCT/CN2022/114839 CN2022114839W WO2024040523A1 WO 2024040523 A1 WO2024040523 A1 WO 2024040523A1 CN 2022114839 W CN2022114839 W CN 2022114839W WO 2024040523 A1 WO2024040523 A1 WO 2024040523A1
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sub
pixel
period
switching element
pixels
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PCT/CN2022/114839
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English (en)
French (fr)
Inventor
翁祖伟
赖意强
胡波
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京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002847.6A priority Critical patent/CN117940988A/zh
Priority to PCT/CN2022/114839 priority patent/WO2024040523A1/zh
Publication of WO2024040523A1 publication Critical patent/WO2024040523A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • Embodiments of the present disclosure relate to a driving method of a liquid crystal display panel and a liquid crystal display panel.
  • LCD Liquid Crystal Display
  • At least one embodiment of the present disclosure provides a driving method for a liquid crystal display panel, wherein the liquid crystal display panel includes a pixel array, the pixel array includes a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels, and the plurality of sub-pixels
  • the pixels are arranged in multiple rows and columns.
  • Each gate line provides a gate signal for at least one row of sub-pixels.
  • Each data line provides a data signal for at least one column of sub-pixels.
  • Each sub-pixel is connected to a corresponding gate line and a corresponding data line.
  • the driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in multiple rows of sub-pixels, wherein the first gate signal includes an on period and an off period for controlling The first row of sub-pixels are respectively turned on and off; during the period when the first gate signal is in the on-state, multiple data lines are respectively written to the multiple sub-pixels of the first row of sub-pixels through the plurality of data lines.
  • a first data signal wherein the plurality of first data signals include a positive polarity data signal and a negative polarity data signal, and during the turn-on period of the first gate signal, the first write of the negative polarity data signal
  • the input time length is less than the second writing time length of the positive polarity data signal.
  • the delay time of the negative polarity data signal relative to the starting time point of the turn-on period corresponding to the first gate signal is a first time length
  • the delay time of the data signal relative to the starting time point of the turn-on period corresponding to the first gate signal is a second time length
  • the first time length is greater than the second time length, so that in the The first gate signal is in the turn-on period, and the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal.
  • the negative polarity data signal is relative to the starting time point of the turn-on period corresponding to the first gate signal and the positive polarity data signal is relative to the first gate signal.
  • the starting time points of the turn-on period corresponding to a gate signal are the same or different.
  • the first gate signal further includes a transition period between adjacent on-periods and off-periods, and the first time length is longer than the second time period.
  • the length is longer than a preset time length, and the preset time length is the writing time length of the negative polarity data signal and the writing time of the positive polarity data signal during the transition period of the first gate signal. The difference between the lengths.
  • each data line provides a data signal for two adjacent columns of sub-pixels.
  • each data line A positive polarity data signal and a negative polarity data signal are respectively provided to the first sub-pixel and the second sub-pixel in the same row and two adjacent columns.
  • the turn-on period of the first gate signal includes a first sub-turn-on period and a second sub-turn period.
  • the positive polarity data signal is applied to the first sub-pixel during the first sub-turn-on period
  • the negative polarity data signal is applied to the second sub-pixel during the second sub-turn-on period, so The time length of the first sub-on period is greater than the time length of the second sub-on period.
  • each sub-pixel further includes a pixel electrode, and each data line provides the positive polarity data signal to the first sub-pixel through a first multiplexing switching element.
  • the pixel electrode of the pixel provides the negative polarity data signal to the pixel electrode of the second sub-pixel through the second multiplexing switching element.
  • the first multiplexing switching element is connected to a first control line to receive a first control signal provided by the first control line.
  • the switch element is configured to turn on and off in response to the control of the first control signal
  • the second multiplexing switch element is connected to a second control line to receive a second control signal provided by the second control line.
  • the second multiplexing switch element is configured to be turned on and off in response to the control of the second control signal.
  • the first sub-on period and the second sub-on period are respectively related to the on-time period of the first multiplexing switching element and the second multiplexing switch element.
  • the on-time periods of the switching elements are the same.
  • the first multiplexing switching element and the second multiplexing switching element are arranged around the liquid crystal display panel, and the first sub-pixel is located in a A column of sub-pixels shares the first multiplexing switching element, and a column of sub-pixels in which the second sub-pixel is located shares the second multiplexing switching element.
  • the first multiplexing switching element is arranged in the first sub-pixel
  • the second multiplexing switching element is arranged in the second sub-pixel.
  • each sub-pixel further includes a pixel switching element, and the pixel switching element is connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line,
  • the pixel switching element in the first sub-pixel and the first multiplexing switching element are connected in series between the data line and the pixel electrode, and the pixel switching element in the second sub-pixel is connected to the first multiplexing switching element in series.
  • Two multiplexing switching elements are connected in series between the data line and the pixel electrode.
  • At least one embodiment of the present disclosure provides a liquid crystal display panel, including a pixel array.
  • the pixel array includes a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels.
  • the plurality of sub-pixels are arranged in multiple rows and columns, each of which The gate line provides gate signals for one row of sub-pixels, and each data line provides data signals for two adjacent columns of sub-pixels.
  • Each sub-pixel is connected to the corresponding gate line and the corresponding data line.
  • the first row of sub-pixels in multiple rows The first gate line corresponding to the pixel is configured to provide a first gate signal to the first row of sub-pixels, wherein the first gate signal includes an on period and an off period and is used to control the first row of sub-pixels. Turn on and off respectively, and each data line is configured to provide positive polarity data signals to the first sub-pixels in two adjacent columns and to provide positive polarity data signals to the first sub-pixels in two adjacent columns during the period when the first gate signal is on.
  • the second sub-pixel provides a negative polarity data signal, and during the turn-on period of the first gate signal, each data line is configured such that the first writing time length of the negative polarity data signal is less than the positive polarity data signal.
  • the second writing time length of the sexual data signal, the turn-on period of the first gate signal includes a first sub-turn-on period and a second sub-turn-on period, when the first gate signal is in the turn-on period, the Each data line is configured such that the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal, including: the positive polarity data signal is in the first sub-on period.
  • the negative polarity data signal is applied to the second sub-pixel during the second sub-on period, the time length of the first sub-on period is greater than the second sub-on period length of time.
  • each sub-pixel further includes a pixel electrode, and each data line is electrically connected to the pixel electrode of the first sub-pixel through a first multiplexing switching element,
  • the second multiplexing switch element is electrically connected to the pixel electrode of the second sub-pixel.
  • the first multiplexing switch element is connected to the first control line to receive the first control signal provided by the first control line.
  • the switching switch element is configured to be turned on and off in response to the control of the first control signal
  • the second multiplexing switching element is connected to the second control line to receive the second control signal provided by the second control line
  • the The second multiplexing switching element is configured to be turned on and off in response to control by the second control signal.
  • the first multiplexing switching element and the second multiplexing switching element are disposed around the liquid crystal display panel, and the first sub-pixel The sub-pixels in the column share the first multiplexing switch element, and the sub-pixels in the column of the second sub-pixel share the second multiplexing switch element.
  • the first multiplexing switching element is arranged in the first sub-pixel, and the second multiplexing switching element is arranged in the second sub-pixel.
  • each sub-pixel further includes a pixel switching element, and the pixel switching element is connected to a corresponding gate line to receive a gate signal provided by the corresponding gate line, so
  • the pixel switching element in the first sub-pixel and the first multiplexing switching element are connected in series between the data line and the pixel electrode, and the pixel switching element in the second sub-pixel is connected to the second A multiplexing switching element is connected in series between the data line and the pixel electrode.
  • Figure 1A shows an equivalent circuit of a sub-pixel in a liquid crystal display panel
  • Figure 1B shows the equivalent circuit of a sub-pixel in another liquid crystal display panel
  • Figure 1C shows a voltage waveform diagram driven by a common electrode DC voltage
  • Figure 1D shows a partial timing diagram of a gate signal and a data signal
  • Figure 1E shows a partial timing diagram of another gate signal and data signal
  • Figure 2A shows a flow chart of a driving method provided by at least one embodiment of the present disclosure
  • FIG. 2B shows a schematic diagram of a pixel driving architecture of a liquid crystal display panel provided by at least one embodiment of the present disclosure
  • FIG. 2C and 2D illustrate a schematic diagram of a polarity reversal driving method provided by at least one embodiment of the present disclosure
  • FIG. 2E shows a timing signal diagram of a gate signal and a data signal provided by at least one embodiment of the present disclosure
  • FIG. 3A shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure
  • 3B and 3C illustrate a timing signal diagram provided by at least one embodiment of the present disclosure
  • FIG. 4 shows a partial schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure
  • Figure 5A shows a timing signal diagram of the Nth image frame provided by at least one embodiment of the present disclosure
  • Figure 5B shows a timing signal diagram of the N+1th image frame provided by at least one embodiment of the present disclosure
  • Figure 6 shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure.
  • 8A to 8D illustrate other pixel driving architectures of liquid crystal display panels applied to the driving method provided by at least one embodiment of the present disclosure.
  • liquid crystal is a non-conductive dielectric layer, for example, it is sandwiched between the pixel electrode provided on the array substrate and the common electrode provided on the color filter substrate, or for example, it is covered and provided on the array substrate at the same time.
  • the pixel electrode and the common electrode are insulated from each other.
  • the liquid crystal display panel includes a pixel array, which includes multiple rows and columns of pixels for displaying a single pixel in an image. Each pixel includes multiple sub-pixels for controlling the display of certain primary colors (such as red, green, and blue). .
  • FIG. 1A shows an equivalent circuit of a sub-pixel in a liquid crystal display panel.
  • FIG. 1B shows an equivalent circuit of a sub-pixel in another liquid crystal display panel.
  • the sub-pixel includes a pixel switching element T0, a liquid crystal capacitor C LC and a storage capacitor C ST .
  • the pixel switching element T0 may be, for example, a thin film transistor, the first electrode (such as the drain electrode) of which is electrically connected to the pixel electrode, the second electrode (such as the source electrode) is electrically connected to the data line corresponding to the pixel column in which the sub-pixel is located, and the control electrode ( For example, the gate electrode) is electrically connected to the gate line corresponding to the pixel row where the sub-pixel is located.
  • Liquid crystal molecules are located between the pixel electrode and the common electrode, forming a liquid crystal capacitor C LC for storing the data signal written through the pixel switching element T0.
  • the storage capacitor C ST is formed by overlapping the pixel electrode and a potential reference electrode.
  • the storage capacitor has two structural forms depending on the potential reference electrode. One is to use the common electrode as the potential reference electrode, called C ST -on-COM, as shown in Figure 1A. The other is to use the gate line of the previous row (or the next row) of the pixel as the potential reference electrode, which is called C ST -on-Gate, as shown in Figure 1B.
  • a voltage signal with changing positive and negative polarity needs to be applied to the liquid crystal molecules to achieve AC driving of the liquid crystal molecules.
  • the AC drive of the liquid crystal molecules is achieved so that the potential of the other electrode of the liquid crystal capacitor (i.e., the pixel electrode) is higher and lower relative to the potential of the common electrode.
  • This AC drive method is called common electrode DC voltage drive.
  • this AC driving method is a voltage jump driving method of the common electrode.
  • FIG. 1C shows a voltage waveform diagram of a common electrode DC voltage drive.
  • the voltage of the common electrode is fixed, and the voltage of the pixel electrode fluctuates up and down according to different gray levels.
  • the example of FIG. 1C shows the voltage waveform changes of the pixel electrode at 256 gray levels.
  • the voltage of the common electrode is higher than the voltage of the pixel electrode, and the liquid crystal molecules have negative polarity; for the N+1th image frame, the voltage of the common electrode is lower than the voltage of the pixel electrode, and the liquid crystal molecules have positive polarity. Whether it is positive or negative polarity, liquid crystal molecules can achieve different gray scales.
  • the gate of the pixel switching element T0 is connected to the gate line to receive the gate signal, and the source of the pixel switching element T0 is connected to the data line to receive the data signal (also called "source signal”). ).
  • the drain of the pixel switching element T0 is connected to the pixel electrode.
  • One or more embodiments of the present disclosure provide a driving method to solve the problems that liquid crystal display panels are prone to uneven display, residual images, and even negative polarity data offset.
  • the inventor of the present disclosure found that the timing of the gate signal and the data signal caused the liquid crystal display panel to be prone to problems such as uneven display, afterimages, and even negative polarity data offset, and thus proposed The present invention solves this problem.
  • FIG. 1D shows a partial timing diagram of a gate signal and a data signal.
  • the Gamma voltage Vs+ of positive polarity liquid crystal molecules is between 8.8V and 16.3V
  • the Gamma voltage Vs- of negative polarity liquid crystal molecules is between 0.3V and 7.8V.
  • Vs- is smaller than Vs+, at the falling edge of the gate signal (during the gate voltage changing from VGH to VGL), when the liquid crystal molecules are of negative polarity, the pixel switching element T0 (hereinafter referred to as the "negative polarity sub-pixel") Vgs> Vgs' of the pixel switching element T0 (hereinafter referred to as "positive sub-pixel") when the liquid crystal molecules are positive, that is, the off-voltage position of the positive sub-pixel is earlier than the off-voltage position of the negative sub-pixel, resulting in the negative sub-pixel
  • the charging time on the falling edge is longer than for positive polarity subpixels.
  • the positive polarity data signal is a signal that causes the voltage of the pixel electrode of the subpixel to be higher than the voltage of the common electrode
  • the negative polarity data signal is a signal that causes the voltage of the pixel electrode of the subpixel to be lower than the voltage of the common electrode
  • FIG. 1D takes the falling edge of the gate signal as an example to illustrate that the charging time of positive polarity and negative polarity is different, but this does not have a limiting effect on the embodiments to be described below.
  • the driving method provided by the embodiments of the present disclosure below can also be applied on the rising edge of the gate signal.
  • the falling edge and rising edge of the gate signal are collectively referred to as the transition period.
  • the charging time of negative polarity sub-pixels during the transition period is longer than that of positive polarity sub-pixels. This will cause differences in charging time under different polarities, resulting in poor display (such as uneven display, afterimages) and other problems, and even negative polarity data offset. .
  • Figure 1E shows a partial timing diagram of another gate signal and data signal.
  • the ideal positive polarity data signal, the ideal negative polarity data signal and the ideal gate signal are all square wave signals (i.e., the signal represented by the dotted line), but in actual applications, regardless of the positive polarity data
  • the signal and the negative polarity data signal are still gate signals.
  • the actual signal is represented by a solid line in Figure 1E.
  • the actual positive polarity data signal includes data signal 1 and data signal 2.
  • Data signal 1 represents the positive polarity data signal received by the sub-pixel closer to the source driving chip;
  • data signal 2 represents the positive polarity data signal received by the sub-pixel farther from the source driving chip.
  • the positive polarity data signal received by the sub-pixel farther from the source driving chip has a greater delay than the positive polarity data signal received by the sub-pixel closer to the source driving chip.
  • actual negative polarity data signals include data signal 3 and data signal 4.
  • Data signal 3 represents the negative polarity data signal received by the sub-pixel closer to the source driving chip;
  • data signal 4 represents the negative polarity data signal received by the sub-pixel farther from the source driving chip.
  • the negative polarity data signal received by the sub-pixel farther from the source driving chip has a greater delay than the negative polarity data signal received by the sub-pixel closer to the source driving chip.
  • the actual falling edge of the gate signal is a slope. Due to the existence of the slope, the actual positive polarity data signal is turned off earlier than the actual negative polarity data signal. The actual negative polarity data signal is turned off relative to the actual positive polarity. There is a time delay ⁇ T when the data signal is turned off.
  • the driver chip requires too many source channels (i.e., 46080 Channel), and the Chip On Flex film Or Chip On Film (COF) size is moving towards smaller and smaller design trends.
  • COF Chip On Flex film Or Chip On Film
  • the module binding process limits the development of COF size. For example, the size of the COF on the LCD panel side is too small and easily exceeds the minimum size binding capability. That is, when the device is adjusted after pre-alignment, the minimum step displacement distance exceeds the COF's size.
  • the larger number of COFs required leads to a decrease in the binding yield and an increase in costs.
  • At least one embodiment of the present disclosure provides a driving method of a liquid crystal display panel and a liquid crystal display panel.
  • the liquid crystal display panel includes a pixel array.
  • the pixel array includes a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels.
  • the plurality of sub-pixels are arranged in multiple rows and columns.
  • Each gate line provides a gate signal for at least one row of sub-pixels.
  • the data lines provide data signals for at least one column of sub-pixels, and each sub-pixel is connected to a corresponding gate line and a corresponding data line.
  • the driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels in multiple rows of sub-pixels.
  • the first gate signal includes an on period and an off period, and is used to control the first row of sub-pixels. Turn on and off respectively; while the first gate signal is on, multiple first data signals are respectively written to multiple sub-pixels of the first row of sub-pixels through multiple data lines, and the multiple first data signals include positive polarity data signal and the negative polarity data signal, during the period when the first gate signal is on, the first writing time length of the negative polarity data signal is less than the second writing time length of the positive polarity data signal.
  • This driving method can improve the image quality and yield of liquid crystal display panels, and alleviate problems such as uneven display, residual images, and even negative polarity data that are prone to occur in liquid crystal display panels.
  • FIG. 2A shows a flow chart of a driving method provided by at least one embodiment of the present disclosure.
  • FIG. 2B shows a schematic diagram of a pixel driving architecture of a liquid crystal display panel provided by at least one embodiment of the present disclosure. This pixel driving architecture can apply the driving method shown in Figure 2A.
  • the driving method may include steps S10 to S20.
  • Step S10 Provide a first gate signal to the first gate line corresponding to the first row of sub-pixels in the multiple rows of sub-pixels.
  • the first gate signal includes an on period and an off period, and is used to control the first row of sub-pixels to turn on respectively. and close.
  • Step S20 While the first gate signal is on, write multiple first data signals to multiple sub-pixels in the first row of sub-pixels through multiple data lines.
  • the multiple first data signals include positive polarity data signals and For the negative polarity data signal, during the period when the first gate signal is on, the first writing time length of the negative polarity data signal is shorter than the second writing time length of the positive polarity data signal.
  • the liquid crystal display panel includes a pixel array.
  • the pixel array includes a plurality of gate lines (gate lines G1 to gate lines Gn), a plurality of data lines (data lines Data1 to data lines Data(m)), and a plurality of sub-pixels. (Subpixel P11 to subpixel P(nm)). Multiple sub-pixels are arranged in multiple rows and multiple columns. For example, sub-pixels P11 to sub-pixels P(nm) are arranged in n rows and m columns. Both n and m are integers greater than or equal to 1.
  • Each sub-pixel may have the structure shown in Figure 1A or Figure 1B.
  • each sub-pixel includes a pixel switching element and an equivalent capacitance C.
  • the equivalent capacitance C may include, for example, the liquid crystal capacitance and storage capacitance shown in FIG. 1A or FIG. 1B .
  • Each gate line provides a gate signal for at least one row of sub-pixels
  • each data line provides a data signal for at least one column of sub-pixels
  • each sub-pixel is connected to a corresponding gate line and a corresponding data line.
  • the first row of sub-pixels refers to an optional row of sub-pixels in the pixel array, that is, "first" in this disclosure does not indicate a sequence.
  • the first gate line refers to the gate line connected to the first row of sub-pixels among the plurality of gate lines
  • the first gate line signal refers to a signal provided by the gate line connected to the first row of sub-pixels.
  • the first row of sub-pixels is the sub-pixel arranged in the i-th row in the pixel array
  • the first gate line is the gate line connected to the sub-pixel arranged in the i-th row in the pixel array
  • i is greater than or equal to 1 integer.
  • the on period of the first gate signal is used to control the first row of sub-pixels to be on, and the off period of the first gate signal is used to control the first row of sub-pixels to be off.
  • the turn-on period of the first gate signal may be a period during which the first gate signal is at a high level VGH, and the turn-on period of the first gate signal may be a period during which the first gate signal is at a high level VGL.
  • a gate signal is provided to a plurality of sub-pixels P(n1) to P(nm) arranged in the n-th row in the pixel array through the gate line Gn.
  • the plurality of data lines write a plurality of first data signals to the plurality of sub-pixels Pn1 to P(nm) respectively.
  • the plurality of first data signals include positive polarity data signals and negative polarity data signals.
  • the plurality of sub-pixels Pn1 to P(nm) arranged in the n-th row are examples of sub-pixels in the first row.
  • 2C and 2D illustrate a schematic diagram of a polarity reversal driving method provided by at least one embodiment of the present disclosure.
  • FIG. 2C is a schematic polarity diagram of the data signal of the Nth image frame
  • FIG. 2D is a schematic polarity diagram of the data signal of the N+1th image frame.
  • the polarity inversion driving mode is a column inversion driving mode, that is, the data signals in the same column have the same polarity, and the data signals in adjacent columns have opposite polarities.
  • multiple data lines write data signals to the row of sub-pixels respectively. For example, negative polarity data signals are written into sub-pixels in odd-numbered columns, and positive-polarity data signals are written into sub-pixels in even-numbered columns.
  • multiple data lines write data signals to the row of sub-pixels respectively. For example, positive polarity data signals are written into sub-pixels in odd-numbered columns, and negative-polarity data signals are written into sub-pixels in even-numbered columns.
  • FIG. 2C and FIG. 2D are only examples of a polarity inversion driving method, and it does not mean that the embodiments of the present disclosure are only applicable to the polarity inversion driving method shown in FIG. 2C and FIG. 2D .
  • embodiments of the present disclosure are also applicable to row inversion driving methods, that is, the data signal polarities of the same row are consistent, and the data signal polarities of adjacent rows are opposite.
  • embodiments of the present disclosure are also applied to the dot inversion driving method, that is, the data signal polarity of each adjacent sub-pixel is opposite.
  • the writing time length of the negative polarity data signal is T-
  • the writing time length of the positive polarity data signal is T+, 0 ⁇ T- ⁇ T+.
  • T- is an example of the first writing time length
  • T+ is an example of the second writing time length.
  • the impact caused by the charging time of the signal can alleviate problems such as uneven display, afterimages, and even negative polarity data misshooting.
  • This embodiment only needs to adjust the timing relationship between the negative polarity data signal or the positive polarity data signal and the first gate signal. It does not need to modify the hardware circuit of the liquid crystal display panel, is easy to implement, and has good compatibility.
  • the delay time of the starting time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal is a first time length
  • the delay time of the positive polarity data signal relative to the first gate signal corresponds to The delay time of the starting time point of the turn-on period is a second time length
  • the first time length is greater than the second time length, so that during the turn-on period of the first gate signal, the first writing time length of the negative polarity data signal is less than The second writing time length of the positive polarity data signal.
  • FIG. 2E shows a timing signal diagram of a gate signal and a data signal provided by at least one embodiment of the present disclosure.
  • the turn-on period corresponding to the first gate signal may, for example, refer to the period during which the gate voltage of the first gate signal is VGH, and the starting time point of the turn-on period corresponding to the first gate signal. Refers to the moment when the gate voltage starts to be VGH. As shown in FIG. 2E , the turn-on period corresponding to the first gate signal may be Tkq, and the starting time point of the turn-on period corresponding to the first gate signal may be time Tq.
  • the starting time point of the turn-on period corresponding to the first gate signal is slightly earlier than the Tq moment.
  • the delay time of the negative polarity data signal relative to the starting time point Tq is the first time length T1
  • the delay time of the positive polarity data signal relative to the starting time point Tq is the second time length T2.
  • the first time length T1 is greater than the second time length T2.
  • the second time length T2 may be approximately equal to 0, for example.
  • the first time length may be determined based on the difference between the charging time length of the negative polarity data signal and the charging time length of the positive polarity data signal and the second time length T2.
  • the first gate signal includes a transition period between adjacent on-periods and off-periods.
  • the first time length is longer than the second time length by a preset time length, and the preset time length is the writing time length of the negative polarity data signal and the writing time length of the positive polarity data signal during the transition period of the first gate signal. the difference between.
  • the transition period is the falling edge period of the first gate signal.
  • the transition period Tgd is the falling edge between the adjacent on-period and off-period.
  • the preset time length T Treg-Tpos, therefore the first time length T1 is longer than the second time length T2 by the preset time length T.
  • the preset time length can be slightly larger than T. For example, on the rising edge, the time when the negative polarity data signal is written into the subpixel is t earlier than the time when the positive polarity data signal is written into the subpixel, then the preset time length may be T+t.
  • the first time length T1 is longer than the second time length T2 by a preset time length T.
  • the starting time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal and the starting time point of the turn-on period corresponding to the positive polarity data signal relative to the first gate signal Same or different.
  • the starting time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal and the starting time point of the turn-on period corresponding to the positive polarity data signal relative to the first gate signal All are Tq moments.
  • the starting time point of the turn-on period corresponding to the negative polarity data signal relative to the first gate signal is the moment when the gate voltage starts to be VGH in the kth period of the first gate signal, and the positive polarity data signal corresponds to the kth period of the first gate signal.
  • the starting time point of the turn-on period corresponding to a gate signal is the moment when the gate voltage starts to be VGH in the r-th cycle, and k and r are different integers.
  • the k-th period and the r-th period are adjacent periods, that is, in the k-th period of the first gate signal, a negative polarity data signal is provided to the odd rows in Figure 2C, and in the k-th period of the first gate signal r cycles provide positive polarity data signals to the even rows in Figure 2C.
  • 3A shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure.
  • 3B and 3C illustrate a timing signal diagram provided by at least one embodiment of the present disclosure.
  • each data line provides data signals for two adjacent columns of sub-pixels.
  • data line S1 provides data signals to sub-pixels arranged in, for example, adjacent first and second columns of a pixel array.
  • each data line provides data signals for two adjacent columns of sub-pixels, the other structures are similar to Figure 2B. Please refer to the description of Figure 2B.
  • each data line provides a positive polarity data signal and a negative polarity data signal respectively to the first sub-pixel and the second sub-pixel in the same row and two adjacent columns.
  • each data line respectively provides a positive polarity data signal and a negative polarity data to the first sub-pixel and the second sub-pixel in two adjacent columns of the first row of sub-pixels.
  • the turn-on period of the first gate signal includes a first sub-turn-on period and a second sub-turn-on period.
  • each data line respectively provides a negative polarity data signal and a positive polarity data signal to the first sub-pixel and the second sub-pixel in two adjacent columns of the first row of sub-pixels. data signal.
  • the polarity distribution of the liquid crystal molecules of the Nth image frame is, for example, the example of FIG. 2C .
  • a sub-pixel arranged in the i-th row in the pixel array an example of a first-row sub-pixel
  • G(i) the first gate signal
  • each data line sequentially provides a negative polarity data signal and a positive polarity data signal to the first sub-pixel and the second sub-pixel in the first row and adjacent column, respectively.
  • multiple data lines first provide negative polarity data signals to sub-pixels in odd-numbered rows, and then provide positive-polarity data signals to sub-pixels in even-numbered rows, and providing negative-polarity data signals to sub-pixels in odd-numbered rows is faster than providing negative-polarity data signals to sub-pixels in even rows.
  • the pixel provides a positive polarity data signal for a short period of time.
  • the turn-on period of the first gate signal G(i) includes a first sub-turn-on period Tkq1 and a second sub-turn-on period Tkq2.
  • the time length of the first sub-on period Tkq1 is greater than the time length of the second sub-on period Tkq2.
  • multiple data lines provide negative polarity data signals to sub-pixels in odd rows respectively.
  • multiple data lines provide positive polarity data to sub-pixels in even rows respectively.
  • the second sub-on period Tkq2 is earlier than the first sub-on period Tkq1 .
  • the second sub-on period Tkq2 may also be later than the first sub-on period Tkq1.
  • the second row of sub-pixels is turned on.
  • the second row of sub-pixels may be, for example, adjacent rows or non-adjacent rows of sub-pixels to the first row of sub-pixels.
  • the second gate signal G(i+1) for the second row of sub-pixels is in the on period, causing the second row of sub-pixels to be turned on, so that multiple data lines provide negative polarity data signals and Positive polarity data signal.
  • the way in which the multiple data lines provide negative polarity data signals and positive polarity data signals to the second row of sub-pixels is the same as the way in which the negative polarity data signals and positive polarity data signals are respectively provided to the first row of sub-pixels, which will not be described again here. .
  • FIG. 3C is a timing signal diagram of the N+1th image frame.
  • the polarity distribution of liquid crystal molecules in the N+1th image frame is as shown in FIG. 2D .
  • each data line sequentially provides a positive polarity data signal and a negative polarity data signal to the first sub-pixel and the second sub-pixel in the first row and adjacent column.
  • multiple data lines first provide positive polarity data signals to sub-pixels in odd-numbered rows, and then provide negative-polarity data signals to sub-pixels in even-numbered rows.
  • the turn-on period of the first gate signal includes a first sub-turn-on period Tkq1 and a second sub-turn-on period Tkq2.
  • the time length of the first sub-on period Tkq1 is greater than the time length of the second sub-on period Tkq2.
  • multiple data lines provide positive polarity data signals to sub-pixels in odd rows respectively.
  • multiple data lines provide negative polarity data to sub-pixels in even rows respectively.
  • the second sub-on period Tkq2 is later than the first sub-on period Tkq1. In other embodiments, the second sub-on period Tkq2 may also be earlier than the first sub-on period Tkq1.
  • the second row of subpixels is turned on.
  • the second row of sub-pixels may be, for example, adjacent rows or non-adjacent rows of sub-pixels to the first row of sub-pixels.
  • the second gate signal G(i+1) for the second row of sub-pixels is in the on period, causing the second row of sub-pixels to be turned on, so that multiple data lines provide negative polarity data signals and Positive polarity data signal.
  • This pixel driving architecture provides data signals to two sub-pixels in adjacent columns (i.e., 1:2 control) through a data line, which can reduce the number of COFs used, while also improving the bonding yield and reducing costs in disguise, and the The driver architecture makes it easier to control the first write time length and the second write time length.
  • FIG. 4 shows a partial schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure.
  • each sub-pixel in the liquid crystal display panel includes a pixel electrode and a pixel switching element.
  • pixel electrode and pixel switching element please refer to Figure 1A and Figure 1B, but is not limited to what is shown in Figure 1A and Figure 1B. situation.
  • each data line provides data signals to two adjacent columns of subpixels.
  • data line S1 provides data signals for the first column of sub-pixels and the second column of sub-pixels.
  • the sub-pixels in the first column refer to an optional row of sub-pixels in the pixel array, and the sub-pixels in the second column are sub-pixels adjacent to the sub-pixels in the first column.
  • the first column of sub-pixels is the column where sub-pixel Q11 is located
  • the second column of sub-pixels is the column where sub-pixel Q12 is located.
  • FIG. 4 only shows the connection relationship between the data line S1 and two columns of sub-pixels, it does not mean that the pixel driving architecture only includes the data line S1 and these two columns of sub-pixels. In fact, the pixel driving architecture It usually includes multiple data lines and multiple columns of sub-pixels. The arrangement of other data lines and sub-pixels in other columns is similar to that shown in Figure 4 and will not be described again.
  • each sub-pixel may include a multiplexing switching element in addition to a pixel switching element.
  • subpixel Q11 includes a pixel switching element T11-1 and a multiplexing switching element T11-2
  • subpixel Q12 includes a pixel switching element T12-1 and a multiplexing switching element T12-2.
  • Each data line provides a positive polarity data signal to the pixel electrode of the first sub-pixel through the first multiplexing switching element, and provides a negative polarity data signal to the pixel electrode of the second sub-pixel through the second multiplexing switching element.
  • the data line S1 provides the positive polarity data signal to the source of the pixel switching element T11-1 of sub-pixel Q11 through the multiplexed switching element T11-2, thereby switching the positive polarity
  • the data signal is supplied to the pixel electrode of the sub-pixel Q11.
  • the liquid crystal molecules of the sub-pixel Q12 are of negative polarity, so the data line S1 provides the negative-polarity data signal to the source of the pixel switching element T12-1 of the sub-pixel Q12 through the multiplexing switching element T12-2, thereby switching the negative-polarity data signal Provided to the pixel electrode of sub-pixel Q12.
  • the multiplexing switching element T11-2 and the multiplexing switching element T12-2 are examples of the first multiplexing switching element and the second multiplexing switching element respectively.
  • another switching element in the sub-pixel may be, for example, a thin film transistor, or other types of switching elements.
  • the first multiplexing switching element, the second multiplexing switching element and the pixel switching element are all thin film transistors.
  • the multiplexing switching element T11-2 is connected to the control line VDDODD to receive the first control signal provided by the control line VDDODD.
  • the multiplexing switching element T11-2 is configured to respond to the control of the first control signal.
  • the multiplexing switch element T12-2 is connected to the control line VDDEVEN to receive the second control signal provided by the control line VDDEVEN, and the multiplexing switching element T12-2 is configured to be turned on and off in response to the control of the second control signal.
  • the first control signal provided by the control line VDDODD causes the multiplexing switching element T11-2 to turn on, so that the positive polarity data signal is provided to the pixel electrode of the pixel switching element T11-1
  • the second control signal provided by the control line VDDEVEN causes the multiplexing switching element T12-2 to turn off, so that the positive polarity data signal cannot be provided to the pixel electrode of the multiplexing switching element T12-1.
  • the first control signal provided by the control line VDDODD causes the multiplexing switching element T11-2 to turn off, so that the negative polarity data signal cannot be provided to the pixels of the pixel switching element T11-1.
  • the second control signal provided by the control line VDDEVEN causes the multiplexing switching element T12-2 to turn on, so that the negative polarity data signal is provided to the pixel electrode of the multiplexing switching element T12-1.
  • the multiplexing switch element T11-2 when the data line S1 provides a negative polarity signal, the multiplexing switch element T11-2 is turned on. , when the data line S1 provides a positive polarity signal, the multiplexing switching element T12-2 is turned off.
  • This embodiment uses the first multiplexing switching element and the second multiplexing switching element to determine whether to write data signals to the sub-pixels during the first turn-on period and the second turn-on period, thereby achieving AC driving of the liquid crystal molecules, and by adjusting
  • the time ratio between the second turn-on period Tkq2 and the first turn-on period Tkq1 can reduce the second turn-on period Tkq2 (negative polarity charging time) and increase the first turn-on period Tkq1 (positive polarity charging time), thereby adjusting the positive and negative electrodes.
  • the charging time allows the pixel voltage to reach a balance between positive and negative polarities, thereby improving the uniformity of the display panel and improving image quality.
  • the first sub-on period and the second sub-on period are respectively the same as the on-time period of the first multiplexing switching element and the on-time period of the second multiplexing switching element. For example, during the sub-on period Tkq1, the multiplexing switching element T11-2 is turned on; during the sub-on period Tkq2, the multiplexing switching element T12-2 is turned on.
  • FIG. 5A shows a timing signal diagram of the Nth image frame provided by at least one embodiment of the present disclosure
  • FIG. 5B shows a timing signal diagram of the N+1th image frame provided by at least one embodiment of the present disclosure.
  • the gate signals of multiple rows of sub-pixels are turned on in sequence.
  • the liquid crystal molecules of the sub-pixels in the odd-numbered columns have negative polarity
  • the liquid crystal molecules of the sub-pixels in the even-numbered columns have positive polarity.
  • Data lines connected to adjacent columns sequentially provide negative polarity data signals to sub-pixels in odd-numbered columns, and provide positive-polarity data signals to sub-pixels in even-numbered columns. That is, the polarity distribution of the data signal of the Nth image frame is as shown in FIG. 2C.
  • Tkq1 is the same as the on-time period of the multiplexing switching elements of the even columns (that is, the time period when the VDDEVEN signal is high level), and during the sub-on period Tkq2 is the same as the multiplexing switching elements of the odd columns.
  • the turn-on period of the switching elements (that is, the period in which the VDDODD signal is high level) is the same.
  • the gate signals of multiple rows of sub-pixels are turned on in sequence.
  • the liquid crystal molecules of the sub-pixels in the odd-numbered columns have positive polarity
  • the liquid crystal molecules of the sub-pixels in the even-numbered columns have negative polarity.
  • Data lines connected to adjacent columns sequentially provide positive polarity data signals to sub-pixels in odd-numbered columns, and provide negative-polarity data signals to sub-pixels in even-numbered columns. That is, the polarity distribution of the data signal of the N+1th image frame is as shown in FIG. 2D.
  • the sub-on period Tkq1 is the same as the on-time period of the multiplexing switch elements of the odd columns (that is, the time period when the VDDODD signal is high level), and the sub-on period Tkq2 is the same as the multiplexing switch elements of the even columns.
  • the on-time periods of the components ie, the period during which the VDDEVEN signal is high) are the same.
  • FIG. 6 shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure.
  • the first multiplexing switching element and the second multiplexing switching element are arranged around the liquid crystal display panel.
  • the periphery of the liquid crystal display panel is, for example, a control area of the liquid crystal display panel.
  • Multiple sub-pixels are provided in the display area of the liquid crystal display panel.
  • the multiplexing switching element TFT1 and the multiplexing switching element TFT2 are provided in a control area around the liquid crystal display panel.
  • the multiplexing switching element TFT1 and the multiplexing switching element TFT2 are examples of the first multiplexing switching element and the second multiplexing switching element respectively.
  • the data line SD1 provides the positive polarity data signal and the negative polarity data signal to the sub-pixel W11 and the sub-pixel W12 through the multiplexing switching element TFT1 and the multiplexing switching element TFT2 respectively, or, at the second moment , the data line SD1 supplies the positive polarity data signal and the positive polarity data signal to the sub-pixel W11 and the sub-pixel W12 through the multiplexing switching element TFT1 and the multiplexing switching element TFT2, respectively.
  • the subpixel W11 and the subpixel W12 are examples of the first subpixel and the second subpixel, respectively.
  • a column of sub-pixels in which the sub-pixel W11 is located shares the multiplexing switching element TFT1
  • a column of sub-pixels in which the sub-pixel W12 is located shares the multiplexing switching element TFT2.
  • the other data lines in the liquid crystal display panel are connected to two adjacent sub-pixels in the same manner as the data line S1 and the sub-pixels P11 and P12, which will not be described again.
  • the structure of each sub-pixel is similar to the structure of the sub-pixels in the previous embodiments and will not be described again.
  • This embodiment adds a first multiplexing switching element and a second multiplexing switching element controlled by the voltage provided by the VDDODD signal line and the VDDEVEN signal line, and sets the first multiplexing switching element and the second multiplexing switching element in the control area
  • the switching element reduces the number of first multiplexing switching elements and the second multiplexing switching element, and makes the multiplexing switching element setting and control area instead of the display area, which can further eliminate the need to increase the opening of the switching element to the pixel rate impact.
  • FIG. 7 shows a schematic diagram of another pixel driving architecture of a liquid crystal display panel applying a driving method provided by at least one embodiment of the present disclosure.
  • the pixel driving architecture includes a plurality of sub-pixels P'11, sub-pixels P'12, ..., P' (nm), and each data line is a first sub-pixel and a second sub-pixel in the same row and two adjacent columns.
  • the sub-pixels provide positive polarity data signals and negative polarity data signals.
  • the data line S'1 provides a positive polarity data signal and a negative polarity data signal to the sub-pixel P'11 and the sub-pixel P'12 respectively.
  • the subpixel P'11 and the subpixel P'12 are examples of the first subpixel and the second subpixel, respectively.
  • each sub-pixel may include a multiplexing switching element.
  • the subpixel P'11 includes a multiplexing switching element T'11-1
  • the subpixel P'12 includes a multiplexing switching element T'12-1.
  • each sub-pixel is the same as the previous embodiment (for example, FIG. 1A and FIG. 1B ), and will not be described again.
  • the switching element is placed between the pixel switching element and the pixel electrode.
  • Each data line provides a positive polarity data signal to the pixel electrode of the first sub-pixel through the first multiplexing switching element, and provides a negative polarity data signal to the pixel electrode of the second sub-pixel through the second multiplexing switching element.
  • the multiplexing switching element T'11-1 and the multiplexing switching element T'12-1 are examples of the first multiplexing switching element and the second multiplexing switching element, respectively.
  • the data line S1 provides a positive polarity data signal to the pixel electrode of the sub-pixel P'11 through the multiplexing switching element T'11-1, and the multiplexing switching element T'12-1
  • the negative polarity data signal is provided to the pixel electrode of sub-pixel P'12.
  • the data line S'1 provides the negative polarity data signal to the pixel electrode of the sub-pixel P'11 through the multiplexing switching element T'11-1, and the multiplexing switching element T'12-1
  • the positive polarity data signal is provided to the pixel electrode of sub-pixel P'12.
  • the first multiplexing switching element is arranged in the first sub-pixel, and the second multiplexing switching element is arranged in the second sub-pixel.
  • the multiplexing switching element T'11-1 is provided in the sub-pixel P'11
  • the multiplexing switching element T'12-1 is provided in the sub-pixel P'12.
  • each sub-pixel further includes a pixel switching element, and the pixel switching element is connected to the corresponding gate line to receive the gate signal provided by the corresponding gate line.
  • the sub-pixel P'11 includes a pixel switching element T'11-2, which is connected to the gate line G1 to receive a gate signal provided by the gate line G1.
  • the sub-pixel P'12 includes a pixel switching element T'12-2, which is also connected to the gate line G1 to receive the gate signal provided by the gate line G1.
  • the pixel switching element and the first multiplexing switching element in the first sub-pixel are connected in series between the data line and the pixel electrode, and the pixel switching element and the second multiplexing switching element in the second sub-pixel are connected in series between the data line and the pixel electrode.
  • Connected in series between the data line and the pixel electrode For example, the pixel switching element T'11-2 and the multiplexing switching element T'11-1 of the sub-pixel P'11 are connected in series between the data line S1 and the pixel electrode.
  • the pixel switching element T'12-2 and the multiplexing switching element T'12-1 in the sub-pixel P'12 are connected in series between the data line and the pixel electrode.
  • the pixel driving structure is provided with multiplexing switching elements for realizing data line multiplexing in each sub-pixel to facilitate individual control of each sub-pixel.
  • the liquid crystal display panel includes a pixel array.
  • the pixel array includes multiple gate lines, multiple data lines and multiple sub-pixels.
  • the multiple sub-pixels are arranged in multiple rows and columns.
  • Each gate line provides gate signals for one row of sub-pixels, and each data line provides two adjacent columns of sub-pixels.
  • Provide a data signal each sub-pixel is connected to a corresponding gate line and a corresponding data line, and the first gate line corresponding to the first row of sub-pixels in the multiple rows of sub-pixels is configured to provide a first gate signal to the first row of sub-pixels.
  • the first gate signal includes an on period and an off period, and is used to control the sub-pixels in the first row to turn on and off respectively.
  • Each data line is configured to be the first gate signal in two adjacent columns during the on period.
  • One sub-pixel provides a positive polarity data signal and a second sub-pixel in two adjacent columns provides a negative polarity data signal.
  • each data line is configured as a first write of the negative polarity data signal.
  • the input time length is less than the second write time length of the positive polarity data signal.
  • the turn-on period of the first gate signal includes the first sub-turn on period and the second sub-turn on period.
  • each piece of data is configured such that a first writing time length of the negative polarity data signal is less than a second writing time length of the positive polarity data signal, including: the positive polarity data signal is applied to the first sub-pixel during the first sub-on period, the negative polarity data signal The second sub-on period is applied to the second sub-pixel, and the time length of the first sub-on period is greater than the time length of the second sub-on period.
  • This liquid crystal display panel can improve the image quality and yield of the display panel, and alleviate problems such as uneven display, residual images, and even negative polarity data that are prone to occur in the liquid crystal display panel.
  • each sub-pixel further includes a pixel electrode, each data line is electrically connected to the pixel electrode of the first sub-pixel through a first multiplexing switching element, and is electrically connected to the pixel electrode of the first sub-pixel through a second multiplexing switching element.
  • the pixel electrodes of the two sub-pixels are electrically connected.
  • the first multiplexing switching element is connected to the first control line to receive the first control signal provided by the first control line, and the first multiplexing switching element is configured to respond to the first control signal
  • the second multiplexing switching element is connected to the second control line to receive the second control signal provided by the second control line, and the second multiplexing switching element is configured to respond to the control of the second control signal. to turn on and off.
  • the first multiplexing switching element and the second multiplexing switching element are arranged around the liquid crystal display panel, and a column of sub-pixels where the first sub-pixel is located shares the first multiplexing switching element, A column of sub-pixels in which the second sub-pixel is located shares the second multiplexing switching element.
  • the first multiplexing switching element is disposed in the first sub-pixel, and the second multiplexing switching element is disposed in the second sub-pixel.
  • each sub-pixel further includes a pixel switching element, and the pixel switching element is connected to the corresponding gate line to receive the gate signal provided by the corresponding gate line,
  • the pixel switching element in the first sub-pixel and the first multiplexing switching element are connected in series between the data line and the pixel electrode,
  • the pixel switching element and the second multiplexing switching element in the second sub-pixel are connected in series between the data line and the pixel electrode.
  • the liquid crystal display panel provided by the above embodiments of the present disclosure can be a pixel driving architecture of the liquid crystal display panel shown in any of the driving methods described above, such as the pixel driving architecture shown in Figure 2B, Figure 3A, Figure 6 and Figure 7 .
  • the specific functions and components of the liquid crystal display panel please refer to the relevant description of the driving method, which will not be described again here.
  • the components and structures of the liquid crystal display panel shown in FIG. 2B, FIG. 3A, FIG. 6 and FIG. 7 are only exemplary and not restrictive.
  • the liquid crystal display panel may also include other components and structures as needed.
  • FIG. 8A to 8D illustrate some other exemplary pixel driving architectures of liquid crystal display panels applied to the driving method provided by at least one embodiment of the present disclosure.
  • each gate line (for example, gate line 1 to gate line 4) is electrically connected to a row of sub-pixels, and sub-pixels in adjacent rows of the same column are respectively connected to two different data lines.
  • the red sub-pixels located in the first row are connected to data line 1
  • the red sub-pixels located in the second row are connected to data line 2.
  • the pixel driving architecture shown in Figure 8A is called a single gate line + Z architecture.
  • the plurality of gate lines may include, for example, gate lines Gate1 ⁇ Gate8, and the plurality of data lines may include, for example, Data1 ⁇ Data8.
  • Each row of sub-pixels is connected to two gate lines.
  • the sub-pixels in the first row are connected to the gate line Gate1 and the gate line Gate2.
  • Sub-pixels in adjacent columns in the same row are connected to two different gate lines. For example, the red subpixel in the first column is connected to Gate1, and the green subpixel in the second column is connected to Gate2.
  • two adjacent sub-pixels are connected to the same data line, and sub-pixels in adjacent rows of the same column are connected to two different data lines.
  • the red sub-pixels located in the first row are connected to the data line Data1
  • the red sub-pixels located in the second row are connected to the data line Data2.
  • the red sub-pixel located in the first column is connected to the data line Data1
  • the green sub-pixel located in the second column is also connected to the data line Data1.
  • the sub-pixels in each row are arranged as red light sub-pixels, green light sub-pixels, blue light sub-pixels, red light sub-pixels, green light sub-pixels, and blue light sub-pixels, and cycle according to this rule.
  • the first red light sub-pixel is connected to the gate line Gate1
  • the first green light sub-pixel is connected to the gate line Gate2
  • the first blue light sub-pixel is connected to the gate line Gate1
  • the second red light sub-pixel is connected to the gate line Gate2
  • the second green light sub-pixel is connected to the gate line Gate1
  • the second blue light sub-pixel is connected to the gate line Gate2. That is, in the pixel driving architecture of FIG. 8B , there are multiple sub-pixels in the same row that emit light of the same color and are respectively connected to two different gate lines.
  • the pixel driving architecture shown in Figure 8A is called a dual gate line + Z-2 architecture.
  • each row of sub-pixels is connected to two gate lines.
  • the sub-pixels in the first row are connected to the gate line Gate1 and the gate line Gate2.
  • two adjacent sub-pixels are connected to the same data line, and sub-pixels in adjacent rows of the same column are connected to two different data lines.
  • the red sub-pixels located in the first row are connected to the data line Data1
  • the red sub-pixels located in the second row are connected to the data line Data2.
  • the red sub-pixel located in the first column is connected to the data line Data1
  • the green sub-pixel located in the second column is also connected to the data line Data1.
  • sub-pixels in the same row that emit light of the same color are connected to the same gate line. For example, all red sub-pixels are connected to the gate line Gate1, and all green sub-pixels are connected to the gate line Gate2.
  • the pixel driving architecture shown in Figure 8C is called a dual gate line + Z-1 architecture.
  • the plurality of gate lines may include, for example, Gate Line 1 to Gate Line 4, and the plurality of data lines may include, for example, Data1 to Data6.
  • Each row is connected to a gate line, and subpixels in the same column are connected to the same data line.
  • FIGS. 8A to 8D represents a positive polarity data signal
  • “-" represents a negative polarity data signal.
  • the architecture shown in FIGS. 8A to 8D is only an example and does not limit the present disclosure.
  • the pixel array in the liquid crystal display panel may include more gate lines, data lines and sub-pixel units.
  • the positive polarity data signal and the negative polarity data signal may also be different from the examples of FIGS. 8A to 8D .
  • the driving methods in the above embodiments provided by the present disclosure can be widely used in various liquid crystal display panels, such as the architectures of Figures 8A to 8D.
  • Embodiments of the present disclosure adjust the writing time length of positive and negative polarities to improve defects caused by differences in charging time due to different output characteristics of thin film transistors under positive and negative polarities (such as uneven display, afterimages, etc.), thereby further improving The picture quality and quality of the display device.
  • At least one embodiment of the present invention also provides a display device, including the liquid crystal display panel provided by any embodiment of the present disclosure.
  • the display device can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, Any product or component with a display function such as a navigator.

Abstract

一种液晶显示面板和液晶显示面板的驱动方法。该液晶显示面板包括像素阵列，每个子像素连接到对应的栅线和对应的数据线，驱动方法包括：向多行子像素中的第一行子像素对应的第一栅线提供第一栅极信号，第一栅极信号包括开启期间和关闭期间，用于控制第一行子像素分别开启和关闭(S10)；在第一栅极信号处于开启期间，通过多条数据线向第一行子像素的多个子像素分别写入多个第一数据信号，其中，多个第一数据信号包括正极性数据信号和负极性数据信号，在第一栅极信号处于开启期间，负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度(S20)。该驱动方法能够提高液晶显示面板的画质及品质。

Description

液晶显示面板的驱动方法和液晶显示面板 技术领域
本公开的实施例涉及一种液晶显示面板的驱动方法和液晶显示面板。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。液晶显示面板(Liquid Crystal Display,LCD)是近二十年来发展较快的高新技术，因具有更薄更轻、低辐射、对比度高、响应速度快及低耗能等优点，已被广泛应用于平面显示装置。
发明内容
本公开至少一个实施例提供一种液晶显示面板的驱动方法，其中，所述液晶显示面板包括像素阵列，所述像素阵列包括多条栅线、多条数据线以及多个子像素，所述多个子像素排列为多行多列，每条栅线为至少一行子像素提供栅极信号，每条数据线为至少一列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线，所述驱动方法包括：向多行子像素中的第一行子像素对应的第一栅线提供第一栅极信号，其中，所述第一栅极信号包括开启期间和关闭期间，用于控制所述第一行子像素分别开启和关闭；在所述第一栅极信号处于所述开启期间，通过所述多条数据线向所述第一行子像素的多个子像素分别写入多个第一数据信号，其中，所述多个第一数据信号包括正极性数据信号和负极性数据信号，在所述第一栅极信号处于所述开启期间，所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度。
例如，在本公开一实施例提供的驱动方法中，负极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点的延迟时间为第一时间长度，所述正极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点的延迟时间为第二时间长度，所述第一时间长度大于所述第二时间长度，使得在所述第一栅极信号处于所述开启期间，所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度。
例如，在本公开一实施例提供的驱动方法中，负极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点和所述正极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点相同或不同。
例如，在本公开一实施例提供的驱动方法中，所述第一栅极信号还包括位于相邻的开启期间和关闭期间之间的过渡期间，所述第一时间长度比所述第二时间长度长预设时间长度，所述预设时间长度为在所述第一栅极信号的所述过渡期间，所述负极性数据信号的写入时间长度与所述正极性数据信号的写入时间长度之间的差值。
例如，在本公开一实施例提供的驱动方法中，所述每条数据线为相邻两列子像素提供数据信号，在所述第一栅极信号处于所述开启期间，所述每条数据线分别为处于同一行相邻两 列的第一子像素和第二子像素提供正极性数据信号和负极性数据信号，所述第一栅极信号的开启期间包括第一子开启期间和第二子开启期间，所述正极性数据信号在所述第一子开启期间施加至所述第一子像素，所述负极性数据信号在所述第二子开启期间施加至所述第二子像素，所述第一子开启期间的时间长度大于所述第二子开启期间的时间长度。
例如，在本公开一实施例提供的驱动方法中，每个子像素还包括像素电极，所述每条数据线通过第一复用切换开关元件将所述正极性数据信号提供到所述第一子像素的像素电极，通过第二复用切换开关元件将所述负极性数据信号提供到所述第二子像素的像素电极。
例如，在本公开一实施例提供的驱动方法中，所述第一复用切换开关元件与第一控制线连接，以接收所述第一控制线提供的第一控制信号，所述第一复用切换开关元件配置为响应所述第一控制信号的控制以开启和关闭，所述第二复用切换开关元件与第二控制线连接，以接收所述第二控制线提供的第二控制信号，所述第二复用切换开关元件配置为响应所述第二控制信号的控制以开启和关闭。
例如，在本公开一实施例提供的驱动方法中，所述第一子开启期间和所述第二子开启期间分别与所述第一复用切换开关元件的开启时间段和所述第二复用切换开关元件的开启时间段相同。
例如，在本公开一实施例提供的驱动方法中，第一复用切换开关元件和所述第二复用切换开关元件设置在所述液晶显示面板的周边，所述第一子像素所在的一列子像素共享所述第一复用切换开关元件，所述第二子像素所在的一列子像素共享所述第二复用切换开关元件。
例如，在本公开一实施例提供的驱动方法中，所述第一复用切换开关元件设置在所述第一子像素内，所述第二复用切换开关元件设置在第二子像素内。
例如，在本公开一实施例提供的驱动方法中，所述每个子像素还包括像素开关元件，所述像素开关元件连接到对应的栅线以接收所述对应的栅线提供的栅极信号，所述第一子像素中的像素开关元件与所述第一复用切换开关元件串联在所述数据线和所述像素电极之间，所述第二子像素中的像素开关元件与所述第二复用切换开关元件串联在所述数据线和所述像素电极之间。
本公开至少一个实施例提供一种液晶显示面板，包括像素阵列，所述像素阵列包括多条栅线、多条数据线以及多个子像素，所述多个子像素排列为多行多列，每条栅线为一行子像素提供栅极信号，每条数据线为相邻两列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线，多行子像素中的第一行子像素对应的第一栅线配置为向所述第一行子像素提供第一栅极信号，其中，所述第一栅极信号包括开启期间和关闭期间，用于控制所述第一行子像素分别开启和关闭，所述每条数据线配置为在所述第一栅极信号处于所述开启期间分别为相邻两列中的第一子像素提供正极性数据信号和为相邻两列中的第二子像素提供负极性数据信号，在所述第一栅极信号处于所述开启期间，所述每条数据线配置为所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度，所述第 一栅极信号的开启期间包括第一子开启期间和第二子开启期间，在所述第一栅极信号处于所述开启期间，所述每条数据线配置为所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度，包括：所述正极性数据信号在所述第一子开启期间施加至所述第一子像素，所述负极性数据信号在所述第二子开启期间施加至所述第二子像素，所述第一子开启期间的时间长度大于所述第二子开启期间的时间长度。
例如，在本公开一实施例提供的液晶显示面板中，每个子像素还包括像素电极，所述每条数据线通过第一复用切换开关元件与所述第一子像素的像素电极电连接，通过第二复用切换开关元件与所述第二子像素的像素电极电连接。
例如，在本公开一实施例提供的液晶显示面板中，所述第一复用切换开关元件与第一控制线连接，以接收第一控制线提供的第一控制信号，所述第一复用切换开关元件配置为响应所述第一控制信号的控制以开启和关闭，所述第二复用切换开关元件与第二控制线连接，以接收第二控制线提供的第二控制信号，所述第二复用切换开关元件配置为响应所述第二控制信号的控制以开启和关闭。
例如，在本公开一实施例提供的液晶显示面板中，所述第一复用切换开关元件和所述第二复用切换开关元件设置在所述液晶显示面板的周边，所述第一子像素所在的一列子像素共享所述第一复用切换开关元件，所述第二子像素所在的一列子像素共享所述第二复用切换开关元件。
例如，在本公开一实施例提供的液晶显示面板中，所述第一复用切换开关元件设置在所述第一子像素内，所述第二复用切换开关元件设置在第二子像素内。
例如，在本公开一实施例提供的液晶显示面板中，每个子像素还包括像素开关元件，所述像素开关元件连接到对应的栅线以接收所述对应的栅线提供的栅极信号，所述第一子像素中的像素开关元件与所述第一复用切换开关元件串联在所述数据线和所述像素电极之间，所述第二子像素中的像素开关元件与所述第二复用切换开关元件串联在所述数据线和所述像素电极之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A示出了一种液晶显示面板中子像素的等效电路；
图1B示出了另一种液晶显示面板中子像素的等效电路；
图1C示出了一种公共电极直流电压驱动的电压波形图；
图1D示出了一种栅极信号和数据信号的部分时序图；
图1E示出了另一种栅极信号和数据信号的部分时序图；
图2A示出了本公开至少一实施例提供的一种驱动方法的流程图；
图2B示出了本公开至少一个实施例提供的液晶显示面板的一种像素驱动架构示意图；
图2C和图2D示出了本公开至少一个实施例提供的一种极性反转驱动方式的示意图；
图2E示出了本公开至少一个实施例提供的一种栅极信号和数据信号的时序信号图；
图3A示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图；
图3B和图3C示出了本公开至少一个实施例提供的一种时序信号图；
图4示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一种像素驱动架构的部分示意图；
图5A示出了本公开至少一个实施例提供的第N图像帧的时序信号图；
图5B示出了本公开至少一个实施例提供的第N+1图像帧的时序信号图；
图6示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图；
图7示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图；以及
图8A～图8D示出了本公开至少一个实施例提供的应用于驱动方法的液晶显示面板的另一些像素驱动架构。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在液晶显示面板中，液晶是一层不导电的介质层，例如夹在设置在阵列基板上的像素电极和设置在彩膜基板上的公共电极之间，或者例如覆盖在同时设置在阵列基板上且彼此绝缘的像素电极和公共电极。液晶显示面板包括像素阵列，该像素阵列包括多行和多列像素，用于显示图像中单个像素点的每个像素包括多个分别用于控制显示某种原色(例如红绿蓝) 的子像素。图1A示出了一种液晶显示面板中的子像素的等效电路。图1B示出了另一种液晶显示面板中的子像素的等效电路。
如图1A和图1B所示，子像素包括像素开关元件T0、液晶电容C LC和存储电容C ST。像素开关元件T0例如可以是薄膜晶体管，其第一极(例如漏极)与像素电极电连接，第二极(例如源极)与该子像素所在像素列对应的数据线电连接，控制极(例如栅极)与该子像素所在像素行对应的栅线电连接。液晶分子位于像素电极和公共电极之间，形成液晶电容C LC，用于存储通过像素开关元件T0写入的数据信号。存储电容C ST是像素电极与一个电位参考电极之间交叠形成的。例如，根据电位参考电极不同，存储电容由两种结构形式。一种是用公共电极作为电位参考电极，称为C ST-on-COM，如图1A所示。另一种是以该像素上一行(或下一行)的栅线为电位参考电极，称为C ST-on-Gate，如图1B所示。
液晶显示面板工作过程中，为了避免液晶分子的极化，需给液晶分子施加一个正负极性改变的电压信号实现液晶分子的交流驱动。
如图1A和1B所示，如果公共电极的电位一直不变，则实现液晶分子的交流驱动通过使得液晶电容的另外一个电极(即，像素电极)的电位相对于公共电极电位时高时低，这种交流驱动方式称为公共电极直流电压驱动。在本公开的另一些实施例中，如果公共电极的电位在图像帧与图像帧之间跳变来实现液晶分子的交流驱动，则这种交流驱动方式为公共电极的电压跳变驱动方式。
图1C示出了一种公共电极直流电压驱动的电压波形图。
如图1C所示，公共电极的电压固定不动，像素电极的电压按照灰阶的不同，上下变动。图1C的示例示出了256灰阶的像素电极的电压波形变化。例如，对于第N图像帧，公共电极的电压高于像素电极的电压，液晶分子为负极性；对于第N+1图像帧，公共电极的电压低于像素电极的电压，液晶分子为正极性。无论是正极性还是负极性，液晶分子均可以实现不同的灰阶。
如图1A和图1B所示，像素开关元件T0的栅极与栅线连接以接收栅极信号，像素开关元件T0的源极与数据线连接以接收数据信号(又称为“源极信号”)。像素开关元件T0的漏极与像素电极连接。当像素开关元件T0的栅源极的电压Vgs<阈值电压Vth时，像素开关元件T0关断；当像素开关元件T0的栅源极的电压Vgs>阈值电压Vth时，像素开关元件T0开启。Vgs＝Vg-Vs，Vg表示像素开关元件T0的栅极电压，Vs表示像素开关元件T0的源极电压。
由于在液晶显示面板显示图像的过程中，需要给液晶分子施加一个正负极性改变的电压信号实现液晶分子的交流驱动，但是这易于导致液晶显示面板容易出现显示不均、残像等问题，甚至负极性数据错冲。
本公开的一个或多个实施例提供了一种驱动方法以解决液晶显示面板容易出现显示不均、残像，甚至负极性数据错冲等问题。在对液晶显示面板进行研究、分析之后，本公开的发明人发现栅极信号和数据信号的时序导致液晶显示面板容易出现显示不均、残像，甚至负 极性数据错冲等问题，并由此提出本本发明以解决该问题。
图1D示出了一种栅极信号和数据信号的部分时序图。
例如，栅极信号为高电平VGH等于36V，低电平VGL等于-6V，即，像素开关元件T0的栅极电压VGH＝36V，VGL＝-6V。正极性的液晶分子的伽马(Gamma)电压Vs+在8.8V到16.3V之间，负极性的液晶分子的Gamma电压Vs-在0.3V到7.8V之间。Gamma电压即为像素开关元件T0的源极电压。因此，当第N图像帧为负极性时，Vgs＝36-(Vs-)，当第N+1图像帧为正极性时，Vgs’＝36-(Vs+)。由于Vs-小于Vs+，因此，在栅极信号的下降沿(栅极电压由VGH变为VGL的过程中)，液晶分子为负极性时像素开关元件T0(以下简称为“负极性子像素”)的Vgs＞液晶分子为正极性时像素开关元件T0(以下简称为“正极性子像素”)的Vgs’，即正极性子像素的关闭电压位置早于负极性子像素的关闭电压位置，导致负极性的子像素在下降沿的充电时间长于正极性的子像素。
在本公开中，正极性数据信号是使得子像素的像素电极的电压高于公共电极的电压的信号，负极性数据信号使得子像素的像素电极的电压低于公共电极的电压的信号。
如图1D所示，例如阈值电压Vth＝0，在栅极信号的下降沿，即栅极电压由VGH变为VGL的过程中，若数据信号向像素开关元件T0提供正极性数据信号，则在t1时刻像素开关元件T0的Vgs’＝Vth＝0，若数据线向像素开关元件T0提供负极性数据信号，则在t2时刻像素开关元件T0的Vgs＝Vth＝0。因此，正极性子像素关闭的时刻比负极性子像素关闭的时刻早一个延时时间Td。
需要说明的是，在上面，图1D以栅极信号的下降沿为例说明正极性和负极性的充电时间不同，但是这对本公开下面要描述的实施例不具有限定作用。例如，在栅极信号的上升沿也可以应用下文中本公开的实施例提供的驱动方法。在下文中，将栅极信号的下降沿和上升沿统一称为过渡期间。并且，阈值电压Vth＝0也仅为一种示例，在实际应用中，阈值电压可以是任何值。
负极性子像素在过渡期间的充电时间长于正极性子像素，这会造成正负不同极性下充电时间有差异，从而造成显示不良(例如，显示不均、残像)等问题，甚至负极性数据错冲。
图1E示出了另一种栅极信号和数据信号的部分时序图。
如图1E所示，理想的正极性数据信号、理想的负极性数据信号和理想的栅极信号均为方波信号(即，虚线表示的信号)，但是在实际应用中，无论是正极性数据信号和负极性数据信号还是栅极信号，在上升沿和下降沿电压变化存在延时，也即需要经过一定的时间信号值才由第一值变化为第二值。在图1E中通过实线来表示实际的信号。
如图1E所示，实际的正极性数据信号包括数据信号1和数据信号2。数据信号1表示距离源驱动芯片较近的子像素接收到的正极性数据信号；数据信号2表示距离源驱动芯片较远的子像素接收到的正极性数据信号。如图1E所示，距离源驱动芯片较远的子像素接收到的正极性数据信号相对于距离源驱动芯片较近的子像素接收到的正极性数据信号的延时较大。类似地，实际的负极性数据信号包括数据信号3和数据信号4。数据信号3表示距离 源驱动芯片较近的子像素接收到的负极性数据信号；数据信号4表示距离源驱动芯片较远的子像素接收到的负极性数据信号。如图1E所示，距离源驱动芯片较远的子像素接收到的负极性数据信号相对于距离源驱动芯片较近的子像素接收到的负极性数据信号的延时较大。
例如，实际的栅极信号的下降沿是一个斜坡，由于斜坡的存在，导致实际的正极性数据信号早于实际的负极性数据信号关闭，实际的负极性数据信号的关闭相对于实际的正极性数据信号关闭存在时间延时ΔT。
例如，标注为16K的液晶显示面板的分辨率为15360*RGB*8640，共有15360*3＝46080列子像素，驱动芯片需要源通道数太多(即，46080 Channel)，覆晶薄膜(Chip On Flex或者Chip On Film，COF)的尺寸朝着越来越小的设计趋势发展。模组绑定工艺限制了COF尺寸的发展，例如液晶显示面板端COF的尺寸太小，容易超出最小尺寸绑定能力，即设备预对位后调整位置时，最小步进位移距离已超出COF的尺寸大小，导致无法绑定对位完成；以960个显示模块的COF为例，单片显示模块需要COF数量为46080/960＝48，需求COF数量较多导致绑定良率下降，成本上升。
因此，如何提升显示面板的画质和良率，并且在保证品质的同时又能进一步降低成本是本领域技术人员亟需解决的技术问题。
本公开至少一个实施例提供了一种液晶显示面板的驱动方法和液晶显示面板。液晶显示面板包括像素阵列，像素阵列包括多条栅线、多条数据线以及多个子像素，多个子像素排列为多行多列，每条栅线为至少一行子像素提供栅极信号，每条数据线为至少一列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线。该驱动方法包括：向多行子像素中的第一行子像素对应的第一栅线提供第一栅极信号，第一栅极信号包括开启期间和关闭期间，用于控制第一行子像素分别开启和关闭；在第一栅极信号处于开启期间，通过多条数据线向第一行子像素的多个子像素分别写入多个第一数据信号，多个第一数据信号包括正极性数据信号和负极性数据信号，在第一栅极信号处于开启期间，负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度。该驱动方法能够提高液晶显示面板的画质和良率，缓解液晶显示面板容易出现显示不均、残像，甚至负极性数据错冲等问题。
图2A示出了本公开至少一实施例提供的一种驱动方法的流程图。图2B示出了本公开至少一个实施例提供的液晶显示面板的一种像素驱动架构示意图。该像素驱动架构可以应用图2A所示的驱动方法。
如图2A所示，该驱动方法可以包括步骤S10～S20。
步骤S10：向多行子像素中的第一行子像素对应的第一栅线提供第一栅极信号，第一栅极信号包括开启期间和关闭期间，用于控制第一行子像素分别开启和关闭。
步骤S20：在第一栅极信号处于开启期间，通过多条数据线向第一行子像素的多个子像素分别写入多个第一数据信号，多个第一数据信号包括正极性数据信号和负极性数据信号，在第一栅极信号处于开启期间，负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度。
如图2B所示，液晶显示面板包括像素阵列，像素阵列包括多条栅线(栅线G1～栅线Gn)、多条数据线(数据线Data1～数据线Data(m))以及多个子像素(子像素P11～子像素P(nm))。多个子像素排列为多行多列，例如子像素P11～子像素P(nm)排列为n行m列，n和m均为大于或者等于1的整数。每个子像素可以图1A或者图1B所示的结构。例如，每个子像素包括像素开关元件和等效电容C，等效电容C例如可以包括图1A或者图1B所示的液晶电容和存储电容。
每条栅线为至少一行子像素提供栅极信号，每条数据线为至少一列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线。
对于步骤S10，第一行子像素是指像素阵列中的任选的一行子像素，也即在本公开中“第一”并不是表示一种顺序。类似地，第一栅线是指多条栅线中与第一行子像素连接的栅线，第一栅线信号是指与第一行子像素连接的栅线提供的一种信号。例如，第一行子像素为在像素阵列中排在第i行的子像素，第一栅线为与在像素阵列中排在第i行的子像素连接的栅线，i为大于或者等于1的整数。
第一栅极信号的开启期间用于控制第一行子像素开启，第一栅极信号的关闭期间用于控制第一行子像素关闭。例如，第一栅极信号的开启期间可以是第一栅极信号处于高电平VGH的期间，第一栅极信号的开启期间可以是第一栅极信号处于高电平VGL的期间。
例如，通过栅线Gn向在像素阵列中排在第n行的多个子像素P(n1)～子像素P(nm)提供栅极信号。
对于步骤S20，例如在排在第n行的栅极信号的开启期间，多条数据线向多个子像素Pn1～子像素P(nm)分别写入多个第一数据信号。多个第一数据信号包括正极性数据信号和负极性数据信号。排在第n行的多个子像素Pn1～子像素P(nm)为第一行子像素的示例。
图2C和图2D示出了本公开至少一个实施例提供的一种极性反转驱动方式的示意图。
图2C为第N图像帧的数据信号的极性示意图，图2D为第N+1图像帧的数据信号的极性示意图。
如图2C和图2D所示，该极性反转驱动方式为列反转驱动方式，即，同一列的数据信号极性是一致的，相邻列的数据信号极性则相反。
对于同一个子像素，前后相邻两帧的极性发生改变。
如图2C所示，对于第N图像帧的任一行子像素，在该行子像素的开启期间，多条数据线分别向该行子像素写入数据信号。例如，负极性数据信号写入奇数列的子像素，正极性数据信号写入偶数列的子像素。
如图2D所示，对于第N+1图像帧的任一行子像素，在该行子像素的开启期间，多条数据线分别向该行子像素写入数据信号。例如，正极性数据信号写入奇数列的子像素，负极性数据信号写入偶数列的子像素。
需要说明的是，图2C和图2D仅为一种极性反转驱动方式的示例，并不意味着本公开的实施例只应用于图2C和图2D所示的极性反转驱动方式。例如，本公开的实施例还应用 于行反转驱动方式，即，同一行的数据信号极性是一致的，相邻行的数据信号极性则相反。又例如，本公开的实施例还应用于点反转驱动方式，即，相邻的每个子像素的数据信号极性是相反的。
例如，在第一栅极信号处于开启期间，负极性数据信号的写入时间长度为T-，正极性数据信号的写入时间长度为T+，0<T-<T+。T-为第一写入时间长度的示例，T+为第二写入时间长度的示例。该实施例通过调整在第一栅极信号的开启期间，负极性数据信号的写入时间长度小于正极性数据信号的写入时间长度来弥补由于过渡期间负极性数据信号的充电时间长于正极性数据信号的充电时间带来的影响，从而缓解显示不均、残像，甚至负极性数据错冲等问题。该实施例只需要调整负极性数据信号或者正极性数据信号与第一栅极信号的时序关系来实现，不需要对液晶显示面板的硬件电路进行改动，易于实现，具有较好的兼容性。
在本公开的一些实施例中，负极性数据信号相对于第一栅极信号对应的开启期间的起始时间点的延迟时间为第一时间长度，正极性数据信号相对于第一栅极信号对应的开启期间的起始时间点的延迟时间为第二时间长度，第一时间长度大于第二时间长度，使得在第一栅极信号处于开启期间，负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度。
图2E示出了本公开至少一个实施例提供的一种栅极信号和数据信号的时序信号图。
在本公开的一些实施例中，第一栅极信号对应的开启期间例如可以是指第一栅极信号的栅极电压为VGH的期间，第一栅极信号对应的开启期间的起始时间点是指栅极电压开始为VGH的时刻。如图2E所示，第一栅极信号对应的开启期间可以为Tkq，第一栅极信号对应的开启期间的起始时间点可以为Tq时刻。
在本公开的另一些实施例中，例如将第一数据线提供正极性数据信号时栅源极电压Vgs’＝阈值电压Vth的时刻作为第一栅极信号对应的开启期间的起始时间点。例如，在该实施例中，第一栅极信号对应的开启期间的起始时间点略早于Tq时刻。
在下文中除非特别说明，则以起始时间点为Tq时刻来说明本公开的至少部分实施例。
如图2E所示，负极性数据信号相对于起始时间点Tq的延迟时间为第一时间长度T1，正极性数据信号相对于起始时间点Tq的延迟时间为第二时间长度T2。第一时间长度T1大于第二时间长度T2。该实施例通过提供负极性数据信号晚于提供正极性数据信号来弥补由于负极性数据信号的充电时间长于正极性数据信号的充电时间带来的影响，从而缓解显示不均、残像，甚至负极性数据错冲等问题。
在本公开的一些实施例中，第二时间长度T2例如可以约等于0。第一时间长度可以根据负极性数据信号的充电时长与正极性数据信号的充电时长之差以及第二时间长度T2来确定。
在本公开的一些实施例中，第一栅极信号包括位于相邻的开启期间和关闭期间之间的过渡期间。第一时间长度比第二时间长度长预设时间长度，预设时间长度为在第一栅极信号的过渡期间，负极性数据信号的写入时间长度与正极性数据信号的写入时间长度之间的差 值。
例如，过渡期间为第一栅极信号的下降沿期间，在图2E中过渡期间Tgd为位于相邻的开启期间和关闭期间之间的下降沿。
如图2E所示，例如阈值电压Vth＝0，在过渡期间Tgd，对于负极性数据信号，在t4时刻薄膜晶体管的Vgs＝Vth＝0，此时负极性数据信号停止写入，对于正极性数据信号，在t3时刻时薄膜晶体管的Vgs’＝Vth＝0，此时正极性数据信号停止写入。因此，负极性数据信号的写入时间长度为Treg，正极性数据信号的写入时间长度为Tpos。预设时间长度T＝Treg-Tpos，因此第一时间长度T1比第二时间长度T2长预设时间长度T。
在本公开的另一些实施例中，考虑到在第一栅极信号还包括上升沿，由于上升沿导致负极性数据信号写入子像素的时间早于正极性数据信号写入子像素的时间，因此，预设时间长度可以略大于T。例如，在上升沿，负极性数据信号写入子像素的时间比正极性数据信号写入子像素的时间早t，则预设时间长度可以为T+t。
又例如，在将数据线提供正极性数据信号时，栅源极电压Vgs’＝阈值电压Vth的时刻作为第一栅极信号对应的开启期间的起始时间点的实施例中，第一时间长度T1比第二时间长度T2长预设时间长度T。
在本公开的一些实施例中，负极性数据信号相对于第一栅极信号对应的开启期间的起始时间点和正极性数据信号相对于第一栅极信号对应的开启期间的起始时间点相同或不同。
例如，在图2E的示例中，负极性数据信号相对于第一栅极信号对应的开启期间的起始时间点和正极性数据信号相对于第一栅极信号对应的开启期间的起始时间点均为Tq时刻。
又例如，负极性数据信号相对于第一栅极信号对应的开启期间的起始时间点为第一栅极信号第k个周期中栅极电压开始为VGH的时刻，正极性数据信号相对于第一栅极信号对应的开启期间的起始时间点为第r个周期中栅极电压开始为VGH的时刻，k和r为不相同的整数。例如，第k个周期和第r个周期为相邻周期，即在第一栅极信号的第k个周期中向图2C中的奇数行提供负极性数据信号，在第一栅极信号的第r个周期向图2C中的偶数行提供正极性数据信号。
图3A示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图。图3B和图3C示出了本公开至少一个实施例提供的一种时序信号图。
如图3A所示，在该驱动架构中，每条数据线为相邻两列子像素提供数据信号。例如，数据线S1为排在像素阵列中例如相邻的第一列和第二列子像素提供数据信号。在该驱动架构中，除了每条数据线为相邻两列子像素提供数据信号之外，其他与的结构与图2B类似，请参考图2B的描述。
在该驱动架构的一个示例中，每条数据线分别为处于同一行相邻两列的第一子像素和第二子像素提供正极性数据信号和负极性数据信号。例如，在第一栅极信号的开启期间的第一时刻，每条数据线分别为第一行子像素相邻两列的第一子像素和第二子像素提供正极性数据信号和负极性数据信号。第一栅极信号的开启期间包括第一子开启期间和第二子开启 期间。正极性数据信号在第一子开启期间施加至第一子像素，负极性数据信号在第二子开启期间施加至第二子像素，第一子开启期间的时间长度大于第二子开启期间的时间长度。又例如，在第一栅极信号的开启期间的第二时刻，每条数据线分别为第一行子像素相邻两列的第一子像素和第二子像素提供负极性数据信号和正极性数据信号。
在图3B的示例中，例如第N个图像帧的液晶分子的极性分布例如为图2C的示例。对于在像素阵列中排在第i行的子像素(第一行子像素的示例)，在为第一行子像素提供的第一栅极信号G(i)的开启期间(即，栅极信号G(i)处于高电平期间)，每条数据线依次为第一行相邻列的第一子像素和第二子像素分别提供负极性数据信号和正极性数据信号。例如，多条数据线先向奇数行的子像素提供负极性数据信号，再向偶数行的子像素提供正极性数据信号，并且向奇数行的子像素提供负极性数据信号比向偶数行的子像素提供正极性数据信号的时间长度短。
如图3B所示，第一栅极信号G(i)的开启期间包括第一子开启期间Tkq1和第二子开启期间Tkq2。第一子开启期间Tkq1的时间长度大于第二子开启期间Tkq2的时间长度。在第二子开启期间Tkq2内，多条数据线分别向奇数行的子像素提供负极性数据信号，在第一子开启期间Tkq1内，多条数据线分别向偶数行的子像素提供正极性数据信号。在图3B的示例中，例如第二子开启期间Tkq2早于第一子开启期间Tkq1。在另外一些实施例中，第二子开启期间Tkq2也可以晚于第一子开启期间Tkq1。
在第一行子像素关闭后，第二行子像素开启。第二行子像素例如可以是与第一行子像素相邻行或者不相邻行的子像素。例如，为第二行子像素的第二栅极信号G(i+1)处于开启期间，使得第二行子像素开启，从而多条数据线向第二行子像素分别提供负极性数据信号和正极性数据信号。多条数据线向第二行子像素分别提供负极性数据信号和正极性数据信号的方式与向第一行子像素分别提供负极性数据信号和正极性数据信号的方式相同，在此不再赘述。
例如，图3C为第N+1图像帧的时序信号图。例如，第N+1图像帧的液晶分子的极性分布例如为图2D的示例。对于在像素阵列中排在第i行的子像素(第一行子像素的示例)，在为第一行子像素提供的栅极信号G(i)的开启期间(即，栅极信号G(i)处于高电平期间)，每条数据线依次为第一行相邻列的第一子像素和第二子像素分别提供正极性数据信号和负极性数据信号。例如，多条数据线先向奇数行的子像素提供正极性数据信号，再向偶数行的子像素提供负极性数据信号。
第一栅极信号的开启期间包括第一子开启期间Tkq1和第二子开启期间Tkq2。第一子开启期间Tkq1的时间长度大于第二子开启期间Tkq2的时间长度。在第一子开启期间Tkq1内，多条数据线分别向奇数行的子像素提供正极性数据信号，在第二子开启期间Tkq2内，多条数据线分别向偶数行的子像素提供负极性数据信号。在图3C的示例中，例如第二子开启期间Tkq2晚于第一子开启期间Tkq1。在另外一些实施例中，第二子开启期间Tkq2也可以早于第一子开启期间Tkq1。
类似地，在第一行子像素关闭后，第二行子像素开启。第二行子像素例如可以是与第一行子像素相邻行或者不相邻行的子像素。例如，为第二行子像素的第二栅极信号G(i+1)处于开启期间，使得第二行子像素开启，从而多条数据线向第二行子像素分别提供负极性数据信号和正极性数据信号。
该像素驱动架构通过一条数据线向相邻列的两个子像素(即，1：2控制)提供数据信号，能够减少COF使用数量，同时也变相的提高了绑定良率，降低成本，并且该驱动架构更容易实现第一写入时间长度和第二写入时间长度的控制。
图4示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一种像素驱动架构的部分示意图。
如图4所示，液晶显示面板中每个子像素包括像素电极和像素开关元件，关于像素电极和像素开关元件等的描述请参考图1A和图1B，但并非限于图1A和图1B所示的情形。
在该示例中，每条数据线为相邻两列子像素提供数据信号。例如，数据线S1为第一列子像素和第二列子像素提供数据信号。第一列子像素是指像素阵列中的任选的一行子像素，第二列子像素是和第一列子像素是相邻的子像素。例如，第一列子像素为子像素Q11所在的列，第二列子像素为子像素Q12所在的列。
需要说明的是，虽然图4中仅示出了数据线S1与两列子像素的连接关系，但是并不意味中该像素驱动架构只包括数据线S1和这两列子像素，实际上，像素驱动架构通常包括多条数据线和多列子像素，其他数据线和其他列的子像素的排布与图4所示出的部分类似，不再赘述。
如图4所示，每个子像素除了像素开关元件之外还可以包括复用切换开关元件。例如，子像素Q11包括像素开关元件T11-1和复用切换开关元件T11-2，子像素Q12包括像素开关元件T12-1和复用切换开关元件T12-2。
每条数据线通过第一复用切换开关元件将正极性数据信号提供到第一子像素的像素电极，通过第二复用切换开关元件将负极性数据信号提供到第二子像素的像素电极。
例如，子像素Q11的液晶分子为正极性，则数据线S1通过复用切换开关元件T11-2将正极性数据信号提供到子像素Q11的像素开关元件T11-1的源极，从而将正极性数据信号提供到子像素Q11的像素电极。子像素Q12的液晶分子为负极性，则数据线S1通过复用切换开关元件T12-2将负极性数据信号提供到子像素Q12的像素开关元件T12-1的源极，从而将负极性数据信号提供到子像素Q12的像素电极。复用切换开关元件T11-2和复用切换开关元件T12-2分别为第一复用切换开关元件和第二复用切换开关元件的示例。在本公开的一些实施例中，在子像素中的另一开关元件例如可以是薄膜晶体管，或者其他类型的开关元件。例如，第一复用切换开关元件、第二复用切换开关元件和像素开关元件均为薄膜晶体管。
如图4所示，复用切换开关元件T11-2与控制线VDDODD连接，以接收控制线VDDODD提供的第一控制信号，复用切换开关元件T11-2配置为响应第一控制信号的控制以开启和 关闭。复用切换开关元件T12-2与控制线VDDEVEN连接，以接收控制线VDDEVEN提供的第二控制信号，复用切换开关元件T12-2配置为响应第二控制信号的控制以开启和关闭。
例如，在数据线S1提供正极性数据信号时，控制线VDDODD提供的第一控制信号使得复用切换开关元件T11-2开启，从而使得正极性数据信号提供至像素开关元件T11-1的像素电极，控制线VDDEVEN提供的第二控制信号使得复用切换开关元件T12-2关闭，从而使得正极性数据信号无法提供至复用切换开关元件T12-1的像素电极。
例如，在数据线S1提供负极性数据信号时，控制线VDDODD提供的第一控制信号使得复用切换开关元件T11-2关闭，从而使得负极性数据信号无法提供至像素开关元件T11-1的像素电极，控制线VDDEVEN提供的第二控制信号使得复用切换开关元件T12-2开启，从而使得负极性数据信号提供至复用切换开关元件T12-1的像素电极。
需要说明的是，本公开的上述实施例仅以数据线S1、子像素P11和子像素P12为示例来说明本公开提供的实施例，对本公开不具有限定作为，像素阵列中的其他数据线以及其他子像素被执行类似于数据线S1、子像素P11和子像素P12的驱动方法，不再赘述。
又例如，当某个图像帧中子像素Q11中的液晶分子为负极性且子像素Q12的液晶分子为正极性时，在数据线S1提供负极性信号时，复用切换开关元件T11-2开启，在数据线S1提供正极性信号时，复用切换开关元件T12-2关闭。
该实施例通过第一复用切换开关元件和第二复用切换开关元件实现在第一开启期间和第二开启期间是否向子像素写入数据信号，实现了液晶分子的交流驱动，并且通过调整第二开启期间Tkq2与第一开启期间Tkq1的时间比，可达到减少第二开启期间Tkq2(负极性充电时间长度)，增加第一开启期间Tkq1(正极性充电时间长度)，从而调节正负极性充电时间，使像素电压达到正负极性平衡，从而提高显示面板的均匀性，提升画质。
第一子开启期间和第二子开启期间分别与第一复用切换开关元件的开启时间段和第二复用切换开关元件的开启时间段相同。例如，在子开启期间Tkq1，复用切换开关元件T11-2开启；在子开启期间Tkq2复用切换开关元件T12-2开启。
图5A示出了本公开至少一个实施例提供的第N图像帧的时序信号图；图5B示出了本公开至少一个实施例提供的第N+1图像帧的时序信号图。
如图5A所示，对于第N图像帧，多行子像素的栅极信号依次处于开启状态。例如，当第一行子像素的第一栅极信号G(i)开启时，奇数列的子像素的液晶分子为负极性，偶数列的子像素的液晶分子为正极性。相邻列连接的数据线依次向奇数列的子像素提供负极性数据信号，向偶数列的子像素提供正极性数据信号。即，第N图像帧的数据信号的极性分布如图2C所示。
如图5A所示，在子开启期间Tkq1与偶数列的复用切换开关元件的开启时间段(即，VDDEVEN信号为高电平的时间段)相同，在子开启期间Tkq2与奇数列的复用切换开关元件的开启时间段(即，VDDODD信号为高电平的时间段)相同。
如图5B所示，对于第N+1图像帧，多行子像素的栅极信号依次处于开启状态。例如， 当第一行子像素的第一栅极信号G(i)开启时，奇数列的子像素的液晶分子为正极性，偶数列的子像素的液晶分子为负极性。相邻列连接的数据线依次向奇数列的子像素提供正极性数据信号，向偶数列的子像素提供负极性数据信号。即，第N+1图像帧的数据信号的极性分布如图2D所示。
如图5B所示，子开启期间Tkq1与奇数列的复用切换开关元件的开启时间段(即，VDDODD信号为高电平的时间段)相同，子开启期间Tkq2与偶数列的复用切换开关元件的开启时间段(即，VDDEVEN信号为高电平的时间段)相同。
图6示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图。
如图6所示，第一复用切换开关元件和第二复用切换开关元件设置在液晶显示面板的周边。液晶显示面板的周边例如为液晶显示面板的控制区。多个子像素设置在液晶显示面板的显示区。例如，复用切换开关元件TFT1和复用切换开关元件TFT2设置在液晶显示面板周边的控制区。复用切换开关元件TFT1和复用切换开关元件TFT2分别为第一复用切换开关元件和第二复用切换开关元件的示例。例如，在第一时刻，数据线SD1分别通过复用切换开关元件TFT1和复用切换开关元件TFT2将正极性数据信号和负极性数据信号提供到子像素W11和子像素W12，或者，在第二时刻，数据线SD1分别通过复用切换开关元件TFT1和复用切换开关元件TFT2将正极性数据信号和正极性数据信号提供到子像素W11和子像素W12。子像素W11和子像素W12分别为第一子像素和第二子像素的示例。
如图6所示，子像素W11所在的一列子像素共享复用切换开关元件TFT1，子像素W12所在的一列子像素共享复用切换开关元件TFT2。
液晶显示面板中其他的数据线与相邻的两个子像素的连接方式与数据线S1和子像素P11和子像素P12的连接方式相同，不再赘述。每个子像素的结构与前述实施例中子像素的结构类似，不再赘述。
该实施例增加由VDDODD信号线和VDDEVEN信号线提供的电压控制的第一复用切换开关元件和第二复用切换开关元件，以及在控制区设置第一复用切换开关元件和第二复用切换开关元件，减少了第一复用切换开关元件和第二复用切换开关元件的使用数量，并且使复用切换开关元件设置与控制区而非显示区，能够进一步消除增加开关元件对像素开口率的影响。
图7示出了本公开至少一个实施例提供的应用驱动方法的液晶显示面板的另一像素驱动架构示意图。
例如，该像素驱动架构包括多个子像素P’11、子像素P’12、……、P’(nm)，每条数据线分别为处于同一行相邻两列的第一子像素和第二子像素提供正极性数据信号和负极性数据信号。例如，在某个图像帧，数据线S’1为子像素P’11和子像素P’12分别提供正极性数据信号和负极性数据信号。子像素P’11和子像素P’12分别为第一子像素和第二子像素的示例。
如图7所示，每个子像素可以包括复用切换开关元件。例如，子像素P’11包括复用切换开关元件T’11-1，子像素P’12包括复用切换开关元件T’12-1。
在图7的示例中，除了在每个子像素中添加了复用切换开关元件之外，每个子像素的结构与前述实施例(例如，图1A和图1B)相同，不再赘述。例如，开关元件放置于像素开关元件和像素电极之间。
每条数据线通过第一复用切换开关元件将正极性数据信号提供到第一子像素的像素电极，通过第二复用切换开关元件将负极性数据信号提供到第二子像素的像素电极。复用切换开关元件T’11-1和复用切换开关元件T’12-1例如分别为第一复用切换开关元件和第二复用切换开关元件的示例。例如，在某个图像帧，数据线S1通过复用切换开关元件T’11-1将正极性数据信号提供到子像素P’11的像素电极，通过复用切换开关元件T’12-1将负极性数据信号提供到子像素P’12的像素电极。在另一个图像帧，数据线S’1通过复用切换开关元件T’11-1将负极性数据信号提供到子像素P’11的像素电极，通过复用切换开关元件T’12-1将正极性数据信号提供到子像素P’12的像素电极。
如图7所示，第一复用切换开关元件设置在第一子像素内，第二复用切换开关元件设置在第二子像素内。例如，复用切换开关元件T’11-1设置在子像素P’11内，复用切换开关元件T’12-1设置在子像素P’12内。
在本公开的一些实施例中，如图7所示，每个子像素还包括像素开关元件，像素开关元件连接到对应的栅线以接收对应的栅线提供的栅极信号。例如，子像素P’11包括像素开关元件T’11-2，像素开关元件T’11-2连接到栅线G1，以接收栅线G1提供的栅极信号。子像素P’12包括像素开关元件T’12-2，像素开关元件T’12-2也连接到栅线G1，以接收栅线G1提供的栅极信号。
如图7所示，第一子像素中的像素开关元件与第一复用切换开关元件串联在数据线和像素电极之间，第二子像素中的像素开关元件与第二复用切换开关元件串联在数据线和像素电极之间。例如，子像素P’11的像素开关元件T’11-2和复用切换开关元件T’11-1串联在数据线S1和像素电极之间。子像素P’12中的像素开关元件T’12-2和复用切换开关元件T’12-1串联在数据线和像素电极之间。
该像素驱动结构在每个子像素中设置用于实现数据线复用的复用切换开关元件，便于对每个子像素的单独控制。
本公开的另一方面提供了一种液晶显示面板。该液晶显示面板包括像素阵列。像素阵列包括多条栅线、多条数据线以及多个子像素，多个子像素排列为多行多列，每条栅线为一行子像素提供栅极信号，每条数据线为相邻两列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线，多行子像素中的第一行子像素对应的第一栅线配置为向第一行子像素提供第一栅极信号，第一栅极信号包括开启期间和关闭期间，用于控制第一行子像素分别开启和关闭，每条数据线配置为在第一栅极信号处于开启期间分别为相邻两列中的第一子像素提供正极性数据信号和为相邻两列中的第二子像素提供负极性数据信号，在第一栅 极信号处于开启期间，每条数据线配置为负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度，第一栅极信号的开启期间包括第一子开启期间和第二子开启期间，在第一栅极信号处于开启期间，每条数据线配置为负极性数据信号的第一写入时间长度小于正极性数据信号的第二写入时间长度，包括：正极性数据信号在第一子开启期间施加至第一子像素，负极性数据信号在第二子开启期间施加至第二子像素，第一子开启期间的时间长度大于第二子开启期间的时间长度。该液晶显示面板能够提升显示面板的画质和良率，缓解液晶显示面板容易出现显示不均、残像，甚至负极性数据错冲等问题。
在本公开的一些实施例中，每个子像素还包括像素电极，每条数据线通过第一复用切换开关元件与第一子像素的像素电极电连接，通过第二复用切换开关元件与第二子像素的像素电极电连接。
在本公开的一些实施例中，第一复用切换开关元件与第一控制线连接，以接收第一控制线提供的第一控制信号，第一复用切换开关元件配置为响应第一控制信号的控制以开启和关闭，第二复用切换开关元件与第二控制线连接，以接收第二控制线提供的第二控制信号，第二复用切换开关元件配置为响应第二控制信号的控制以开启和关闭。
在本公开的一些实施例中，第一复用切换开关元件和第二复用切换开关元件设置在液晶显示面板的周边，第一子像素所在的一列子像素共享第一复用切换开关元件，第二子像素所在的一列子像素共享第二复用切换开关元件。
在本公开的一些实施例中，第一复用切换开关元件设置在第一子像素内，第二复用切换开关元件设置在第二子像素内。
在本公开的一些实施例中，每个子像素还包括像素开关元件，像素开关元件连接到对应的栅线以接收对应的栅线提供的栅极信号，
第一子像素中的像素开关元件与第一复用切换开关元件串联在数据线和像素电极之间，
第二子像素中的像素开关元件与第二复用切换开关元件串联在数据线和像素电极之间。
本公开的上述实施例提供的液晶显示面板可以是上文所描述的任一驱动方法示出的液晶显示面板的像素驱动架构，例如图2B、图3A图6和图7所示的像素驱动架构。关于液晶显示面板的具体功能和部件可以参考关于驱动方法的相关描述，此处不再赘述。例如图2B、图3A图6和图7所示的液晶显示面板的组件和结构只是示例性的，而非限制性的，根据需要，该液晶显示面板还可以包括其他组件和结构。
图8A～图8D示出了本公开至少一个实施例提供的应用于驱动方法的液晶显示面板的另一些示例性像素驱动架构。
例如，在图8A的像素驱动架构中，每条栅线(例如，栅线1～栅线4)与一行子像素电连接，同一列的相邻行的子像素分别连接两条不同的数据线。例如，位于第一行的红色子像素与数据线1连接，位于第二行的红色子像素与数据线2连接。图8A所示的像素驱动架构称为单栅线+Z架构。
例如，在图8B的像素驱动架构中，包括多条栅线和多条数据线。多条栅线例如可以包 括栅线Gate1～栅线Gate8，以及多条数据线例如可以包括Data1～Data8。每行子像素连接两条栅线，例如排在第一行的子像素连接栅线Gate1和栅线Gate2。同一行相邻列的子像素分别连接不同的两条栅线。例如，第一列的红色子像素与Gate1连接，第二列的绿色子像素与Gate2连接。
在图8B的像素驱动架构中，相邻的两个子像素连接到同一数据线，同一列的相邻行的子像素分别连接两条不同的数据线。例如，位于第一行的红色子像素与数据线Data1连接，位于第二行的红色子像素与数据线Data2连接。以第一行为例，位于第一列的红色子像素与数据线Data1连接，位于第二列的绿色子像素也与数据线Data1连接。
例如，每一行子像素的排布为红光子像素、绿光子像素、蓝光子像素、红光子像素、绿光子像素、蓝光子像素，并且按照该规律循环。如图8B所示，第一个红光子像素连接栅线Gate1、第一个绿光子像素连接栅线Gate2、第一个蓝光子像素连接栅线Gate1、第二个红光子像素连接栅线Gate2、第二个绿光子像素连接栅线Gate1、第二个蓝光子像素连接栅线Gate2。即，在图8B的像素驱动架构中，同一行中存在发同一颜色的光的多个子像素分别连接不同的两条栅线。图8A所示的像素驱动架构称为双栅线+Z-2架构。
例如，在图8C的像素驱动架构中，每行子像素连接两条栅线，例如排在第一行的子像素连接栅线Gate1和栅线Gate2。在图8C的像素驱动架构中，相邻的两个子像素连接到同一数据线，同一列的相邻行的子像素分别连接两条不同的数据线。例如，位于第一行的红色子像素与数据线Data1连接，位于第二行的红色子像素与数据线Data2连接。以第一行为例，位于第一列的红色子像素与数据线Data1连接，位于第二列的绿色子像素也与数据线Data1连接。
在图8C的像素驱动架构中，同一行中发相同颜色的光的子像素连接同一条栅线。例如，所有的红色子像素连接栅线Gate1，所有的绿色子像素连接栅线Gate2。图8C所示的像素驱动架构称为双栅线+Z-1架构。
例如，在图8D的像素驱动架构中，包括多条栅线和多条数据线。多条栅线例如可以包括栅线1～栅线4，以及多条数据线例如可以包括Data1～Data6。每行各连接一条栅线，同一列子像素连接同一数据线。
图8A～图8D的“+”表示正极性数据信号，“-”表示负极性数据信号。需要说明的是，图8A～图8D的所示的架构仅为一种示例，对本公开不具有限定作用，例如液晶显示面板中的像素阵列可以包括更多的栅线和数据线以及子像素单元，以及正极性数据信号和负极性数据信号也可以有别于图8A～图8D的示例。
本公开提供的上述实施例中的驱动方法，可广泛应用于各自液晶显示面板，如图8A～图8D的架构。
本公开的实施例通过调整正负极性的写入时间长度来改善因正负极性下薄膜晶体管输出特性不同导致充电时间差异造成的不良(例如显示不均，残像等问题)，从而进一步提高显示装置的画质及品质。
本发明至少一实施例还提供了一种显示装置，包括本公开任一实施例提供的液晶显示面板，例如，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种液晶显示面板的驱动方法，其中，所述液晶显示面板包括像素阵列，所述像素阵列包括多条栅线、多条数据线以及多个子像素，所述多个子像素排列为多行多列，每条栅线为至少一行子像素提供栅极信号，每条数据线为至少一列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线，
    所述驱动方法包括：
    向多行子像素中的第一行子像素对应的第一栅线提供第一栅极信号，其中，所述第一栅极信号包括开启期间和关闭期间，用于控制所述第一行子像素分别开启和关闭；
    在所述第一栅极信号处于所述开启期间，通过所述多条数据线向所述第一行子像素的多个子像素分别写入多个第一数据信号，其中，所述多个第一数据信号包括正极性数据信号和负极性数据信号，
    在所述第一栅极信号处于所述开启期间，所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度。
  2. 根据权利要求1所述的驱动方法，其中，所述负极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点的延迟时间为第一时间长度，
    所述正极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点的延迟时间为第二时间长度，
    所述第一时间长度大于所述第二时间长度，使得在所述第一栅极信号处于所述开启期间，所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度。
  3. 根据权利要求2所述的驱动方法，其中，所述负极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点和所述正极性数据信号相对于所述第一栅极信号对应的所述开启期间的起始时间点相同或不同。
  4. 根据权利要求2或3所述的驱动方法，其中，所述第一栅极信号还包括位于相邻的开启期间和关闭期间之间的过渡期间，
    所述第一时间长度比所述第二时间长度长预设时间长度，
    所述预设时间长度为在所述第一栅极信号的所述过渡期间，所述负极性数据信号的写入时间长度与所述正极性数据信号的写入时间长度之间的差值。
  5. 根据权利要求1或2所述的驱动方法，其中，所述每条数据线为相邻两列子像素提供数据信号，
    在所述第一栅极信号处于所述开启期间，所述每条数据线分别为处于同一行相邻两列的第一子像素和第二子像素提供正极性数据信号和负极性数据信号，
    所述第一栅极信号的开启期间包括第一子开启期间和第二子开启期间，
    所述正极性数据信号在所述第一子开启期间施加至所述第一子像素，所述负极性数据 信号在所述第二子开启期间施加至所述第二子像素，
    所述第一子开启期间的时间长度大于所述第二子开启期间的时间长度。
  6. 根据权利要求5所述的驱动方法，其中，所述每个子像素还包括像素电极，
    所述每条数据线通过第一复用切换开关元件将所述正极性数据信号提供到所述第一子像素的像素电极，通过第二复用切换开关元件将所述负极性数据信号提供到所述第二子像素的像素电极。
  7. 根据权利要求6所述的驱动方法，其中，所述第一复用切换开关元件与第一控制线连接，以接收所述第一控制线提供的第一控制信号，所述第一复用切换开关元件配置为响应所述第一控制信号的控制以开启和关闭，
    所述第二复用切换开关元件与第二控制线连接，以接收所述第二控制线提供的第二控制信号，所述第二复用切换开关元件配置为响应所述第二控制信号的控制以开启和关闭。
  8. 根据权利要求7所述的驱动方法，其中，所述第一子开启期间和所述第二子开启期间分别与所述第一复用切换开关元件的开启时间段和所述第二复用切换开关元件的开启时间段相同。
  9. 根据权利要求6～8任一项所述的驱动方法，其中，所述第一复用切换开关元件和所述第二复用切换开关元件设置在所述液晶显示面板的周边，
    所述第一子像素所在的一列子像素共享所述第一复用切换开关元件，
    所述第二子像素所在的一列子像素共享所述第二复用切换开关元件。
  10. 根据权利要求6～8任一项所述的驱动方法，其中，所述第一复用切换开关元件设置在所述第一子像素内，
    所述第二复用切换开关元件设置在第二子像素内。
  11. 根据权利要求10所述的驱动方法，其中，所述每个子像素还包括像素开关元件，所述像素开关元件连接到对应的栅线以接收所述对应的栅线提供的栅极信号，
    所述第一子像素中的像素开关元件与所述第一复用切换开关元件串联在所述数据线和所述像素电极之间，
    所述第二子像素中的像素开关元件与所述第二复用切换开关元件串联在所述数据线和所述像素电极之间。
  12. 一种液晶显示面板，包括像素阵列，其中，所述像素阵列包括多条栅线、多条数据线以及多个子像素，所述多个子像素排列为多行多列，每条栅线为一行子像素提供栅极信号，每条数据线为相邻两列子像素提供数据信号，每个子像素连接到对应的栅线和对应的数据线，
    多行子像素中的第一行子像素对应的第一栅线配置为向所述第一行子像素提供第一栅极信号，其中，所述第一栅极信号包括开启期间和关闭期间，用于控制所述第一行子像素分别开启和关闭，
    所述每条数据线配置为在所述第一栅极信号处于所述开启期间分别为相邻两列中的第 一子像素提供正极性数据信号和为相邻两列中的第二子像素提供负极性数据信号，
    其中，在所述第一栅极信号处于所述开启期间，所述每条数据线配置为所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度，
    所述第一栅极信号的开启期间包括第一子开启期间和第二子开启期间，
    在所述第一栅极信号处于所述开启期间，所述每条数据线配置为所述负极性数据信号的第一写入时间长度小于所述正极性数据信号的第二写入时间长度，包括：
    所述正极性数据信号在所述第一子开启期间施加至所述第一子像素，所述负极性数据信号在所述第二子开启期间施加至所述第二子像素，所述第一子开启期间的时间长度大于所述第二子开启期间的时间长度。
  13. 根据权利要求12所述的液晶显示面板，其中，所述每个子像素还包括像素电极，
    所述每条数据线通过第一复用切换开关元件与所述第一子像素的像素电极电连接，通过第二复用切换开关元件与所述第二子像素的像素电极电连接。
  14. 根据权利要求13所述的液晶显示面板，其中，所述第一复用切换开关元件与第一控制线连接，以接收第一控制线提供的第一控制信号，所述第一复用切换开关元件配置为响应所述第一控制信号的控制以开启和关闭，
    所述第二复用切换开关元件与第二控制线连接，以接收第二控制线提供的第二控制信号，所述第二复用切换开关元件配置为响应所述第二控制信号的控制以开启和关闭。
  15. 根据权利要求13或14所述的液晶显示面板，其中，所述第一复用切换开关元件和所述第二复用切换开关元件设置在所述液晶显示面板的周边，所述第一子像素所在的一列子像素共享所述第一复用切换开关元件，所述第二子像素所在的一列子像素共享所述第二复用切换开关元件。
  16. 根据权利要求13或14所述的液晶显示面板，其中，所述第一复用切换开关元件设置在所述第一子像素内，所述第二复用切换开关元件设置在第二子像素内。
  17. 根据权利要求15所述的液晶显示面板，所述每个子像素还包括像素开关元件，所述像素开关元件连接到对应的栅线以接收所述对应的栅线提供的栅极信号，
    所述第一子像素中的像素开关元件与所述第一复用切换开关元件串联在所述数据线和所述像素电极之间，
    所述第二子像素中的像素开关元件与所述第二复用切换开关元件串联在所述数据线和所述像素电极之间。
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