WO2024037167A1 - 太阳能电池及其制备方法和光伏组件 - Google Patents

太阳能电池及其制备方法和光伏组件 Download PDF

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Publication number
WO2024037167A1
WO2024037167A1 PCT/CN2023/100504 CN2023100504W WO2024037167A1 WO 2024037167 A1 WO2024037167 A1 WO 2024037167A1 CN 2023100504 W CN2023100504 W CN 2023100504W WO 2024037167 A1 WO2024037167 A1 WO 2024037167A1
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layer
passivation
contact structure
silicon substrate
phosphorus
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PCT/CN2023/100504
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English (en)
French (fr)
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武禄
陈皓
杨苗
曲铭浩
徐希翔
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隆基绿能科技股份有限公司
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Publication of WO2024037167A1 publication Critical patent/WO2024037167A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination

Definitions

  • the present invention relates to the field of photovoltaic technology, and in particular to a solar cell, a preparation method thereof and a photovoltaic module.
  • the passivation contact structure including a stacked tunnel layer and a doped polysilicon layer can provide excellent silicon interface passivation and contact passivation performance, and therefore is widely used in solar cells.
  • the present invention provides a solar cell, a preparation method thereof and a photovoltaic component, aiming to solve the problem of severe contact recombination and/or parasitic absorption on the light-facing surface of existing solar cells with passivated contact structures, reducing the The open circuit voltage, short circuit current, fill factor, and photoelectric conversion efficiency of solar cells are solved.
  • a first aspect of the invention provides a solar cell, including:
  • Silicon substrate front passivation antireflection layer, local passivation contact structure, stacked back intrinsic passivation layer and back doped layer, front electrode, and back electrode;
  • the partially passivated contact structure and the front passivation anti-reflection layer jointly cover the light-facing surface of the silicon substrate and are along a direction perpendicular to the stacking direction of the back doped layer and the back electrode,
  • the local passivation contact structure and the front-side passivation anti-reflection layer are alternately distributed on the light-facing surface of the silicon substrate;
  • the stacked back intrinsic passivation layer and back doped layer are located on the backlight surface of the silicon substrate;
  • the front electrode is located on the locally passivated contact structure
  • the back electrode is electrically connected to the back doped layer.
  • the partially passivated contact structure in contact with the front electrode can effectively suppress contact recombination and surface recombination, ensuring a higher open circuit voltage.
  • the uncovered part of the front electrode is not doped, and the silicon substrate is covered by the front passivation anti-reflection layer, which can effectively reduce the parasitic absorption of light, achieve a good passivation and anti-reflection effect, and improve the short-circuit current and Photoelectric conversion efficiency.
  • the partially passivated contact structure is only located in the part covered by the front electrode, which can sacrifice part of the passivation performance to improve the transmission performance.
  • the partially passivated contact structure only needs to focus on its electrical properties, which broadens the process window for preparing the passivated contact structure. .
  • the backlight surface of the silicon substrate is a heterojunction structure, which can achieve better passivation and contact performance.
  • the front-side passivation and anti-reflection layer includes a stacked front-side passivation layer and a front-side anti-reflection layer;
  • the material of the front passivation layer is selected from: intrinsic amorphous silicon; the material of the front anti-reflection layer is selected from: silicon nitride, silicon carbide, titanium oxide, silicon oxide, magnesium fluoride, silicon oxynitride, TCO at least one of them.
  • the front-side passivation and anti-reflection layer includes a stacked front-side passivation layer and a front-side anti-reflection layer;
  • the material of the front passivation layer is selected from: at least one of phosphosilicate glass, silicon oxide, phosphorus oxide, aluminum oxide and phosphorus oxide;
  • the material of the front anti-reflection layer is selected from at least one of silicon nitride, silicon carbide, titanium oxide, silicon oxide, magnesium fluoride, silicon oxynitride, and TCO.
  • the projected area of the partially passivated contact structure on the light-facing surface of the silicon substrate is larger than the projected area of the front-side electrode on the light-facing surface of the silicon substrate, and the front-side passivation structure
  • the antireflection layer also covers areas of the partially passivated contact structure that are not covered by the front electrode.
  • the projected area of the partially passivated contact structure on the light-facing surface of the silicon substrate is equal to the projected area of the front-side electrode on the light-facing surface of the silicon substrate, along the In the stacking direction of the back doped layer and the back electrode, the front passivation anti-reflection layer is flush with the local passivation contact structure.
  • the partially passivated contact structure includes: a stacked tunnel layer and a doped polysilicon layer.
  • the doped polysilicon layer also contains carbon element and/or oxygen element.
  • the solar cell further includes: a back TCO layer located on the back doped layer, and the back electrode is located on the back TCO layer.
  • a second aspect of the invention provides a method for preparing a solar cell, including:
  • a front electrode is formed on the locally passivated contact structure, and a back electrode is formed electrically connected to the back doped layer.
  • forming a front passivation anti-reflection layer on the exposed light-facing surface of the silicon substrate includes:
  • a front passivation anti-reflection layer is formed on the partially passivated contact structure and the exposed light-facing surface of the silicon substrate, and a second opening is formed in a local area of the front anti-reflection layer, so that the partially passivated contact The structure is at least partially exposed;
  • the forming a front electrode on the partially passivated contact structure and forming a back electrode electrically connected to the back doped layer includes:
  • a front electrode is formed on the exposed partially passivated contact structure, and a back electrode electrically connected to the back doped layer is formed.
  • forming a passivation contact structure on the light-facing surface of the silicon substrate includes:
  • An intrinsic polysilicon layer is deposited on the tunnel layer, and the intrinsic polysilicon layer is subjected to a phosphorus-doping treatment to form a phosphorus-doped polysilicon layer. During the phosphorus-doping treatment, a front-side phosphorus layer is formed on the phosphorus-doped polysilicon layer.
  • Silica glass layer; the thickness of the front phosphosilicate glass layer is 10 to 110 nm.
  • forming a passivation contact structure on the light-facing surface of the silicon substrate includes:
  • In-situ phosphorus doping is performed on the tunneling layer and annealed to form a phosphorus-doped polysilicon layer.
  • the phosphorus-doped polysilicon layer is thermally oxidized in an oxygen atmosphere to form Front-side phosphosilicate glass layer; the thickness of the front-side phosphosilicate glass layer is 10 to 110 nm.
  • the method before forming the first opening on the passivation contact structure, the method further includes:
  • Forming the first opening on the passivation contact structure includes:
  • the method before forming the first opening on the passivation contact structure, the method further includes:
  • a patterned mask material is screen-printed on a local area of the front phosphosilicate glass layer and solidified to obtain a patterned mask; or a pattern is printed on a local area of the front phosphosilicate glass layer by inkjet printing. Chemicalize the mask material to obtain a patterned mask;
  • wet processing is used to etch the front phosphorus silicate glass layer into a phosphorus silicate glass pattern consistent with the shape of the patterned mask, so that part of the phosphorus-doped polysilicon layer Bare, remove the patterned mask;
  • Forming the first opening on the passivation contact structure includes:
  • the exposed phosphorus-doped polysilicon layer is alkali-washed to form the first opening on the tunneling layer and the phosphorus-doped polysilicon layer.
  • the method before forming the first opening on the passivation contact structure, the method further includes:
  • Forming the first opening on the passivation contact structure includes:
  • the exposed passivation contact structure is alkali washed to form the first opening in the area of the passivation contact structure corresponding to the fourth opening.
  • the method before forming the first opening on the passivation contact structure, the method further includes:
  • a patterned mask material is screen-printed and solidified to obtain a patterned mask. film; or, inkjet printing a patterned mask material on a local area of the silicon nitride layer to obtain a patterned mask;
  • wet processing is used to etch the silicon nitride layer into a silicon nitride pattern consistent with the shape of the patterned mask, so that the passivated contact structure part, removing the patterned mask;
  • Forming the first opening on the passivation contact structure includes:
  • the exposed passivation contact structure is alkali washed to form the first opening on the passivation contact structure.
  • the material of the patterned mask is selected from: paraffin.
  • the method before forming a back electrode electrically connected to the back doped layer, the method further includes:
  • the formation of a back electrode electrically connected to the back doped layer includes:
  • the back electrode is formed on the back TCO layer.
  • a third aspect of the present invention provides a photovoltaic module, including a battery string formed by a plurality of any of the aforementioned solar cells connected in series.
  • Figure 1 shows a schematic structural diagram of a first solar cell in an embodiment of the present invention
  • Figure 2 shows a schematic structural diagram of a third solar cell in an embodiment of the present invention
  • Figure 3 shows a step flow chart of a solar cell in an embodiment of the present invention
  • Figure 4 shows a schematic structural diagram of the preparation process of the first solar cell in the embodiment of the present invention
  • Figure 5 shows a schematic structural diagram of the preparation process of the second solar cell in the embodiment of the present invention.
  • Figure 6 shows a schematic structural diagram of the preparation process of the third solar cell in an embodiment of the present invention
  • Figure 7 shows a schematic structural diagram of the preparation process of the fourth solar cell in an embodiment of the present invention.
  • Figure 8 shows a schematic structural diagram of the preparation process of the fifth solar cell in an embodiment of the present invention.
  • Figure 9 shows a schematic structural diagram of the preparation process of the sixth solar cell in the embodiment of the present invention.
  • Figure 10 shows a schematic structural diagram of the preparation process of the seventh solar cell in the embodiment of the present invention.
  • Figure 11 shows a schematic structural diagram of the preparation process of the eighth solar cell in the embodiment of the present invention.
  • Figure 12 shows a schematic structural diagram of the preparation process of the ninth solar cell in the embodiment of the present invention.
  • Figure 13 shows a schematic structural diagram of the preparation process of the tenth solar cell in the embodiment of the present invention.
  • Figure 14 shows a schematic structural diagram of the preparation process of the eleventh solar cell in the embodiment of the present invention.
  • Figure 15 shows a schematic structural diagram of the preparation process of the twelfth solar cell in the embodiment of the present invention
  • Figure 16 shows a schematic structural diagram of the preparation process of the thirteenth solar cell in the embodiment of the present invention.
  • Figure 17 shows a schematic structural diagram of the preparation process of the fourteenth solar cell in the embodiment of the present invention.
  • Figure 18 shows a schematic structural diagram of the preparation process of the fifteenth solar cell in the embodiment of the present invention.
  • Figure 19 shows a schematic structural diagram of the preparation process of the sixteenth solar cell in the embodiment of the present invention.
  • Figure 20 shows a schematic structural diagram of the preparation process of the seventeenth solar cell in the embodiment of the present invention.
  • 1-front electrode 2-front anti-reflection layer, 3-front passivation layer, 4-doped polysilicon layer or phosphorus-doped polysilicon layer, 5- Tunneling layer, 6-silicon substrate, 7-back intrinsic amorphous silicon passivation layer, 8-back doped layer, 9-back TCO layer, 10-back electrode, 11-PSG layer, 11-L-phosphorus silicon Glass Pattern, 13-Patterned Mask.
  • FIG. 1 shows a schematic structural diagram of a first solar cell in an embodiment of the present invention.
  • Figure 2 shows a schematic structural diagram of a second solar cell in an embodiment of the present invention.
  • the solar cell of the present invention includes: a silicon substrate 6, a front passivation antireflection layer, a local passivation contact structure, a stacked back intrinsic passivation layer 7 and a back doped layer 8, a front electrode 1, and a back electrode 10.
  • the local passivation contact structure and the front passivation anti-reflection layer jointly cover the light-facing surface of the silicon substrate 6 and are connected to the back doped layer 8 and In a direction perpendicular to the stacking direction of the back electrode 10 , the local passivation contact structure and the front passivation anti-reflection layer are alternately distributed on the light-facing surface of the silicon substrate 6 .
  • the stacking direction of the back doped layer 8 and the back electrode 10 is the up-down direction. Therefore, the direction perpendicular to the stacking direction of the back doped layer 8 and the back electrode 10 can be as shown in FIGS.
  • a locally passivated contact structure is formed at the contact part of the front electrode 1, which can effectively suppress contact recombination and surface recombination, reduce the contact resistance in the front contact area, and improve the open circuit voltage, short circuit current and photoelectric conversion efficiency of the solar cell.
  • locally passivated contact structures can effectively reduce parasitic absorption of light and improve the short-circuit current and photoelectric conversion efficiency of solar cells.
  • the uncovered part of the front electrode 1 is not doped, and the front passivation anti-reflection layer covers the silicon substrate 6, which has a good passivation and anti-reflection effect, can further reduce surface recombination and contact recombination, increase the short-circuit current density, and further Improve the short-circuit current, open-circuit voltage and photoelectric conversion efficiency of solar cells.
  • the partially passivated contact structure is only located in the part covered by the front electrode 1, which can sacrifice part of the passivation performance to improve the transmission performance.
  • the partially passivated contact structure only needs to pay attention to its electrical properties and does not need to pay attention to the optical properties, which broadens the scope of preparation of passivation.
  • the process window of the passivation contact structure expands the selection range of conductive materials in the front passivation contact structure. Compared with conductive materials with high transmittance, low transmittance conductive materials usually have lower costs and can reduce the cost of solar cells. production costs.
  • the stacked back intrinsic passivation layer 7 and the back doping layer 8 are located on the backlight surface of the silicon substrate 6.
  • the backlight surface of the silicon substrate 6 is a heterojunction structure, which achieves better performance.
  • the passivation and contact performance further improve the short-circuit current, open-circuit voltage and photoelectric conversion efficiency of solar cells.
  • the photoelectric conversion efficiency of the solar cell prepared by the present invention is about 1% abs higher than that of the TOPCon (Tunnel Oxide Passivated Contact, tunnel layer passivated contact) solar cell.
  • the open circuit voltage of solar cells is close to or greater than 740mV.
  • the short-circuit current density of solar cells increases by about 2mA/ cm2 .
  • the front passivation anti-reflection layer may include a front passivation layer 3 and a front anti-reflection layer 2 arranged in a stack.
  • the local passivation contact structure may include: a stacked doped polysilicon layer 4 and a tunneling layer 5 .
  • the silicon substrate 6 can be N-type single/polycrystalline silicon.
  • the front electrode 1, the doped polysilicon layer 4 and the tunneling layer 5 below form a local passivation contact structure of a majority carrier.
  • the front passivation layer 3 is superimposed on the front anti-reflection layer 2 to passivate the parts except the passivation contact area to reduce the recombination of carriers.
  • the front anti-reflection layer 2 also reduces the escape and reflection of light from the light-facing surface. role.
  • the back intrinsic amorphous silicon passivation layer 7 and the back doped layer 8 on the backlight surface of the silicon substrate 6 form a heterojunction structure, in which the back intrinsic amorphous silicon passivation layer 7 also plays a passivation role.
  • the back TCO layer 9 forms contact with the back doped layer 8 and helps the lateral transport of minority carriers.
  • the back electrode 10 contacts the back TCO layer 9 to draw out current.
  • Sunlight illuminates the light-facing surface of the solar cell shown in Figure 1 or Figure 2, and most of the light that illuminates the front electrode 1 is reflected back to the atmosphere. If the front electrode 1 is a regular triangle or trapezoid, most of the light is reflected to the adjacent In the area of the front electrode 1, the light irradiating the front anti-reflection layer 2 is refracted, and a small part may be absorbed, and enters the N-type silicon substrate 6 through the front passivation layer 3. Light excites a large number of majority carriers (electrons) and minority carriers (holes) in the N-type silicon substrate 6 . After the carriers are generated, they diffuse freely in the N-type silicon substrate 6 .
  • majority carriers electrons
  • holes minority carriers
  • the material and preparation method of the tunnel layer 5 are not specifically limited.
  • the tunnel layer 5 may be a tunnel oxide layer, and the tunnel oxide layer may be prepared by thermal oxidation or the like.
  • the area of the projection of the partially passivated contact structure on the light-facing surface of the silicon substrate 6 is larger than the area of the projection of the front-side electrode 1 on the light-facing surface of the silicon substrate 6 .
  • Front-side passivation The antireflection layer also covers the area in the local passivation contact structure that is not covered by the front electrode 1, that is, the front passivation layer 3, covering the silicon substrate 6 and the doped polysilicon layer 4, and the front electrode 1 penetrates the front passivation layer 3 and the front
  • the antireflection layer 2 is electrically connected to the doped polysilicon layer 4.
  • the front passivation layer 3 and the front antireflection layer 2 protect the local passivation contact structure, further improving the passivation contact structure. Passivation performance.
  • the area of the projection of the local passivation contact structure on the light-facing surface of the silicon substrate 6 is equal to the area of the projection of the front electrode 1 on the light-facing surface of the silicon substrate 6, along the In the stacking direction of the back doped layer 8 and the back electrode 10, the front passivation anti-reflection layer and the local passivation contact structure are evenly distributed. That is, the local passivation contact structure, the stacked front passivation layer 3 and the front anti-reflection layer 2 just cover the light-facing surface of the silicon substrate 6, and the front electrode 1 is disposed on the doped polysilicon layer 4.
  • the solar cell Various forms.
  • the material of the front passivation layer 3 may be selected from: at least one of PSG (Phospho Silicate Glass), silicon oxide, phosphorus oxide, aluminum oxide and phosphorus oxide.
  • PSG Phospho Silicate Glass
  • silicon oxide silicon oxide
  • phosphorus oxide aluminum oxide
  • phosphorus oxide aluminum oxide
  • phosphorus oxide silicon oxide
  • the above materials all have good passivation effects, which can further reduce surface recombination and further improve the open circuit voltage and photoelectric conversion efficiency of solar cells.
  • the material of the front passivation layer 3 can also be selected from: intrinsic amorphous silicon.
  • the above-mentioned intrinsic amorphous silicon has a good passivation effect and can further reduce surface recombination.
  • the material of the front anti-reflection layer 2 is selected from at least one of silicon nitride, silicon carbide, titanium oxide, silicon oxide, magnesium fluoride, silicon oxynitride, and TCO.
  • the above-mentioned materials have good anti-reflection effects, which can further reduce surface recombination and contact recombination, increase the short-circuit current density, and further improve the short-circuit current, open-circuit voltage and photoelectric conversion efficiency of solar cells.
  • the front anti-reflection layer 2 has a single-layer or laminated structure.
  • the structure of the front anti-reflection layer 2 is flexible and diverse, and the anti-reflection effect is good.
  • the refractive index of the front anti-reflection layer 2 decreases in the direction away from the silicon substrate 6 , and the refractive index of the front anti-reflection layer 2 decreases in the direction away from the silicon substrate 6 , resulting in a better anti-reflection effect.
  • the front anti-reflection layer 2 includes a silicon nitride film and a magnesium fluoride film, where the silicon nitride film is close to the silicon substrate, and the refractive index of the magnesium fluoride film is smaller than that of the silicon nitride film, reducing The anti-reflection effect is better, and the material of the front anti-reflection layer 2 is easy to obtain and the cost is low.
  • the doped polysilicon layer 4 contains carbon element and/or oxygen element.
  • Carbon element and oxygen element can increase the band gap of the doped polysilicon layer 4 and improve the light transmittance and conductivity of the doped polysilicon layer 4 . , easy to prepare, simple process, and low cost.
  • the area of the portion of the front electrode 1 located in the front passivation layer 3 and the front anti-reflection layer 2 on the light-facing surface of the silicon substrate 6 is less than or equal to that of the front electrode 1
  • the portion protruding from the front passivation layer 3 and the front anti-reflection layer 2 is the area projected onto the light surface of the silicon substrate 6 .
  • the front electrode 1 with the above shape is easy to process and manufacture. There is no specific limit on how much the areas of the two projections differ.
  • the area of the light-facing surface of the silicon substrate 6 that is opposite to the front electrode 1 is a polished surface, and the remaining areas have a textured structure.
  • the area of the light-facing surface of the silicon substrate 6 that is opposite to the front electrode 1 is covered by the front electrode 1.
  • Blocking, being a polished surface or having a textured structure will not affect the optical effect, but the area of the light-facing surface of the silicon substrate 6 opposite to the front electrode 1 is a polished surface, which is beneficial to the preparation of the layers above it, especially the front electrode. 1 Preparation.
  • the material of the back doped layer 8 is selected from at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.
  • the material selection of the back doped layer 8 is flexible and diverse.
  • the back doped layer 8 and the back intrinsic passivation layer 7 form a heterojunction, and the doped polysilicon layer 4 and the silicon substrate 6 form a high-low junction.
  • the solar cell of the present invention combines the advantages of TOPCon cells and HIT cells, and has Higher short circuit current, open circuit voltage and photoelectric conversion efficiency.
  • the doping type of the silicon substrate 6 is not specifically limited.
  • the silicon substrate 6 can be N-type doped, then the doped polysilicon layer 4 is also N-type doped, and the back doped layer 8 is P-type doped.
  • the silicon substrate 6 is an N-type silicon substrate
  • the back doped layer 8 is at least one of P-type doped amorphous silicon, P-type doped microcrystalline silicon, and P-type doped nanocrystalline silicon.
  • the hybrid layer 8 has more selectivity.
  • the solar cell may also include: a back TCO layer 9, the back TCO layer 9 is located on the back doped layer 8, the back electrode 10 is located on the back TCO layer 9, the back TCO layer 9 plays a certain role.
  • the role of energy band adaptation is beneficial to optimizing the performance of solar cells.
  • the width of each front electrode 1 is 1 to 50um.
  • the direction of the length of the front electrode 1 and the direction of the width of the front electrode 1 are both consistent with the stacking direction of the front passivation layer 3 and the front anti-reflection layer 2. Vertical and width less than length. The directions corresponding to the length and width mentioned throughout the article are defined in this way.
  • the width of the front electrode 1 is 1 to 50um, and has good current conductivity. For example, the width of the front electrode 1 is 1um, 5um, 13um, 20um, 25um, 31um, 39um, 46um, 50um.
  • the cross-sectional shape of the front electrode 1 and the back electrode 10 parallel to the light facing surface of the silicon substrate 6 may be square, semicircular, triangular, trapezoidal, or other irregular shapes.
  • the present invention provides a method for manufacturing a solar cell as described above.
  • Figure 3 shows the embodiment of the present invention A flow chart of steps for a solar cell.
  • the solar cell includes the following steps:
  • Step 101 Form a passivation contact structure on the light-facing surface of the silicon substrate.
  • Figure 4 shows a schematic structural diagram of the preparation process of the first solar cell in the embodiment of the present invention.
  • Figure 5 shows a schematic structural diagram of the preparation process of the second solar cell in the embodiment of the present invention.
  • Figure 6 shows a schematic structural diagram of the preparation process of the third solar cell in the embodiment of the present invention.
  • Figure 7 shows a schematic structural diagram of the preparation process of the fourth solar cell in the embodiment of the present invention.
  • Figure 8 shows a schematic structural diagram of the preparation process of the fifth solar cell in the embodiment of the present invention.
  • Figure 9 shows a schematic structural diagram of the preparation process of the sixth solar cell in the embodiment of the present invention.
  • Figure 10 shows a schematic structural diagram of the preparation process of the seventh solar cell in the embodiment of the present invention.
  • Figure 11 shows a schematic structural diagram of the preparation process of the eighth solar cell in the embodiment of the present invention.
  • Figure 12 shows a schematic structural diagram of the preparation process of the ninth solar cell in the embodiment of the present invention.
  • Figure 13 shows a schematic structural diagram of the preparation process of the tenth solar cell in the embodiment of the present invention.
  • Figure 14 shows a schematic structural diagram of the preparation process of the eleventh solar cell in the embodiment of the present invention.
  • Figure 15 shows a schematic structural diagram of the preparation process of the twelfth solar cell in the embodiment of the present invention.
  • Figure 16 shows a schematic structural diagram of the preparation process of the thirteenth solar cell in the embodiment of the present invention.
  • Figure 17 shows a schematic structural diagram of the preparation process of the fourteenth solar cell in the embodiment of the present invention.
  • Figure 18 shows a schematic structural diagram of the preparation process of the fifteenth solar cell in the embodiment of the present invention.
  • Figure 19 shows a schematic structural diagram of the preparation process of the sixteenth solar cell in the embodiment of the present invention.
  • Figure 20 shows a schematic structural diagram of the preparation process of the seventeenth solar cell in the embodiment of the present invention. All structures in the drawings of the description are schematic diagrams and do not represent relative size relationships.
  • the method may further include: texturing processing.
  • a texturing process is performed on an N-type silicon substrate with a resistivity of 0.1 to 10 ⁇ .cm (ohm.cm) and a thickness of 50 to 400 ⁇ m to obtain a textured surface.
  • the silicon substrate can be obtained by surface texturing and cleaning of a single crystal silicon wafer prepared by the N-type Czochralski method (or zone melting method, ingot casting method, etc.).
  • an alkaline solution containing KOH or NaOH can also be used for the texturing process, and the temperature can be 60 to 85°C. Then use No.
  • a HF or NH 4 HF 2 solution with a concentration of 0.5-10%, or a mixed solution of one of the two solutions and HCl can be used to remove the surface layer to obtain the silicon substrate 6 mentioned above.
  • other texturing methods are not specifically limited.
  • a passivation contact structure is formed on the light-facing side of the silicon substrate.
  • the passivation contact structure may include a stacked tunnel layer 5 and a doped polysilicon layer 4 .
  • the tunnel layer 5 can be formed on the light-facing surface of the silicon substrate 6 first.
  • the preparation method of the tunnel layer 5 is not limited.
  • at least one of thermal oxidation, wet oxidation, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), and ALD (Atomic layer deposition) can be used on the silicon substrate 6
  • the light-facing surface forms a tunneling layer 5.
  • the temperature of thermal oxidation of tunnel layer 5 is: 200 to 800°C.
  • the oxidant of wet oxidation can be HNO 3 , O 3 , H 2 O 2 , etc.
  • the gas SiH 4 passed in PECVD is used as the silicon source, and N 2 O and/or CO 2 can be used as the oxygen source, TMS (tetramethylsilane) can be introduced into the ALD as the silicon source, and H 2 O and/or O 3 can be used as the oxygen source.
  • the thermal oxidation preparation method the silicon substrate 6 is placed in a quartz boat, and a layer of silicon oxide with a thickness of 0.5 to 2 nm is deposited on the surface of the silicon substrate 6 at a temperature of 300 to 700°C.
  • the reaction gas used for deposition is O2 , its flow rate can be 0.1 to 20slm (standard liter per minute, under standard conditions, liters per minute), the deposition pressure can be 100Pa to normal pressure, and the specific thermal oxidation method can be Constant oxygen flow, variable oxygen flow, etc., the total oxygen ventilation time can be from 5 to 120 minutes.
  • the preparation method of other tunneling layers 5 is not specifically limited.
  • the doped polysilicon layer 4 can be prepared by: first forming intrinsic polysilicon with a low crystallization rate, and then preparing a high crystallization rate doped polysilicon layer 4, or the doped polysilicon with a high crystallization rate can be formed in one go. Layer 4.
  • the silicon substrate 6 is an N-type silicon substrate
  • the doped polysilicon layer 4 can be prepared by depositing an intrinsic polysilicon layer on the tunnel layer 5 .
  • the intrinsic polysilicon layer is subjected to phosphorus-doping treatment to form a phosphorus-doped polysilicon layer 4 .
  • inorganic elements such as oxygen and carbon can be additionally doped.
  • a PSG (Phospho Silicate Glass) layer 11 is formed on the phosphorus-doped polysilicon layer 4 , and the thickness of the PSG layer 11 is 10 to 110 nm.
  • Preparation methods of intrinsic polysilicon include but are not limited to APCVD (Atmospheric Pressure Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD, PVD, etc.
  • the reaction temperature of LPCVD can be 400 to 700°C
  • the feed gas can be SiH 4
  • the feed gas of PECVD can be SiH 4 .
  • the intrinsic polysilicon layer is prepared by LPCVD, the preparation is performed directly after the tunnel layer 5 is prepared.
  • the tunnel layer 5 and the intrinsic polysilicon can be integrated into one process.
  • an intrinsic polysilicon layer with a thickness of 10 to 300 nm is deposited on the tunnel layer 5 at a temperature of 400 to 700°C.
  • the preferred thickness of the intrinsic polysilicon layer is 50 to 200 nm.
  • the reaction gas used when depositing the intrinsic polysilicon layer is SiH 4 , with a flow rate of 50 to 1000 sccm, a deposition pressure of 100 to 400 Pa, and a time of 2 to 60 minutes.
  • the chip insertion method can be single chip or double chip in one slot. The chip insertion method will not Have a greater impact on this process.
  • the preparation method of other intrinsic polysilicon is not specifically limited.
  • the phosphorus doping treatment may include: phosphorus diffusion, or printing phosphorus paste and annealing.
  • the doped polysilicon layer 4 is formed by using a phosphorus diffusion (POCl 3 ) process or annealing after printing the phosphorus paste.
  • the thickness of the PSG layer 11 may be 10 to 50 nm.
  • the thickness of the PSG layer 11 may be 10 nm, 30 nm, 40 nm, 45 nm, 50 nm, 60 nm, 80 nm, 90 nm, 100 nm, or 110 nm.
  • a phosphorus-doped polysilicon layer 4 is formed on the tunnel layer 5 on the surface of the N-type silicon substrate 6 through pre-deposition and advancement through thermal diffusion of POCl 3 , and a phosphorus-doped polysilicon layer 4 is formed on the surface of the N-type silicon substrate 6.
  • PSG layer 11 is formed in the thermal diffusion furnace tube.
  • intrinsic amorphous silicon can be deposited first, and then phosphorus doping is performed.
  • the process of phosphorus doping is: first pre-deposit a phosphorus source on the intrinsic amorphous silicon layer, and the pre-deposited phosphorus source will be on the intrinsic amorphous silicon layer.
  • PSG is formed on the crystalline silicon layer and then pushed forward. The phosphorus in the PSG will be pushed into the intrinsic amorphous silicon layer.
  • the pushing process is accompanied by crystallization to form a phosphorus-doped polysilicon layer.
  • the temperature of the pre-deposited phosphorus source is 700 to 850°C, and the deposition time is 5 to 100 minutes.
  • the pushing temperature is 700 to 1100°C
  • the pushing time is 15 to 150min
  • the pushing pressure is 100 to 400Pa.
  • the temperatures of the pre-deposited phosphorus source are: 700°C, 720°C, 760°C, 780°C, 790°C, 800°C, 820°C, 830°C, 840°C, 850°C
  • the deposition time is 5min, 8min, 10min, 20min , 28min, 37min, 42min, 50min, 60min, 70min, 80min, 100min
  • the advancing temperature is: 700°C, 720°C, 760°C, 780°C, 790°C, 800°C, 820°C, 830°C, 840°C, 850°C , 930°C, 970°C, 1000°C, 1020°C, 1048°C, 1100°C
  • the pushing time can be: 15min, 18min, 20min, 32min, 38min, 47min, 55min, 63min
  • the doped polysilicon layer 4 can also be prepared by in-situ doping of phosphorus on the tunneling layer 5 and annealing to form the phosphorus-doped polysilicon layer 4 .
  • Depositing the in-situ phosphorus-doped amorphous silicon layer and/or polysilicon layer on the tunnel layer 5 includes but is not limited to APCVD, LPCVD, PECVD, PVD and other processes.
  • the process temperature of PECVD is 400 to 700°C, and the gas introduced is SiH 4 .
  • LPCVD is used to prepare in-situ phosphorus-doped polysilicon, and the tunneling silicon oxide is directly prepared.
  • the tunneling layer 5 and the in-situ phosphorus-doped polysilicon can be integrated into one process. Specifically, an in-situ phosphorus-doped polysilicon layer of 10 to 300 nm is deposited on the tunnel layer 5 at a temperature of 400 to 700°C. The preferred thickness of the polysilicon layer may be 50 to 200 nm.
  • the reaction gases used when depositing the polysilicon layer are SiH 4 and PH 3.
  • the flow rates of SiH 4 and PH 3 are 50 to 1000 sccm and 2 to 40 sccm respectively.
  • the deposition pressure is 100 to 400 Pa, and the time is 5 to 120 minutes.
  • the chip insertion method can be a single chip or a double chip in one slot.
  • the chip insertion method will not have a major impact on the process flow.
  • the preparation methods of other in-situ doped polysilicon are not specifically limited.
  • an in-situ phosphorus-doped amorphous silicon layer and/or a polysilicon layer is deposited on the tunnel layer 5, and then annealed to prepare a phosphorus-doped polysilicon layer 4 with a high crystallization rate, which can be performed during the annealing process, and/or After completion, oxygen is passed through, and a PSG layer 11 of a certain thickness is formed on the surface of the phosphorus-doped polysilicon layer 4 in the oxygen atmosphere.
  • N 2 is passed for crystallization treatment, and then O 2 is passed to form the PSG layer 11 on the N-type doped polysilicon layer 4 .
  • the temperature of thermal annealing and oxidation is 700 to 1100°C, the annealing time is 15 to 120 minutes, the thermal oxidation time is 15 to 120 minutes, and the process pressure is 100 Pa to normal pressure.
  • the thickness of the PSG layer 11 is 5 to 50 nm, and then the sheet resistance of the silicon substrate 6 containing the PSG layer 11 is measured to be 10 to 1000 ⁇ /sq. It should be noted that during the in-situ phosphorus doping process, inorganic elements such as oxygen and carbon can be additionally doped.
  • Step 102 Form a first opening on the passivation contact structure to form a partial passivation contact structure and expose the light-facing portion of the silicon substrate.
  • the passivation contact structure includes a stacked tunnel layer 5 and a doped polysilicon layer 4, that is, a first opening is formed on the tunnel layer 5 and the doped polysilicon layer 4 so that the light-facing surface of the silicon substrate 6
  • the method of exposing and forming the first opening is not specifically limited.
  • This step forms a locally passivated contact structure.
  • it can be laser opening, or masking and then wet etching, etc.
  • a PSG layer 11 is generated on the surface of the doped polysilicon layer 4 , and a laser is used to form a third opening on the PSG layer 11 to obtain a phosphosilicate glass pattern, that is, a PSG pattern 11 -L, and make The phosphorus-doped polysilicon layer 4 is partially exposed.
  • the exposed phosphorus-doped polysilicon layer 4 is alkali-washed to form a third opening on the tunneling layer 5 and the area corresponding to the third opening on the doped polysilicon layer 4 . Open your mouth.
  • the PSG layer 11 as the mask layer is formed, and the process is simple.
  • an alkali such as KOH or NaOH is used to wash away the local area of the tunnel layer 5 and the doped polysilicon layer 4 corresponding to the third opening to form the first opening.
  • the alkaline solution also textures the light-facing surface of the exposed portion of the silicon substrate 6 .
  • the silicon substrate with the PSG layer 11 formed with the third opening is placed in a tank or chain cleaning machine at a temperature of 60 to 85° C., and under the protection of the PSG mask layer with the third opening formed.
  • an alkaline solution containing KOH or NaOH is used to form the first opening, and a secondary texturing process is performed on the light-facing surface of the exposed part of the silicon substrate 6 .
  • alkali polishing pretreatment can also be performed.
  • the PSG layer 11 on which the third opening is formed is completely removed by cleaning with HF or NH 4 HF 2 (or a mixed solution thereof and HCl).
  • the method may also include: forming a silicon nitride layer on the phosphorus-doped polysilicon layer 4, and filling hydrogen into the doped polysilicon layer 4 during the formation of the silicon nitride layer, so that The passivation performance of the doped polysilicon layer 4 is further improved. Then, a laser is used to form a fourth opening on the silicon nitride layer to form a silicon nitride pattern and partially expose the doped polysilicon layer 4 .
  • the above step 102 may include: using the silicon nitride layer formed with the fourth opening, that is, the silicon nitride pattern, as a mask layer, alkali washing the exposed doped polysilicon layer 4 to separate the tunnel layer 5 and the doped polysilicon layer 4 A first opening is formed on a local area corresponding to the fourth opening.
  • the alkaline solution also textures the light-facing surface of the exposed portion of the silicon substrate 6 .
  • the silicon nitride layer can be removed using acid.
  • the wavelength of the laser is 100 to 800 nm
  • the pulse width is 100 fs to 1 ms
  • the frequency is 100 kHz to 100 MHz.
  • the above laser is more common, has lower cost, and is easy to form openings for both the PSG layer 11 and the silicon nitride layer.
  • the wavelength of the laser here can be 532nm or 355nm
  • the pulse width can be 1ps to 500ns
  • the laser spot shape is square or circular
  • the spot length or diameter is 10 to 500 ⁇ m
  • the output power is 1 to 100W
  • the line Speed is 1 to 100m/s.
  • the above-mentioned laser is more common, lower cost, and easy to form openings for both the PSG layer and the silicon nitride layer.
  • the pulse width of the laser that forms the fourth opening is one of 1ps, 300ps, 1100ps, 2ns, 2.5ns, 250ns, 360ns, 440ns, and 500ns.
  • the laser spot shape is square or circular, and the length or diameter of the spot is 10 ⁇ m, 23 ⁇ m, 65 ⁇ m, 146 ⁇ m, 250 ⁇ m, 255 ⁇ m, 300 ⁇ m, 378 ⁇ m, 500 ⁇ m
  • the output power is 1W, 20W, 48W, 50W, 63W, 74W, 87W, 100W
  • the line speed is 1m/s, 21m/s, 45m/ s, 50m/s, 56m/s, 70m/s, 80m/s, 86m/s, 90m/s, 100m/s.
  • a PSG layer 11 is formed on the surface of the phosphorus-doped polysilicon layer 4.
  • the method may also include: using a screen printing pattern mask on a local area of the PSG layer 11. film material and solidify to obtain the patterned mask 13; or, inkjet print the patterned mask material on a local area of the PSG layer 11 to obtain the patterned mask 13.
  • the head of the inkjet printing device usually has a heating or curing function, so the patterned mask material does not need to be cured after inkjet printing.
  • patterned mask material such as screen printing, printing patterned mask material on a local area of the above-mentioned PSG layer 11, and placing the silicon substrate printed with the patterned mask material in a drying oven for drying, solidification, and drying.
  • the temperature is 150 to 250°C and the time is 0.2 to 10 minutes to form a patterned mask 13 that matches the shape of the front electrode 1 or is slightly larger than the front electrode 1 .
  • the preparation methods of other patterned masks 13 will not be described in detail here.
  • the material of the patterned mask 13 is selected from: paraffin wax, which is easy to screen print or inkjet print, easy to solidify, easy to remove later, and low cost.
  • paraffin wax which is easy to screen print or inkjet print, easy to solidify, easy to remove later, and low cost.
  • Other choices of materials for the patterned mask are not specifically limited.
  • the patterned mask 13 is formed, wet processing is used under the protection of the patterned mask to etch the PSG layer 11 into phosphorus silicon consistent with the shape of the patterned mask 13
  • the glass pattern 11-L makes the phosphorus-doped polysilicon layer 4 partially exposed, and the patterned mask 13 is removed.
  • the patterned mask 13 can be removed using a mixed solution of NH 3 ⁇ H 2 O (or KOH/NaOH) with a concentration of 1 to 10% and H 2 O 2 with a concentration of 2 to 20%, at room temperature to 80°C.
  • the aforementioned step 102 may include: using the phosphorus silicate glass pattern 11 -L as a mask layer, alkali washing the exposed phosphorus-doped polysilicon layer 4 to separate the tunnel layer 5 and the phosphorus-doped polysilicon layer. A first opening is formed on a local area.
  • the phosphosilicate glass pattern 11-L can be removed through a HF (or NH 4 HF 2 ) solution with a concentration of 0.5-10%.
  • an alkaline solution containing KOH or NaOH is used to form the first opening, and the exposed part of the silicon substrate 6 is exposed to light.
  • a secondary texturing process or etching process is performed on the surface and the backlight surface of the silicon substrate 6 .
  • the method may also include: forming a silicon nitride layer on the doped polysilicon layer 4, and filling hydrogen into the doped polysilicon layer 4 during the formation of the silicon nitride layer to further Improve the passivation performance of passivated contact structures.
  • step 102 may include: using the silicon nitride layer pattern as a mask layer, alkali washing the exposed doped polysilicon layer to separate the tunnel layer 5 and the doped polysilicon layer.
  • a local area on layer 4 forms a first opening.
  • the above-mentioned process of forming the first opening is easy to achieve mass production and greatly improves production efficiency.
  • the process of forming the patterned mask 13 is easier to achieve mass production and improves production efficiency.
  • Step 103 Form a front passivation antireflection layer on the exposed light-facing surface of the silicon substrate, and sequentially form a back intrinsic passivation layer and a back doped layer on the back light surface of the silicon substrate.
  • a front passivation antireflection layer is formed on the exposed light-facing surface of the silicon substrate 6 , and a back intrinsic passivation layer 7 and a back doped layer 8 are sequentially formed on the back light surface of the silicon substrate 6 .
  • this step 103 may also include: forming a front passivation anti-reflection layer on the partially passivated contact structure and the exposed light-facing surface of the silicon substrate 6, and forming a second opening in a local area of the front anti-reflection layer, so that The partially passivated contact structure is at least partially exposed.
  • the front passivation anti-reflection layer may include: front passivation layer 3 and front anti-reflection layer 2 .
  • the front passivation anti-reflection layer is formed in the above step 103, and The backlight surface of the silicon substrate 6 is sequentially formed with a backside intrinsic passivation layer 7 and a backside doping layer 8 as shown in FIGS. 12 to 15 .
  • a front passivation layer 3 and a front anti-reflection layer 2 are sequentially formed on the doped polysilicon layer 4 and the exposed silicon substrate 6 .
  • the front passivation layer 3 can be thermal oxidation or the like.
  • the SiO 2 front passivation layer 3 is prepared by thermal oxidation. In tubular equipment, the reaction temperature is 500 to 1000°C, the oxygen flow rate is 0.1 to 20slm (standard liter per minute, L/min under standard conditions), and the reaction time is 10 to 120 min, and the thickness of the prepared front passivation layer 3 is 1 to 50 nm.
  • the front anti-reflection layer 2 is formed on the front passivation layer 3.
  • the method of forming the front anti-reflection layer 2 includes but is not limited to SiN x , SiC x , TiO x or other film layers with similar refractive index prepared by PECVD.
  • the outermost layer is also Film layers with lower refractive index such as SiO x and MgF 2 can be stacked to improve the anti-reflection effect.
  • SiOx can be prepared by PECVD or ALD, and MgF2 can be prepared by PVD.
  • x in the chemical formula is a number greater than 0.
  • an anti-reflection film of a single SiN The volume ratio is (1:2) to (1:40), the power supply power is 1 to 20kW, the pressure is 20 to 400Pa, and the thickness of the front antireflection layer 2 finally prepared is 50 to 90nm.
  • the preparation method of other front-side anti-reflection layers 2 is not specifically limited.
  • the direction of the thickness is parallel to the stacking direction of the tunnel layer 5 and the doped polysilicon layer 4. The thickness and direction mentioned throughout this article are all defined in this way.
  • FIG. 12 succeeds the aforementioned FIG. 11
  • FIG. 13 succeeds the aforementioned FIG. 8 .
  • the tunneling layer, passivation layer, and anti-reflection layer that may be formed on the backlight surface of the silicon substrate 6 are cleaned.
  • the pyramid suede surface can be directly cleaned with single-sided or double-sided HF solution to remove the back coating, and then undergo surface modification, such as HNO 3 and HF surface rounding treatment.
  • the acid-etched surface directly adopts a chain single-sided etching process.
  • the process tank includes solutes such as HNO 3 and HF to form a surface with a certain roughness.
  • the alkali polished surface is a polishing process using an alkali solution system such as KOH or NaOH to form a smoother surface.
  • a backside intrinsic passivation layer 7 is deposited on the backlight surface of the silicon substrate 6, including but not limited to PECVD, HWCVD (hot wire chemical vapor deposition) PVD, Cat-CVD (catalytic chemical vapor deposition) deposition, catalytic chemical vapor deposition), ALD or solution methods.
  • PECVD hot wire chemical vapor deposition
  • HWCVD hot wire chemical vapor deposition
  • Cat-CVD catalytic chemical vapor deposition
  • ALD catalytic chemical vapor deposition
  • the process temperature of HWCVD is 100 to 250°C
  • the gas introduced is SiH 4 , H 2 , etc.
  • the PECVD method is used to deposit a layer of back intrinsic passivation layer 7 with a thickness of 2 to 16 nm
  • the reaction gases are SiH 4 and H 2
  • the volume ratio of SiH 4 and H 2 in the mixed gas is (1:1) to (1:50 )
  • the power density is 0.01 to 0.5W/cm 2
  • the pressure is 20 to 200Pa
  • the reaction temperature is 100 to 200°C.
  • a backside doped layer 8 is formed on the backside intrinsic passivation layer 7 .
  • the back doped layer 8 is one of: an amorphous silicon doped layer, a microcrystalline silicon doped layer, and a nanocrystalline silicon doped layer.
  • the back doped layer 8 can be a phosphorus-doped amorphous/microcrystalline/nanocrystalline silicon film, and on this basis, it can also be doped with oxygen, carbon elements, etc.
  • the formation method of the back doped layer 8 includes but is not limited to PECVD, HWCVD, Cat-CVD, PVD, ALD or solution method.
  • the process temperature of HWCVD is 100 to 250°C, and the gas introduced is SiH 4 , H 2 , etc.
  • a P-type amorphous, microcrystalline, and nanocrystalline doping layer of 10 to 40 nm is continued to be deposited on the surface of the back intrinsic amorphous silicon passivation layer 7 , and the reaction gases are SiH 4 , H 2 and B 2 H 6 , mixed
  • the volume ratio of SiH 4 and H 2 in the gas is (1:1) to (1:50)
  • the volume ratio of SiH 4 and B 2 H 6 is (5:1) to (100:1)
  • the power power density is 0.01 to 0.2W/cm 2
  • pressure 20 to 200Pa reaction temperature 100 to 200°C.
  • a front passivation anti-reflection layer is formed in the above step 103, and a back intrinsic passivation layer 7 and a back intrinsic passivation layer 7 are formed on the backlight surface of the silicon substrate 6 in sequence.
  • the backside doped layer 8 can be shown with reference to FIGS. 16 to 19 .
  • a backside intrinsic passivation layer 7 is deposited on the backlight surface of the silicon substrate 6 .
  • the method of forming the backside intrinsic passivation layer 7 can refer to the above-mentioned relevant records. In order to avoid repetition, it will not be described again here. .
  • a front intrinsic passivation layer 3 is formed on the exposed light-facing surface of the doped polysilicon layer 4 and the silicon substrate 6.
  • the method of forming the front intrinsic passivation layer 3 can refer to forming the back intrinsic passivation.
  • the method of layer 7 will not be described again here.
  • the formation of the front intrinsic passivation layer 3 and the formation of the back intrinsic passivation layer 7 can be performed simultaneously, and this is not specifically limited in the present invention.
  • a front anti-reflection layer 2 is formed on the front intrinsic passivation layer 3 .
  • the method of forming the front anti-reflection layer 2 can refer to the aforementioned formation method of the front anti-reflection layer 2 . In order to avoid repetition, no details are shown here. Again.
  • a back doped layer 8 is formed on the back intrinsic passivation layer 7 .
  • the formation method of the back doped layer 8 refer to the above-mentioned relevant descriptions. In order to avoid duplication, details will not be described here.
  • the method may further include: forming a second opening in a local area of the front-side anti-reflection layer, so that the local passivation contact structure is at least partially exposed.
  • a second opening is formed in a local area of the front anti-reflection layer and the front passivation layer, so that the doped polysilicon layer is at least partially exposed.
  • a second opening is formed in a local area of the front antireflection layer 2 and the front passivation layer 3 so that the doped polysilicon layer 4 is at least partially exposed.
  • the entire polysilicon layer 4 may be exposed, or a part of the polysilicon layer 4 may be exposed. For example, as shown in FIG. 20 , part of the polysilicon layer 4 is exposed.
  • the second opening may be formed by laser opening, or by wet processing.
  • at least one of laser, printing etching slurry, and spraying etching slurry is used to open local areas of the front passivation layer 3 and the front anti-reflection layer 2 .
  • the second opening is through the opening, and the laser opening process is simple.
  • the laser wavelength is 100 to 800nm
  • the pulse width is 100fs to 1ms
  • the frequency is 100kHz to 100MHz.
  • the wavelength of the laser is 532nm or 355nm
  • the pulse width is 1ps to 500ns
  • the laser spot shape is square or circular
  • the spot length or diameter is 0.5 to 30 ⁇ m
  • the output power is 1 to 20W
  • the linear speed is 1 to 100m/s.
  • the second opening has a width of 1 to 40 microns. The direction of the width is perpendicular to the stacking direction of the tunnel layer 5 and the doped polysilicon layer 4 .
  • the pulse width of the laser that forms the second opening is one of 1ps, 300ps, 1100ps, 2ns, 2.5ns, 250ns, 360ns, 440ns, and 500ns
  • the laser spot shape is square or circular
  • the length or diameter of the spot is 0.5 ⁇ m, 3 ⁇ m, 6.5 ⁇ m, 14.6 ⁇ m, 15 ⁇ m, 15.5 ⁇ m, 21 ⁇ m, 27.5 ⁇ m, 30 ⁇ m
  • output power is 1W, 8W, 9.9W, 10W, 10.3W, 14W, 17W, 20W
  • linear speed is 1m/s , 21m/s, 45m/s, 50m/s, 56m/s, 70m/s, 80m/s, 86m/s, 90m/s, 100m/s.
  • the layer formed in the laser area can also be removed by wet method.
  • low-concentration acid such as HF, HNO 3 , HCl, etc. can be used to clean the structure containing the second opening in a short time.
  • Step 104 Form a front electrode on the local passivation contact structure, and form a back electrode electrically connected to the back doped layer.
  • step 104 may include: forming a front-side electrode on the exposed doped polysilicon layer, and forming an electrical connection with the back-side doped layer. Connect the back electrode.
  • a front electrode 1 is formed on the exposed doped polysilicon layer 4 , and a back electrode 10 electrically connected to the back doped layer 8 is formed.
  • Methods of forming the front electrode 1 and the back electrode 10 include but are not limited to screen printing, laser transfer, electroplating, evaporation, and can also be combined with other patterning methods, such as photolithography.
  • the subsequent processing processes of the solar cells formed by the present invention include but are not limited to: solidification, sintering, light injection (Light-Induced Regeneration), electric injection (Electric-Induced Regeneration) or dark state annealing ( dark annealing) etc.
  • the present invention does not specifically limit this.
  • the method may further include: forming a back TCO layer 9 on the back doped layer 8 .
  • Forming the back electrode 10 may include forming the back electrode 10 on the back TCO layer 9 .
  • Forming the back TCO layer 9 on the back doped layer 8 may include depositing ITO, IWO, FTO, AZO and other metal oxides or mixtures thereof on the backlight surface of the back doped layer 8, or other work functions between P-type amorphous /Materials for the back doped layer 8 and back electrode 10 of microcrystalline/nanocrystalline silicon.
  • the formation methods of the back TCO layer 9 include but are not limited to magnetron sputtering, RPD (Reactive Plasma Deposition, reactive plasma deposition), and vacuum evaporation. , PECVD, ALD and other preparation methods.
  • the PVD method is used to deposit 75nm ITO on the back doped layer 8.
  • the flow ratio of O 2 and Ar is 0.01 to 0.2
  • the pressure is 0.1 to 5 Pa
  • the temperature of the silicon substrate 6 is room temperature.
  • the back TCO layer 9 can also be prepared after forming the back doping layer 8 and before forming the second opening, which is not specifically limited in the embodiment of the present invention.
  • the materials of the front electrode 1 and the back electrode 10 can be metals and alloys with good conductivity such as Ag, Al, Cu, and Au.
  • the present invention also provides a photovoltaic module, which includes a battery string formed by a plurality of any of the aforementioned solar cells connected in series.
  • This photovoltaic module has the same or similar beneficial effects as any of the aforementioned solar cells and any of the aforementioned solar cell preparation methods, and the relevant points between the three can be referred to each other. In order to avoid duplication, they will not be described again here. .
  • the silicon substrate 6 is subjected to texturing treatment.
  • a tunnel layer 5 and a doped polysilicon layer 4 are formed on the light-facing surface of the silicon substrate 6
  • a PSG layer 11 is formed on the doped polysilicon layer 4 .
  • a laser is used to form a third opening on the PSG layer 11 to obtain a phosphorus silicate glass pattern, that is, a PSG pattern 11 -L, and to partially expose the phosphorus-doped polysilicon layer 4 .
  • the exposed phosphorus-doped polysilicon layer 4 is alkali-washed to form a third opening on the tunneling layer 5 and the area corresponding to the third opening on the doped polysilicon layer 4 . Open your mouth.
  • a front passivation layer 3 and a front anti-reflection layer 2 are sequentially formed on the doped polysilicon layer 4 and the exposed silicon substrate 6 .
  • the tunneling layer, passivation layer, and anti-reflection layer that may be formed on the backlight surface of the silicon substrate 6 are cleaned. Referring to FIG.
  • a back intrinsic passivation layer 7 a back doping layer 8 , and a back TCO layer 9 are formed on the backlight surface of the silicon substrate 6 in sequence.
  • a second opening is formed in a local area of the front antireflection layer 2 and the front passivation layer 3 , so that the doped polysilicon layer 4 is completely exposed.
  • a front electrode 1 is formed on the exposed doped polysilicon layer 4 , and a back electrode 10 electrically connected to the back doped layer 8 is formed.
  • Table 1 Comparison of the electrical performance of solar cells in the examples and the highest record data of TOPCon and HJT cells
  • FZ Float Zone
  • CZ the single crystal drawn by the Czochralski method
  • P-FZ refers to a single crystal whose silicon substrate is drawn by the P-type floating zone method or zone melting method
  • N-FZ a single crystal whose silicon substrate is drawn by the N-type floating zone method or zone melting method
  • P-CZ refers to silicon
  • the substrate is a single crystal drawn by P-type Czochralski method.
  • N-CZ refers to the silicon substrate is a single crystal drawn by N-type Czochralski method.
  • N-type refers to an N-type doped silicon substrate.
  • the preparation method of the silicon substrate is not limited. .
  • the photoelectric conversion efficiency of the solar cell in the present invention is significantly higher, the current density is significantly higher, and the filling factor is significantly higher.
  • a local passivation contact structure is formed at the contact part of the front electrode 1, which can effectively suppress contact recombination and surface recombination.
  • the uncovered part of the front electrode 1 is not doped.
  • the silicon substrate 6 is covered by the front passivation layer 3 and the front anti-reflection layer 2, which can effectively reduce the parasitic absorption of light, achieve a good passivation and anti-reflection effect, and improve The short-circuit current density is reduced, and the short-circuit current and photoelectric conversion efficiency of the solar cell are further improved.
  • the backlight surface of the silicon substrate 6 can also have a heterojunction structure, which can obtain better passivation and contact performance.
  • the device embodiments described above are only illustrative.
  • the units described as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in One location, or it can be distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Persons of ordinary skill in the art can understand and implement the method without any creative effort.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the element claim enumerating several means, several of these means may be embodied by the same item of hardware.
  • the use of the words first, second, third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

本发明提供了一种太阳能电池及其制备方法和光伏组件，涉及光伏技术领域。太阳能电池包括：硅基底、正面钝化减反层、局部钝化接触结构、层叠设置的背面本征钝化层和背面掺杂层、正面电极、背面电极；局部钝化接触结构和正面钝化减反层，共同覆盖硅基底的向光面，且沿着与背面掺杂层和背面电极的层叠方向垂直的方向，局部钝化接触结构和正面钝化减反层，在硅基底的向光面上交替分布；层叠设置的背面本征钝化层和背面掺杂层，位于硅基底的背光面；正面电极位于所述局部钝化接触结构上；背面电极与背面掺杂层电连接。局部钝化接触结构可有效抑制接触复合和表面复合，由正面钝化层、正面减反层覆盖硅基底，减少了寄生性吸收，钝化减反效果好。

Description

太阳能电池及其制备方法和光伏组件
本申请要求在2022年8月19日提交中国专利局、申请号为202211002855.9、发明名称为“太阳能电池及其制备和光伏组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及光伏技术领域，特别是涉及一种太阳能电池及其制备方法和光伏组件。
背景技术
包括层叠设置的隧穿层和掺杂多晶硅层的钝化接触结构，能够提供优异的硅界面钝化和接触钝化性能，因此，在太阳能电池中应用广泛。
然而现有的向光面具有钝化接触结构的太阳能电池，在向光面存在较为严重的接触复合和/或寄生吸收，降低了太阳能电池的开路电压、短路电流、填充因子，以及光电转换效率。
发明内容
本发明提供一种太阳能电池及其制备方法和光伏组件，旨在解决现有的向光面具有钝化接触结构的太阳能电池，在向光面存在较为严重的接触复合和/或寄生吸收，降低了太阳能电池的开路电压、短路电流、填充因子，以及光电转换效率的问题。
本发明的第一方面，提供一种太阳能电池，包括：
硅基底、正面钝化减反层、局部钝化接触结构、层叠设置的背面本征钝化层和背面掺杂层、正面电极、背面电极；
所述局部钝化接触结构和所述正面钝化减反层，共同覆盖所述硅基底的向光面，且沿着与所述背面掺杂层和所述背面电极的层叠方向垂直的方向，所述局部钝化接触结构和所述正面钝化减反层，在所述硅基底的向光面上交替分布；
所述层叠设置的背面本征钝化层和背面掺杂层，位于所述硅基底的背光面；
所述正面电极位于所述局部钝化接触结构上；
所述背面电极与所述背面掺杂层电连接。
本发明实施例中，与正面电极接触的局部钝化接触结构，可以有效抑制接触复合和表面复合，保证了较高的开路电压。正面电极未覆盖的部分没有形成掺杂，由正面钝化减反层覆盖硅基底，可以有效减少对光的寄生性吸收，起到了良好的钝化减反效果，提升了太阳能电池的短路电流和光电转换效率。并且，局部钝化接触结构仅位于正面电极覆盖的部分，可牺牲部分钝化性能来提升传输性能，局部钝化接触结构只需要关注其电学性能即可，拓宽了制备钝化接触结构的工艺窗口。并且硅基底的背光面为异质结结构，可获得较优的钝化及接触性能。
可选的，所述正面钝化减反层包括层叠设置的正面钝化层和正面减反层；
所述正面钝化层的材料选自：本征非晶硅；所述正面减反层的材料选自：氮化硅、碳化硅、氧化钛、氧化硅、氟化镁、氮氧化硅、TCO中的至少一种。
可选的，所述正面钝化减反层包括层叠设置的正面钝化层和正面减反层；
所述正面钝化层的材料选自：磷硅玻璃、氧化硅、氧化磷、氧化铝和氧化磷，四者中的至少一种；
所述正面减反层的材料选自：氮化硅、碳化硅、氧化钛、氧化硅、氟化镁、氮氧化硅、TCO中的至少一种。
可选的，所述局部钝化接触结构在所述硅基底的向光面上的投影的面积，大于所述正面电极在所述硅基底的向光面上的投影的面积，所述正面钝化减反层还覆盖所述局部钝化接触结构中未被所述正面电极覆盖的区域。
可选的，所述局部钝化接触结构在所述硅基底的向光面上的投影的面积，等于所述正面电极在所述硅基底的向光面上的投影的面积，沿着与所述背面掺杂层和所述背面电极的层叠方向，所述正面钝化减反层与所述局部钝化接触结构平齐分布。
可选的，所述局部钝化接触结构包括：层叠设置的隧穿层和掺杂多晶硅层。
可选的，所述掺杂多晶硅层中还含有碳元素，和/或，氧元素。
可选的，所述太阳能电池还包括：背面TCO层，所述背面TCO层位于所述背面掺杂层上，所述背面电极位于所述背面TCO层上。
本发明的第二方面，提供一种太阳能电池的制备方法，包括：
在硅基底的向光面形成钝化接触结构；
在所述钝化接触结构上形成第一开口，以形成局部钝化接触结构，并使得所述硅基底的向光面部分裸露；
在所述硅基底裸露的向光面上，形成正面钝化减反层，并在所述硅基底的背光面依次形成背面本征钝化层和背面掺杂层；
在局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极。
可选的，所述在所述硅基底裸露的向光面上，形成正面钝化减反层，包括：
在所述局部钝化接触结构以及所述硅基底裸露的向光面上，形成正面钝化减反层，在所述正面减反层的局部区域形成第二开口，使得所述局部钝化接触结构至少部分裸露；
所述在局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极，包括：
在裸露的局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极。
可选的，所述在硅基底的向光面形成钝化接触结构，包括：
在所述硅基底的向光面形成隧穿层；
在所述隧穿层上沉积本征多晶硅层，对所述本征多晶硅层进行掺磷处理，形成掺磷多晶硅层，在掺磷处理的同时，在所述掺磷多晶硅层上，形成正面磷硅玻璃层；所述正面磷硅玻璃层的厚度为10至110nm。
可选的，所述在硅基底的向光面形成钝化接触结构，包括：
在所述硅基底的向光面形成隧穿层；
在所述隧穿层上进行原位掺磷，并退火，形成掺磷多晶硅层，在退火过程中，和/或，退火后，在氧气氛围中，在所述掺磷多晶硅层上热氧化形成正面磷硅玻璃层；所述正面磷硅玻璃层的厚度为10至110nm。
可选的，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
采用激光在所述正面磷硅玻璃层上形成第三开口，以得到磷硅玻璃图案，并使得所述掺磷多晶硅层部分裸露；
所述在所述钝化接触结构上形成第一开口，包括：
以所述磷硅玻璃图案为掩膜层，碱洗裸露的掺磷多晶硅层，以在所述隧穿层和所述掺磷多晶硅层上与所述第三开口对应区域，形成所述第一开口。
可选的，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
在所述正面磷硅玻璃层的局部区域上，丝网印刷图形化掩膜材料，并固化，得到图形化掩膜；或，在所述正面磷硅玻璃层的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜；
在所述图形化掩膜的保护下，采用湿法处理，将所述正面磷硅玻璃层刻蚀为与所述图形化掩膜形状一致的磷硅玻璃图案，使得所述掺磷多晶硅层部分裸露，去除所述图形化掩膜；
所述在所述钝化接触结构上形成第一开口，包括：
以所述磷硅玻璃图案为掩膜层，碱洗裸露的掺磷多晶硅层，以在所述隧穿层和所述掺磷多晶硅层上，形成所述第一开口。
可选的，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
在所述钝化接触结构上形成氮化硅层，在形成所述氮化硅层的过程中，向所述钝化接触结构中填充氢；
采用激光在所述氮化硅层上形成第四开口，以形成氮化硅图案，并使得所述钝化接触结构部分裸露；
所述在所述钝化接触结构上形成第一开口，包括：
以所述氮化硅图案为掩膜层，碱洗裸露的所述钝化接触结构，以在所述钝化接触结构上与所述第四开口对应的区域，形成所述第一开口。
可选的，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
在所述钝化接触结构上形成氮化硅层，在形成所述氮化硅层的过程中，向所述钝化接触结构中填充氢；
在所述氮化硅层的局部区域上，丝网印刷图形化掩膜材料，并固化，得到图形化掩 膜；或，在所述氮化硅层的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜；
在所述图形化掩膜的保护下，采用湿法处理，将所述氮化硅层刻蚀为与所述图形化掩膜形状一致的氮化硅图案，使得所述钝化接触结构部分，去除所述图形化掩膜；
所述在所述钝化接触结构上形成第一开口，包括：
以所述氮化硅层图案为掩膜层，碱洗裸露的所述钝化接触结构，以在所述钝化接触结构上，形成所述第一开口。
可选的，所述图形化掩膜的材料选自：石蜡。
可选的，所述形成与所述背面掺杂层电连接的背面电极之前，所述方法还包括：
在所述背面掺杂层上形成背面TCO层；
所述形成与所述背面掺杂层电连接的背面电极，包括：
在所述背面TCO层上形成所述背面电极。
本发明的第三方面，提供一种光伏组件，包括由若干个任一前述的太阳能电池串联形成的电池串。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本发明实施例中的第一种太阳能电池的结构示意图；
图2示出了本发明实施例中的第三种太阳能电池的结构示意图；
图3示出了本发明实施例中的一种太阳能电池的步骤流程图；
图4示出了本发明实施例中的第一种太阳能电池的制备过程结构示意图；
图5示出了本发明实施例中的第二种太阳能电池的制备过程结构示意图；
图6示出了本发明实施例中的第三种太阳能电池的制备过程结构示意图；
图7示出了本发明实施例中的第四种太阳能电池的制备过程结构示意图；
图8示出了本发明实施例中的第五种太阳能电池的制备过程结构示意图；
图9示出了本发明实施例中的第六种太阳能电池的制备过程结构示意图；
图10示出了本发明实施例中的第七种太阳能电池的制备过程结构示意图；
图11示出了本发明实施例中的第八种太阳能电池的制备过程结构示意图；
图12示出了本发明实施例中的第九种太阳能电池的制备过程结构示意图；
图13示出了本发明实施例中的第十种太阳能电池的制备过程结构示意图；
图14示出了本发明实施例中的第十一种太阳能电池的制备过程结构示意图；
图15示出了本发明实施例中的第十二太阳能电池的制备过程结构示意图；
图16示出了本发明实施例中的第十三种太阳能电池的制备过程结构示意图；
图17示出了本发明实施例中的第十四种太阳能电池的制备过程结构示意图；
图18示出了本发明实施例中的第十五种太阳能电池的制备过程结构示意图；
图19示出了本发明实施例中的第十六种太阳能电池的制备过程结构示意图；
图20示出了本发明实施例中的第十七种太阳能电池的制备过程结构示意图。
附图标记说明：
1-正面电极，2-正面减反射层，3-正面钝化层，4-掺杂多晶硅层或掺磷多晶硅层，5-
隧穿层，6-硅基底，7-背面本征非晶硅钝化层，8-背面掺杂层，9-背面TCO层，10-背面电极，11-PSG层，11-L-磷硅玻璃图案，13-图形化掩膜。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
发明人发现，向光面具有钝化接触结构的太阳能电池，在向光面存在较为严重的接触复合和/或寄生吸收的主要原因在于：向光面的钝化接触结构钝化效果和减反效果欠佳， 导致较为严重的接触复合和/或寄生吸收。
图1示出了本发明实施例中的第一种太阳能电池的结构示意图。图2示出了本发明实施例中的第二种太阳能电池的结构示意图。本发明的太阳能电池包括：硅基底6、正面钝化减反层、局部钝化接触结构、层叠设置的背面本征钝化层7和背面掺杂层8、正面电极1、背面电极10。
针对上述问题，参照图1和图2所示，本发明中，局部钝化接触结构和正面钝化减反层，共同覆盖硅基底6的向光面，且沿着与背面掺杂层8和背面电极10的层叠方向垂直的方向，局部钝化接触结构和正面钝化减反层，在硅基底6的向光面上交替分布。如图1和图2中，背面掺杂层8和背面电极10的层叠方向为上下方向，因此，与背面掺杂层8和背面电极10的层叠方向垂直的方向，可以是图1和图2中的左右方向。在正面电极1接触的部分形成了局部钝化接触结构，可以有效抑制接触复合和表面复合，降低了正面接触区域的接触电阻，提升了太阳能电池开路电压、短路电流和光电转换效率。同时，局部钝化接触结构，可以有效减少对光的寄生性吸收，提升了太阳能电池的短路电流和光电转换效率。正面电极1未覆盖的部分没有形成掺杂，由正面钝化减反层覆盖硅基底6，起到了良好的钝化减反效果，可以进一步降低表面复合和接触复合，提升了短路电流密度，进一步提升太阳能电池的短路电流、开路电压和光电转换效率。并且，局部钝化接触结构仅位于正面电极1覆盖的部分，可牺牲部分钝化性能来提升传输性能，局部钝化接触结构只需要关注其电学性能即可，无需关注光学性能，拓宽了制备钝化接触结构的工艺窗口，拓展了正面钝化接触结构中导电材料的选择范围，且低透光率的导电材料相对于高透光率的导电材料而言，通常成本较低，可以降低太阳能电池的生产成本。同时，层叠设置的背面本征钝化层7和背面掺杂层8，位于硅基底6的背光面，本发明提供的太阳能电池，硅基底6的背光面为异质结结构，获得了较优的钝化及接触性能，进一步提升了太阳能电池的短路电流、开路电压和光电转换效率。例如，本发明制备的太阳能电池的光电转换效率，相对TOPCon(Tunnel Oxide Passivated Contact，隧穿层钝化接触)太阳能电池高约1％abs。太阳能电池的开路电压接近或大于740mV。太阳能电池的短路电流密度提升2mA/cm2左右。
可选的，参照图1和图2所示，正面钝化减反层可以包括层叠设置的正面钝化层3和正面减反层2。局部钝化接触结构可以包括：层叠设置的掺杂多晶硅层4和隧穿层5。
如图1和图2所示的太阳能电池，硅基底6可以为N型单/多晶硅。正面电极1与下方的掺杂多晶硅层4和隧穿层5组成多子端(majority carrier)的局域钝化接触结构。正面钝化层3叠加正面减反射层2起到对除钝化接触区域外部分的钝化作用，以减少载流子的复合，其中，正面减反层2兼顾减少光从向光面逃逸反射的作用。硅基底6的背光面的背面本征非晶硅钝化层7和背面掺杂层8形成异质结结构，其中，背面本征非晶硅钝化层7兼顾钝化作用。背面TCO层9与背面掺杂层8形成接触，并帮助少数载流子的横向传输，背面电极10与背面TCO层9接触导出电流。
太阳光照射到图1或图2所示的太阳能电池的向光面，照射到正面电极1的光大部分被反射回大气，若正面电极1为规则的三角形或梯形，则大部分被反射到邻近正面电极1区域，照射到正面减反层2的光经过折射，可能存在少部分被吸收，透过正面钝化层3进入到N型硅基底6。光在N型硅基底6中激发产生大量多数载流子(电子，electron)和少数载流子(空穴，hole)，载流子产生后在N型硅基底6中自由扩散。其中，部分电子直接运动至隧穿层5处，经N型掺杂多晶硅层4被正面电极1收集。大部分空穴扩散到异质结区附近，或在结区附近产生的载流子，受到N型硅基底6、背面本征非晶硅钝化层7和背面掺杂层8异质结结构产生的内建电场的作用向背光面快速移动。空穴经由结区发射到背面TCO层9并在其中横向传输，然后由背面电极10汇集导出，电子在硅体内横向传输至邻近的由隧穿层5、N型掺杂多晶硅层4组成的局部钝化接触结构并由正面电极1导出。太阳能电池工作过程中，电流的流向为：N型硅基底6→背面电极10→外电路→正面电极1→N型硅基底6。
需要说明的是，此处隧穿层5的材料和制备方法等均可以不作具体限定。例如，隧穿层5可以为隧穿氧化层，隧穿氧化层的制备方式可以为热氧化方式等。
可选的，参照图1所示，局部钝化接触结构在硅基底6的向光面上的投影的面积，大于正面电极1在硅基底6的向光面上的投影的面积，正面钝化减反层还覆盖局部钝化接触结构中未被正面电极1覆盖的区域，即，正面钝化层3，覆盖硅基底6和掺杂多晶硅层4，正面电极1贯穿正面钝化层3和正面减反层2与掺杂多晶硅层4电连接，正面钝化层3和正面减反层2对于局部钝化接触结构进行了保护，进一步提升了钝化接触结构的 钝化性能。
需要说明的是，钝化接触结构在硅基底6的向光面的投影的面积，比正面电极1在硅基底1在硅基底6的向光面的投影的面积，具体大多少不作具体限定。
可选的，参照图2所示，局部钝化接触结构在硅基底6的向光面上的投影的面积，等于正面电极1在硅基底6的向光面上的投影的面积，沿着与背面掺杂层8和所述背面电极10的层叠方向，正面钝化减反层与局部钝化接触结构平齐分布。即，局部钝化接触结构，和层叠设置的正面钝化层3和正面减反层2，刚好共同覆盖硅基底6的向光面，正面电极1设置在掺杂多晶硅层4上，太阳能电池的形式多样。
可选的，正面钝化层3的材料可以选自：PSG(Phospho Silicate Glass，磷硅玻璃)、氧化硅、氧化磷、氧化铝和氧化磷，四者中的至少一种。上述材料均具有起良好的钝化效果，可以进一步降低表面复合，进一步提升太阳能电池的开路电压和光电转换效率。
可选的，正面钝化层3的材料还可以选自：本征非晶硅。上述本征非晶硅具有起良好的钝化效果，可以进一步降低表面复合。
可选的，正面减反层2的材料选自：氮化硅、碳化硅、氧化钛、氧化硅、氟化镁、氮氧化硅、TCO中的至少一种。上述材料具有良好的减反效果，可以进一步降低表面复合和接触复合，提升了短路电流密度，进一步提升太阳能电池的短路电流、开路电压和光电转换效率。
可选的，正面减反层2为单层或叠层结构，正面减反层2结构灵活多样，且减反效果较好。
可选的，沿着远离硅基底6的方向，正面减反层2的折射率减小，正面减反层2的折射率沿着远离硅基底6的方向减小，减反效果更好。
可选的，正面减反层2包括氮化硅膜和氟化镁膜，其中，氮化硅膜靠近硅基底，氟化镁膜的折射率相对于氮化硅膜的折射率更小，减反效果更好，且上述正面减反层2的材料易于获得，成本较低。
可选的，掺杂多晶硅层4中含有碳元素，和/或，氧元素，碳元素、氧元素可以提升掺杂多晶硅层4的带隙，提升掺杂多晶硅层4的透光率和导电性，且易于制备，工艺简单，且成本较低。
可选的，参照图1所示，正面电极1中位于正面钝化层3和正面减反层2中的部分，在硅基底6的向光面的投影的面积，小于或等于正面电极1中凸出于正面钝化层3和正面减反层2的部分，在硅基底6的向光面的投影的面积。上述形状的正面电极1易于加工制得。两个投影的面积具体相差多少不作具体限定。
可选的，硅基底6的向光面中与正面电极1相对的区域为抛光面，其余区域具有绒面结构，硅基底6的向光面中与正面电极1相对的区域被正面电极1所遮挡，为抛光面或具有绒面结构均也不影响光学效果，但是硅基底6的向光面中与正面电极1相对的区域为抛光面，利于其上各层的制备，特别是利于正面电极1的制备。
可选的，背面掺杂层8的材料选自：掺杂非晶硅、掺杂微晶硅、掺杂纳米晶硅中的至少一种，背面掺杂层8的材料选择灵活多样。
可选的，背面掺杂层8和背面本征钝化层7形成异质结，掺杂多晶硅层4和硅基底6形成高低结，本发明的太阳能电池综合了TOPCon电池和HIT电池优点，具有更高的短路电流、开路电压和光电转换效率。对于硅基底6的掺杂类型不作具体限定，例如，硅基底6可以为N型掺杂，则，掺杂多晶硅层4也为N型掺杂，背面掺杂层8为P型掺杂。
可选的，硅基底6为N型硅基底，背面掺杂层8为P型掺杂非晶硅、P型掺杂微晶硅、P型掺杂纳米晶硅中的至少一种，背面掺杂层8的选择性较多。
参照图1和图2所示，太阳能电池还可以包括：背面TCO层9，背面TCO层9位于背面掺杂层8上，背面电极10位于背面TCO层9上，背面TCO层9起到一定的能带适配的作用，利于优化太阳能电池的性能。
可选的，每个正面电极1的宽度为1至50um，正面电极1的长度所在的方向和正面电极1的宽度所在的方向，均与正面钝化层3、正面减反层2的层叠方向垂直，且宽度小于长度。全文所提及的长度、宽度对应的方向均如此定义。正面电极1的宽度为1至50um，对电流的传导能力较好。例如，正面电极1的宽度为1um、5um、13um、20um、25um、31um、39um、46um、50um。
正面电极1和背面电极10在平行于硅基底6的向光面的截面形状可以为方形、半圆型、三角形、梯形，或其他不规则形状。
本发明提供一种如任一上述的太阳能电池的制备方法。图3示出了本发明实施例中 的一种太阳能电池的步骤流程图。参照图3所示，该太阳能电池包括如下步骤：
步骤101，在硅基底的向光面形成钝化接触结构。
图4示出了本发明实施例中的第一种太阳能电池的制备过程结构示意图。图5示出了本发明实施例中的第二种太阳能电池的制备过程结构示意图。图6示出了本发明实施例中的第三种太阳能电池的制备过程结构示意图。图7示出了本发明实施例中的第四种太阳能电池的制备过程结构示意图。图8示出了本发明实施例中的第五种太阳能电池的制备过程结构示意图。图9示出了本发明实施例中的第六种太阳能电池的制备过程结构示意图。图10示出了本发明实施例中的第七种太阳能电池的制备过程结构示意图。图11示出了本发明实施例中的第八种太阳能电池的制备过程结构示意图。图12示出了本发明实施例中的第九种太阳能电池的制备过程结构示意图。图13示出了本发明实施例中的第十种太阳能电池的制备过程结构示意图。图14示出了本发明实施例中的第十一种太阳能电池的制备过程结构示意图。图15示出了本发明实施例中的第十二太阳能电池的制备过程结构示意图。图16示出了本发明实施例中的第十三种太阳能电池的制备过程结构示意图。图17示出了本发明实施例中的第十四种太阳能电池的制备过程结构示意图。图18示出了本发明实施例中的第十五种太阳能电池的制备过程结构示意图。图19示出了本发明实施例中的第十六种太阳能电池的制备过程结构示意图。图20示出了本发明实施例中的第十七种太阳能电池的制备过程结构示意图。说明书附图中所有结构均为示意图，不代表相对大小关系。
参照图4所示，在执行步骤101之前，该方法还可以包括：制绒处理。例如，对电阻率为0.1至10Ω.cm(欧姆.厘米)、厚度为50至400μm的N型硅基底进行制绒工艺，得到织构化表面。例如，该硅基底可以通过对N型直拉法(或区熔法、铸锭法等)制备的单晶硅片进行表面制绒清洗的方式获得。此外，还可以使用含有KOH或NaOH的碱性溶液进行制绒工艺，温度可以为60至85℃。接着采用RCA标准清洗方法中2号溶液，或碱和H2O2混合溶液，对制绒后的硅基底进行表面清洗，去除表面杂质。最后，可以用浓度为0.5-10％HF或NH4HF2溶液，或者该两种溶液中的一种与HCl的混合溶液，去除表面层，获得上述硅基底6。本发明中，对于其余制绒方式不作具体限定。
在硅基底的向光面形成钝化接触结构。参照图5所示，该钝化接触结构可以包括层叠设置的隧穿层5和掺杂多晶硅层4。则，可以先在硅基底6的向光面形成隧穿层5。隧穿层5的制备方式不作限定。可选的，可以采用热氧化、湿法氧化、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积)、ALD(Atomic layer deposition，原子层沉积)中的至少一种，在硅基底6的向光面形成隧穿层5。
例如，隧穿层5热氧化的温度为：200至800℃，湿法氧化的氧化剂可以为HNO3、O3、H2O2等，PECVD中通入的气体SiH4作为硅源，N2O和/或CO2可以作为氧源，ALD中通入的可以是TMS(四甲基硅烷)作为硅源，H2O和/或O3等可以作为氧源。具体的，如热氧化制备方式，将硅基底6置于石英舟中，在300至700℃的温度条件，在硅基底6的表面沉积一层0.5至2nm的氧化硅。其中，沉积所应用的反应气体为O2，其流量可以为0.1至20slm(standard litre per minute，标准状况下，升每分钟)，沉积压力可以为100Pa至常压，具体的热氧化方式可以为恒氧流量、变氧流量等，通氧总时长可以为5至120min。其他隧穿层5的制备方式不作具体限定。
掺杂多晶硅层4的制备方式可以为：先形成低晶化率的本征多晶硅，然后再制备得到高晶化率的掺杂多晶硅层4，也可以一次性形成高晶化率的掺杂多晶硅层4。
可选的，硅基底6为N型硅基底，掺杂多晶硅层4的制备方式可以为：在隧穿层5上沉积本征多晶硅层。对本征多晶硅层进行掺磷处理，形成掺磷多晶硅层4。在掺磷处理过程中，可以额外掺杂氧、碳等无机元素。如图6所示，在掺磷处理的同时，在掺磷多晶硅层4上，形成PSG(Phospho Silicate Glass，磷硅玻璃)层11，PSG层11的厚度为10至110nm。本征多晶硅的制备方式包括但不限于APCVD(Atmospheric Pressure Chemical Vapor Deposition，常压化学气相沉积)、LPCVD(Low Pressure Chemical Vapor Deposition低压力化学气相沉积法)、PECVD、PVD等。例如，LPCVD的反应温度可以为400至700℃，通入气体可以为SiH4，PECVD通入气体可以为SiH4。具体的，如LPCVD制备本征多晶硅层，在制备完隧穿层5后直接进行制备，隧穿层5和本征多晶硅可集成一次工艺完成。具体的在400至700℃温度条件下，在隧穿层5上沉积一层厚度为10至300nm的本征多晶硅层。该本征多晶硅层的优选厚度为50至200nm。上述沉积本征多晶硅层时应用的反应气体为SiH4，其流量为50至1000sccm，沉积压力为100至400Pa，时间为2至60min。采用LPCVD制备时，插片方式可以为一槽单片或双片，插片方式不会 对本工艺流程造成较大影响。其他本征多晶硅的制备方式不作具体限定。
可选的，掺磷处理可以包括：磷扩散，或，印刷磷浆并退火。如，采用磷扩散(POCl3)工艺，或印刷磷浆后退火等，形成掺杂多晶硅层4。
例如，PSG层11的厚度可以为10至50nm，再例如，PSG层11的厚度可以为10nm、30nm、40nm、45nm、50nm、60nm、80nm、90nm、100nm、110nm。具体的，在热扩散炉管中，通过POCl3热扩散经预沉积和推进在N型硅基底6的表面的隧穿层5上形成掺磷多晶硅层4、以及在掺磷多晶硅层4上形成PSG层11。具体的，可以是先沉积本征非晶硅，然后再进行掺磷处理，掺磷处理的过程为：先在本征非晶硅层上预沉积磷源，预沉积磷源会在本征非晶硅层上形成PSG，然后推进，PSG中的磷会推进至本征非晶硅层中，推进过程伴随晶化，形成掺磷多晶硅层。可选的，预沉积磷源的温度为700至850℃，沉积时长为5至100min。推进温度为700至1100℃，推进时长为15至150min，推进压力为100至400Pa。例如，预沉积磷源的温度为：700℃、720℃、760℃、780℃、790℃、800℃、820℃、830℃、840℃、850℃，沉积时长为5min、8min、10min、20min、28min、37min、42min、50min、60min、70min、80min、100min，推进温度为：700℃、720℃、760℃、780℃、790℃、800℃、820℃、830℃、840℃、850℃、930℃、970℃、1000℃、1020℃、1048℃、1100℃，推进时长可以为：15min、18min、20min、32min、38min、47min、55min、63min、75min，推进压力为100Pa、120Pa、140Pa、200Pa、230Pa、280Pa、300Pa、380Pa、400Pa。然后测量含有PSG层11的硅基底6的方块电阻为10至500Ω/sq(欧姆/平方米)。
可选的，掺杂多晶硅层4的制备方式还可以为：在隧穿层5上进行原位掺磷，并退火，形成掺磷多晶硅层4。在隧穿层5上沉积原位掺磷非晶硅层和/或多晶硅层包括但不限于APCVD、LPCVD、PECVD、PVD等工艺。PECVD的工艺温度为400至700℃，通入气体为SiH4。具体的，如LPCVD制备原位掺磷多晶硅，制备完隧穿氧化硅后直接进行制备，隧穿层5和原位掺磷多晶硅可集成一次工艺完成。具体的，在400至700℃温度条件下，在隧穿层5上沉积一层10至300nm的原位掺磷多晶硅层。该多晶硅层的优选厚度可以为50至200nm。上述沉积多晶硅层时应用的反应气体为SiH4和PH3，SiH4和PH3流量分别为50至1000sccm和2至40sccm，沉积压力为100至400Pa，时间为5至120min。采用LPCVD制备时，插片方式可以为一槽单片或双片，插片方式不会对本工艺流程造成较大影响。其他原位掺杂多晶硅的制备方式不作具体限定。
可选的，在隧穿层5上沉积原位掺磷非晶硅层和/或多晶硅层，然后退火制备高晶化率的掺磷多晶硅层4，可以在退火过程中，和/或，退火结束后，通氧气，在氧气氛围中，在掺磷多晶硅层4表面生成一定厚度的PSG层11。具体的，在热退火炉管中，通N2进行晶化处理，之后通O2在N型掺杂多晶硅层4上形成PSG层11。其中热退火及氧化的温度为700至1100℃，退火时长为15至120min，热氧化时长为15至120min，工艺压力为100Pa至常压。PSG层11的厚度为5至50nm，然后测量含有PSG层11的硅基底6的方块电阻为10至1000Ω/sq。需要说明的是，在原位掺磷过程中，可以额外掺杂氧、碳等无机元素。
步骤102，在所述钝化接触结构上形成第一开口，以形成局部钝化接触结构，并使得所述硅基底的向光面部分裸露。
在钝化接触结构包括层叠设置的隧穿层5和掺杂多晶硅层4的情况下，也就是在隧穿层5和掺杂多晶硅层4上形成第一开口，使得硅基底6的向光面裸露，形成第一开口的方式不作具体限定。该步骤就形成了局部钝化接触结构。例如，可以为激光开口，或者掩膜然后湿法刻蚀等。
可选的，参照图7所示，在掺杂多晶硅层4表面生成PSG层11，采用激光在PSG层11上形成第三开口，以得到磷硅玻璃图案，即PSG图案11-L，并使得掺磷多晶硅层4部分裸露。参照图8所示，以PSG图案11-L为掩膜层，碱洗裸露的掺磷多晶硅层4，以在隧穿层5和掺杂多晶硅层4上与第三开口对应的区域，形成第一开口。在形成掺磷多晶硅4的过程中或借用形成掺磷多晶硅4的工艺条件等，形成作为掩膜层的PSG层11，工艺简单。形成第一开口后，采用碱如KOH或NaOH等，将隧穿层5和掺杂多晶硅层4上与第三开口对应的局部区域洗掉，形成第一开口。在形成第一开口的过程中，在掩膜层PSG层11的保护下，碱性溶液还对裸露的部分硅基底6的向光面进行了制绒。
例如，将形成有第三开口的PSG层11的硅基底置于槽式或链式清洗机中，在60至85℃的温度条件下，并在形成有第三开口的PSG掩膜层的保护下，使用含有KOH或NaOH的碱性溶液，形成第一开口，并对裸露的部分硅基底6的向光面进行了二次制绒工艺。 碱刻蚀之前，为了得到更优表面形貌，还可以进行碱抛光预处理。制绒之后还可以采用RCA标准清洗方法中2号溶液(或碱和H2O2混合溶液)，对二次制绒后的硅基底进行表面清洗，去除表面杂质。最后，通过HF或NH4HF2(或其与HCl的混合溶液)清洗，将形成有第三开口的PSG层11完全去除。
可选的，形成第一开口之前，该方法还可以包括：在掺磷多晶硅层4上形成氮化硅层，在形成氮化硅层的过程中，向掺杂多晶硅层4中填充氢，使得掺杂多晶硅层4的钝化性能进一步提升。然后，采用激光在氮化硅层上形成第四开口，以形成氮化硅图案，并使得掺杂多晶硅层4部分裸露。上述步骤102可以包括：以形成有第四开口的氮化硅层即氮化硅图案，为掩膜层，碱洗裸露的掺杂多晶硅层4，以在隧穿层5和掺杂多晶硅层4上与第四开口对应的局部区域，形成第一开口。在形成第一开口的过程中，在掩膜层氮化硅层的保护下，碱性溶液还对裸露的部分硅基底6的向光面进行了制绒。制绒之后还可以采用RCA标准清洗方法中2号溶液(或碱和H2O2混合溶液)，对二次制绒后的硅基底进行表面清洗，去除表面杂质。最后，可以采用酸将氮化硅层去除。
可选的，激光的波长为100至800nm，脉宽100fs至1ms，频率为100kHz至100MHz，上述激光更为常见，成本更低，且对于PSG层11和氮化硅层均易于形成开口。
可选的，此处激光的波长可以为532nm或355nm，脉宽可以为1ps至500ns，激光光斑形状为方形或圆形，光斑的长度或直径为10至500μm，输出功率为1至100W，线速度为1至100m/s。上述激光更为常见，成本更低，且对于PSG层和氮化硅层均易于形成开口。
例如，形成第四开口的激光的脉宽为1ps、300ps、1100ps、2ns、2.5ns、250ns、360ns、440ns、500ns中的一种，激光光斑形状为方形或圆形，光斑的长度或直径为10μm、23μm、65μm、146μm、250μm、255μm、300μm、378μm、500μm，输出功率为1W、20W、48W、50W、63W、74W、87W、100W，线速度为1m/s、21m/s、45m/s、50m/s、56m/s、70m/s、80m/s、86m/s、90m/s、100m/s。
可选的，掺磷多晶硅层4表面生成有PSG层11，参照图9所示，形成第一开口之前，该方法还可以包括：在PSG层11的局部区域上，采用丝网印刷图形化掩膜材料，并固化，得到图形化掩膜13；或，在PSG层11的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜13。需要说明的是，喷墨打印设备的头部通常就具有加热或固化功能，因此，喷墨打印图形化掩膜材料后可以不再进行固化。具体的，如丝网印刷方式，在上述PSG层11的局部区域上印刷图形化掩膜材料，并将印刷有图形化掩膜材料的硅基底置于烘干炉中烘干、固化，烘干温度为150至250℃，时间为0.2至10min，以形成与正面电极1的形状相匹配，或略大于正面电极1的图形化掩膜13。其他图形化掩膜13的制备方式在此不做赘述。
可选的，该图形化掩膜13的材料选自：石蜡，石蜡易于丝网印刷或喷墨打印，且易于固化，后续容易去除，同时成本较低。对于图形化掩膜的材料的其他选择不作具体限定。
可选的，参照图10所示，形成图形化掩膜13之后，在图形化掩膜的保护下，采用湿法处理，将PSG层11刻蚀为与图形化掩膜13形状一致的磷硅玻璃图案11-L，使得掺磷多晶硅层4部分裸露，去除图形化掩膜13。去除图形化掩膜13可以采用浓度为1至10％的NH3·H2O(或KOH/NaOH)与浓度为2至20％的H2O2的混合溶液，在室温至80℃去除。
可选的，参照图11所示，前述步骤102可以包括：以磷硅玻璃图案11-L为掩膜层，碱洗裸露的掺磷多晶硅层4，以在隧穿层5和掺磷多晶硅层上的局部区域，形成第一开口。磷硅玻璃图案11-L可以经过浓度为0.5-10％的HF(或NH4HF2)溶液去除。
例如，在磷硅玻璃图案11-L的保护下，在60至85℃的温度条件下，使用含有KOH或NaOH的碱性溶液，形成第一开口，并对裸露的部分硅基底6的向光面和硅基底6的背光面进行了二次制绒工艺或刻蚀工艺。
可选的，前述步骤102之前，该方法还可以包括：在掺杂多晶硅层4上形成氮化硅层，在形成氮化硅层的过程中，向掺杂多晶硅层4中填充氢，以进一步提升钝化接触结构的钝化性能。在氮化硅层的局部区域上，采用丝网印刷图形化掩膜材料，并固化，得到图形化掩膜；或，在氮化硅层的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜。在图形化掩膜的保护下，采用湿法处理，将氮化硅层刻蚀为与图形化掩膜形状一致的氮化硅图案，使得掺杂多晶硅层部分裸露，去除图形化掩膜。上述步骤102可以包括：以氮化硅层图案为掩膜层，碱洗裸露的掺杂多晶硅层，以在隧穿层5和掺杂多晶硅 层4上的局部区域，形成第一开口。此处的相关步骤可以参照前述有关记载，为了避免重复，此处不再赘述。
需要说明的是，上述形成第一开口的工艺易于实现量产，大幅度提升生产效率，特别是，形成图形化掩膜13的工艺，更易于实现量产，提升生产效率。
步骤103，在所述硅基底裸露的向光面上，形成正面钝化减反层，并在所述硅基底的背光面依次形成背面本征钝化层和背面掺杂层。
在硅基底6裸露的向光面上形成正面钝化减反层，并在硅基底6的背光面依次形成背面本征钝化层7和背面掺杂层8。
可选的，该步骤103还可以包括：在局部钝化接触结构以及硅基底6裸露的向光面上，形成正面钝化减反层，在正面减反层的局部区域形成第二开口，使得局部钝化接触结构至少部分裸露。正面钝化减反层可以包括：正面钝化层3和正面减反层2。
在正面钝化层3的材料选自：PSG、氧化硅、氧化磷、氧化铝和氧化磷，四者中的至少一种的情况下，上述步骤103中形成正面钝化减反层，并在硅基底6的背光面依次形成背面本征钝化层7和背面掺杂层8可以参照图12至图15所示。
具体的，如图12、图13所示，在掺杂多晶硅层4以及裸露的硅基底6上依次形成正面钝化层3和正面减反层2。正面钝化层3可以采用热氧化等。如，热氧化法制备SiO2正面钝化层3，在管式设备中，反应温度为500至1000℃，氧气流量为0.1至20slm(standard litre per minute，标准状态下L/min)，反应时间为10至120min，制备的正面钝化层3的厚度为1至50nm。
在正面钝化层3上形成正面减反层2，形成正面减反层2的方式包括但不限于PECVD制备的SiNx、SiCx、TiOx或其他折射率接近的膜层，最外层亦可叠加SiOx和MgF2等更低折射率的膜层改善减反射效果。SiOx可以由PECVD或ALD制备，MgF2可以由PVD制备。本发明中化学式中的x均为大于0的数。
具体的，如制备单一SiNx材料的减反膜，将上述结构置于PECVD中，沉积温度为200至600℃，反应气体为SiH4和NH3的混合气体，其总流量为100至50000sccm，体积比为(1:2)至(1:40)，电源功率为1至20kW，压力为20至400Pa，最终制备出正面减反层2的厚度为50至90nm。其他的正面减反层2的制备方式不作具体限定。厚度所在的方向与隧穿层5和掺杂多晶硅层4的层叠方向平行，全文所提及的厚度，其所在的方向均同此定义。
需要说明的是，图12承接了前述的图11，图13承接前述的图8。
参照图14所示，对硅基底6的背光面可能形成的隧穿层、钝化层、减反层进行清洗。此处包括但不限于金字塔绒面、酸刻蚀表面、碱抛光表面。其中，金字塔绒面可直接通过单面或双面HF溶液清洗，去除背面绕镀层，再进行表面修饰，如HNO3、HF表面圆化处理。酸刻蚀表面即直接采用链式单面刻蚀工艺，工艺槽中包括HNO3、HF等溶质，形成具有一定粗糙度的表面。碱抛光表面即进行碱溶液体系如KOH或NaOH等的抛光工艺，形成较平整的表面。
参照图15所示，在硅基底6的背光面沉积背面本征钝化层7，包括但不限于PECVD、HWCVD(hot wire chemical vapor deposition热丝化学气相沉积)PVD、Cat-CVD(catalytic chemical vapor deposition，催化化学气相沉积)、ALD或溶液法等方法。其中，HWCVD的工艺温度为100至250℃，通入气体为SiH4、H2等。如采用PECVD方法沉积一层2至16nm的背面本征钝化层7，反应气体为SiH4和H2，混合气体中SiH4和H2的体积比为(1:1)至(1:50)，电源功率密度为0.01至0.5W/cm2，压力为20至200Pa，反应温度为100至200℃。
在背面本征钝化层7上形成背面掺杂层8。背面掺杂层8为：非晶硅掺杂层、微晶硅掺杂层、纳米晶硅掺杂层中的一种。例如，背面掺杂层8可以为磷掺杂的非晶/微晶/纳晶硅薄膜，在此基础上还可以掺杂有氧、碳元素等。背面掺杂层8的形成方式包括但不限于PECVD、HWCVD、Cat-CVD、PVD、ALD或溶液法等方法。HWCVD的工艺温度为100至250℃，通入气体为SiH4、H2等。具体的，在背面本征非晶硅钝化层7表面继续沉积10至40nm的P型非晶、微晶、纳米晶掺杂层，反应气体为SiH4、H2和B2H6，混合气体中SiH4和H2的体积比为(1:1)至(1:50)，SiH4和B2H6的体积比为(5:1)至(100:1)，电源功率密度为0.01至0.2W/cm2，压力为20至200Pa，反应温度为100至200℃。
在正面钝化层3的材料选自：本征非晶硅的情况下，上述步骤103中形成正面钝化减反层，并在硅基底6的背光面依次形成背面本征钝化层7和背面掺杂层8可以参照图16至图19所示。
具体的，参照图16所示，在硅基底6的背光面沉积背面本征钝化层7，形成背面本征钝化层7的方式可以参照前述有关记载，为了避免重复，此处不再赘述。
参照图17所示，在掺杂多晶硅层4以及硅基底6裸露的向光面上，形成正面本征钝化层3，形成正面本征钝化层3的方式可以参照形成背面本征钝化层7的方式，此处不再赘述。形成正面本征钝化层3和形成背面本征钝化层7可以同步进行，在本发明中，对此不作具体限定。
参照图18所示，在正面本征钝化层3上形成正面减反层2，形成正面减反层2的方式可以参照前述对于正面减反层2的形成方式，为了避免重复，此处不再赘述。
参照图19所示，在背面本征钝化层7上形成背面掺杂层8，对于背面掺杂层8的形成方式参照前述有关记载，为了避免重复，此处不再赘述。
在钝化接触结构上也形成正面钝化减反层的情况下，该方法还可以包括：在正面减反层的局部区域形成第二开口，使得局部钝化接触结构至少部分裸露。如，在正面减反层和正面钝化层的局部区域形成第二开口，使得所述掺杂多晶硅层至少部分裸露。
参照图20所示，在正面减反层2和正面钝化层3的局部区域形成第二开口，使得掺杂多晶硅层4至少部分裸露。此处可以是将全部的多晶硅层4裸露，或者，将部分的多晶硅层4裸露。如，参照图20所示，是将部分的多晶硅层4裸露。
形成第二开口的方式可以为激光开口，或者，设置湿法处理等。如，采用激光、印刷腐蚀浆料、喷涂腐蚀浆料，三者中的至少一种，对正面钝化层3和正面减反层2的局部区域开口。
可选的，第二开口通过开口，激光开口工艺简单。可选的，激光波长为100至800nm，脉宽100fs至1ms，频率为100kHz至100MHz。
可选的，激光的波长为532nm或355nm，脉宽为1ps至500ns，激光光斑形状为方形或圆形，光斑的长度或直径为0.5至30μm，输出功率为1至20W，线速度为1至100m/s。该第二开口的宽度为1至40微米。该宽度所在的方向与隧穿层5和掺杂多晶硅层4的层叠方向垂直。例如，形成第二开口的激光的脉宽为1ps、300ps、1100ps、2ns、2.5ns、250ns、360ns、440ns、500ns中的一种，激光光斑形状为方形或圆形，光斑的长度或直径为0.5μm、3μm、6.5μm、14.6μm、15μm、15.5μm、21μm、27.5μm、30μm，输出功率为1W、8W、9.9W、10W、10.3W、14W、17W、20W，线速度为1m/s、21m/s、45m/s、50m/s、56m/s、70m/s、80m/s、86m/s、90m/s、100m/s。
激光开口形成第二开口之后，还可以通过湿法去除激光区域形成的层，如，用HF、HNO3、HCl等低浓度酸液，短时间清洗含有第二开口的结构。
步骤104，在局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极。
在钝化接触结构上也形成正面钝化减反层，并形成第二开口的情况下，该步骤104可以包括：在裸露的掺杂多晶硅层上形成正面电极，并形成与背面掺杂层电连接的背面电极。
如参照图1或图2所示，在裸露的掺杂多晶硅层4上形成正面电极1，并形成与背面掺杂层8电连接的背面电极10。形成正面电极1和背面电极10的方式均包括但不限于丝网印刷、激光转印、电镀、蒸镀，还可以结合其他图形化手段，如光刻蚀等。
本发明形成的太阳能电池后续还以包括的处理工艺包括但不限于：固化(solidification)、烧结(firing)、光注入(Light-Induced Regeneration)、电注入(Electric-Induced Regeneration)或暗态退火(dark annealing)等。本发明对此不作具体限定。
可选的，参照图20所示，形成背面掺杂层8之后，该方法还可以包括：在背面掺杂层8上形成背面TCO层9。形成背面电极10可以包括：在背面TCO层9上形成背面电极10。在背面掺杂层8上形成背面TCO层9可以为：在背面掺杂层8的背光面沉积ITO、IWO、FTO、AZO等金属氧化物或其混合物，或其他功函数介于P型非晶/微晶/纳晶硅的背面掺杂层8和背面电极10的材料，背面TCO层9的形成方式包括但不限于磁控溅射、RPD(Reactive Plasma Deposition，反应等离子体沉积)、真空蒸发、PECVD、ALD等制备方法。如，采用PVD方法在背面掺杂层8上沉积75nm的ITO，ITO中In元素的质量:Sn元素的质量＝(1:1)至(20:1)，ITO中还充入Ar和O2，制备ITO过程中，O2和Ar的流量比为0.01至0.2，压力0.1至5Pa，硅基底6的温度为室温。
需要说明的是，背面TCO层9还可以是在形成背面掺杂层8之后，形成第二开口之前进行制备，本发明实施例对此不作具体限定。
正面电极1、背面电极10的材料可以为Ag、Al、Cu、Au等具有良好导电性的金属与合金。
本发明还提供一种光伏组件，该光伏组件包括由若干个任一前述的太阳能电池串联形成的电池串。该光伏组件与任一前述的太阳能电池、任一前述的太阳能电池的制备方法具有相同或相似的有益效果，且三者之间，相关之处可以相互参照，为了避免重复，此处不再赘述。
下面结合具体的实施例，进一步解释说明本发明：
实施例
参照图4所示，对硅基底6进行制绒处理。参照图5、图6所示，在硅基底6的向光面形成隧穿层5和掺杂多晶硅层4，并在掺杂多晶硅层4上形成PSG层11。参照图7所示，采用激光在PSG层11上形成第三开口，以得到磷硅玻璃图案，即PSG图案11-L，并使得掺磷多晶硅层4部分裸露。参照图8所示，以PSG图案11-L为掩膜层，碱洗裸露的掺磷多晶硅层4，以在隧穿层5和掺杂多晶硅层4上与第三开口对应的区域，形成第一开口。参照图13所示，在掺杂多晶硅层4以及裸露的硅基底6上依次形成正面钝化层3和正面减反层2。参照图14所示，对硅基底6的背光面可能形成的隧穿层、钝化层、减反层进行清洗。参照图15所示，在硅基底6的背光面依次形成背面本征钝化层7、背面掺杂层8、背面TCO层9。参照图20，在正面减反层2和正面钝化层3的局部区域形成第二开口，使得掺杂多晶硅层4全部裸露。参照图2所示，在裸露的掺杂多晶硅层4上形成正面电极1，并形成与背面掺杂层8电连接的背面电极10。
表1：实施例中的太阳能电池电性能与TOPCon及HJT电池最高纪录数据对比表
表1中FZ(Float Zone)是区域熔融法或区熔法拉制单晶，CZ是直拉法拉制单晶。P-FZ是指硅基底为P型浮区法或区域熔融法拉制的单晶，N-FZ是指硅基底为N型浮区法或区域熔融法拉制的单晶，P-CZ是指硅基底为P型直拉法拉制的单晶，N-CZ是指硅基底为N型直拉法拉制的单晶，N-type是指N型掺杂的硅基底，硅基底的制备方式不限定。通过上述对比可以得出，相对于TOPCon及HJT电池，本发明中的太阳能电池的光电转换效率明显较高，电流密度明显较高，填充因子明显较高，主要原因在于，本发明中的太阳能电池中，在正面电极1接触的部分形成了局部钝化接触结构，可以有效抑制接触复合和表面复合。正面电极1未覆盖的部分没有形成掺杂，由正面钝化层3、正面减反层2覆盖硅基底6，可以有效减少对光的寄生性吸收，起到了良好的钝化减反效果，提升了短路电流密度，进一步提升太阳能电池的短路电流和光电转换效率。同时，本发明提供的太阳能电池，硅基底6的背光面还可以为异质结结构，可获得较优的钝化及接触性能。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定都是本申请实施例所必须的。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (19)

  1. 一种太阳能电池，其特征在于，包括：硅基底、正面钝化减反层、局部钝化接触结构、层叠设置的背面本征钝化层和背面掺杂层、正面电极、背面电极；
    所述局部钝化接触结构和所述正面钝化减反层，共同覆盖所述硅基底的向光面，且沿着与所述背面掺杂层和所述背面电极的层叠方向垂直的方向，所述局部钝化接触结构和所述正面钝化减反层，在所述硅基底的向光面上交替分布；
    所述层叠设置的背面本征钝化层和背面掺杂层，位于所述硅基底的背光面；
    所述正面电极位于所述局部钝化接触结构上；
    所述背面电极与所述背面掺杂层电连接。
  2. 根据权利要求1所述的太阳能电池，其特征在于，所述正面钝化减反层包括层叠设置的正面钝化层和正面减反层；
    所述正面钝化层的材料选自：本征非晶硅；所述正面减反层的材料选自：氮化硅、碳化硅、氧化钛、氧化硅、氟化镁、氮氧化硅、TCO中的至少一种。
  3. 根据权利要求1所述的太阳能电池，其特征在于，所述正面钝化减反层包括层叠设置的正面钝化层和正面减反层；
    所述正面钝化层的材料选自：磷硅玻璃、氧化硅、氧化磷、氧化铝和氧化磷，四者中的至少一种；
    所述正面减反层的材料选自：氮化硅、碳化硅、氧化钛、氧化硅、氟化镁、氮氧化硅、TCO中的至少一种。
  4. 根据权利要求1所述的太阳能电池，其特征在于，所述局部钝化接触结构在所述硅基底的向光面上的投影的面积，大于所述正面电极在所述硅基底的向光面上的投影的面积，所述正面钝化减反层还覆盖所述局部钝化接触结构中未被所述正面电极覆盖的区域。
  5. 根据权利要求1所述的太阳能电池，其特征在于，所述局部钝化接触结构在所述硅基底的向光面上的投影的面积，等于所述正面电极在所述硅基底的向光面上的投影的面积，沿着与所述背面掺杂层和所述背面电极的层叠方向，所述正面钝化减反层与所述局部钝化接触结构平齐分布。
  6. 根据权利要求1至5中任一所述的太阳能电池，其特征在于，
    所述局部钝化接触结构包括：层叠设置的隧穿层和掺杂多晶硅层。
  7. 根据权利要求6所述的太阳能电池，其特征在于，所述掺杂多晶硅层中还含有碳元素，和/或，氧元素。
  8. 根据权利要求1至5中任一所述的太阳能电池，其特征在于，所述太阳能电池还包括：背面TCO层，所述背面TCO层位于所述背面掺杂层上，所述背面电极位于所述背面TCO层上。
  9. 一种太阳能电池的制备方法，其特征在于，包括：
    在硅基底的向光面形成钝化接触结构；
    在所述钝化接触结构上形成第一开口，以形成局部钝化接触结构，并使得所述硅基底的向光面部分裸露；
    在所述硅基底裸露的向光面上，形成正面钝化减反层，并在所述硅基底的背光面依次形成背面本征钝化层和背面掺杂层；
    在局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极。
  10. 根据权利要求9所述的太阳能电池的制备方法，其特征在于，所述在所述硅基底裸露的向光面上，形成正面钝化减反层，包括：
    在所述局部钝化接触结构以及所述硅基底裸露的向光面上，形成正面钝化减反层，在所述正面减反层的局部区域形成第二开口，使得所述局部钝化接触结构至少部分裸露；
    所述在局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极，包括：
    在裸露的局部钝化接触结构上形成正面电极，并形成与所述背面掺杂层电连接的背面电极。
  11. 根据权利要求9所述的太阳能电池的制备方法，其特征在于，所述在硅基底的 向光面形成钝化接触结构，包括：
    在所述硅基底的向光面形成隧穿层；
    在所述隧穿层上沉积本征多晶硅层，对所述本征多晶硅层进行掺磷处理，形成掺磷多晶硅层，在掺磷处理的同时，在所述掺磷多晶硅层上，形成正面磷硅玻璃层；所述正面磷硅玻璃层的厚度为10至110nm。
  12. 根据权利要求9所述的太阳能电池的制备方法，其特征在于，所述在硅基底的向光面形成钝化接触结构，包括：
    在所述硅基底的向光面形成隧穿层；
    在所述隧穿层上进行原位掺磷，并退火，形成掺磷多晶硅层，在退火过程中，和/或，退火后，在氧气氛围中，在所述掺磷多晶硅层上热氧化形成正面磷硅玻璃层；所述正面磷硅玻璃层的厚度为10至110nm。
  13. 根据权利要求11或12所述的太阳能电池的制备方法，其特征在于，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
    采用激光在所述正面磷硅玻璃层上形成第三开口，以得到磷硅玻璃图案，并使得所述掺磷多晶硅层部分裸露；
    所述在所述钝化接触结构上形成第一开口，包括：
    以所述磷硅玻璃图案为掩膜层，碱洗裸露的掺磷多晶硅层，以在所述隧穿层和所述掺磷多晶硅层上与所述第三开口对应区域，形成所述第一开口。
  14. 根据权利要求11或12所述的太阳能电池的制备方法，其特征在于，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
    在所述正面磷硅玻璃层的局部区域上，丝网印刷图形化掩膜材料，并固化，得到图形化掩膜；或，在所述正面磷硅玻璃层的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜；
    在所述图形化掩膜的保护下，采用湿法处理，将所述正面磷硅玻璃层刻蚀为与所述图形化掩膜形状一致的磷硅玻璃图案，使得所述掺磷多晶硅层部分裸露，去除所述图形化掩膜；
    所述在所述钝化接触结构上形成第一开口，包括：
    以所述磷硅玻璃图案为掩膜层，碱洗裸露的掺磷多晶硅层，以在所述隧穿层和所述掺磷多晶硅层上，形成所述第一开口。
  15. 根据权利要求9所述的太阳能电池的制备方法，其特征在于，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
    在所述钝化接触结构上形成氮化硅层，在形成所述氮化硅层的过程中，向所述钝化接触结构中填充氢；
    采用激光在所述氮化硅层上形成第四开口，以形成氮化硅图案，并使得所述钝化接触结构部分裸露；
    所述在所述钝化接触结构上形成第一开口，包括：
    以所述氮化硅图案为掩膜层，碱洗裸露的所述钝化接触结构，以在所述钝化接触结构上与所述第四开口对应的区域，形成所述第一开口。
  16. 根据权利要求9所述的太阳能电池的制备方法，其特征在于，所述在所述钝化接触结构上形成第一开口之前，所述方法还包括：
    在所述钝化接触结构上形成氮化硅层，在形成所述氮化硅层的过程中，向所述钝化接触结构中填充氢；
    在所述氮化硅层的局部区域上，丝网印刷图形化掩膜材料，并固化，得到图形化掩膜；或，在所述氮化硅层的局部区域上，喷墨打印图形化掩膜材料，得到图形化掩膜；
    在所述图形化掩膜的保护下，采用湿法处理，将所述氮化硅层刻蚀为与所述图形化掩膜形状一致的氮化硅图案，使得所述钝化接触结构部分，去除所述图形化掩膜；
    所述在所述钝化接触结构上形成第一开口，包括：
    以所述氮化硅层图案为掩膜层，碱洗裸露的所述钝化接触结构，以在所述钝化接触结构上，形成所述第一开口。
  17. 根据权利要求16所述的太阳能电池的制备方法，其特征在于，所述图形化掩膜 的材料选自：石蜡。
  18. 根据权利要求9至12、15至17中任一所述的太阳能电池的制备方法，其特征在于，所述形成与所述背面掺杂层电连接的背面电极之前，所述方法还包括：
    在所述背面掺杂层上形成背面TCO层；
    所述形成与所述背面掺杂层电连接的背面电极，包括：
    在所述背面TCO层上形成所述背面电极。
  19. 一种光伏组件，其特征在于，包括由若干个权利要求1至8中任一所述的太阳能电池串联形成的电池串。
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