WO2024036797A1 - 应用于存储器的写调平电路、及其控制方法 - Google Patents

应用于存储器的写调平电路、及其控制方法 Download PDF

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Publication number
WO2024036797A1
WO2024036797A1 PCT/CN2022/132674 CN2022132674W WO2024036797A1 WO 2024036797 A1 WO2024036797 A1 WO 2024036797A1 CN 2022132674 W CN2022132674 W CN 2022132674W WO 2024036797 A1 WO2024036797 A1 WO 2024036797A1
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signal
write
data strobe
indication
sampling
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PCT/CN2022/132674
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English (en)
French (fr)
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张志强
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长鑫存储技术有限公司
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Priority to US18/513,533 priority Critical patent/US20240087627A1/en
Publication of WO2024036797A1 publication Critical patent/WO2024036797A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the present disclosure relates to the field of memory technology, and in particular, to a write leveling circuit applied to a memory and a control method thereof.
  • write leveling Writing Leveling
  • DQS Data Strobe Signal
  • the time difference between the valid edge of the DQS signal and the valid edge of the clock signal received by the memory meets the requirements of the memory specification.
  • the write leveling process of the memory can be divided into external write leveling and internal write leveling. In the process of internal write leveling, it is necessary to determine the shortened column write latency based on the original column write latency (CWL) of the memory and the reduction time of the column write latency, and based on the reduction The write signal is delayed for the subsequent column write latency period.
  • the present disclosure provides a write leveling circuit applied to a memory and a control method thereof to solve the problem in the related art that the column write latency period and column write latency period of the memory are shortened during the internal write leveling process of the memory.
  • the time specifications of the time are inconsistent, resulting in the problem that internal write leveling cannot be achieved.
  • the present disclosure provides a write leveling circuit method applied to a memory, including:
  • a write signal generating unit configured to receive a first clock signal and a first indication signal, and generate the first write signal according to the first clock signal, the first indication signal, and a specified bit in the first indication signal. The signal is delayed and a second write signal is output; wherein, the first indication signal is used to indicate the shortening time of the column write latency period of the memory, and the first indication signal includes a specified bit; the character of the specified bit is used Instructing that the shortening time is an odd number multiple of the clock cycle of the first clock signal or that the shortening time is an even multiple of the clock cycle of the first clock signal;
  • a sampling unit connected to the write signal generating unit, is used to receive a first data strobe signal and the second write signal, and output a second data strobe signal according to the first data strobe signal and the second write signal. sample signal.
  • the present disclosure provides a control method for a write leveling circuit applied to a memory.
  • the method is applied to the circuit as described in the first aspect, and the method includes:
  • the time delay of the first data strobe signal is extended by a preset period, and the extended signal is determined to be the memory. Data strobe signal received during write operation.
  • the present disclosure provides a memory including the write leveling circuit according to any one of the first aspects.
  • the present disclosure provides a control device applied to a write leveling circuit of a memory.
  • the device is applied to the circuit described in the first aspect, and the device includes:
  • an adjustment unit configured to adjust the delay of the first data strobe signal or the first data strobe signal if it is determined that the second sampling signal represents the effective edge of the first data strobe signal and the effective edge of the second write signal are not aligned. Instruction signal; repeat the first adjustment unit until the first adjustment unit determines that the effective edge of the first data strobe signal is aligned with the effective edge of the second write signal based on the second sampling signal output by the sampling unit:
  • An extension unit configured to extend the time delay of the first data strobe signal by a preset period when the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, and determine the extended signal The data strobe signal received during a write operation to the memory.
  • the present disclosure provides an electronic device, including: a processor, and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, To implement the method described in any one of the second aspects.
  • the present disclosure provides a computer-readable storage medium that stores computer-executable instructions, which when executed by a processor are used to implement any one of the second aspects. the method described.
  • the present disclosure provides a computer program product, including a computer program that implements any of the methods in the second aspect when executed by a processor.
  • the present disclosure provides a write leveling circuit applied to a memory and a control method thereof.
  • the write leveling circuit includes a write signal generating unit for receiving a first clock signal and a first indication signal, and generating a signal according to the first The clock signal, the first indication signal, and the designated bit in the first indication signal perform delay processing on the first write signal and output a second write signal; wherein the first indication signal is used to indicate the memory.
  • the shortening time of the latency period, and the first indication signal includes a specified bit; the character of the specified bit is used to indicate that the shortening time is an odd multiple of the clock cycle of the first clock signal or the shortening time is an even multiple of the clock cycle of the first clock signal; a sampling unit is connected to the write signal generation unit, used to receive the first data strobe signal and the second write signal, and generate the signal according to the first data The strobe signal and the second write signal are used to output a second sampling signal.
  • the write signal generation unit in the write leveling circuit in this embodiment can predetermine the shortening time corresponding to the first indication signal to be an odd multiple or an even multiple of the first signal clock cycle through the designated bit of the first indication signal, and then , and then combined with the shortened time corresponding to the first instruction signal and the first clock signal to delay the first write signal.
  • This prevents the inconsistency between the column write latency period in the memory specification requirements and the shortened time specification of the column write latency period, resulting in the inability to directly determine the indication signal corresponding to the shortened column write latency period, and thus making it impossible to perform the write signal analysis. Problems with delayed processing.
  • Figure 1 is a schematic circuit structure diagram of a write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 2 is a schematic circuit structure diagram of a second write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 3 is a schematic circuit structure diagram of a third write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 4 is a schematic circuit structure diagram of a compensator provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic circuit structure diagram of a fourth write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 6 is a schematic circuit structure diagram of a fifth write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 7 is a schematic circuit structure diagram of a sixth write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 8 is a schematic circuit structure diagram of a seventh write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 9 is a schematic flowchart of a control method for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 10 is a schematic flowchart of yet another control method for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • Figure 11 is a schematic structural diagram of a control device applied to a write leveling circuit of a memory provided by an embodiment of the present disclosure
  • Figure 12 is a schematic structural diagram of another control device for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure.
  • 21 Write signal generation unit; 211: Preprocessing module; 212: Determination module; 2121: Processing sub-module; 2122: Shift register; 2123: Compensator; 21231: Delay; 21232: First data selector; 213: Decoder; 214: signal conversion module;
  • DRAM Dynamic Random Access Memory
  • a fly-by bus topology is usually used Structure, that is, the clock signal output port in the controller corresponding to each DRAM is connected to the first DRAM among multiple series-connected DRAMs, and is used to transmit the clock signal to the first DRAM.
  • the clock signal received by the remaining DRAMs in the plurality of series-connected DRAMs is output by the previous DRAM connected in series.
  • each DRAM in the plurality of DRAMs is directly connected to the controller, and is used to receive the data strobe signal sent by the controller, and is used to transmit the data strobe signal between each DRAM and the controller.
  • the trace lengths of the numbers are the same.
  • each DRAM needs to continuously adjust the delay of the DQS signal it receives (that is, perform memory write leveling training), so that the effective edge of the DQS signal received by each DRAM is in line with the clock
  • the time difference between the active edges of the signal meets the memory specification to ensure that data can be written to the memory at the correct clock cycle.
  • the write leveling process of the memory can usually be divided into two stages, one stage is the external write leveling stage, and the other stage is the internal write leveling stage.
  • the column write latency corresponding to the write signal will be continuously reduced to reduce the power consumption caused by the transmission of the write signal within the memory.
  • the data strobe signal received by the memory will also be affected. The delay is adjusted, and then the delay of the above two signals is adjusted to ensure that the effective edge of the write signal inside the memory is aligned with the effective edge of the data strobe signal.
  • the column write latency period is inconsistent with the shortening time specification of the column write latency period, that is, in the specification definition of the actual memory, , the memory specification requires that the column write latency period is an even multiple of the clock cycle of the clock signal; and the shortening time of the storage column write latency period is an integer multiple of the clock cycle of the clock signal (that is, it may be an odd multiple of the clock cycle of the clock signal). Possibly an even multiple).
  • the shortening time of the storage column write latency period is an integer multiple of the clock cycle of the clock signal (that is, it may be an odd multiple of the clock cycle of the clock signal). Possibly an even multiple).
  • the signal corresponding to the shortened column write latency period cannot be determined, resulting in the inability to delay processing of the write signal.
  • the write leveling circuit and its control method applied to memory provided by this disclosure are intended to solve the above technical problems of the prior art.
  • Figure 1 is a schematic circuit structure diagram of a write leveling circuit applied to a memory provided by an embodiment of the present disclosure. As shown in Figure 1, the write leveling circuit includes:
  • the write signal generation unit 21 is configured to receive the first clock signal and the first instruction signal, and perform delay processing on the first write signal according to the first clock signal, the first instruction signal, and the designated bit in the first instruction signal, Output a second write signal; wherein, the first indication signal is used to indicate the shortening time of the column write latency period of the memory, and the first indication signal includes a specified bit; the character of the specified bit is used to indicate that the shortening time is the clock of the first clock signal An odd multiple of the period or the shortened time is an even multiple of the clock period of the first clock signal;
  • the sampling unit 22 is connected to the write signal generating unit 21 and is used for receiving the first data strobe signal and the second write signal, and outputting the second sampling signal according to the first data strobe signal and the second write signal.
  • the write signal generation unit 21 included in the write leveling circuit is used to receive the first clock signal transmitted from the memory pin to the inside of the memory, and the first clock signal sent by the controller arranged outside the memory.
  • the first instruction signal sent by the controller is used to instruct the write signal generating unit 21 to shorten the column write latency period of the current memory.
  • the specified bit character of the first indication signal may also represent that the shortening time of the column write latency period of the current memory is an odd multiple of the clock cycle of the first clock signal or is an odd multiple of the clock cycle of the first clock signal.
  • the clock period of the first clock signal is the minimum period of the first clock period.
  • the write signal generating unit 21 After receiving the first instruction signal and the first clock signal, the write signal generating unit 21 performs delay processing on the first write signal to obtain a second write signal.
  • the write leveling circuit also includes a sampling unit 22, which is configured to receive the second write signal output by the write signal generating unit 21 connected thereto. Furthermore, the sampling unit 22 is also configured to receive a first data strobe signal, where the first data strobe signal can be considered as a data strobe signal received at a pin of the memory. Afterwards, the sampling unit 22 generates a second sampling signal based on the received first data strobe signal and the second write signal output by the write signal generating unit 21, so that the controller outside the memory can, based on the received second sampling signal, Determine whether the valid edge of the first write signal of the memory is aligned with the valid edge of the first data strobe signal. It should be noted that the effective edge of the signal mentioned in this disclosure may be the rising edge of the signal or the falling edge of the signal.
  • the second sampling signal may be the difference between the time corresponding to the valid edge of the first write signal calculated by the write signal generation unit 21 and the time of the valid edge of the first data strobe signal, where After receiving the second sampling signal, the controller may determine whether the valid edge of the first write signal and the valid edge of the first data strobe signal are aligned based on the difference between the second sampling signal.
  • the write signal generation unit 21 when the write signal generation unit 21 performs delay processing on the first write signal based on the received first clock signal, the first indication signal, and the specified bit of the first indication signal, the following processing method may be used:
  • the write signal generation unit 21 determines based on the character of the specified bit of the first instruction signal that the shortening time indicated by the first instruction signal is an even multiple of the clock cycle of the first clock signal.
  • the memory column write latency period and the column write latency period The difference between the shortened times is still an even multiple of the clock cycle of the first clock signal.
  • the signal corresponding to the difference between the two can be determined, so that the write signal generating unit 21 can write the signal based on the difference.
  • the determined signal delays the first write signal.
  • the write signal generation unit 21 determines that the shortening time indicated by the first indication signal is an odd multiple of the clock cycle of the first clock signal based on the character of the specified bit of the first indication signal, at this time, the memory column write latency period is the same as the column write The difference between the shortening time of the latency period is an odd multiple of the clock cycle of the first clock signal.
  • a first time can be selected from the shortening times defined in the memory specification, wherein the first time is greater than the first indication signal.
  • the indicated shortened time is an even multiple of the clock period of the first clock signal.
  • the difference between the first time and the column write latency period of the memory is an even multiple of the clock cycle, so that the write signal generation unit 21 can perform delay processing based on the signal determined by the above difference, and because the first time Greater than the shortening time indicated by the first indication signal, the delay time of the first write signal is shortened. Therefore, after the signal determined based on the difference is delayed, it is necessary to continue to delay the delayed first write signal. Processing, at this time, the delay processing time is the difference between the first time and the shortened time indicated by the first instruction, and then the second write signal is obtained.
  • the memory specifications of the memory in this disclosure can be a memory with DDR5 memory specifications or a memory with other memory specifications.
  • the write signal generating unit 21 of the write leveling circuit can predetermine the shortening time corresponding to the first indication signal to be an odd multiple of the clock cycle of the first signal through the designated bit of the first indication signal. Even times, and then combined with the shortened time corresponding to the first indication signal and the first clock signal to delay the first write signal. This avoids that when the time specifications used for the stored column write latency period and the shortened time of the column write latency period are inconsistent, it is impossible to directly determine the indication signal corresponding to the shortened column write latency period, which makes it impossible to perform the write signal Problems with delayed processing.
  • the second sampling signal represents whether the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal.
  • the process of write leveling the memory includes external write leveling and internal write leveling.
  • the main purpose of setting the internal write leveling is to further ensure the effective edge of the first data strobe signal received inside the memory and the second write signal on the basis of reducing the transmission path for the data strobe signal to be transmitted inside the memory. Whether the valid edges are aligned.
  • the sampling unit 22 directly outputs a second sampling signal based on the first data strobe signal and the second writing signal generated by the writing signal generating unit 21 connected to the sampling unit 22, so that the second sampling signal , determine whether the valid edge of the first data strobe signal and the valid edge of the second write signal are aligned.
  • the sampling unit 22 may perform a difference process on the time corresponding to each valid edge of the first data strobe signal and the time corresponding to each valid edge of the second write signal, so as to determine the validity of the first data strobe signal. Whether the edge is aligned with the valid edge of the second write signal.
  • FIG. 2 is a schematic circuit structure diagram of a second write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the first indication signal includes at least one binary character
  • the designated bit is the lowest bit of the first indication signal
  • the write Signal generation unit 21 includes:
  • the preprocessing module 211 is used to perform a summation process on the first indication signal and the designated characters of the first indication signal to obtain a preprocessing signal; the determination module 212 is connected to the preprocessing module 211 and is used to perform a summation process based on the first clock signal. , the preprocessing signal, the second indication signal, and the designated bit of the first indication signal, perform delay processing on the first write signal, and output the second write signal; the second indication signal is used to indicate the column write latency period of the memory.
  • the designation of the first indication signal may be the lowest bit of the first indication signal.
  • the lowest bit of the first indication signal is 0, it can mean that the shortening time indicated by the first indication signal is an even multiple of the clock cycle of the first clock signal; when the lowest bit of the first indication signal is 1 , can represent that the shortening time indicated by the first indication signal is an odd multiple of the clock cycle of the first clock signal.
  • the write signal generation unit 21 in this embodiment includes: a pre-processing module 211, and a determination module 212 connected to the pre-processing module 211.
  • the preprocessing module 211 is used to receive the first indication signal and the specified bit of the first indication signal, and perform a summation process on the received first indication signal and the specified bit of the first indication signal to obtain a preprocessed signal. .
  • the lowest bit of the first indication signal is 0, it indicates that the shortening time indicated by the first indication signal is an even multiple of the clock cycle of the first clock signal, and if the lowest bit of the first indication signal is 1, it indicates the first indication.
  • the shortening time indicated by the signal is an odd multiple of the clock cycle of the first clock signal
  • the lowest bit of the first indication signal is 0, then the lowest bit of the preprocessed signal obtained after the summation process is 0; if The lowest bit of the first indication signal is 1, then the lowest bit of the preprocessed signal obtained after the summation process is also 0; that is, after the summation process of the lowest bit of the first indication signal and the first indication signal, the The shortening time indicated by the preprocessing signal is an even multiple of the clock cycle of the first clock signal; and, if the memory specification requirements with the above write leveling circuit stipulate that the larger the value of the preprocessing signal, the greater the value of the preprocessing signal.
  • the specification that the shortening time corresponding to the preprocessing signal is larger, then the shortening time corresponding to the preprocessing signal obtained through the summation process is greater than or equal to the shortening time corresponding to the first indication signal.
  • the determination module 212 provided in the write leveling circuit in this embodiment can be used to receive a second instruction signal sent by a controller outside the memory, where the second instruction signal is used to indicate the column write latency period of the memory.
  • the column write latency of the memory can be determined based on the required read and write rate of the memory. That is, when the read and write rate of the memory needs to be changed, the second instruction issued to the memory can be adjusted at this time. The column write latency indicated by the signal ensures that the memory read and write rate meets the required requirements.
  • the determination module 212 When the determination module 212 receives the preprocessing signal output by the preprocessing module 211 connected to the determination module 212, at this time, the determination module 212 will based on the received first clock signal, preprocessing signal, second indication signal and first The first write signal is delayed at a specified bit of the clock signal to obtain the second write signal.
  • the determining module 212 when the determining module 212 performs delay processing on the first write signal, it is first determined based on the specified bit of the first indication signal that the shortened time indicated by the first indication signal is an odd number of clock cycles of the first clock signal. times, the determination module 212 will request the pre-processing module 211 to forward the first indication signal currently received by the pre-processing module 211, and then the determination module 212 determines the delay time based on the first indication signal and the pre-processing signal, and performs the processing on the received first indication signal. The write signal is delayed, and after the delayed first write signal is obtained, the delayed first write signal is delayed based on the delay time indicated by the preprocessing signal, and then the second write signal is obtained.
  • the preprocessing module 211 in the write signal generating unit 21 obtains the preprocessed signal after performing summation processing based on the first indication signal and the characters in the specified position of the first indication signal, so that the preprocessing signal is obtained.
  • the shortened time indicated by the processing signal is consistent with the time specification of the write latency period indicated by the second indication signal.
  • the times indicated by the above two signals are both even multiples of the clock cycle of the first clock signal, and then
  • the shortened column write latency obtained after the difference processing between the two can also be in the specification requirements preset by the memory to avoid being unable to obtain when the times indicated by the first indication signal and the second indication signal are inconsistent.
  • the time corresponding to the difference between the two corresponds to the indication signal in the memory preset specifications.
  • Figure 3 is a schematic circuit structure diagram of a third write leveling circuit applied to a memory provided by an embodiment of the present disclosure. As shown in Figure 3, based on the device structure shown in Figure 2, the determination provided by this embodiment Module 212, including:
  • the processing sub-module 2121 is connected to the pre-processing module 211, and is used to determine the third indication signal based on the pre-processing signal and the second indication signal.
  • the third indication signal is used to indicate the time that the first write signal currently needs to be delayed;
  • shift The register 2122 is used to delay the first write signal based on the third instruction signal and the first clock signal to obtain the third write signal;
  • the compensator 2123 is connected to the shift register 2122, and is configured based on the designation of the first instruction signal. bit, and the first clock signal, the delay of the third write signal is compensated to obtain the second write signal.
  • the determination module 212 includes: a processing sub-module 2121, a shift register connected to the processing sub-module 2121, and a compensator 2123 connected to the shift register 2122.
  • the processing sub-module 2121 is used to receive the pre-processing signal output by the pre-processing module 211 connected to the processing sub-module 2121.
  • the processing sub-module 2121 is also used to receive a second indication signal.
  • the pre-processing signal can be used as the time that the column write latency period of the current memory needs to be shortened
  • the second indication signal is used to indicate the column write latency period of the memory.
  • the processing sub-module 2121 can be based on the second instruction signal and the preprocessing signal. , determine the third indication signal, where the third indication signal is used to indicate the time that the first write signal currently needs to be delayed.
  • the shift register 2122 in the write leveling circuit will shift the first write signal based on the third instruction signal and the first clock signal, that is, delay the first write signal. Process, and then obtain the third write signal.
  • a compensator 2123 is also provided in the write leveling circuit. It can be understood that since the shortening time indicated by the preprocessing signal is greater than or equal to the shortening indicated by the first indication signal received by the preprocessing module 211 in the memory time. Therefore, when the shortening time indicated by the preprocessing signal is greater than the shortening time indicated by the first indication signal, at this time, the delay time between the first writing signal and the third writing signal will be smaller than the original delay. time, where the original delay time is the difference between the column write latency period of the memory and the shortened time indicated by the first indication signal. Therefore, the compensator 2123 will also perform compensation processing on the third write signal, so that the delay time between the obtained second write signal and the first write signal is equal to the original delay time.
  • the compensator 2123 determines whether the preprocessing signal output by the preprocessing module 211 is the same as the first indication signal based on the character corresponding to the specified bit of the first indication signal. When the compensator 2123 determines that the first indication signal is the same as the first indication signal. When the preprocessed signals are different, compensation processing needs to be performed at this time. When the compensator 2123 determines that the first indication signal is the same as the preprocessed signal, then the third write signal can be directly used as the second write signal finally output by the write signal generation unit 21 at this time.
  • the compensator 2123 in the determination module 212 can also be set before the processing sub-module 2121, that is, the compensator 2123 is connected to the processing sub-module 2121 and the shift register 2122 respectively.
  • the processing sub-module 2121 is connected to the shift register 2122, wherein the compensator 2123 compensates the delay of the first write signal based on the specified bit of the first instruction signal, and outputs the compensated signal to the shift register connected to the compensator 2123.
  • Register 2122 so that the shift register 2122 can perform delay processing on the compensated signal based on the third indication signal output by the processing sub-module 2121 connected thereto, thereby obtaining the second write signal.
  • a processing sub-module 2121 can be provided in the determination module 212 to process the second indication signal and the pre-processing signal sent by the pre-processing module 211 to the processing sub-module 2121, thereby obtaining the third indication. signal, so that the shift register 2122 connected to the processing sub-module 2121 can perform delay processing on the first write signal based on the third instruction signal sent by the processing sub-module 2121 to obtain a third write signal. Afterwards, the compensator 2123 in the determination module 212 will also perform compensation processing on the third write signal based on the designation of the first indication signal, thereby obtaining a second write signal.
  • the processing submodule 2121 in the write leveling circuit is specifically used for:
  • the shortening time of the column write latency period of the memory corresponding to the first indication signal that is the same as the preprocessing signal in the first mapping relationship is determined as the first delay time corresponding to the preprocessing signal ;
  • the first delay time is used to characterize the current time that needs to be shortened for the column write latency period of the memory;
  • the first mapping relationship is used to indicate multiple first indication signals of the memory, and the memory corresponding to the first indication signal one-to-one The shortening time of the column write latency period;
  • the column write latency corresponding to the second indication signal is determined; the second mapping relationship is used to indicate a plurality of second indication signals of the memory, and the columns corresponding to the second indication signal one-to-one write latency period;
  • the indication signal is the third indication signal.
  • a first register and a second register may be set in the memory, wherein the first register may be used to store the first indication signal, and the second register may be used to store the second indication signal.
  • the memory when the memory is respectively equipped with a high-order data strobe signal receiving pin and a low-order data strobe signal receiving pin, then it is necessary to separately process the signal received by the high-order data strobe signal receiving pin of the memory and The signal received by the low-bit data strobe signal receiving pin performs write leveling processing.
  • the number of bits in the first register is 8 bits, at this time, the lower four bits of the first register can be used to store the first indication signal received when writing and leveling the lower data strobe signal.
  • the upper four bits can be used to store the first indication signal received during write leveling of the upper data strobe signal.
  • the second register may be used to store the received second indication signal.
  • the first mapping relationship in this embodiment can be used to represent the shortened time of the column write latency period of the memory corresponding to the first indication signal in the first register. For example, when the first indication signal in the first register is 0000, at this time, based on the first mapping relationship, it can be determined that the shortened data of the column write latency period of the memory corresponding to the first indication signal is 0tck, where tck is represented by is used to represent the clock period of the first clock signal. That is, the first mapping relationship may be used to indicate a plurality of first indication signals and a shortened time of the column write latency corresponding to each of the plurality of first indication signals.
  • the second mapping relationship in this embodiment is used to represent the column write latency period indicated by the second indication signal in the second register. For example, when the second indication signal is 00000, at this time, based on the second mapping relationship, it can be determined that the column write latency period corresponding to 00000 is 22tck. That is, the second mapping relationship is used to indicate a plurality of second indication signals of the memory, and second indication signals corresponding to the second indication signals one-to-one, wherein the second indication signal is used to indicate the column write latency of the memory.
  • the first mapping relationship is used to indicate the corresponding relationship between the first indication signal and the shortening time of the column write latency period
  • the second mapping relationship is used to indicate the correspondence relationship between the second indication signal and the column write latency period.
  • the shortening time of the column write latency period, and the shortening time of the column write latency period is used as the first delay time corresponding to the preprocessing signal, where the first delay time can be regarded as the current column write latency period of the memory Need to shorten the time. Furthermore, based on the second mapping relationship, the column write latency period corresponding to the received second instruction signal is searched in the second mapping relationship. Afterwards, the processing sub-module 2121 obtains the second delay time after calculating the difference between the column write latency period and the first delay time. Furthermore, the processing sub-module 2121 will also search for the indication signal corresponding to the second delay time based on the second mapping relationship, and use the indication signal as the third indication signal.
  • the processing sub-module 2121 determines the third indication.
  • the signal method can ensure that the shift register 2122 can accurately identify the delay time corresponding to the third indication signal and implement delay processing of the first write signal, thereby ensuring the accuracy of the write leveling process of the memory.
  • the compensator 2123 in this embodiment is specifically used;
  • the third write signal is used as the second writing signal; if it is determined that the character representation of the specified bit of the first indication signal
  • the shortening time is an odd multiple of the clock cycle of the first clock signal, and the third write signal is delayed to obtain a second write signal.
  • the duration of the delay processing is the first delay time corresponding to the preprocessing signal and the first instruction signal. The difference in shortening time of the memory's column write latency.
  • the preprocessing module 211 performs sum processing on the specified bit of the first indication signal and the first indication signal. , the obtained preprocessed signal is the same as the first instruction signal, then the compensator 2123 directly outputs the third write signal output by the shift register 2122 connected thereto as the second write signal.
  • the preprocessing module 211 When the specified bit character representation shortening time of the first indication signal is an odd multiple of the clock cycle of the first clock signal, when the preprocessing module 211 performs sum processing on the specified bit of the first indication signal and the first indication signal, the The shortening time indicated by the obtained preprocessing signal is an even multiple of the clock cycle of the first clock signal. Since the current required shortening time indicated by the preprocessing signal after the summation process is greater than the shortening time indicated by the first indication signal, therefore , the compensator 2123 will also perform delay processing on the third write signal output by the shift register 2122 connected thereto, and output the delayed signal as the second write signal.
  • the compensator 2123 is performing the third write operation.
  • the duration of the delay processing is the difference between the first delay time indicated by the preprocessing signal and the shortened time indicated by the first indication signal.
  • Table 1 and Table 2 are respectively schematic tables of a first mapping relationship and a second mapping relationship provided by embodiments of the present disclosure.
  • Table 1 is a schematic table of a first mapping relationship provided by the embodiment of the present disclosure.
  • Table 2 is a schematic table of a second mapping relationship provided by the embodiment of the present disclosure.
  • the values of the column write latency period are all even multiples of the clock period of the first clock signal.
  • the shortened time corresponding to the first indication signal ie, the characterized first delay time
  • the corresponding column write latency period is the first clock signal an even multiple of .
  • the corresponding column write latency period is an odd multiple of the first clock signal.
  • tck in the table is used to characterize the clock cycle of the first clock signal. That is, 22tck in the table is used to represent that the column write latency period of the memory is 22 times the clock period of the first clock signal.
  • the preprocessing module 211 When the first indication signal received by the preprocessing module 211 is 0001, at this time, the preprocessing module 211 will perform a summation process on the first indication signal 0001 and the lowest bit 1 of the first indication signal, and then obtain the preprocessing signal 0010 ;
  • the processing sub-module 2121 when receiving the pre-processing signal 0010 and the second instruction signal 00001 sent by the pre-processing module 211 connected to it, will combine the first delay time 2tck corresponding to the pre-processing signal 0010 with the second instruction signal 00001
  • the corresponding column writing latency period is 24tck, and the difference is processed to obtain 22tck.
  • the second indication signal corresponding to 22tck is 00000
  • the second indication signal is sent as the third indication signal to the shift connected to the processing sub-module 2121 Register 2122.
  • the shift register 2122 delays the first write signal based on the received third instruction signal and the first clock signal, and the delay processing time is 22tck, thereby obtaining the third write signal, and outputs the third write signal. to the compensator 2123 connected to the shift register 2122.
  • the compensator 2123 After receiving the designated bit 1 of the first indication signal, the compensator 2123 determines that the delay time between the currently obtained third write signal and the first write signal is shortened, and, since it can be determined from the first mapping table It turns out that the preprocessed signal obtained by summing the first indication signal and the lowest bit 1 of the first indication signal is the next first indication adjacent to the first indication signal in the first mapping relationship. signal, and the difference between the shortened times corresponding to the adjacent first indication signals is 1tck. Therefore, the compensator 2123 can continue to delay the received third write signal, and the delay time is 1tck, and then we get Second write signal.
  • the delay time between the second write signal and the first write signal is 23tck, which is equal to the difference between the column write latency period 24tck corresponding to the second instruction signal 00001 and the shortening time 1tck corresponding to the first instruction signal 0001 .
  • the preprocessing module 211 When the first indication signal received by the preprocessing module 211 is 0010, at this time, the preprocessing module 211 will perform a summation process on the first indication signal 0010 and the lowest bit 0 of the first indication signal, and then obtain the preprocessing signal 0010 (At this time, the first instruction signal is the same as the preprocessing signal); the processing sub-module 2121, when receiving the preprocessing signal 0010 and the second instruction signal 00001 sent by the preprocessing module 211 connected to it, will process the preprocessing signal 0010 The corresponding first delay time 2tck and the column write latency period 24tck corresponding to the second instruction signal 00001 are subjected to difference processing to obtain 22tck.
  • the second indication signal corresponding to 22tck is 00000
  • the second indication signal is sent as the third indication signal to the shift connected to the processing sub-module 2121 Register 2122.
  • the shift register 2122 delays the first write signal based on the received third instruction signal and the first clock signal, and the delay processing time is 22tck, thereby obtaining the third write signal, and outputs the third write signal. to the compensator 2123 connected to the shift register 2122.
  • the compensator 2123 After receiving the designated bit 0 of the first indication signal, the compensator 2123 determines that the delay time between the currently obtained third write signal and the first write signal has not been shortened, and then the third write signal can be directly used as the third write signal.
  • the second write signal is output to the sampling unit 22.
  • Figure 4 is a schematic circuit structure diagram of a compensator 2123 provided by an embodiment of the present disclosure. As shown in the figure, the compensator 2123 includes:
  • the delayer 21231 is connected to the shift register 2122 and is used to delay the third write signal output by the shift register 2122 to obtain the delayed third write signal;
  • the first data selector 21232 is connected to the delayer 21231 and the first data selector 21232 respectively, and is used to receive the delayed processed third write signal output by the delayer 21231 and the third write signal output by the shift register 2122.
  • the third write signal; the first data selector 21232 is also used to receive the specified bit of the first indication signal, and the first data selector 21232 is used to determine that the character of the specified bit of the first indication signal represents the clock cycle of the first clock signal.
  • the third write signal will be output as the second write signal; the first data selector 21232 is used to determine that the character of the specified bit of the first indication signal represents an odd multiple of the clock cycle of the first clock signal, then the delay process will The subsequent third write signal is output as the second write signal.
  • the compensator 2123 includes a delayer 21231 and a first data selector 21232.
  • the delayer 21231 is connected to the shift register 2122 in the determination module 212, and is used to receive the third write signal output by the shift register 2122, and perform delay processing on the received third write signal, thereby obtaining the delayed processed the third write signal, and outputs the delayed third write signal to the first data selector 21232 connected to the delayer 21231.
  • the first data selector 21232 is also connected to the shift register 2122 in the determination module 212 for receiving the third write signal output by the shift register 2122.
  • the first data selector 21232 is also configured to receive a character in a specified bit of the first indication signal, and select from the delayed processed third write signal and the third write signal based on the character in a specified bit of the first indication signal. The signal that currently needs to be output.
  • the third write signal is output as the second write signal; if the first data selector 21232 is used to determine that the character of the specified bit of the first indication signal represents an odd multiple of the clock cycle of the first clock signal, and then output the delayed third write signal as the second write signal.
  • the circuit structure is relatively simple and easy to implement.
  • FIG. 5 is a schematic circuit structure diagram of a fourth write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the write signal generation unit 21 also includes a translator. Coder 213.
  • the decoder 213 is connected to the determination module 212 and is used to decode the received write instruction and output the first write signal.
  • the write signal generation circuit in this embodiment includes a decoder 213 , a preprocessing module 211 , and a determination module 212 .
  • the write command received by the decoder 213 can be regarded as a write command sent by the corresponding controller outside the memory containing the write signal generation circuit, that is, the controller sends the write command to the memory pin.
  • Write instructions are used to indicate that the memory currently requires a write operation.
  • the decoder 213 in the write signal generation circuit can decode the write instruction to obtain the first write signal that can be recognized by the device inside the memory and is used to represent the current write operation that needs to be performed. , the decoder 213 sends the obtained first write signal to the determination module 212 connected to the decoder 213, and the determination module 212 generates the preprocessing signal, the first clock signal, and the first signal based on the preprocessing module 211 connected to it. The designated bit of the indication signal and the second indication signal perform delay processing on the received first write signal to obtain a second write signal, and output the second write signal to the sampling unit 22 connected to the determination module 212 .
  • the decoder 213 is provided in the write signal generation unit 21 to decode the write instructions received by the decoder 213, so that the device in the memory can accurately determine the current memory requirements. Perform write operations.
  • the controller can more accurately determine the data strobe signal required by the memory, thereby improving the accuracy of memory data writing.
  • Figure 6 is a schematic circuit structure diagram of the fifth write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the write signal generation unit 21 also includes: Signal conversion module 214; the decoder 213 is connected to the write signal generation unit 21 through the signal conversion module 214; the signal conversion module 214 is used to perform pulse broadening processing on the first write signal output by the decoder 213, and output the broadened write signal, and output the broadened write signal as the first write signal to the determination module 212 .
  • the write signal generation unit 21 in the write leveling circuit includes a decoder 213, a signal conversion module 214 and a determination module 212.
  • the decoder 213 is used to receive the write instruction, decode the write instruction, and send the decoded signal to the signal conversion module 214 connected to the decoder 213 .
  • the signal conversion module 214 performs pulse stretching processing on the decoded signal output by the decoder 213, and outputs the pulse stretching processed signal as the first write signal to the determination module 212 connected thereto, so that the determination module 212
  • the first write signal received can be delayed to obtain a second write signal, which is output to the sampling unit 22 connected to the determination module 212 .
  • the signal conversion module 214 in the write signal generation unit 21 performs pulse stretching processing on the signal output by the decoder 213 to the signal conversion module 214 in order to meet the corresponding specification requirements of the memory (for example, SPEC requirements).
  • a second flip-flop 222 is provided in the sampling unit 22 , and the data end of the second flip-flop 222 is connected to the write signal generating unit 21 for receiving the second second flip-flop 222 output by the write signal generating unit 21 .
  • Write signal; the clock terminal of the second flip-flop 222 is used to receive the first data strobe signal, and the second flip-flop 222 is used to output a second sampling signal based on the second write signal and the first data strobe signal.
  • the clock terminal of the second flip-flop 222 is used to receive the first data strobe signal
  • the data terminal of the second flip-flop 222 is connected to the write signal generating unit 21 and is used to receive the write signal generating unit 21 outputs the second write signal.
  • the second flip-flop 222 samples the second write signal received by the second flip-flop 222 based on the valid edge of the received first data strobe signal, and obtains the sampling result. as the second sampling signal.
  • the write leveling circuit provided in this embodiment also includes: a delay unit 23, used to delay the received first data strobe signal and output the second data strobe signal. pass signal; the sampling unit 22 is connected to the delay unit 23, and is also used to receive the second data strobe signal output by the delay unit 23, and output the first sampling signal according to the second data strobe signal and the second write signal. ; The first sampling signal represents whether the effective edge of the first clock signal is aligned with the effective edge of the first data strobe signal.
  • the external write leveling is used to align the memory pin out of the valid edge of the received data strobe signal and the valid edge of the clock signal.
  • a delay unit 23 is also provided in the write leveling circuit.
  • the delay unit 23 can be used to delay the received first data strobe signal to obtain a second data strobe signal, and send the second data strobe signal to the sampling device connected to the delay unit 23 Unit 22.
  • the first data strobe signal received by the delay unit 23 can be regarded as the data strobe signal transmitted inside the memory, and this signal can be controlled by the memory pin.
  • the received data strobe signal is converted.
  • sampling unit 22 in this embodiment is also used to generate the first sample based on the second write signal output by the write signal generation unit 21 connected thereto and the second data strobe signal output by the delay unit 23 connected thereto. signal so that the controller outside the memory can adjust the signal sent by the controller to the memory based on the received first sampling signal, thereby ensuring that the interval between the valid edge of the data strobe signal received at the memory pin and the valid edge of the clock signal The time difference meets the time difference range specified by the memory.
  • the delay when the delay unit 23 delays the first data strobe signal is equivalent to the delay when the write signal generation unit 21 receives the first clock signal.
  • Delay processing is performed to obtain the time delay of the second write signal, and then the sampling unit 22 can determine the effective edge of the first data strobe signal by comparing whether the effective edge of the second data strobe signal is aligned with the effective edge of the second write signal. Whether it is aligned with the valid edge of the first clock signal.
  • the controller external to the memory can determine whether the purpose of external write leveling of the memory is achieved based on the first sampling signal output by the sampling unit 22.
  • FIG. 7 is a schematic circuit structure diagram of a sixth write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the write leveling circuit in this embodiment includes: a delay unit 23 , a write signal generating unit 21 and a sampling unit 22 .
  • the sampling unit 22 includes: a first flip-flop 221, a second flip-flop 222, and a second data selector 223. The data end of the first flip-flop 221 is connected to the write signal generation unit 21 for receiving the write signal.
  • the clock terminal of the first flip-flop 221 is connected to the output terminal of the delay unit 23 for receiving the second data strobe signal output by the delay unit 23; the first flip-flop 221 is Based on the second write signal and the second data strobe signal, the first sampling signal is output; the data terminal of the second flip-flop 222 is connected to the write signal generation unit 21 for receiving the second write signal output by the write signal generation unit 21 ;
  • the clock terminal of the second flip-flop 222 is used to receive the first data strobe signal, and the second flip-flop 222 is used to output a second sampling signal based on the second write signal and the first data strobe signal; the first flip-flop 221
  • the output terminal is connected to the first terminal of the second data selector 223 , and the output terminal of the second flip-flop 222 is connected to the second terminal of the second data selector 223 .
  • the write leveling circuit in this embodiment includes a delay unit 23, a write signal generation unit 21, and a sampling unit 22, and the sampling unit 22 is also provided with a first flip-flop 221. , the second flip-flop 222 and the second data selector 223. Among them, the clock terminal and the data terminal of the first flip-flop 221 are respectively connected to the delay unit 23 and the write signal generating unit 21, and then the first flip-flop 221 sends a signal based on the delay unit 23 connected to it received by its clock terminal.
  • the second write signal output by the write signal generating unit 21 connected to the first flip-flop 221 received by the data terminal is sampled, and the sampling result is used as the first sampling signal and output to The first flip-flop 221 is connected to the second data selector 223 .
  • the clock terminal of the second flip-flop 222 is used to receive the first data strobe signal
  • the data terminal of the second flip-flop 222 is connected to the write signal generating unit 21 and is used to receive the second write signal output by the write signal generating unit 21, Afterwards, the second flip-flop 222 samples the second write signal received by the second flip-flop 222 based on the valid edge of the received first data strobe signal, and outputs the sampling result as a second sampling signal to
  • the second data selector 223 is connected to the second flip-flop 222 .
  • the second data selector 223 After receiving the first sampling signal sent by the first flip-flop 221 connected to it and the second sampling signal sent by the second flip-flop 222 connected thereto, the second data selector 223 will select one of the sampling signals to output, So that the controller outside the memory can adjust the signal sent by the controller to the memory based on the received first sampling signal or the second sampling signal.
  • the device of the sampling unit 22 provided in this embodiment, can reduce the occupation of the data receiving port on the controller.
  • the write leveling circuit is packaged in the memory, it can also reduce the occupation of pins on the memory.
  • FIG. 8 is a schematic circuit structure diagram of a seventh write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the write leveling circuit provided in this embodiment further includes a first converter 24 and a second converter 25 .
  • the first converter 24 is connected to the delay unit 23 and the sampling unit 22 respectively, and is used to perform logic level conversion processing on the received third data strobe signal to obtain the first data strobe signal; wherein, the third data
  • the level of the strobe signal is a current mode logic level; the level of the first data strobe signal is a CMOS level.
  • the second converter 25 is connected to the write signal generating unit 21 and is used to perform logic level conversion processing on the received second clock signal to obtain the first clock signal; wherein the level of the second clock signal is current mode logic. level; the level of the first clock signal is the CMOS level.
  • this embodiment also includes a first converter 24 .
  • the third data strobe signal received by the first converter 24 can be considered as a data strobe signal sent to a pin of the memory by a controller external to the memory.
  • the controller sends the third data strobe signal to the memory, in order to improve the signal transmission efficiency, the current mode logic (Current Model Logic, CML for short) level transmission form is usually used.
  • CML Current Model Logic
  • CMOS complementary metal oxide semiconductor
  • the first converter 24 in the write leveling circuit After the first converter 24 in the write leveling circuit obtains the third data strobe signal at the pin, it will convert the third data strobe signal transmitted in the form of CML level transmission into a CMOS level.
  • the first data strobe signal transmitted in the form of transmission is then transmitted to the delay unit 23 connected to the first converter 24 and the second flip-flop 222 in the sampling unit 22 respectively, so that the first data strobe signal in the memory
  • Each device in the write leveling circuit can accurately identify the first data strobe signal.
  • a second converter 25 is included in the write leveling circuit.
  • the second clock signal received by the second converter 25 can be considered as a clock signal sent to a pin of the memory by a controller external to the memory or a previous memory connected in series with it.
  • the controller sends a clock signal to the memory or sends a clock signal between memories, in order to improve the signal transmission efficiency, the current mode logic (Current Model Logic, CML) level transmission form is usually used.
  • CML Current Model Logic
  • CMOS level transmission is usually used for signal transmission. Therefore, after the second converter 25 in the write leveling circuit obtains the second clock signal at the pin, it will convert the second clock signal transmitted in the CML level transmission form into the second clock signal transmitted in the CMOS level transmission form.
  • the first clock signal is then transmitted to the write signal generation unit 21 connected to the second converter 25 so that each device in the write leveling circuit in the memory can accurately identify the first clock signal.
  • the first sampling signal is specifically used to indicate adjusting the delay of the first clock signal when the first sampling signal represents that the valid edge of the first clock signal is not aligned with the valid edge of the first data strobe signal;
  • the second sampling signal is specifically used to align the valid edge of the first clock signal and the valid edge of the first data strobe signal when the first sampling signal represents the first clock signal, and the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal. When misaligned, it indicates adjusting the delay of the first write signal or the delay of the first data strobe signal.
  • the controller in order to implement the external write leveling process of the memory, when the controller external to the memory determines that the first sampling signal represents the valid edge of the first clock signal and the valid edge of the first data strobe signal are not in contact with each other.
  • the controller can continuously adjust the delay of the data strobe signal sent to the memory, that is, continuously adjust the delay of the first data strobe signal, so as to achieve the effective edge of the first clock signal and the first data strobe signal.
  • the purpose of aligning the valid edge of the communication signal in order to implement the external write leveling process of the memory, when the controller external to the memory determines that the first sampling signal represents the valid edge of the first clock signal and the valid edge of the first data strobe signal are not in contact with each other.
  • the controller can continuously adjust the delay of the data strobe signal sent to the memory, that is, continuously adjust the delay of the first data strobe signal, so as to achieve the effective edge of the first clock signal and the first data strobe signal.
  • the following methods can be used to adjust.
  • the delay of the first write signal or the delay of the first data strobe signal can be adjusted to achieve the first data strobe signal. The purpose of aligning the valid edge of the signal with the valid edge of the second write signal.
  • Delay processing of the first data strobe signal is equivalent to reducing the delay when the first data strobe signal is transmitted inside the memory, and the delay caused by the first write signal during the transmission process can also be reduced by adjusting the delay of the first write signal. After that, the delay of the first write signal or the delay of the first data strobe signal is continuously adjusted to ensure that the purpose of internal write leveling is achieved.
  • Figure 9 is a schematic flowchart of a control method for a write leveling circuit of a memory provided by an embodiment of the present disclosure. The method provided by this embodiment is applied to the write leveling circuit shown in Figure 1. The method includes the following step:
  • Step S901 is repeated until it is determined based on the second sampling signal output by the sampling unit that the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal.
  • the execution subject of this embodiment may be a controller external to the memory or other electronic devices, and this disclosure does not impose specific limitations.
  • the following description takes the controller as the execution subject of the present disclosure as an example.
  • the controller when performing internal write leveling on the memory, first, when the controller determines based on the second sampling signal that the valid edge of the first data strobe signal is not aligned with the valid edge of the second write signal, at this time, the controller can adjust the first The data strobe signal or the first instruction signal is used to ensure that the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, that is, to ensure that the data strobe signal and the write signal received by the memory unit part inside the memory are aligned.
  • adjusting the first indication signal is equivalent to adjusting the time delay between the first writing signal and the second writing signal.
  • the controller determines that the second sampling signal represents that the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, at this time, the time delay of the first data strobe signal during alignment can be extended by a preset period. , and the delayed data strobe signal is used as the first data strobe signal received by the memory during a write operation.
  • the effective edge of the first data strobe signal after the preset period is extended, compared with the effective edge of the first clock signal received at the memory pin during alignment, the time difference between the two effective edges
  • the time difference required by the memory specification for example, the memory's tDQSoffset.
  • the preset period in the present disclosure can be determined based on the write preamble signal and the correspondence between the write preamble signal and the preset duration.
  • the controller in order to reduce the power consumption caused by the transmission of the data strobe signal and the write signal within the memory, during the internal write leveling process, the controller will based on the received second sampling signal To continuously adjust the delay of the first data strobe signal or the delay of the first write signal, so as to finally complete the write leveling process of the memory, so that the memory can accurately write data. And by extending the delay of the first data strobe signal by a preset period when the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, the data that ultimately needs to be received by the memory pin is determined. Strobe signal so that the memory can accurately write data.
  • the controller outside the memory determines whether the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal based on the second sampling signal output by the sampling unit, it can be determined in the following manner:
  • the level value of the second sampling signal output by the sampling unit changes from the second level value to the first level value, it is determined that the effective edge of the first data strobe signal is aligned with the effective edge of the second write signal.
  • the sampling unit after the sampling unit generates the second write signal output by the unit based on the received first data strobe signal and the received write signal, in order to determine the valid edge of the first data strobe signal and Whether the effective edge of the second write signal is aligned can be determined by sampling the level value of the second write signal at the effective edge of the first data strobe signal and using the sampling result as the second sampling signal output by the sampling unit.
  • By continuously monitoring changes in the level value of the second sampling signal when the level value of the second sampling signal switches from the second level value to the first level value, at this time, it represents the effective edge of the second write signal. Aligned with the active edge of the first data strobe signal.
  • the difference between the valid edge of the first data strobe signal and the first data strobe signal can be determined by detecting whether the level value of the second sampling signal changes from the second level value to the first level value. Whether the valid edges of the two write signals are aligned.
  • the method provided by this embodiment is simple and easy to implement, and there is no need to repeatedly calculate the time difference between the valid edges of the signal multiple times.
  • Figure 10 is a schematic flowchart of yet another control method for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure. The method includes the following steps:
  • step S1001 is repeated until the level value of the second sampling signal output by the sampling unit is converted from the first level value to the second level value.
  • the controller determines the level value of the second sampling signal output by the sampling unit in real time to determine the effective edge of the second write signal and the first data strobe signal. Whether the valid edges are aligned. Specifically, when the controller determines that the level value of the second sampling signal output by the second sampling unit is the first level value, at this time, the controller can adjust the first indication signal sent to the write signal generation unit, by Adjust the first indication signal to increase the shortening time of the column write latency period indicated by the first indication signal, that is, correspondingly, it is equivalent to continuously reducing the time between the first write signal and the second write signal generated by the write signal generation unit. delay. By continuously adjusting the time delay of the first write signal generated by the write signal generation unit, the time difference between the effective edge of the first data strobe signal and the effective edge of the second write signal is reduced.
  • the shortening time of the column write latency period can only be an integer multiple of the time period of the first clock signal. , resulting in that when adjusting the time delay of the first write signal, the change value of each time delay can only be an integer multiple of the time period.
  • the output sampling value of the second sampling signal switches from the first level value to the second level value, At flat value, at this time, the valid edge of the first data strobe signal and the valid edge of the second write signal may not be aligned, and the time corresponding to the valid edge of the first data strobe signal may be later than that of the second write signal. The phenomenon of the time corresponding to the valid edge, therefore, it is also necessary to adjust the delay of the first data strobe signal.
  • the level value of the second sampling signal output by the sampling unit is the second level value, reduce the time delay of the first data strobe signal received by the sampling unit, and issue the second delay to the write signal generation unit.
  • the second delay signal is the first instruction signal received by the write signal generating unit when the second sampling signal output by the sampling unit switches from the first level value to the second level value.
  • step S1002 is repeated until the level value of the second sampling signal output by the sampling unit switches from the second level value to the first level value.
  • the first data strobe signal is also adjusted. Delay is adjusted. Since the delay of the first data strobe signal is not limited by the memory specifications, the change amount of each delay adjustment does not need to be an integer multiple of the clock cycle of the first clock signal. Therefore, in this step, the first data strobe signal can be adjusted by The delay of the data strobe signal is continuously adjusted, that is, by continuously reducing the delay of the first data strobe signal, the effective edge of the first data strobe signal is aligned with the effective edge of the second data strobe signal.
  • a second delay signal also needs to be sent to the write signal generation unit in the memory.
  • the second delay signal at this time is the second sampling signal from the first voltage.
  • step S902 the specific principle of this step can be found in step S902, which will not be described again here.
  • the power consumption of the first write signal during transmission is first reduced by reducing the delay in the delay processing of the first write signal.
  • the delay of the first data strobe signal is adjusted so that the valid edges of the first data strobe signal and the second write signal can be aligned, so that the memory can achieve accurate writing of data when performing a write operation. , and also reduces the power consumption during internal signal transmission of the memory during the write operation.
  • Figure 11 is a schematic structural diagram of a control device for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the device includes: an adjustment unit 1101, configured to determine that the second sampling signal represents the first data strobe signal. If the valid edge is not aligned with the valid edge of the second write signal, adjust the delay of the first data strobe signal or the first indication signal; repeat the first adjustment unit until the first adjustment unit is based on the second sampling signal output by the sampling unit Determine that the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal:
  • the extension unit 1102 is configured to extend the time delay of the first data strobe signal by a preset period when the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, and determine the extended signal as Data strobe signal received during a write operation to the memory.
  • the device provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principles and technical effects are similar and will not be described again.
  • Figure 12 is a schematic structural diagram of another control device for a write leveling circuit applied to a memory provided by an embodiment of the present disclosure.
  • the adjustment unit 1101 is based on the sampling unit output
  • the second sampling signal determines that the valid edge of the first data strobe signal is aligned with the valid edge of the second write signal, it is specifically used: if the level value of the second sampling signal output by the sampling unit changes from the second level value to the first level value, it is determined that the effective edge of the first data strobe signal is aligned with the effective edge of the second write signal.
  • the adjustment unit 1101 includes:
  • Adjustment module 11011 configured to adjust the first indication signal received by the write signal generation unit to increase the level indicated by the first indication signal if it is determined that the level value of the second sampling signal output by the sampling unit is the first level value.
  • the storage write latency is shortened;
  • the first sending module 11012 is configured to send the adjusted first indication signal to the write signal generation unit.
  • the adjustment module 11011 and the first sending module 11012 are repeated until the adjustment module 11011 determines that the level value of the second sampling signal output by the sampling unit is converted from the first level value to the second level value.
  • the reduction module 11012 is configured to reduce the delay of the first data strobe signal received by the sampling unit if it is determined that the level value of the second sampling signal output by the sampling unit is the second level value.
  • the second sending module 11013 is configured to send a second delay signal to the write signal generation unit, where the second delay signal is when the second sampling signal output by the sampling unit switches from the first level value to the second level value.
  • the write signal generates the first indication signal received by the unit.
  • the reducing module 11012 and the sending module are repeated until the reducing module 11012 determines that the level value of the second sampling signal output by the sampling unit switches from the second level value to the first level value.
  • the device provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principles and technical effects are similar and will not be described again.
  • the present disclosure provides a memory, which includes the write leveling circuit provided in any embodiment of FIGS. 1 to 8 .
  • the present disclosure provides an electronic device, including: a processor, and a memory communicatively connected to the processor; wherein the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement either implementation of Figure 9 or Figure 10 Example of any of the methods provided.
  • FIG 13 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. As shown in Figure 13, the electronic device includes:
  • the electronic device also includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. Among them, the processor 291, the memory 292, and the communication interface 293 can communicate with each other through the bus 294. Communication interface 293 may be used for information transmission.
  • the processor 291 can call logical instructions in the memory 292 to execute the methods of the above embodiments.
  • the above-mentioned logical instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.
  • the memory 292 can be used to store software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure.
  • the processor 291 executes software programs, instructions and modules stored in the memory 292 to execute functional applications and data processing, that is, to implement the methods in the above method embodiments.
  • the memory 292 may include a stored program area and a stored data area, where the stored program area may store an operating system and an application program required for at least one function; the stored data area may store data created according to the use of the terminal device, etc.
  • the memory 292 may include high-speed random access memory and may also include non-volatile memory.
  • the present disclosure provides a computer-readable storage medium.
  • Computer-executable instructions are stored in the computer-readable storage medium. When the computer-executable instructions are executed by a processor, they are used to implement the method provided in any embodiment of Figure 9 or Figure 10.
  • the present disclosure provides a computer program product, which includes a computer program.
  • the computer program When the computer program is executed by a processor, the method provided in any embodiment of FIG. 9 or FIG. 10 is implemented.

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Abstract

一种应用于存储器的写调平电路、及其控制方法，在写调平电路中包括有写信号生成单元，用于接收第一时钟信号和第一指示信号，并根据第一时钟信号、第一指示信号、以及第一指示信号中的指定位，对第一写信号进行延迟处理，输出第二写信号；指定位的字符用于指示缩短时间为第一时钟信号的时钟周期的奇数倍或者缩短时间为第一时钟信号的时钟周期的偶数倍；采样单元，与写信号生成单元连接，用于根据接收到的第一数据选通信号和第二写信号，输出第二采样信号。所述写调平电路避免了当列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致时，导致无法对写信号进行延迟处理的问题。

Description

应用于存储器的写调平电路、及其控制方法
本申请要求于2022年08月16日提交中国专利局、申请号为202210986112.3、申请名称为“应用于存储器的写调平电路、及其控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及存储器技术领域，尤其涉及一种应用于存储器的写调平电路、及其控制方法。
背景技术
目前，在存储器中写入数据之前，需要进行写调平(Write Leveling)处理，即需要对存储器所接收到的数据选通信号(Data Strobe Signal，简称DQS)不断调整，以便存储器所接收到的DQS信号的有效沿与存储器接收到的时钟信号的有效沿之间的时间差值满足存储器规格的要求。存储器的写调平处理可分为外部写调平以及内部写调平。在内部写调平的过程中，需要基于存储器原本的列写潜伏周期(Column Address Strobe Write Latency，简写为CWL)以及列写潜伏周期的缩短时间，确定缩短后的列写潜伏周期，并基于缩短后的列写潜伏周期对写信号进行延迟处理。
然而，在上述延迟处理的过程中，由于存储器的规格要求中，列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致，导致无法直接确定出缩短后的列写潜伏周期对应的指示信号，无法实现上述延迟处理过程。
因此，需要提供一种写调平电路，以解决上述无法进行延迟处理的问题。
发明内容
本公开提供一种应用于存储器的写调平电路、及其控制方法，用以解决相关技术中在进行存储器的内部写调平过程中，由于存储器的列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致，而导致的无法实现内部写调平的问题。
第一方面，本公开提供一种应用于存储器的写调平电路方法，包括：
写信号生成单元，用于接收第一时钟信号和第一指示信号，并根据所述第一时钟信号、所述第一指示信号、以及所述第一指示信号中的指定位，对第一写信号进行延迟处理，输出第二写信号；其中，所述第一指示信号用于指示存储器的列写潜伏周期的缩短时间，所述第一指示信号中包括指定位；所述指定位的字符用于指示所述缩短时间为所述第一时钟信号的时钟周期的奇数倍或者所述缩短时间为所述第一时钟信号的时钟周期的偶数倍；
采样单元，与所述写信号生成单元连接，用于接收第一数据选通信号和所述第二写信号，并根据所述第一数据选通信号和所述第二写信号，输出第二采样信号。
第二方面，本公开提供一种应用于存储器的写调平电路的控制方法，所述方法应用于如第一方面所述的电路，所述方法包括：
重复以下步骤，直至基于所述采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐：若确定所述第二采样信号表征第一数据选通信号的有效沿与第二写 信号的有效沿未对齐，则调整第一数据选通信号的时延或者所述第一指示信号；
当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将所述第一数据选通信号的时延延长预设时段，并将延长后的信号确定为所述存储器进行写操作时所接收到的数据选通信号。
第三方面，本公开提供一种存储器，所述存储器包括如第一方面中的任一项所述的写调平电路。
第四方面，本公开提供一种应用于存储器的写调平电路的控制装置，所述装置应用于如第一方面所述的电路，所述装置包括：
调整单元，用于若确定所述第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐，则调整第一数据选通信号的时延或者所述第一指示信号；重复所述第一调整单元，直至所述第一调整单元基于所述采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐：
延长单元，用于当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将所述第一数据选通信号的时延延长预设时段，并将延长后的信号确定为所述存储器进行写操作时所接收到的数据选通信号。
第五方面，本公开提供一种电子设备，包括：处理器，以及与所述处理器通信连接的存储器；所述存储器存储计算机执行指令；所述处理器执行所述存储器存储的计算机执行指令，以实现如第二方面中任一项所述的方法。
第六方面，本公开提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现如第二方面中任一项所述的方法。
第七方面，本公开提供一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时实现第二方面中任一项所述的方法。
本公开提供的应用于存储器的写调平电路、及其控制方法，在写调平电路中包括有写信号生成单元，用于接收第一时钟信号和第一指示信号，并根据所述第一时钟信号、所述第一指示信号、以及所述第一指示信号中的指定位，对第一写信号进行延迟处理，输出第二写信号；其中，所述第一指示信号用于指示存储器的列写潜伏周期的缩短时间，所述第一指示信号中包括指定位；所述指定位的字符用于指示所述缩短时间为所述第一时钟信号的时钟周期的奇数倍或者所述缩短时间为所述第一时钟信号的时钟周期的偶数倍；采样单元，与所述写信号生成单元连接，用于接收第一数据选通信号和所述第二写信号，并根据所述第一数据选通信号和所述第二写信号，输出第二采样信号。本实施例中的写调平电路中的写信号生成单元，可以通过第一指示信号的指定位预先确定第一指示信号所对应的缩短时间为第一信号时钟周期的奇数倍或者偶数倍，之后，再结合第一指示信号对应的缩短时间、第一时钟信号对第一写信号进行延迟处理时。进而避免存储器规格要求中的列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致时，导致无法直接确定出缩短后的列写潜伏周期所对应的指示信号，进而使得无法对写信号进行延迟处理的问题。
附图说明
图1为本公开实施例提供的一种应用于存储器的写调平电路的电路结构示意图；
图2为本公开实施例提供的第二种应用于存储器的写调平电路的电路结构示意图；
图3为本公开实施例提供的第三种应用于存储器的写调平电路的电路结构示意图；
图4为本公开实施例提供的一种补偿器的电路结构示意图；
图5为本公开实施例提供的第四种应用于存储器的写调平电路的电路结构示意图；
图6为本公开实施例提供的第五种应用于存储器的写调平电路的电路结构示意图；
图7为本公开实施例提供的第六种应用于存储器的写调平电路的电路结构示意图；
图8为本公开实施例提供的第七种应用于存储器的写调平电路的电路结构示意图；
图9为本公开实施例提供的一种应用于存储器的写调平电路的控制方法的流程示意图；
图10为本公开实施例提供的又一种应用于存储器的写调平电路的控制方法的流程示意图；
图11为本公开实施例提供的一种应用于存储器的写调平电路的控制装置的结构示意图；
图12为本公开实施例提供的又一种应用于存储器的写调平电路的控制装置的结构示意图；
图13为本公开实施例中提供的一种电子设备的结构示意图。
附图标记说明：
21：写信号生成单元；211：预处理模块；212：确定模块；2121：处理子模块；2122：移位寄存器；2123：补偿器；21231：延迟器；21232：第一数据选择器；213：译码器；214：信号转换模块；
22：采样单元；221：第一触发器；222：第二触发器；223：第二数据选择器；
23：延时单元；24：第一转换器；25：第二转换器。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
目前，在电子设备中，通常会设置有存储器用于进行数据存储。为了减少电子设备中的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)与存储器的控制器之间的走线，当电子设备中包括多个DRAM时，通常会采用fly-by的总线拓扑结构，即，各个DRAM对应的控制器中的时钟信号输出端口与多个串联的DRAM中的首个DRAM连接，用于向首个DRAM传输时钟信号。多个串联的DRAM中的其余DRAM所接收到的时钟信号是由与其串联连接的前一DRAM输出的。此外，多个DRAM中的每一DRAM的数据选通信号端，分别与控制器直接连接，用于接收控制器发出的数据选通信号，且各个DRAM与控制器之间用于传输数据选通信号的走线长度相同。
当采用上述总线拓扑结构连接控制器与多个DRAM时，数据选通信号到达每一DRAM的时间是相同的，但各DRAM接收到的时钟信号的时间会存在偏差，各DRAM所接收到的时钟信号的时间以及数据选通信号的时间之间具有不同的偏差。因此，针对每一DRAM都需要对其接收到的DQS信号的时延进行不断调整(即，进行存储器的写调平训练)，进而使得每一DRAM上所接收到的DQS信号的有效沿与时钟信号的有效沿之间的时间差值满足存储器规格的要求，以确保数据可以在正确的时钟周期写入存储器。
存储器的写调平过程通常可以分为两个阶段，一个阶段为外部写调平阶段，另一个阶段为内部写调平阶段。在内部写调平过程中，会不断减少写信号所对应的列写潜伏周期，以降低写信号在存储器内部传输时所造成的功耗，同时还会对存储器所接收到的数据选通信号的时延进行调整，进而经过对上述两个信号的时延的调整，以确保存储器内部的写信号的有效沿与数据选通信号的有效沿为对齐状态。
然而，在对写信号所对应的列写潜伏周期的时长进行缩短时，由于存储器的规格要求中，列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致，即在实际存储器的规格定义中，存储器的规格要求中的列写潜伏周期均为时钟信号的时钟周期的偶数倍；而存储列写潜伏周期的缩短时间均为时钟信号的时钟周期的整数倍(即，可能为奇数倍也可能为偶数倍)。基于上述规格设置，当缩短后的列写潜伏周期为时钟周期的奇数倍时，此时，无法确定出该缩短后的列写潜伏周期所对应的信号，进而导致无法对写信号进行延迟处理。
本公开提供的应用于存储器的写调平电路及其控制方法，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本公开的技术方案以及本公开的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本公开的实施例进行描述。
图1为本公开实施例提供的一种应用于存储器的写调平电路的电路结构示意图，如图1所示，该写调平电路包括：
写信号生成单元21，用于接收第一时钟信号和第一指示信号，并根据第一时钟信号、第一指示信号、以及第一指示信号中的指定位，对第一写信号进行延迟处理，输出第二写信号；其中，第一指示信号用于指示存储器的列写潜伏周期的缩短时间，第一指示信号中包括指定位；指定位的字符用于指示缩短时间为第一时钟信号的时钟周期的奇数倍或者缩短时间为第一时钟信号的时钟周期的偶数倍；
采样单元22，与写信号生成单元21连接，用于接收第一数据选通信号和第二写信号，并根据第一数据选通信号和第二写信号，输出第二采样信号。
示例性地，本实施例中，写调平电路中所包括的写信号生成单元21，用于接收存储器引脚处传输至存储器内部的第一时钟信号，以及设置在存储器外部的控制器所发送的第一指示信号，其中，控制器所发送的第一指示信号用于指示写信号生成单元21当前存储器的列写潜伏周期的缩短时间。此外，第一指示信号的指定位的字符还可以表征出当前存储器的列写潜伏周期的缩短时间是第一时钟信号的时钟周期的奇数倍或者时第一时钟信号的时钟周期的奇数倍。其中，第一时钟信号的时钟周期为第一时钟周期的最小周期。
当写信号生成单元21接收到第一指示信号以及第一时钟信号之后，会对第一写信号进行延迟处理，进而得到第二写信号。
此外，写调平电路中还包括采样单元22，采样单元22用于接收与其连接的写信号生成单元21输出的第二写信号。并且，采样单元22还用于接收第一数据选通信号，其中，第一数据选通信号可以认为是存储器的引脚处所接收到的数据选通信号。之后，采样单元22基于接收到的第一数据选通信号以及写信号生成单元21输出的第二写信号，生成第二采样信号，以便存储器外部的控制器可以基于接收到的第二采样信号，确定存储器第一写信号的有效沿与第一数据选通信号的有效沿是否对齐。需要说明的是，本公开中所提及的信号的有效沿，可以为该信号的上升沿，也可以为该信号的下降沿。
在一些实施例中，第二采样信号可以为写信号生成单元21计算得到的第一写信号的有效沿所对应的时间与第一数据选通信号的有效沿的时间之间的差值，在控制器接收到该第二采样信号之后，可以基于第二采样信号之间的差值，确定第一写信号的有效沿与第一数据选通信号的有效沿是否对齐。
在一些实施例中，在写信号生成单元21基于接收到的第一时钟信号、第一指示信号、第一指 示信号的指定位对第一写信号进行延迟处理时，可以采用如下处理方式：当写信号生成单元21基于第一指示信号的指定位的字符确定第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的偶数倍，此时，存储器列写潜伏周期与列写潜伏周期的缩短时间之间的差值仍为第一时钟信号的时钟周期的偶数倍，此时可以确定出上述二者之间的差值所对应的信号，以便写信号生成单元21可以基于差值所确定出的信号对第一写信号进行延迟处理。
当写信号生成单元21基于第一指示信号的指定位的字符确定第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的奇数倍时，此时，存储器列写潜伏周期与列写潜伏周期的缩短时间之间的差值为第一时钟信号的时钟周期的奇数倍，可以存储器规格中所定义的缩短时间中选择一个第一时间，其中，该第一时间大于第一指示信号所指示的缩短时间，且该第一时间为第一时钟信号的时钟周期的偶数倍。此时，第一时间与存储器的列写潜伏周期之间的差值为时钟周期的偶数倍，以便写信号生成单元21可以基于上述差值所确定的信号进行延迟处理，并且，由于第一时间大于第一指示信号所指示的缩短时间，导致第一写信号的延迟时间缩短，因此，在基于差值所确定的信号进行延迟处理之后，还需要继续对上述延迟后的第一写信号进行延迟处理，此时延迟处理的时间为第一时间与第一指示指示的缩短时间之间的差值，进而得到第二写信号。
需要说明的是，本公开中对存储器的内存规格不做具体限制，可以为DDR5内存规格的存储器，也可以为其余内存规格的存储器。
可以理解的是，本实施例中，写调平电路的写信号生成单元21可以通过第一指示信号的指定位预先确定第一指示信号所对应的缩短时间为第一信号时钟周期的奇数倍或者偶数倍，之后，再结合第一指示信号对应的缩短时间、第一时钟信号对第一写信号进行延迟处理时。进而避免用于所存储的列写潜伏周期与列写潜伏周期的缩短时间的时间规格不一致时，导致无法直接确定出缩短后的列写潜伏周期所对应的指示信号，进而使得无法对写信号进行延迟处理的问题。
在一些实施例中，第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿是否对齐。
示例性地，在对存储器进行写调平的过程中，包括有外部写调平以及内部写调平。设置内部写调平主要目的是为了在减少数据选通信号在存储器内部进行传输的传输路径的基础上，进一步确保存储器内部所接收到的第一数据选通信号的有效沿与第二写信号的有效沿是否对齐。
在内部写调平过程中，采样单元22直接基于第一数据选通信号以及与采样单元22连接的写信号生成单元21生成的第二写信号，输出第二采样信号，以便通过第二采样信号，确定出第一数据选通信号的有效沿与第二写信号的有效沿是否对齐。例如，采样单元22可以通过将第一数据选通信号的各个有效沿对应的时间与第二写信号的各个有效沿所对应的时间进行求差处理，以便确定出第一数据选通信号的有效沿与第二写信号的有效沿是否对齐。
在一些实施例中，图2为本公开实施例提供的第二种应用于存储器的写调平电路的电路结构示意图。如图2所示，在图1所示的写调平电路的结构示意图的基础上，本实施例中，第一指示信号包括至少一个二进制字符，指定位为第一指示信号的最低位，写信号生成单元21包括：
预处理模块211，用于对第一指示信号以及第一指示信号的指定位的字符进行求和处理，得到预处理信号；确定模块212，与预处理模块211连接，用于基于第一时钟信号、预处理信号、第二指示信号、以及第一指示信号的指定位，对第一写信号进行延迟处理，输出第二写信号；第二指示信号用于指示存储器的列写潜伏周期。
示例性地，本实施例中，当第一指示信号为二进制字符时，此时，第一指示信号的指定为可 以为第一指示信号的最低位。举例来说，当第一指示信号的最低位为0时，可以表征第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的偶数倍；当第一指示信号的最低位为1时，可以表征第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的奇数倍。
此外，本实施例中的写信号生成单元21，包括：预处理模块211，以及与预处理模块211连接的确定模块212。其中，预处理模块211，用于接收第一指示信号以及第一指示信号的指定位，并将接收到的第一指示信号与第一指示信号的指定位进行求和处理，进而得到预处理信号。
可以理解的是，若第一指示信号的最低位为0表征第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的偶数倍，第一指示信号的最低位为1表征第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的奇数倍时，此时，若第一指示信号的最低位为0，则求和处理之后得到的预处理信号的最低位为0；若第一指示信号的最低位为1，则求和处理后得到的预处理信号的最低位也为0；即通过将第一指示信号的最低位与第一指示信号进行求和处理之后，得到的预处理信号所指示的缩短时间为第一时钟信号的时钟周期的偶数倍；并且，若设置有上述写调平电路的存储器规格要求中，规定有预处理信号的取值越大，则与该预处理信号对应的缩短时间越大的规范，则此时通过求和处理得到的预处理信号所对应的缩短时间大于或等于第一指示信号所对应的缩短时间。
此外，本实施例中写调平电路中所设置的确定模块212，可用于接收存储器外部的控制器发送的第二指示信号，其中，第二指示信号用于指示存储器的列写潜伏周期。在一些实施例中，存储器的列写潜伏周期可以基于所需要的存储器的读写速率来确定，即，当需要改变存储器的读写速率时，此时可以通过调整向存储器下发的第二指示信号所指示的列写潜伏周期，以确保存储器的读写速率达到所需要求。
当确定模块212接收到与确定模块212连接的预处理模块211输出的预处理信号时，此时，确定模块212会基于接收到的第一时钟信号、预处理信号、第二指示信号以及第一时钟信号的指定位，对第一写信号进行延迟处理，进而得到第二写信号。
在一些实施例中，在确定模块212对第一写信号进行延迟处理时，首先会基于第一指示信号的指定位确定第一指示信号所指示的缩短时间为第一时钟信号的时钟周期的奇数倍时，确定模块212会请求预处理模块211转发预处理模块211当前接收到的第一指示信号，之后确定模块212基于第一指示信号以及预处理信号确定延迟时间，并对接收到的第一写信号进行延迟，得到延迟后的第一写信号之后，在基于预处理信号所指示的延迟时间对延迟后的第一写信号进行延迟，进而得到第二写信号。
可以理解的是，本实施例中，写信号生成单元21中的预处理模块211通过基于第一指示信号以及第一指示信号的指定位的字符进行求和处理之后，得到预处理信号，使得预处理信号所指示的缩短时间和第二指示信号所指示的列写潜伏周期的时间的时间规格一致，例如，上述两个信号所指示的时间均为第一时钟信号的时钟周期的偶数倍，进而二者进行求差处理后所得到的缩短后的列写潜伏周期也可以在存储器预先设置的规格要求中，避免了第一指示信号与第二指示信号二者所指示的时间不一致时，无法得到二者求差后所对应的时间在存储器预设规格规范中所对应的指示信号的问题。
图3为本公开实施例提供的第三种应用于存储器的写调平电路的电路结构示意图，如图3所示，在图2所示的装置结构的基础上，本实施例所提供的确定模块212，包括：
处理子模块2121，与预处理模块211连接，用于基于预处理信号，以及第二指示信号，确定 第三指示信号，第三指示信号用于指示第一写信号当前需要延迟的时间；移位寄存器2122，用于基于第三指示信号，以及第一时钟信号，对第一写信号进行延迟处理，得到第三写信号；补偿器2123，与移位寄存器2122连接，基于第一指示信号的指定位，以及第一时钟信号，对第三写信号的时延进行补偿处理，得到第二写信号。
示例性地，本实施例中，确定模块212中包括：处理子模块2121、与处理子模块2121连接的移位寄存、以及与移位寄存器2122连接的补偿器2123。
其中，处理子模块2121，用于接收与处理子模块2121连接的预处理模块211输出的预处理信号。此外，处理子模块2121还用于接收第二指示信号，可以理解的是，预处理信号可以作为当前存储器的列写潜伏周期需要缩短的时间，第二指示信号用于指示存储器的列写潜伏周期，并且，预处理信号所指示的缩短时间的时间规格与第二指示信号所指示的存储器的列写潜伏周期的时间规格一致，因此，处理子模块2121，可以基于第二指示信号以及预处理信号，确定出第三指示信号，其中，第三指示信号用于指示第一写信号当前需要延迟的时间。
之后，写调平电路中的移位寄存器2122在接收到第三指示信号之后，会基于第三指示信号以及第一时钟信号对第一写信号进行移位处理，即对第一写信号进行延迟处理，进而得到第三写信号。
此外，在写调平电路中还设置有补偿器2123，可以理解的是，由于预处理信号所指示的缩短时间大于或者等于存储器中预处理模块211所接收到的第一指示信号所指示的缩短时间，因此，当预处理信号所指示的缩短时间大于第一指示信号所指示的缩短时间时，此时，会导致第一写信号与第三写信号之间的延时时间小于原本的延时时间，其中，原本的延时时间为存储器的列写潜伏周期与第一指示信号所指示的缩短时间之间的差值。因此，补偿器2123还会对第三写信号进行补偿处理，以便得到的第二写信号与第一写信号之间延时时间等于原本的延时时间。
在一些实施例中，补偿器2123会基于第一指示信号的指定位所对应的字符确定预处理模块211输出的预处理信号与第一指示信号是否相同，当补偿器2123确定第一指示信号与预处理信号不同时，则此时需要进行补偿处理。当补偿器2123确定第一指示信号与预处理信号相同时，则此时可以直接将第三写信号作为写信号生成单元21最终输出的第二写信号。
需要说明的是，在一些实施例中，确定模块212中的补偿器2123也可以设置在处理子模块2121之前，即，补偿器2123分别与处理子模块2121和移位寄存器2122连接，处理子模块2121与移位寄存器2122连接，其中，补偿器2123基于第一指示信号的指定位对第一写信号的时延进行补偿处理，并将补偿处理后的信号输出至与补偿器2123连接的移位寄存器2122，以便移位寄存器2122可以基于与其连接的处理子模块2121输出的第三指示信号对补偿处理后的信号，进行延迟处理，进而得到第二写信号。
可以理解的是，本实施例中，确定模块212中可以设置处理子模块2121，来对第二指示信号以及预处理模块211发送至处理子模块2121的预处理信号进行处理，进而得到第三指示信号，以便与处理子模块2121连接的移位寄存器2122可以基于处理子模块2121发送的第三指示信号对第一写信号进行延迟处理，得到第三写信号。之后，确定模块212中的补偿器2123还会基于第一指示信号的指定为对第三写信号进行补偿处理，进而得到第二写信号。通过上述方法，可以确保最终得到的第二写信号与第一写信号之间的延时时间符合第一指示信号和第二指示信号所对应的时间差值，进而确保存储器的写调平过程的准确性。
在一些实施例中，在图3所示的写调平电路的基础上，写调平电路中的处理子模块2121，具 体用于：
基于预处理信号与第一映射关系，并将第一映射关系中与预处理信号相同的第一指示信号所对应的存储器的列写潜伏周期的缩短时间确定为预处理信号对应的第一延迟时间；其中，第一延迟时间用于表征存储器的列写潜伏周期的当前需要缩短的时间；第一映射关系用于指示存储器的多个第一指示信号，以及与第一指示信号一一对应的存储器的列写潜伏周期的缩短时间；
基于第二指示信号与第二映射关系，确定第二指示信号对应的列写潜伏周期；第二映射关系用于指示存储器的多个第二指示信号，以及与第二指示信号一一对应的列写潜伏周期；
对预处理信号对应的第一延迟时间与第二指示信号对应的列写潜伏周期进行求差处理，得到第二延迟时间，并基于第二延迟时间与第二映射关系，确定第二延迟时间对应的指示信号为第三指示信号。
示例性地，本实施例中，在存储器中可以设置第一寄存器以及第二寄存器，其中，第一寄存器可用于存储第一指示信号，第二寄存器可用于存储第二指示信号。
举例来说，当存储器分别设置有高位数据选通信号接收引脚以及低位数据选通信号接收引脚时，此时则需要分别对存储器的高位数据选通信号接收引脚所接收到的信号以及低位数据选通信号接收引脚接收到的信号进行写调平处理。当第一寄存器中的位数为8位时，此时，第一寄存器的低四位可用于存储在对低位数据选通信号进行写调平时所接收到的第一指示信号，第一寄存器的高四位可用于存储在对高位数据选通信号进行写调平时所接收到的第一指示信号。而，在第二寄存器中可用于存储所接收到的第二指示信号。
本实施例中的第一映射关系可以用于表示第一寄存器中的第一指示信号所对应的存储器的列写潜伏周期的缩短时间。例如，当第一寄存器中的第一指示信号为0000时，此时，基于第一映射关系可以确定出该第一指示信号所对应的存储器的列写潜伏周期的缩短数据为0tck，其中tck用于表征第一时钟信号的时钟周期。即，第一映射关系可用于指示多个第一指示信号，以及与多个第一指示信号中的每一第一指示信号所对应的列写潜伏周期的缩短时间。
本实施例中的第二映射关系，用于表示第二寄存器中的第二指示信号所指示的列写潜伏周期。例如，当第二指示信号为00000时，此时，基于第二映射关系可用于确定出00000所对应的列写潜伏周期为22tck。即，第二映射关系用于指示存储器的多个第二指示信号，以及与第二指示信号一一对应的第二指示信号，其中，第二指示信号用于指示存储器的列写潜伏周期。也就是说，第一映射关系用于指示第一指示信号与列写潜伏周期的缩短时间之间的对应关系，第二映射关系用于指示第二指示信号与列写潜伏周期之间的对应关系。当处理子模块2121，接收到预处理信号以及第二指示信号之后，会基于第一映射关系，在第一映射关系中查找与所接收到的预处理信号相同的第一指示信号所对应的存储器的列写潜伏周期的缩短时间，并将该列写潜伏周期的缩短时间作为预处理信号所对应的第一延时时间，其中该第一延时时间可以看做是存储器的列写潜伏周期当前需要缩短的时间。并且，还会基于第二映射关系，在第二映射关系中查找与所接收到的第二指示信号所对应的列写潜伏周期。之后，处理子模块2121，对列写潜伏周期与第一延时时间求差之后，得到第二延时时间。并且，处理子模块2121还会基于第二映射关系中，查找与第二延时时间所对应的指示信号，并将该指示信号作为第三指示信号。
可以理解的是，当移位寄存器2122是基于第一映射关系，以及接收到的第三指示信号对第一写信号进行延迟处理时，本实施例中所提供的处理子模块2121确定第三指示信号的方式，可以确保移位寄存器2122可以准确的识别出第三指示信号所对应的延迟时间，并实现对第一写信号的延 迟处理，进而确保存储器的写调平过程的准确性。
在一些实施例中，在图3所示的写调平电路结构的基础上，本实施例中的补偿器2123，具体用于；
若确定第一指示信号的指定位的字符表征缩短时间为第一时钟信号的时钟周期的偶数倍，则将第三写信号作为第二写信号；若确定第一指示信号的指定位的字符表征缩短时间为第一时钟信号的时钟周期的奇数倍，将第三写信号进行延迟处理，得到第二写信号，延迟处理的时长为预处理信号对应的第一延迟时间与第一指示信号指示的存储器的列写潜伏周期的缩短时间的差值。
示例性地，本实施例中，当存储器的规格要求中列写潜伏周期均为时钟信号的时钟周期的偶数倍，列写潜伏周期的缩短时间均为时钟信号的时钟周期的整数倍时，若第一指示信号的指定位字符表征缩短时间为第一时钟信号的时钟周期的偶数倍，则此时，预处理模块211在对第一指示信号的指定位以及第一指示信号进行求和处理时，所得到的预处理信号与第一指示信号相同，则补偿器2123直接将与其连接的移位寄存器2122输出的第三写信号作为第二写信号输出。
当第一指示信号的指定位字符表征缩短时间为第一时钟信号的时钟周期的奇数倍时，预处理模块211在对第一指示信号的指定位以及第一指示信号进行求和处理时，所得到的预处理信号所指示的缩短时间为第一时钟信号的时钟周期的偶数倍，由于求和处理后预处理信号所指示的当前需要缩短的时间大于第一指示信号所指示的缩短时间，因此，补偿器2123还会对与其连接的移位寄存器2122输出的第三写信号进行延迟处理，并将延迟处理后的信号作为第二写信号输出。可以理解的是，为了确保第一写信号与第二写信号之间的时延符合第一指示信号与第二指示信号各自所指示的时间的差值，此时补偿器2123在对第三写信号进行延迟处理时延迟处理的时长即为预处理信号所指示的第一延迟时间与第一指示信号所指示的缩短时间之间的差值。
举例来说，如下表所示，表1和表2分别为本公开实施例提供的一种第一映射关系和第二映射关系的示意表。
表1 为本公开实施例提供的一种第一映射关系的示意表
Figure PCTCN2022132674-appb-000001
表2 为本公开实施例提供的一种第二映射关系的示意表
Figure PCTCN2022132674-appb-000002
从表2中可以看出，列写潜伏周期的取值均为第一时钟信号的时钟周期的偶数倍。从表1中可以看出第一指示信号所对应的缩短时间(即表征的第一延时时间)为第一时钟信号的时钟周期的整数倍。并且，从表1中可以看出，当第一指示信号采用二进制计数方式时，此时，当第一指示信号的最低位的字符为0时，所对应的列写潜伏周期为第一时钟信号的偶数倍。当第一指示信号的最低位的字符为1时，所对应的列写潜伏周期为第一时钟信号的奇数倍。需要说明的是，表格中的tck，用于表征第一时钟信号的时钟周期。即，表格中的22tck，用于表征存储器的列写潜伏周期为第一时钟信号的时钟周期的22倍。
当预处理模块211接收到的第一指示信号为0001时，此时，预处理模块211会将第一指示信号0001与第一指示信号的最低位1进行求和处理，进而得到预处理信号0010；处理子模块2121，在接收到与其连接的预处理模块211发送的预处理信号0010以及第二指示信号00001时，会将预处理信号0010对应的第一延迟时间2tck，与第二指示信号00001对应的列写潜伏周期24tck，进行求差处理，得到22tck。并且，基于第二映射关系以及求差处理结果22tck，确定出22tck对应的第二指示信号为00000，并将该第二指示信号作为第三指示信号，发送至与处理子模块2121连接的移位寄存器2122。移位寄存器2122基于接收到的第三指示信号以及第一时钟信号，会对第一写信号进行延迟处理，且延迟处理的时间为22tck，进而得到第三写信号，并将第三写信号输出至与移位寄存器2122连接的补偿器2123。补偿器2123在接收到第一指示信号的指定位1之后，会确定出当前得到的第三写信号与第一写信号之间的延迟时间被缩短，并且，由于从第一映射表中可以确定出，通过将第一指示信号与第一指示信号的最低位1进行求和处理之后得到的预处理信号，为该在第一映射关系中与该第一指示信号相邻的下一第一指示信号，且相邻的第一指示信号所对应的缩短时间之间的差值为1tck，因此，补偿器2123可以对接收到的第三写信号继续进行延迟处理，且延迟时长为1tck，进而得到第二写信号。此时，第二写信号与第一写信号之间的延迟时间为23tck，等于第二指示信号00001对应的列写潜伏周期24tck与第一指示信号0001所对应的缩短时间1tck之间的差值。
当预处理模块211接收到的第一指示信号为0010时，此时，预处理模块211会将第一指示信号0010与第一指示信号的最低位0进行求和处理，进而得到预处理信号0010(此时，第一指示信号与预处理信号相同)；处理子模块2121，在接收到与其连接的预处理模块211发送的预处理信号0010以及第二指示信号00001时，会将预处理信号0010对应的第一延迟时间2tck，与第二指示信号00001对应的列写潜伏周期24tck，进行求差处理，得到22tck。并且，基于第二映射关系以及求差处理结果22tck，确定出22tck对应的第二指示信号为00000，并将该第二指示信号作为第三指示信号，发送至与处理子模块2121连接的移位寄存器2122。移位寄存器2122基于接收到的第三指示信号以及第一时钟信号，会对第一写信号进行延迟处理，且延迟处理的时间为22tck，进而得到第三写信号，并将第三写信号输出至与移位寄存器2122连接的补偿器2123。补偿器2123在接收到第一指示信号的指定位0之后，会确定出当前得到的第三写信号与第一写信号之间的延迟时间未被缩短，则可以直接将第三写信号作为第二写信号输出至采样单元22。
在一些实施例中，图4为本公开实施例提供的一种补偿器2123的电路结构示意图，如图所示，补偿器2123，包括：
延迟器21231，与移位寄存器2122连接，用于对移位寄存器2122输出的第三写信号进行延迟处理，得到延迟处理后的第三写信号；
第一数据选择器21232，第一数据选择器21232分别与延迟器21231以及第一数据选择器 21232连接，用于接收延迟器21231输出的延迟处理后的第三写信号以及移位寄存器2122输出的第三写信号；第一数据选择器21232还用于接收第一指示信号的指定位，第一数据选择器21232用于确定第一指示信号的指定位的字符表征第一时钟信号的时钟周期的偶数倍，则将第三写信号作为第二写信号输出；第一数据选择器21232用于确定第一指示信号的指定位的字符表征第一时钟信号的时钟周期的奇数倍，则将延迟处理后的第三写信号作为第二写信号输出。
示例性地，本实施例中，补偿器2123中包括延迟器21231以及第一数据选择器21232。其中，延迟器21231与确定模块212中的移位寄存器2122连接，用于接收移位寄存器2122输出的第三写信号，并对接收到的第三写信号进行延迟处理，进而得到延迟处理后的第三写信号，并将延迟处理后的第三写信号输出至与延迟器21231连接的第一数据选择器21232。此外，第一数据选择器21232还与确定模块212中的移位寄存器2122连接，用于接收移位寄存器2122输出的第三写信号。此外，第一数据选择器21232还用于接收第一指示信号的指定位的字符，并基于第一指示信号的指定位的字符，在延迟处理后的第三写信号和第三写信号中选择当前需要输出的信号。
并且，当第一数据选择器21232确定第一指示信号的指定位的字符表征第一时钟信号的时钟周期的偶数倍，则将第三写信号作为第二写信号输出；若第一数据选择器21232用于确定第一指示信号的指定位的字符表征第一时钟信号的时钟周期的奇数数倍，则将延迟处理后的第三写信号作为第二写信号输出。
可以理解的是，本实施例中通过设置延迟器21231与第一数据选择器21232的方式，确定最终输出的第二写信号的方式，电路结构较为简单且容易实现。
图5为本公开实施例提供的第四种应用于存储器的写调平电路的电路结构示意图，在图2所示的结构的基础上，本实施例中，写信号生成单元21中还包括译码器213。其中，译码器213，与确定模块212连接，用于对接收到的写指令进行解码处理，输出第一写信号。
示例性地，如图5所示，本实施例中的写信号生成电路包括有译码器213、预处理模块211、以及确定模块212。其中，译码器213所接收到的写指令，可以看作是内部包含有该写信号生成电路的存储器其外部所对应的控制器所发送的写指令，即控制器发送至存储器引脚处的写指令，用于指示存储器当前需要进行写操作。
写信号生成电路中的译码器213当接收到写指令之后，可以对写指令进行解码处理，进而得到存储器内部的器件所能识别的用于表征当前需要进行写操作的第一写信号，之后，译码器213将得到的第一写信号发送至与译码器213连接的确定模块212，由确定模块212基于与其连接的预处理模块211生成的预处理信号、第一时钟信号、第一指示信号的指定位以及第二指示信号对其接收到的第一写信号进行延迟处理，进而得到第二写信号，并将第二写信号输出至与确定模块212连接的采样单元22。
可以理解的是，本实施例中通过在写信号生成单元21中设置译码器213，对译码器213接收到的写指令进行解码处理，以便存储器中的器件可以准确确定出当前需要存储器需要进行写操作。此外，后续在基于该写调平电路进行信号调整时，控制器可以得到更为准确的确定出该存储器需要的数据选通信号，提高存储器数据写入的准确度。
图6为本公开实施例提供的第五种应用于存储器的写调平电路的电路结构示意图，在图5所示的结构的基础上，本实施例中，写信号生成单元21，还包括：信号转换模块214；译码器213通过信号转换模块214与写信号生成单元21连接；信号转换模块214，用于对译码器213输出的第一写信号，进行脉冲展宽处理，输出展宽后的写信号，并将展宽后的写信号作为第一写信号输 出至确定模块212。
示例性地，本实施例中在写调平电路中的写信号生成单元21中包括有译码器213、信号转换模块214以及确定模块212。其中，译码器213用于接收写指令，并对写指令进行解码处理，并将解码处理后的信号发送至与译码器213连接的信号转换模块214。之后，信号转换模块214，对译码器213输出的解码处理后的信号进行脉冲展宽处理，并将脉冲展宽处理后的信号作为第一写信号输出至与其连接的确定模块212，以便确定模块212可以对其接收到的第一写信号进行延迟处理，进而得到第二写信号，输出至与确定模块212连接的采样单元22。
可以理解的是，本实施例中写信号生成单元21中的信号转换模块214，通过对译码器213输出至信号转换模块214的信号进行脉冲展宽处理，以便满足存储器对应的规格要求(例如，SPEC要求)。
在上述任一实施例的基础上，采样单元22中设置有第二触发器222，第二触发器222的数据端与写信号生成单元21连接，用于接收写信号生成单元21输出的第二写信号；第二触发器222的时钟端用于接收第一数据选通信号，第二触发器222用于基于第二写信号与第一数据选通信号，输出第二采样信号。
示例性地，本实施例中，第二触发器222的时钟端用于接收第一数据选通信号，第二触发器222的数据端与写信号生成单元21连接，用于接收写信号生成单元21输出的第二写信号，之后，第二触发器222基于接收到的第一数据选通信号的有效沿，对第二触发器222所接收到的第二写信号进行采样，并将采样结果作为第二采样信号。
可以理解的是，本实施例中通过设置第二触发器222来比较第二写信号的有效沿与第一数据选通信号的有效沿是否对齐的方式，容易实现，避免了对两个信号的有效沿之间的时间差值进行计算的复杂过程。
在上述任一实施例的基础上，本实施例中所提供的写调平电路还包括：延时单元23，用于对接收到的第一数据选通信号进行延迟处理，输出第二数据选通信号；采样单元22，与延时单元23连接，还用于接收延时单元23输出的第二数据选通信号，并根据第二数据选通信号和第二写信号，输出第一采样信号；第一采样信号表征第一时钟信号的有效沿与第一数据选通信号的有效沿是否对齐。
示例性地，为了实现存储器写调平训练中的外部写调平过程，其中，外部写调平用于对齐存储器引脚出接收到的数据选通信号的有效沿以及时钟信号的有效沿。本实施例中，在写调平电路中还设置有延时单元23。其中，延时单元23可用于将其接收到的第一数据选通信号进行延迟处理，进而得到第二数据选通信号，并将第二数据选通信号发送至与延时单元23连接的采样单元22。其中，当该写调平电路设置在存储器内部时，此时，延时单元23接收到的第一数据选通信号可以认为是存储器内部传输的数据选通信号，该信号可以由存储器引脚处所接收到的数据选通信号转换得到。
此外，本实施例中的采样单元22，还用于基于与其连接的写信号生成单元21输出的第二写信号以及与其连接的延时单元23输出的第二数据选通信号，生成第一采样信号，以便存储器外部的控制器可以基于接收到的第一采样信号调整控制器向存储器发送的信号，进而确保存储器引脚处接收到的数据选通信号的有效沿以及时钟信号的有效沿之间的时间差值满足存储器所规定的时间差值范围。
需要说明的是，本实施例中，延时单元23对第一数据选通信号的延迟处理时的时延，等效于 写信号生成单元21在接收到第一时钟信号时对第一写信号进行延迟处理得到第二写信号的时延，进而采样单元22可以通过比较第二数据选通信号的有效沿与第二写信号的有效沿是否对齐，来确定第一数据选通信号的有效沿和第一时钟信号的有效沿是否对齐。
可以理解的是，通过上述对延时单元23的时延的设置，使得存储器外部的控制器可以基于采样单元22输出的第一采样信号来确定是否达到存储器的外部写调平的目的。
在上述实施例的基础上，图7为本公开实施例提供的第六种应用于存储器的写调平电路的电路结构示意图。如图7所示，在图1所示的写调平电路的结构的基础上，本实施例中的写调平电路中包括：延时单元23、写信号生成单元21以及采样单元22。其中，采样单元22中包括：第一触发器221、第二触发器222、第二数据选择器223，其中，第一触发器221的数据端与写信号生成单元21连接，用于接收写信号生成单元21输出的第二写信号；第一触发器221的时钟端与延时单元23的输出端连接，用于接收延时单元23输出的第二数据选通信号；第一触发器221用于基于第二写信号与第二数据选通信号，输出第一采样信号；第二触发器222的数据端与写信号生成单元21连接，用于接收写信号生成单元21输出的第二写信号；第二触发器222的时钟端用于接收第一数据选通信号，第二触发器222用于基于第二写信号与第一数据选通信号，输出第二采样信号；第一触发器221的输出端与第二数据选择器223的第一端连接，第二触发器222的输出端与第二数据选择器223的第二端连接。
示例性地，如图7所示，本实施例中的写调平电路中包括延时单元23、写信号生成单元21、采样单元22，并且，采样单元22中还设置有第一触发器221、第二触发器222以及第二数据选择器223。其中，第一触发器221的时钟端与数据端，分别与延时单元23和写信号生成单元21连接，进而第一触发器221基于其时钟端所接收到的与其连接的延时单元23发送的时钟信号的有效沿，对第一触发器221的数据端所接收到的与其连接的写信号生成单元21输出的第二写信号进行采样，并将采样结果作为第一采样信号，输出至与第一触发器221连接的第二数据选择器223。
此外，第二触发器222时钟端用于接收第一数据选通信号，第二触发器222的数据端与写信号生成单元21连接，用于接收写信号生成单元21输出的第二写信号，之后，第二触发器222基于接收到的第一数据选通信号的有效沿，对第二触发器222所接收到的第二写信号进行采样，并将采样结果作为第二采样信号，输出至与第二触发器222连接的第二数据选择器223。
第二数据选择器223在接收到与其连接的第一触发器221发送的第一采样信号以及与其连接的第二触发器222发送的第二采样信号之后，会选择在其中选择一个采样信号输出，以便存储器外的控制器可以基于接收到的第一采样信号或者第二采样信号进行调整控制器发送至该存储器的信号。
可以理解的是，本实施例中通过在采样单元22中设置第一触发器221、第二触发器222以及第二数据选择器223，相比于同时将第一采样信号以及第二采样信号同时发送至控制器，本实施例中所提供的采样单元22的装置，可以减少控制器上数据接收端口的占用，当写调平电路封装在存储器中时，还可以减少存储器上引脚的占用。
在上述实施例的基础上，图8为本公开实施例提供的第七种应用于存储器的写调平电路的电路结构示意图。如图8所示，在图7所示的写调平电路的结构的基础上，本实施例所提供的写调平电路中还包括有第一转换器24以及第二转换器25。第一转换器24，分别与延时单元23和采样单元22连接，用于对接收到的第三数据选通信号进行逻辑电平转换处理，得到第一数据选通信号；其中，第三数据选通信号的电平为电流模式逻辑电平；第一数据选通信号的电平为CMOS电平。第 二转换器25，与写信号生成单元21连接，用于对接收到的第二时钟信号进行逻辑电平转换处理，得到第一时钟信号；其中，第二时钟信号的电平为电流模式逻辑电平；第一时钟信号的电平为CMOS电平。
示例性地，在图7所示的写调平电路的结构的基础上，本实施例中还包括有第一转换器24。其中，第一转换器24所接收到的第三数据选通信号，在实际应用中可以认为是存储器外部的控制器发送至存储器的引脚处的数据选通信号。而在控制器向存储器发送第三数据选通信号时，为了提高信号的传输效率，通常采用电流模式逻辑(Current Model Logic，简称CML)电平的传输形式。而在存储器内部通常采用互补金属氧化物半导体(Complementary Metal Oxide Semiconducto，简称CMOS)电平的传输形式进行信号传输。因此，在写调平电路中的第一转换器24在引脚处获取到第三数据选通信号之后，会将采用CML电平传输形式传输的第三数据选通信号转换为采用CMOS电平传输形式传输的第一数据选通信号，之后将第一数据选通信号分别传输至与第一转换器24连接的延时单元23以及采样单元22中的第二触发器222，以便存储器中的写调平电路中的各个器件可以准确识别该第一数据选通信号。
此外，在写调平电路中还包括有第二转换器25。其中，第二转换器25所接收到的第二时钟信号，在实际应用中可以认为是存储器外部的控制器或者与其串联的前一存储器发送至该存储器的引脚处的时钟信号。而在控制器向存储器发送时钟信号或者存储器之间发送时钟信号时，为了提高信号的传输效率，通常采用电流模式逻辑(Current Model Logic，简称CML)电平的传输形式。而在存储器内部通常采用CMOS电平的传输形式进行信号传输。因此，在写调平电路中的第二转换器25在引脚处获取到第二时钟信号之后，会将采用CML电平传输形式传输的第二时钟信号转换为采用CMOS电平传输形式传输的第一时钟信号，之后将第一时钟信号传输至与第二转换器25连接的写信号生成单元21，以便存储器中的写调平电路中的各个器件可以准确识别该第一时钟信号。
在一些实施例中，第一采样信号具体用于在第一采样信号表征第一时钟信号的有效沿与第一数据选通信号的有效沿未对齐时，指示调整第一时钟信号的时延；第二采样信号具体用于在第一采样信号表征第一时钟信号的有效沿与第一数据选通信号的有效沿对齐，且第一数据选通信号的有效沿与第二写信号的有效沿未对齐时，指示调整第一写信号的时延或者第一数据选通信号的时延。
示例性地，本实施例中，为了实现对存储器外部写调平过程，当存储器外部的控制器确定出第一采样信号表征第一时钟信号的有效沿与第一数据选通信号的有效沿未对齐时，此时，控制器可以不断调整向存储器发送的数据选通信号的时延，即不断调整第一数据选通信号的时延，以便达到第一时钟信号的有效沿与第一数据选通信号的有效沿对齐的目的。
此外，在内部写调平过程中，为了避免存储器内部信号传输时消耗的功率较大的问题，可采用以下方式进行调整。本实施例中，当外部写调平过程结束之后，即当在第一采样信号表征第一时钟信号的有效沿与第一数据选通信号的有效沿对齐后，并且第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐时，此时，可以通过调整第一写信号的时延或者第一数据选通信号的时延，以便达到第一数据选通信号的有效沿与第二写信号的有效沿对齐的目的。
可以理解的是，相比于外部写调平过程中第一数据选通信号需要通过延时单元23的延迟处理后再输出的方式，在内部写调平过程中，无需对第一数据选通信号进行延迟处理，相当于减少了第一数据选通信号在存储器内部传输时的时延，并且之后还可以通过调整第一写信号的时延，减少第一写信号在传输过程中所造成的功耗，之后，再不断调整第一写信号的时延或者第一数据选 通信号的时延过程中，以确保达到内部写调平的目的。
图9为本公开实施例提供的一种应用于存储器的写调平电路的控制方法的流程示意图，本实施例所提供的方法应用于图1所示的写调平电路中，该方法包括以下步骤：
S901、若确定第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐，则调整第一数据选通信号的时延或者第一指示信号。
重复步骤S901，直至基于采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐。
示例性地，本实施例的执行主体可以为存储器外部的控制器或者其余电子设备，本公开不做具体限制。下面以控制器为本公开的执行主体为例描述。
本实施例中，当外部写调平过程结束之后，需要继续对存储器进行内部写调平。在对存储器进行内部写调平时，首先当控制器基于第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿未对齐时，此时，控制器可以通过调整第一数据选通信号或者第一指示信号来确保第一数据选通信号的有效沿与第二写信号的有效沿对齐，即确保存储器内部的存储单元部分所接收到的数据选通信号以及写信号是对齐的。其中，调整第一指示信号，相当于调整第一写信号与第二写信号之间的时延。
S902、当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将第一数据选通信号的时延延长预设时段，并将延长后的信号确定为存储器进行写操作时所接收到的数据选通信号。
示例性地，为了进一步确保存储器引脚处所接收到的数据选通信号的有效沿与引脚处接收到的时钟信号的有效沿之间的时间差值满足存储器的规格要求，本实施例中，控制器在确定第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿对齐时，此时，可以将对齐时的第一数据选通信号的时延延长预设时段，并将时延延长后的数据选通信号作为存储器在进行写操作时所接收到的第一数据选通信号。并且，此时延长预设时段后的第一数据选通信号有效沿，相比于对齐时的存储器引脚处接收到的第一时钟信号的有效沿，两个有效沿之间的时间差值符合存储器规格所要求的时间差值(例如，存储器的tDQSoffset)。
需要说明的是，本公开中的预设时段，可以通过基于写入前导码(write preamble)信号以及写入前导码信号和预设时长之间的对应关系确定的。
可以理解的是，本实施例中，为了减少数据选通信号以及写信号在存储器内部传输时所造成的功耗，在内部写调平过程中，控制器会基于所接收到的第二采样信号来不断调整第一数据选通信号的时延或者第一写信号的时延，以便使得最终完成对存储器的写调平过程，使得存储器可以准确的写入数据。并且通过对第一数据选通信号的有效沿与第二写信号的有效沿对齐时的第一数据选通信号的时延延长预设时段，进而确定出存储器引脚端最终需要接收到的数据选通信号，以便存储器可以准确的写入数据。
在一些实施例中，在存储器外部的控制器基于采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿是否对齐时，可以通过以下方式确定：
若采样单元输出的第二采样信号的电平值从第二电平值变化至第一电平值，则确定第一数据选通信号的有效沿与第二写信号的有效沿对齐。
示例性地，本实施例中，在采样单元基于接收到的第一数据选通信号以及接收到的写信号生成单元输出的第二写信号之后，为了确定第一数据选通信号的有效沿与第二写信号的有效沿是否对齐，可以通过在第一数据选通信号的有效沿处对第二写信号的电平值进行采样，并将采样结果 作为采样单元输出的第二采样信号，进而可以通过不断监测第二采样信号的电平值的变化，当第二采样信号的电平值从第二电平值切换至第一电平值时，此时，表征第二写信号的有效沿与第一数据选通信号的有效沿对齐。
可以理解的是，本实施例中，可以通过检测第二采样信号的电平值变化是否从第二电平值切换至第一电平值，来确定第一数据选通信号的有效沿与第二写信号的有效沿是否对齐。本实施例提供的方法简单，容易实现，无需多次重复计算信号有效沿之间的时间差值。
图10为本公开实施例提供的又一种应用于存储器的写调平电路的控制方法的流程示意图，该方法包括以下步骤：
S1001、若确定采样单元输出的第二采样信号的电平值为第一电平值，则调整写信号生成单元接收到的第一指示信号，以增大第一指示信号所指示的存储器的列写潜伏期的缩短时间，并向写信号生成单元下发调整后的第一指示信号。
重复上述步骤S1001，直至采样单元输出的第二采样信号的电平值从第一电平值转换至第二电平值。
示例性地，本实施例中，在存储器进行内部写调平时，控制器通过实时确定采样单元输出的第二采样信号的电平值来确定第二写信号的有效沿与第一数据选通信号的有效沿是否对齐。具体地，当控制器确定第二采样单元输出的第二采样信号的电平值为第一电平值时，此时，控制器可以通过调整向写信号生成单元发送的第一指示信号，通过调整第一指示信号，从而增大第一指示信号所指示的列写潜伏周期的缩短时间，即相应的，相当于不断减少写信号生成单元所产生的第一写信号与第二写信号之间的时延。通过对写信号生成单元所产生的第一写信号的时延的不断调整，进而减少第一数据选通信号的有效沿与第二写信号的有效沿之间的时间差值。
需要说明的是，受存储器中规格要求的限制，在调整第一指示信号所指示的列写潜伏周期的缩短时间时，列写潜伏周期的缩短时间只能取第一时钟信号的时间周期的整数倍，导致在调整第一写信号的时延时，每次时延的改变值只能为时间周期的整数倍，当第二采样信号的输出的采样值从第一电平值切换到第二电平值时，此时，第一数据选通信号的有效沿与第二写信号的有效沿可能并未对齐，会出现第一数据选通信号的有效沿所对应的时间晚于第二写信号的有效沿所对应的时间的现象，因此，还需要调整第一数据选通信号的时延。
S1002、若确定采样单元输出的第二采样信号的电平值为第二电平值，减小采样单元接收到的第一数据选通信号的时延，向写信号生成单元下发第二延迟信号，其中，第二延迟信号为采样单元输出的第二采样信号从第一电平值切换至第二电平值时，写信号生成单元接收到的第一指示信号。
重复上述步骤S1002，直至采样单元输出的第二采样信号的电平值从第二电平值切换至第一电平值。
示例性地，在完成上述步骤S1001中的调整之后，为了确保第一数据选通信号的有效沿与第二写信号的有效沿对齐，在本步骤中，还会对第一数据选通信号的时延进行调整。由于第一数据选通信号的时延不受存储器规格的限制，每次时延的调整的变化量无需为第一时钟信号的时钟周期的整数倍，因此，本步骤中，可以通过对第一数据选通信号的时延不断调整，即通过不断减少第一数据选通信号的时延，使得第一数据选通信号的有效沿与第二数据选通信号的有效沿对齐。并且，每次向存储器发送调整后的第一数据选通信号时，还需要向存储器中的写信号生成单元发送第二延迟信号，此时的第二延迟信号为第二采样信号从第一电平值切换至第二电平值时，确定 模块所接收到的第一指示信号，即步骤S1001循环执行结束时确定模块所接收到的第一指示信号。
S1003、当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将第一数据选通信号的时延延长预设时段，并将延长后的信号确定为存储器进行写操作时所接收到的数据选通信号。
示例性地，本步骤的具体原理可以参见步骤S902，此处不再赘述。
可以理解的是，本实施例中，在进行存储器的内部调整的过程中，首先会通过减少第一写信号延迟处理时的时延，来减少第一写信号在传输过程中的功耗。之后，在通过调整第一数据选通信号的时延，以便第一数据选通信号以及第二写信号的有效沿可以实现对齐，进而使得存储器在进行写操作时，可以实现数据的准确写入，并且还降低了写操作过程中，存储器内部信号传输时的功耗。
图11为本公开实施例提供的一种应用于存储器的写调平电路的控制装置的结构示意图，该装置包括：调整单元1101，用于若确定第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐，则调整第一数据选通信号的时延或者第一指示信号；重复第一调整单元，直至第一调整单元基于采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐：
延长单元1102，用于当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将第一数据选通信号的时延延长预设时段，并将延长后的信号确定为存储器进行写操作时所接收到的数据选通信号。
本实施例提供的装置，用于实现上述方法提供的技术方案，其实现原理和技术效果类似，不再赘述。
图12为本公开实施例提供的又一种应用于存储器的写调平电路的控制装置的结构示意图，在图12所示的装置的基础上，本实施例中，调整单元1101基于采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐时，具体用于：若采样单元输出的第二采样信号的电平值从第二电平值变化至第一电平值，则确定第一数据选通信号的有效沿与第二写信号的有效沿对齐。
在一些实施例中，调整单元1101，包括：
调整模块11011，用于若确定采样单元输出的第二采样信号的电平值为第一电平值，则调整写信号生成单元接收到的第一指示信号，以增大第一指示信号所指示的存储器的列写潜伏期的缩短时间；
第一发送模块11012，用于向写信号生成单元下发调整后的第一指示信号。
重复调整模块11011以及第一发送模块11012，直至调整模块11011确定采样单元输出的第二采样信号的电平值从第一电平值转换至第二电平值。
减少模块11012，用于若确定采样单元输出的第二采样信号的电平值为第二电平值，则减少采样单元接收到的第一数据选通信号的时延。
第二发送模块11013，用于向写信号生成单元下发第二延迟信号，其中，第二延迟信号为采样单元输出的第二采样信号从第一电平值切换至第二电平值时，写信号生成单元接收到的第一指示信号。重复减少模块11012和发送模块，直至减少模块11012确定采样单元输出的第二采样信号的电平值从第二电平值切换至第一电平值。
本实施例提供的装置，用于实现上述方法提供的技术方案，其实现原理和技术效果类似，不再赘述。
本公开提供一种存储器，存储器包括图1-图8中任一实施例所提供的写调平电路。
本公开提供一种电子设备，包括：处理器，以及与处理器通信连接的存储器；其中，存储器存储计算机执行指令；处理器执行存储器存储的计算机执行指令，以实现图9或图10任一实施例任一项所提供的方法。
图13为本公开实施例中提供的一种电子设备的结构示意图，如图13所示，该电子设备包括：
处理器(processor)291，电子设备还包括了存储器(memory)292；还可以包括通信接口(Communication Interface)293和总线294。其中，处理器291、存储器292、通信接口293、可以通过总线294完成相互间的通信。通信接口293可以用于信息传输。处理器291可以调用存储器292中的逻辑指令，以执行上述实施例的方法。
此外，上述的存储器292中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。
存储器292作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序，如本公开实施例中的方法对应的程序指令/模块。处理器291通过运行存储在存储器292中的软件程序、指令以及模块，从而执行功能应用以及数据处理，即实现上述方法实施例中的方法。
存储器292可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端设备的使用所创建的数据等。此外，存储器292可以包括高速随机存取存储器，还可以包括非易失性存储器。
本公开提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，计算机执行指令被处理器执行时用于实现如图9或图10任一实施例所提供的方法。
本公开提供一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时实现图9或图10任一实施例所提供的方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (18)

  1. 一种应用于存储器的写调平电路，所述写调平电路包括：
    写信号生成单元，用于接收第一时钟信号和第一指示信号，并根据所述第一时钟信号、所述第一指示信号、以及所述第一指示信号中的指定位，对第一写信号进行延迟处理，输出第二写信号；其中，所述第一指示信号用于指示存储器的列写潜伏周期的缩短时间，所述第一指示信号中包括指定位；所述指定位的字符用于指示所述缩短时间为所述第一时钟信号的时钟周期的奇数倍或者所述缩短时间为所述第一时钟信号的时钟周期的偶数倍；
    采样单元，与所述写信号生成单元连接，用于接收第一数据选通信号和所述第二写信号，并根据所述第一数据选通信号和所述第二写信号，输出第二采样信号。
  2. 根据权利要求1所述的写调平电路，其中，所述第一指示信号包括至少一个二进制字符，所述指定位为所述第一指示信号的最低位，所述写信号生成单元包括：
    预处理模块，用于对所述第一指示信号以及所述第一指示信号的指定位的字符进行求和处理，得到预处理信号；
    确定模块，与所述预处理模块连接，用于基于所述第一时钟信号、所述预处理信号、第二指示信号、以及所述第一指示信号的指定位，对所述第一写信号进行延迟处理，输出第二写信号；所述第二指示信号用于指示所述存储器的列写潜伏周期。
  3. 根据权利要求2所述的写调平电路，其中，所述确定模块，包括：
    处理子模块，与所述预处理模块连接，用于基于所述预处理信号，以及所述第二指示信号，确定第三指示信号，所述第三指示信号用于指示所述第一写信号当前需要延迟的时间；
    移位寄存器，用于基于所述第三指示信号，以及所述第一时钟信号，对所述第一写信号进行延迟处理，得到第三写信号；
    补偿器，与所述移位寄存器连接，基于所述第一指示信号的指定位，以及所述第一时钟信号，对所述第三写信号的时延进行补偿处理，得到所述第二写信号。
  4. 根据权利要求3所述的写调平电路，其中，所述处理子模块，具体用于：
    基于所述预处理信号与第一映射关系，并将所述第一映射关系中与所述预处理信号相同的第一指示信号所对应的存储器的列写潜伏周期的缩短时间确定为所述预处理信号对应的第一延迟时间；其中，所述第一延迟时间用于表征存储器的列写潜伏周期的当前需要缩短的时间；所述第一映射关系用于指示所述存储器的多个第一指示信号，以及与所述第一指示信号一一对应的存储器的列写潜伏周期的缩短时间；
    基于所述第二指示信号与第二映射关系，确定所述第二指示信号对应的列写潜伏周期；所述第二映射关系用于指示存储器的多个第二指示信号，以及与所述第二指示信号一一对应的列写潜伏周期；
    对所述预处理信号对应的第一延迟时间与所述第二指示信号对应的列写潜伏周期进行求差处理，得到第二延迟时间，并基于所述第二延迟时间与所述第二映射关系，确定所述第二延迟时间对应的指示信号为第三指示信号。
  5. 根据权利要求3或4所述的写调平电路，其中，所述补偿器，具体用于；
    若确定所述第一指示信号的指定位的字符表征所述缩短时间为所述第一时钟信号的时钟周期的偶数倍，则将所述第三写信号作为所述第二写信号；
    若确定所述第一指示信号的指定位的字符表征所述缩短时间为所述第一时钟信号的时钟周期 的奇数倍，将所述第三写信号进行延迟处理，得到所述第二写信号，所述延迟处理的时长为所述预处理信号对应的第一延迟时间与所述第一指示信号指示的存储器的列写潜伏周期的缩短时间的差值。
  6. 根据权利要求5所述的写调平电路，其中，所述补偿器，包括：
    延迟器，与所述移位寄存器连接，用于对所述移位寄存器输出的第三写信号进行延迟处理，得到延迟处理后的第三写信号；
    第一数据选择器，所述第一数据选择器分别与所述延迟器以及所述第一数据选择器连接，用于接收所述延迟器输出的延迟处理后的第三写信号以及所述移位寄存器输出的第三写信号；所述第一数据选择器还用于接收所述第一指示信号的指定位，所述第一数据选择器用于确定所述第一指示信号的指定位的字符表征所述第一时钟信号的时钟周期的偶数倍，则将所述第三写信号作为所述第二写信号输出；所述第一数据选择器用于确定所述第一指示信号的指定位的字符表征所述第一时钟信号的时钟周期的奇数数倍，则将所述延迟处理后的第三写信号作为所述第二写信号输出。
  7. 根据权利要求2-6中任一项所述的写调平电路，其中，所述写信号生成单元还包括：
    译码器，与所述确定模块连接，用于对接收到的写指令进行解码处理，输出所述第一写信号。
  8. 根据权利要求7所述的写调平电路，其中，所述写信号生成单元，还包括：信号转换模块；所述译码器通过所述信号转换模块与所述写信号生成单元连接；
    所述信号转换模块，用于对所述译码器输出的第一写信号，进行脉冲展宽处理，输出展宽后的写信号，并将所述展宽后的写信号作为第一写信号输出至所述确定模块。
  9. 根据权利要求1-8中任一项所述的写调平电路，其中，所述第二采样信号表征所述第一数据选通信号的有效沿与所述第二写信号的有效沿是否对齐。
  10. 根据权利要求1-9中任一项所述的电路，其中，所述采样单元，包括：
    第二触发器，所述第二触发器的数据端与所述写信号生成单元连接，用于接收所述写信号生成单元输出的第二写信号；所述第二触发器的时钟端用于接收所述第一数据选通信号，所述第二触发器用于基于所述第二写信号与所述第一数据选通信号，输出第二采样信号。
  11. 根据权利要求1-10中任一项所述的写调平电路，其中，所述写调平电路还包括：
    延时单元，用于对接收到的第一数据选通信号进行延迟处理，输出第二数据选通信号；
    所述采样单元，与所述延时单元连接，还用于接收所述延时单元输出的所述第二数据选通信号，并根据所述第二数据选通信号和所述第二写信号，输出第一采样信号；所述第一采样信号表征所述第一时钟信号的有效沿与所述第一数据选通信号的有效沿是否对齐。
  12. 根据权利要求11所述的写调平电路，其中，所述采样单元包括：第一触发器、第二触发器、第二数据选择器；
    所述第一触发器的数据端与所述写信号生成单元连接，用于接收所述写信号生成单元输出的第二写信号；所述第一触发器的时钟端与所述延时单元的输出端连接，用于接收所述延时单元输出的第二数据选通信号；所述第一触发器用于基于所述第二写信号与所述第二数据选通信号，输出第一采样信号；所述第二触发器的数据端与所述写信号生成单元连接，用于接收所述写信号生成单元输出的第二写信号；所述第二触发器的时钟端用于接收所述第一数据选通信号，所述第二触发器用于基于所述第二写信号与所述第一数据选通信号，输出第二采样信号；所述第一触发器的输出端与所述第二数据选择器的第一端连接，所述第二触发器的输出端与所述第二数据选择器 的第二端连接。
  13. 根据权利要求11或12所述的写调平电路，其中，所述写调平电路还包括：
    第一转换器，分别与所述延时单元和所述采样单元连接，用于对接收到的第三数据选通信号进行逻辑电平转换处理，得到所述第一数据选通信号；其中，所述第三数据选通信号的电平为电流模式逻辑电平；所述第一数据选通信号的电平为CMOS电平。
  14. 根据权利要求11-13中任一项所述的写调平电路，其中，所述写调平电路还包括：
    第二转换器，与所述写信号生成单元连接，用于对接收到的第二时钟信号进行逻辑电平转换处理，得到所述第一时钟信号；其中，所述第二时钟信号的电平为电流模式逻辑电平；所述第一时钟信号的电平为CMOS电平。
  15. 根据权利要求11-14中任一项所述的写调平电路，其中，所述第一采样信号具体用于在所述第一采样信号表征所述第一时钟信号的有效沿与所述第一数据选通信号的有效沿未对齐时，指示调整所述第一数据选通信号的时延；所述第二采样信号具体用于在所述第一采样信号表征所述第一时钟信号的有效沿与所述第一数据选通信号的有效沿对齐，且所述第一数据选通信号的有效沿与所述第二写信号的有效沿未对齐时，指示调整所述第一写信号的时延或者所述第一数据选通信号的时延。
  16. 一种应用于存储器的写调平电路的控制方法，所述方法应用于如权利要求1所述的电路，所述方法包括：
    重复以下步骤，直至基于所述采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐：若确定所述第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐，则调整第一数据选通信号的时延或者所述第一指示信号；
    当第一数据选通信号的有效沿与第二写信号的有效沿对齐时，将所述第一数据选通信号的时延延长预设时段，并将延长后的信号确定为所述存储器进行写操作时所接收到的数据选通信号。
  17. 根据权利要求16所述的方法，其中，基于所述采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐，包括：
    若所述采样单元输出的第二采样信号的电平值从第二电平值变化至第一电平值，则确定第一数据选通信号的有效沿与第二写信号的有效沿对齐。
  18. 根据权利要求17所述的方法，其中，所述重复以下步骤，直至基于所述采样单元输出的第二采样信号确定第一数据选通信号的有效沿与第二写信号的有效沿对齐：若确定所述第二采样信号表征第一数据选通信号的有效沿与第二写信号的有效沿未对齐，则调整第一数据选通信号的时延或者所述第一指示信号，包括：
    重复以下步骤，直至所述采样单元输出的第二采样信号的电平值从所述第一电平值转换至所述第二电平值：若确定所述采样单元输出的第二采样信号的电平值为所述第一电平值，则调整所述写信号生成单元接收到的第一指示信号，以增大所述第一指示信号所指示的存储器的列写潜伏期的缩短时间，并向所述写信号生成单元下发调整后的第一指示信号；
    重复以下步骤，直至所述采样单元输出的第二采样信号的电平值从所述第二电平值切换至所述第一电平值：若确定所述采样单元输出的第二采样信号的电平值为所述第二电平值，减少所述采样单元接收到的第一数据选通信号的时延，向所述写信号生成单元下发第二延迟信号，其中，所述第二延迟信号为所述采样单元输出的第二采样信号从第一电平值切换至第二电平值时，所述写信号生成单元接收到的第一指示信号。
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