WO2024034054A1 - ウエハ載置台 - Google Patents

ウエハ載置台 Download PDF

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Publication number
WO2024034054A1
WO2024034054A1 PCT/JP2022/030570 JP2022030570W WO2024034054A1 WO 2024034054 A1 WO2024034054 A1 WO 2024034054A1 JP 2022030570 W JP2022030570 W JP 2022030570W WO 2024034054 A1 WO2024034054 A1 WO 2024034054A1
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WO
WIPO (PCT)
Prior art keywords
power supply
layer
jumper layer
wafer mounting
supply via
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/030570
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English (en)
French (fr)
Japanese (ja)
Inventor
博哉 杉本
征樹 石川
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NGK Insulators Ltd
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NGK Insulators Ltd
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Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=89845886&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2024034054(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to JP2023514948A priority Critical patent/JP7478905B1/ja
Priority to KR1020257019192A priority patent/KR20250088665A/ko
Priority to PCT/JP2022/030570 priority patent/WO2024034054A1/ja
Priority to KR1020237008049A priority patent/KR102821058B1/ko
Priority to CN202280006007.7A priority patent/CN119585859A/zh
Priority to US18/180,204 priority patent/US20240057223A1/en
Priority to TW112113770A priority patent/TW202407869A/zh
Publication of WO2024034054A1 publication Critical patent/WO2024034054A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B3/00—Ohmic-resistance heating
    • H05B3/20—Heating elements having extended surface area substantially in a two-dimensional [2D] plane, e.g. plate-heater
    • H05B3/22—Heating elements having extended surface area substantially in a two-dimensional [2D] plane, e.g. plate-heater non-flexible
    • H05B3/28—Heating elements having extended surface area substantially in a two-dimensional [2D] plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material
    • H05B3/283—Heating elements having extended surface area substantially in a two-dimensional [2D] plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material the insulating material being an inorganic material, e.g. ceramic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B3/00—Ohmic-resistance heating
    • H05B3/10—Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor
    • H05B3/12—Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material
    • H05B3/14—Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material the material being non-metallic
    • H05B3/141—Conductive ceramics, e.g. metal oxides, metal carbides, barium titanate, ferrites, zirconia, vitrous compounds
    • H05B3/143—Conductive ceramics, e.g. metal oxides, metal carbides, barium titanate, ferrites, zirconia, vitrous compounds applied to semiconductors, e.g. wafers heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0432—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7616—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating, a hardness or a material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2260/00—Layered product comprising an impregnated, embedded, or bonded layer wherein the layer comprises an impregnation, embedding, or binder material
    • B32B2260/02—Composition of the impregnated, bonded or embedded layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2260/00—Layered product comprising an impregnated, embedded, or bonded layer wherein the layer comprises an impregnation, embedding, or binder material
    • B32B2260/04—Impregnation, embedding, or binder material
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/34—Oxidic
    • C04B2237/343—Alumina or aluminates
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/36—Non-oxidic
    • C04B2237/366—Aluminium nitride
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/62—Forming laminates or joined articles comprising holes, channels or other types of openings
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/68—Forming laminates or joining articles wherein at least one substrate contains at least two different parts of macro-size, e.g. one ceramic substrate layer containing an embedded conductor or electrode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B2203/00—Aspects relating to Ohmic resistive heating covered by group H05B3/00
    • H05B2203/002—Heaters using a particular layout for the resistive material or resistive elements
    • H05B2203/005—Heaters using a particular layout for the resistive material or resistive elements using multiple resistive elements or resistive zones isolated from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B2203/00—Aspects relating to Ohmic resistive heating covered by group H05B3/00
    • H05B2203/013—Heaters using resistive films or coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B2203/00—Aspects relating to Ohmic resistive heating covered by group H05B3/00
    • H05B2203/016—Heaters using particular connecting means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B2203/00—Aspects relating to Ohmic resistive heating covered by group H05B3/00
    • H05B2203/017—Manufacturing methods or apparatus for heaters

Definitions

  • the present invention relates to a wafer mounting table.
  • a ceramic heater in which an inner peripheral resistance heating element and an outer peripheral resistance heating element are located on the same plane of a ceramic base.
  • one end of the outer peripheral resistance heating element is connected to a first conductive surface provided on another plane of the ceramic base and intersecting the inner peripheral resistance heating element three-dimensionally.
  • the other end of the outer resistance heating element is connected to one of the pair of outer power supply terminals through a second conductive surface that is provided on another plane of the ceramic base and intersects the inner resistance heating element.
  • a device connected to the other of a pair of outer circumferential power supply terminals is disclosed.
  • the first and second conductive surfaces are planar jumper layers.
  • connection part of the first conductive surface to which one end of the outer resistance heating element is connected and the connection part to which the outer power supply terminal is connected is short, the shortest route between both connection parts and the The current density in the vicinity increased, causing local heat generation. This point also applies to the second conductive surface. Such localized heat generation is undesirable because it adversely affects the temperature control of the wafer.
  • the present invention was made to solve these problems, and its main purpose is to suppress local heat generation in the jumper layer.
  • the wafer mounting table of the present invention includes: a ceramic base material having a wafer mounting surface; a resistance heating element embedded in the ceramic base material; a planar jumper layer provided on a layer different from the resistance heating element; an internal via connecting the jumper layer and one end of the resistive heating element; a power supply via connected to the jumper layer; Equipped with A center-to-center distance between the internal via and the power supply via in the jumper layer is 50 mm or more.
  • the center-to-center distance between the internal via and the power supply via in the jumper layer is 50 mm or more.
  • the current flows not only through the shortest route between the internal via and the power supply via, but also through relatively large curved routes on both sides of the shortest route, so it is possible to suppress the current density from increasing in the shortest route and its vicinity.
  • the center-to-center distance is relatively long, heat generation is easily dispersed.
  • the wafer mounting table described above (the wafer mounting table described in [1] above) has a shortest route between the internal via and the power supply via in the jumper layer.
  • a blocking high resistance region may be provided.
  • a high-resistance region When a high-resistance region is provided, current flows through regions other than the high-resistance region, so it is possible to prevent the current density from increasing in the shortest route between the internal via and the power supply via or in the vicinity thereof.
  • the high resistance region may be a slit provided in the jumper layer. In this case, since current cannot flow through the slit, it becomes easier to prevent the current density from increasing in the shortest route between the internal via and the power supply via and in the vicinity thereof.
  • the high-resistance region has two wires that are in contact with the outer shape of the internal via and the outer shape of the power supply via, respectively. It may be provided so as to intersect the tangent line.
  • the area surrounded by these two tangent lines is relatively easy for current to flow and generate heat, but here, a high resistance area is provided to intersect with the two tangent lines, so local heat generation is suppressed. It becomes easier to do.
  • the high resistance region is centered on one of the internal via and the power supply via. It may be an arcuate region. This allows the current to flow in a large detour while avoiding the arcuate region, making it easier to suppress local heat generation.
  • the resistance heating element may be provided for each zone of the ceramic base material
  • the jumper layer may be provided in multiple stages within the ceramic base material.
  • FIG. 3 is a plan view of the wafer mounting table 10.
  • FIG. 3 is a cross-sectional view of the cut surface of the wafer mounting table 10 when cut at the upper surface of the third ceramic layer 23 when viewed from above.
  • FIG. 3 is a cross-sectional view of the cut surface of the wafer mounting table 10 when cut at the upper surface of the second ceramic layer 22, viewed from above.
  • FIG. 3 is a cross-sectional view of the cut surface of the wafer mounting table 10 when cut at the upper surface of the first ceramic layer 21 when viewed from above.
  • a graph showing the relationship between the center-to-center distance X between power feeding parts and the surface temperature of a ceramic base material.
  • FIG. 4 is a schematic diagram of a current flowing between an internal via 42 and a power supply via 46.
  • FIG. 3 is a manufacturing process diagram of the wafer mounting table 10.
  • FIG. 4 is a plan view of an upper jumper layer 40 with a slit 40a. A plan view of the slit 40a and its surroundings. A plan view of the slit 40b and its surroundings. A plan view of the slit 40c and its surroundings.
  • FIG. 1 is a plan view of the wafer mounting table 10
  • FIG. 2 is a sectional view taken along the line AA in FIG. be.
  • up and down, left and right, and front and back may be used, but up and down, left and right, and front and back are only relative positional relationships.
  • the wafer mounting table 10 has a heater electrode 30, an upper jumper layer 40, and a lower jumper layer 50 embedded in a ceramic base material 20.
  • the ceramic base material 20 is a circular plate made of ceramic, and has a wafer mounting surface 20a on the upper surface for mounting a wafer. Examples of the ceramic include alumina and aluminum nitride.
  • the ceramic base material 20 is a multilayer structure, and in this embodiment, as shown in FIG. 2, first to fourth ceramic layers 21 to 24 are laminated from the bottom to the top.
  • the heater electrode 30 is provided on the upper surface of the third ceramic layer 23. Heater electrodes 30 are provided for each zone. The zones are obtained by dividing the circular shape of the third ceramic layer 23 in a plan view into a plurality of sectors (four in this embodiment).
  • the heater electrode 30 has a resistive heating element wired in a single stroke from the outer peripheral end 32 to the central end 34 over the entire fan-shaped zone.
  • the heater electrode 30 is made of a mixed material of metal and ceramic. Examples of the metal include Ru, W, Mo, etc., but metals having a coefficient of thermal expansion close to that of the ceramic base material 20 are preferable.
  • the ceramic the same material as the ceramic base material 20 is used. Since the heater electrode 30 is formed of such a mixed material, it is possible to prevent cracks from occurring between the heater electrode 30 and the ceramic base material 20 due to a difference in thermal expansion between the two.
  • the upper jumper layer 40 has a planar shape and is provided on the upper surface of the second ceramic layer 22.
  • the upper jumper layer 40 is formed into a fan shape corresponding to each of the four heater electrodes 30.
  • the upper jumper layer 40 is connected to the outer peripheral edge 32 of the corresponding heater electrode 30 via an electrically conductive internal via 42 .
  • the internal via 42 penetrates the third ceramic layer 23 in the vertical direction.
  • the upper end of the internal via 42 is connected to the outer peripheral edge 32 of the heater electrode 30 , and the lower end of the internal via 42 is connected to the upper jumper layer 40 .
  • the upper end of a conductive power supply via 46 is connected to the upper jumper layer 40 .
  • the power supply via 46 is formed by vertically connecting an upper columnar member 46a and a lower columnar member 46b.
  • the upper columnar member 46a passes through the second ceramic layer 22 in the vertical direction, and the lower columnar member 46b passes through the first ceramic layer 21 in the vertical direction.
  • the lower end of the power supply via 46 is exposed on the lower surface of the ceramic base material 20.
  • the internal via 42 and the power supply via 46 may be made of the same material as the heater electrode 30, for example.
  • the center-to-center distance L1 between the internal via 42 and the power supply via 46 in the upper jumper layer 40 is 50 mm or more.
  • the lower jumper layer 50 has a planar shape and is provided on the upper surface of the first ceramic layer 21.
  • the lower jumper layer 50 is formed into a fan shape corresponding to each of the four heater electrodes 30.
  • the lower jumper layer 50 is connected to the center end 34 of the corresponding heater electrode 30 via a conductive internal via 54 .
  • the internal via 54 vertically penetrates the second and third ceramic layers 22 and 23.
  • the internal via 54 connects an upper columnar member 54a and a lower columnar member 54b in the vertical direction.
  • the upper columnar member 54a passes through the third ceramic layer 23 in the vertical direction
  • the lower columnar member 54b passes through the second ceramic layer 22 in the vertical direction.
  • the upper end of the internal via 54 is connected to the center end 34 of the heater electrode 30 and the lower end of the internal via 54 is connected to the lower jumper layer 50.
  • the upper end of a conductive power supply via 56 is connected to the lower jumper layer 50 .
  • the power supply via 56 passes through the first ceramic layer 21 in the vertical direction.
  • the lower end of the power supply via 56 is exposed on the lower surface of the ceramic base material 20.
  • a cutout 58 is provided in the lower jumper layer 50 so as not to contact the power supply via 46 .
  • the internal via 54 and the power supply via 56 may be made of the same material as the heater electrode 30, for example.
  • the center-to-center distance L2 between the internal via 54 and the power supply via 56 in the lower jumper layer 50 is 50 mm or more.
  • a first power feeding part with a diameter of 1 mm and a thickness of 0.1 mm is placed at the center position on the back surface of the circular electrode, and a first power feeding part with a diameter of 1 mm and a thickness of 0.1 mm is placed at a position separated by a distance (center-to-center distance) of X mm in the radial direction from the center position.
  • a second power supply section was arranged.
  • the volume resistivity of the disk electrode was 2.5 ⁇ 10 ⁇ 5 ⁇ cm, and the volume resistivity of the first and second power feeding parts was also 2.5 ⁇ 10 ⁇ 5 ⁇ cm.
  • the center-to-center distance X between the power supply parts and the ceramic base material when direct current is passed between the first power supply part and the second power supply part was determined.
  • the currents were 10A, 15A, and 20A.
  • the results are shown in the graph of FIG. As can be seen from the graph, at any current value, the surface temperature of the ceramic base material converged and became stable when the center-to-center distance X was 50 mm or more. Based on this result, in this embodiment, the center-to-center distances L1 and L2 are set to 50 mm or more.
  • FIG. 8 is a manufacturing process diagram of the wafer mounting table 10. As shown in FIG. First, four disc-shaped ceramic green sheets GS are produced. Ceramic green sheet GS is produced by tape molding method.
  • first ceramic green sheet GS For the first ceramic green sheet GS, through holes are formed at positions corresponding to the lower columnar member 46b and the power supply via 56, and the through holes are filled with conductive paste to form paste filling portions 146b and 156 ( (see Figure 8A). Thereafter, a conductive paste is printed on the upper surface of the ceramic green sheet GS in the same pattern as the lower jumper layer 50 to form the lower jumper precursor 150, thereby obtaining the first sheet 121 (see FIG. 8B).
  • the second ceramic green sheet GS through holes are formed at positions corresponding to the upper columnar member 46a and the lower columnar member 54b, and the through holes are filled with conductive paste to form paste filling portions 146a and 154b. (See Figure 8A). Thereafter, a conductive paste is printed on the upper surface of the ceramic green sheet GS in the same pattern as the upper jumper layer 40 to form an upper jumper precursor 140, thereby obtaining a second sheet 122 (see FIG. 8B).
  • the third ceramic green sheet GS For the third ceramic green sheet GS, through holes are formed at positions corresponding to the internal vias 42 and the upper columnar member 54a, and the through holes are filled with conductive paste to form paste filled portions 142, 154a ( (see Figure 8A). Thereafter, a conductive paste is printed on the top surface of the ceramic green sheet GS in the same pattern as the heater electrode 30 to form a heater electrode precursor 130, thereby obtaining a third sheet 123 (see FIG. 8B).
  • the fourth ceramic green sheet GS is used as it is as the fourth sheet 124 (see FIG. 8A).
  • the first to fourth sheets 121 to 124 are stacked in this order from the bottom to form a laminate 110 (see FIG. 8C).
  • the wafer mounting table 10 is obtained.
  • a heater power source (not shown) is connected to each heater electrode 30. Specifically, one (positive pole) of the pair of power supply terminals of the heater power supply is connected to the power supply via 46 of the heater electrode 30, and the other (negative pole) of the pair of power supply terminals of the heater power supply is connected to the power supply via 46 of the heater electrode 30. Connect to 56. Then, a wafer is placed on the wafer placement surface 20a, and power is individually supplied to each heater electrode 30 to heat the wafer. At this time, power is supplied so that the entire wafer has the same temperature. The wafer is processed in this state.
  • the ceramic base material 20 of this embodiment corresponds to the ceramic base material of the present invention
  • the heater electrode 30 corresponds to a heater electrode.
  • the upper jumper layer 40 corresponds to a jumper layer, and the center-to-center distance L1 between the internal via 42 and the power supply via 46 in the upper jumper layer 40 is 50 mm or more.
  • the lower jumper layer 50 corresponds to a jumper layer, and the center-to-center distance L2 between the internal via 54 and the power supply via 56 in the lower jumper layer 50 is 50 mm or more.
  • the center-to-center distance L1 between the internal via 42 and the power supply via 46 in the upper jumper layer 40 is 50 mm or more. Therefore, the current flows not only through the shortest route between the internal via 42 and the power supply via 46 in the upper jumper layer 40 but also through relatively large curved routes on both sides of the shortest route. This makes it possible to prevent the current density from increasing in the shortest route and its vicinity. Furthermore, since the center-to-center distance L1 is long, heat generation is easily dispersed. This also applies to the internal vias 54 and power supply vias 56 in the lower jumper layer 50. Therefore, local heat generation in the upper jumper layer 40 and the lower jumper layer 50 can be suppressed.
  • the center-to-center distance L1 of the shortest route between the internal via 42 and the power supply via 46 in the upper jumper layer 40 is 50 mm or more, as shown in FIGS.
  • an arcuate slit 40a may be provided between the internal via 42 and the power supply via 46 in the upper jumper layer 40 to interrupt the shortest route (dotted chain line in FIG. 10) between the internal via 42 and the power supply via 46. good.
  • the center-to-center distance L1 of the shortest route is less than 50 mm (for example, 10 mm or 20 mm).
  • the slit 40a is an example of a high resistance region, and is provided so as to intersect with two tangent lines (two-dot chain lines in FIG. 10) that are in contact with the outer shape of the internal via 42 and the outer shape of the power supply via 46, respectively. Further, the slit 40a is an annular region having an arc shape (here, a semicircle shape) centered on the power supply via 46. In this case, as shown in FIG. 10, the current flows through a region other than the slit 40a (see dotted arrow). Therefore, it is possible to prevent the current density from increasing in the shortest route between the internal via 42 and the power supply via 46 or in the vicinity thereof. Therefore, local heat generation in the upper jumper layer 40 can be suppressed.
  • the slit 40a is a region that vertically penetrates the upper jumper layer 40, but instead of the slit 40a, a thin region made by thinning the upper jumper layer 40 may be provided as a high resistance region. Further, a similar high resistance region (such as a slit) may be provided between the internal via 54 and the power supply via 56 in the lower jumper layer 50 as well.
  • slits 40b and 40c shown in FIGS. 11 and 12 may be used.
  • the slit 40b in FIG. 11 is rectangular and is provided in the upper jumper layer 40 so as to block the shortest route between the internal via 42 and the power supply via 56 (dotted chain line in FIG. 11). Further, the slit 40b is provided so as to intersect with two tangent lines (two-dot chain lines in FIG. 11) that are in contact with the outer shape of the internal via 42 and the outer shape of the power feeding via 56, respectively. Even if such a slit 40b is employed, the same effect as the slit 40a can be obtained.
  • the arc-shaped slit 40a is preferable because the current is larger and can be easily detoured compared to the rectangular slit 40b.
  • the slit 40c in FIG. 12 is also rectangular and is provided in the upper jumper layer 40 so as to block the shortest route between the internal via 42 and the power supply via 56 (dotted chain line in FIG. 12).
  • the slit 40c does not intersect with two tangent lines (two-dot chain lines in FIG. 12) that are in contact with the outer shape of the internal via 42 and the outer shape of the power supply via 56, respectively.
  • the center-to-center distance L1 of the shortest route between the internal via 42 and the power supply via 46 in the upper jumper layer 40 is 50 mm or more.
  • the center-to-center distance L2 of the shortest route between the internal via 54 and the power supply via 56 in the lower jumper layer 50 is 50 mm or more.
  • the ceramic base material 20 may have an electrostatic chuck electrode built in at a position close to the wafer mounting surface 20a.
  • the electrostatic chuck electrode is connected to a DC power source.
  • the wafer placed on the wafer placement surface 20a is attracted and fixed to the wafer placement surface 20a by applying a DC voltage to the electrostatic chuck electrode.
  • the ceramic base material 20 may have a built-in RF electrode for plasma generation.
  • the wafer mounting table 10 may have a plurality of holes penetrating the wafer mounting table 10 in the vertical direction. These holes include a plurality of gas holes opened in the wafer placement surface 20a and lift pin holes through which lift pins for moving the wafer up and down with respect to the wafer placement surface 20a are inserted.
  • a seal band may be provided along the outer peripheral edge of the wafer mounting surface 20a, and a plurality of small protrusions (flat circular protrusions) may be provided in the area inside the seal band.
  • the top surface of the seal band and the top surfaces of the plurality of small protrusions are made to be on the same plane.
  • the wafer is supported by the top surface of the seal band and the top surfaces of the plurality of small protrusions.
  • the ceramic green sheet GS was used to produce the ceramic base material 20, but the present invention is not particularly limited thereto.
  • a ceramic molded body made by compacting ceramic powder may be used, a ceramic molded body produced by a mold casting method may be used, or a combination of these may be used.
  • the present invention can be used to perform various treatments on wafers.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Resistance Heating (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Surface Heating Bodies (AREA)
PCT/JP2022/030570 2022-08-10 2022-08-10 ウエハ載置台 Ceased WO2024034054A1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2023514948A JP7478905B1 (ja) 2022-08-10 2022-08-10 ウエハ載置台
KR1020257019192A KR20250088665A (ko) 2022-08-10 2022-08-10 웨이퍼 배치대
PCT/JP2022/030570 WO2024034054A1 (ja) 2022-08-10 2022-08-10 ウエハ載置台
KR1020237008049A KR102821058B1 (ko) 2022-08-10 2022-08-10 웨이퍼 배치대
CN202280006007.7A CN119585859A (zh) 2022-08-10 2022-08-10 晶片载放台
US18/180,204 US20240057223A1 (en) 2022-08-10 2023-03-08 Wafer placement table
TW112113770A TW202407869A (zh) 2022-08-10 2023-04-13 晶圓載置台

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/030570 WO2024034054A1 (ja) 2022-08-10 2022-08-10 ウエハ載置台

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/180,204 Continuation US20240057223A1 (en) 2022-08-10 2023-03-08 Wafer placement table

Publications (1)

Publication Number Publication Date
WO2024034054A1 true WO2024034054A1 (ja) 2024-02-15

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ID=89845886

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US (1) US20240057223A1 (https=)
JP (1) JP7478905B1 (https=)
KR (2) KR20250088665A (https=)
CN (1) CN119585859A (https=)
TW (1) TW202407869A (https=)
WO (1) WO2024034054A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7758122B1 (ja) 2024-09-19 2025-10-22 Toto株式会社 静電チャック

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172208A (ja) * 2006-12-15 2008-07-24 Ngk Insulators Ltd セラミックヒータ
JP2018005998A (ja) * 2016-06-27 2018-01-11 日本特殊陶業株式会社 セラミックスヒータ
JP2019220645A (ja) * 2018-06-22 2019-12-26 日本特殊陶業株式会社 保持装置
JP2020017686A (ja) * 2018-07-27 2020-01-30 日本特殊陶業株式会社 保持装置
JP2020191315A (ja) * 2019-05-20 2020-11-26 日本特殊陶業株式会社 保持装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6084906B2 (ja) 2013-07-11 2017-02-22 日本碍子株式会社 セラミックヒータ
JP2023088622A (ja) * 2021-12-15 2023-06-27 日本碍子株式会社 ウエハ載置台

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172208A (ja) * 2006-12-15 2008-07-24 Ngk Insulators Ltd セラミックヒータ
JP2018005998A (ja) * 2016-06-27 2018-01-11 日本特殊陶業株式会社 セラミックスヒータ
JP2019220645A (ja) * 2018-06-22 2019-12-26 日本特殊陶業株式会社 保持装置
JP2020017686A (ja) * 2018-07-27 2020-01-30 日本特殊陶業株式会社 保持装置
JP2020191315A (ja) * 2019-05-20 2020-11-26 日本特殊陶業株式会社 保持装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7758122B1 (ja) 2024-09-19 2025-10-22 Toto株式会社 静電チャック
JP2026056193A (ja) * 2024-09-19 2026-04-01 Toto株式会社 静電チャック

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US20240057223A1 (en) 2024-02-15
KR102821058B1 (ko) 2025-06-13
TW202407869A (zh) 2024-02-16
KR20240022435A (ko) 2024-02-20
KR20250088665A (ko) 2025-06-17
JP7478905B1 (ja) 2024-05-07
JPWO2024034054A1 (https=) 2024-02-15
CN119585859A (zh) 2025-03-07

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