WO2024032134A1 - Chip and preparation method therefor, and electronic device - Google Patents

Abstract

Some embodiments of the present application relate to the technical field of semiconductors. Provided are a chip and a preparation method therefor, and an electronic device, which aim to improve the accuracy of the resistance value of a resistor device in a chip. The chip may be a die, and may also be a packaged chip, which may comprise one or more dies. The chip comprises a high resistance layer, at least one dielectric layer arranged on the high resistance layer, a plurality of first contact columns and a plurality of second contact columns, wherein the high resistance layer comprises a first end and a second end, the first end and the second end being opposite ends of the high resistance layer in a first direction, and the first direction being parallel to an extension surface of the high resistance layer; and the plurality of first contact columns penetrate through the at least one dielectric layer to electrically connect to the first end, and the plurality of second contact columns penetrate through the at least one dielectric layer to electrically connect to the second end. The chip may be applied to an electronic device.

Description

Chip and preparation method thereof, electronic equipment

This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office on August 11, 2022, with application number 202210963680.1 and application name "Chip and Preparation Method, Electronic Equipment", the entire content of which is incorporated herein by reference. Applying.

Technical field

The present application relates to the field of semiconductor technology, and in particular to a chip and its preparation method, and electronic equipment.

Background technique

With the development of semiconductor technology, the integration level of chips in electronic devices has gradually increased, which is conducive to achieving smaller size and thinner chips.

Usually, the chip includes a resistive device, and the resistive device includes, for example, a High Resistance (HiR) layer. The chip also includes a dielectric layer covering the resistance layer, a first contact structure and a second contact structure. The first contact structure penetrates the dielectric layer and is connected to one end of the resistance layer, and the second contact structure penetrates the other end of the dielectric layer and the resistance layer. Connect one end.

However, as the size of the chip becomes smaller, the size of the resistor layer in the chip also decreases, which brings greater challenges to the interconnection between the first contact structure and the second contact structure and the resistor layer. In addition, during the process of preparing the chip, the existing process can easily cause damage to the resistor layer, resulting in poor contact between the first contact structure and the second contact structure and the resistor layer, thereby causing misalignment of the resistance value of the resistor device.

Contents of the invention

Some embodiments of the present application provide a chip, a preparation method thereof, and electronic equipment, aiming to improve the accuracy of the resistance value of the resistive device in the chip.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a chip is provided. The chip may be a bare chip or a packaged chip. The packaged chip may include one or more bare chips.

The chip includes a resistor layer, at least one dielectric layer disposed on the resistor layer, a plurality of first contact pillars and a plurality of second contact pillars. Wherein, the resistance distribution layer includes a first end and a second end, the first end and the second end are opposite ends of the resistance distribution layer along a first direction, and the first direction is parallel to the extension surface of the resistance distribution layer. A plurality of first contact pillars penetrates at least one dielectric layer and is electrically connected to the first end, and a plurality of second contact pillars penetrates at least one dielectric layer and is electrically connected to the second end.

The chip provided in the above embodiments of the present application is electrically connected to the first end of the resistance distribution layer by providing a plurality of first contact posts, and a plurality of second contact posts are electrically connected to the second end of the resistance distribution layer. Based on this, during the process of preparing the chip, it is necessary to form a plurality of first contact holes and a plurality of second contact holes in the dielectric layer. The first contact holes are used to form the first contact pillars, and the second contact holes are used to form the third contact holes. Two contact posts.

In the embodiment of the present application, the first contact post and the second contact post are both columnar, and the first contact hole and the second contact hole are hole-shaped. Compared with the long groove-shaped contact hole, the first contact hole and the second contact hole are both in the shape of a hole. The opening area of the second contact hole is reduced. In this way, during the process of etching the dielectric layer, the etching depth of the first contact hole and the second contact hole is easy to control. By controlling the etching to stop on the surface of the resistor layer, the etching depth is avoided. The volume of the resistive layer is reduced due to over-etching, thereby ensuring the accurate resistance value of the resistive layer.

In some embodiments, a plurality of first contact pillars are arranged in an array, and/or a plurality of second contact pillars are arranged in an array.

Through the above arrangement, the uniformity of the in-plane arrangement of the plurality of first contact pillars and the plurality of second contact pillars can be improved.

Furthermore, in the process of preparing the chip, the dielectric layer is etched to form a plurality of first contact holes and a plurality of second contact holes, and then a first contact pillar is formed in the first contact hole, and a third contact post is formed in the second contact hole. Two contact posts. Therefore, when the plurality of first contact pillars are arranged in an array, and the plurality of second contact pillars are arranged in an array, the plurality of first contact holes are also arranged in an array, and the plurality of second contact holes are also arranged in an array. Arranged in an array, the uniformity of the in-plane arrangement of the plurality of first contact holes and the plurality of second contact holes can be improved. In this way, during the process of etching the dielectric layer, the first contact holes and the second contact holes are The etching depth of the hole is easier to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thereby ensuring the accuracy of the resistance value of the resistor layer.

In some embodiments, the plurality of first contact pillars includes a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersecting the second direction. And/or, the plurality of second contact posts include a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, where the first direction intersects the second direction.

Through the above arrangement, the uniformity of the in-plane arrangement of the plurality of first contact pillars and the plurality of second contact pillars can be further improved. Therefore, during the process of preparing the chip, the uniformity of the in-plane arrangement of the plurality of first contact holes and the plurality of second contact holes can be further improved, so that during the process of etching the dielectric layer, the first contact holes The etching depth of the second contact hole is easier to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thereby ensuring the accuracy of the resistance value of the resistor layer.

In some embodiments, the spacing between two adjacent first contact posts along the first direction is equal to the spacing between two adjacent first contact posts along the second direction, and the first direction and the second contact post are equal to the spacing between the two adjacent first contact posts along the second direction. directions intersect. And/or, the spacing between two adjacent second contact pillars along the first direction is equal to the spacing between two adjacent second contact pillars along the second direction, and the first direction is equal to the second direction. cross.

Through the above arrangement, the uniformity of the in-plane arrangement of the plurality of first contact pillars and the plurality of second contact pillars can also be further improved. Therefore, during the process of preparing the chip, the uniformity of the in-plane arrangement of the plurality of first contact holes and the plurality of second contact holes can also be further improved, so that during the process of etching the dielectric layer, the first contact holes The etching depth of the hole and the second contact hole is easier to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thereby ensuring the accuracy of the resistance value of the resistor layer.

In some embodiments, the radial dimension of the first contact post along the first direction is a first dimension, the radial dimension of the first contact post along the second direction is a second dimension, the first dimension is equal to the second dimension, and the radial dimension of the first contact post along the second direction is a second dimension. One direction intersects the second direction. And/or, the radial dimension of the second contact post along the first direction is a third dimension, the radial dimension of the second contact post along the second direction is a fourth dimension, the third dimension is equal to the fourth dimension, and the first direction Intersect with the second direction.

Through the above arrangement, the uniformity of the plane dimensions of the first contact pillars and the second contact pillars can be improved, and it is also beneficial to improve the uniformity of the in-plane arrangement of the plurality of first contact pillars and the plurality of second contact pillars. Therefore, during the process of preparing the chip, the uniformity of the in-plane arrangement of the plurality of first contact holes and the plurality of second contact holes can be improved, so that during the process of etching the dielectric layer, the first contact holes and the plurality of second contact holes can be The etching depth of the second contact hole is easier to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thereby ensuring the accuracy of the resistance value of the resistor layer.

In some embodiments, the plurality of first contact pillars includes a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersects the second direction, and the columns of the plurality of first contact pillars The number ranges from 2 to 20, and the number of rows of the plurality of first contact pillars ranges from 1 to 20. and/or, the plurality of second contact pillars includes a plurality of columns arranged along the first direction, and a plurality of rows arranged along the second direction, the first direction intersects the second direction, the number of columns of the plurality of second contact pillars ranges from 2 to 20, and the number of rows of the plurality of second contact pillars ranges from 1 to 20.

In some embodiments, the shape of the first contact post is one of a quadrangular prism, a quadrangular frustum, a cylinder, and a truncated cone, and/or the shape of the second contact post is one of a quadrangular prism, a quadrangular frustum, a cylinder, and a circular cone. A type of round platform.

In some embodiments, at least one dielectric layer includes a stacked first dielectric layer and a second dielectric layer. The chip further includes a second conductive pattern and a third conductive pattern. The second conductive pattern is disposed on the second dielectric layer away from the resistor. On one side of the layer, one end of the plurality of first contact posts away from the resistance layer is electrically connected to the second conductive pattern to realize interconnection between the resistance layer and the second conductive pattern. The third conductive pattern is disposed on the side of the second dielectric layer away from the resistance layer. One end of the plurality of second contact pillars away from the resistance layer is electrically connected to the third conductive pattern to realize the connection between the resistance layer and the third conductive pattern. interconnected.

In some embodiments, the chip includes a resistor arrangement area and a device area, the resistor arrangement layer and the first dielectric layer are located in the resistor arrangement area, and the second dielectric layer is located in the resistor arrangement area and the device area.

The chip also includes a first conductive pattern, a third dielectric layer and a third contact pillar, wherein the first conductive pattern is located in the device area, and the third dielectric layer is disposed on the first conductive pattern and is located in the resistance distribution area and the device area. The third dielectric layer is located on a side of the second dielectric layer close to the first conductive pattern. The third contact pillar penetrates the second dielectric layer and the third dielectric layer, and one end is electrically connected to the first conductive pattern to realize interconnection between the first conductive pattern and the third contact pillar.

In some embodiments, the first contact post, the second contact post and the third contact post are made of the same material, that is, they can be prepared using the same film formation process.

In some embodiments, the chip further includes a fourth conductive pattern, the fourth conductive pattern is disposed on a side of the second dielectric layer away from the first conductive pattern, and an end of the third contact post away from the first conductive pattern is electrically connected to the fourth conductive pattern. connection to realize interconnection between the first conductive pattern and the fourth conductive pattern.

In a second aspect, a method for manufacturing a chip is provided. The preparation method includes: forming a resistor layer and at least one dielectric layer, the at least one dielectric layer is located on the resistor layer, and the resistor layer includes a first end and a second end, The first end and the second end are opposite ends of the resistance distribution layer along the first direction. A plurality of first contact holes and a plurality of second contact holes are formed in at least one dielectric layer, the plurality of first contact holes expose the first end, and the plurality of second contact holes expose the second end. A first contact post is formed in the first contact hole, and a second contact post is formed in the second contact hole. The first contact post is electrically connected to the first end, and the second contact post is electrically connected to the second end.

The preparation method provided by the above embodiments of the present application includes forming a plurality of first contact holes and a plurality of second contact holes in the dielectric layer, and then forming first contact pillars in the first contact holes, and forming first contact posts in the second contact holes. A second contact pillar is formed, the first contact pillar is electrically connected to the first end of the resistance arrangement layer, and the second contact pillar is electrically connected to the second end of the resistance arrangement layer.

In the embodiment of the present application, both the first contact hole and the second contact hole are hole-shaped. Compared with the long groove-shaped contact hole, the opening area of the first contact hole and the second contact hole is reduced. In this way, when engraving During the process of etching the dielectric layer, the etching depth of the first contact hole and the second contact hole is easy to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thereby ensuring The resistance value of the resistance distribution layer is accurate.

In some embodiments, the chip includes a resistor matching area and a device area.

Forming the resistor layer and at least one dielectric layer includes: sequentially forming a resistor film and a first dielectric film. The portion of the first dielectric film located outside the resistance arrangement area and the portion of the resistance arrangement film located outside the resistance arrangement area are removed to form a resistance arrangement layer and a first dielectric layer covering the resistance arrangement layer. A second dielectric layer is formed. The second dielectric layer is located in the resistor arrangement area and the device area, and is located on a side of the first dielectric layer away from the resistor arrangement layer.

In some embodiments, before forming the resistance layer and at least one dielectric layer, the method further includes: sequentially forming a first conductive pattern and a third dielectric layer, the first conductive pattern is located in the device area, and the third dielectric layer is located in the resistance area and the device. district.

In some embodiments, forming a plurality of first contact holes and a plurality of second contact holes includes: etching the second dielectric layer and the first dielectric layer to form a plurality of first contact holes and a plurality of second contact holes. During the process of etching the second dielectric layer and the first dielectric layer, the second dielectric layer and the third dielectric layer are also etched to form a third contact hole, and the third contact hole exposes the first conductive pattern.

In the above embodiment, the plurality of first contact holes and the plurality of second contact holes are hole-shaped, and the opening areas of the first contact holes and the second contact holes are reduced. In this way, when etching the second dielectric layer and the first contact hole, During the process of forming the dielectric layer, the etching depth of the first contact hole and the second contact hole is easy to control. By controlling the etching to stop on the surface of the resistor layer, the volume of the resistor layer is prevented from being reduced due to over-etching, thus ensuring the resistor layer. The resistance value of the resistive layer is accurate.

Moreover, during the process of etching the second dielectric layer and the first dielectric layer, the second dielectric layer and the third dielectric layer are also etched to form a third contact hole, and the third contact hole exposes the first conductive pattern.

In some embodiments, after forming the third contact hole, the method further includes: etching the first conductive pattern through the bottom of the third contact hole to form a cavity in the first conductive pattern, and the third contact hole includes the cavity and the third contact hole. The connected openings and the orthographic projection of the openings on the first conductive pattern are located within the range of the orthographic projection of the cavity on the first conductive pattern.

In the above embodiment, since the opening areas of the first contact hole and the second contact hole are reduced, during the etching process of the first conductive pattern, the etching gas or etching liquid through the first contact hole can be reduced or even avoided. The second contact hole is in contact with the resistor layer to prevent the resistor layer from being reduced in volume due to etching, thereby ensuring that the resistance value of the resistor layer is accurate.

Moreover, since the orthographic projection of the opening on the first conductive pattern is located within the range of the orthographic projection of the cavity on the first conductive pattern, the third contact hole is connected with the cavity to form a cavity with a shape similar to a "rivet". Therefore, After the third contact post is formed in the cavity, the shape of the third contact post is also similar to a "rivet". During the subsequent grinding process, if the grinding fluid penetrates along the gap between the third contact post and the side wall of the third contact hole, the third contact post will be The "nail cap" of the contact post can block the grinding liquid and prevent the grinding liquid from contacting and corroding the first conductive pattern.

In some embodiments, a selective deposition process is used to form the first contact pillar in the first contact hole, and in the process of forming the second contact pillar in the second contact hole, a third contact pillar is also formed in the third contact hole. The contact pillar and the third contact pillar are electrically connected to the first conductive pattern. No gaps will be formed in the contact pillar formed by the selective deposition process, which is beneficial to reducing the resistance of the contact pillar.

In some embodiments, after forming the first contact pillar and the second contact pillar, the method further includes: performing ion implantation on at least one dielectric layer.

In the above embodiments, ion implantation into the dielectric layer can cause the dielectric layer to expand to reduce the diameters of the first contact hole, the second contact hole and the third contact hole, thereby narrowing the gap between the corresponding holes and the contact pillars. , in the subsequent grinding process, the problem of grinding fluid seeping down through the gap between the hole and the contact structure can be improved, so as to reduce the corrosion of the first conductive pattern and the resistance layer by the grinding fluid.

Moreover, since the opening areas of the first contact hole and the second contact hole are reduced, the probability of ions entering through the gap between the holes and the contact pillars is reduced during the ion implantation process, thereby avoiding the possibility of ions being injected into the resistive layer and causing damage to the resistive layer. Causes the problem of misalignment of the resistance value of the resistance distribution layer.

In some embodiments, after forming the first contact pillar and the second contact pillar, the method further includes: sequentially forming a protective layer and a sacrificial layer, and the protective layer and the sacrificial layer cover at least one dielectric layer, the first contact pillar and the second contact pillar. Grind the portion of the sacrificial layer, the protective layer and the at least one dielectric layer away from the resistor layer to expose the first contact pillar and the second The end of the contact pillar away from the resistor layer.

In the above embodiment, a plurality of first contact pillars and a plurality of second contact pillars are provided in the resistance matching area, which is beneficial to improving the intensity uniformity of the surface of the resistance matching area, thereby improving the uniformity of surface grinding of the resistance matching area. properties, avoid "dish-shaped" damage on the tops of the first contact post and the second contact post, and ensure that the top surfaces of the first contact post and the second contact post are flat and fully exposed, so as to facilitate the connection between the first contact post and the second contact post. After the conductive pattern is formed above the pillar, it is beneficial to the stable contact between the conductive pattern and the first contact pillar and the second contact pillar.

In the third aspect, an electronic device is provided. The electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. The electronic device includes the chip described in any of the above embodiments, and a circuit board electrically connected to the chip.

It can be understood that the beneficial effects that can be achieved by the electronic device provided by the above embodiments of the present application can be referred to the beneficial effects of the chip above, and will not be described again here.

Description of drawings

In order to explain the technical solutions in the present application more clearly, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only appendices to some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of the present application.

Figure 1 is a structural diagram of an electronic device according to some embodiments;

Figure 2 is a top view of a chip in the related art;

Figure 3 is a cross-sectional view of the chip in Figure 2 along section line A-A';

Figure 4 is a top view of another chip in the related art;

Figure 5 is a cross-sectional view of the chip in Figure 4 along section line B-B';

Figure 6 is a top view of another chip in the related art;

Figure 7 is a cross-sectional view of the chip in Figure 6 along section line C-C';

Figure 8 is a cross-sectional view of the chip in Figure 6 along section line D-D';

Figures 9A to 9I are diagrams of steps for preparing the chip 10' in the related art;

Figure 10 is a top view of a chip according to some embodiments;

Figure 11 is a cross-sectional view of the chip in Figure 10 along the section line E-E';

Figure 12 is a cross-sectional view of the chip in Figure 10 along the section line F-F';

Figures 13A to 13J are diagrams of steps for preparing the above chip according to some embodiments.

Detailed ways

The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art fall within the scope of protection of this application.

In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", The orientations or positional relationships indicated by "top", "bottom", "inner", "outside", etc. are based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present application and simplifying the description, and are not indicated or implied. The device or component referred to must have a specific orientation, be in a specific orientation construction and operation, and therefore should not be construed as limitations on this application.

Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted in an open, inclusive sense, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" and the like are intended to indicate specific features associated with the embodiment or example. , structures, materials or characteristics are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, some embodiments may be described using the term "connected" to indicate that two or more components are in direct physical or electrical contact with each other.

"At least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation or other action "based on" one or more stated conditions or values may in practice be based on additional conditions or beyond the stated values.

As used herein, "parallel," "perpendicular," and "equal" include the stated situation as well as situations that are approximate to the stated situation within an acceptable deviation range, where Such acceptable deviation ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system). For example, "parallel" includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°; "perpendicular" includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.

Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

Some embodiments of the present application provide an electronic device, which is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products such as mobile phones, tablet computers, notebook computers, e-readers, personal computers, (referred to as PC), personal digital assistant (Personal Digital Assistant, referred to as PDA), desktop monitors, smart wearable products (such as smart watches, smart bracelets), virtual reality (Virtual Reality, referred to as VR) terminal equipment, augmented reality (Augmented Reality) , referred to as AR) terminal equipment, drones, etc. Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include vehicle navigation systems, vehicle-mounted high-density digital video discs, etc. Financial terminal products include automatic teller machines, self-service terminals, etc. Communication electronic products include communication equipment such as servers, memories, and base stations.

Some embodiments of the present application do not place special restrictions on the specific form of the above-mentioned electronic device. For convenience of explanation, the following embodiments take the electronic device as a mobile phone as an example.

Figure 1 is a structural diagram of an electronic device according to some embodiments.

As shown in FIG. 1 , the electronic device 1 mainly includes a cover 11 , a display 12 , a middle frame 13 and a rear case 14 . The back shell 14 and the display screen 12 are respectively located on both sides of the middle frame 13 , and the middle frame 13 and the display screen 12 are arranged in the back shell 14 . The cover plate 11 is disposed on the side of the display screen 12 away from the middle frame 13 . The display screen 12 The display surface faces the cover 11.

Among them, the display screen 12 can be a liquid crystal display (Liquid Crystal Display, LCD for short). In this case, the liquid crystal display screen includes a liquid crystal display panel and a backlight module. The liquid crystal display panel is arranged between the cover 11 and the backlight module. , the backlight module is used to provide light source for the LCD panel. The above-mentioned display screen 12 may also be an organic light emitting diode (OLED for short) display screen. Since the OLED display is a self-luminous display, there is no need to set up a backlight module.

The above-mentioned middle frame 13 includes a bearing plate 131 and a frame 132 surrounding the bearing plate 131 . The electronic device 1 also includes electronic components such as a circuit board 15 , a battery, and a camera, which are disposed on the carrier board 131 .

As shown in FIG. 1 , the above-mentioned electronic device 1 may further include a chip 10 disposed on a circuit board 15 , and the chip 10 is electrically connected to the circuit board 15 .

The above-mentioned chip 10 may include a processor chip, a memory chip, a radio frequency chip, a radio frequency power amplifier chip, a power management chip, an audio processor chip, a touch screen control chip, an image sensor chip, a charging protection chip, etc.

The chip 10 provided in some embodiments of the present application may be a bare chip or a packaged chip, and the packaged chip may include one or more bare chips. The following embodiments of the present application are described by taking the chip 10 as a two-dimensional bare chip as an example.

Figure 2 is a top view of a chip in the related art; Figure 3 is a cross-sectional view of the chip in Figure 2 along the section line A-A'.

Referring to Figures 2 and 3, the chip 10' includes a substrate 20', and a transfer layer L' and a rewiring layer 27' laminated on the substrate 20'.

The substrate 20' includes a substrate G' and an electronic component T' disposed on the substrate G'.

Illustratively, the electronic component T' may include a transistor, a capacitor, an inductor, etc. The electronic component T' in Figure 2 takes a transistor as an example. The transistor includes a gate G, a source S and a drain D.

Continuing to refer to Figures 2 and 3, the transfer layer L' includes a first dielectric layer 21' and a second dielectric layer 23' stacked on the substrate 20', a conductive pattern 22' penetrating the first dielectric layer 21', and Conductive pillars 24' penetrating the second dielectric layer 23'.

One end of the conductive pattern 22' is electrically connected to the electronic component T'. For example, the gate G, the source S and the drain D of the transistor respectively correspond to and are electrically connected to one conductive pattern 22'.

One end of the conductive pillar 24' is electrically connected to the other end of the conductive pattern 22'. The transfer layer L' also includes an adhesive layer 26' surrounding the side and bottom surfaces of the conductive pillars 24'. The adhesive layer 26' can be used to adhere the conductive pillars 24' to improve the connection between the conductive pillars 24' and the second dielectric layer 23'. the strength of the connection between them.

Continuing to refer to FIGS. 2 and 3 , the rewiring layer 27 ′ includes a plurality of conductive layers, and the lowest conductive layer among the plurality of conductive layers is electrically connected to the conductive pillar 24 ′. The uppermost conductive layer is exposed to the surface of the rewiring layer 27' and can be used to connect functional devices. For example, the uppermost conductive layer can be used as a pad to connect functional devices.

During the working process of the above-mentioned chip 10', the electrical signal in the electronic component T' can be transmitted to the conductive layer of the rewiring layer 27' through the conductive pattern 22' and the conductive pillar 24', and then the electrical signal can pass through the rewiring layer. The uppermost conductive layer in 27' is transmitted to the functional device connected to it.

In the process of preparing the above-mentioned chip 10', usually the electronic component T' is first prepared on the substrate G' to form the substrate 20', and then the first dielectric layer 21' is formed on the substrate 20', and a penetrating first dielectric layer is formed. 21′ conductive pattern 22′. After that, a second dielectric layer 23' is formed on the side of the first dielectric layer 21' away from the substrate 20', and a conductive pillar 24' is formed penetrating the second dielectric layer 23'. Finally, the second dielectric layer 23' is away from the substrate 20. 'A rewiring layer 27' is formed on one side.

In the process of forming the conductive pillars 24' penetrating the second dielectric layer 23', it is necessary to first form a via hole penetrating the second dielectric layer 23', and the via hole exposes the conductive pattern 22', and then on the side of the via hole The wall and bottom form an adhesive layer 26'. Finally, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process can be used to deposit conductive material in the via hole to form a conductive pillar 24'.

The inventor of the present application found through research that, with reference to Figures 2 and 3, during the process of depositing conductive material in the via hole, the conductive material is deposited simultaneously on the side walls and bottom of the via hole, and the connection between the side wall and the bottom The deposition rate is faster at the corners (corners). Furthermore, when the conductive material at the top of the via hole is closed, a gap 25' will be generated inside the conductive material in the via hole, so that there will be a gap 25' inside the conductive pillar 24'. , which will increase the resistance of the conductive pillar 24', causing loss of the electrical signal during transmission on the conductive pillar 24' (for example, the voltage value of the electrical signal decreases), thereby affecting the performance of the chip 10'.

Moreover, since the adhesive layer 26' has a certain thickness, it will occupy the space of the via hole, causing the diameter of the conductive pillar 24' to decrease and the radial cross-sectional area to decrease, which will also increase the resistance of the conductive pillar 24'. .

In addition, the conductive pattern 22' and the conductive pillar 24' are separated by an adhesive layer 26'. Usually, the material of the adhesive layer 26' is titanium or titanium nitride, but the conductive properties of titanium or titanium nitride are relatively poor. The difference will increase the contact resistance between the conductive pattern 22', the conductive pillar 24' and the adhesive layer 26', resulting in losses during the transmission of electrical signals from the conductive pattern 22' through the adhesive layer 26' to the conductive pillar 24', affecting Chip 10' performance.

Based on this, the related art provides another chip. Figure 4 is a top view of another chip in the related art; Figure 5 is a cross-sectional view of the chip in Figure 4 along the section line B-B'.

Referring to Figures 4 and 5, there are no gaps in the conductive pillars 24' of the chip 10', and there is no adhesive layer between the conductive pillars 24' and the conductive patterns 22', which can reduce the resistance of the conductive pillars 24' and reduce the conductive pillars. The contact resistance between 24' and the conductive pattern 22' can reduce the loss caused by the transmission of electrical signals from the conductive pattern 22' to the conductive pillar 24', which is beneficial to improving the performance of the chip 10'.

In the process of preparing the conductive pillars 24' of the above-mentioned chip 10', the contact holes H' and the conductive patterns 22' are first subjected to surface treatment to remove chemical residues and dangling bonds attached to the inner walls of the contact holes H', as well as the conductive chemical residues and dangling bonds on the surface of pattern 22′ to expose the non-metallic material on the inner wall of the contact hole H′, as well as the conductive The metal material on the surface of the electrical pattern 22′.

The above-mentioned "chemical residues" may be chemical substances remaining in the process of forming the contact hole H'; the "dangling bonds" may be, for example, chemical bonds without electrons capable of pairing.

The surface treatment method for the contact hole H' and the conductive pattern 22' may include, for example: heat treatment, plasma treatment, treatment by introducing reducing gas (such as hydrogen), and introducing oxidizing gas (such as oxygen and nitrous oxide). ) treatment, inert gas treatment, etc.

Then, a selective deposition process is used to deposit conductive material in the contact hole H'. The deposition rate of the conductive material on the surface of the metal material is greater than the deposition rate of the conductive material on the surface of the non-metal material. That is, the conductive material is deposited on the surface of the conductive pattern 22' The deposition rate is greater than the deposition rate of the conductive material on the inner wall of the contact hole H', achieving "selective deposition" of the conductive material. In this way, before the conductive material on the top of the contact hole H' is closed, the contact hole H' has been filled with the conductive material, which can avoid the occurrence of voids inside the conductive material in the contact hole H', thereby avoiding the occurrence of voids inside the conductive pillar 24'.

Usually, the chip 10' also includes a resistive device. Figure 6 is a top view of another chip in the related art; Figure 7 is a cross-sectional view of the chip in Figure 6 along the section line C-C'; Figure 8 is a cross-sectional view of the chip in Figure 6 along the section line C-C'. Sectional view of section line D-D'.

Referring to Figures 6 to 8, the chip 10' includes a resistance arrangement area A1 and a device area A2. The resistance device R' is arranged in the resistance arrangement area A1, and the electronic component T' is arranged in the device area A2.

The chip 10' includes a substrate 20', a first dielectric layer 21' disposed on the substrate 20', and a first conductive pattern 22' penetrating the first dielectric layer 21'. The substrate 20' includes a substrate G', and an electronic component T' disposed on the substrate G'. For example, the electronic component T' is a transistor, and the transistor includes a gate G, a source S and a drain D. The gate of the transistor The electrode G, the source electrode S and the drain electrode D respectively correspond to one first conductive pattern 22' and are electrically connected.

The chip 10' further includes a second dielectric layer 23', which is disposed on the side of the first dielectric layer 21' away from the substrate 20'.

Continuing to refer to Figures 6 to 8, the resistance device R' is disposed on the side of the second dielectric layer 23' away from the substrate 20', and the resistance device R' includes a resistance layer 24'. The chip 10' also includes a third dielectric layer 25' and a fourth dielectric layer 26' which are sequentially disposed on the side of the resistance layer 24' away from the substrate 20', and a third dielectric layer 25' and a fourth dielectric layer 26' that penetrate the fourth dielectric layer 26' and the third dielectric layer 25'. a contact structure 28a' and a second contact structure 28b', and a third contact structure 28c' penetrating the fourth dielectric layer 26' and the second dielectric layer 23'. Among them, the first contact structure 28a' and the second contact structure 28b' are electrically connected to both ends of the resistance layer 24' respectively to realize the interconnection of the resistance device R'. The third contact structure 28c' is columnar and is electrically connected to the first conductive pattern 22' to realize the interconnection of the electronic components T'.

The resistance distribution layer 24' has a design resistance value. When the shape of the resistance distribution layer 24' is a rectangular parallelepiped, the length, width and height of the resistance distribution layer 24' are set according to the design resistance value, thereby determining the resistance distribution layer 24'. volume.

However, referring to FIGS. 6 to 8 , both the first contact structure 28a' and the second contact structure 28b' penetrate the resistance distribution layer 24' and are electrically connected to the resistance distribution layer 24'. Equivalently, there are through holes in the resistance distribution layer 24', and the first contact structure 28a' and the second contact structure 28b' are electrically connected to the resistance distribution layer 24' at the through holes. The volume of the resistance distribution layer 24' is due to the through holes. And decreases, causing the resistance value of the resistance distribution layer 24' to be misaligned, thereby causing the resistance value of the resistance distribution layer 24' to miss match the resistance values of other resistance distribution layers in the chip 10'.

Moreover, the side surfaces of the bottoms of the first contact structure 28a' and the second contact structure 28b' are in contact with the resistance layer 24'. There are gaps between them, which will lead to poor contact between the two and the resistor layer 24', resulting in an increase in contact resistance, which will also lead to misalignment of the resistance of the resistor layer 24'.

Moreover, the tops of the first contact structure 28a' and the second contact structure 28b' are both "dish-shaped", that is, the top surfaces of the first contact structure 28a' and the second contact structure 28b' are both recessed downward. After the wires are formed above the contact structure 28a' and the second contact structure 28b', poor contact or even disconnection between the wires and the first contact structure 28a' and the second contact structure 28b' is likely to occur.

The inventor of this application has discovered through research that the problems caused by the above-mentioned chip 10' are all caused in the process of preparing the chip 10'. Next, the reasons for the above-mentioned problems will be explained based on the preparation process of the chip 10'.

Figures 9A to 9I are diagrams of steps for preparing the chip 10' in the related art. The specific preparation process of the chip 10' is as follows:

As shown in FIG. 9A, a first dielectric layer 21', a first conductive pattern 22' penetrating the first dielectric layer 21', a second dielectric layer 23', a resistive film 240' and a third resistive film 240' are sequentially formed on the substrate 20'. Dielectric film 250'.

As shown in FIG. 9B , the parts of the resistor film 240' and the third dielectric film 250' located in the device area A2 are removed by etching, while the parts of the resistor film 240' and the third dielectric film 250' located in the resistor area A1 are retained. , that is, the resistive layer 24' and the third dielectric layer 25' are obtained.

As shown in FIG. 9C, a fourth dielectric layer 26' is formed. The fourth dielectric layer 26' is located in the resistor arrangement area A1 and the device area A2, and the fourth dielectric layer 26' covers the third dielectric layer 25'.

As shown in FIG. 9D , in the resistor matching area A1 , the fourth dielectric layer 26 ′ and the third dielectric layer 25 ′ are etched to form a first contact hole H1 and a second contact hole H2 penetrating them. And in the device area A2, the fourth dielectric layer 26' and the second dielectric layer 23' are etched to form a third contact hole H3 penetrating them.

Since the first contact hole H1 and the second contact hole H2 are both in the shape of long grooves and the third contact hole H3 is a circular via hole, the opening areas of the first contact hole H1 and the second contact hole H2 are larger than those of the third contact hole H1 and the second contact hole H2. The opening area of hole H3, during the process of etching the fourth dielectric layer 26' and the third dielectric layer 25', the etching depth of the first contact hole H1 and the second contact hole H2 is difficult to control, and the resistor layer 24' is easily is penetrated by etching, thereby causing the resistance value of the resistor matching layer 24' to be misaligned.

As shown in FIG. 9E , the first conductive pattern 22 ′ is etched back through the third contact hole H3 to form a cavity in the first conductive pattern 22 ′. However, due to the large opening areas of the first contact hole H1 and the second contact hole H2, during the process of etching back the first conductive pattern 22', the etching gas or etching liquid will pass through the first contact hole H1 The second contact hole H2 is in contact with the resistor layer 24', and will etch the resistor layer 24' laterally, causing depressions on its side, and will also cause the resistance value of the resistor layer 24' to be misaligned.

As shown in FIG. 9F , conductive material is deposited in the first contact hole H1 , the second contact hole H2 and the third contact hole H3 to form the first contact structure 28 a ′, the second contact structure 28 b ′ and the third contact structure respectively. 28c＇.

As shown in Figure 9G, an ion implantation process is used to inject ions into the second dielectric layer 23', the third dielectric layer 25' and the fourth dielectric layer 26', so that the second dielectric layer 23', the third dielectric layer 25' and the fourth dielectric layer 26' expand to reduce the diameters of the first contact hole H1, the second contact hole H2 and the third contact hole H3, thereby narrowing the gap between the corresponding holes and the contact structure. In the subsequent grinding process During the process, the problem of the grinding liquid penetrating down through the gap between the hole and the contact structure can be improved, so as to reduce the corrosion of the first conductive pattern 22' and the resistance layer 24' by the grinding liquid.

However, due to the large opening areas of the first contact hole H1 and the second contact hole H2, during the ion implantation process, some ions will enter through the gap between the holes and the contact structure and be injected into the resistance layer 24' , resulting in distribution resistance The resistance value of layer 24' is misaligned.

As shown in Figure 9H, a protective layer 29' and a sacrificial layer 30' are formed in sequence. The protective layer 29' and the sacrificial layer 30' cover the fourth dielectric layer 26', the first contact structure 28a', the second contact structure 28b' and the third contact structure 28a'. Three-contact structure 28c'.

As shown in FIG. 9H and FIG. 9I , the portions of the sacrificial layer 30 ′, the protective layer 29 ′ and the fourth dielectric layer 26 ′ away from the substrate 20 ′ are polished to expose the first contact structure 28 a ′ and the second contact structure 28 b ' and the end of the third contact structure 28c' away from the substrate 20'.

However, in the resistance matching area A1, since the first contact structure 28a' and the second contact structure 28b' are provided on both sides of this area, and the first contact structure 28a' and the second contact structure 28b' are made of metal materials , the fourth dielectric layer 26' is made of non-metallic material, and the material strength of the two materials is different, so that the strength of the surface of the resistance region A1 is inconsistent, thereby causing the first contact structure 28a' and the second contact structure 28b' The polishing rate is greater than the polishing rate of the fourth dielectric layer 26', and "dish-shaped" damage occurs on the tops of the first contact structure 28a' and the second contact structure 28b', that is, the first contact structure 28a' and the second contact structure 28b 'The top surfaces are all concave downwards.

In order to solve the above problems, some embodiments of the present application also provide a chip and a preparation method thereof. Figure 10 is a top view of the chip according to some embodiments; Figure 11 is a cross-sectional view of the chip in Figure 10 along the section line E-E' ; Figure 12 is a cross-sectional view of the chip in Figure 10 along the section line F-F'.

Referring to Figures 10 to 12, the chip 10 includes a resistance distribution layer 24. The resistance distribution layer 24 includes a first end 24a and a second end 24b. The first end 24a and the second end 24b are the resistance distribution layer 24 along the first direction X. the opposite ends of.

The above-mentioned first direction X is parallel to the extension surface of the resistance distribution layer 24 . For example, the first direction

For example, the length of the resistance layer 24 ranges from 0.36 μm to 25 μm, the width ranges from 0.2 μm to 1.8 μm, and the thickness ranges from 0.03 μm to 0.07 μm.

The chip 10 further includes at least one dielectric layer disposed on the resistance layer 24. For example, the at least one dielectric layer includes a first dielectric layer 25 and a second dielectric layer 26 that are stacked.

The chip 10 also includes a plurality of first contact posts 28a and a plurality of second contact posts 28b. The plurality of first contact posts 28a penetrate through at least one dielectric layer and are electrically connected to the first end 24a of the resistance layer 24. The plurality of second contacts The pillar 28b penetrates at least one dielectric layer and is electrically connected to the second end 24b of the resistance layer 24.

The chip 10 provided in the above embodiment of the present application uses a plurality of columnar first contact pillars 28a to be electrically connected to the first end 24a of the resistance distribution layer 24, and a plurality of columnar second contact pillars 28b to be electrically connected to the resistance distribution layer 24. The second end 24b is electrically connected. Based on this, during the process of preparing the chip 10, it is necessary to form a plurality of first contact holes and a plurality of second contact holes in the dielectric layer. The first contact holes are used to form the first contact pillars 28a, and the second contact holes are used to form the first contact posts 28a. Second contact pillars 28b are formed.

In the embodiment of the present application, the first contact post 28a and the second contact post 28b are both columnar, and the first contact hole and the second contact hole are both hole-shaped. Compared with the long groove-shaped contact hole, the first contact hole and the opening area of the second contact hole is reduced. In this way, during the process of etching the dielectric layer, the etching depth of the first contact hole and the second contact hole is easy to control. By controlling the etching to stop at the surface of the resistor layer 24 , to prevent the resistance distribution layer 24 from being reduced in volume due to over-etching, thereby ensuring that the resistance value of the resistance distribution layer 24 is accurate.

Referring to FIGS. 10 to 12 , neither the first contact pillar 28 a nor the second contact pillar 28 b penetrates the resistance layer 24 . The volume loss of the resistance layer 24 is smaller, making the resistance more stable and improving the resistance layer 24 . The resistance value mismatches with the resistance values of other resistance matching layers in the chip 10 .

Moreover, there is a gap between each first contact pillar 28a and the resistance layer 24, and between each second contact pillar 28b and the resistance layer 24. 24 are in good contact without gaps, which can reduce the contact resistance between the contact pillars and the resistor layer 24 , and can also improve the resistance mismatch between the resistance layer 24 and other resistor layers in the chip 10 .

In addition, the top surfaces of the first contact pillars 28a and the second contact pillars 28b are flat and completely exposed. After the conductive patterns are subsequently formed above the first contact pillars 28a and the second contact pillars 28b, it is beneficial for the conductive patterns to connect with the first contact pillars. 28a and the second contact post 28b.

In some embodiments, as shown in FIG. 10 , a plurality of first contact pillars 28a are arranged in an array. Alternatively, a plurality of second contact pillars 28b are arranged in an array. Alternatively, the plurality of first contact pillars 28a and the plurality of second contact pillars 28b are arranged in an array.

Exemplarily, the plurality of first contact pillars 28a include a plurality of columns arranged along the first direction X, and a plurality of rows arranged along the second direction Y.

Exemplarily, the number of columns of the plurality of first contact posts 28a ranges from 2 to 20, and the number of rows ranges from 1 to 20. For example, the number of columns of the plurality of first contact posts 28a is 2, and the number of rows is 1; or, The number of columns of the plurality of first contact posts 28a is 6, and the number of rows is 2; or, the number of columns of the plurality of first contact posts 28a is 20, and the number of rows is 20.

Exemplarily, the plurality of second contact pillars 28b include a plurality of columns arranged along the first direction X, and a plurality of rows arranged along the second direction Y.

Exemplarily, the number of columns of the plurality of second contact posts 28b ranges from 2 to 20, and the number of rows ranges from 1 to 20. For example, the number of columns of the plurality of second contact posts 28b is 2, and the number of rows is 1; or, The number of columns of the plurality of second contact posts 28b is 6, and the number of rows is 2; or, the number of columns of the plurality of second contact posts 28b is 20, and the number of rows is 20.

Exemplarily, the plurality of first contact pillars 28a includes a plurality of columns arranged along the first direction Multiple columns, and multiple rows arranged along the second direction Y.

The above-mentioned first direction X intersects with the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

Through the above arrangement, the uniformity of the arrangement of the plurality of first contact pillars 28a and the plurality of second contact pillars 28b in the X-Y plane can be improved.

In some embodiments, as shown in FIG. 10 , the distance D1 between two adjacent first contact posts 28a along the first direction X is the same as the distance D1 between two adjacent first contact posts 28a along the second direction Y. The distance D2 between them is equal.

Alternatively, the distance D3 between two adjacent second contact posts 28b along the first direction X is equal to the distance D4 between two adjacent second contact posts 28b along the second direction Y.

Alternatively, the distance D1 between two adjacent first contact posts 28a along the first direction X is equal to the distance D2 between two adjacent first contact posts 28a along the second direction Y. Furthermore, the distance D3 between two adjacent second contact posts 28b along the first direction X is equal to the distance D4 between two adjacent second contact posts 28b along the second direction Y.

Through the above arrangement, the uniformity of the arrangement of the plurality of first contact pillars 28a and the plurality of second contact pillars 28b in the X-Y plane can be further improved.

In some embodiments, as shown in FIG. 10 , the radial dimension of the first contact post 28a along the first direction X is a first dimension, and the radial dimension of the first contact post 28a along the second direction Y is a second dimension, And the first size and the second size are equal.

Alternatively, the radial dimension of the second contact post 28b along the first direction X is a third dimension, the radial dimension of the second contact post 28b along the second direction Y is a fourth dimension, and the third dimension is equal to the fourth dimension.

Alternatively, the first size of the first contact post 28a is equal to the second size, and the third size of the second contact post 28b is equal to the fourth size.

It can be understood that the shape of the first contact post 28a may be one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone. Alternatively, the shape of the second contact post 28b may be one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone. Alternatively, the shape of the first contact post 28a may be one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone, and the shape of the second contact post 28b may be one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone. kind of.

Through the above arrangement, the uniformity of the size of the first contact pillars 28a and the second contact pillars 28b along the X-Y plane can be improved, and it is also conducive to improving the arrangement of the plurality of first contact pillars 28a and the plurality of second contact pillars 28b in the X-Y plane. uniformity of cloth.

In some embodiments, as shown in FIGS. 11 and 12 , the chip 10 further includes a second conductive pattern P1 and a third conductive pattern P2. The second conductive pattern P1 is disposed on a side of the second dielectric layer 26 away from the resistance layer 24 . On the other side, one end of the plurality of first contact posts 28a away from the resistance layer 24 is electrically connected to the second conductive pattern P1 to realize interconnection between the resistance layer 24 and the second conductive pattern P1.

The third conductive pattern P2 is disposed on the side of the second dielectric layer 26 away from the resistance arrangement layer 24. One end of the plurality of second contact pillars 28b away from the resistance arrangement layer 24 is electrically connected to the third conductive pattern P2 to realize the resistance arrangement layer. 24 and the interconnection with the third conductive pattern P2.

In some embodiments, as shown in FIG. 11 , the chip 10 includes a resistance matching area A1 and a device area A2. The resistance matching layer 24 and the first dielectric layer 25 are located in the resistance matching area A1, and the second dielectric layer 26 is located in the resistance matching area A1. and device area A2.

The chip 10 further includes a substrate 20 , a dielectric layer 21 disposed on the substrate 20 , a first conductive pattern 22 penetrating the dielectric layer 21 , and a third dielectric layer 23 disposed on the first conductive pattern 22 .

The substrate 20 includes a substrate G, and an electronic component T disposed on the substrate G. For example, the electronic component T is a transistor, and the transistor includes a gate G, a source S, and a drain D. The gate G, The source electrode S and the drain electrode D respectively correspond to one first conductive pattern 22 and are electrically connected.

The above-mentioned electronic component T and the first conductive pattern 22 are both located in the device area A2, the third dielectric layer 23 is located in the resistance arrangement area A1 and the device area A2, and the third dielectric layer 23 is located in the second dielectric layer 26 close to the first conductive pattern 22. one side. The chip 10 further includes a third contact pillar 28c. The third contact pillar 28c penetrates the second dielectric layer 26 and the third dielectric layer 23, and has one end electrically connected to the first conductive pattern 22.

Exemplarily, as shown in FIG. 11 , the chip 10 further includes a fourth conductive pattern P3. The fourth conductive pattern P3 is disposed on a side of the second dielectric layer 26 away from the first conductive pattern 22, and the third contact post 28c is away from the first conductive pattern 22. One end of a conductive pattern 22 is electrically connected to the fourth conductive pattern P3 to realize interconnection between the electronic component T and the fourth conductive pattern P3.

In some embodiments, the first contact post 28a, the second contact post 28b, and the third contact post 28c are made of the same material.

It can be understood that the first contact pillar 28a, the second contact pillar 28b and the third contact pillar 28c are made of the same material and are arranged in the same layer.

The above-mentioned "same layer" refers to a layer structure formed by using the same film-forming process to prepare film layers for forming a specific pattern, and then using the same mask to form a patterning process. Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.

The structural design improvement of the chip 10 provided in the above embodiments of the present application also benefits from its manufacturing process. Next, by introducing the manufacturing process of the chip 10, we will describe in detail how the above structure is prepared and formed.

Figures 13A to 13J are diagrams of steps for preparing the above chip according to some embodiments.

As shown in FIG. 13A , a dielectric layer 21 , a first conductive pattern 22 penetrating the dielectric layer 21 , a third dielectric layer 23 , a resistive film 240 and a first dielectric film 250 are sequentially formed on the substrate 20 .

Exemplarily, the material of the first conductive pattern 22 may include cobalt.

As shown in FIG. 13B, the resistor layer 24 and the first dielectric layer 25 are formed.

Illustratively, with reference to FIG. 13A and FIG. 13B , the portion of the first dielectric film 250 located outside the resistor arrangement area A1 and the portion of the resistor arrangement film 240 located outside the resistor arrangement area A1 are removed to form the resistor arrangement layer 24 and the covering resistor arrangement layer. 24 of the first dielectric layer 25 .

For example, photoresist can be used to cover the portion of the first dielectric film 250 located in the resistor configuration area A1, and the photoresist is used as a mask to etch the first dielectric film 250 and the resistor configuration film 240 to remove the first dielectric film 250 located in the resistor configuration area A1. The portion outside the resistance matching area A1, and the portion of the resistance matching film 240 located outside the resistance matching area A1.

As shown in FIG. 13C , a second dielectric layer 26 is formed. The second dielectric layer 26 is located in the resistor arrangement area A1 and the device area A2 and is located on the side of the first dielectric layer 25 away from the resistor arrangement layer 24 .

Since the resistance matching area A1 is provided with the resistance matching layer 24 and the first dielectric layer 25, the surface of the resistance matching area A1 is higher than the surface of the device area A2, so that the surface of the second dielectric layer 26 located in the resistance matching area A1 is higher. on its surface located in device area A2.

As shown in FIG. 13D , a plurality of first contact holes H1 and a plurality of second contact holes H2 are formed in the second dielectric layer 26 and the first dielectric layer 25 . The plurality of first contact holes H1 expose the third portion of the resistor layer 24 . On one end 24a, a plurality of second contact holes H2 expose the second end 24b of the resistive layer 24.

For example, the second dielectric layer 26 and the first dielectric layer 25 are etched to form a plurality of first contact holes H1 and a plurality of second contact holes H2.

Compared with the related art, the first contact holes H1 and the second contact holes H2 are both in the shape of long grooves. In the above embodiments of the present application, the plurality of first contact holes H1 and the plurality of second contact holes H2 are all in the shape of long grooves. hole shape, the opening areas of the first contact hole H1 and the second contact hole H2 are reduced, so that during the process of etching the second dielectric layer 26 and the first dielectric layer 25, the first contact hole H1 and the second contact hole The etching depth of H2 is easy to control. By controlling the etching to stop on the surface of the resistor layer 24, the volume of the resistor layer 24 is prevented from being reduced due to over-etching, thereby ensuring the accuracy of the resistance value of the resistor layer 24.

Moreover, according to the foregoing, the plurality of first contact pillars 28a are arranged in an array, and the plurality of second contact pillars 28b are arranged in an array. Since the first contact holes H1 are used to form the first contact pillars 28a, the second contact pillars 28a are arranged in an array. The contact holes H2 are used to form the second contact pillars 28b. Therefore, the plurality of first contact holes H1 are also arranged in an array, and the plurality of second contact holes H2 are also arranged in an array, which can improve the efficiency of the multiple first contact holes. H1 and the plurality of second contact holes H2 are arranged uniformly on the X-Y plane. In this way, during the process of etching the second dielectric layer 26 and the first dielectric layer 25, the first contact hole H1 and the second contact hole H2 are The etching depth is easier to control.

In addition, during the process of etching the second dielectric layer 26 and the first dielectric layer 25, the second dielectric layer 26 and the third dielectric layer 23 are also etched to form a third contact hole H3, which exposes the third contact hole H3. A conductive pattern 22.

As shown in FIG. 13E , the first conductive pattern 22 is etched through the bottom of the third contact hole H3 to form a cavity K in the first conductive pattern 22 . The third contact hole H3 includes an opening connected to the cavity K, and the orthographic projection of the opening on the first conductive pattern 22 is located within the range of the orthographic projection of the cavity K on the first conductive pattern 22 .

The above-mentioned third contact hole H3 is connected with the cavity K, forming a cavity similar in shape to a “rivet”.

In the above embodiments of the present application, since the opening areas of the first contact hole H1 and the second contact hole H2 are reduced, during the etching process of the first conductive pattern 22, the etching gas or etching gas can be reduced or even avoided. The liquid contacts the resistance matching layer 24 through the first contact hole H1 and the second contact hole H2 to prevent the resistance matching layer 24 from being reduced in volume due to etching, thereby ensuring the accuracy of the resistance value of the resistance matching layer 24 .

As shown in FIG. 13F , a first contact post 28a is formed in the first contact hole H1, and a second contact post 28b is formed in the second contact hole H2. The first contact post 28a is connected to the first end 24a of the resistance layer 24. Electrically connected, the second contact post 28b is electrically connected to the second end 24b of the resistance distribution layer 24.

Illustratively, a selective deposition process is used to form the first contact post 28a in the first contact hole H1, and in the process of forming the second contact post 28b in the second contact hole H2, the first contact post 28a is also formed in the third contact hole H3. The third contact pillar 28c is formed, and the third contact pillar 28c is electrically connected to the first conductive pattern 22, and no void is formed in the contact pillar formed by the selective deposition process, which is beneficial to reducing the resistance of the contact pillar.

It can be understood that, according to the foregoing description, the third contact hole H3 is connected with the cavity K to form a cavity with a shape similar to a “rivet”. Therefore, the shape of the third contact post 28c is also similar to a “rivet”.

In the above embodiment of the present application, the first contact pillar 28a and the second contact pillar 28b do not penetrate the resistance matching layer 24, so that the volume loss of the resistance matching layer 24 is smaller, making the resistance value more stable, and improving the resistance matching layer 24. The resistance value of the chip 10 does not match the resistance value of other resistance layers in the chip 10 .

Moreover, there is good contact between the first contact pillar 28a and the resistor layer 24, and between the second contact pillar 28b and the resistor layer 24, without gaps, which can reduce the contact resistance between the contact pillar and the resistor layer 24, and can also improve the contact resistance. The resistance value of the resistance distribution layer 24 does not match the resistance values of other resistance distribution layers in the chip 10 .

As shown in FIG. 13G, ion implantation is performed on the third dielectric layer 23, the first dielectric layer 25 and the second dielectric layer 26, for example, germanium ions are implanted to make the third dielectric layer 23, the first dielectric layer 25 and the second dielectric layer The layer 26 expands to reduce the diameters of the first contact hole H1, the second contact hole H2 and the third contact hole H3, thereby narrowing the gaps between the corresponding holes and the contact pillars, which can improve the performance during the subsequent grinding process. The problem of the grinding liquid seeping down through the gap between the hole and the contact structure can reduce the corrosion of the first conductive pattern 22 and the resistance layer 24 by the grinding liquid.

Moreover, since the opening areas of the first contact hole H1 and the second contact hole H2 are reduced, during the ion implantation process, the probability of ions entering through the gap between the holes and the contact pillars is reduced, thereby avoiding the ion implantation resistance. layer 24, causing the problem of misalignment of the resistance value of the resistance distribution layer 24.

As shown in FIG. 13H, a protective layer 29 and a sacrificial layer 30 are formed in sequence, and the protective layer 29 and the sacrificial layer 30 cover the second dielectric layer 26, the first contact pillar 28a, the second contact pillar 28b and the third contact pillar 28c.

As shown in Figure 13H and Figure 13I, a chemical mechanical polishing (CMP) process can be used to polish the portion of the sacrificial layer 30, the protective layer 29 and the second dielectric layer 26 on the side away from the resistor layer 24, so as to The ends of the first contact pillar 28 a and the second contact pillar 28 b away from the resistance layer 24 are exposed, and the end of the third contact pillar 28 c away from the first conductive pattern 22 is exposed.

As shown in FIG. 13J, a second conductive pattern P1, a third conductive pattern P2 and a fourth conductive pattern P3 are formed on the side of the second dielectric layer 26 away from the resistance layer 24. The second conductive pattern P1 is connected with a plurality of first contacts. The ends of the pillars 28a away from the resistance distribution layer 24 are electrically connected, the third conductive pattern P2 is electrically connected to the ends of the plurality of second contact pillars 28b away from the resistance distribution layer 24, and the fourth conductive pattern P3 is electrically connected to the third contact pillars 28c. The ends away from the first conductive pattern 22 are electrically connected.

In the above embodiment of the present application, a plurality of first contact posts 28a and a plurality of second contacts are provided in the resistance matching area A1. The contact pillar 28b is conducive to improving the intensity uniformity throughout the surface of the resistance matching area A1, thereby improving the uniformity of surface grinding of the resistance matching area A1, and avoiding "disking" on the tops of the first contact pillar 28a and the second contact pillar 28b. "shaped" damage to ensure that the top surfaces of the first contact pillar 28a and the second contact pillar 28b are flat and completely exposed, so that after the conductive pattern is formed above the first contact pillar 28a and the second contact pillar 28b, it is conducive to the conductive pattern and Stable contact between the first contact post 28a and the second contact post 28b.

Moreover, since the shape of the third contact post 28c is similar to a "rivet", during the grinding process, if the grinding fluid penetrates along the gap between the third contact post 28c and the side wall of the third contact hole H3, the "rivet" of the third contact post 28c will The “cap” can block the polishing liquid to prevent the polishing liquid from contacting and corroding the first conductive pattern 22 .

The chip 10 and its preparation method provided by some embodiments of the present application use a plurality of columnar first contact pillars 28a to be electrically connected to the first end 24a of the resistance distribution layer 24, and a plurality of columnar second contact pillars 28b to be electrically connected to the resistance distribution layer 24. The second end 24b of the resistive layer 24 is electrically connected. Based on this, during the process of preparing the chip 10, it is necessary to form a plurality of first contact holes and a plurality of second contact holes in the dielectric layer. The first contact holes are used to form the first contact pillars 28a, and the second contact holes are used to form the first contact posts 28a. Second contact pillars 28b are formed.

In the embodiment of the present application, both the first contact hole and the second contact hole are hole-shaped. Compared with the long groove-shaped contact hole, the opening area of the first contact hole and the second contact hole is reduced. In this way, when engraving During the process of etching the dielectric layer, the etching depth of the first contact hole and the second contact hole is easy to control. By controlling the etching to stop on the surface of the resistor layer 24, the volume of the resistor layer 24 is prevented from being reduced due to over-etching. This ensures that the resistance value of the resistance distribution layer 24 is accurate.

The electronic device 1 provided in some embodiments of the present application includes the chip 10 provided in any of the above embodiments. The beneficial effects it can achieve can be referred to the beneficial effects of the chip 10 mentioned above, which will not be described again here.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that come to mind within the technical scope disclosed in the present application by any person familiar with the technical field should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (20)

1. A chip is characterized by including:

   The resistance distribution layer includes a first end and a second end; the first end and the second end are opposite ends of the resistance distribution layer along a first direction, and the first direction is parallel to the distribution resistance layer. The extended surface of the resistive layer;

   At least one dielectric layer is provided on the resistance layer;

   A plurality of first contact pillars and a plurality of second contact pillars. The plurality of first contact pillars penetrate the at least one dielectric layer and are electrically connected to the first end. The plurality of second contact pillars penetrate the at least one dielectric layer. A dielectric layer is electrically connected to the second end.
2. The chip according to claim 1, characterized in that:

   The plurality of first contact pillars are arranged in an array; and/or,

   The plurality of second contact pillars are arranged in an array.
3. The chip according to claim 2, characterized in that:

   The plurality of first contact pillars includes a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; and/or,

   The plurality of second contact pillars include a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersecting the second direction.
4. The chip according to claim 2 or 3, characterized in that the distance between two adjacent first contact pillars along the first direction is different from the distance between two adjacent first contact pillars along the second direction. The spacing is equal; the first direction intersects the second direction; and/or,

   The distance between two adjacent second contact pillars along the first direction is equal to the distance between two adjacent second contact pillars along the second direction; the first direction is opposite to the second direction. cross.
5. The chip according to any one of claims 1 to 4, characterized in that:

   The radial dimension of the first contact post along the first direction is a first dimension, the radial dimension of the first contact post along the second direction is a second dimension, and the first dimension is equal to the second dimension. ;The first direction intersects the second direction; and/or,

   The radial dimension of the second contact post along the first direction is a third dimension, the radial dimension of the second contact post along the second direction is a fourth dimension, and the third dimension is equal to the fourth dimension. ; The first direction intersects the second direction.
6. The chip according to any one of claims 1 to 5, characterized in that:

   The plurality of first contact pillars include a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; the plurality of first contact pillars The number of columns ranges from 2 to 20, and the number of rows of the plurality of first contact posts ranges from 1 to 20; and/or,

   The plurality of second contact posts include a plurality of columns arranged along a first direction, and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; the plurality of second contact posts The number of columns ranges from 2 to 20, and the number of rows of the plurality of second contact posts ranges from 1 to 20.
7. The chip according to any one of claims 1 to 6, characterized in that:

   The shape of the first contact post is one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone; and/or,

   The shape of the second contact post is one of a quadrangular prism, a quadrangular cone, a cylinder, and a truncated cone.
8. The chip according to any one of claims 1 to 7, characterized in that at least one dielectric layer includes a first dielectric layer and a second dielectric layer arranged in a stack;

   The chip also includes a second conductive pattern and a third conductive pattern. The second conductive pattern is disposed on a side of the second dielectric layer away from the resistance layer. The plurality of first contact pillars are on a side away from the resistance layer. One end of the resistance distribution layer is electrically connected to the second conductive pattern;

   The third conductive pattern is disposed on a side of the second dielectric layer away from the resistance layer, and one end of the plurality of second contact posts away from the resistance layer is electrically connected to the third conductive pattern. .
9. The chip according to claim 8, characterized in that, the chip includes a resistor matching area and a device area, the resistor matching layer and the first dielectric layer are located in the resistor matching area, and the second dielectric layer is located in the resistance matching area and the device area;

   The chip also includes:

   A first conductive pattern located in the device area;

   A third dielectric layer is disposed on the first conductive pattern and is located in the resistance distribution area and the device area; the third dielectric layer is located in a portion of the second dielectric layer close to the first conductive pattern. side;

   A third contact pillar penetrates the second dielectric layer and the third dielectric layer, and has one end electrically connected to the first conductive pattern.
10. The chip according to claim 9, wherein the first contact pillar, the second contact pillar and the third contact pillar are made of the same material.
11. The chip according to claim 9 or 10, further comprising:

    A fourth conductive pattern is provided on a side of the second dielectric layer away from the first conductive pattern; an end of the third contact post away from the first conductive pattern is electrically connected to the fourth conductive pattern.
12. A method for preparing a chip, which is characterized by including:

    A resistance matching layer and at least one dielectric layer are formed, and the at least one dielectric layer is located on the resistance matching layer; the resistance matching layer includes a first end and a second end, and the first end and the second end are , the opposite ends of the resistance distribution layer along the first direction;

    A plurality of first contact holes and a plurality of second contact holes are formed in the at least one dielectric layer, the plurality of first contact holes expose the first end, and the plurality of second contact holes expose the first end. two ends;

    A first contact post is formed in the first contact hole, and a second contact post is formed in the second contact hole; the first contact post is electrically connected to the first end, and the second contact post is electrically connected to the second end.
13. The preparation method according to claim 12, characterized in that the chip includes a resistor matching area and a device area;

    The forming of the resistor layer and at least one dielectric layer includes:

    Form a resistive film and a first dielectric film in sequence;

    Remove the part of the first dielectric film located outside the resistor matching area and the part of the resistor matched film located outside the resistor matched area to form the resistor matched layer and the first dielectric covering the resistor matched layer layer;

    A second dielectric layer is formed, the second dielectric layer is located in the resistor arrangement area and the device area, and is located on a side of the first dielectric layer away from the resistor arrangement layer.
14. The preparation method according to claim 12 or 13, characterized in that before forming the resistance layer and at least one dielectric layer, it further includes:

    A first conductive pattern and a third dielectric layer are formed in sequence, the first conductive pattern is located in the device area, and the third dielectric layer is located in the resistance matching area and the device area.
15. The preparation method according to claim 14, wherein forming a plurality of first contact holes and a plurality of second contact holes includes:

    Etching the second dielectric layer and the first dielectric layer to form a plurality of first contact holes and a plurality of second contact holes;

    During the process of etching the second dielectric layer and the first dielectric layer, the second dielectric layer and the third dielectric layer are also etched to form a third contact hole; the third contact hole is exposed the first conductive pattern.
16. The preparation method according to claim 15, characterized in that after forming the third contact hole, it further includes:

    The first conductive pattern is etched through the bottom of the third contact hole to form a cavity in the first conductive pattern; the third contact hole includes an opening connected to the cavity, the The orthographic projection of the opening on the first conductive pattern is located within the range of the orthographic projection of the cavity on the first conductive pattern.
17. The preparation method according to claim 15 or 16, characterized in that a selective deposition process is used to form a first contact pillar in the first contact hole, and a second contact pillar is formed in the second contact hole. In the process, a third contact post is also formed in the third contact hole;

    The third contact pillar is electrically connected to the first conductive pattern.
18. The preparation method according to any one of claims 12 to 17, characterized in that after forming the first contact pillar and the second contact pillar, it further includes:

    Ion implantation is performed on the at least one dielectric layer.
19. The preparation method according to any one of claims 12 to 18, characterized in that after forming the first contact pillar and the second contact pillar, it further includes:

    Forming a protective layer and a sacrificial layer in sequence, the protective layer and the sacrificial layer covering the at least one dielectric layer, the first contact pillar and the second contact pillar;

    Grind the portions of the sacrificial layer, the protective layer and the at least one dielectric layer away from the resistor layer to expose the first contact pillar and the second contact pillar away from the resistor layer. the end of the layer.
20. An electronic device, characterized by including:

    The chip according to any one of claims 1 to 11;

    A circuit board is electrically connected to the chip.