CN117637711A

CN117637711A - Chip, preparation method thereof and electronic equipment

Info

Publication number: CN117637711A
Application number: CN202210963680.1A
Authority: CN
Inventors: 王艺潼; 马野; 史志界
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2024-03-01
Also published as: WO2024032134A1

Abstract

Some embodiments of the application provide a chip, a preparation method thereof and electronic equipment, which relate to the technical field of semiconductors and aim to improve the accuracy of the resistance value of a resistor device in the chip. The chip may be a bare chip or a packaged chip, and the packaged chip may include one or more bare chips. The chip comprises a resistance matching layer, at least one dielectric layer arranged on the resistance matching layer, a plurality of first contact posts and a plurality of second contact posts. The first end and the second end are opposite ends of the resistance matching layer along a first direction, and the first direction is parallel to an extension surface of the resistance matching layer. A plurality of first contact pillars penetrate through the at least one dielectric layer and are electrically connected with the first end, and a plurality of second contact pillars penetrate through the at least one dielectric layer and are electrically connected with the second end. The chip can be applied to electronic equipment.

Description

Chip, preparation method thereof and electronic equipment

Technical Field

The application relates to the technical field of semiconductors, in particular to a chip, a preparation method thereof and electronic equipment.

Background

With the development of semiconductor technology, the integration level of chips in electronic devices is gradually improved, which is beneficial to realizing the miniaturization and the thinness of the chips.

Typically, a chip includes a resistor device, which includes, for example, a High Resistance (or "High") layer. The chip also comprises a dielectric layer covering the resistance matching layer, a first contact structure and a second contact structure, wherein the first contact structure penetrates through the dielectric layer to be connected with one end of the resistance matching layer, and the second contact structure penetrates through the dielectric layer to be connected with the other end of the resistance matching layer.

However, as the chip is miniaturized, the size of the matching layer in the chip is reduced, which brings a great challenge to interconnection between the first contact structure and the second contact structure and the matching layer, and in the process of manufacturing the chip, the existing process is easy to cause damage to the matching layer, so that poor contact between the first contact structure and the second contact structure and the matching layer is caused, and further, the resistance value of the resistor device is misaligned.

Disclosure of Invention

Some embodiments of the application provide a chip, a preparation method thereof and electronic equipment, and aims to improve the accuracy of the resistance value of a resistor device in the chip.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, a chip is provided, which may be a bare chip or a packaged chip, where the packaged chip may include one or more bare chips.

The chip comprises a resistance matching layer, at least one dielectric layer arranged on the resistance matching layer, a plurality of first contact posts and a plurality of second contact posts. The first end and the second end are opposite ends of the resistance matching layer along a first direction, and the first direction is parallel to an extension surface of the resistance matching layer. A plurality of first contact pillars penetrate through the at least one dielectric layer and are electrically connected with the first end, and a plurality of second contact pillars penetrate through the at least one dielectric layer and are electrically connected with the second end.

The chip provided by the embodiment of the application is electrically connected with the first end of the resistance matching layer through the plurality of first contact posts, and the plurality of second contact posts are electrically connected with the second end of the resistance matching layer. Based on this, in the process of manufacturing the chip, a plurality of first contact holes for forming the first contact pillars and a plurality of second contact holes for forming the second contact pillars need to be formed in the dielectric layer.

In the embodiment of the application, the first contact column and the second contact column are columnar, the first contact hole and the second contact hole are hole-shaped, and compared with the contact hole in the shape of a long groove, the opening area of the first contact hole and the opening area of the second contact hole are reduced, so that the etching depth of the first contact hole and the etching depth of the second contact hole are easy to control in the process of etching the dielectric layer, the etching is stopped on the surface of the resistance matching layer through controlling, the volume of the resistance matching layer is prevented from being reduced due to over etching, and the accuracy of the resistance matching layer is ensured.

In some embodiments, the plurality of first contact beams are arranged in an array and/or the plurality of second contact beams are arranged in an array.

Through the arrangement mode, the uniformity of arrangement of the first contact columns and the second contact columns in the plane can be improved.

And in the process of preparing the chip, etching the dielectric layer to form a plurality of first contact holes and a plurality of second contact holes, then forming first contact pillars in the first contact holes, and forming second contact pillars in the second contact holes. Therefore, under the condition that a plurality of first contact columns are arranged in an array mode, a plurality of second contact columns are arranged in an array mode, a plurality of first contact holes are also arranged in an array mode, a plurality of second contact holes are also arranged in an array mode, and the uniformity of arrangement of the plurality of first contact holes and the plurality of second contact holes in a plane can be improved.

In some embodiments, the plurality of first contact beams includes a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction. And/or the plurality of second contact pillars comprise a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction.

Through the arrangement mode, the uniformity of arrangement of the plurality of first contact columns and the plurality of second contact columns in the plane can be further improved. Therefore, in the process of preparing the chip, the uniformity of arrangement of the first contact holes and the second contact holes in the plane can be further improved, and in the process of etching the dielectric layer, the etching depth of the first contact holes and the etching depth of the second contact holes are easier to control, and the etching is controlled to stop on the surface of the resistance matching layer, so that the volume of the resistance matching layer is prevented from being reduced due to over etching, and the accuracy of the resistance matching layer is ensured.

In some embodiments, the spacing between adjacent two first contact beams in a first direction is equal to the spacing between adjacent two first contact beams in a second direction, the first direction intersecting the second direction. And/or, the spacing between two adjacent second contact columns along the first direction is equal to the spacing between two adjacent second contact columns along the second direction, and the first direction is intersected with the second direction.

In some embodiments, the radial dimension of the first contact beams in the first direction is a first dimension, the radial dimension of the first contact beams in the second direction is a second dimension, the first dimension is equal to the second dimension, and the first direction intersects the second direction. And/or the radial dimension of the second contact column along the first direction is a third dimension, the radial dimension of the second contact column along the second direction is a fourth dimension, the third dimension is equal to the fourth dimension, and the first direction and the second direction are intersected.

Through the arrangement mode, the uniformity of the plane sizes of the first contact columns and the second contact columns can be improved, and the uniformity of the arrangement of a plurality of first contact columns and a plurality of second contact columns in the plane is improved. Therefore, in the process of preparing the chip, the uniformity of arrangement of the first contact holes and the second contact holes in the plane can be improved, and in the process of etching the dielectric layer, the etching depth of the first contact holes and the second contact holes is easier to control, and the etching is controlled to stop on the surface of the resistance matching layer, so that the volume of the resistance matching layer is prevented from being reduced due to over etching, and the accuracy of the resistance matching layer is ensured.

In some embodiments, the plurality of first contact pillars includes a plurality of columns arranged in a first direction and a plurality of rows arranged in a second direction, the first direction intersecting the second direction, the plurality of first contact pillars having a column number ranging from 2 to 20, and the plurality of first contact pillars having a row number ranging from 1 to 20. And/or the plurality of second contact columns comprise a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction, the first direction is intersected with the second direction, the column number range of the plurality of second contact columns is 2-20, and the row number range of the plurality of second contact columns is 1-20.

In some embodiments, the first contact pillars are in the shape of one of a quadrangular prism, a quadrangular frustum of a prism, a cylinder, and a frustum of a cone, and/or the second contact pillars are in the shape of one of a quadrangular prism, a quadrangular frustum of a prism, a cylinder, and a frustum of a cone.

In some embodiments, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer that are stacked, the chip further includes a second conductive pattern and a third conductive pattern, the second conductive pattern is disposed on a side of the second dielectric layer away from the resistance matching layer, and one ends of the plurality of first contact pillars away from the resistance matching layer are electrically connected with the second conductive pattern, so as to realize interconnection between the resistance matching layer and the second conductive pattern. The third conductive pattern is arranged on one side, far away from the resistance matching layer, of the second dielectric layer, and one ends, far away from the resistance matching layer, of the second contact columns are electrically connected with the third conductive pattern so as to realize interconnection of the resistance matching layer and the third conductive pattern.

In some embodiments, the chip includes a resistive region and a device region, the resistive layer and the first dielectric layer are located in the resistive region, and the second dielectric layer is located in the resistive region and the device region.

The chip further comprises a first conductive pattern, a third dielectric layer and a third contact column, wherein the first conductive pattern is located in the device region, and the third dielectric layer is arranged on the first conductive pattern and located in the resistance matching region and the device region. The third dielectric layer is positioned on one side of the second dielectric layer close to the first conductive pattern. The third contact post penetrates through the second dielectric layer and the third dielectric layer, and one end of the third contact post is electrically connected with the first conductive pattern so as to realize interconnection of the first conductive pattern and the third contact post.

In some embodiments, the first contact post, the second contact post, and the third contact post are the same material, i.e., the three can be prepared using the same film forming process.

In some embodiments, the chip further includes a fourth conductive pattern disposed on a side of the second dielectric layer away from the first conductive pattern, and an end of the third contact pillar away from the first conductive pattern is electrically connected to the fourth conductive pattern to achieve interconnection between the first conductive pattern and the fourth conductive pattern.

In a second aspect, a method for manufacturing a chip is provided, the method comprising: and forming a resistance matching layer and at least one dielectric layer, wherein the at least one dielectric layer is positioned on the resistance matching layer, the resistance matching layer comprises a first end and a second end, and the first end and the second end are opposite ends of the resistance matching layer along the first direction. A plurality of first contact holes and a plurality of second contact holes are formed in the at least one dielectric layer, the plurality of first contact holes exposing the first ends, and the plurality of second contact holes exposing the second ends. A first contact stud is formed in the first contact hole, and a second contact stud is formed in the second contact hole, the first contact stud is electrically connected to the first end, and the second contact stud is electrically connected to the second end.

According to the preparation method provided by the embodiment of the application, a plurality of first contact holes and a plurality of second contact holes are formed in the dielectric layer, then a first contact column is formed in the first contact holes, a second contact column is formed in the second contact holes, the first contact column is electrically connected with the first end of the resistance matching layer, and the second contact column is electrically connected with the second end of the resistance matching layer.

In the embodiment of the application, the first contact hole and the second contact hole are in a hole shape, compared with the contact hole in a long groove shape, the opening area of the first contact hole and the opening area of the second contact hole are reduced, so that the etching depth of the first contact hole and the etching depth of the second contact hole are easy to control in the process of etching the dielectric layer, the etching is stopped on the surface of the resistance matching layer through control, the volume reduction of the resistance matching layer due to over etching is avoided, and the accuracy of the resistance matching layer is ensured.

In some embodiments, the chip includes a resistive region and a device region.

Forming a resistance matching layer and at least one dielectric layer, comprising: and forming a resistance matching film and a first dielectric film in sequence. And removing the part of the first dielectric film outside the resistance matching region and the part of the resistance matching film outside the resistance matching region to form a resistance matching layer and a first dielectric layer covering the resistance matching layer. And forming a second dielectric layer which is positioned at one side of the first dielectric layer far away from the resistance matching region and the device region.

In some embodiments, before forming the resistive layer and the at least one dielectric layer, further comprising: and sequentially forming a first conductive pattern and a third dielectric layer, wherein the first conductive pattern is positioned in the device region, and the third dielectric layer is positioned in the resistance matching region and the device region.

In some embodiments, forming a plurality of first contact holes and a plurality of second contact holes includes: and etching the second dielectric layer and the first dielectric layer to form a plurality of first contact holes and a plurality of second contact holes. And in the process of etching the second dielectric layer and the first dielectric layer, etching the second dielectric layer and the third dielectric layer to form a third contact hole, wherein the third contact hole exposes the first conductive pattern.

In the above embodiment, the plurality of first contact holes and the plurality of second contact holes are all in a hole shape, and the opening areas of the first contact holes and the second contact holes are reduced, so that the etching depths of the first contact holes and the second contact holes are easy to control in the process of etching the second dielectric layer and the first dielectric layer, and the etching is controlled to stop on the surface of the resistance matching layer, so that the volume of the resistance matching layer is prevented from being reduced due to over etching, and the accuracy of the resistance matching layer is ensured.

And in the process of etching the second dielectric layer and the first dielectric layer, the second dielectric layer and the third dielectric layer are also etched to form a third contact hole, and the third contact hole exposes the first conductive pattern.

In some embodiments, after forming the third contact hole, further comprising: and etching the first conductive pattern through the bottom of the third contact hole to form a cavity in the first conductive pattern, wherein the third contact hole comprises an opening connected with the cavity, and the orthographic projection of the opening on the first conductive pattern is positioned in the orthographic projection range of the cavity on the first conductive pattern.

In the above embodiment, since the opening areas of the first contact hole and the second contact hole are reduced, in the process of etching the first conductive pattern, the contact between the etching gas or the etching liquid and the matching resistance layer through the first contact hole and the second contact hole can be weakened or even avoided, the volume reduction of the matching resistance layer due to etching is avoided, and thus the accuracy of the resistance value of the matching resistance layer is ensured.

In addition, as the orthographic projection of the opening on the first conductive pattern is positioned in the orthographic projection range of the cavity on the first conductive pattern, the third contact hole is communicated with the cavity to form a cavity with the appearance similar to a rivet, so that after the third contact post is formed in the cavity, the appearance of the third contact post is also similar to a rivet, and in the subsequent grinding process, if grinding fluid permeates along the gap between the third contact post and the side wall of the third contact hole, the nail cap of the third contact post can play a role of blocking the grinding fluid, so that the grinding fluid is prevented from contacting and corroding the first conductive pattern.

In some embodiments, a selective deposition process is adopted to form a first contact post in the first contact hole, and a third contact post is further formed in the third contact hole in the process of forming a second contact post in the second contact hole, and the third contact post is electrically connected with the first conductive pattern, so that a gap is not formed in the contact post formed by the selective deposition process, and the resistance of the contact post is reduced.

In some embodiments, after forming the first contact stud and the second contact stud, further comprising: and performing ion implantation on at least one dielectric layer.

In the above embodiment, the ion implantation is performed on the dielectric layer, so that the dielectric layer can be expanded to reduce the apertures of the first contact hole, the second contact hole and the third contact hole, thereby reducing the gap between the corresponding hole and the contact post, and in the process of the subsequent polishing process, the problem of infiltration of the polishing liquid through the gap between the hole and the contact structure can be improved, so as to reduce the phenomenon that the polishing liquid corrodes the first conductive pattern and the resistance-matching layer.

And, because the opening area of the first contact hole and the second contact hole is reduced, the probability of entering ions through the gap between the hole and the contact column is reduced in the ion implantation process, thereby avoiding the problem of misalignment of the resistance value of the resistance matching layer caused by ion implantation of the resistance matching layer.

In some embodiments, after forming the first contact stud and the second contact stud, further comprising: and forming a protective layer and a sacrificial layer in sequence, wherein the protective layer and the sacrificial layer cover at least one dielectric layer, the first contact posts and the second contact posts. And grinding the sacrificial layer, the protective layer and the part of one side, away from the resistance matching layer, of the at least one dielectric layer to expose the ends, away from the resistance matching layer, of the first contact pillars and the second contact pillars.

In the above embodiment, the plurality of first contact pillars and the plurality of second contact pillars are arranged in the resistance matching area, which is favorable for improving the uniformity of intensity of the surface of the resistance matching area, thereby improving the uniformity of surface grinding of the resistance matching area, avoiding the top of the first contact pillars and the second contact pillars from generating dishing damage, ensuring that the top surfaces of the first contact pillars and the second contact pillars are flat and completely exposed, and facilitating the stable contact between the conductive patterns and the first contact pillars and the second contact pillars after the conductive patterns are formed above the first contact pillars and the second contact pillars.

In a third aspect, an electronic device is provided, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product. The electronic device comprises the chip of any embodiment and a circuit board electrically connected with the chip.

It can be appreciated that the beneficial effects of the electronic device provided in the above embodiments of the present application can refer to the beneficial effects of the chip described above, and will not be described herein.

Drawings

For a clearer description of the technical solutions in the present application, the drawings that need to be used in some embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings may be obtained according to these drawings for a person of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. according to the embodiments of the present application.

FIG. 1 is a block diagram of an electronic device according to some embodiments;

FIG. 2 is a top view of a chip of the related art;

FIG. 3 is a cross-sectional view of the chip of FIG. 2 along section line A-A';

FIG. 4 is a top view of another chip according to the related art;

FIG. 5 is a cross-sectional view of the chip of FIG. 4 along section line B-B';

FIG. 6 is a top view of yet another chip in the related art;

FIG. 7 is a cross-sectional view of the chip of FIG. 6 along section line C-C';

FIG. 8 is a cross-sectional view of the chip of FIG. 6 along section line D-D';

FIGS. 9A-9I are views of steps in preparing a chip 10' in the related art;

FIG. 10 is a top view of a chip according to some embodiments;

FIG. 11 is a cross-sectional view of the chip of FIG. 10 along section line E-E';

FIG. 12 is a cross-sectional view of the chip of FIG. 10 along section line F-F';

fig. 13A-13J are diagrams of steps for preparing the chips described above, according to some embodiments.

Detailed Description

The following description of some embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided herein are within the scope of the present application.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel may be, for example, a deviation within 5 °; "vertical" includes absolute vertical and near vertical, where the acceptable deviation range for near vertical may also be deviations within 5 °, for example. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Some embodiments of the present application provide an electronic device, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product. Among them, consumer electronics products such as mobile phones, tablet computers, notebook computers, electronic readers, personal computers (Personal Computer, abbreviated as PC), personal digital assistants (Personal Digital Assistant, abbreviated as PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual Reality (VR) terminal devices, augmented Reality (Augmented Reality, abbreviated as AR) terminal devices, unmanned aerial vehicles, and the like. Household electronic products such as intelligent door locks, televisions, remote controllers, refrigerators, small household appliances (e.g., soymilk makers, sweeping robots) and the like. The vehicle-mounted electronic products are, for example, vehicle-mounted navigator, vehicle-mounted high-density digital video optical disk and the like. Financial terminal products such as terminals for automated teller machines, self-service business processes, and the like. The communication electronic product is a communication device such as a server, a memory, a base station, and the like.

Some embodiments of the present application do not particularly limit the specific form of the electronic device described above. For convenience of explanation, the following embodiments take an electronic device as a mobile phone for illustration.

Fig. 1 is a block diagram of an electronic device according to some embodiments.

As shown in fig. 1, the electronic device 1 mainly includes a cover plate 11, a display screen 12, a middle frame 13, and a rear case 14. The rear shell 14 and the display screen 12 are respectively positioned at two sides of the middle frame 13, the middle frame 13 and the display screen 12 are arranged in the rear shell 14, the cover plate 11 is arranged at one side of the display screen 12 far away from the middle frame 13, and the display surface of the display screen 12 faces the cover plate 11.

The display 12 may be a liquid crystal display (Liquid Crystal Display, abbreviated as LCD), in which case the liquid crystal display includes a liquid crystal display panel and a backlight module, the liquid crystal display panel is disposed between the cover plate 11 and the backlight module, and the backlight module is used for providing a light source for the liquid crystal display panel. The display 12 may also be an organic light emitting diode (Organic Light Emitting Diode, OLED) display. The OLED display screen is a self-luminous display screen, so that a backlight module is not required to be arranged.

The middle frame 13 includes a carrying plate 131 and a frame 132 surrounding the carrying plate 131. The electronic device 1 further includes electronic components such as a circuit board 15, a battery, and a camera, which are disposed on the carrier 131.

As shown in fig. 1, the electronic device 1 may further include a chip 10 disposed on the circuit board 15, where the chip 10 is electrically connected to the circuit board 15.

The chip 10 may include a processor chip, a memory chip, a radio frequency power amplifier chip, a power management chip, an audio processor chip, a touch screen control chip, an image sensor chip, a charge protection chip, and the like.

Some embodiments of the present application provide for a chip 10 that may be a bare chip or a packaged chip that may include one or more bare chips. The following examples of the present application will be described with reference to a chip 10 being a two-dimensional bare chip.

FIG. 2 is a top view of a chip of the related art; fig. 3 is a cross-sectional view of the chip of fig. 2 along section line A-A'.

Referring to fig. 2 and 3, the chip 10 ' includes a substrate 20 ', and a transfer layer L ' and a rewiring layer 27 ' stacked on the substrate 20 '.

Wherein the substrate 20 'includes a substrate G', and an electronic component T 'disposed on the substrate G'.

Illustratively, the electronic component T' may include a transistor, a capacitor, an inductor, or the like. The electronic component T' in fig. 2 is illustrated as a transistor including a gate G, a source S, and a drain D.

With continued reference to fig. 2 and 3, the transfer layer L 'includes a first dielectric layer 21' and a second dielectric layer 23 'stacked on the substrate 20', a conductive pattern 22 'extending through the first dielectric layer 21', and a conductive post 24 'extending through the second dielectric layer 23'.

One end of the conductive pattern 22 ' is electrically connected to the electronic element T ', for example, the gate G, the source S, and the drain D of the transistor are respectively corresponding to and electrically connected to one conductive pattern 22 '.

One end of the conductive post 24 'is electrically connected to the other end of the conductive pattern 22'. The transfer layer L ' further includes an adhesive layer 26 ' surrounding the sides and bottom of the conductive post 24 ', the adhesive layer 26 ' being operable to adhere to the conductive post 24 ' to improve the strength of the connection between the conductive post 24 ' and the second dielectric layer 23 '.

With continued reference to fig. 2 and 3, the rewiring layer 27 'includes a plurality of conductive layers therein, the lowermost conductive layer of the plurality of conductive layers being electrically connected to the conductive posts 24'. The uppermost conductive layer is exposed to the surface of the rewiring layer 27' and is available for connection to a functional device, for example, the uppermost conductive layer may serve as a pad for connection to a functional device.

During operation of the chip 10 ', an electrical signal in the electronic component T' may be transmitted to the conductive layer of the rewiring layer 27 'via the conductive pattern 22' and the conductive post 24 ', and, in turn, the electrical signal may be transmitted to a functional device connected thereto via the uppermost conductive layer of the rewiring layer 27'.

In the process of manufacturing the chip 10 ', the electronic component T' is generally first manufactured on the substrate G 'to form the substrate 20', then the first dielectric layer 21 'is formed on the substrate 20', and the conductive pattern 22 'penetrating the first dielectric layer 21' is formed. Thereafter, a second dielectric layer 23 'is formed on the side of the first dielectric layer 21' away from the substrate 20 ', and a conductive post 24' is formed to penetrate the second dielectric layer 23 ', and finally a rewiring layer 27' is formed on the side of the second dielectric layer 23 'away from the substrate 20'.

In the process of forming the conductive pillar 24 'penetrating the second dielectric layer 23', a via penetrating the second dielectric layer 23 'is required to be formed, the via exposes the conductive pattern 22', then the adhesive layer 26 'is formed on the sidewall and the bottom of the via, and finally, a chemical vapor deposition (Chemical Vapor Deposition, abbreviated as CVD) process may be used to deposit a conductive material in the via to form the conductive pillar 24'.

The inventors of the present application have studied and found that, with reference to fig. 2 and 3, during the process of depositing conductive material in the via, the conductive material is deposited at both the sidewall and the bottom of the via, and at the junction (corner) between the sidewall and the bottom, at a faster rate, and thus, with the conductive material at the top of the via closed, the inside of the conductive material in the via will generate a void 25 ', so that the inside of the conductive post 24' has a void 25 ', which increases the resistance of the conductive post 24', resulting in loss of the electrical signal (e.g., voltage value of the electrical signal is reduced) during the transmission on the conductive post 24 ', thereby affecting the performance of the chip 10'.

Also, since the adhesive layer 26 ' has a certain thickness, it occupies the space of the via hole, resulting in a reduction in the diameter of the conductive post 24 ' and a reduction in the area of the radial cross section, which also increases the resistance of the conductive post 24 '.

In addition, the conductive pattern 22 ' and the conductive post 24 ' are separated by the adhesive layer 26 ', and in general, the material of the adhesive layer 26 ' is titanium or titanium nitride, but the conductive property of titanium or titanium nitride is poor, which increases the contact resistance between the conductive pattern 22 ' and the conductive post 24 ' and the adhesive layer 26 ', resulting in loss of the electrical signal in the process of transmitting from the conductive pattern 22 ' to the conductive post 24 ' through the adhesive layer 26 ', and affecting the performance of the chip 10 '.

Based on this, the related art provides another chip, and fig. 4 is a top view of another chip in the related art;

fig. 5 is a cross-sectional view of the chip of fig. 4 along section line B-B'.

Referring to fig. 4 and 5, the conductive post 24 'of the chip 10' has no void therein and no adhesive layer between the conductive post 24 'and the conductive pattern 22', which reduces the resistance of the conductive post 24 ', reduces the contact resistance between the conductive post 24' and the conductive pattern 22 ', and thus reduces the loss of electrical signals transmitted from the conductive pattern 22' to the conductive post 24 ', which is beneficial for improving the performance of the chip 10'.

In the process of preparing the conductive pillars 24 'of the chip 10', the contact holes H 'and the conductive patterns 22' are first surface-treated to remove chemical residues and dangling bonds attached to the inner walls of the contact holes H ', and chemical residues and dangling bonds attached to the surfaces of the conductive patterns 22' to expose nonmetallic materials of the inner walls of the contact holes H ', and metallic materials of the surfaces of the conductive patterns 22'.

The above-mentioned "chemical residue" may be a chemical substance remaining in the process of forming the contact hole H'; the "dangling bond" may be, for example, a chemical bond that has no electron energy pairing.

The manner of surface-treating the contact hole H 'and the conductive pattern 22' may include, for example: heat treatment, plasma treatment, treatment with a reducing gas (e.g., hydrogen gas), treatment with an oxidizing gas (e.g., oxygen gas and nitrous oxide), and treatment with an inert gas.

Then, a selective deposition process is adopted to deposit the conductive material in the contact hole H ', the deposition rate of the conductive material on the surface of the metal material is larger than that of the conductive material on the surface of the nonmetal material, namely, the deposition rate of the conductive material on the surface of the conductive pattern 22 ' is larger than that of the conductive material on the inner wall of the contact hole H ', and the selective deposition of the conductive material is realized. In this way, the conductive material is filled in the contact hole H 'before the top conductive material of the contact hole H' is closed, so that the void is avoided inside the conductive material in the contact hole H ', and the void is avoided inside the conductive column 24'.

Typically, the chip 10' further includes a resistor device, and fig. 6 is a top view of yet another chip in the related art; FIG. 7 is a cross-sectional view of the chip of FIG. 6 along section line C-C'; fig. 8 is a cross-sectional view of the chip of fig. 6 along section line D-D'.

Referring to fig. 6 to 8, the chip 10 ' includes a resistance matching region A1 and a device region A2, the resistance device R ' is disposed in the resistance matching region A1, and the electronic component T ' is disposed in the device region A2.

The chip 10 'includes a substrate 20', a first dielectric layer 21 'disposed on the substrate 20', and a first conductive pattern 22 'penetrating the first dielectric layer 21'. The substrate 20 'includes a substrate G', and an electronic component T 'disposed on the substrate G', for example, the electronic component T 'is a transistor including a gate G, a source S, and a drain D, which are respectively corresponding to and electrically connected to one of the first conductive patterns 22'.

The chip 10 ' further includes a second dielectric layer 23 ', the second dielectric layer 23 ' being disposed on a side of the first dielectric layer 21 ' remote from the substrate 20 '.

With continued reference to fig. 6-8, a resistive device R ' is disposed on a side of the second dielectric layer 23 ' remote from the substrate 20 ', the resistive device R ' including a resistive layer 24 '. The chip 10 'further includes third and fourth dielectric layers 25' and 26 'disposed in this order on a side of the resistive layer 24' remote from the substrate 20 ', first and second contact structures 28 a' and 28b 'extending through the fourth and third dielectric layers 26' and 25 ', and a third contact structure 28 c' extending through the fourth and second dielectric layers 26 'and 23'. Wherein the first contact structure 28a 'and the second contact structure 28 b' are electrically connected to both ends of the resistive layer 24 ', respectively, to realize interconnection of the resistive devices R'. The third contact structure 28c ' is a pillar shape, which is electrically connected to the first conductive pattern 22 ' to realize interconnection of the electronic element T '.

The resist layer 24 'has a designed resistance value, and in the case where the resist layer 24' has a rectangular parallelepiped shape, the length, width, and height of the resist layer 24 'are set according to the designed resistance value, thereby determining the volume of the resist layer 24'.

However, referring to fig. 6-8, the first contact structure 28a 'and the second contact structure 28 b' each extend through the resistive layer 24 'and are electrically connected to the resistive layer 24'. Equivalently, the resist layer 24 'has a through hole therein, where the first contact structure 28 a' and the second contact structure 28b 'are electrically connected to the resist layer 24', and the volume of the resist layer 24 'is reduced due to the through hole, so that the resistance of the resist layer 24' is misaligned, which results in a mismatch (mismatch) between the resistance of the resist layer 24 'and the resistance of other resist layers in the chip 10'.

Furthermore, the side surfaces of the bottoms of the first contact structure 28a ' and the second contact structure 28b ' and the matching resist layer 24 ' have a gap therebetween, which may cause poor contact between the first contact structure and the matching resist layer 24 ', raise contact resistance, and further cause misalignment of the resistance value of the matching resist layer 24 '.

Moreover, the tops of the first contact structure 28a 'and the second contact structure 28 b' are each "dished", i.e., the top surfaces of the first contact structure 28a 'and the second contact structure 28 b' are recessed downward, and then after forming a wire over the first contact structure 28a 'and the second contact structure 28 b', the wire is prone to poor contact, or even disconnection, between the first contact structure 28a 'and the second contact structure 28 b'.

The inventors of the present application have studied to find that the problems generated by the chip 10 ' are all generated in the process of manufacturing the chip 10 ', and the reason for the problems is explained next in conjunction with the manufacturing process of the chip 10 '.

Fig. 9A to 9I are views of steps of preparing a chip 10 'according to the related art, and a specific preparation process of the chip 10' is as follows:

as shown in fig. 9A, a first dielectric layer 21 ', a first conductive pattern 22 ' penetrating the first dielectric layer 21 ', a second dielectric layer 23 ', a resist film 240 ', and a third dielectric film 250 ' are sequentially formed on a substrate 20 '.

As shown in fig. 9B, the portions of the resist matching film 240 'and the third dielectric film 250' located in the device region A2 are etched away, and the portions of the resist matching film 240 'and the third dielectric film 250' located in the resist matching region A1 are left, so as to obtain a resist matching layer 24 'and a third dielectric layer 25'.

As shown in fig. 9C, a fourth dielectric layer 26 'is formed, the fourth dielectric layer 26' being located in the resistive area A1 and the device area A2, and the fourth dielectric layer 26 'covering the third dielectric layer 25'.

As shown in fig. 9D, in the resistance matching region A1, the fourth dielectric layer 26 'and the third dielectric layer 25' are etched to form a first contact hole H1 and a second contact hole H2 therethrough. And the fourth dielectric layer 26 'and the second dielectric layer 23' are etched within the device region A2 to form a third contact hole H3 therethrough.

Because the first contact hole H1 and the second contact hole H2 are long grooves, the third contact hole H3 is a circular via hole, the opening area of the first contact hole H1 and the second contact hole H2 is larger than that of the third contact hole H3, and in the process of etching the fourth dielectric layer 26 'and the third dielectric layer 25', the etching depth of the first contact hole H1 and the second contact hole H2 is difficult to control, the resistance matching layer 24 'is easy to etch and penetrate, and the resistance of the resistance matching layer 24' is further inaccurate.

As shown in fig. 9E, the first conductive pattern 22 'is etched back via the third contact hole H3 to form a cavity within the first conductive pattern 22'. However, since the opening areas of the first contact hole H1 and the second contact hole H2 are large, during the etching back of the first conductive pattern 22 ', the etching gas or the etching liquid may contact the resist 24' through the first contact hole H1 and the second contact hole H2, and may etch the resist 24 'laterally to cause the recess of the side surface thereof, and may also cause the misalignment of the resistance value of the resist 24'.

As shown in fig. 9F, a conductive material is deposited in the first, second and third contact holes H1, H2 and H3 to form first, second and third contact structures 28a ', 28b ' and 28c ', respectively.

As shown in fig. 9G, an ion implantation process is used to implant ions into the second dielectric layer 23 ', the third dielectric layer 25' and the fourth dielectric layer 26 ', so that the second dielectric layer 23', the third dielectric layer 25 'and the fourth dielectric layer 26' are expanded to reduce the aperture of the first contact hole H1, the aperture of the second contact hole H2 and the aperture of the third contact hole H3, thereby reducing the gap between the corresponding holes and the contact structure, and in the subsequent polishing process, the problem of infiltration of the polishing liquid through the gap between the holes and the contact structure can be improved, so as to reduce the phenomenon that the polishing liquid corrodes the first conductive pattern 22 'and the distribution layer 24'.

However, due to the large opening areas of the first contact hole H1 and the second contact hole H2, during the ion implantation process, some ions may enter through the gap between the hole and the contact structure and be implanted into the resist layer 24 ', resulting in misalignment of the resistance value of the resist layer 24'.

As shown in fig. 9H, a protective layer 29 'and a sacrificial layer 30' are sequentially formed, the protective layer 29 'and the sacrificial layer 30' covering the fourth dielectric layer 26 ', the first contact structure 28 a', the second contact structure 28b ', and the third contact structure 28 c'.

As shown in fig. 9H and 9I, portions of the sacrificial layer 30 ', the protective layer 29', and the fourth dielectric layer 26 'on the side away from the substrate 20' are polished to expose ends of the first contact structure 28a ', the second contact structure 28 b', and the third contact structure 28c 'that are away from the substrate 20'.

However, in the resist matching region A1, since the first contact structure 28a 'and the second contact structure 28 b' are disposed at both sides of the region, and the first contact structure 28a 'and the second contact structure 28 b' are made of a metal material, the fourth dielectric layer 26 'is made of a non-metal material, and the materials of the two materials are different, so that the strength of the surface of the resist matching region A1 is not uniform, and the polishing rate of the first contact structure 28 a' and the second contact structure 28b 'is greater than that of the fourth dielectric layer 26', the tops of the first contact structure 28a 'and the second contact structure 28 b' generate "dishing" damage, i.e., the top surfaces of the first contact structure 28a 'and the second contact structure 28 b' are concave downward.

To solve the above problems, some embodiments of the present application further provide a chip and a method for manufacturing the same, and fig. 10 is a top view of the chip according to some embodiments; FIG. 11 is a cross-sectional view of the chip of FIG. 10 along section line E-E'; fig. 12 is a cross-sectional view of the chip of fig. 10 taken along section line F-F'.

Referring to fig. 10-12, the chip 10 includes a resist layer 24, the resist layer 24 includes a first end 24a and a second end 24b, and the first end 24a and the second end 24b are opposite ends of the resist layer 24 along a first direction X.

The first direction X is parallel to the extension plane of the resist layer 24, for example, the first direction X is the length extension direction of the resist layer 24.

Illustratively, the resistive layer 24 has a length in the range of 0.36 μm to 25 μm, a width in the range of 0.2 μm to 1.8 μm, and a thickness in the range of 0.03 μm to 0.07 μm.

The chip 10 further comprises at least one dielectric layer disposed on the resistive layer 24, for example, the at least one dielectric layer comprises a first dielectric layer 25 and a second dielectric layer 26 disposed in a stack.

The chip 10 further includes a plurality of first contact pillars 28a electrically connected to the first end 24a of the resistive layer 24 through at least one dielectric layer, and a plurality of second contact pillars 28b electrically connected to the second end 24b of the resistive layer 24 through at least one dielectric layer.

The chip 10 provided in the above embodiment of the present application employs a plurality of columnar first contact pillars 28a electrically connected to the first end 24a of the resistive layer 24, and a plurality of columnar second contact pillars 28b electrically connected to the second end 24b of the resistive layer 24. Based on this, in the process of manufacturing the chip 10, a plurality of first contact holes for forming the first contact pillars 28a and a plurality of second contact holes for forming the second contact pillars 28b need to be formed in the dielectric layer.

In the embodiment of the application, the first contact pillar 28a and the second contact pillar 28b are both cylindrical, the first contact hole and the second contact hole are both in a hole shape, and compared with the contact hole in a long groove shape, the opening area of the first contact hole and the opening area of the second contact hole are reduced, so that the etching depth of the first contact hole and the etching depth of the second contact hole are easy to control in the process of etching the dielectric layer, the etching is stopped on the surface of the matching resistance layer 24 through controlling, the volume of the matching resistance layer 24 is prevented from being reduced due to over etching, and the resistance value of the matching resistance layer 24 is ensured to be accurate.

Referring to fig. 10 to 12, neither the first contact stud 28a nor the second contact stud 28b penetrates the matching layer 24, so that the volume of the matching layer 24 is smaller, the resistance is more stable, and the mismatch between the resistance of the matching layer 24 and the resistance of other matching layers in the chip 10 is improved.

In addition, the first contact pillars 28a and the matching resistance layer 24 and the second contact pillars 28b and the matching resistance layer 24 have good contact and no gap, so that the contact resistance between the contact pillars and the matching resistance layer 24 can be reduced, and the mismatch between the resistance value of the matching resistance layer 24 and the resistance value of other matching resistance layers in the chip 10 can be improved.

In addition, the top surfaces of the first contact stud 28a and the second contact stud 28b are flat and completely exposed, and subsequent formation of the conductive pattern over the first contact stud 28a and the second contact stud 28b facilitates stable contact of the conductive pattern with the first contact stud 28a and the second contact stud 28 b.

In some embodiments, as shown in fig. 10, a plurality of first contact beams 28a are arranged in an array. Alternatively, a plurality of second contact beams 28b are arranged in an array. Alternatively, a plurality of first contact beams 28a and a plurality of second contact beams 28b are each arranged in an array.

Illustratively, the plurality of first contact beams 28a includes a plurality of columns aligned in the first direction X and a plurality of rows aligned in the second direction Y.

Illustratively, the number of columns of the plurality of first contact beams 28a ranges from 2 to 20, and the number of rows ranges from 1 to 20, e.g., the number of columns of the plurality of first contact beams 28a is 2, and the number of rows is 1; alternatively, the number of columns of the first plurality of contact beams 28a is 6 and the number of rows is 2; alternatively, the number of columns of the first contact beams 28a is 20 and the number of rows is 20.

Illustratively, the plurality of second contact beams 28b includes a plurality of columns aligned in the first direction X and a plurality of rows aligned in the second direction Y.

Illustratively, the number of columns of the plurality of second contact beams 28b ranges from 2 to 20, and the number of rows ranges from 1 to 20, e.g., the number of columns of the plurality of second contact beams 28b is 2, and the number of rows is 1; alternatively, the number of columns of the plurality of second contact beams 28b is 6 and the number of rows is 2; alternatively, the number of columns of the second contact beams 28b is 20 and the number of rows is 20.

Illustratively, the first plurality of contact beams 28a includes a plurality of columns aligned in the first direction X and a plurality of rows aligned in the second direction Y, and the second plurality of contact beams 28b includes a plurality of columns aligned in the first direction X and a plurality of rows aligned in the second direction Y.

The first direction X intersects with the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

By the arrangement, the uniformity of the arrangement of the plurality of first contact beams 28a and the plurality of second contact beams 28b in the X-Y plane can be improved.

In some embodiments, as shown in fig. 10, the spacing D1 between adjacent two first contact beams 28a in the first direction X is equal to the spacing D2 between adjacent two first contact beams 28a in the second direction Y.

Alternatively, the spacing D3 between two adjacent second contact beams 28b in the first direction X is equal to the spacing D4 between two adjacent second contact beams 28b in the second direction Y.

Alternatively, the spacing D1 between adjacent two of the first contact beams 28a in the first direction X is equal to the spacing D2 between adjacent two of the first contact beams 28a in the second direction Y. And, the spacing D3 between two adjacent second contact beams 28b in the first direction X is equal to the spacing D4 between two adjacent second contact beams 28b in the second direction Y.

By the arrangement, the uniformity of the arrangement of the plurality of first contact beams 28a and the plurality of second contact beams 28b in the X-Y plane can be further improved.

In some embodiments, as shown in fig. 10, the radial dimension of the first contact beams 28a in the first direction X is a first dimension, the radial dimension of the first contact beams 28a in the second direction Y is a second dimension, and the first dimension is equal to the second dimension.

Alternatively, the radial dimension of the second contact beams 28b along the first direction X is a third dimension, the radial dimension of the second contact beams 28b along the second direction Y is a fourth dimension, and the third dimension is equal to the fourth dimension.

Alternatively, the first dimension of the first contact beam 28a is equal to the second dimension and the third dimension of the second contact beam 28b is equal to the fourth dimension.

It is understood that the shape of the first contact stud 28a may be one of a quadrangular prism, a quadrangular pyramid, a cylinder, and a truncated cone. Alternatively, the second contact stud 28b may have one of a quadrangular prism, a quadrangular prism table, a cylinder, and a circular table. Alternatively, the first contact stud 28a may be one of a quadrangular prism, a cylinder, and a circular truncated cone in shape, and the second contact stud 28b may be one of a quadrangular prism, a cylinder, and a circular truncated cone in shape.

By the arrangement mode, the uniformity of the dimensions of the first contact beams 28a and the second contact beams 28b along the X-Y plane can be improved, and the uniformity of the arrangement of the plurality of first contact beams 28a and the plurality of second contact beams 28b along the X-Y plane can be improved.

In some embodiments, as shown in fig. 11 and 12, the chip 10 further includes a second conductive pattern P1 and a third conductive pattern P2, where the second conductive pattern P1 is disposed on a side of the second dielectric layer 26 away from the resistive layer 24, and one ends of the plurality of first contact pillars 28a away from the resistive layer 24 are electrically connected to the second conductive pattern P1 to implement interconnection between the resistive layer 24 and the second conductive pattern P1.

The third conductive pattern P2 is disposed on a side of the second dielectric layer 26 away from the resistive layer 24, and one end of the plurality of second contact pillars 28b away from the resistive layer 24 is electrically connected to the third conductive pattern P2, so as to interconnect the resistive layer 24 and the third conductive pattern P2.

In some embodiments, as shown in fig. 11, the chip 10 includes a matching resistive region A1 and a device region A2, the matching resistive layer 24 and the first dielectric layer 25 are located in the matching resistive region A1, and the second dielectric layer 26 is located in the matching resistive region A1 and the device region A2.

The chip 10 further includes a substrate 20, a dielectric layer 21 disposed on the substrate 20, a first conductive pattern 22 penetrating the dielectric layer 21, and a third dielectric layer 23 disposed on the first conductive pattern 22.

The substrate 20 includes a substrate G, and an electronic component T disposed on the substrate G, for example, the electronic component T is a transistor, and the transistor includes a gate G, a source S, and a drain D, and the gate G, the source S, and the drain D of the transistor are respectively corresponding to and electrically connected to one of the first conductive patterns 22.

The electronic component T and the first conductive pattern 22 are both located in the device area A2, the third dielectric layer 23 is located in the resistive area A1 and the device area A2, and the third dielectric layer 23 is located on a side of the second dielectric layer 26 close to the first conductive pattern 22. The chip 10 further comprises third contact studs 28c, which third contact studs 28c penetrate the second dielectric layer 26 and the third dielectric layer 23 and are electrically connected at one end to the first conductive pattern 22.

As shown in fig. 11, the chip 10 further includes a fourth conductive pattern P3, the fourth conductive pattern P3 is disposed on a side of the second dielectric layer 26 away from the first conductive pattern 22, and an end of the third contact pillar 28c away from the first conductive pattern 22 is electrically connected with the fourth conductive pattern P3 to interconnect the electronic component T and the fourth conductive pattern P3.

In some embodiments, the first contact beam 28a, the second contact beam 28b, and the third contact beam 28c are the same material.

It will be appreciated that the first contact beam 28a, the second contact beam 28b, and the third contact beam 28c are of the same material and are disposed in the same layer.

The above-mentioned "same layer" refers to a layer structure formed by preparing a film layer for forming a specific pattern by the same film forming process and then using the same mask plate through a one-time patterning process. Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular patterns in the formed layer structure may be continuous or discontinuous, and may be at different heights or have different thicknesses.

The chip 10 provided in the above embodiment of the present application also benefits from its manufacturing process, and next, how the above structure is formed by describing the manufacturing process of the chip 10 will be specifically described.

As shown in fig. 13A, a dielectric layer 21, a first conductive pattern 22 penetrating the dielectric layer 21, a third dielectric layer 23, a resist film 240, and a first dielectric film 250 are sequentially formed on a substrate 20.

Illustratively, the material of the first conductive pattern 22 may include cobalt.

As shown in fig. 13B, the resist layer 24 and the first dielectric layer 25 are formed.

Illustratively, referring to fig. 13A and 13B, a portion of the first dielectric film 250 located outside the resist matching region A1 and a portion of the resist matching film 240 located outside the resist matching region A1 are removed to form a resist matching layer 24 and a first dielectric layer 25 covering the resist matching layer 24.

For example, the portion of the first dielectric film 250 located in the resist matching region A1 may be covered with photoresist, and the first dielectric film 250 and the resist matching film 240 may be etched using the photoresist as a mask, so as to remove the portion of the first dielectric film 250 located outside the resist matching region A1 and the portion of the resist matching film 240 located outside the resist matching region A1.

As shown in fig. 13C, a second dielectric layer 26 is formed, where the second dielectric layer 26 is located in the resistive matching region A1 and the device region A2, and is located on a side of the first dielectric layer 25 away from the resistive matching layer 24.

Since the resistance matching region A1 is provided with the resistance matching layer 24 and the first dielectric layer 25, the surface of the resistance matching region A1 is higher than the surface of the device region A2, so that the surface of the second dielectric layer 26 located in the resistance matching region A1 is higher than the surface of the second dielectric layer located in the device region A2.

As shown in fig. 13D, a plurality of first contact holes H1 and a plurality of second contact holes H2 are formed in the second dielectric layer 26 and the first dielectric layer 25, the plurality of first contact holes H1 exposing the first end 24a of the resist layer 24, and the plurality of second contact holes H2 exposing the second end 24b of the resist layer 24.

Illustratively, the second dielectric layer 26 and the first dielectric layer 25 are etched to form a plurality of first contact holes H1 and a plurality of second contact holes H2.

Compared with the related art, the first contact hole H1 and the second contact hole H2 are long grooves, in the above embodiment of the present application, the first contact holes H1 and the second contact holes H2 are all holes, and the opening areas of the first contact holes H1 and the second contact holes H2 are reduced, so that the etching depth of the first contact holes H1 and the second contact holes H2 is easy to control in the process of etching the second dielectric layer 26 and the first dielectric layer 25, and the etching is stopped on the surface of the distribution resistance layer 24 by controlling the etching, so that the volume of the distribution resistance layer 24 is prevented from being reduced due to over etching, and the resistance value of the distribution resistance layer 24 is ensured to be accurate.

In addition, according to the foregoing, the plurality of first contact pillars 28a are arranged in an array, the plurality of second contact pillars 28b are arranged in an array, and since the first contact holes H1 are used for forming the first contact pillars 28a and the second contact holes H2 are used for forming the second contact pillars 28b, the plurality of first contact holes H1 are also arranged in an array, and the plurality of second contact holes H2 are also arranged in an array, so that the uniformity of the arrangement of the plurality of first contact holes H1 and the plurality of second contact holes H2 in the X-Y plane can be improved, and in this way, the etching depth of the first contact holes H1 and the second contact holes H2 can be controlled more easily in the process of etching the second dielectric layer 26 and the first dielectric layer 25.

In addition, in the process of etching the second dielectric layer 26 and the first dielectric layer 25, the second dielectric layer 26 and the third dielectric layer 23 are also etched, forming a third contact hole H3, and the third contact hole H3 exposes the first conductive pattern 22.

As shown in fig. 13E, the first conductive pattern 22 is etched through the bottom of the third contact hole H3 to form a cavity K within the first conductive pattern 22. The third contact hole H3 includes an opening connected to the cavity K, which is in front projection on the first conductive pattern 22, within a range of front projection of the cavity K on the first conductive pattern 22.

The third contact hole H3 communicates with the cavity K to form a cavity having a shape similar to a rivet.

In the above embodiment of the present application, since the opening areas of the first contact hole H1 and the second contact hole H2 are reduced, in the process of etching the first conductive pattern 22, the contact between the etching gas or the etching liquid and the matching layer 24 via the first contact hole H1 and the second contact hole H2 can be weakened or even avoided, and the volume of the matching layer 24 is prevented from being reduced due to etching, thereby ensuring the accuracy of the resistance value of the matching layer 24.

As shown in fig. 13F, a first contact stud 28a is formed in the first contact hole H1, and a second contact stud 28b is formed in the second contact hole H2, the first contact stud 28a being electrically connected to the first end 24a of the resistive layer 24, the second contact stud 28b being electrically connected to the second end 24b of the resistive layer 24.

Illustratively, in the process of forming the first contact stud 28a in the first contact hole H1 and the second contact stud 28b in the second contact hole H2, a third contact stud 28c is also formed in the third contact hole H3, and the third contact stud 28c is electrically connected to the first conductive pattern 22, and no void is formed in the contact stud formed by the selective deposition process, which is advantageous for reducing the resistance of the contact stud.

It will be appreciated that, in accordance with the foregoing, the third contact hole H3 communicates with the cavity K to form a cavity shaped like a "rivet" and, therefore, the third contact post 28c also has a shape like a "rivet".

In the above embodiment of the present application, the first contact pillars 28a and the second contact pillars 28b do not penetrate the matching resistive layer 24, so that the volume loss of the matching resistive layer 24 is smaller, the resistance thereof is more stable, and the mismatch between the resistance of the matching resistive layer 24 and the resistance of other matching resistive layers in the chip 10 is improved.

As shown in fig. 13G, ion implantation is performed on the third dielectric layer 23, the first dielectric layer 25 and the second dielectric layer 26, for example, germanium ions are implanted, so that the third dielectric layer 23, the first dielectric layer 25 and the second dielectric layer 26 are expanded to reduce the aperture of the first contact hole H1, the aperture of the second contact hole H2 and the aperture of the third contact hole H3, thereby reducing the gap between the corresponding hole and the contact post, and in the process of the subsequent polishing process, the problem of infiltration of the polishing solution through the gap between the hole and the contact structure can be improved, so as to reduce the phenomenon that the polishing solution corrodes the first conductive pattern 22 and the resistive layer 24.

In addition, as the opening areas of the first contact hole H1 and the second contact hole H2 are reduced, the probability of ions entering through the gap between the hole and the contact column is reduced in the ion implantation process, and therefore the problem of misalignment of the resistance value of the resistance matching layer 24 caused by ion implantation of the resistance matching layer 24 is avoided.

As shown in fig. 13H, a protective layer 29 and a sacrificial layer 30 are sequentially formed, the protective layer 29 and the sacrificial layer 30 covering the second dielectric layer 26, the first contact pillars 28a, the second contact pillars 28b, and the third contact pillars 28c.

As shown in fig. 13H and 13I, a chemical mechanical polishing (Chemical Mechanical Polishing, abbreviated as CMP) process may be used to polish portions of the sacrificial layer 30, the protective layer 29, and the side of the second dielectric layer 26 that is away from the resist layer 24 to expose ends of the first contact pillars 28a and the second contact pillars 28b that are away from the resist layer 24, and ends of the third contact pillars 28c that are away from the first conductive patterns 22.

As shown in fig. 13J, a second conductive pattern P1, a third conductive pattern P2 and a fourth conductive pattern P3 are formed on the side of the second dielectric layer 26 away from the resistive layer 24, the second conductive pattern P1 is electrically connected to the ends of the plurality of first contact pillars 28a away from the resistive layer 24, the third conductive pattern P2 is electrically connected to the ends of the plurality of second contact pillars 28b away from the resistive layer 24, and the fourth conductive pattern P3 is electrically connected to the ends of the third contact pillars 28c away from the first conductive pattern 22.

In the above embodiment of the present application, the plurality of first contact pillars 28a and the plurality of second contact pillars 28b are disposed in the resistance matching area A1, which is favorable for improving the uniformity of intensity of the surface of the resistance matching area A1, so as to improve the uniformity of surface grinding of the resistance matching area A1, avoid the top of the first contact pillars 28a and the second contact pillars 28b from generating "dishing" damage, and ensure that the top surfaces of the first contact pillars 28a and the second contact pillars 28b are flat and completely exposed, so that after the conductive patterns are formed above the first contact pillars 28a and the second contact pillars 28b, the conductive patterns are favorable for being in stable contact with the first contact pillars 28a and the second contact pillars 28b.

In addition, since the third contact post 28c has a shape similar to a rivet, if the polishing liquid permeates along the gap between the third contact post 28c and the sidewall of the third contact hole H3 during the polishing process, the "nut" of the third contact post 28c can play a role of blocking the polishing liquid, so as to prevent the polishing liquid from contacting and corroding the first conductive pattern 22.

In the chip 10 and the method for manufacturing the same according to some embodiments of the present application, a plurality of columnar first contact pillars 28a are electrically connected to the first end 24a of the resistive layer 24, and a plurality of columnar second contact pillars 28b are electrically connected to the second end 24b of the resistive layer 24. Based on this, in the process of manufacturing the chip 10, a plurality of first contact holes for forming the first contact pillars 28a and a plurality of second contact holes for forming the second contact pillars 28b need to be formed in the dielectric layer.

In the embodiment of the application, the first contact hole and the second contact hole are in a hole shape, compared with the contact hole in a long groove shape, the opening area of the first contact hole and the opening area of the second contact hole are reduced, so that the etching depth of the first contact hole and the etching depth of the second contact hole are easy to control in the process of etching the dielectric layer, the etching is controlled to stop on the surface of the resistance matching layer 24, the volume of the resistance matching layer 24 is prevented from being reduced due to over etching, and the accuracy of the resistance matching layer 24 is ensured.

The electronic device 1 provided in some embodiments of the present application includes the chip 10 provided in any of the above embodiments, and the advantages achieved by the chip 10 may be referred to as the advantages of the chip 10 above, which are not described herein.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip, comprising:

the resistance matching layer comprises a first end and a second end; the first end and the second end are opposite ends of the resistance matching layer along a first direction, and the first direction is parallel to the extension surface of the resistance matching layer;

At least one dielectric layer arranged on the resistance matching layer;

the first contact pillars penetrate through the at least one dielectric layer and are electrically connected with the first end, and the second contact pillars penetrate through the at least one dielectric layer and are electrically connected with the second end.

2. The chip of claim 1, wherein the chip comprises a plurality of chips,

the first contact columns are arranged in an array mode; and/or the number of the groups of groups,

the plurality of second contact columns are arranged in an array mode.

3. The chip of claim 2, wherein the chip comprises a plurality of chips,

the plurality of first contact beams includes a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; and/or the number of the groups of groups,

the plurality of second contact beams includes a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction.

4. A chip according to claim 2 or 3, characterized in that the spacing between adjacent two first contact pillars in the first direction is equal to the spacing between adjacent two first contact pillars in the second direction; the first direction intersects the second direction; and/or the number of the groups of groups,

The spacing between two adjacent second contact columns along the first direction is equal to the spacing between two adjacent second contact columns along the second direction; the first direction intersects the second direction.

5. The chip according to any one of claim 1 to 4, wherein,

the radial dimension of the first contact column along the first direction is a first dimension, the radial dimension of the first contact column along the second direction is a second dimension, and the first dimension is equal to the second dimension; the first direction intersects the second direction; and/or the number of the groups of groups,

the radial dimension of the second contact column along the first direction is a third dimension, the radial dimension of the second contact column along the second direction is a fourth dimension, and the third dimension is equal to the fourth dimension; the first direction intersects the second direction.

6. The chip according to any one of claim 1 to 5, wherein,

the plurality of first contact beams includes a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; the column number range of the plurality of first contact columns is 2-20, and the column number range of the plurality of first contact columns is 1-20; and/or the number of the groups of groups,

The plurality of second contact beams includes a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, the first direction intersecting the second direction; the number of columns of the plurality of second contact columns ranges from 2 to 20, and the number of rows of the plurality of second contact columns ranges from 1 to 20.

7. The chip according to any one of claim 1 to 6, wherein,

the shape of the first contact column is one of a quadrangular prism, a quadrangular frustum, a cylinder and a circular truncated cone; and/or the number of the groups of groups,

the shape of the second contact column is one of a quadrangular prism, a quadrangular frustum, a cylinder and a round table.

8. The chip of any one of claims 1 to 7, wherein at least one dielectric layer comprises a first dielectric layer and a second dielectric layer arranged in a stack;

the chip further comprises a second conductive pattern and a third conductive pattern, wherein the second conductive pattern is arranged on one side, far away from the resistance matching layer, of the second dielectric layer, and one ends, far away from the resistance matching layer, of the plurality of first contact posts are electrically connected with the second conductive pattern;

the third conductive patterns are arranged on one side, far away from the resistance matching layer, of the second dielectric layer, and one ends, far away from the resistance matching layer, of the second contact columns are electrically connected with the third conductive patterns.

9. The chip of claim 8, wherein the chip comprises a resistive region and a device region, the resistive layer and the first dielectric layer are located in the resistive region, and the second dielectric layer is located in the resistive region and the device region;

the chip further includes:

a first conductive pattern located in the device region;

the third dielectric layer is arranged on the first conductive pattern and is positioned in the resistance matching area and the device area; the third dielectric layer is positioned on one side of the second dielectric layer close to the first conductive pattern;

and a third contact post penetrating the second dielectric layer and the third dielectric layer and having one end electrically connected to the first conductive pattern.

10. The chip of claim 9, wherein the first contact stud, the second contact stud, and the third contact stud are the same material.

11. The chip according to claim 9 or 10, further comprising:

the fourth conductive pattern is arranged on one side of the second dielectric layer away from the first conductive pattern; one end of the third contact post far away from the first conductive pattern is electrically connected with the fourth conductive pattern.

12. A method of manufacturing a chip, comprising:

forming a resistance matching layer and at least one dielectric layer, wherein the at least one dielectric layer is positioned on the resistance matching layer; the resistance matching layer comprises a first end and a second end, wherein the first end and the second end are opposite ends of the resistance matching layer along a first direction;

forming a plurality of first contact holes and a plurality of second contact holes in the at least one dielectric layer, wherein the first contact holes expose the first end, and the second contact holes expose the second end;

forming a first contact post in the first contact hole and forming a second contact post in the second contact hole; the first contact stud is electrically connected to the first end and the second contact stud is electrically connected to the second end.

13. The method of manufacturing according to claim 12, wherein the chip comprises a resistive matching region and a device region;

the forming of the resistance matching layer and the at least one dielectric layer comprises the following steps:

sequentially forming a resistance matching film and a first dielectric film;

removing the part of the first dielectric film outside the resistance matching region and the part of the resistance matching film outside the resistance matching region to form the resistance matching layer and a first dielectric layer covering the resistance matching layer;

And forming a second dielectric layer, wherein the second dielectric layer is positioned at the resistance matching region and the device region and is positioned at one side of the first dielectric layer far away from the resistance matching layer.

14. The method of claim 12 or 13, further comprising, prior to forming the resistive layer and the at least one dielectric layer:

and sequentially forming a first conductive pattern and a third dielectric layer, wherein the first conductive pattern is positioned in the device region, and the third dielectric layer is positioned in the resistance matching region and the device region.

15. The method of manufacturing according to claim 14, wherein the forming a plurality of first contact holes and a plurality of second contact holes comprises:

etching the second dielectric layer and the first dielectric layer to form a plurality of first contact holes and a plurality of second contact holes;

in the process of etching the second dielectric layer and the first dielectric layer, the second dielectric layer and the third dielectric layer are also etched to form a third contact hole; the third contact hole exposes the first conductive pattern.

16. The method of manufacturing according to claim 15, further comprising, after the forming of the third contact hole:

etching the first conductive pattern through the bottom of the third contact hole to form a cavity in the first conductive pattern; the third contact hole comprises an opening connected with the cavity, and the orthographic projection of the opening on the first conductive pattern is positioned in the orthographic projection range of the cavity on the first conductive pattern.

17. The method of claim 15 or 16, wherein a selective deposition process is used to form a first contact stud in the first contact hole and a third contact stud in the third contact hole during the formation of a second contact stud in the second contact hole;

the third contact pillars are electrically connected to the first conductive pattern.

18. The method of any one of claims 12 to 17, further comprising, after the forming the first contact pillars and the second contact pillars:

and carrying out ion implantation on the at least one dielectric layer.

19. The method of any one of claims 12 to 18, further comprising, after the forming the first contact pillars and the second contact pillars:

forming a protective layer and a sacrificial layer in sequence, wherein the protective layer and the sacrificial layer cover the at least one dielectric layer, the first contact column and the second contact column;

and grinding the sacrificial layer, the protective layer and the part of one side, away from the resistance matching layer, of the at least one dielectric layer to expose the ends, away from the resistance matching layer, of the first contact column and the second contact column.

20. An electronic device, comprising:

the chip of any one of claims 1 to 11;

and the circuit board is electrically connected with the chip.