CN209544306U - Unit contact structures and memory - Google Patents
Unit contact structures and memory Download PDFInfo
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- CN209544306U CN209544306U CN201920570982.6U CN201920570982U CN209544306U CN 209544306 U CN209544306 U CN 209544306U CN 201920570982 U CN201920570982 U CN 201920570982U CN 209544306 U CN209544306 U CN 209544306U
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- 230000015654 memory Effects 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 239000000463 material Substances 0.000 claims description 31
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910018999 CoSi2 Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 239000010936 titanium Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000012774 insulation material Substances 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000011435 rock Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The disclosure is directed to a kind of unit contact structures and memories.The unit contact structures include substrate, dielectric layer, semiconductor layer and conductive layer, and dielectric layer is set on the surface of the substrate, and the dielectric layer includes the unit hole of array-like, substrate described in described hole bottom-exposed；Semiconductor layer is set on the surface of the substrate in described hole, and one side of the semiconductor layer far from the substrate is first surface；Conductive layer is set on the first surface of the semiconductor layer.The unit contact structures that the disclosure provides, the contact resistance in unit contact structures are lower.
Description
Technical field
This disclosure relates to technical field of semiconductors, in particular to a kind of unit contact structures and memory.
Background technique
Dynamic random access memory (DRAM, Dynamic Random Access Memory), because its access speed is fast,
The advantages that storage density is high is widely used in contemporary electronic systems, and basic unit of storage generally includes a capacitor and one
Transistor.
Under normal conditions, each transistor in dynamic random access memory include a grid, one in the substrate
Drain electrode and one with the source electrode that separates of drain electrode.Grid is usually electrically connected with a wordline, and drain electrode usually electrically connects with a bit line
It connects, source electrode usually passes through a unit contact structures (Cell Contact) and a capacitor is electrically connected.
With the Highgrade integration of semiconductor devices, the size of dynamic random access memory is smaller and smaller, unit contact
Size also with diminution, therefore the problem of the contact resistance for producing dynamic random access memory becomes larger.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of lower unit contact structures of contact resistance.
According to one aspect of the disclosure, a kind of unit contact structures are provided.The unit contact structures include:
Substrate；
Dielectric layer, on the surface of the substrate, the dielectric layer includes the unit hole of array-like, described hole bottom
Portion's exposure substrate；
Semiconductor layer, on the surface of the substrate in described hole, the semiconductor layer is far from the substrate
It is on one side first surface；
Conductive layer, on the first surface of the semiconductor layer.
In a kind of exemplary embodiment of the disclosure, the conductive layer includes:
First conductive layer, on the first surface of the semiconductor layer；
Second conductive layer, on the surface of first conductive layer far from the substrate.
In a kind of exemplary embodiment of the disclosure, first conductive layer is the second song far from the substrate on one side
Face, second curved surface are matched with the first surface shape；
Second conductive layer is third curved surface far from the substrate on one side, the third curved surface and second curved form
Shape matching.
In a kind of exemplary embodiment of the disclosure, the first surface is the V-arrangement curved surface being recessed towards the substrate.
In a kind of exemplary embodiment of the disclosure, the material of the semiconductor layer includes polysilicon, and described first leads
The material of electric layer includes CoSi2, the material of second conductive layer includes at least one of Ti and TiN.
In a kind of exemplary embodiment of the disclosure, the unit contact structures further include:
Tungsten layer, on surface of the conductive layer far from the substrate.
In a kind of exemplary embodiment of the disclosure, the substrate includes burying gate transistor, described hole bottom position
Corresponding to the source electrode for burying gate transistor
A kind of memory another aspect of the present disclosure provides.The memory includes any of the above-described embodiment
Unit contact structures.
The unit contact structures that the disclosure provides, one side of the semiconductor layer far from substrate is curved surface, therefore, in semiconductor layer
First surface on the contact area that is laminated between the conductive layer of formation and semiconductor layer will increase, thereby reduce conductive layer with
Contact resistance between semiconductor layer is able to ascend the transistor driving electric conduction using the manufacturing method of the unit contact structures
The ability and operating rate of stream, and then can be improved the storage speed of memory.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the flow chart of the manufacturing method for the unit contact structures that a kind of embodiment of the disclosure provides；
Fig. 2 is the flow chart of the manufacturing method for the unit contact structures that another embodiment of the disclosure provides；
Fig. 3-Fig. 7 is the process sequence figure for indicating the manufacturing method of unit contact structures of the disclosure；
Fig. 8 is the schematic diagram for the unit contact structures that a kind of embodiment of the disclosure provides.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used
Method, step etc..In other cases, known solution is not shown in detail or describes to avoid a presumptuous guest usurps the role of the host and makes the disclosure
Various aspects thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note indicates same or similar part, thus will omit repetition thereof.Some block diagrams shown in the drawings are function
Energy entity, not necessarily must be corresponding with physically or logically independent entity.These function can be realized using software form
Energy entity, or these functional entitys are realized in one or more hardware modules or integrated circuit, or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
Term "one", " one ", "the" and " described " to indicate there are one or more elements/component part/etc.；With
Language " comprising " and " having " is to indicate the open meaning being included and refer to element/composition portion in addition to listing
Also may be present except divide/waiting other element/component part/etc.；Term " first ", " second " and " third " etc. are only as marking
It uses, is not the quantity limitation to its object.
A kind of manufacturing method of unit contact structures is provided firstly in this example embodiment.As shown in Figure 1, the manufacture
Method includes:
Step S100, dielectric layer is formed on the substrate, forms the unit hole of array-like in the dielectric layer, hole bottom is sudden and violent
Reveal substrate；
Step S200, semiconductor layer is formed on the surface of the substrate in hole, one side of the semiconductor layer far from substrate is
First surface；
Step S300, conductive layer is formed on the first surface of semiconductor layer.
The manufacturing method for the unit contact structures that the disclosure provides, one side of the semiconductor layer far from substrate is curved surface, therefore,
The contact area being laminated between the conductive layer of formation and semiconductor layer on the first surface of semiconductor layer will increase, and then reduce
Contact resistance between conductive layer and semiconductor layer, is able to ascend the transistor of the manufacturing method using the unit contact structures
Drive the ability and operating rate of conducting electric current.
In the following, each step of the manufacturing method to the unit contact structures in this example embodiment is carried out further
Explanation.
In the step s 100, dielectric layer is formed on the substrate, forms the unit hole of array-like, hole bottom in the dielectric layer
Portion's exposure substrate, including step S110- step S130:
Step S110, a substrate is provided.
Specifically, it as shown in figure 3, substrate 10 can be silicon substrate, or can be made of other semiconductor materials or wafer.Substrate
10 are formed with and bury gate transistor, and (STI, the shallow trench of Shallow trench isolation structure 101 is formed under the upper surface of substrate 10
Isolation), multiple ditching type gate structures 102, between Shallow trench isolation structure 101 and ditching type gate structure 102
Source electrode 103103, the drain electrode 104 between two ditching type gate structures 102.Wherein, each ditching type gate structure 102
Include cap rock 1021, the conductive part 1022 under cap rock 1021 exposed from 10 surface of substrate, and is coated on cap rock
1021 with the gate dielectric 1023 of 1022 outer surface of conductive part, cap rock 1021 may include silicon oxide or silicon nitride, conductive part
1022 can be to include titanium nitride or tungsten；Hole bottom position corresponds to the source electrode 103 for burying gate transistor.
Step S120, dielectric layer is formed on the substrate, forms the unit hole of array-like in the dielectric layer.
As shown in figure 4, dielectric layer includes forming multiple interval pre-determined distances on the upper surface of semiconductor substrate to be arranged
First projective structure 20.First projective structure 20 includes being set to silicon positioned at the siliceous lower position 201 of 10 upper surface of substrate, stacking
Metal position 202 on upper surface of the matter lower position 201 far from substrate 10, and be located at 202 top of metal position and cover
The insulating layer 203 of siliceous lower position 201 and the side wall at metal position 202, insulating layer 203 can be nitride layer, such as nitrogenize
Silicon.Wherein, stacking be set to siliceous upper surface of the lower position 201 far from substrate 10 on metal position 202 can be used as dynamic with
Machine accesses the bit line (digit line) in memory.
In one embodiment, silicrete and metal layer are sequentially formed by depositing operation in the upper surface of substrate 10, then
Multiple siliceous lower positions 201 being stacked and metal position 202 are formed by mask photolithographic process, then deposit insulation material
Material is formed by mask photolithographic process herein and is located at 202 top of metal position and covers siliceous lower position 201 and metal position
The insulating layer 203 of 202 side wall.
Step S130, multiple second projective structures, the first projective structure and the second protrusion are formed on the upper surface of the substrate
Structure is arranged alternately, and forms hole between the first projective structure and the second projective structure.
Specifically, as shown in Figure 4 and Figure 5, the upper surface of covering substrate 10 and the insulation of insulating layer 203 are formed by deposition
Material layer 50 planarizes the upper surface of insulation material layer 50, then by mask photolithographic process in insulation material layer 50
The upper surface of substrate 10 is exposed in hole of the upper formation between the first projective structure 20, the bottom of hole, then cvd nitride
Object material makes nitride material be filled up completely hole, then removes the nitride material of 50 upper surface of insulation material layer, only remains
Oxymtride material in hole then removes insulation material layer 50, and the oxymtride material in hole is made to form the second protrusion
Structure 30, the first projective structure 20 are arranged alternately with the second projective structure 30, the first projective structure 20 and the second projective structure 30
Between form hole.
In step s 200, form semiconductor layer on the surface of the substrate in hole, semiconductor layer far from substrate one
Face is first surface, including step S210 and step S220:
Step S210, deposited semiconductor material in the hole between the first projective structure 20 and the second projective structure 30,
Semiconductor material at least coverage hole side wall and bottom.
Specifically, as shown in fig. 6, due to the hole between the first projective structure 20 and the second projective structure 30 depth-to-width ratio
Larger, i.e. the width of hole is smaller, in the deposited semiconductor material into hole, has between the semiconductor material on hole sidewalls
There is certain gap.Wherein, semiconductor material can be polysilicon, and the setting of semiconductor layer can be avoided metal to monocrystalline silicon table
The damage in face.
Step S220, semiconductor material carve, to form the semiconductor layer with first surface.
Specifically, as shown in fig. 7, passing through back the partial semiconductor material carved on the side wall in removal hole, hole is remained
The semiconductor material of bottom deposit, and the semiconductor material of gap bottom periphery is performed etching, to expand the width of gap bottom
Degree, keeps first surface of the semiconductor layer 401 far from 10 one side of substrate V-shaped or U-shaped.It will be apparent to those skilled in the art that from
The one side wall of hole, which first gradually decreases curved surface that is rear and gradually rising to the height of opposite another side wall, can be understood as V-arrangement
Or U-shaped.
Wherein, the formation of 401 first surface of semiconductor layer, is utilized in the deposited semiconductor material into hole, hole
The difficulty of the formation of first surface inherently is reduced with the characteristic in certain gap between semiconductor material on side wall,
Thereby reduce the difficulty of the manufacturing process of unit contact structures.
In another embodiment, first surface can be the curved surface of continuous bend, such as W-shaped, can etch work by orientation
Skill forms the curved surface.The disclosure to the specific shape of first surface with no restriction, those skilled in the art can as needed into
Row design.
In step S300, conductive layer is formed on the first surface of semiconductor layer.
Specifically, it using self-registered technology (Self align), sinks on the first surface of the semiconductor layer 401 in hole
Product layer of conductive material, with shape conductive layer.The conductive layer can be high melting point metal materials, high melting point metal materials can for Co, Ti,
The materials such as Ni or alloy material containing it.
Since the contact surface of semiconductor layer 401 and conductive layer is curved surface, semiconductor layer 401 and conductive layer contact face are increased
Area, and then can guarantee when aperture width is smaller good electric conductivity between semiconductor layer 401 and conductive layer.In addition,
Since the contact surface of semiconductor layer 401 and conductive layer is curved surface, so that surface of the conductive layer far from substrate 10 is also and the first song
The same or similar curved surface of face shape.
In implementing one, as shown in figure 8, conductive layer includes the first conduction on the first surface of semiconductor layer 401
Layer 402, and the second conductive layer 403 on the first surface of the conductive layer 402 far from substrate 10.In addition, conductive layer may be used also
Including third conductive layer or more, the disclosure to this with no restriction.Wherein, the material of the first conductive layer includes CoSi2,
The material of second conductive layer includes at least one of Ti and TiN, but is not limited only to this.CoSi can reduce contact resistance, Ti or
TiN is conducive to adherency and stops.
Specifically, the first conductive layer 402 is the second curved surface, the second curved surface and first surface shape far from 10 one side of substrate
Match；Second conductive layer 403 is third curved surface far from 10 one side of substrate, and third curved surface is matched with the second curve form, i.e., second is bent
The shape in face is identical or approximately uniform as first surface shape, and the shape of third curved surface is identical or close as the shape of the second curved surface
Patibhaga-nimitta is same.
In one embodiment, as shown in Fig. 2, the manufacturing method for the unit contact structures that the disclosure provides further include:
Step S400, on surface of the conductive layer far from substrate, stacking forms tungsten layer.
Following is structure of the invention embodiment, can be obtained with inventive method embodiment.For in structure of the invention embodiment
Undisclosed details, please refers to embodiment of the present invention method.
The disclosure additionally provides a kind of unit contact structures, as shown in figure 8, the unit contact structures include substrate 10, are situated between
Matter layer, semiconductor layer 401 and conductive layer.Dielectric layer is set on the surface of substrate 10, and dielectric layer includes the unit hole of array-like,
Hole bottom-exposed substrate 10.Semiconductor layer 401 be set to hole in substrate 10 surface on, semiconductor layer far from substrate one
Face is first surface.Conductive layer is set on the first surface of semiconductor layer 401.Wherein, conductive layer can be high melting point metal materials,
High melting point metal materials can be materials or the alloy materials containing it such as Co, Ti, Ni.
The unit contact structures that the disclosure provides, one side of the semiconductor layer 401 far from substrate 10 is curved surface, therefore, half
The contact area being laminated between the conductive layer of formation and semiconductor layer 401 on the first surface of conductor layer 401 will increase, and then drop
Low contact resistance between conductive layer and semiconductor layer 401 is able to ascend the manufacturing method using the unit contact structures
The ability and operating rate of transistor driving conducting electric current.
Specifically, as shown in figure 8, dielectric layer includes being alternately disposed at the first projective structure 20 and the second protrusion on substrate 10
Structure 30, hole is between the first projective structure 20 and the second projective structure 30.
Conductive layer includes the first conductive layer 402 and the second conductive layer 403.The stacking of first conductive layer 402 is set to semiconductor layer
On 401 first surface, the stacking of the second conductive layer 403 is set on the first surface of the conductive layer 402 far from substrate 10.In addition, leading
Electric layer may also include third conductive layer or more, the disclosure to this with no restriction.
Wherein, the first conductive layer 402 is the second curved surface, the second curved surface and first surface shape far from 10 one side of substrate
Match；Second conductive layer 403 is third curved surface far from 10 one side of substrate, and third curved surface is matched with the second curve form, i.e., second is bent
The shape in face is identical or approximately uniform as first surface shape, and the shape of third curved surface is identical or close as the shape of the second curved surface
Patibhaga-nimitta is same.
First surface is V-shaped or U-shaped, it will be apparent to those skilled in the art that from the one side wall of hole to another side wall
Height, which first gradually decreases curved surface that is rear and gradually rising, can be understood as V-arrangement or U-shaped.In another embodiment, first surface
It can be the curved surface of continuous bend, such as W-shaped, the curved surface can be formed by orienting etching technics.The disclosure is to first surface
With no restriction, those skilled in the art can be designed specific shape as needed.
Wherein, semiconductor layer 401 can be polycrystalline silicon material, and the material of the first conductive layer includes CoSi2, the second conductive layer
Material includes at least one of Ti and TiN, but is not limited only to this.The setting of semiconductor layer can be avoided metal to monocrystalline silicon surface
Damage, CoSi can reduce contact resistance, and Ti or TiN are conducive to adherency and stop.
In one embodiment, as shown in figure 8, the unit contact structures that the disclosure provides further include tungsten layer 404.The tungsten layer
404 stackings are set on surface of the conductive layer far from substrate 10.
The disclosure additionally provides a kind of memory.The memory includes above-mentioned unit contact structures, can be improved storage
The storage speed of device, memory can be dynamic random access memory, can be applied to mobile phone, tablet computer, laptop,
In the electronic equipments such as server, more beneficial effects can refer to the beneficial effect of said units contact structures, herein no longer
It repeats.
In addition, it will be apparent to those skilled in the art that using said units contact structures semiconductor devices, also should belong to
In the protection scope of the disclosure.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (8)
1. a kind of unit contact structures characterized by comprising
Substrate；
Dielectric layer, on the surface of the substrate, the dielectric layer includes the unit hole of array-like, and described hole bottom is sudden and violent
Reveal the substrate；
Semiconductor layer, on the surface of the substrate in described hole, one side of the semiconductor layer far from the substrate
For first surface；
Conductive layer, on the first surface of the semiconductor layer.
2. unit contact structures according to claim 1, which is characterized in that the conductive layer includes:
First conductive layer, on the first surface of the semiconductor layer；
Second conductive layer, on the surface of first conductive layer far from the substrate.
3. unit contact structures according to claim 2, which is characterized in that first conductive layer is far from the substrate one
Face is the second curved surface, and second curved surface is matched with the first surface shape；
Second conductive layer is third curved surface far from the substrate on one side, the third curved surface and second curve form
Match.
4. unit contact structures according to claim 1, which is characterized in that the first surface is recessed towards the substrate
Sunken V-arrangement curved surface.
5. unit contact structures according to claim 2, which is characterized in that the material of the semiconductor layer includes polycrystalline
The material of silicon, first conductive layer includes CoSi2, the material of second conductive layer includes at least one of Ti and TiN.
6. unit contact structures according to claim 1, which is characterized in that the unit contact structures further include:
Tungsten layer, on surface of the conductive layer far from the substrate.
7. unit contact structures according to claim 1, which is characterized in that the substrate includes burying gate transistor, described
Hole bottom position corresponds to the source electrode for burying gate transistor.
8. a kind of memory, which is characterized in that including the described in any item unit contact structures of claim 1-7.
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| CN201920570982.6U CN209544306U (en) | 2019-04-24 | 2019-04-24 | Unit contact structures and memory |
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| CN201920570982.6U CN209544306U (en) | 2019-04-24 | 2019-04-24 | Unit contact structures and memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863726A (en) * | 2019-04-24 | 2020-10-30 | 长鑫存储技术有限公司 | Memory, cell contact structure and manufacturing method thereof |
| US11723207B2 (en) | 2021-08-27 | 2023-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip with a gate structure disposed within a trench |
-
2019
- 2019-04-24 CN CN201920570982.6U patent/CN209544306U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863726A (en) * | 2019-04-24 | 2020-10-30 | 长鑫存储技术有限公司 | Memory, cell contact structure and manufacturing method thereof |
| US11723207B2 (en) | 2021-08-27 | 2023-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip with a gate structure disposed within a trench |
| TWI838683B (en) * | 2021-08-27 | 2024-04-11 | 台灣積體電路製造股份有限公司 | Integrated chip with a gate structure disposed within a trench and method for forming the same |
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