WO2024031815A1 - 灵敏放大器、控制方法及半导体存储器 - Google Patents

灵敏放大器、控制方法及半导体存储器 Download PDF

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Publication number
WO2024031815A1
WO2024031815A1 PCT/CN2022/123952 CN2022123952W WO2024031815A1 WO 2024031815 A1 WO2024031815 A1 WO 2024031815A1 CN 2022123952 W CN2022123952 W CN 2022123952W WO 2024031815 A1 WO2024031815 A1 WO 2024031815A1
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Prior art keywords
type transistor
gate
bit line
switch unit
drain
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PCT/CN2022/123952
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English (en)
French (fr)
Inventor
董平
李韶
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

Definitions

  • the present disclosure relates to, but is not limited to, a sense amplifier, a control method and a semiconductor memory.
  • the sense amplifier plays an important role in the normal operation of the semiconductor memory. It completes the data reading operation by amplifying the voltage difference between the target bit line and the complementary bit line. .
  • the problem of incomplete matching of transistors will be caused by the introduction of manufacturing defects, which may cause incorrect amplification of the sensitive amplifier and cause data reading errors.
  • An embodiment of the present disclosure provides a sensitive amplifier, including: a sensing module and a balancing module;
  • the sensing module is connected to the bit line and the complementary bit line, and the balancing module is connected to the bit line and the complementary bit line;
  • the balancing module drives the bit line and the complementary bit line to the precharge voltage during the precharge phase; the sensing module is used to generate the compensation voltage on the bit line and the complementary bit line during the offset elimination phase; and adjusts the bit line during the forward driving phase.
  • the compensation voltage on the line and the complementary bit line controls charge sharing between the memory cell and the bit line during the charge sharing stage, and amplifies the voltage difference between the bit line and the complementary bit line during the sensing amplification stage.
  • the sensing module includes: a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor;
  • the gate of the first P-type transistor is connected to the first end of the fifth switching unit, the gate is also connected to the first end of the sixth switching unit, the drain is connected to the drain of the first N-type transistor, and the source is connected to The first power terminal;
  • the gate of the second P-type transistor is connected to the second end of the fifth switching unit, the gate is also connected to the first end of the seventh switching unit, the drain is connected to the drain of the second N-type transistor, and the source is connected to the source of the first P-type transistor;
  • the control end of the fifth switch unit receives the second isolation control signal
  • the sixth switch unit has a second end connected to the complementary bit line and a control end that receives the third isolation control signal;
  • the seventh switch unit has a second end connected to the bit line and a control end that receives the third isolation control signal;
  • the gate of the first N-type transistor is connected to the complementary bit line, and the source is connected to the second power terminal;
  • the second N-type transistor has its gate connected to the bit line and its source connected to the source of the first N-type transistor;
  • the first switch unit has a first end connected to the drain of the first N-type transistor, a second end connected to the gate of the first N-type transistor, and a control end thereof to receive the offset cancellation signal;
  • the second switch unit has a first end connected to the gate of the second N-type transistor, a second end connected to the drain of the second N-type transistor, and a control end thereof to receive the offset cancellation signal;
  • the third switch unit has a first terminal connected to the drain of the first N-type transistor, a second terminal connected to the gate of the second P-type transistor, and a control terminal receiving the first isolation control signal;
  • the fourth switch unit has a first terminal connected to the gate of the first P-type transistor, a second terminal connected to the drain of the second N-type transistor, and a control terminal receiving the first isolation control signal.
  • the fifth switch unit includes:
  • the drain or source of the seventh N-type transistor is the first terminal of the fifth switching unit, the source or drain is the second terminal of the fifth switching unit, and its gate is the control terminal of the fifth switching unit, for receiving
  • the second isolation control signal controls whether the gate of the first P-type transistor and the gate of the second P-type transistor are connected according to the second isolation control signal.
  • the sixth switch unit includes:
  • the drain of the eighth N-type transistor is the first terminal of the sixth switching unit, the source is the second terminal of the sixth switching unit, and the gate is the control terminal of the sixth switching unit, and is used to receive the third isolation control signal, Control whether the gate of the first P-type transistor and the complementary bit line are connected according to the third isolation control signal;
  • the seventh switch unit includes:
  • the drain of the ninth N-type transistor is the first terminal of the seventh switch unit, its source is the second terminal of the seventh switch unit, and its gate is the control terminal of the seventh switch unit, and is used to receive the third isolation control signal, Whether the gate electrode and the bit line of the second P-type transistor are connected is controlled according to the third isolation control signal.
  • the first switch unit includes:
  • the drain of the third N-type transistor is the first terminal of the first switch unit, its source is the second terminal of the first switch unit, and its gate is the control terminal of the first switch unit, and is used to receive the offset cancellation signal, according to The offset cancellation signal controls whether the gate and drain of the first N-type transistor are turned on;
  • the second switch unit includes:
  • the source of the fourth N-type transistor is the first terminal of the second switching unit, the drain is the second terminal of the second switching unit, and the gate is the control terminal of the second switching unit, and is used to receive the offset cancellation signal, according to The offset cancellation signal controls whether the gate and drain of the second N-type transistor are turned on.
  • the third switch unit includes:
  • the source or drain of the fifth N-type transistor is the first end of the third switch unit, and its drain or source is the second end of the third switch unit; its gate is the control end of the third switch unit, receiving the first Isolating the control signal, the fifth N-type transistor and the ninth N-type transistor jointly control whether the drain and bit line of the first N-type transistor are connected;
  • the fourth switch unit includes:
  • the source or drain of the sixth N-type transistor is the first end of the fourth switching unit, its drain or source is the second end of the fourth switching unit, and its gate is the control end of the fourth switching unit, receiving the first Isolating the control signal, the sixth N-type transistor and the eighth N-type transistor jointly control whether the drain of the second N-type transistor and the complementary bit line are connected.
  • the equalization module includes:
  • the tenth N-type transistor has a first end connected to the bit line, a second end connected to the first end of the eleventh N-type transistor and a charging power supply end, and its gate receives a precharge signal;
  • the eleventh N-type transistor has a second end connected to the complementary bit line and a gate connected to the gate of the tenth N-type transistor;
  • the twelfth N-type transistor has a first end connected to the bit line, a second end connected to the complementary bit line, and a gate electrode connected to the gate electrode of the tenth N-type transistor.
  • An embodiment of the present disclosure also provides a control method for a sense amplifier.
  • the sense amplifier includes a sensing module and a balancing module.
  • the working stages of the sense amplifier include a precharge stage, an offset elimination stage, a forward driving stage, a charge sharing stage, and a sensing stage.
  • Measurement amplification stage; methods include:
  • the voltage of the control equalization module driving the bit line and the complementary bit line during the precharge stage is both the precharge voltage
  • controlling the sensing module to generate compensation voltages on the bit lines and complementary bit lines during the offset cancellation phase
  • Control the sensing module to adjust the compensation voltage of the bit line and the complementary bit line during the forward driving stage
  • the memory cell and the bit line are controlled to share charge
  • the sensing module is controlled to amplify the voltage difference between the bit line and the complementary bit line during the sensing amplification stage.
  • the sensing module includes:
  • the gate of the first P-type transistor is connected to the first end of the fifth switching unit, the gate of the first P-type transistor is also connected to the first end of the sixth switching unit, and the drain of the first P-type transistor is connected to the first N-type The drain of the transistor and the source of the first P-type transistor are connected to the first power terminal;
  • the gate of the second P-type transistor is connected to the second end of the fifth switching unit, the gate of the second P-type transistor is also connected to the first end of the seventh switching unit, and the drain of the second P-type transistor is connected to the second N-type The drain of the transistor and the source of the second P-type transistor are connected to the source of the first P-type transistor;
  • the control end of the fifth switch unit receives the second isolation control signal
  • the second end of the sixth switch unit is connected to the complementary bit line, and the control end of the sixth switch unit receives the third isolation control signal;
  • the second end of the seventh switch unit is connected to the bit line, and the control end of the seventh switch unit receives the third isolation control signal. control signal;
  • the gate of the first N-type transistor is connected to the complementary bit line, and the source of the first N-type transistor is connected to the second power terminal;
  • the gate of the second N-type transistor is connected to the bit line, and the source of the second N-type transistor is connected to the source of the first N-type transistor;
  • the first end of the first switch unit is connected to the drain of the first N-type transistor, the second end of the first switch unit is connected to the gate of the first N-type transistor, and the control end of the first switch unit receives the offset cancellation signal;
  • the first end of the second switch unit is connected to the gate of the second N-type transistor, the second end of the second switch unit is connected to the drain of the second N-type transistor, and the control end of the second switch unit receives the offset cancellation signal;
  • the first end of the third switch unit is connected to the drain of the first N-type transistor, the second end of the third switch unit is connected to the gate of the second P-type transistor, and the control end of the third switch unit receives the first isolation control signal;
  • the first end of the fourth switch unit is connected to the gate of the first P-type transistor, the second end of the fourth switch unit is connected to the drain of the second N-type transistor, and the control end of the fourth switch unit receives the first isolation control signal;
  • the control sensing module generates compensation voltages on the bit lines and complementary bit lines during the offset elimination phase, including:
  • the voltage of the first power supply terminal is controlled to be the power supply voltage
  • the voltage of the second power supply terminal is controlled to be the ground voltage
  • the transistor in the memory unit is controlled to be turned off
  • Control the equalization module to stop driving the bit line and the complementary bit line control the first switch unit to connect the gate and drain of the first N-type transistor, and control the second switch unit to connect the gate and drain of the second N-type transistor.
  • the third switching unit is controlled to disconnect the drain of the first N-type transistor from the gate of the second P-type transistor
  • the fourth switching unit is controlled to disconnect the drain of the second N-type transistor from the gate of the first P-type transistor.
  • the fifth switching unit is controlled to disconnect the gate of the first P-type transistor from the gate of the second P-type transistor
  • the sixth switching unit is controlled to connect the gate of the first P-type transistor to the complementary bit line.
  • controlling the seventh switch unit to connect the gate of the second P-type transistor to the bit line.
  • control sensing module adjusts the compensation voltage on the bit line and the complementary bit line during the forward driving stage, specifically including:
  • the voltage of the first power supply terminal is controlled to be the power supply voltage
  • the voltage of the second power supply terminal is controlled to be the ground voltage
  • the transistor in the memory unit is controlled to be turned off
  • Control the equalization module to stop driving the bit line and the complementary bit line control the first switch unit to connect the gate and drain of the first N-type transistor, and control the second switch unit to connect the gate and drain of the second N-type transistor.
  • the third switching unit is controlled to disconnect the drain of the first N-type transistor from the gate of the second P-type transistor
  • the fourth switching unit is controlled to disconnect the drain of the second N-type transistor from the gate of the first P-type transistor.
  • the fifth switching unit is controlled to connect the gate of the first P-type transistor with the gate of the second P-type transistor
  • the sixth switching unit is controlled to disconnect the gate of the first P-type transistor from the complementary bit line.
  • controlling the seventh switch unit to disconnect the gate of the second P-type transistor from the bit line.
  • controlling the memory cell and the bit line to share charge during the charge sharing stage specifically includes:
  • the voltage of the first power supply terminal and the voltage of the second power supply terminal are controlled to be the precharge voltage; the transistor in the memory unit is controlled to be turned on;
  • Control the equalization module to stop driving the bit line and the complementary bit line control the first switching unit to disconnect the gate and drain of the first N-type transistor, and control the second switching unit to disconnect the gate and drain of the second N-type transistor.
  • the third switching unit is controlled to connect the drain of the first N-type transistor and the gate of the second P-type transistor
  • the fourth switching unit is controlled to connect the drain of the second N-type transistor and the gate of the first P-type transistor.
  • the fifth switching unit is controlled to disconnect the gate of the first P-type transistor from the gate of the second P-type transistor
  • the sixth switching unit is controlled to connect the gate of the first P-type transistor to the complementary bit line.
  • controlling the seventh switch unit to connect the gate of the second P-type transistor to the bit line.
  • the sensing module is controlled to amplify the voltage difference between the bit line and the complementary bit line during the sensing amplification stage, specifically including:
  • the voltage of the first power supply terminal is controlled to be the power supply voltage, and the voltage of the second power supply terminal is controlled to be the ground voltage; the transistor in the memory unit is controlled to be turned on;
  • Control the equalization module to stop driving the bit line and the complementary bit line control the first switching unit to disconnect the gate and drain of the first N-type transistor, and control the second switching unit to disconnect the gate and drain of the second N-type transistor.
  • the third switching unit is controlled to connect the drain of the first N-type transistor and the gate of the second P-type transistor
  • the fourth switching unit is controlled to connect the drain of the second N-type transistor and the gate of the first P-type transistor.
  • the fifth switching unit is controlled to disconnect the gate of the first P-type transistor from the gate of the second P-type transistor
  • the sixth switching unit is controlled to connect the gate of the first P-type transistor to the complementary bit line.
  • controlling the seventh switch unit to connect the gate of the second P-type transistor to the bit line.
  • the balancing module includes a tenth N-type transistor, an eleventh N-type transistor, and a twelfth N-type transistor;
  • the first terminal of the tenth N-type transistor is connected to the bit line
  • the second terminal of the tenth N-type transistor is connected to the first terminal of the eleventh N-type transistor and is connected to the charging power supply terminal
  • the gate of the tenth N-type transistor receives precharge. Signal
  • the second terminal of the eleventh N-type transistor is connected to the complementary bit line, and the gate of the eleventh N-type transistor is connected to the gate of the tenth N-type transistor; the first terminal of the twelfth N-type transistor is connected to the bit line, and the gate of the eleventh N-type transistor is connected to the complementary bit line.
  • the second ends of the two N-type transistors are connected to the complementary bit lines, and the gate electrode of the twelfth N-type transistor is connected to the gate electrode of the tenth N-type transistor;
  • the voltages of the driven bit lines and complementary bit lines of the equalization module are both precharge voltages, including:
  • the first switching unit is controlled to disconnect the gate and drain of the first N-type transistor
  • the second switching unit is controlled to disconnect the gate and drain of the second N-type transistor
  • the third switching unit is controlled to disconnect the first N-type transistor.
  • the drain of the transistor is connected to the gate of the second P-type transistor
  • the fourth switch unit is controlled to connect the drain of the second N-type transistor to the gate of the first P-type transistor
  • the fifth switch unit is controlled to connect the first P-type transistor to the drain of the second N-type transistor.
  • the gate of the P-type transistor is disconnected from the gate of the second P-type transistor
  • the sixth switching unit is controlled to connect the gate of the first P-type transistor to the complementary bit line
  • the seventh switching unit is controlled to connect the second P-type transistor.
  • the gate is connected to the bit line.
  • the first switching unit includes a third N-type transistor
  • the second switching unit includes a fourth N-type transistor
  • the third switching unit includes a fifth N-type transistor
  • the fourth switching unit includes a sixth N-type transistor
  • the The fifth switch unit includes a seventh N transistor
  • the sixth switch unit includes an eighth N transistor
  • the seventh switch unit includes a ninth N transistor
  • the precharge signal is high level during the precharge stage, and the precharge signal is low level during the offset elimination stage, forward driving stage, charge sharing stage and sensing amplification stage;
  • the offset cancellation signal is high level during the offset cancellation stage and the forward driving stage, and the offset cancellation signal is low level during the precharge stage, charge sharing stage and sensing amplification stage;
  • the first isolation control signal is low level during the offset elimination stage and the forward driving stage, and the first isolation control signal is high level during the precharge stage, charge sharing stage and sensing amplification stage;
  • the second isolation control signal is high level in the forward driving stage, and the second isolation control signal is low level in the precharge stage, offset elimination stage, charge sharing stage and sensing amplification stage;
  • the third isolation control signal is low level in the forward driving stage, and the third isolation control signal is high level in the precharge stage, offset elimination stage, charge sharing stage and sensing amplification stage.
  • An embodiment of the present disclosure provides a controller for implementing the control method of the sense amplifier involved in the above embodiment.
  • An embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier related to the above embodiment.
  • the present disclosure provides a sensitive amplifier, a control method and a semiconductor memory.
  • the equalization module drives the voltage of the bit line and the complementary bit line to the precharge voltage in the precharge stage, and stops driving the bit line and the complementary bit line in other stages.
  • the sensing module In the offset elimination phase, the sensing module generates compensation voltages on the bit lines and complementary bit lines.
  • the sensing module adjusts the compensation voltages on the bit lines and complementary bit lines.
  • the charge sharing stage the memory cell shares charge with the complementary bit line.
  • the sensing amplification stage the sensing module amplifies the voltage difference between the bit line and the complementary bit line to achieve accurate data reading.
  • Figure 1 is a schematic circuit diagram of a sensitive amplifier
  • Figure 2 is a schematic circuit diagram of a sense amplifier provided by an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of the sense amplifier provided by the embodiment shown in Figure 2;
  • Figure 4 is a schematic diagram of the principle of the sense amplifier in the precharge stage provided by the embodiment shown in Figure 2;
  • FIG. 5 is a schematic diagram of the principle of the sensitive amplifier provided in the offset elimination stage according to the embodiment shown in Figure 2;
  • Figure 6 is a schematic diagram of the principle of the sense amplifier provided by the embodiment shown in Figure 2 in the forward driving stage;
  • Figure 7 is a schematic diagram of the principle of the charge sharing stage of the sensitive amplifier provided by the embodiment shown in Figure 2;
  • FIG. 8 is a schematic diagram of the principle of the sense amplifier provided by the embodiment shown in FIG. 2 in the sensing amplification stage.
  • a sense amplifier includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1 and a second N-type transistor N2.
  • the source of the first P-type transistor P1 is connected to the source of the second P-type transistor P2 and then connected to the first power supply terminal SAP.
  • the voltage of the first power supply terminal SAP is the power supply voltage VDD.
  • the source of the first N-type transistor N1 is connected to the source of the second N-type transistor N2 and then connected to the second power supply terminal SAN.
  • the voltage of the second power supply terminal SAN is the ground voltage VSS.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the drain of the second P-type transistor P2 is connected to the drain of the second N-type transistor N2 and then connected to the bit line BL.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the bit line BL.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the complementary bit line BLB.
  • the memory cell 100 is connected to the bit line BL, and the memory cell 100 is connected to the complementary bit line BLB.
  • the memory cell 100 includes a transistor M1 and a capacitor C1.
  • the sense amplifier is used to read data from the memory cell 100 .
  • the working stages of the sense amplifier include a precharge stage T1, a charge sharing stage T4, a sensing amplification stage T5, and a recovery stage.
  • the equalization module 300 drives the bit line BL and the complementary bit line BLB to the precharge voltage VBLP.
  • the charge sharing stage T4 the transistor M1 in the memory cell 100 connected to the bit line BL is turned on, and the capacitor C1 in the memory cell 100 shares charges with the bit line BL, generating a charge sharing voltage on the bit line BL.
  • the sense amplifier amplifies the voltage difference on the bit line BL and the complementary bit line BLB.
  • the recovery phase the data in the memory cell 100 is recovered, and the data on the bit line BL is read out.
  • the transistors in the sense amplifier will be mismatched due to process changes, temperature, etc. For example, if the transistors in the sense amplifier have different sizes or different threshold voltages, the transistor mismatch will cause mismatch noise and cause data readout. The problem of failure.
  • an embodiment of the present disclosure provides a sense amplifier, a control method and a semiconductor memory.
  • an embodiment of the present disclosure provides a sense amplifier.
  • the sense amplifier includes a sensing module 200 and an equalizing module 300 .
  • the sensing module 200 is connected to the bit line BL and the complementary bit line BLB, and the balancing module 300 is connected to the bit line BL and the complementary bit line BLB.
  • the balancing module 300 drives the voltages of the bit line BL and the complementary bit line BLB to the precharge voltage VBLP.
  • the equalization module 300 stops driving the bit line BL and the complementary bit line BLB.
  • the sensing module 200 generates a compensation voltage on the bit line BL and the complementary bit line BLB.
  • the sensing module 200 adjusts the compensation voltage on the bit line BL and the complementary bit line BLB.
  • the charge sharing stage T4 the memory cell 100 is controlled to share charges with the bit line BL.
  • the sensing amplification stage T5 the sensing module 200 amplifies the voltage difference on the bit line BL and the complementary bit line BLB.
  • the balancing module 300 drives the voltages of the bit line BL and the complementary bit line BLB to the precharge voltage VBLP in the precharge stage T1, and stops driving the bit line BL and the complementary bit line BLB in other stages.
  • the sensing module 200 In the offset elimination phase T2, the sensing module 200 generates a compensation voltage on the bit line BL and the complementary bit line BLB.
  • the sensing module 200 adjusts the compensation voltage on the bit line BL and the complementary bit line BLB.
  • the charge sharing stage T4 the memory cell 100 performs charge sharing with the complementary bit line BLB.
  • the sensing amplification stage T5 the sensing module 200 amplifies the voltage difference between the bit line BL and the complementary bit line BLB to achieve accurate data reading.
  • the sensing module 200 includes: a first switch unit 210, a second switch unit 220, a third switch unit 230, a fourth switch unit 240, a fifth switch unit 250, a sixth The switch unit 260, the seventh switch unit 270, the first P-type transistor P1, the second P-type transistor P2, the first N-type transistor N1 and the second N-type transistor N2.
  • the gate of the first P-type transistor P1 is connected to the first terminal of the fifth switching unit 250 , the gate of the first P-type transistor P1 is also connected to the first terminal of the sixth switching unit 260 , and the drain of the first P-type transistor P1 The drain of the first N-type transistor N1 is connected, and the source of the first P-type transistor P1 is connected with the first power terminal SAP.
  • the gate of the second P-type transistor P2 is connected to the second terminal of the fifth switching unit 250 , the gate of the second P-type transistor P2 is also connected to the first terminal of the seventh switching unit 270 , and the drain of the second P-type transistor P2 The drain of the second N-type transistor N2 is connected, and the source of the second P-type transistor P2 is connected with the source of the first P-type transistor P1.
  • the gate of the first N-type transistor N1 is connected to the complementary bit line BLB, and the source of the first N-type transistor N1 is connected to the second power terminal SAN.
  • the gate of the second N-type transistor N2 is connected to the bit line BL, and the source of the second N-type transistor N2 is connected to the source of the first N-type transistor N1.
  • the control terminal of the fifth switch unit 250 receives the second isolation control signal ISO2, the second terminal of the sixth switch unit 260 is connected to the complementary bit line BLB, and the control terminal of the sixth switch unit 260 receives the third isolation control signal ISO3.
  • the second terminal of the seventh switch unit 270 is connected to the bit line BL, and the control terminal of the seventh switch unit 270 receives the third isolation control signal ISO3.
  • the first terminal of the first switch unit 210 is connected to the drain of the first N-type transistor N1, the second terminal of the first switch unit 210 is connected to the gate of the first N-type transistor N1, and the control terminal of the first switch unit 210 receives a bias. shift cancellation signal OC.
  • the first terminal of the second switch unit 220 is connected to the gate of the second N-type transistor N2, the second terminal of the second switch unit 220 is connected to the drain of the second N-type transistor N2, and the control terminal of the second switch unit 220 receives a bias. shift cancellation signal OC.
  • the first end of the third switch unit 230 is connected to the drain of the first N-type transistor N1, the second end of the third switch unit 230 is connected to the gate of the second P-type transistor P2, and the control end of the third switch unit 230 receives the third An isolation control signal ISO1.
  • the first end of the fourth switch unit 240 is connected to the gate of the first P-type transistor P1, the second end of the fourth switch unit 240 is connected to the drain of the second N-type transistor N2, and the control end of the fourth switch unit 240 receives the third An isolation control signal ISO1.
  • An embodiment of the present disclosure provides a control method for a sense amplifier.
  • the sense amplifier includes a precharge stage T1, an offset elimination stage T2, a forward driving stage T3, a charge sharing stage T4, and a sensing amplification stage.
  • the control method includes the following steps:
  • the voltages of the control equalization module 300 driving the bit line BL and the complementary bit line BLB are both the precharge voltage VBLP.
  • the voltage of the first power terminal SAP and the voltage of the second power terminal SAN are controlled to be the precharge voltage VBLP, the word line is turned off, and the memory unit 100 is controlled.
  • the internal transistor M1 is turned off.
  • the first switch unit 210 is controlled to disconnect the gate and drain of the first N-type transistor N1
  • the second switch unit 220 is controlled to disconnect the gate and drain of the second N-type transistor N2
  • the third switch unit 230 is controlled.
  • the drain of the first N-type transistor N1 and the gate of the second P-type transistor P2 are connected, and the fourth switching unit 240 is controlled to connect the drain of the second N-type transistor N2 and the gate of the first P-type transistor P1.
  • the fifth switch unit 250 is controlled to disconnect the gate of the first P-type transistor P1 from the gate of the second P-type transistor P2, and the sixth switch unit 260 is controlled to disconnect the gate of the first P-type transistor P1 from the complementary bit.
  • the line BLB is turned on, and the seventh switch unit 270 is controlled to disconnect the gate of the second P-type transistor P2 from the bit line BL.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB and the bit line BL are connected.
  • the voltage of the first power terminal SAP and the voltage of the second power terminal SAN are controlled to be the precharge voltage VBLP, and the balancing module 300 drives the voltage of the bit line BL and the voltage of the complementary bit line BLB to the precharge voltage VBLP.
  • the voltage of the first power supply terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power supply terminal SAN is the ground voltage VSS
  • the word line is turned off
  • the control Transistor M1 in memory cell 100 is turned off.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the first switching unit 210 is controlled to turn on the gate and drain of the first N-type transistor N1, and the second switching unit 220 is controlled to turn on the gate and drain of the second N-type transistor N2.
  • the third switch unit 230 is controlled to disconnect the drain of the first N-type transistor N1 from the gate of the second P-type transistor P2, and the fourth switch unit 240 is controlled to disconnect the drain of the second N-type transistor N2 from the gate of the first P-type transistor P2.
  • the gate of transistor P1 is open.
  • the fifth switch unit 250 is controlled to disconnect the gate of the first P-type transistor P1 from the gate of the second P-type transistor P2.
  • the sixth switch unit 260 is controlled to connect the gate of the first P-type transistor P1 to the complementary bit line BLB, and the seventh switch unit 270 is controlled to connect the gate of the second P-type transistor P2 to the bit line BL.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the gate of the first N-type transistor N1 is connected to the drain of the first N-type transistor N1.
  • the gate of the second N-type transistor N2 is connected to the drain of the second N-type transistor N2.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power terminal SAN is controlled to be the ground voltage VSS
  • the sensing module 200 is controlled to generate a compensation voltage on the bit line BL and the complementary bit line BLB.
  • S103 in the forward driving stage T3, controls the voltage of the first power supply terminal SAP to be the power supply voltage VDD, and the voltage of the second power supply terminal SAN to be the ground voltage VSS.
  • the word line is turned off, and the transistor M1 in the memory cell 100 is controlled to be turned off.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the first switch unit 210 is controlled to turn on the gate and drain of the first N-type transistor N1
  • the second switch unit 220 is controlled to turn on the gate and drain of the second N-type transistor N2.
  • the third switch unit 230 is controlled to disconnect the drain of the first N-type transistor N1 from the gate of the second P-type transistor P2
  • the fourth switch unit 240 is controlled to disconnect the drain of the second N-type transistor N2 from the gate of the first P-type transistor P2.
  • the gate of transistor P1 is open.
  • the fifth switch unit 250 is controlled to connect the gate of the first P-type transistor P1 to the gate of the second P-type transistor P2, and the sixth switch unit 260 is controlled to connect the gate of the first P-type transistor P1 to the complementary bit line BLB. is turned off, and the seventh switch unit 270 is controlled to disconnect the gate of the second P-type transistor P2 from the bit line BL.
  • the gate of the first P-type transistor P1 is disconnected from the complementary bit line BLB
  • the gate of the second P-type transistor P2 is disconnected from the bit line BL
  • the gate of the first P-type transistor P1 is connected.
  • the gate of the second P-type transistor P2. The gate of the first N-type transistor N1 is connected to the drain of the first N-type transistor N1.
  • the gate of the second N-type transistor N2 is connected to the drain of the second N-type transistor N2.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power supply terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power supply terminal SAN is controlled to be the ground voltage VSS.
  • the sensing module 200 further adjusts the compensation voltage on the bit line BL and the complementary bit line BLB.
  • the voltage of the bit line BL is greater than the voltage of the complementary bit line BLB, and the difference between the voltage of the bit line BL and the voltage of the complementary bit line BLB is the compensation voltage. That is, in the offset elimination stage T2, the gate voltage of the second P-type transistor P2 is greater than the gate voltage of the first P-type transistor P1.
  • the gate of the first P-type transistor P1 is connected to the gate of the second P-type transistor P2, the gate voltage of the first P-type transistor P1 rises, and the drain voltage of the first P-type transistor P1
  • the drain voltage of the first N-type transistor N1 decreases, and the voltage of the complementary bit line BLB decreases.
  • the gate voltage of the second P-type transistor P2 decreases, the drain voltage of the second P-type transistor P2 and the drain voltage of the second N-type transistor N2 increase, and the voltage of the bit line BL increases, achieving further amplification of the bit line BL and complementary Compensation voltage on bit line BLB.
  • the voltage of the bit line BL is less than the voltage of the complementary bit line BLB, and the difference between the voltage of the bit line BL and the voltage of the complementary bit line BLB is the compensation voltage. That is, in the offset elimination stage T2, the gate voltage of the second P-type transistor P2 is smaller than the gate voltage of the first P-type transistor P1.
  • the gate of the first P-type transistor P1 is connected to the gate of the second P-type transistor P2, the gate voltage of the first P-type transistor P1 decreases, and the drain voltage of the first P-type transistor P1
  • the drain voltage of the first N-type transistor N1 rises, and the voltage of the complementary bit line BLB rises.
  • the gate voltage of the second P-type transistor P2 increases, the drain voltage of the second P-type transistor P2 and the drain voltage of the second N-type transistor N2 decrease, and the voltage of the bit line BL decreases, achieving further amplification of the bit line BL and complementary Compensation voltage on bit line BLB.
  • the voltage of the first power supply terminal SAP and the voltage of the second power supply terminal SAN are controlled to be the precharge voltage VBLP, the word line is turned on, and the memory unit 100 is controlled.
  • the transistor M1 is turned on.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the first switching unit 210 is controlled to disconnect the gate and drain of the first N-type transistor N1, and the second switching unit 220 is controlled to disconnect the gate and drain of the second N-type transistor N2.
  • the third switch unit 230 is controlled to connect the drain of the first N-type transistor N1 and the gate of the second P-type transistor P2, and the fourth switch unit 240 is controlled to connect the drain of the second N-type transistor N2 to the gate of the first P-type transistor P2.
  • the gate of transistor P1 is turned on.
  • the fifth switch unit 250 is controlled to disconnect the gate of the first P-type transistor P1 from the gate of the second P-type transistor P2.
  • the sixth switch unit 260 is controlled to connect the gate of the first P-type transistor P1 to the complementary bit line BLB, and the seventh switch unit 270 is controlled to disconnect the gate of the second P-type transistor P2 from the bit line BL.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB and the bit line BL are connected.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power terminal SAP and the voltage of the second power terminal SAN are controlled to be the precharge voltage VBLP, and the transistors in the memory unit 100 are turned on, so that charge sharing occurs between the capacitor C1 in the memory unit 100 and the bit line BL.
  • the voltage of the first power supply terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power supply terminal SAN is controlled to be the ground voltage VSS.
  • the word line is turned on, and the transistor M1 in the memory cell 100 is controlled to be turned on.
  • the balancing module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB, the first switching unit 210 is controlled to disconnect the gate and drain of the first N-type transistor N1, and the second switching unit 220 is controlled to disconnect the second N-type transistor N2.
  • the gate and drain of the first N-type transistor N1 are disconnected, the third switching unit 230 is controlled to connect the drain of the first N-type transistor N1 and the gate of the second P-type transistor P2, and the fourth switching unit 240 is controlled to connect the second N-type transistor N1 and the gate of the second N-type transistor P2.
  • the drain of N2 is connected to the gate of the first P-type transistor P1, and the fifth switch unit 250 is controlled to disconnect the gate of the first P-type transistor P1 from the gate of the second P-type transistor P2, and the sixth switch is controlled.
  • the unit 260 turns on the gate of the first P-type transistor P1 and the complementary bit line BLB, and controls the seventh switch unit 270 to turn off and on the gate of the second P-type transistor P2 and the bit line BL.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB and the bit line BL are connected.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power supply terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power supply terminal SAN is controlled to be the ground voltage VSS.
  • the transistor in the memory unit 100 is turned on, so that the sensing module 200 amplifies the voltage difference between the bit line BL and the complementary bit line BLB. .
  • the first switching unit 210 includes a third N-type transistor N3.
  • the drain of the third N-type transistor N3 is the first terminal of the first switching unit 210.
  • the source of the third N-type transistor N3 is the first switch.
  • the second end of the unit 210, the gate of the third N-type transistor N3 is the control end of the first switching unit 210, the gate of the third N-type transistor N3 receives the offset cancellation signal OC, and the third N-type transistor N3 responds to the offset
  • the cancel signal OC controls whether the gate and drain of the first N-type transistor N1 are turned on.
  • the second switch unit 220 includes a fourth N-type transistor N4.
  • the source of the fourth N-type transistor N4 is the first terminal of the second switch unit 220.
  • the drain of the fourth N-type transistor N4 is the second terminal of the second switch unit 220.
  • the gate of the fourth N-type transistor N4 is the control terminal of the second switch unit 220, the gate of the fourth N-type transistor N4 receives the offset cancellation signal OC, and the fourth N-type transistor N4 controls the second switch unit 220 according to the offset cancellation signal OC. Whether the gate and drain of N-type transistor N2 are connected.
  • the third switching unit 230 includes a fifth N-type transistor N5.
  • the source or drain of the fifth N-type transistor N5 is the first terminal of the third switching unit 230.
  • the drain of the fifth N-type transistor N5 is Or the source is the second terminal of the third switch unit 230, the gate of the fifth N-type transistor N5 is the control terminal of the third switch unit 230, the gate of the fifth N-type transistor N5 receives the first isolation control signal ISO1, and the fifth The N-type transistor N5 and the ninth N-type transistor N9 jointly control whether the drain of the first N-type transistor N1 and the bit line BL are turned on.
  • the fourth switch unit 240 includes a sixth N-type transistor N6.
  • the source or drain of the sixth N-type transistor N6 is the first end of the fourth switch unit 240.
  • the drain or source of the sixth N-type transistor N6 is the fourth switch.
  • the second end of the unit 240, the gate of the sixth N-type transistor N6 is the control end of the fourth switching unit 240, the gate of the sixth N-type transistor N6 receives the first isolation control signal ISO1, the sixth N-type transistor N6 and the
  • the eight N-type transistors N8 jointly control whether the drain of the second N-type transistor N2 and the complementary bit line BLB are turned on.
  • the fifth switching unit 250 includes a seventh N-type transistor N7.
  • the drain or source of the seventh N-type transistor N7 is the first terminal of the fifth switching unit 250.
  • the source of the seventh N-type transistor N7 is Or the drain is the second terminal of the fifth switching unit 250, the gate of the seventh N-type transistor N7 is the control terminal of the fifth switching unit 250, and the gate of the seventh N-type transistor N7 receives the second isolation control signal ISO2.
  • the second isolation control signal ISO2 controls whether the gate of the first P-type transistor P1 and the gate of the second P-type transistor P2 are connected.
  • the sixth switch unit 260 includes an eighth N-type transistor N8, the drain of the eighth N-type transistor N8 is the first terminal of the sixth switch unit 260, and the source of the eighth N-type transistor N8 is the sixth switch.
  • the second terminal of the unit 260, the gate of the eighth N-type transistor N8 is the control terminal of the sixth switching unit 260, the gate of the eighth N-type transistor N8 receives the third isolation control signal ISO3, and the gate of the eighth N-type transistor N8 is based on
  • the third isolation control signal ISO3 controls whether the gate of the first P-type transistor P1 and the complementary bit line BLB are turned on.
  • the seventh switching unit 270 includes a ninth N-type transistor N9.
  • the drain of the ninth N-type transistor N9 is the first terminal of the seventh switching unit 270.
  • the source of the ninth N-type transistor N9 is the second terminal of the seventh switching unit 270.
  • the gate of the ninth N-type transistor N9 is the control terminal of the seventh switch unit 270, the gate of the ninth N-type transistor N9 receives the third isolation control signal ISO3, and the ninth N-type transistor N9 is controlled according to the third isolation control signal ISO3. Whether the gate of the second P-type transistor P2 and the bit line BL are connected.
  • the balancing module 300 includes a tenth N-type transistor N10, an eleventh N-type transistor N11, and a twelfth N-type transistor N12.
  • the first terminal of the tenth N-type transistor N10 is connected to the bit line BL
  • the second terminal of the tenth N-type transistor N10 is connected to the first terminal of the eleventh N-type transistor N11 and then connected to the charging power supply terminal.
  • the gate receives the precharge signal BLEQ.
  • the second end of the eleventh N-type transistor N11 is connected to the complementary bit line BLB, and the gate of the eleventh N-type transistor N11 is connected to the gate of the tenth N-type transistor N10.
  • the first terminal of the twelfth N-type transistor N12 is connected to the bit line BL
  • the second terminal of the twelfth N-type transistor N12 is connected to the complementary bit line BLB
  • the gate of the twelfth N-type transistor N12 is connected to the tenth N-type transistor N10 the gate.
  • the bit line BL and the complementary bit line BLB are charged to the precharge voltage VBLP.
  • the precharge signal BLEQ is high level during the precharge phase T1 , and the tenth N-type transistor N10 , the eleventh N-type transistor N11 and the twelfth N-type transistor N12 is all on.
  • the offset cancellation signal OC is low level during the precharge phase T1, and both the third N-type transistor N3 and the fourth N-type transistor N4 are turned off.
  • the first isolation control signal ISO1 is high level during the precharge phase T1, and both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned on.
  • the second isolation control signal ISO2 is low level during the precharge stage T1, and the seventh N-type transistor N7 is turned off.
  • the third isolation control signal ISO3 is high level during the precharge stage T1, and both the eighth N-type transistor N8 and the ninth N-type transistor N9 are turned on.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB and the bit line BL are connected.
  • the word line signal is low level, the word line is turned off, and the transistor M1 in the memory cell 100 is turned off.
  • the voltage of the first power terminal SAP and the voltage of the second power terminal SAN are controlled to be the precharge voltage VBLP, and the balancing module 300 drives the voltage of the bit line BL and the voltage of the complementary bit line BLB to the precharge voltage VBLP.
  • the precharge signal BLEQ is low level during the offset elimination phase T2 , and the tenth N-type transistor N10 , the eleventh N-type transistor N11 and the twelfth N-type transistor N10 are at a low level.
  • Transistors N12 are both turned off.
  • the offset cancellation signal OC is high level during the offset cancellation phase T2, and both the third N-type transistor N3 and the fourth N-type transistor N4 are turned on.
  • the first isolation control signal ISO1 is low level during the offset elimination phase T2, and both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned off.
  • the second isolation control signal ISO2 is low level during the offset elimination phase T2, and the seventh N-type transistor N7 is turned off.
  • the third isolation control signal ISO3 is high level during the offset elimination phase T2, and both the eighth N-type transistor N8 and the ninth N-type transistor N9 are turned on.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the gate of the first N-type transistor N1 is connected to the drain of the first N-type transistor N1.
  • the gate of the second N-type transistor N2 is connected to the drain of the second N-type transistor N2.
  • the word line signal is low level, the word line is turned off, and the transistor M1 in the memory cell 100 is turned off.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power terminal SAN is controlled to be the ground voltage VSS
  • the sensing module 200 is controlled to generate a compensation voltage on the bit line BL and the complementary bit line BLB.
  • the precharge signal BLEQ is low level in the forward driving phase T3
  • the tenth N-type transistor N10 , the eleventh N-type transistor N11 and the twelfth N-type transistor N10 are at a low level.
  • Transistors N12 are both turned off.
  • the offset cancellation signal OC is high level in the forward driving phase T3, and both the third N-type transistor N3 and the fourth N-type transistor N4 are turned on.
  • the first isolation control signal ISO1 is low level during the forward driving phase T3, and both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned off.
  • the second isolation control signal ISO2 is high level during the forward driving phase T3, and the seventh N-type transistor N7 is turned on.
  • the third isolation control signal ISO3 is low level in the forward driving phase T3, and the eighth N-type transistor N8 and the ninth N-type transistor N9 are both turned off.
  • the gate of the first P-type transistor P1 is disconnected from the complementary bit line BLB
  • the gate of the second P-type transistor P2 is disconnected from the bit line BL
  • the gate of the first P-type transistor P1 is disconnected.
  • the gate of the first N-type transistor N1 is connected to the drain of the first N-type transistor N1.
  • the gate of the second N-type transistor N2 is connected to the drain of the second N-type transistor N2.
  • the word line signal is low level, the word line is turned off, and the transistor M1 in the memory cell 100 is turned off.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power supply terminal SAP is controlled to be the power supply voltage VDD, and the voltage of the second power supply terminal SAN is controlled to be the ground voltage VSS.
  • the sensing module 200 further adjusts the compensation voltage on the bit line BL and the complementary bit line BLB.
  • the precharge signal BLEQ is low level in the charge sharing phase T4, and the tenth N-type transistor N10, the eleventh N-type transistor N11 and the twelfth N-type transistor N12 is cut off.
  • the offset cancellation signal OC is low level during the charge sharing phase T4, and both the third N-type transistor N3 and the fourth N-type transistor N4 are turned off.
  • the first isolation control signal ISO1 is high level during the charge sharing phase T4, and both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned on.
  • the second isolation control signal ISO2 is low level during the charge sharing phase T4, and the seventh N-type transistor N7 is turned off.
  • the third isolation control signal ISO3 is high level during the charge sharing phase T4, and both the eighth N-type transistor N8 and the ninth N-type transistor N9 are turned on.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB is connected.
  • the word line signal is high level, the word line is turned on, and the transistor M1 in the memory cell 100 is turned on.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power terminal SAP and the voltage of the second power terminal SAN are controlled to be the precharge voltage VBLP, and the transistors in the memory unit 100 are turned on, so that charge sharing occurs between the capacitor C1 in the memory unit 100 and the bit line BL.
  • the precharge signal BLEQ is low level in the sensing amplification stage T5 , and the tenth N-type transistor N10 , the eleventh N-type transistor N11 and the twelfth N-type transistor N10 are at a low level.
  • Transistors N12 are both turned off.
  • the offset cancellation signal OC is low level during the sensing amplification stage T5, and both the third N-type transistor N3 and the fourth N-type transistor N4 are turned off.
  • the first isolation control signal ISO1 is high level during the sensing amplification stage T5, and both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned on.
  • the second isolation control signal ISO2 is low level during the sensing amplification stage T5, and the seventh N-type transistor N7 is turned off.
  • the third isolation control signal ISO3 is high level during the sensing amplification stage T5, and both the eighth N-type transistor N8 and the ninth N-type transistor N9 are turned on.
  • the gate of the first P-type transistor P1 is connected to the gate of the first N-type transistor N1 and then connected to the complementary bit line BLB.
  • the gate of the second P-type transistor P2 is connected to the gate of the second N-type transistor N2 and then connected to the bit line BL.
  • the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 and then connected to the bit line BL.
  • the complementary bit line BLB is connected.
  • the word line signal is high level, the word line is turned on, and the transistor M1 in the memory cell 100 is turned on.
  • the equalization module 300 is controlled to stop driving the bit line BL and the complementary bit line BLB.
  • the voltage of the first power terminal SAP is controlled to be the power supply voltage VDD
  • the voltage of the second power terminal SAN is controlled to be the ground voltage VSS
  • the sensing module 200 amplifies the voltage difference on the bit line BL and the complementary bit line BLB.
  • the balancing module 300 drives the voltage of the bit line BL and the complementary bit line BLB to the precharge voltage VBLP.
  • the sensing module 200 drives the voltage of the bit line BL and the complementary bit line BLB to the precharge voltage VBLP.
  • the gate voltage of the first P-type transistor P1 and the gate voltage of the second P-type transistor P2 can be adjusted in the forward driving phase T3,
  • the drain voltage of the first N-type transistor N1 and the drain voltage of the second N-type transistor N2 are adjusted to adjust the compensation voltage on the bit line BL and the complementary bit line BLB.
  • the capacitor C1 in the memory unit 100 shares charges with the complementary bit line BLB.
  • the sensing module 200 amplifies the voltage difference between the bit line BL and the complementary bit line BLB to achieve accurate readout. data.
  • An embodiment of the present disclosure provides a controller for implementing the control method of the sense amplifier involved in the above embodiment.
  • An embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier related to the above embodiment.

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Abstract

本公开提供一种灵敏放大器、控制方法及半导体存储器，包括感测模块和均衡模块，感测模块连接位线和互补位线，均衡模块连接位线和互补位线，均衡模块在预充电阶段驱动位线和互补位线的电压均为预充电电压，感测模块用于在偏移消除阶段在位线和互补位线上生成补偿电压，在正向驱动阶段调整位线和互补位线上的补偿电压，在电荷共享阶段控制存储单元与位线进行电荷共享，在感测放大阶段放大位线和互补位线上的电压差。通过如此设置，可以提高数据的读出准确性。

Description

灵敏放大器、控制方法及半导体存储器
本公开要求于2022年08月10日提交中国专利局、申请号为202210957826.1、申请名称为“灵敏放大器、控制方法及半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限定于一种灵敏放大器、控制方法及半导体存储器。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。
灵敏放大器作为半导体存储器的数据传输的中转站，它对半导体存储器的能否正常工作起着重要的作用，它通过放大目标位线与互补位线之间的电压差，来完成数据的读取操作。但在实际生产工艺中，会因引入制造缺陷而带来晶体管不完全匹配的问题，可能会造成灵敏放大器错误放大，造成数据读取错误。
发明内容
本公开一实施例提供一种灵敏放大器，包括：感测模块和均衡模块；
感测模块连接位线和互补位线，均衡模块连接位线和互补位线；
均衡模块在预充电阶段驱动位线和互补位线的电压均为预充电电压；感测模块用于在偏移消除阶段在位线和互补位线上生成补偿电压；在正向驱动阶段调整位线和互补位线上的补偿电压，在电荷共享阶段控制存储单元与位线进行电荷共享，在感测放大阶段放大位线和互补位线上的电压差。
在一些实施例中，感测模块包括：第一开关单元、第二开关单元、第三开关单元、第四开关单元、第五开关单元、第六开关单元、第七开关单元、第一P型晶体管、第二P型晶体管、第一N型晶体管以及第二N型晶体管；
第一P型晶体管，其栅极连接第五开关单元的第一端，其栅极还连接第六开关单元的第一端，其漏极连接第一N型晶体管的漏极，其源极连接第一电源端；
第二P型晶体管，其栅极连接第五开关单元的第二端，其栅极还连接第七开关单元的第一端，其漏极连接第二N型晶体管的漏极，其源极连接第一P型晶体管的源极；
第五开关单元的控制端接收第二隔离控制信号；
第六开关单元，其第二端连接互补位线，其控制端接收第三隔离控制信号；
第七开关单元，其第二端连接位线，其控制端接收第三隔离控制信号；
第一N型晶体管，其栅极连接互补位线，其源极连接第二电源端；
第二N型晶体管，其栅极连接位线，其源极连接第一N型晶体管的源极；
第一开关单元，其第一端连接第一N型晶体管的漏极，其第二端连接第一N型晶体管的栅极，其控制端接收偏移消除信号；
第二开关单元，其第一端连接第二N型晶体管的栅极，其第二端连接第二N型晶体管的漏极，其控制端接收偏移消除信号；
第三开关单元，其第一端连接第一N型晶体管的漏极，其第二端连接第二P型晶体管的栅极，其控制端接收第一隔离控制信号；
第四开关单元，其第一端连接第一P型晶体管的栅极，其第二端连接第二N型晶体管的漏极，其控制端接收第一隔离控制信号。
在一些实施例中，第五开关单元包括：
第七N型晶体管，其漏极或源极为第五开关单元的第一端，其源极或漏极为第五开关单元的第二端，其栅极为第五开关单元的控制端，用于接收第二隔离控制信号，根据所第二隔离控制信号控制第一P型晶体管的栅极和第二P型晶体管的栅极是否接通。
在一些实施例中，第六开关单元包括：
第八N型晶体管，其漏极为第六开关单元的第一端，其源极为第六开关单元的第二端，其栅极为第六开关单元的控制端，用于接收第三隔离控制信号，根据第三隔离控制信号控制第一P型晶体管的栅极和互补位线是否接通；
第七开关单元包括：
第九N型晶体管，其漏极为第七开关单元的第一端，其源极为第七开关单元的第二端，其栅极为第七开关单元的控制端，用于接收第三隔离控制信号，根据第三隔离控制信号控制第二P型晶体管的栅极和位线是否接通。
在一些实施例中，第一开关单元包括：
第三N型晶体管，其漏极为第一开关单元的第一端，其源极为第一开关单元的第二端，其栅极为第一开关单元的控制端，用于接收偏移消除信号，根据偏移消除信号控制第一N型晶体管的栅极和漏极是否接通；
第二开关单元包括：
第四N型晶体管，其源极为第二开关单元的第一端，其漏极为第二开关单元的第二端，其栅极为第二开关单元的控制端，用于接收偏移消除信号，根据偏移消除信号控制第二N型晶体管的栅极和漏极是否接通。
在一些实施例中，第三开关单元包括：
第五N型晶体管，其源极或漏极为第三开关单元的第一端，其漏极或源极为第三开关单元的第二端；其栅极为第三开关单元的控制端，接收第一隔离控制信号，第五N型晶体管和第九N型晶体管共同控制第一N型晶体管的漏极和位线是否接通；
第四开关单元包括：
第六N型晶体管，其源极或漏极为第四开关单元的第一端，其漏极或源极为第四开关单元的第二端，其栅极为第四开关单元的控制端，接收第一隔离控制信号，第六N型晶体管和第八N型晶体管共同控制第二N型晶体管的漏极和互补位线是否接通。
在一些实施例中，均衡模块包括：
第十N型晶体管，其第一端连接位线，其第二端连接第十一N型晶体管的第一端且连接充电电源端，其栅极接收预充电信号；
第十一N型晶体管，其第二端连接互补位线，其栅极连接第十N型晶体管的栅极；
第十二N型晶体管，其第一端连接位线，其第二端连接互补位线，其栅极连接第十N型晶体管的栅极。
本公开一实施例还提供一种灵敏放大器的控制方法，灵敏放大器包括感测模块和均衡模块，灵敏放大器的工作阶段包括预充电阶段、偏移消除阶段、正向驱动阶段、电荷共享阶段以及感测放大阶段；方法包括：
控制均衡模块在预充电阶段驱动位线和互补位线的电压均为预充电电压；
控制感测模块在偏移消除阶段在位线和互补位线上生成补偿电压；
控制感测模块在正向驱动阶段调整位线和互补位线上的补偿电压；
在电荷共享阶段控制存储单元与位线进行电荷共享；
控制感测模块在感测放大阶段放大位线和互补位线上的电压差。
在一些实施例中，感测模块包括：
第一开关单元、第二开关单元、第三开关单元、第四开关单元、第五开关单元、第六开关单元、第七开关单元、第一P型晶体管、第二P型晶体管、第一N型晶体管以及第二N型晶体管；
第一P型晶体管的栅极连接第五开关单元的第一端，第一P型晶体管的栅极还连接第六开关单元的第一端，第一P型晶体管的漏极连接第一N型晶体管的漏极，第一P型晶体管的源极连接第一电源端；
第二P型晶体管的栅极连接第五开关单元的第二端，第二P型晶体管的栅极还连接第七开关单元的第一端，第二P型晶体管的漏极连接第二N型晶体管的漏极，第二P型晶体管的源极连接第一P型晶体管的源极；
第五开关单元的控制端接收第二隔离控制信号；
第六开关单元的第二端连接互补位线，第六开关单元的控制端接收第三隔离控制信号；第七开关单元的第二端连接位线，第七开关单元的控制端接收第三隔离控制信号；
第一N型晶体管的栅极连接互补位线，第一N型晶体管的源极连接第二电源端；
第二N型晶体管的栅极连接位线，第二N型晶体管的源极连接第一N型晶体管的源极；
第一开关单元的第一端连接第一N型晶体管的漏极，第一开关单元的第二端连接第一N型晶体管的栅极，第一开关单元的控制端接收偏移消除信号；
第二开关单元的第一端连接第二N型晶体管的栅极，第二开关单元的第二端连接第二N型晶体管的漏极，第二开关单元的控制端接收偏移消除信号；
第三开关单元的第一端连接第一N型晶体管的漏极，第三开关单元的第二端连接第二P型晶体管的栅极，第三开关单元的控制端接收第一隔离控制信号；
第四开关单元的第一端连接第一P型晶体管的栅极，第四开关单元的第二端连接第二N型晶体管的漏极，第四开关单元的控制端接收第一隔离控制信号；
控制感测模块在偏移消除阶段在位线和互补位线上生成补偿电压，具体包括：
在偏移消除阶段，控制第一电源端的电压为电源电压，第二电源端的电压为接地电压；控制存储单元内晶体管截止；
控制均衡模块停止驱动位线和互补位线，控制第一开关单元使第一N型晶体管的栅极和漏极接通，控制第二开关单元使第二N型晶体管的栅极和漏极接通，控制第三开关单元使第一N型晶体管的漏极和第二P型晶体管的栅极断开，控制第四开关单元使第二N型晶体管的漏极和第一P型晶体管的栅极断开，控制第五开关单元使第一P型晶体管的栅极与第二P型晶体管的栅极断开，控制第六开关单元使第一P型晶体管的栅极与互补位线接通，控制第七开关单元使第二P型晶体管的栅极与位线接通。
在一些实施例中，控制感测模块在正向驱动阶段调整位线和互补位线上的补偿电压，具体包括：
在正向驱动阶段，控制第一电源端的电压为电源电压，第二电源端的电压为接地电压；控制存储单元内晶体管截止；
控制均衡模块停止驱动位线和互补位线，控制第一开关单元使第一N型晶体管的栅极和漏极接通，控制第二开关单元使第二N型晶体管的栅极和漏极接通，控制第三开关单元使第一N型晶体管的漏极和第二P型晶体管的栅极断开，控制第四开关单元使第二N型晶体管的漏极和第一P型晶体管的栅极断开，控制第五开关单元使第一P型晶体管的栅极与第二P型晶体管的栅极接通，控制第六开关单元使第一P型晶体管的栅极与互补位线断开，控制第七开关单元使第二P型晶体管的栅极与位线断开。
在一些实施例中，在电荷共享阶段控制存储单元与位线进行电荷共享，具体包括：
在电荷共享阶段，控制第一电源端的电压和第二电源端的电压为预充电电压；控制存储单元内晶体管导通；
控制均衡模块停止驱动位线和互补位线，控制第一开关单元使第一N型晶体管的栅极和漏极断开，控制第二开关单元使第二N型晶体管的栅极和漏极断开，控制第三开关单元使第一N型晶体管的漏极和第二P型晶体管的栅极接通，控制第四开关单元使第二N型晶体管的漏极和第一P型晶体管的栅极接通，控制第五开关单元使第一P型晶体管的栅极与第二P型晶体管的栅极断开，控制第六开关单元使第一P型晶体管的栅极与互补位线接通，控制第七开关单元使第二P型晶体管的栅极与位线接通。
在一些实施例中，控制感测模块在感测放大阶段放大位线和互补位线上的电压差，具体包括：
在感测放大阶段，控制第一电源端的电压为电源电压，第二电源端的电压为接地电压；控制存储单元内晶体管导通；
控制均衡模块停止驱动位线和互补位线，控制第一开关单元使第一N型晶体管的栅极和漏极断开，控制第二开关单元使第二N型晶体管的栅极和漏极断开，控制第三开关单元使第一N型晶体管的漏极和第二P型晶体管的栅极接通，控制第四开关单元使第二N型晶体管的漏极和第一P型晶体管的栅极接通，控制第五开关单元使第一P型晶体管的栅极与第二P型晶体管的栅极断开，控制第六开关单元使第一P型晶体管的栅极与互补位线接通，控制第七开关单元使第二P型晶体管的栅极与位线接通。
在一些实施例中，均衡模块包括第十N型晶体管、第十一N型晶体管以及第十二N型晶体管；
第十N型晶体管的第一端连接位线，第十N型晶体管的第二端连接第十一N型晶体管的第一端且连接充电电源端，第十N型晶体管的栅极接收预充电信号；
第十一N型晶体管的第二端连接互补位线，第十一N型晶体管的栅极连接第十N型晶体管的栅极；第十二N型晶体管的第一端连接位线，第十二N型晶体管的第二端连接互补位线，第十二N型晶体管的栅极连接第十N型晶体管的栅极；
制均衡模块在预充电阶段驱动位线和互补位线的电压均为预充电电压，具体包括：
控制第十N型晶体管、第十一N型晶体管以及第十二N型晶体管导通，使位线和互补位线充电至预充电电压；
控制第一电源端的电压和第二电源端的电压为预充电电压，控制存储单元内晶体管截止；
控制第一开关单元使第一N型晶体管的栅极和漏极断开，控制第二开关单元使第二N型晶体管的栅极和漏极断开，控制第三开关单元使第一N型晶体管的漏极和第二P型晶体管的栅极接通，控制第四开关单元使第二N型晶体管的漏极和第一P型晶体管的栅极接通，控制第五开关单元使第一P型晶体管的栅极与第二P型晶体管的栅极断开，控制第六开关单元使第一P型晶体管的栅极与互补位线接通，控制第七开关单元使第二P型晶体管的栅极与位线接通。
在一些实施例中，第一开关单元包括第三N型晶体管，第二开关单元包括第四N型晶体管，第三开关单元包括第五N型晶体管，第四开关单元包括第六N晶体管，第五开关单元包括第七N晶体管，第六开关单元包括第八N晶体管，第七开关单元包括第九N晶体管；
预充电信号在预充电阶段为高电平，预充电信号在偏移消除阶段、正向驱动阶段、电荷共享阶段以及感测放大阶段为低电平；
偏移消除信号在偏移消除阶段和正向驱动阶段为高电平，偏移消除信号在预充电阶段、电荷共享阶段以及感测放大阶段均为低电平；
第一隔离控制信号在偏移消除阶段和正向驱动阶段为低电平，第一隔离控制信号在预充电阶段、电荷共享阶段以及感测放大阶段均为高电平；
第二隔离控制信号在正向驱动阶段为高电平，第二隔离控制信号在预充电阶段、偏移消除阶段、电荷共享阶段以及感测放大阶段均为低电平；
第三隔离控制信号在正向驱动阶段为低电平，第三隔离控制信号在预充电阶段、偏移消除阶段、电荷共享阶段以及感测放大阶段均为高电平。
本公开一实施例提供一种控制器，用于实现上述实施例所涉及的灵敏放大器的控制方法。
本公开一实施例提供一种半导体存储器，包括上述实施例所涉及的灵敏放大器。
本公开提供灵敏放大器、控制方法及半导体存储器，由均衡模块在预充电阶段驱动位线和互补位线的电压至预充电电压，在其他阶段停止驱动位线和互补位线。在偏移消除阶段，感测模块在位线和互补位线上产生补偿电压，在正向驱动阶段，感测模块调整位线和互补位线上补偿电压。在电荷共享阶段，存储单元与互补位线进行电荷共享，在感测放大阶段，感测模块放大位线和互补位线上的电压差，实现准确读出数据。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为一种灵敏放大器的电路示意图；
图2为本公开一实施例提供的灵敏放大器的电路示意图；
图3为图2所示实施例提供的灵敏放大器的时序示意图；
图4为图2所示实施例提供的灵敏放大器在预充电阶段的原理示意图；
图5为图2所示实施例提供的灵敏放大器在偏移消除阶段的原理示意图；
图6为图2所示实施例提供的灵敏放大器在正向驱动阶段的原理示意图；
图7为图2所示实施例提供的灵敏放大器在电荷共享阶段的原理示意图；
图8为图2所示实施例提供的灵敏放大器在感测放大阶段的原理示意图。
附图标记：
100、存储单元；200、感测模块；210、第一开关单元；220、第二开关单元；230、第三开关单元；240、第四开关单元；250、第五开关单元；260、第六开关单元；270、第七开关单元；300、均衡模块；BLB、互补位线；BL、位线；ISO1、第一隔离控制信号；ISO2、第二隔离控制信号；ISO3、第三隔离控制信号；OC、偏移消除信号；BLEQ、充电信号；T1、预充电阶段；T2、偏移消除阶段；T3、正向驱动阶段；T4、电荷共享阶段；T5、感测放大阶段；VBLP、充电电源端；P1、第一P型晶体管；P2、第二P型晶体管；N1、第一N型晶体管；N2、第二N型晶体管；N3、第三N型晶体管；N4、第四N型晶体管；N5、第五N型晶体管；N6、第六N型晶体管；N7、第七N型晶体管；N8、第八N型晶体管；N9、第九N型晶体管；N10、第十N型晶体管；N11、第十一N型晶体管；N12、第十二N型晶体管；VDD、电源电压；VSS、接地电压；VBLP、预充电电压；SAP、第一电源端；SAN、第二电源端。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不 代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
如图1所示，一种灵敏放大器包括第一P型晶体管P1、第二P型晶体管P2、第一N型晶体管N1以及第二N型晶体管N2。第一P型晶体管P1的源极连接第二P型晶体管P2的源极后连接第一电源端SAP，第一电源端SAP的电压为电源电压VDD。第一N型晶体管N1的源极连接第二N型晶体管N2的源极后连接第二电源端SAN，第二电源端SAN的电压为接地电压VSS。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接互补位线BLB。第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接位线BL。第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接位线BL。第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接互补位线BLB。位线BL上连接有存储单元100，互补位线BLB上连接有存储单元100。存储单元100包括晶体管M1和电容C1。
灵敏放大器用于从存储单元100中读出数据。在从存储单元100中读出数据时，灵敏放大器的工作阶段包括预充电阶段T1、电荷共享阶段T4、感测放大阶段T5以及恢复阶段。
在预充电阶段T1，均衡模块300驱动位线BL和互补位线BLB至预充电电压VBLP。在电荷共享阶段T4，与位线BL连接的存储单元100内的晶体管M1开启，存储单元100内电容C1与位线BL电荷共享，在位线BL上产生电荷共享电压。在感测放大阶段T5，灵敏放大器放大位线BL和互补位线BLB上的电压差。在恢复阶段，恢复存储单元100中数据，并读出位线BL上的数据。
然而，灵敏放大器内晶体管会由于工艺变化、温度等原因，导致灵敏放大器内晶体管失配，例如：灵敏放大器内晶体管的尺寸不同或阈值电压不同，晶体管失配会引起失配噪声，造成数据读出失败的问题。
为解决上述问题，本公开一实施例提供一种灵敏放大器、控制方法及半导体存储器。
如图2所示，本公开一实施例提供一种灵敏放大器，灵敏放大器包括感测模块200和均衡模块300。感测模块200连接位线BL和互补位线BLB，均衡模块300连接位线BL和互补位线BLB。
在预充电阶段T1，均衡模块300驱动位线BL和互补位线BLB的电压均为预充电电压VBLP，在偏移消除阶段T2、正向驱动阶段T3、电荷共享阶段T4以及感测放大阶段T5，均衡模块300停止驱动位线BL和互补位线BLB。在偏移消除阶段T2，感测模块200在位线BL和互补位线BLB上生成补偿电压。在正向驱动阶段T3，感测模块200调整位线BL和互补位线BLB上的补偿电压。在电荷共享阶段T4，控制存储单元100与位线BL进行电荷共享。在感测放大阶段T5，感测模块200放大位线BL和互补位线BLB上的电压差。
在上述技术方案中，由均衡模块300在预充电阶段T1驱动位线BL和互补位线BLB的电压至预充电电压VBLP，在其他阶段停止驱动位线BL和互补位线BLB。在偏移消除阶段T2，感测模块200在位线BL和互补位线BLB上产生补偿电压，在正向驱动阶段T3，感测模块200调整位线BL和互补位线BLB上补偿电压。在电荷共享阶段T4，存储单元100与互补位线BLB进行电荷共享，在感测放大阶段T5，感测模块200放大位线BL和互补位线BLB上的电压差，实现准确读出数据。
在一些实施例中，如图2所示，感测模块200包括：第一开关单元210、第二开关单元220、第三开关单元230、第四开关单元240、第五开关单元250、第六开关单元260、第七开关单元270、第一P型晶体管P1、第二P型晶体管P2、第一N型晶体管N1以及第二N型晶体管N2。
第一P型晶体管P1的栅极连接第五开关单元250的第一端，第一P型晶体管P1的栅极还连接第六开关单元260的第一端，第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极，第一P型晶体管P1的源极连接第一电源端SAP。
第二P型晶体管P2的栅极连接第五开关单元250的第二端，第二P型晶体管P2的栅极还连接第 七开关单元270的第一端，第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极，第二P型晶体管P2的源极连接第一P型晶体管P1的源极。
第一N型晶体管N1的栅极连接互补位线BLB，第一N型晶体管N1的源极连接第二电源端SAN。第二N型晶体管N2的栅极连接位线BL，第二N型晶体管N2的源极连接第一N型晶体管N1的源极。
第五开关单元250的控制端接收第二隔离控制信号ISO2，第六开关单元260的第二端连接互补位线BLB，第六开关单元260的控制端接收第三隔离控制信号ISO3。第七开关单元270的第二端连接位线BL，第七开关单元270的控制端接收第三隔离控制信号ISO3。
第一开关单元210的第一端连接第一N型晶体管N1的漏极，第一开关单元210的第二端连接第一N型晶体管N1的栅极，第一开关单元210的控制端接收偏移消除信号OC。
第二开关单元220的第一端连接第二N型晶体管N2的栅极，第二开关单元220的第二端连接第二N型晶体管N2的漏极，第二开关单元220的控制端接收偏移消除信号OC。
第三开关单元230的第一端连接第一N型晶体管N1的漏极，第三开关单元230的第二端连接第二P型晶体管P2的栅极，第三开关单元230的控制端接收第一隔离控制信号ISO1。
第四开关单元240的第一端连接第一P型晶体管P1的栅极，第四开关单元240的第二端连接第二N型晶体管N2的漏极，第四开关单元240的控制端接收第一隔离控制信号ISO1。
本公开一实施例提供一种灵敏放大器的控制方法，灵敏放大器包括预充电阶段T1、偏移消除阶段T2、正向驱动阶段T3、电荷共享阶段T4以及感测放大阶段。该控制方法包括如下步骤：
S101、控制均衡模块300在预充电阶段T1驱动位线BL和互补位线BLB的电压均为预充电电压VBLP。
S102、控制感测模块200在偏移消除阶段T2时在位线BL和互补位线BLB上生成补偿电压。
S103、控制感测模块200在正向驱动阶段T3调整位线BL和互补位线BLB上的补偿电压。
S103、控制存储单元100在电荷共享阶段T4与位线BL进行电荷共享。
S104、控制感测模块200在感测放大阶段T5放大位线BL和互补位线BLB上的电压差。
其中，如图3和图4所示，在S101，在预充电阶段T1，控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，字线关闭，控制存储单元100内的晶体管M1截止。
控制第一开关单元210使第一N型晶体管N1的栅极和漏极断开，控制第二开关单元220使第二N型晶体管N2的栅极和漏极断开，控制第三开关单元230使第一N型晶体管N1的漏极和第二P型晶体管P2的栅极接通，控制第四开关单元240使第二N型晶体管N2的漏极和第一P型晶体管P1的栅极接通，控制第五开关单元250使第一P型晶体管P1的栅极与第二P型晶体管P2的栅极断开，控制第六开关单元260使第一P型晶体管P1的栅极与互补位线BLB导通，控制第七开关单元270使第二P型晶体管P2的栅极与位线BL断开导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接互补位线BLB位线BL。
控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，均衡模块300驱动位线BL的电压和互补位线BLB的电压均至预充电电压VBLP。
其中，如图3和图5所示，S102，在偏移消除阶段T2，控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，字线关闭，控制存储单元100内的晶体管M1截止。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一开关单元210使第一N型晶体管 N1的栅极和漏极接通，控制第二开关单元220使第二N型晶体管N2的栅极和漏极接通。控制第三开关单元230使第一N型晶体管N1的漏极和第二P型晶体管P2的栅极断开，控制第四开关单元240使第二N型晶体管N2的漏极和第一P型晶体管P1的栅极断开。控制第五开关单元250使第一P型晶体管P1的栅极与第二P型晶体管P2的栅极断开。控制第六开关单元260使第一P型晶体管P1的栅极与互补位线BLB接通，控制第七开关单元270使第二P型晶体管P2的栅极与位线BL接通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一N型晶体管N1的栅极连接第一N型晶体管N1的漏极。第二N型晶体管N2的栅极连接第二N型晶体管N2的漏极。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，控制感测模块200在位线BL和互补位线BLB上产生补偿电压。
其中，如图3和图6所示，S103，在正向驱动阶段T3，控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS。字线关闭，控制存储单元100内的晶体管M1截止。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一开关单元210使第一N型晶体管N1的栅极和漏极接通，控制第二开关单元220使第二N型晶体管N2的栅极和漏极接通。控制第三开关单元230使第一N型晶体管N1的漏极和第二P型晶体管P2的栅极断开，控制第四开关单元240使第二N型晶体管N2的漏极和第一P型晶体管P1的栅极断开。控制第五开关单元250使第一P型晶体管P1的栅极与第二P型晶体管P2的栅极接通，控制第六开关单元260使第一P型晶体管P1的栅极与互补位线BLB断开，控制第七开关单元270使第二P型晶体管P2的栅极与位线BL断开。
通过如此设置，将第一P型晶体管P1的栅极与互补位线BLB断开，将第二P型晶体管P2的栅极与位线BL断开，将第一P型晶体管P1的栅极连接第二P型晶体管P2的栅极。第一N型晶体管N1的栅极连接第一N型晶体管N1的漏极。第二N型晶体管N2的栅极连接第二N型晶体管N2的漏极。控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，感测模块200进一步调整位线BL和互补位线BLB上的补偿电压。
例如：在偏移消除阶段T2，位线BL电压大于互补位线BLB电压，位线BL电压和互补位线BLB电压之间差值为补偿电压。也就是，在偏移消除阶段T2，第二P型晶体管P2的栅极电压大于第一P型晶体管P1的栅极电压。
在正向驱动阶段T3，将第一P型晶体管P1的栅极连接第二P型晶体管P2的栅极，第一P型晶体管P1的栅极电压上升，第一P型晶体管P1的漏极电压和第一N型晶体管N1的漏极电压下降，互补位线BLB的电压下降。第二P型晶体管P2的栅极电压下降，第二P型晶体管P2的漏极电压和第二N型晶体管N2的漏极电压上升，位线BL的电压上升，实现进一步放大位线BL和互补位线BLB上的补偿电压。
例如：在偏移消除阶段T2，位线BL电压小于互补位线BLB电压，位线BL电压和互补位线BLB电压之间差值为补偿电压。也就是，在偏移消除阶段T2，第二P型晶体管P2的栅极电压小于第一P型晶体管P1的栅极电压。
在正向驱动阶段T3，将第一P型晶体管P1的栅极连接第二P型晶体管P2的栅极，第一P型晶体管P1的栅极电压下降，第一P型晶体管P1的漏极电压和第一N型晶体管N1的漏极电压上升，互补位线BLB的电压上升。第二P型晶体管P2的栅极电压上升，第二P型晶体管P2的漏极电压和第 二N型晶体管N2的漏极电压下降，位线BL的电压下降，实现进一步放大位线BL和互补位线BLB上的补偿电压。
其中，如图3和图7所示，S104，在电荷共享阶段T4，控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，字线开启，控制存储单元100内的晶体管M1导通。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一开关单元210使第一N型晶体管N1的栅极和漏极断开，控制第二开关单元220使第二N型晶体管N2的栅极和漏极断开。控制第三开关单元230使第一N型晶体管N1的漏极和第二P型晶体管P2的栅极接通，控制第四开关单元240使第二N型晶体管N2的漏极和第一P型晶体管P1的栅极接通。控制第五开关单元250使第一P型晶体管P1的栅极与第二P型晶体管P2的栅极断开。控制第六开关单元260使第一P型晶体管P1的栅极与互补位线BLB接通，控制第七开关单元270使第二P型晶体管P2的栅极与位线BL断开接通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接互补位线BLB位线BL。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，开启存储单元100中晶体管，使存储单元100内电容C1和位线BL之间进行电荷共享。
其中，如图3和图8所示，S105，在感测放大阶段T5，控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS。字线开启，控制存储单元100内的晶体管M1导通。
控制均衡模块300停止驱动位线BL和互补位线BLB，控制第一开关单元210使第一N型晶体管N1的栅极和漏极断开，控制第二开关单元220使第二N型晶体管N2的栅极和漏极断开，控制第三开关单元230使第一N型晶体管N1的漏极和第二P型晶体管P2的栅极接通，控制第四开关单元240使第二N型晶体管N2的漏极和第一P型晶体管P1的栅极接通，控制第五开关单元250使第一P型晶体管P1的栅极与第二P型晶体管P2的栅极断开，控制第六开关单元260使第一P型晶体管P1的栅极与互补位线BLB导通，控制第七开关单元270使第二P型晶体管P2的栅极与位线BL断开导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接互补位线BLB位线BL。
控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，开启存储单元100中晶体管，使感测模块200放大位线BL和互补位线BLB上的电压差。
在一些实施例中，第一开关单元210包括第三N型晶体管N3，第三N型晶体管N3的漏极为第一开关单元210的第一端，第三N型晶体管N3的源极为第一开关单元210的第二端，第三N型晶体管N3的栅极为第一开关单元210的控制端，第三N型晶体管N3的栅极接收偏移消除信号OC，第三N型晶体管N3根据偏移消除信号OC控制第一N型晶体管N1的栅极和漏极是否接通。
第二开关单元220包括第四N型晶体管N4，第四N型晶体管N4的源极为第二开关单元220的第一端，第四N型晶体管N4的漏极为第二开关单元220的第二端，第四N型晶体管N4的栅极为第二开关单元220的控制端，第四N型晶体管N4的栅极接收偏移消除信号OC，第四N型晶体管N4根据偏移消除信号OC控制第二N型晶体管N2的栅极和漏极是否接通。
在一些实施例中，第三开关单元230包括第五N型晶体管N5，第五N型晶体管N5的源极或漏极为第三开关单元230的第一端，第五N型晶体管N5的漏极或源极为第三开关单元230的第二端，第五N型晶体管N5的栅极为第三开关单元230的控制端，第五N型晶体管N5的栅极接收第一隔离控制信号ISO1，第五N型晶体管N5和第九N型晶体管N9共同控制第一N型晶体管N1的漏极和位线BL是否接通。
第四开关单元240包括第六N型晶体管N6，第六N型晶体管N6的源极或漏极为第四开关单元240的第一端，第六N型晶体管N6的漏极或源极为第四开关单元240的第二端，第六N型晶体管N6的栅极为第四开关单元240的控制端，第六N型晶体管N6的栅极接收第一隔离控制信号ISO1，第六N型晶体管N6和第八N型晶体管N8共同控制第二N型晶体管N2的漏极和互补位线BLB是否接通。
在一些实施例中，第五开关单元250包括第七N型晶体管N7，第七N型晶体管N7的漏极或源极为第五开关单元250的第一端，第七N型晶体管N7的源极或漏极为第五开关单元250的第二端，第七N型晶体管N7的栅极为第五开关单元250的控制端，第七N型晶体管N7的栅极接收第二隔离控制信号ISO2，根据所第二隔离控制信号ISO2控制第一P型晶体管P1的栅极和第二P型晶体管P2的栅极是否接通。
在一些实施例中，第六开关单元260包括第八N型晶体管N8，第八N型晶体管N8的漏极为第六开关单元260的第一端，第八N型晶体管N8的源极为第六开关单元260的第二端，第八N型晶体管N8的栅极为第六开关单元260的控制端，第八N型晶体管N8的栅极接收第三隔离控制信号ISO3，第八N型晶体管N8的根据第三隔离控制信号ISO3控制第一P型晶体管P1的栅极和互补位线BLB是否接通。
第七开关单元270包括第九N型晶体管N9，第九N型晶体管N9的漏极为第七开关单元270的第一端，第九N型晶体管N9的源极为第七开关单元270的第二端，第九N型晶体管N9的栅极为第七开关单元270的控制端，第九N型晶体管N9的栅极接收第三隔离控制信号ISO3，第九N型晶体管N9根据第三隔离控制信号ISO3控制第二P型晶体管P2的栅极和位线BL是否接通。
在一些实施例中，均衡模块300包括第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12。
第十N型晶体管N10的第一端连接位线BL，第十N型晶体管N10的第二端连接第十一N型晶体管N11的第一端后连接充电电源端，第十N型晶体管N10的栅极接收预充电信号BLEQ。第十一N型晶体管N11的第二端连接互补位线BLB，第十一N型晶体管N11的栅极连接第十N型晶体管N10的栅极。第十二N型晶体管N12的第一端连接位线BL，第十二N型晶体管N12的第二端连接互补位线BLB，第十二N型晶体管N12的栅极连接第十N型晶体管N10的栅极。
通过控制第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12导通，使位线BL和互补位线BLB充电至预充电电压VBLP。
在一些实施例中，如图3和图4所示，预充电信号BLEQ在预充电阶段T1为高电平，第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12均导通。偏移消除信号OC在预充电阶段T1为低电平，第三N型晶体管N3和第四N型晶体管N4均截止。第一隔离控制信号ISO1在预充电阶段T1为高电平，第五N型晶体管N5和第六N型晶体管N6均导通。第二隔离控制信号ISO2在预充电阶段T1为低电平，第七N型晶体管N7截止。第三隔离控制信号ISO3在预充电阶段T1为高电平，第八N型晶体管N8和第九N型晶体管N9均导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型 晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接互补位线BLB位线BL。
字线信号为低电平，字线关闭，存储单元100内的晶体管M1截止。控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，均衡模块300驱动位线BL的电压和互补位线BLB的电压均至预充电电压VBLP。
在一些实施例中，如图3和图5所示，预充电信号BLEQ在偏移消除阶段T2为低电平，第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12均截止。偏移消除信号OC在偏移消除阶段T2为高电平，第三N型晶体管N3和第四N型晶体管N4均导通。第一隔离控制信号ISO1在偏移消除阶段T2为低电平，第五N型晶体管N5和第六N型晶体管N6均截止。第二隔离控制信号ISO2在偏移消除阶段T2为低电平，第七N型晶体管N7截止。第三隔离控制信号ISO3在偏移消除阶段T2为高电平，第八N型晶体管N8和第九N型晶体管N9均导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一N型晶体管N1的栅极连接第一N型晶体管N1的漏极。第二N型晶体管N2的栅极连接第二N型晶体管N2的漏极。
字线信号为低电平，字线关闭，存储单元100内的晶体管M1截止。控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，控制感测模块200在位线BL和互补位线BLB上产生补偿电压。
在一些实施例中，如图3和图6所示，预充电信号BLEQ在正向驱动阶段T3为低电平，第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12均截止。偏移消除信号OC在正向驱动阶段T3为高电平，第三N型晶体管N3和第四N型晶体管N4均导通。第一隔离控制信号ISO1在正向驱动阶段T3为低电平，第五N型晶体管N5和第六N型晶体管N6均截止。第二隔离控制信号ISO2在正向驱动阶段T3为高电平，第七N型晶体管N7导通。第三隔离控制信号ISO3在正向驱动阶段T3为低电平，第八N型晶体管N8和第九N型晶体管N9均截止。
通过如此设置，实现将第一P型晶体管P1的栅极与互补位线BLB断开，将第二P型晶体管P2的栅极与位线BL断开，将第一P型晶体管P1的栅极连接第二P型晶体管P2的栅极。第一N型晶体管N1的栅极连接第一N型晶体管N1的漏极。第二N型晶体管N2的栅极连接第二N型晶体管N2的漏极。
字线信号为低电平，字线关闭，存储单元100内的晶体管M1截止。控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，感测模块200进一步调整位线BL和互补位线BLB上的补偿电压。
在一些实施例中，如图3和图7所示，预充电信号BLEQ在电荷共享阶段T4为低电平，第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12均截止。偏移消除信号OC在电荷共享阶段T4为低电平，第三N型晶体管N3和第四N型晶体管N4均截止。第一隔离控制信号ISO1在电荷共享阶段T4为高电平，第五N型晶体管N5和第六N型晶体管N6均导通。第二隔离控制信号ISO2在电荷共享阶段T4为低电平，第七N型晶体管N7截止。第三隔离控制信号ISO3在电荷共享阶段T4为高电平，第八N型晶体管N8和第九N型晶体管N9均导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连 接第二N型晶体管N2的漏极后，连接互补位线BLB。
字线信号为高电平，字线开启，存储单元100内的晶体管M1导通。控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压和第二电源端SAN的电压为预充电电压VBLP，开启存储单元100中晶体管，使存储单元100内电容C1和位线BL之间进行电荷共享。
在一些实施例中，如图3和图8所示，预充电信号BLEQ在感测放大阶段T5为低电平，第十N型晶体管N10、第十一N型晶体管N11以及第十二N型晶体管N12均截止。偏移消除信号OC在感测放大阶段T5为低电平，第三N型晶体管N3和第四N型晶体管N4均截止。第一隔离控制信号ISO1在感测放大阶段T5为高电平，第五N型晶体管N5和第六N型晶体管N6均导通。第二隔离控制信号ISO2在感测放大阶段T5为低电平，第七N型晶体管N7截止。第三隔离控制信号ISO3在感测放大阶段T5为高电平，第八N型晶体管N8和第九N型晶体管N9均导通。
通过如此设置，实现将第一P型晶体管P1的栅极连接第一N型晶体管N1的栅极后，连接互补位线BLB。将第二P型晶体管P2的栅极连接第二N型晶体管N2的栅极后，连接位线BL。第一P型晶体管P1的漏极连接第一N型晶体管N1的漏极后，连接位线BL。将第二P型晶体管P2的漏极连接第二N型晶体管N2的漏极后，连接互补位线BLB。
字线信号为高电平，字线开启，存储单元100内的晶体管M1导通。控制均衡模块300停止驱动位线BL和互补位线BLB。控制第一电源端SAP的电压为电源电压VDD，第二电源端SAN的电压为接地电压VSS，感测模块200放大位线BL和互补位线BLB上的电压差。
在上述技术方案中，在预充电阶段T1，均衡模块300驱动位线BL和互补位线BLB电压至预充电电压VBLP，在偏移消除阶段T2，感测模块200在位线BL和互补位线BLB上产生补偿电压后，在正向驱动阶段T3，使第一P型晶体管P1的栅极和第二P型晶体管P2的栅极接通，第一N型晶体管N1的栅极连接其漏极，第二N型晶体管N2的栅极连接其漏极，通过如此设置，可以通过在正向驱动阶段T3调整第一P型晶体管P1的栅极电压和第二P型晶体管P2的栅极电压，调节第一N型晶体管N1的漏极电压和第二N型晶体管N2的漏极电压，实现调整位线BL和互补位线BLB上补偿电压。在电荷共享阶段T4，存储单元100内电容C1与互补位线BLB进行电荷共享，在感测放大阶段T5，感测模块200放大位线BL和互补位线BLB上的电压差，实现准确读出数据。
本公开一实施例提供一种控制器，用于实现上述实施例所涉及的灵敏放大器的控制方法。
本公开一实施例提供一种半导体存储器，包括上述实施例所涉及的灵敏放大器。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (16)

  1. 一种灵敏放大器，包括：感测模块和均衡模块；
    所述感测模块连接位线和互补位线，所述均衡模块连接所述位线和所述互补位线；
    所述均衡模块在预充电阶段驱动所述位线和所述互补位线的电压均为预充电电压；所述感测模块在偏移消除阶段在所述位线和所述互补位线上生成补偿电压，在正向驱动阶段调整所述位线和所述互补位线上的补偿电压，在电荷共享阶段控制存储单元与所述位线进行电荷共享，在感测放大阶段放大所述位线和所述互补位线上的电压差。
  2. 根据权利要求1所述的灵敏放大器，其中，所述感测模块包括：第一开关单元、第二开关单元、第三开关单元、第四开关单元、第五开关单元、第六开关单元、第七开关单元、第一P型晶体管、第二P型晶体管、第一N型晶体管以及第二N型晶体管；
    所述第一P型晶体管，其栅极连接所述第五开关单元的第一端，其栅极还连接所述第六开关单元的第一端，其漏极连接所述第一N型晶体管的漏极，其源极连接第一电源端；
    所述第二P型晶体管，其栅极连接所述第五开关单元的第二端，其栅极还连接所述第七开关单元的第一端，其漏极连接所述第二N型晶体管的漏极，其源极连接所述第一P型晶体管的源极；
    所述第五开关单元的控制端接收第二隔离控制信号；
    所述第六开关单元，其第二端连接所述互补位线，其控制端接收第三隔离控制信号；
    所述第七开关单元，其第二端连接所述位线，其控制端接收所述第三隔离控制信号；
    所述第一N型晶体管，其栅极连接所述互补位线，其源极连接第二电源端；
    所述第二N型晶体管，其栅极连接所述位线，其源极连接所述第一N型晶体管的源极；
    所述第一开关单元，其第一端连接所述第一N型晶体管的漏极，其第二端连接所述第一N型晶体管的栅极，其控制端接收偏移消除信号；
    所述第二开关单元，其第一端连接所述第二N型晶体管的栅极，其第二端连接所述第二N型晶体管的漏极，其控制端接收所述偏移消除信号；
    所述第三开关单元，其第一端连接所述第一N型晶体管的漏极，其第二端连接所述第二P型晶体管的栅极，其控制端接收第一隔离控制信号；
    所述第四开关单元，其第一端连接所述第一P型晶体管的栅极，其第二端连接所述第二N型晶体管的漏极，其控制端接收所述第一隔离控制信号。
  3. 根据权利要求2所述的灵敏放大器，其中，所述第五开关单元包括：
    第七N型晶体管，其漏极或源极为所述第五开关单元的第一端，其源极或漏极为所述第五开关单元的第二端，其栅极为所述第五开关单元的控制端，用于接收所述第二隔离控制信号，根据所第二隔离控制信号控制所述第一P型晶体管的栅极和第二P型晶体管的栅极是否接通。
  4. 根据权利要求2所述的灵敏放大器，其中，
    所述第六开关单元包括：
    第八N型晶体管，其漏极为所述第六开关单元的第一端，其源极为所述第六开关单元的第二端，其栅极为所述第六开关单元的控制端，用于接收所述第三隔离控制信号，根据所述第三隔离控制信号控制所述第一P型晶体管的栅极和所述互补位线是否接通；
    所述第七开关单元包括：
    第九N型晶体管，其漏极为所述第七开关单元的第一端，其源极为所述第七开关单元的第二端，其栅极为所述第七开关单元的控制端，用于接收所述第三隔离控制信号，根据所述第三隔离控制信号 控制所述第二P型晶体管的栅极和所述位线是否接通。
  5. 根据权利要求4所述的灵敏放大器，其中，
    所述第一开关单元包括：
    第三N型晶体管，其漏极为所述第一开关单元的第一端，其源极为所述第一开关单元的第二端，其栅极为所述第一开关单元的控制端，用于接收所述偏移消除信号，根据所述偏移消除信号控制所述第一N型晶体管的栅极和漏极是否接通；
    所述第二开关单元包括：
    第四N型晶体管，其源极为所述第二开关单元的第一端，其漏极为所述第二开关单元的第二端，其栅极为所述第二开关单元的控制端，用于接收所述偏移消除信号，根据所述偏移消除信号控制所述第二N型晶体管的栅极和漏极是否接通。
  6. 根据权利要求4所述的灵敏放大器，其中，
    所述第三开关单元包括：
    第五N型晶体管，其源极或漏极为所述第三开关单元的第一端，其漏极或源极为所述第三开关单元的第二端；其栅极为所述第三开关单元的控制端，接收所述第一隔离控制信号，所述第五N型晶体管和所述第九N型晶体管共同控制所述第一N型晶体管的漏极和所述位线是否接通；
    所述第四开关单元包括：
    第六N型晶体管，其源极或漏极为所述第四开关单元的第一端，其漏极或源极为所述第四开关单元的第二端，其栅极为所述第四开关单元的控制端，接收所述第一隔离控制信号，所述第六N型晶体管和所述第八N型晶体管共同控制所述第二N型晶体管的漏极和所述互补位线是否接通。
  7. 根据权利要求1所述的灵敏放大器，其中，所述均衡模块包括：
    第十N型晶体管，其第一端连接所述位线，其第二端连接第十一N型晶体管的第一端且连接充电电源端，其栅极接收预充电信号；
    所述第十一N型晶体管，其第二端连接所述互补位线，其栅极连接所述第十N型晶体管的栅极；
    第十二N型晶体管，其第一端连接所述位线，其第二端连接所述互补位线，其栅极连接所述第十N型晶体管的栅极。
  8. 一种灵敏放大器的控制方法，所述灵敏放大器包括感测模块和均衡模块，所述灵敏放大器的工作阶段包括预充电阶段、偏移消除阶段、正向驱动阶段、电荷共享阶段以及感测放大阶段；所述方法包括：
    控制所述均衡模块在所述预充电阶段驱动位线和互补位线的电压均为预充电电压；
    控制所述感测模块在所述偏移消除阶段在所述位线和所述互补位线上生成补偿电压；
    控制所述感测模块在所述正向驱动阶段调整所述位线和所述互补位线上的补偿电压；
    在所述电荷共享阶段控制存储单元与所述位线进行电荷共享；
    控制所述感测模块在所述感测放大阶段放大所述位线和所述互补位线上的电压差。
  9. 根据权利要求8所述的控制方法，其中，所述感测模块包括第一开关单元、第二开关单元、第三开关单元、第四开关单元、第五开关单元、第六开关单元、第七开关单元、第一P型晶体管、第二P型晶体管、第一N型晶体管以及第二N型晶体管；
    所述第一P型晶体管的栅极连接所述第五开关单元的第一端，所述第一P型晶体管的栅极还连接所述第六开关单元的第一端，所述第一P型晶体管的漏极连接所述第一N型晶体管的漏极，所述第一P型晶体管的源极连接第一电源端；
    所述第二P型晶体管的栅极连接所述第五开关单元的第二端，所述第二P型晶体管的栅极还连接 所述第七开关单元的第一端，所述第二P型晶体管的漏极连接所述第二N型晶体管的漏极，所述第二P型晶体管的源极连接所述第一P型晶体管的源极；
    所述第五开关单元的控制端接收第二隔离控制信号；
    所述第六开关单元的第二端连接所述互补位线，所述第六开关单元的控制端接收第三隔离控制信号；所述第七开关单元的第二端连接所述位线，所述第七开关单元的控制端接收所述第三隔离控制信号；
    所述第一N型晶体管的栅极连接所述互补位线，所述第一N型晶体管的源极连接第二电源端；
    所述第二N型晶体管的栅极连接所述位线，所述第二N型晶体管的源极连接所述第一N型晶体管的源极；
    所述第一开关单元的第一端连接所述第一N型晶体管的漏极，所述第一开关单元的第二端连接所述第一N型晶体管的栅极，所述第一开关单元的控制端接收偏移消除信号；
    所述第二开关单元的第一端连接所述第二N型晶体管的栅极，所述第二开关单元的第二端连接所述第二N型晶体管的漏极，所述第二开关单元的控制端接收所述偏移消除信号；
    所述第三开关单元的第一端连接所述第一N型晶体管的漏极，所述第三开关单元的第二端连接所述第二P型晶体管的栅极，所述第三开关单元的控制端接收第一隔离控制信号；
    所述第四开关单元的第一端连接所述第一P型晶体管的栅极，所述第四开关单元的第二端连接所述第二N型晶体管的漏极，所述第四开关单元的控制端接收所述第一隔离控制信号；
    控制所述感测模块在偏移消除阶段在所述位线和所述互补位线上生成补偿电压，具体包括：
    在所述偏移消除阶段，控制所述第一电源端的电压为电源电压，所述第二电源端的电压为接地电压；控制所述存储单元内晶体管截止；
    控制所述均衡模块停止驱动所述位线和所述互补位线，控制所述第一开关单元使所述第一N型晶体管的栅极和漏极接通，控制所述第二开关单元使所述第二N型晶体管的栅极和漏极接通，控制所述第三开关单元使所述第一N型晶体管的漏极和所述第二P型晶体管的栅极断开，控制所述第四开关单元使所述第二N型晶体管的漏极和所述第一P型晶体管的栅极断开，控制所述第五开关单元使所述第一P型晶体管的栅极与所述第二P型晶体管的栅极断开，控制所述第六开关单元使所述第一P型晶体管的栅极与所述互补位线接通，控制所述第七开关单元使所述第二P型晶体管的栅极与所述位线接通。
  10. 根据权利要求9所述的控制方法，其中，控制所述感测模块在所述正向驱动阶段调整所述位线和所述互补位线上的补偿电压，具体包括：
    在所述正向驱动阶段，控制所述第一电源端的电压为电源电压，所述第二电源端的电压为接地电压；控制所述存储单元内晶体管截止；
    控制所述均衡模块停止驱动所述位线和所述互补位线，控制所述第一开关单元使所述第一N型晶体管的栅极和漏极接通，控制所述第二开关单元使所述第二N型晶体管的栅极和漏极接通，控制所述第三开关单元使所述第一N型晶体管的漏极和所述第二P型晶体管的栅极断开，控制所述第四开关单元使所述第二N型晶体管的漏极和所述第一P型晶体管的栅极断开，控制所述第五开关单元使所述第一P型晶体管的栅极与所述第二P型晶体管的栅极接通，控制所述第六开关单元使所述第一P型晶体管的栅极与所述互补位线断开，控制所述第七开关单元使所述第二P型晶体管的栅极与所述位线断开。
  11. 根据权利要求9所述的控制方法，其中，在所述电荷共享阶段控制存储单元与所述位线进行电荷共享，具体包括：
    在所述电荷共享阶段，控制所述第一电源端的电压和所述第二电源端的电压为预充电电压；控制所述存储单元内晶体管导通；
    控制所述均衡模块停止驱动所述位线和所述互补位线，控制所述第一开关单元使所述第一N型晶体管的栅极和漏极断开，控制所述第二开关单元使所述第二N型晶体管的栅极和漏极断开，控制所述第三开关单元使所述第一N型晶体管的漏极和所述第二P型晶体管的栅极接通，控制所述第四开关单元使所述第二N型晶体管的漏极和所述第一P型晶体管的栅极接通，控制所述第五开关单元使所述第一P型晶体管的栅极与所述第二P型晶体管的栅极断开，控制所述第六开关单元使所述第一P型晶体管的栅极与所述互补位线接通，控制所述第七开关单元使所述第二P型晶体管的栅极与所述位线接通。
  12. 根据权利要求9所述的控制方法，其中，控制所述感测模块在所述感测放大阶段放大所述位线和所述互补位线上的电压差，具体包括：
    在所述感测放大阶段，控制所述第一电源端的电压为电源电压，所述第二电源端的电压为接地电压；控制所述存储单元内晶体管导通；
    控制所述均衡模块停止驱动所述位线和所述互补位线，控制所述第一开关单元使所述第一N型晶体管的栅极和漏极断开，控制所述第二开关单元使所述第二N型晶体管的栅极和漏极断开，控制所述第三开关单元使所述第一N型晶体管的漏极和所述第二P型晶体管的栅极接通，控制所述第四开关单元使所述第二N型晶体管的漏极和所述第一P型晶体管的栅极接通，控制所述第五开关单元使所述第一P型晶体管的栅极与所述第二P型晶体管的栅极断开，控制所述第六开关单元使所述第一P型晶体管的栅极与所述互补位线接通，控制所述第七开关单元使所述第二P型晶体管的栅极与所述位线接通。
  13. 根据权利要求9所述的控制方法，其中，所述均衡模块包括第十N型晶体管、第十一N型晶体管以及第十二N型晶体管；
    所述第十N型晶体管的第一端连接所述位线，所述第十N型晶体管的第二端连接第十一N型晶体管的第一端且连接充电电源端，所述第十N型晶体管的栅极接收预充电信号；
    所述第十一N型晶体管的第二端连接所述互补位线，所述第十一N型晶体管的栅极连接所述第十N型晶体管的栅极；所述第十二N型晶体管的第一端连接所述位线，所述第十二N型晶体管的第二端连接所述互补位线，所述第十二N型晶体管的栅极连接所述第十N型晶体管的栅极；
    控制所述均衡模块在预充电阶段驱动所述位线和所述互补位线的电压均为预充电电压，具体包括：
    控制所述第十N型晶体管、所述第十一N型晶体管以及所述第十二N型晶体管导通，使所述位线和所述互补位线充电至所述预充电电压；
    控制所述第一电源端的电压和所述第二电源端的电压为预充电电压，控制所述存储单元内晶体管截止；
    控制所述第一开关单元使所述第一N型晶体管的栅极和漏极断开，控制所述第二开关单元使所述第二N型晶体管的栅极和漏极断开，控制所述第三开关单元使所述第一N型晶体管的漏极和所述第二P型晶体管的栅极接通，控制所述第四开关单元使所述第二N型晶体管的漏极和所述第一P型晶体管的栅极接通，控制所述第五开关单元使所述第一P型晶体管的栅极与所述第二P型晶体管的栅极断开，控制所述第六开关单元使所述第一P型晶体管的栅极与所述互补位线接通，控制所述第七开关单元使所述第二P型晶体管的栅极与所述位线接通。
  14. 根据权利要求9所述的控制方法，其中，所述第一开关单元包括第三N型晶体管，所述第二开关单元包括第四N型晶体管，所述第三开关单元包括第五N型晶体管，所述第四开关单元包括第六N晶体管，所述第五开关单元包括第七N晶体管，所述第六开关单元包括第八N晶体管，所述第七开关单元包括第九N晶体管；
    所述预充电信号在所述预充电阶段为高电平，所述预充电信号在所述偏移消除阶段、所述正向驱动阶段、所述电荷共享阶段以及所述感测放大阶段为低电平；
    所述偏移消除信号在所述偏移消除阶段和所述正向驱动阶段为高电平，所述偏移消除信号在所述预充电阶段、所述电荷共享阶段以及所述感测放大阶段均为低电平；
    所述第一隔离控制信号在所述偏移消除阶段和正向驱动阶段为低电平，所述第一隔离控制信号在所述预充电阶段、所述电荷共享阶段以及所述感测放大阶段均为高电平；
    所述第二隔离控制信号在所述正向驱动阶段为高电平，所述第二隔离控制信号在所述预充电阶段、所述偏移消除阶段、所述电荷共享阶段以及所述感测放大阶段均为低电平；
    所述第三隔离控制信号在所述正向驱动阶段为低电平，所述第三隔离控制信号在所述预充电阶段、所述偏移消除阶段、所述电荷共享阶段以及所述感测放大阶段均为高电平。
  15. 一种控制器，用于实现如权利要求8至14中任意一项所述的灵敏放大器的控制方法。
  16. 一种半导体存储器，包括如权利要求1至7中任意一项所述的灵敏放大器。
PCT/CN2022/123952 2022-08-10 2022-10-09 灵敏放大器、控制方法及半导体存储器 Ceased WO2024031815A1 (zh)

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