WO2024031287A1 - 一种数据处理方法、装置及设备 - Google Patents

一种数据处理方法、装置及设备 Download PDF

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WO2024031287A1
WO2024031287A1 PCT/CN2022/110969 CN2022110969W WO2024031287A1 WO 2024031287 A1 WO2024031287 A1 WO 2024031287A1 CN 2022110969 W CN2022110969 W CN 2022110969W WO 2024031287 A1 WO2024031287 A1 WO 2024031287A1
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block
sub
encoded
data corresponding
coding
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PCT/CN2022/110969
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English (en)
French (fr)
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童佳杰
张华滋
王献斌
李榕
王俊
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华为技术有限公司
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Priority to PCT/CN2022/110969 priority Critical patent/WO2024031287A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems

Definitions

  • the present application relates to the field of communication technology, and in particular, to a data processing method, device and equipment.
  • Polar code is a channel coding scheme that can be strictly proven to "reach" Shannon channel capacity. It has the characteristics of good performance and low complexity, and can be applied to the fifth generation (the 5th generation, 5G) communications. systems and future communication systems.
  • the mother code length of the Polar code is an integer power of 2 (that is, 2 n ).
  • the code length N required for actual communication is not the mother code length (for example, it is not 2 n ), further puncturing and retransmission are required.
  • the code length matching process is implemented in other ways to achieve rate matching. For ordinary Polar codes, existing protocol standards specify a sequence construction method and a rate matching mode based on sub-block interleaving.
  • the construction method of this sequence is only suitable for coding matrices with a mother code length of 2 n .
  • For coding matrices with a mother code length other than 2 n currently it can only be constructed through Gaussian approximation. There is no fast and flexible construction method and corresponding rate matching. model.
  • This application provides a data processing method, device and equipment.
  • This method can quickly construct information bits and rate match coded data whose mother code length is not an integer multiple of 2n .
  • the construction method is simple and effective, and is conducive to improving the system. performance.
  • this application provides a data processing method, which can be executed by a terminal device or a network device.
  • the terminal device taking the terminal device as the execution subject and the terminal device as the encoding side as an example, the terminal device obtains K information bits, and determines the length of the block to be encoded based on the K, and determines the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • the terminal device encodes the block to be encoded, obtains the encoded data, and sends the encoded data.
  • an information bit construction and encoding method based on allocation sequence is designed.
  • the information bit construction method is simple and effective, which is beneficial to improving system performance and reducing system power consumption.
  • the block to be encoded includes m sub-blocks to be encoded
  • the allocation sequence includes S-1 variables ⁇ A 0 ,A 1 ,A 2 ,...,A S-2 ⁇ ; the relationship between the elements in the allocation sequence is A 0 ⁇ A 1 ⁇ ... ⁇ A S -2 .
  • the length of the block to be encoded and the number of sub-blocks to be encoded in the block to be encoded are designed, thereby determining the number of encoding sub-blocks, and the size of the encoding sub-block is designed to be 2 n , so that the code rate and encoding sub-block are
  • the size of the blocks is fixed, which facilitates the construction of information bits based on the allocation sequence.
  • An allocation sequence was also designed to support simpler construction of information bits.
  • this method can support information bit construction and rate matching when the length of the coding sub-block is less than an integer multiple of 2n .
  • the length of each sub-block to be encoded is:
  • the terminal device determines the number of information bits for each sub-block to be encoded in the block to be encoded based on the length and allocation sequence of the block to be encoded, which may specifically include:
  • the length of the sub-block to be encoded and the number of information bits of each sub-block to be encoded in the block to be encoded are designed, which can support the construction of information bits under the encoding matrix G'.
  • the length of each sub-block to be encoded is:
  • the terminal device determines the number of information bits for each sub-block to be encoded in the block to be encoded based on the length and allocation sequence of the block to be encoded, which may specifically include:
  • the A m-2 is the m-2 element in the allocation sequence, and the ⁇ 2 is determined based on the difference between the E m-2 and the N′, and the value is 0 or 1; or,
  • the length of the sub-block to be encoded and the number of information bits of each sub-block to be encoded in the block to be encoded are designed, which can support the construction of information bits under the encoding matrix G.
  • the terminal device encodes the to-be-encoded block to obtain encoded data, which may specifically include:
  • the K information bits are divided into m sub-segments
  • the K information bits are inserted into the sequence to be encoded, and the sequence to be encoded and the encoding matrix are subjected to modular square multiplication processing to obtain encoded data.
  • the encoding matrix is
  • the G is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), the m and the n are positive integers,
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n ,
  • the matrix O is an all-zero matrix with a size of 2 n ⁇ 2 n .
  • a new Polar code encoding matrix G is designed.
  • the terminal device uses the encoding matrix G to encode the information bits to be encoded, it can receive a part of the information bits during the encoding process and then encode the part of the information bits. Encoding and sending the encoded data implements stream encoding, which is beneficial to reducing the size of the encoder and cache in the terminal device.
  • the m-1th sub-block to be coded is first sent, and then the i-th coded sub-block is sent in sequence, and the i satisfies 0 ⁇ i ⁇ m-2.
  • the sending order of encoded data is designed, which is beneficial to the decoding side to implement stream decoding.
  • the encoding matrix is The G' is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), the m and the n are positive integers,
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n ,
  • the matrix O is an all-zero matrix with a size of 2 n ⁇ 2 n .
  • the i-th coding sub-block is sent in sequence, and the i satisfies 0 ⁇ i ⁇ m-1.
  • the method described in the first aspect above can also be executed by a network device.
  • the network device is the encoding side and the terminal device is the decoding side.
  • this application provides another data processing method, which can be executed by a terminal device or a network device.
  • the network device receives the encoded data and decodes the encoded data to obtain the decoded data.
  • the encoded data is obtained by encoding the block to be encoded.
  • the block to be encoded includes multiple sub-blocks to be encoded.
  • the number of information bits of each sub-block to be encoded in the block to be encoded is determined based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • stream decoding can be implemented for the encoded data.
  • the block to be encoded includes m sub-blocks to be encoded
  • the allocation sequence includes S-1 variables ⁇ A 0 ,A 1 ,A 2 ,...,A S-2 ⁇ ; the relationship between the elements in the allocation sequence is A 0 ⁇ A 1 ⁇ ... ⁇ A S -2 .
  • the length of each sub-block to be encoded is:
  • the number of information bits of the 0th sub-block to be encoded is The A 0 is the 0th element in the allocation sequence, and the ⁇ 0 is determined based on the difference between the E 0 and the N′, and the value is 0 or 1; or,
  • the length of each sub-block to be encoded is:
  • the A i is The i-th element in the allocation sequence
  • the number of information bits in the m-2 sub-block to be encoded is The A m-2 is the m-2 element in the allocation sequence, and the ⁇ 2 is determined based on the difference between the E m-2 and the N′, and the value is 0 or 1; or,
  • the coded data is coded using a coding matrix G.
  • the coding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the network device decodes the encoded data to obtain decoded data, which may specifically include:
  • the 0th receiving sub-block is the m-1th coding sub-block
  • the 1st receiving sub-block is the 0th coding. sub-block
  • the mark data corresponding to the 0th received sub-block is enhanced according to the mark data corresponding to the 1st received sub-block and the decoded data corresponding to the 1st received sub-block.
  • the network device decodes based on the 0th received sub-block received for the first time and its adjacent 1st received sub-block, thereby achieving stream decoding, and enhances the 0-th received sub-block, with It is beneficial to realize stream decoding based on the enhanced 0th receiving sub-block in the subsequent decoding process.
  • the network device obtains the mark data corresponding to the q-th received sub-block, the q-th received sub-block is the q-1-th coding sub-block, and q is 2 ⁇ q ⁇ m-1; Perform F operation on the mark data corresponding to the q-th receiving sub-block and the mark data corresponding to the enhanced 0-th receiving sub-block, and obtain the mark data corresponding to the q-th receiving sub-block after the F operation;
  • the mark data corresponding to the q-th receiving sub-block is decoded by Polar code to obtain the decoded data corresponding to the q-th receiving sub-block; according to the mark data corresponding to the q-th receiving sub-block and the q-th receiving sub-block
  • the decoded data corresponding to the block enhances the marked data corresponding to the enhanced 0th received sub-block.
  • the same method is used for decoding from the second received sub-block to the m-1 received sub-block. Moreover, as the decoding proceeds, the mark data corresponding to the 0th received sub-block is continuously enhanced, which is beneficial to the implementation of stream decoding.
  • the coded data is coded using a coding matrix G′
  • the coding matrix G′ is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers
  • matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n
  • matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the network device decodes the encoded data to obtain decoded data, which may specifically include:
  • the 0th receiving sub-block is the 0th encoding sub-block
  • the 1st receiving sub-block is the 1st encoding sub-block.
  • the mark data corresponding to the first receive sub-block is enhanced according to the mark data corresponding to the 0-th receive sub-block and the decoding data corresponding to the 0-th receive sub-block.
  • the network device obtains the mark data corresponding to the p-th received sub-block, the p-th received sub-block is the p-th encoded sub-block, and p is 2 ⁇ p ⁇ m-1; the p-th received sub-block is Perform F operation on the mark data corresponding to the received sub-block and the mark data corresponding to the p-1th received sub-block after the enhancement, and obtain the mark data corresponding to the p-1th received sub-block after the F operation;
  • the marked data corresponding to the p-1th received sub-block is decoded by Polar code to obtain the decoded data corresponding to the p-1th received sub-block; according to the enhanced marked data corresponding to the p-1th received sub-block and
  • the decoded data corresponding to the p-1th received sub-block enhances the mark data corresponding to the p-th received sub-block.
  • the method described in the second aspect above can also be executed by a terminal device.
  • the network device is the encoding side and the terminal device is the decoding side.
  • the data processing device may be a terminal device, a device in the terminal device, or a device that can be used in conjunction with the terminal device.
  • the data processing device may include a module that performs one-to-one correspondence with the methods/operations/steps/actions described in the first and second aspects.
  • the module may be a hardware circuit, software, or It can be implemented by hardware circuit combined with software.
  • the device may include a processing unit and a transceiver unit.
  • inventions of the present application provide a data processing device.
  • the data processing device may be a network device, a device in the network device, or a device that can be used in conjunction with the network device.
  • the data processing device may include a module that performs one-to-one correspondence with the methods/operations/steps/actions described in the first and second aspects.
  • the module may be a hardware circuit, software, or It can be implemented by hardware circuit combined with software.
  • the data processing device may include a processing unit and a transceiver unit.
  • the data processing device can also achieve the effects that can be achieved in the first aspect and the second aspect.
  • inventions of the present application provide a communication device.
  • the communication device is composed of an input-output interface and a logic circuit.
  • the input-output interface is used to input or output data; the logic circuit is as described in the first aspect and the first aspect.
  • the method in any possible implementation manner processes the data and obtains the processed data.
  • inventions of the present application provide a communication device.
  • the communication device is composed of an input-output interface and a logic circuit.
  • the input-output interface is used to input or output data; the logic circuit is as in the second aspect and the second aspect.
  • the method in any possible implementation manner processes the data and obtains the processed data.
  • embodiments of the present application provide a communication device, including: a processor, the processor is coupled to a memory, and the memory is used to store instructions.
  • the terminal device implements the first aspect. Or the method in any possible implementation of the second aspect.
  • the communication device is a terminal device.
  • the communication device is a network device.
  • the present application provides a communication system.
  • the communication system includes one or more of the data processing devices provided in the third aspect and the fourth aspect.
  • the communication system includes a terminal device and a network device as provided in the seventh aspect.
  • the communication system includes a sending end and a receiving end, and the sending end is configured to perform the method described in any one of the first aspect and the possible implementation manners of the first aspect.
  • the receiving end is configured to perform the method described in any one of the second aspect and the possible implementation manners of the second aspect.
  • this application provides a chip system.
  • the chip system includes a processor, and may also include a memory, for implementing the method in the above first aspect and any possible implementation of the first aspect, or the second aspect and any possible implementation of the second aspect. Methods.
  • the chip system can be composed of chips or include chips and other discrete devices.
  • the interface in the chip can be an input/output interface, a pin or a circuit, etc.
  • the above-mentioned chip system can be a system on chip (SOC), or a baseband chip, etc., where the baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • SOC system on chip
  • baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • the present application provides a computer-readable storage medium.
  • the above-mentioned computer-readable storage medium stores a computer program.
  • the above computer program is executed by the processor to implement the first aspect and the method in any possible implementation of the first aspect, or the second aspect and the method in any possible implementation of the second aspect.
  • this application provides a computer program product.
  • the computer program product includes instructions. When the instructions are run on the computer, the computer is caused to perform the first aspect and the method in any possible implementation of the first aspect, or the second aspect and the method in any possible implementation of the second aspect.
  • Figure 1 is a schematic diagram of a communication system provided by this application.
  • Figure 2 is a schematic diagram of an 8 ⁇ 8 polar code encoding
  • Figure 3 is a schematic diagram of calculating the log likelihood ratio LLR in the decoding process
  • Figure 4 is a schematic diagram of calculating the log likelihood ratio LLR in another decoding process
  • Figure 5a is a schematic diagram of the number of information bits of a coding sub-block
  • Figure 5b is a schematic diagram of the number of information bits of another encoding sub-block
  • Figure 6 is a schematic flow chart of the first data processing method provided by this application.
  • FIG. 7 is a schematic flow chart of the second data processing method provided by this application.
  • Figure 8 is a performance analysis diagram of the data processing method provided by this application.
  • Figure 9 is a schematic diagram of a device provided by this application.
  • Figure 10 is a schematic diagram of a communication device provided by this application.
  • A/B can mean A or B;
  • and/or can be used to describe the existence of three relationships between related objects.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural.
  • words such as “first” and “second” may be used to distinguish technical features with the same or similar functions. The words “first”, “second” and other words do not limit the quantity and execution order, and the words “first” and “second” do not limit the number and execution order.
  • This application provides a data processing method, which designs an information bit construction and encoding method based on allocation sequences.
  • This data processing method can be applied to communication systems.
  • the system architecture is shown in Figure 1. Wherein, the communication system includes network equipment and terminal equipment, and the network equipment can provide communication services to the terminal equipment.
  • the communication systems mentioned in this application include but are not limited to: narrowband-Internet of things (NB-IoT), global system for mobile communications (GSM), enhanced data rate GSM evolution system (enhanced data rate for GSM evolution, EDGE), wideband code division multiple access system (wideband code division multiple access, WCDMA), code division multiple access 2000 system (code division multiple access, CDMA2000), time division synchronous code division multiple access system (
  • NB-IoT narrowband-Internet of things
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • GSM global system for mobile communications
  • EDGE enhanced data rate GSM evolution system
  • WCDMA wideband code division multiple access
  • the network device may be a device that can communicate with the terminal device.
  • Network devices can be base stations, relay stations, or access points.
  • the base station can be a base transceiver station (BTS) in the global system for mobile communication (GSM) system or code division multiple access (CDMA) network, or it can be a broadband
  • the 3G base station NodeB in the code division multiple access (wideband code division multiple access, WC DMA) system can also be the evolutionary NodeB (referred to as eNB or eNodeB) in the long term evolution (long term evolution, LTE) system.
  • the network device may also be a satellite in a satellite communications system.
  • the network device can also be a wireless controller in a cloud radio access network (CRAN) scenario.
  • CRAN cloud radio access network
  • the network device may also be a network device in a 5G network or a network device in a future evolved public land mobile network (public land mobile network, PLMN) network (such as gNodeB).
  • Network devices can also be wearable devices, drones, or devices in the Internet of Vehicles (such as vehicle to everything (V2X)), or communication devices in device-to-device (D2D) communication. Or network equipment used in future communication systems.
  • V2X vehicle to everything
  • D2D device-to-device
  • the terminal device can be a user equipment (UE), an access terminal, a terminal unit, a terminal station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a terminal, a wireless communication device, a terminal agent or a terminal.
  • UE user equipment
  • an access terminal a terminal unit
  • a terminal station a mobile station
  • a mobile station a mobile station
  • a remote station a remote terminal
  • a mobile device a terminal
  • a wireless communication device a terminal agent or a terminal.
  • the access terminal may be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), or a device with wireless communications Functional handheld devices, computing devices or other processing devices connected to wireless modems, wearable devices, drones, V2X devices, D2D devices, terminal devices in 5G networks, terminal devices in future evolved PLMN networks or in the future Terminal equipment in communication systems, etc.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • this application includes a coding scheme, which can be used for dedicated network equipment or general equipment, network equipment, various terminal equipment, etc.
  • This application can be implemented through a dedicated chip (such as an application specific integrated circuit (ASIC)), a programmable chip (such as a field programmable gate array (FPGA)), or software ( program code in memory), this application does not limit it.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • Polar code is a channel coding scheme that can be strictly proven to achieve channel capacity. Polar code has the characteristics of high performance, low complexity, and flexible matching method. Currently, Polar codes have been identified as the uplink and/or downlink control channel coding scheme for the fifth generation ( 5th generation, 5G) control channel enhanced mobile broadband (eMBB) scenario.
  • 5G fifth generation
  • eMBB enhanced mobile broadband
  • Figure 2 is a schematic diagram of an 8 ⁇ 8 polar code encoding, in which the bits to be encoded are sorted according to their respective reliability and arranged in different positions in the block to be encoded.
  • bits with higher reliability are set as information bits (data)
  • bits with lower reliability are set as fixed bits (frozen).
  • the value of the fixed bit is usually set to 0 and is known to both the sender and the receiver during actual transmission.
  • u 7 , u 6 , u 5 , and u 3 are the four bits with the highest reliability, which are set as information bits respectively;
  • u 4 , u 2 , u 1 , and u 0 are the four bits with the lowest reliability.
  • G is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, and the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n , expressed as
  • the matrix O is an all-zero matrix of size 2 n ⁇ 2 n .
  • each element in the matrix is a 2 n ⁇ 2 n matrix
  • each element in the diagonal of the matrix is a matrix G N′
  • each element in the base of the matrix is the matrix G N′
  • the elements except the diagonal and the base are all the matrix O.
  • the decoding side After the decoding side receives the encoded data based on the encoding matrix G, the encoded data can be decoded. For example, the decoding process is shown in Figure 3.
  • the decoding side can calculate the mean change of LLR for each G N′ based on the coding matrix G. Assume that under the additive white Gaussian noise (AWGN) channel, the mean value of the received LLR is L.
  • the mean LLR distribution of each G N′ after being decoupled by the last coupling sub-block can be calculated through the Gaussian approximate function (GAF). Therefore, it is possible to calculate the average LLR value of each G N′- sized coding sub-block (receiving sub-block) when entering ordinary Polar code decoding.
  • the LLR mean value of each G N′- sized coding sub-block is as follows:
  • the LLR mean value of any coding sub-block except the last coding sub-block among the m-1 coding sub-blocks is the LLR mean value of the last coding sub-block. It can be seen that, except for the last coding sub-block, the capacity of the other m-1 coding sub-blocks is only related to its own serial number i, and has nothing to do with the total number of coding sub-blocks m of the coding block.
  • G′ is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, and the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n , expressed as
  • the matrix O is an all-zero matrix of size 2 n ⁇ 2 n .
  • each element in the matrix is a 2 n ⁇ 2 n matrix
  • each element in the lower triangular area of the matrix is a matrix G N ′
  • the elements of the matrix except the lower triangular area are all matrix O.
  • the decoding side After the decoding side receives the encoded data based on the encoding matrix G', the encoded data can be decoded. For example, the decoding process is shown in Figure 4.
  • the decoding side can calculate the mean change of LLR for each G N' based on the coding matrix G'. Assume that under the AWGN channel, the average value of the received LLR is L.
  • the LLR distribution mean of each G N′ after being decoupled by the last coupling sub-block can be calculated through GAF. Therefore, it is possible to calculate the average LLR value of each G N′- sized coding sub-block (receiving sub-block) when entering ordinary Polar code decoding.
  • the LLR mean value of each G N′- sized coding sub-block is as follows:
  • the LLR mean value of any coding sub-block except the last coding sub-block among the m-1 coding sub-blocks is the LLR mean value of the last coding sub-block. It can be seen that, except for the last coding sub-block, the capacity of the other m-1 coding sub-blocks is only related to its own serial number i, and has nothing to do with the total number of coding sub-blocks m of the coding block.
  • the LLR mean distribution of each sub-block is as follows: (1) shown. According to the capacity calculation results, the capacity of each corresponding sub-block/information bit reflected in the respective decoding maps of the two coding matrices is consistent, so the same information construction method can be used.
  • the capacity of the other m-1 coding sub-blocks is only related to its own serial number i, and has nothing to do with the total number of coding sub-blocks m of the coding block. Therefore, when a code rate and N′ are fixed, the information bit distribution result of the coding sub-block that satisfies certain rules can be obtained.
  • the first coding sub-block is allocated to 1 information bit
  • the second coding sub-block is allocated to 31 information bits.
  • the first coding sub-block is allocated to 1 information bit
  • the second coding sub-block is allocated to 4 information bits
  • the third coding sub-block is allocated to 4 information bits. 43 information bits are allocated, and so on, as shown in Figure 5a.
  • the first coding sub-block is allocated to 5 information bits, and the second coding sub-block is allocated to 59 information bits.
  • the first coding sub-block is allocated to 4 information bits, the second coding sub-block is allocated to 6 information bits, and the third coding sub-block is allocated to 6 information bits.
  • 89 information bits are allocated, and so on, as shown in Figure 5b.
  • an allocation sequence can be used to describe the number of information bits in all coding sub-blocks except the last coding sub-block in the coding block under the same code rate and coding sub-block size. It can be understood that since the number of information bits included in the encoding sub-block and the sub-block to be encoded is the same, and the lengths of the sub-block to be encoded and the encoding sub-block are also the same, the allocation sequence can also be used to describe the information in the same code. The number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, given the rate and the size of the sub-block to be encoded.
  • F operation is the basic decoding operation of Polar code, and is processed using the predefined F function (f-function).
  • the inputs of the F function are L 0 and L 1 , and the F function can be simplified as:
  • sig is a sign operation. If the immediate value is greater than 0, the return value is 0, otherwise the return value is 1.
  • abs is an absolute value operation. For example, assume that there are encoded data x 0 and x m-1 with length N', perform F operation on x 0 and x m-1 , compare the signs of x 0 and x m-1 , and if they are consistent, the immediate value The value is 1, otherwise the value is -1.
  • G operation is the basic decoding operation of Polar code, and is processed using the predefined G function (g-function).
  • FIG. 6 is a schematic flow chart of the first data processing method provided by this application.
  • This data processing method can be executed by a terminal device or a network device. It mainly performs the encoding process, including the following steps:
  • S103 Determine the number of information bits for each sub-block to be encoded in the block to be encoded based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded. For example, assuming that the allocation sequence includes S-1 variables ⁇ A 0 , A 1 , A 2 ,..., A S-2 ⁇ , the relationship between the elements in the allocation sequence is A 0 ⁇ A 1 ⁇ ... ⁇ AS -2 .
  • the number of information bits for each sub-block to be encoded in the block to be encoded is determined, including the following two methods:
  • Method 1 If the assigned blocks to be encoded will be encoded based on the coding matrix G, the length of each sub-block to be encoded can be determined as shown in the following formulas (2) and (3):
  • i is the sequence number of the sub-block to be encoded
  • m is the total number of blocks to be encoded
  • N' is the size of the block to be encoded
  • E is the length of the block to be encoded.
  • the number of information bits for each sub-block to be encoded can be determined as shown in the following formulas (4) to (6):
  • J i is the number of information bits in the i-th sub-block to be encoded
  • a i is the i-th element in the allocation sequence
  • a m-2 is the m-2 element in the allocation sequence
  • ⁇ 2 is based on
  • the length of the m-2 sub-block to be encoded is determined by the difference between E m-2 and N′, and takes a value of 0 or 1.
  • the number of information bits of the sub-blocks to be encoded except the last and penultimate sub-blocks to be encoded in the block to be encoded is equal to the variable value of the corresponding sequence number in the allocation sequence;
  • the number of information bits in the penultimate sub-block to be encoded is determined based on the length of the sub-block to be encoded, the variable value of the penultimate serial number in the allocation sequence, N′, ⁇ 2 and other parameter values; the last sub-block to be encoded
  • the number of information bits of a block is equal to the total number of information bits K minus the sum of the number of information bits of other sub-blocks to be encoded. That is to say, once the allocation sequence is determined, the number of information bits for each sub-block to be encoded can be determined relatively simply and quickly, which facilitates simpler and faster implementation of the construction of information bits.
  • Method 2 If the allocated block to be encoded will be encoded based on the coding matrix G′ or the coding matrix G, the length of each sub-block to be encoded can be determined as shown in the following formulas (7) and (8):
  • i is the sequence number of the sub-block to be encoded
  • m is the total number of blocks to be encoded
  • N' is the size of the block to be encoded.
  • the number of information bits for each sub-block to be encoded can be determined as shown in the following formulas (9) to (12):
  • J i is the number of information bits in the i-th sub-block to be encoded
  • a i is the i-th element in the allocation sequence
  • ⁇ 0 is the difference between E 0 and N′ according to the length of the 0-th sub-block to be encoded. The value is determined, and the value is 0 or 1.
  • ⁇ 1 is determined based on the difference between the length E 0 and N' of the 0th sub-block to be encoded, and the value is 0 or 1.
  • the default length E 0 of the 0th sub-block to be encoded is full; if the length E 0 of the 0th sub-block to be encoded is too punctured, it may cause the first sub-block to be encoded to be If the increased capacity is limited, E 1 needs to be adjusted through parameter ⁇ 1 , and ⁇ 1 is determined based on the difference between the lengths E 0 and N' of the 0th sub-block to be encoded.
  • the number of information bits of the 0th sub-block to be encoded is determined based on the length of the sub-block to be encoded, the variable value of the 0th serial number in the allocation sequence, N', ⁇ 0 and other parameter values; the 1st to-be-encoded sub-block
  • the number of information bits of the coding sub-block is determined based on the variable value of the first serial number in the allocation sequence and parameter values such as ⁇ 1 ;
  • the number of information bits of the last sub-block to be coded is equal to the total number of information bits K minus the other sub-blocks to be coded The sum of the number of information bits. That is to say, once the allocation sequence is determined, the number of information bits for each sub-block to be encoded can be determined relatively simply and quickly, which facilitates simpler and faster implementation of the construction of information bits.
  • S104 Encode the block to be encoded to obtain encoded data.
  • encoding the block to be encoded and obtaining the encoded data may include the following steps:
  • s12 determine the information bits and frozen bits of each coding sub-block, and construct an information sequence of size m ⁇ 2 n according to the number m of coding sub-blocks;
  • Method 1 When using the coding matrix as When , for a detailed description of the coding matrix G, please refer to the corresponding description above.
  • the frozen position of N' is determined according to the length of the coding sub-block, and the information bit is constructed based on a sequence of size N'.
  • the selection of the freezing bit can adopt the provisions in the existing agreement or can be designed separately, which is not limited in this application.
  • u N can be divided into m segments The length of each segment is N′; according to the coding matrix G, each segment is modulo squared with G N′ , and the result is The resulting encoding result is
  • the encoded data after the encoded data is generated, the encoded data will be sent.
  • the order in which the encoded data is sent can be:
  • Method 2 When using the coding matrix as When , the detailed description of the coding matrix G′ can refer to the corresponding description above.
  • the frozen position of N' is determined according to the length of the coding sub-block, and the information bit is constructed based on a sequence of size N'.
  • the selection of the freezing bit can adopt the provisions in the existing agreement or can be designed separately, which is not limited in this application.
  • u N can be divided into m segments
  • the length of each segment is N′; according to the coding matrix G′, each segment is modulo squared with G N′ , and the result is Adjacent data are coupled from back to front (for example, starting from the m-2th and going forward in sequence until the 0th), resulting in an encoding result of
  • the encoded data after the encoded data is generated, the encoded data will be sent.
  • the order in which the encoded data is sent can be:
  • the i-th coding sub-block is sent in sequence, 0 ⁇ i ⁇ m-1.
  • the first data processing method provided by this application designs an information bit construction and encoding method based on allocation sequences.
  • the information bit construction method is simple and effective, and is conducive to improving system performance and reducing system power consumption.
  • this method can support information bit construction and rate matching when the length of the coding sub-block is less than an integer multiple of 2n .
  • the encoding matrix G is used to encode the information bits to be encoded to obtain encoded data, which is beneficial to realizing stream decoding.
  • Figure 7 is a schematic flow chart of the second data processing method provided by this application.
  • the data processing method can be executed by the terminal device or by the network device. It can be understood that when the terminal device performs the data processing method described in the third part here, that is, the terminal device is the decoding side, then the network device performs the data processing method described in the second part, that is, the network device is the encoding side. . When executing the decoding process, the following steps are included:
  • the encoded data is obtained by encoding the blocks to be encoded.
  • the block to be encoded includes multiple sub-blocks to be encoded, and the number of information bits of each sub-block to be encoded in the block to be encoded is determined based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the operation at the same code rate. and the size of the sub-block to be encoded, the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded.
  • the description of the block to be encoded, the sub-block to be encoded, the encoding block, the encoding sub-block, the number of information bits in the block to be encoded, the allocation sequence, and how to encode the block to be encoded refer to the corresponding description in the second part above, here No longer.
  • the encoded data may be obtained by encoding the information bit sequence based on the encoding matrix G.
  • the process of decoding the encoded data is a stream decoding process.
  • the terminal device can first process the 0th received sub-block and the 1st received sub-block. Decoding is performed in blocks, that is, after receiving part of the information during the decoding process, the part of the information can be decoded. Specifically, the following steps can be included:
  • the s11 obtain the tag data corresponding to the 0th received sub-block and the tag data corresponding to the 1st received sub-block, the 0th received sub-block is the m-1th coding sub-block, and the 1st received sub-block is the 0th coding sub-blocks;
  • S14 Enhance the tag data corresponding to the 0th received sub-block based on the tag data corresponding to the first received sub-block and the decoded data corresponding to the first received sub-block.
  • the marked data corresponding to the 0th received sub-block is the log likelihood ratio (log likelihood ratio, LLR) of the 0th received sub-block, that is, the LLR of the m-1th coding sub-block; the 1st The mark data corresponding to the received sub-block is the LLR of the first received sub-block, that is, the LLR of the 0th encoded sub-block.
  • LLR log likelihood ratio
  • the tag data corresponding to the 1st receiving sub-block after the F operation is obtained (that is, the code received after decoupling data).
  • the description of the F function refers to the previous description and will not be repeated here.
  • the method of performing Polar code decoding on the tag data corresponding to the first received sub-block after the F operation can refer to the existing Polar code decoding method, which is not limited in this application.
  • the LLR of the 0th receiving sub-block, the LLR of the 1st receiving sub-block and the decoding data corresponding to the 1st receiving sub-block are used as inputs of the G function, thereby realizing the marking data corresponding to the 0th receiving sub-block.
  • Enhancement that is, enhancement of the encoded data received first
  • the description of the G function refers to the previous description and will not be repeated here.
  • the tag data corresponding to the 0th received sub-block may be the likelihood probability of the 0th received sub-block
  • the tag data corresponding to the 1st received sub-block may be the likelihood probability of the 1st received sub-block.
  • the above step s12 will become: perform probability operation on the mark data corresponding to the 0th receiving sub-block and the mark data corresponding to the 1st receiving sub-block, and obtain the 1st receiving sub-block in the probability domain.
  • the tag data corresponding to the block It can be understood that the subsequent processing flow is still performed according to s13 and s14, and the marked data corresponding to the 0th received sub-block can be enhanced.
  • the processing method is similar to the above-mentioned s11 ⁇ s14, and may include the following steps:
  • S18 Enhance the enhanced tag data corresponding to the 0th received sub-block based on the marked data corresponding to the q-th received sub-block and the decoded data corresponding to the q-th received sub-block.
  • the tag data corresponding to the second receiving sub-block For example, obtain the tag data corresponding to the second receiving sub-block, perform F operation on the tag data corresponding to the second receiving sub-block and the enhanced tag data corresponding to the 0th receiving sub-block, and obtain the F-th operation.
  • Mark data corresponding to the two receiving sub-blocks ; perform Polar code decoding on the marking data corresponding to the second receiving sub-block after the F operation, and obtain the decoded data corresponding to the second receiving sub-block.
  • the mark data corresponding to the block and the decoded data corresponding to the second received sub-block perform a second enhancement on the marked data corresponding to the 0-th received sub-block after the enhancement, and the second-time enhanced mark data corresponding to the 0-th received sub-block is obtained.
  • Label data For the specific implementation of the above steps, please refer to the specific implementation corresponding to s11 to s14, which will not be described again here.
  • the s21 obtain the tag data corresponding to the 0th receiving sub-block and the tag data corresponding to the 1st receiving sub-block, the 0th receiving sub-block is the 0th coding sub-block, and the 1st receiving sub-block is the 1st coding sub-block;
  • the tag data corresponding to the 0th received sub-block is the LLR of the 0th received sub-block
  • the tag data corresponding to the 1st received sub-block is the LLR of the 1st received sub-block.
  • the method of performing Polar code decoding on the mark data corresponding to the 0th received sub-block after the F operation can refer to the existing Polar code decoding method, which is not limited in this application.
  • the LLR of the first receiving sub-block, the LLR of the 0-th receiving sub-block and the decoding data corresponding to the 0-th receiving sub-block are used as inputs of the G function, thereby realizing the marking data corresponding to the first receiving sub-block.
  • Enhancement that is, the received coded data after enhancement).
  • the description of the G function refers to the previous description and will not be repeated here.
  • the tag data corresponding to the 0th received sub-block may be the likelihood probability of the 0th received sub-block
  • the tag data corresponding to the 1st received sub-block may be the likelihood probability of the 1st received sub-block.
  • the above step s22 will become: perform probability operation on the mark data corresponding to the 0th receiving sub-block and the mark data corresponding to the 1st receiving sub-block, and obtain the 0th receiving sub-block in the probability domain.
  • the tag data corresponding to the block It can be understood that the subsequent processing flow is still executed according to s23 and s24, and the marked data corresponding to the first received sub-block can be enhanced.
  • the processing method is similar to the above-mentioned s21 ⁇ s24, and may include the following steps:
  • S28 Enhance the tag data corresponding to the p-th received sub-block based on the enhanced tag data corresponding to the p-1-th received sub-block and the decoded data corresponding to the p-1-th received sub-block.
  • the tag data corresponding to the second receiving sub-block obtains tag data corresponding to the second receiving sub-block, and perform F operation on the tag data corresponding to the second receiving sub-block and the tag data corresponding to the enhanced first receiving sub-block to obtain the F-operation-based tag data.
  • Mark data corresponding to one receiving sub-block perform Polar code decoding on the marking data corresponding to the first receiving sub-block after the F operation, and obtain the decoded data corresponding to the first receiving sub-block.
  • the mark data corresponding to the block and the decoded data corresponding to the first received sub-block enhance the mark data corresponding to the second received sub-block to obtain enhanced mark data corresponding to the second received sub-block.
  • the data processing method provided by this application can support decoding a part of the information after receiving it during the decoding process, that is, realizing stream decoding, which can reduce the decoding cost. size of the processor, thereby reducing the overhead on the decoding side.
  • FIG. 8 is a performance analysis diagram of the data processing method provided by this application.
  • the abscissa of the performance analysis diagram is EsN0, which represents each The ratio of symbol energy to noise power spectral density; the ordinate is the block error rate (BLER), which is used to measure system performance testing.
  • BLER block error rate
  • three line types are a solid line with a circular symbol, a dotted line with an asterisk, and a dotted line with a square symbol. They can be used to compare the use of decoders of different sizes under different numbers of information bits. The difference in decoding performance when using different decoding methods.
  • the dotted line with an asterisk indicates the decoding result of the decoder size 512, because the maximum decoding length can support 512 (512 is greater than the sending length 384), so there is no segmentation, so the performance is slightly better
  • the decoding performance of this application is represented by the solid line with circular symbols, but the size of its decoder is twice larger than that of this application. This application significantly reduces the overhead on the decoding side.
  • the dashed line with square symbols represents the decoding result of the decoder size 256, because the maximum decoding length can support 256 (256 is smaller than the sending length 384), so it is divided into two segments, so the performance is worse than the real one with circle symbols.
  • the lines represent the decoding performance of the present application.
  • the dotted line with an asterisk indicates the decoding result of the decoder size 512. Because the maximum decoding length can support 512 (512 is smaller than the sending length 704), it is divided into two segments, so the performance is worse than
  • the solid line with a circular symbol represents the decoding performance of the present application; and the size of its decoder is twice larger than that of the present application, and the present application significantly reduces the overhead on the decoding side.
  • the dashed line with square symbols represents the decoding result of the decoder size 256, because the maximum decoding length can support 256 (256 is less than the sending length 704), so it is divided into three segments, so the performance is worse than the real one with round symbols.
  • the lines represent the decoding performance of the present application.
  • the device or equipment provided by this application may include a hardware structure and/or a software module to realize the above functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether one of the above functions is performed as a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.
  • the division of modules in this application is schematic and is only a logical function division. In actual implementation, there may be other division methods.
  • each functional module in various embodiments of the present application can be integrated into a processor, or can exist physically alone, or two or more modules can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software function modules.
  • FIG 9 is a schematic diagram of a device provided by this application.
  • the device may include modules that perform one-to-one correspondence with the methods/operations/steps/actions described in the method embodiments corresponding to Figures 3 to 7.
  • the module may be a hardware circuit, software, or hardware.
  • the circuit is combined with software implementation.
  • the device may be called a data processing device or a communication device.
  • the device includes a communication unit 901 and a processing unit 902, which are used to implement the method executed by the terminal device or network device in the previous embodiment.
  • the communication unit 901 is used to obtain K information bits
  • the processing unit 902 is used to determine the length of the block to be encoded according to the K, and determine the block to be encoded according to the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • the processing unit 902 is used to encode the block to be encoded to obtain encoded data
  • the communication unit 901 is used to send the encoded data.
  • the block to be encoded includes m sub-blocks to be encoded
  • the allocation sequence includes S-1 variables ⁇ A 0 ,A 1 ,A 2 ,...,A S-2 ⁇ ; the relationship between the elements in the allocation sequence is A 0 ⁇ A 1 ⁇ ... ⁇ A S -2 .
  • the length of each sub-block to be encoded is:
  • the processing unit 902 is configured to determine the number of information bits of each sub-block to be encoded in the block to be encoded based on the length of the block to be encoded and the allocation sequence, which may specifically include:
  • the length of each sub-block to be encoded is:
  • the processing unit 902 is configured to determine the number of information bits of each sub-block to be encoded in the block to be encoded based on the length of the block to be encoded and the allocation sequence, which may specifically include:
  • the A m-2 is the m-2 element in the allocation sequence, and the ⁇ 2 is determined based on the difference between the E m-2 and the N′, and the value is 0 or 1; or,
  • processing unit 902 is used to encode the block to be encoded to obtain encoded data, which may specifically include:
  • the K information bits are divided into m sub-segments
  • the K information bits are inserted into the sequence to be encoded, and the sequence to be encoded and the encoding matrix are subjected to modular square multiplication processing to obtain encoded data.
  • the coding matrix is
  • the G is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), the m and the n are positive integers,
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n ,
  • the matrix O is an all-zero matrix with a size of 2 n ⁇ 2 n .
  • the communication unit 901 when used to send coded data (the coded data is obtained according to the coding matrix G), it first sends the m-1 sub-block to be coded, and then sends the i-th coded sub-block in sequence, and the i Satisfies 0 ⁇ i ⁇ m-2.
  • the encoding matrix is The G' is a matrix with a size of (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), the m and the n are positive integers,
  • the matrix G N′ is a Polar generating matrix with a size of 2 n ⁇ 2 n ,
  • the matrix O is an all-zero matrix with a size of 2 n ⁇ 2 n .
  • the communication unit 901 when used to send coded data (the coded data is obtained according to the coding matrix G'), it sends the i-th coding sub-block in sequence, and the i satisfies 0 ⁇ i ⁇ m-1.
  • the data processing method implemented by the communication device designs an information bit construction and encoding method based on allocation sequences.
  • the information bit construction method is simple and effective, and is beneficial to improving system performance and reducing system power consumption.
  • this method can support information bit construction and rate matching when the length of the coding sub-block is less than an integer multiple of 2n .
  • the communication unit 901 is configured to receive encoded data
  • the processing unit 902 is configured to decode the encoded data to obtain decoded data.
  • the encoded data is obtained by encoding the block to be encoded.
  • the block to be encoded includes multiple sub-blocks to be encoded.
  • the number of information bits of each sub-block to be encoded in the block to be encoded is determined based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • the block to be encoded includes m sub-blocks to be encoded
  • the allocation sequence includes S-1 variables ⁇ A 0 ,A 1 ,A 2 ,...,A S-2 ⁇ ; the relationship between the elements in the allocation sequence is A 0 ⁇ A 1 ⁇ ... ⁇ A S -2 .
  • the length of each sub-block to be encoded is:
  • the number of information bits of the 0th sub-block to be encoded is The A 0 is the 0th element in the allocation sequence, and the ⁇ 0 is determined based on the difference between the E 0 and the N′, and the value is 0 or 1; or,
  • the length of each sub-block to be encoded is:
  • the number of information bits in the m-2 sub-block to be encoded is The A m-2 is the m-2 element in the allocation sequence, and the ⁇ 2 is determined based on the difference between the E m-2 and the N′, and the value is 0 or 1; or,
  • the encoded data is encoded using the encoding matrix G.
  • the encoding matrix G is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the processing unit 902 is used to decode the encoded data to obtain decoded data, which may specifically include:
  • the 0th receiving sub-block is the m-1th coding sub-block
  • the 1st receiving sub-block is the 0th coding. sub-block
  • the mark data corresponding to the 0th received sub-block is enhanced according to the mark data corresponding to the 1st received sub-block and the decoded data corresponding to the 1st received sub-block.
  • processing unit 902 is also used to:
  • the enhanced mark data corresponding to the 0th received sub-block is enhanced according to the marked data corresponding to the q-th received sub-block and the decoding data corresponding to the q-th received sub-block.
  • the coded data is coded using the coding matrix G′.
  • the coding matrix G′ is a matrix of size (m ⁇ 2 n ) ⁇ (m ⁇ 2 n ), m and n are positive integers, matrix G N′ is a Polar generating matrix of size 2 n ⁇ 2 n , and matrix O is a size of 2 n ⁇ 2 n all-zero matrix.
  • the processing unit 902 is used to decode the encoded data to obtain decoded data, which may specifically include:
  • the 0th receiving sub-block is the 0th encoding sub-block
  • the 1st receiving sub-block is the 1st encoding sub-block.
  • the mark data corresponding to the first receive sub-block is enhanced according to the mark data corresponding to the 0-th receive sub-block and the decoding data corresponding to the 0-th receive sub-block.
  • processing unit 902 is also used to:
  • the mark data corresponding to the p-th received sub-block is enhanced according to the enhanced mark data corresponding to the p-1-th received sub-block and the decoding data corresponding to the p-1-th received sub-block.
  • the coded data designed in the data processing method implemented by the communication device includes multiple coding blocks, and the number of information bits in the multiple coding blocks is designed according to certain rules, then stream decoding can be implemented for the coded data.
  • FIG. 9 is a schematic diagram of a communication device provided by this application, used to implement the data processing method in the above method embodiment.
  • the communication device 1000 may also be a chip system. It can be understood that the communication device 1000 may be, for example, a terminal device or a network device.
  • the communication device 1000 includes a communication interface 1001 and a processor 1002.
  • the communication interface 1001 may be, for example, a transceiver, an interface, a bus, a circuit, or a device capable of implementing transceiver functions.
  • the communication interface 1001 is used to communicate with other devices through a transmission medium, so that the device 1000 can communicate with other devices.
  • the processor 1002 is configured to perform processing-related operations.
  • the communication interface 1001 is used to obtain K information bits
  • the processor 1002 is used to determine the length of the block to be encoded based on the K, and determine the block to be encoded based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • the processor 1002 is used to encode the block to be encoded to obtain encoded data
  • the communication interface 1001 is used to send the encoded data.
  • the data processing method implemented by the communication device designs an information bit construction and encoding method based on allocation sequences.
  • the information bit construction method is simple and effective, which is beneficial to improving system performance and reducing system power consumption.
  • this method can support information bit construction and rate matching when the length of the coding sub-block is less than an integer multiple of 2n .
  • the communication interface 1001 is used to receive encoded data
  • the processor 1002 is used to decode the encoded data to obtain decoded data.
  • the encoded data is obtained by encoding the block to be encoded.
  • the block to be encoded includes multiple sub-blocks to be encoded.
  • the number of information bits of each sub-block to be encoded in the block to be encoded is determined based on the length of the block to be encoded and the allocation sequence.
  • the allocation sequence is used to describe the number of information bits in all sub-blocks to be encoded except the last sub-block to be encoded in the block to be encoded, under the same code rate and size of the sub-block to be encoded.
  • the encoded data in the data processing method implemented by the communication device includes multiple encoding blocks, and if the number of information bits in the multiple encoding blocks is designed according to certain rules, stream decoding can be implemented for the encoded data.
  • the communication device 1000 may also include at least one memory 1003 for storing program instructions and/or data.
  • the memory is coupled to the processor. Coupling in this application is an indirect coupling or communication connection between devices, units or modules, which may be electrical, mechanical or other forms, and is used for information interaction between devices, units or modules.
  • the processor may operate in conjunction with the memory.
  • the processor may execute program instructions stored in memory.
  • the at least one memory and processor are integrated together.
  • the bus 1004 is represented by a thick line in FIG. 10 .
  • the connection methods between other components are only schematically illustrated and are not limiting.
  • the bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in Figure 10, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component that can implement or execute the present application.
  • a general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in this application can be directly implemented by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or it may be a volatile memory (volatile memory), such as a random access memory.
  • Get memory random-access memory, RAM.
  • Memory is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • the memory in this application can also be a circuit or any other device capable of realizing a storage function, used to store program instructions and/or data.
  • the present application provides a communication device.
  • the communication device is composed of an input and output interface and a logic circuit.
  • the input and output interface is used to input or output data; the logic circuit follows the method in the embodiment corresponding to Figure 3 to Figure 7 Process the data and obtain the processed data.
  • the present application provides a communication device.
  • the communication device is composed of an input and output interface and a logic circuit.
  • the input and output interface is used to input or output data; the logic circuit follows the method in the embodiment corresponding to Figure 3 to Figure 7 Process the data and obtain the processed data.
  • This application provides a communication system, which includes a terminal device and a network device in the embodiments corresponding to Figures 3 to 7.
  • This application provides a computer-readable storage medium.
  • the computer-readable storage medium stores programs or instructions.
  • the program or instruction is run on the computer, the computer is caused to execute the data processing method in the embodiment corresponding to FIG. 3 to FIG. 7 .
  • the computer program product includes instructions.
  • the instructions When the instructions are run on the computer, the computer is caused to execute the data processing method in the embodiment corresponding to FIG. 3 to FIG. 7 .
  • the present application provides a chip or chip system.
  • the chip or chip system includes at least one processor and an interface.
  • the interface and the at least one processor are interconnected through lines.
  • the at least one processor is used to run computer programs or instructions to execute the tasks shown in Figure 3 to Figure 7 corresponds to the data processing method in the embodiment.
  • the interface in the chip can be an input/output interface, a pin or a circuit, etc.
  • the above-mentioned chip system can be a system on chip (SOC), or a baseband chip, etc., where the baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • SOC system on chip
  • baseband chip can include a processor, a channel encoder, a digital signal processor, a modem, an interface module, etc.
  • the chip or chip system described above in this application further includes at least one memory, and instructions are stored in the at least one memory.
  • the memory can be a storage unit inside the chip, such as a register, a cache, etc., or it can be a storage unit of the chip (such as a read-only memory, a random access memory, etc.).
  • the technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in this application are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated.
  • the available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, digital video disc (digital video disc, DVD)), or semiconductor media, etc.
  • the embodiments may refer to each other, for example, the methods and/or terms between the method embodiments may refer to each other, for example, the functions and/or terms between the device embodiments may refer to each other. References may be made to each other, for example functions and/or terms between apparatus embodiments and method embodiments may be referenced to each other.

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Abstract

本申请提供一种数据处理方法、装置及设备，设计了一种基于分配序列的信息比特构造和编码方法。该方法中根据信息比特的数量和分配序列，可以确定待编码块中每个待编码子块的信息比特数量，从而实现了信息比特构造和编码。该信息比特构造方法简单有效，有利于提高系统性能，降低系统功耗。并且，该方法可以支持编码子块的长度不足2 n的整数倍时的信息比特构造和速率匹配。

Description

一种数据处理方法、装置及设备 技术领域
本申请涉及通信技术领域，尤其涉及一种数据处理方法、装置及设备。
背景技术
极化码(Polar code)是一种能够被严格证明“达到”香农信道容量的信道编码方案，具有性能好，复杂度低等特点，可以应用于第五代(the 5 th generation，5G)通信系统以及未来通信系统中。Polar码的母码长度为2的整数次幂(也即是2 n)，当实际通信所需的码长N不是母码长度时(例如不为2 n)，需要进一步通过打孔、重传等方式实现码长匹配过程，从而实现速率匹配。对普通的Polar码，现有协议标准中规定了一种序列的构造方式和基于子块交织的速率匹配模式。但是该序列的构造方式只适用于母码长度为2 n的编码矩阵，对于母码长度不为2 n的编码矩阵，目前只有通过高斯近似构造，没有快速灵活的构造方法，以及对应的速率匹配模式。
发明内容
本申请提供一种数据处理方法、装置及设备，该方法可以对母码长度不为2 n的整数倍的编码数据进行快速的信息位的构造以及速率匹配，构造方法简单有效，有利于提高系统性能。
第一方面，本申请提供一种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以终端设备为执行主体，且终端设备为编码侧为例，终端设备获取K个信息比特，并根据所述K，确定待编码块的长度，根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量。其中，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。终端设备对待编码块进行编码，得到编码数据，并发送编码数据。
该方法中，设计了一种基于分配序列的信息比特构造和编码方法，该信息比特构造方法简单有效，有利于提高系统性能，降低系统功耗。
一种可能的实施方式中，待编码块的长度为E＝K/R，R为码率；
待编码块包括m个待编码子块，
Figure PCTCN2022110969-appb-000001
编码数据包括编码块，编码块包括m个编码子块，编码子块大小为N′，N′＝2 n；
分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
该方法中，设计了待编码块的长度，以及待编码块中待编码子块的数量，从而确定了编码子块的数量，并且设计编码子块的大小为2 n，使得码率和编码子块的大小固定，从而有利于实现基于分配序列的信息比特构造。还设计了一种分配序列，可以支持更简单的信息比特构造。并且，该方法可以支持编码子块的长度不足2 n的整数倍时的信息比特构造和速率匹配。
一种可能的实施方式中，每个待编码子块的长度为：
E 0＝E-(m-1)×N′，或者，E i＝N′，i∈{1,2,...,m-2,m-1}。
一种可能的实施方式中，终端设备根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量，具体可以包括：
当i＝0时，确定第0个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000002
所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i＝1时，确定第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i∈{2,3,...,m-2}时，确定第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-1时，确定第m-1个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000003
上述方法中，设计了待编码子块的长度以及待编码块中每个待编码子块的信息比特数量，可以支持编码矩阵G′下的信息比特构造。
一种可能的实施方式中，每个待编码子块的长度为：
E m-2＝E-(m-1)×N′，或者，E i＝N′，i∈{0,1,2,...,m-3,m-1}。
一种可能的实施方式中，终端设备根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量，具体可以包括：
当i∈{2,3,...,m-3}时，确定第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-2时，确定第m-2个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000004
所述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
当i＝m-1时，确定第m-1个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000005
上述方法中，设计了待编码子块的长度以及待编码块中每个待编码子块的信息比特数量，可以支持编码矩阵G下的信息比特构造。
一种可能的实施方式中，终端设备对待编码块进行编码，得到编码数据，具体可以包括：
根据每个待编码子块的信息比特数据，将所述K个信息比特分成m个子段；
确定每个编码子块的信息位和冻结位，并根据编码子块的数量m构造大小为m×2 n的信息序列；
根据所述信息序列中信息比特的位置，将所述K个信息比特插入到待编码序列中，并将待编码序列与编码矩阵进行模二乘处理，得到编码数据。
一种可能的实施方式中，所述编码矩阵为
Figure PCTCN2022110969-appb-000006
所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
所述矩阵O为大小为2 n×2 n的全零矩阵。
该方法中，设计了一种全新的Polar码编码矩阵G，当终端设备采用该编码矩阵G对待编码的信息比特进行编码时，可以在编码过程中接收一部分信息比特之后就可以对该部分信息比特进行编码并发送编码数据，实现了流编码，有利于降低终端设备中编码器和缓存的大小。
一种可能的实施方式中，发送编码数据(编码数据为根据编码矩阵G得到的)时，首先发送第m-1个待编码子块，再依次发送第i个编码子块，所述i满足0≤i≤m-2。
该方法中，设计了编码数据的发送顺序，有利于译码侧实现流译码。
一种可能的实施方式中，编码矩阵为
Figure PCTCN2022110969-appb-000007
所述G′为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
所述矩阵O为大小为2 n×2 n的全零矩阵。
一种可能的实施方式中，发送编码数据(编码数据为根据编码矩阵G′得到的)时，依次发送第i个编码子块，所述i满足0≤i≤m-1。
可选的，上述第一方面中所述的方法，也可以通过网络设备所执行。在这种情况下，网络设备为编码侧，终端设备为译码侧。
第二方面，本申请提供另一种数据处理方法，该数据处理方法可以由终端设备或网络设备所执行。其中，以网络设备为执行主体，且网络设备为译码侧为例，网络设备接收编码数据，并对编码数据进行译码，得到译码数据。其中，编码数据是由待编码块进行编码得到的，待编码块包括多个待编码子块，待编码块中每个待编码子块的信息比特数量是根据待编码块的长度和分配序列确定的，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。
该方法中，由于编码数据包括多个编码块，并且多个编码块中的信息比特数量的按照一定的规律设计的，则可以针对该编码数据实现流译码。
一种可能的实施方式中，待编码块的长度为E＝K/R，R为码率；
待编码块包括m个待编码子块，
Figure PCTCN2022110969-appb-000008
编码数据包括编码块，编码块包括m个编码子块，编码子块大小为N′，N′＝2 n；
分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
一种可能的实施方式中，每个待编码子块的长度为：
E 0＝E-(m-1)×N′，或者，E i＝N′，i∈{1,2,...,m-2,m-1}。
一种可能的实施方式中，当i＝0时，第0个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000009
所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i＝1时，第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i∈{2,3,...,m-2}时，第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-1时，第m-1个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000010
一种可能的实施方式中，每个待编码子块的长度为：
E m-2＝E-(m-1)×N′，或者，E i＝N′，i∈{0,1,2,...,m-3,m-1}。
一种可能的实施方式中，当i∈{2,3,...,m-3}时，第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-2时，第m-2个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000011
所述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
当i＝m-1时，第m-1个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000012
一种可能的实施方式中，编码数据是采用编码矩阵G进行编码得到的，编码矩阵
Figure PCTCN2022110969-appb-000013
G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
一种可能的实施方式中，网络设备对编码数据进行译码，得到译码数据，具体可以包括：
获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子块为第m-1个编码子块，第1个接收子块为第0个编码子块；
将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第1个接收子块对应的标记数据，
对F运算后的第1个接收子块对应的标记数据进行Polar码译码，得到第1个接收子块对应的译码数据；
根据所述第1个接收子块对应的标记数据和所述第1个接收子块对应的译码数据对所述第0个接收子块对应的标记数据进行增强。
该方法中，网络设备基于首次接收的第0个接收子块及其相邻的第1个接收子块进行译码，从而实现了流译码，并且对第0个接收子块进行增强，有利于后续译码过程中基于增强后的第0个接收子块实现流译码。
一种可能的实施方式中，网络设备获取第q个接收子块对应的标记数据，第q个接收子块为第q-1个编码子块，q为2≤q≤m-1；将所述第q个接收子块对应的标记数据与增强后的第0个接收子块对应的标记数据进行F运算，得到F运算后的第q个接收子块对应的标记数据；对F运算后的第q个接收子块对应的标记数据进行Polar码译码，得到第q个接收子块对应的译码数据；根据所述第q个接收子块对应的标记数据和所述第q个接收子块对应的译码数据对所述增强后的第0个接收子块对应的标记数据进行增强。
该方法中，对于第2个接收子块直至第m-1个接收子块，都采用相同的方法进行译码。并且，随着译码的进行不断增强第0个接收子块对应的标记数据，有利于实现流译码。
一种可能的实施方式中，编码数据是采用编码矩阵G′进行编码得到的，编码矩阵
Figure PCTCN2022110969-appb-000014
G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
一种可能的实施方式中，网络设备对编码数据进行译码，得到译码数据，具体可以包括：
获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子 块为第0个编码子块，第1个接收子块为第1个编码子块；
将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第0个接收子块对应的标记数据，
对F运算后的第0个接收子块对应的标记数据进行Polar码译码，得到第0个接收子块对应的译码数据；
根据所述第0个接收子块对应的标记数据和所述第0个接收子块对应的译码数据对所述第1个接收子块对应的标记数据进行增强。
一种可能的实施方式中，网络设备获取第p个接收子块对应的标记数据，第p个接收子块为第p个编码子块，p为2≤p≤m-1；将第p个接收子块对应的标记数据与增强后的第p-1个接收子块对应的标记数据进行F运算，得到F运算后的第p-1个接收子块对应的标记数据；对F运算后的第p-1个接收子块对应的标记数据进行Polar码译码，得到第p-1个接收子块对应的译码数据；根据增强后的第p-1个接收子块对应的标记数据和所述第p-1个接收子块对应的译码数据对第p个接收子块对应的标记数据进行增强。
可选的，上述第二方面中所述的方法，也可以通过终端设备所执行。在这种情况下，网络设备为编码侧，终端设备为译码侧。
第三方面，本申请实施例提供一种数据处理装置，该数据处理装置可以是终端设备，也可以是终端设备中的装置，或者是能够和终端设备匹配使用的装置。一种设计中，该数据处理装置可以包括执行如第一方面和第二方面中描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合软件实现。一种设计中，该装置可以包括处理单元和收发单元。
其中，对数据处理装置执行的方法/操作/步骤/动作的具体描述可以参考上述第一方面和第二方面中对应的描述，此处不再赘述。可以理解的是，该数据处理装置也可以实现如第一方面和第二方面中可以实现的效果。
第四方面，本申请实施例提供一种数据处理装置，该数据处理装置可以是网络设备，也可以是网络设备中的装置，或者是能够和网络设备匹配使用的装置。一种设计中，该数据处理装置可以包括执行如第一方面和第二方面中描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合软件实现。一种设计中，该数据处理装置可以包括处理单元和收发单元。
其中，对数据处理装置执行的方法的具体描述可以参考上述第一方面和第二方面中对应的描述，此处不再赘述。可以理解的是，该数据处理装置也可以实现如第一方面和第二方面中可以实现的效果。
第五方面，本申请实施例提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如第一方面和第一方面任一种可能的实施方式中的方法对数据进行处理，获取处理后的数据。
第六方面，本申请实施例提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如第二方面和第二方面任一种可能的实施方式中的方法对数据进行处理，获取处理后的数据。
第七方面，本申请实施例提供一种通信设备，包括：处理器，该处理器与存储器耦合，该存储器用于存储指令，当指令被处理器执行时，使得该终端设备实现上述第一方面或第二方面任一种可能的实施方式中的方法。
一种可能的实施方式中，通信设备为终端设备。
另一种可能的实施方式中，通信设备为网络设备。
第八方面，本申请提供一种通信系统。该通信系统包括第三方面和第四方面提供的数据处理装置的一种或多种装置。或者该通信系统包括如第七方面提供的终端设备和网络设备。
一种可能的实施方式中，该通信系统包括发送端和接收端，发送端用于执行第一方面以及第一方面的可能实现的方式中的任一项所述的方法。接收端用于执行第二方面以及第二方面的可能实现的方式中的任一项所述的方法。
第九方面，本申请提供一种芯片系统。该芯片系统包括处理器，还可以包括存储器，用于实现上述第一方面以及第一方面任一种可能的实施方式中的方法，或者第二方面以及第二方面任一种可能的实施方式中的方法。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
其中，芯片中的接口可以为输入/输出接口、管脚或电路等。
上述芯片系统可以是片上系统(system on chip，SOC)，也可以是基带芯片等，其中基带芯片可以包括处理器、信道编码器、数字信号处理器、调制解调器和接口模块等。
第十方面，本申请提供一种计算机可读存储介质。上述计算机可读存储介质存储有计算机程序。上述计算机程序被处理器执行以实现执行第一方面以及第一方面任一种可能的实施方式中的方法，或者第二方面以及第二方面任一种可能的实施方式中的方法。
第十一方面，本申请中提供一种计算机程序产品。该计算机程序产品包括指令。当所述指令在计算机上运行时，使得计算机执行第一方面以及第一方面任一种可能的实施方式中的方法，或者第二方面以及第二方面任一种可能的实施方式中的方法。
附图说明
图1为本申请提供的一种通信系统的示意图；
图2为一种8×8的polar码编码示意图；
图3为一种译码过程中计算对数似然比LLR的示意图；
图4为另一种译码过程中计算对数似然比LLR的示意图；
图5a为一种编码子块的信息比特数量的示意图；
图5b为另一种编码子块的信息比特数量的示意图；
图6为本申请提供的第一种数据处理方法的流程示意图；
图7为本申请提供的第二种数据处理方法的流程示意图；
图8为本申请提供的数据处理方法的性能分析图；
图9为本申请提供的一种装置的示意图；
图10为本申请提供的一种通信设备的示意图。
具体实施方式
在本申请中，“/”可以表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；“和/或”可以用于描述关联对象存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。为了便于描述本申请的技术方案，在本申请中，可以采用“第一”、“第二”等字样对功能相同或相似的技术特征进行区分。该“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。在本申请中，“示例性的”或者“例如”等词用于表示例子、例证或说明，被描述为“示例性的”或者“例如”的任何或设计方案不应被解释为比其它或设计方案更优选或更具优势。使用“示例性的”或者“例如”等词旨在以具 体方式呈现相关概念，便于理解。
下面将结合本申请中的附图，对本申请中的技术方案进行描述。
本申请提供了一种数据处理方法，该方法设计了一种基于分配序列的信息比特构造和编码方法。该数据处理方法可以应用于通信系统中，系统架构如图1所示。其中，该通信系统包括网络设备和终端设备，网络设备可以向终端设备提供通信服务。
本申请提及的通信系统包括但不限于：窄带物联网系统(narrow band-Internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access，CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)以及5G移动通信系统的三大应用场景增强移动宽带(enhanced mobility broad band，eMBB)，超高可靠与低时延通信(ultra-reliable and low latency communications，URLLC)和增强型机器类通信(enhanced machine-type communication，eMTC)以及未来的通信系统(例如6G/7G等)。
其中，网络设备可以是能和终端设备进行通信的设备。网络设备可以是基站、中继站或接入点。其中，基站可以是全球移动通信(global system for mobile communication，GSM)系统或码分多址(code division multiple access，CDMA)网络中的基站收发台(base transc eiver station，BTS)，也可以是宽带码分多址(wideband code division multiple access，WC DMA)系统中的3G基站NodeB，还可以是长期演进(long term evolution，LTE)系统中的evolutional NodeB(简称为eNB或eNodeB)。网络设备还可以是卫星通信系统中的卫星。网络设备还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。网络设备还可以是5G网络中的网络设备或者未来演进的共用陆地移动网(public land mobil e network，PLMN)网络中的网络设备(例如gNodeB)。网络设备还可以是可穿戴设备、无人机，或者车联网中的设备(例如车联万物设备(vehicle to everything，V2X))，或者设备间(device to device，D2D)通信中的通信设备，或者应用于未来的通信系统中的网络设备。
其中，终端设备可以是用户设备(user equipment，UE)、接入终端、终端单元、终端站、移动站、移动台、远方站、远程终端、移动设备、终端、无线通信设备、终端代理或终端装置等。接入终端可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、可穿戴设备、无人机、V2X设备、D2D设备，5G网络中的终端设备、未来演进的PLMN网络中的终端设备或未来的通信系统中的终端设备等。
可以理解的是，本申请包括编码方案，可以用于专用网设备或者通用设备，可以用于网络设备，也可以用于各种终端设备等。本申请可以通过专用芯片(例如专用集成电路(application specific integrated circuit，ASIC)实现，也可以通过可编程芯片(例如现场可编程逻辑门阵列(field programmable gate array，FPGA)实现，还可以通过软件(存储器中程序代码)实现，本申请不作限定。
一、本申请的相关概念
1、本申请基于Polar码编码：
Polar码是一种能够被严格证明达到信道容量的信道编码方案，Polar码具有高性能，低 复杂度，匹配方式灵活等特点。目前Polar码已经被确定为第五代移动通信(the 5 th generation，5G)控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景的上行和/或下行控制信道编码方案。
例如，图2为一种8×8的polar码编码示意图，其中，待编码比特按照各自的可靠度进行排序，依次排列在待编码块中的不同位置。通常来说，可靠度较高的比特被设置为信息比特(data)，可靠度较低的比特被设置为固定比特(frozen)。固定比特的值通常设置为0，在实际传输中发送端和接收端都已知。如图2所示，u 7,u 6,u 5,u 3为可靠度靠前的四位比特，分别设置为信息比特；u 4,u 2,u 1,u 0为可靠度靠后的四位比特，分别设置为固定比特。
其中，Polar码是一种线性块码。其生成矩阵为G N，其编码过程为
Figure PCTCN2022110969-appb-000015
其中，
Figure PCTCN2022110969-appb-000016
是一个二进制的行矢量，长度为N(即码长)。G N是一个N×N的矩阵，且
Figure PCTCN2022110969-appb-000017
其中，
Figure PCTCN2022110969-appb-000018
定义为log 2(N)个矩阵F 2的克罗内克(Kronecker)乘积。例如，当N＝4时，log 2(N)＝log 2(4)＝2，则
Figure PCTCN2022110969-appb-000019
当N＝8时，log 2(N)＝log 2(8)＝3，则
Figure PCTCN2022110969-appb-000020
因此，标准的Polar码的母码长度N＝2 n，n为正整数。
2、本申请提供的第一种Polar码编码矩阵G：
本申请提供的编码矩阵
Figure PCTCN2022110969-appb-000021
其中，G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，表示为
Figure PCTCN2022110969-appb-000022
矩阵O为大小为2 n×2 n的全零矩阵。
也就是说，如果将该编码矩阵G视为一个m×m的矩阵，矩阵中的每一个元素均为一个2 n×2 n的矩阵，矩阵的对角线中各元素均为矩阵G N′，矩阵的底边中各元素均为矩阵G N′，除对角线和底边之外的元素均为矩阵O。
其中，该编码矩阵G的母码长度N′＝m×2 n。可以理解的是，当m＝1或者m＝2时，该编码矩阵G和普通Polar码的编码矩阵相同。当m≥3时，编码矩阵
Figure PCTCN2022110969-appb-000023
3、基于编码矩阵G计算每个G N′的对数似然比(log likelihood ratio，LLR)的均值变化：
当译码侧接收基于编码矩阵G得到的编码数据后，可以对编码数据进行译码。例如，译码过程如图3所示。译码侧可以根据编码矩阵G，计算每个G N′的LLR的均值变化。假设在加性高斯白噪声(additive white Gaussian noise，AWGN)信道下，接收LLR的均值为L。如图3所示，可以通过高斯近似方程(Gaussian approximate function，GAF)来计算每个G N′在被最后一个耦合子块解耦以后的LLR分布均值。因此可以计算每个G N′大小的编码子块(接收子块)，在进入普通Polar码译码时的LLR均值。其中，每个G N′大小的编码子块的LLR均值如下公式所示：
Figure PCTCN2022110969-appb-000024
其中，
Figure PCTCN2022110969-appb-000025
为m-1个编码子块中除最后一个编码子块之外的任意一个编码子块的LLR均值，
Figure PCTCN2022110969-appb-000026
为最后一个编码子块的LLR均值。可见，除了最后一个编码子块，其他的m-1个编码子块的容量，只和自己的序号i有关，跟编码块的编码子块总数m无关。
4、本申请提供的第二种Polar码编码矩阵：
本申请提供的编码矩阵
Figure PCTCN2022110969-appb-000027
其中，G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，表示为
Figure PCTCN2022110969-appb-000028
矩阵O为大小为2 n×2 n的全零矩阵。
也就是说，如果将该编码矩阵G′视为一个m×m的矩阵，矩阵中的每一个元素均为一个2 n×2 n的矩阵，矩阵的下三角区域中各元素均为矩阵G N′，矩阵除下三角区域之外的元素均为矩阵O。其中，该编码矩阵G的母码长度N′＝m×2 n。
5、基于第二种编码矩阵计算每个G N′的LLR的均值变化。
当译码侧接收基于编码矩阵G′得到的编码数据后，可以对编码数据进行译码。例如，译码过程如图4所示。译码侧可以根据编码矩阵G′，计算每个G N′的LLR的均值变化。假设在AWGN信道下，接收LLR的均值为L。如图4所示，可以通过GAF来计算每个G N′在被最后一个耦合子块解耦以后的LLR分布均值。因此可以计算每个G N′大小的编码子块(接收子块)，在进入普通Polar码译码时的LLR均值。其中，每个G N′大小的编码子块的LLR均值如下公式所示：
Figure PCTCN2022110969-appb-000029
其中，
Figure PCTCN2022110969-appb-000030
为m-1个编码子块中除最后一个编码子块之外的任意一个编码子块的LLR均值，
Figure PCTCN2022110969-appb-000031
为最后一个编码子块的LLR均值。可见，除了最后一个编码子块，其他的m-1个编码子块的容量，只和自己的序号i有关，跟编码块的编码子块总数m无关。
6、基于每个G N′的LLR的均值变化确定每个子块信息分布结果
根据前文第2-5小节中的描述，无论采用编码矩阵G或者编码矩阵G′，其得到的编码结果通过信道以后，在子块解耦译码前，每个子块的LLR均值分布都如公式(1)所示。根据容量计算的结果，两种编码矩阵在各自的译码图上反应出来的每个相互对应的子块/信息比特的容量是一致的，因此可以采用相同的信息构造方法。
并且，根据编码子块的均值，除了最后一个编码子块，其他的m-1个编码子块的容量， 只和自己的序号i有关，跟编码块的编码子块总数m无关。因此，当固定一个码率和N′时，可以得到满足一定规律的编码子块的信息比特分布结果。例如，图5a表示R＝1/8，N′＝128时，信息比特的数量为32,48,64,…192时，每个编码子块的信息比特数量。可见，随着信息比特的数量逐渐增长，编码子块的数量也逐渐增长(例如从2增长到12)。图5a的第一行表示K＝32，m＝2，有两个编码子块，第一个编码子块分配到1个信息比特，第二个编码子块分配到31个信息比特。第二行表示K＝48，m＝3，有三个编码子块，第一个编码子块分配到1个信息比特，第二个编码子块分配到4个信息比特，第三个编码子块分配到43个信息比特，以此类推，如图5a所示。又例如，图5b表示R＝1/8，N′＝256时，信息长度为64,96,128,…384时，每个子块的信息数量。可见，随着信息比特的数量逐渐增长，编码子块的数量也逐渐增长(例如从2增长到12)。第一行表示K＝64，m＝2，有两个编码子块，第一个编码子块分配到5个信息比特，第二个编码子块分配到59个信息比特。第二行表示K＝96，m＝3，有三个编码子块，第一个编码子块分配到4个信息比特，第二个编码子块分配到6个信息比特，第三个编码子块分配到89个信息比特，以此类推，如图5b所示。根据图5a和图5b所示，除了最后一个编码子块外，其他的属于同一列的编码子块，其分配到的信息比特数量相同或者只相差1或2个信息比特。因此可以用一个分配序列来描述在相同的码率和编码子块大小的情况下，编码块中除最后一个编码子块之外的所有编码子块中的信息比特数量。可以理解的是，由于编码子块和待编码子块中包括的信息比特数量是相同的，待编码子块和编码子块的长度也是相同的，因此分配序列也可以用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。
7、F运算：
F运算为Polar码的译码基本运算，采用预定义的F函数(f-function)进行处理。其中，F函数的输入为L 0和L 1，且F函数可以简化为：
f(L 0,L 1)＝(sig(L 0)∧sig(L 1)？-1:1)*(abs(L 0)>abs(L 1)？abs(L 1):abs(L 0))，
其中，sig为取符号操作，如果立即数大于0，返回值为0，否则返回值为1。abs为取绝对值操作。例如，假设有长度均为N′的编码数据x 0和x m-1，对x 0和x m-1进行F运算，比较x 0和x m-1的符号，若两者一致则立即数的取值为1，否则取值为-1。
8、G运算：
G运算为Polar码的译码基本运算，采用预定义的G函数(g-function)进行处理。其中，G函数的输入为L 0、L 1和反馈值B，且G函数为：g(L 0,L 1,B)＝(B＝＝0)？L 1+L 0:L 1-L 0。
二、本申请提供的第一种数据处理方法
图6为本申请提供的第一种数据处理方法的流程示意图。该数据处理方法可以由终端设备所执行，也可以由网络设备所执行，主要执行编码的流程，包括以下步骤：
S101，获取K个信息比特。
S102，根据K个信息比特，确定待编码块的长度。
S103，根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量。
其中，待编码块用于承载K个信息比特，则待编码块的长度为E＝K/R，R为码率。待编码块包括m个待编码子块，待编码子块的大小为N′＝2 n，则
Figure PCTCN2022110969-appb-000032
可以理解的是，待编码块对应编码块，待编码子块对应编码子块，则编码块包括m个编码子块，编码子块的大 小为N′＝2 n。
其中，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。例如，假设分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}，分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。可以理解的是，当固定一个码率和N′时，可以得到满足一定规律的编码子块的信息比特分布结果，例如图5a和图5b所示的编码子块的信息比特分布结果，也即是图5a和图5b的每一行可以对应一个分配序列。例如，根据图5a，当固定码率R＝1/8，N′＝128时，假设信息比特数量K＝64，则分配序列为{1,4,5,54}。
具体来说，根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量，包括以下两种方式：
方式一：若分配后的待编码块将基于编码矩阵G进行编码，则可以确定每个待编码子块的长度如下公式(2)和(3)所示：
E i＝N′，i∈{0,1,2,...,m-3,m-1}  (2)
E m-2＝E-(m-1)×N′  (3)
其中，i为待编码子块的序号，m为待编码块的总数，N′为待编码块的大小，E为待编码块的长度。本申请中假设当待编码块编码后得到编码数据，并发送编码数据时，首先发送最后一个编码子块(那么倒数第二个编码子块将最后发送)，有利于实现流译码，则该方式在设计待编码子块中的信息比特数量时，倒数第二个待编码子块被视为最后一个子块，长度为待编码块的总长度减去其他待编码子块的长度之和，如公式(3)所示。
若分配后的待编码块将基于编码矩阵G进行编码，则可以确定每个待编码子块的信息比特数量如下公式(4)至(6)所示：
J i＝A i，i∈{2,3,...,m-3}  (4)
Figure PCTCN2022110969-appb-000033
Figure PCTCN2022110969-appb-000034
其中，J i为第i个待编码子块中的信息比特数量，A i为分配序列中的第i个元素，A m-2为分配序列中的第m-2个元素，Δ 2是根据第m-2个待编码子块的长度E m-2和N′的差值确定的，取值为0或1。
由上述公式(4)至(6)可知，待编码块中除最后一个和倒数第二个待编码子块之外的其他待编码子块的信息比特数量等于分配序列中对应序号的变量值；倒数第二个待编码子块的信息比特数量是根据该待编码子块的长度、分配序列中倒数第二个序号的变量值、N′、Δ 2等参数值确定的；最后一个待编码子块的信息比特数量等于信息比特总数K减去其他待编码子块的信息比特数量之和。也就是说，一旦确定了分配序列，可以比较简单快速地确定每个待编码子块的信息比特数量，从而有利于更简单快速地实现信息位的构造。
方式二：若分配后的待编码块将基于编码矩阵G′或者编码矩阵G进行编码，则可以确定每个待编码子块的长度如下公式(7)和(8)所示：
E 0＝E-(m-1)×N′  (7)
E i＝N′，i∈{1,2,...,m-2,m-1}  (8)
其中，i为待编码子块的序号，m为待编码块的总数，N′为待编码块的大小。本申请中假设当待编码块编码后得到编码数据，并发送编码数据时，首先发送第0个编码子块，有利于实现流译码，则该方式在设计待编码子块中的信息比特数量时，第0个待编码子块被视为 最后一个子块，长度为待编码块的总长度减去其他待编码子块的长度之和，如公式(7)所示。
若分配后的待编码块将基于编码矩阵G′或者编码矩阵G进行编码，则可以确定每个待编码子块的信息比特数量如下公式(9)至(12)所示：
Figure PCTCN2022110969-appb-000035
J 1＝A 1-Δ 1  (10)
J i＝A i，i∈{2,3,...,m-2}  (11)
Figure PCTCN2022110969-appb-000036
其中，J i为第i个待编码子块中的信息比特数量，A i为分配序列中的第i个元素，Δ 0是根据第0个待编码子块的长度E 0和N′的差值确定的，取值为0或1，Δ 1是根据第0个待编码子块的长度E 0和N′的差值确定的，取值为0或1。其中，生成分配序列时，默认第0个待编码子块的长度E 0是满额的；若第0个待编码子块的长度E 0打孔较多，则可能导致第1个待编码子块被增加的容量受限，则需要通过参数Δ 1对E 1进行调整，则Δ 1是根据第0个待编码子块的长度E 0和N′的差值确定的。
由上述公式(9)至(12)可知，待编码块中除最后一个、第0个和第1个待编码子块之外的其他待编码子块的信息比特数量等于分配序列中对应序号的变量值；第0个待编码子块的信息比特数量是根据该待编码子块的长度、分配序列中第0个序号的变量值、N′、Δ 0等参数值确定的；第1个待编码子块的信息比特数量是根据分配序列中第1个序号的变量值和Δ 1等参数值确定的；最后一个待编码子块的信息比特数量等于信息比特总数K减去其他待编码子块的信息比特数量之和。也就是说，一旦确定了分配序列，可以比较简单快速地确定每个待编码子块的信息比特数量，从而有利于更简单快速地实现信息位的构造。
S104，对待编码块进行编码，得到编码数据。
S105，发送编码数据。
其中，对待编码块进行编码，得到编码数据，可以包括以下步骤：
s11，根据每个待编码子块的信息比特数据，将K个信息比特分成m个子段；
s12，确定每个编码子块的信息位和冻结位，并根据编码子块的数量m构造大小为m×2 n的信息序列；
s13，根据信息序列中信息比特的位置，将K个信息比特插入到待编码序列中，并将待编码序列与编码矩阵进行模二乘处理，得到编码数据。
其中，当采用不同的编码矩阵时，得到的编码数据是不相同的。
方式一：当采用编码矩阵为
Figure PCTCN2022110969-appb-000037
时，对编码矩阵G的详细描述可以参考前文对应的描述。
例如，对于任意一个编码块的编码子块，根据编码子块的长度，确定N′的冻结位置，并根据一个大小为N′的序列，构造信息位。冻结位的选择可以采用现有协议中的规定，也可以另行设计，本申请不作限定。根据每个编码子块的信息位和冻结位，以及编码子块的数量m，可以构造大小为m×2 n的信息序列u N＝{u 0,u 1,u 2,...,u N-1}，并将该信息序列u N与编码矩阵G 进行模二乘，得到编码结果为
Figure PCTCN2022110969-appb-000038
又例如，可以将u N分成m个分段
Figure PCTCN2022110969-appb-000039
每个分段的长度为N′；根据编码矩阵G，使得每个分段与G N′进行模二乘，得到的结果为
Figure PCTCN2022110969-appb-000040
从而得到编码结果为
Figure PCTCN2022110969-appb-000041
方式一中，当生成编码数据后，将发送编码数据，其中，发送编码数据的顺序可以是：
首先发送第m-1个待编码子块，
再依次发送第i个编码子块，0≤i≤m-2。
可以理解的是，采用这种发送编码数据的顺序，有利于译码侧实现流译码。
方式二：当采用编码矩阵为
Figure PCTCN2022110969-appb-000042
时，对编码矩阵G′的详细描述可以参考前文对应的描述。
例如，对于任意一个编码块的编码子块，根据编码子块的长度，确定N′的冻结位置，并根据一个大小为N′的序列，构造信息位。冻结位的选择可以采用现有协议中的规定，也可以另行设计，本申请不作限定。根据每个编码子块的信息位和冻结位，以及编码子块的数量m，可以构造大小为m×2 n的信息序列u N＝{u 0,u 1,u 2,...,u N-1}，并将该信息序列u N与编码矩阵G进行模二乘，得到编码结果为
Figure PCTCN2022110969-appb-000043
又例如，可以将u N分成m个分段
Figure PCTCN2022110969-appb-000044
每个分段的长度为N′；根据编码矩阵G′，使得每个分段与G N′进行模二乘，得到的结果为
Figure PCTCN2022110969-appb-000045
相邻的数据依次从后往前进行耦合(例如，从第m-2个开始依次向前，直至第0个)，从而得到编码结果为
Figure PCTCN2022110969-appb-000046
方式二中，当生成编码数据后，将发送编码数据，其中，发送编码数据的顺序可以是：
依次发送第i个编码子块，0≤i≤m-1。
可见，本申请提供的第一种数据处理方法设计了一种基于分配序列的信息比特构造和编码方法，该信息比特构造方法简单有效，有利于提高系统性能，降低系统功耗。并且，该方法可以支持编码子块的长度不足2 n的整数倍时的信息比特构造和速率匹配。并且，采用编码矩阵G对待编码的信息比特进行编码得到编码数据，有利于实现流译码。
三、本申请提供的第二种数据处理方法
图7为本申请提供的第二种数据处理方法的流程示意图。该数据处理方法可以由终端设 备所执行，也可以由网络设备所执行。可以理解的是，当终端设备执行此处第三部分描述的数据处理方法时，即终端设备为译码侧，则网络设备执行前述第二部分中描述的数据处理方法，即网络设备为编码侧。当执行译码的流程时，包括以下步骤：
S201，接收编码数据，编码数据是由待编码块进行编码得到的。
其中，待编码块包括多个待编码子块，待编码块中每个待编码子块的信息比特数量是根据待编码块的长度和分配序列确定的，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。
其中，对待编码块、待编码子块、编码块、编码子块、待编码块中的信息比特数量、分配序列以及如何对待编码块进行编码的描述参考前文第二部分中对应的描述，此处不再赘述。例如，为了支持流译码，编码数据可以是基于编码矩阵G对信息比特序列进行编码得到的。
S202，对编码数据进行译码，得到译码数据。
其中，当编码数据采用不同的编码矩阵得到时，对应的译码流程是不相同的，包括以下两种情况：
情况一：若编码数据是采用编码矩阵G进行编码得到的，对编码数据进行译码的过程为流译码流程，终端设备可以先对接收到的第0个接收子块和第1个接收子块进行译码，也即是，在译码过程中接收一部分信息后就能对该部分信息进行译码。具体来说，可以包括以下步骤：
s11，获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子块为第m-1个编码子块，第1个接收子块为第0个编码子块；
s12，将第0个接收子块对应的标记数据和第1个接收子块对应的标记数据进行F运算，得到F运算后的第1个接收子块对应的标记数据；
s13，对F运算后的第1个接收子块对应的标记数据进行Polar码译码，得到第1个接收子块对应的译码数据；
s14，根据第1个接收子块对应的标记数据和第1个接收子块对应的译码数据对第0个接收子块对应的标记数据进行增强。
其中，第0个接收子块对应的标记数据为第0个接收子块的对数似然比(log likelihood ratio，LLR)，也即是第m-1个编码子块的LLR；第1个接收子块对应的标记数据为第1个接收子块的LLR，也即是第0个编码子块的LLR。将第0个接收子块的LLR和第1个接收子块的LLR作为F函数的输入，得到F运算后的第1个接收子块对应的标记数据(也即是，解耦后接收的编码数据)。其中，对F函数的描述参考前文的描述，此处不再赘述。
其中，对F运算后的第1个接收子块对应的标记数据进行Polar码译码的方法可以参考现有的Polar码译码方式，本申请不作限定。将第0个接收子块的LLR、第1个接收子块的LLR和第1个接收子块对应的译码数据作为G函数的输入，从而实现对第0个接收子块对应的标记数据进行增强(也即是，增强先接收的编码数据)，有利于后续译码过程中基于增强后的第0个接收子块实现流译码。其中，对G函数的描述参考前文的描述，此处不再赘述。
可选的，第0个接收子块对应的标记数据可以为第0个接收子块的似然概率，第1个接收子块对应的标记数据可以为第1个接收子块的似然概率。在这种情况下，上述步骤s12将变为：将第0个接收子块对应的标记数据和第1个接收子块对应的标记数据进行概率运算，得到在概率域中的第1个接收子块对应的标记数据。可以理解的是，后续的处理流程仍然按照s13和s14执行，可以实现对第0个接收子块对应的标记数据进行增强。
进一步，针对后续接收的每一个接收子块，处理方式与上述s11～s14是类似的，可以包 括以下步骤：
s15，获取第q个接收子块对应的标记数据，q为2≤q≤m-1，第q个接收子块为第q-1个编码子块；
s16，将第q个接收子块对应的标记数据与增强后的第0个接收子块对应的标记数据进行F运算，得到F运算后的第q个接收子块对应的标记数据；
s17，对F运算后的第q个接收子块对应的标记数据进行Polar码译码，得到第q个接收子块对应的译码数据；
s18，根据第q个接收子块对应的标记数据和第q个接收子块对应的译码数据对增强后的第0个接收子块对应的标记数据进行增强。
例如，获取第2个接收子块对应的标记数据，并将第2个接收子块对应的标记数据与增强后的第0个接收子块对应的标记数据进行F运算，得到F运算后的第2个接收子块对应的标记数据；对F运算后的第2个接收子块对应的标记数据进行Polar码译码，得到第2个接收子块对应的译码数据，根据第2个接收子块对应的标记数据和第2个接收子块对应的译码数据对增强后的第0个接收子块对应的标记数据进行二次增强，得到二次增强后的第0个接收子块对应的标记数据。上述步骤的具体实施方式，可以参考s11～s14对应的具体实施方式，此处不再赘述。
情况二：若编码数据是采用编码矩阵G′进行编码得到的，对编码数据进行译码的过程可以包括以下步骤：
s21，获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子块为第0个编码子块，第1个接收子块为第1个编码子块；
s22，将第0个接收子块对应的标记数据和第1个接收子块对应的标记数据进行F运算，得到F运算后的第0个接收子块对应的标记数据，
s23，对F运算后的第0个接收子块对应的标记数据进行Polar码译码，得到第0个接收子块对应的译码数据；
s24，根据第0个接收子块对应的标记数据和第0个接收子块对应的译码数据对第1个接收子块对应的标记数据进行增强。
其中，第0个接收子块对应的标记数据为第0个接收子块的LLR，第1个接收子块对应的标记数据为第1个接收子块的LLR。将第0个接收子块的LLR和第1个接收子块的LLR作为F函数的输入，得到F运算后的第0个接收子块对应的标记数据(也即是，解耦先接收的编码数据)。其中，对F函数的描述参考前文的描述，此处不再赘述。
其中，对F运算后的第0个接收子块对应的标记数据进行Polar码译码的方法可以参考现有的Polar码译码方式，本申请不作限定。将第1个接收子块的LLR、第0个接收子块的LLR和第0个接收子块对应的译码数据作为G函数的输入，从而实现对第1个接收子块对应的标记数据进行增强(也即是，增强后接收的编码数据)。其中，对G函数的描述参考前文的描述，此处不再赘述。
可选的，第0个接收子块对应的标记数据可以为第0个接收子块的似然概率，第1个接收子块对应的标记数据可以为第1个接收子块的似然概率。在这种情况下，上述步骤s22将变为：将第0个接收子块对应的标记数据和第1个接收子块对应的标记数据进行概率运算，得到在概率域中的第0个接收子块对应的标记数据。可以理解的是，后续的处理流程仍然按照s23和s24执行，可以实现对第1个接收子块对应的标记数据进行增强。
进一步，针对后续接收的每一个接收子块，处理方式与上述s21～s24是类似的，可以包 括以下步骤：
s25，获取第p个接收子块对应的标记数据，p为2≤p≤m-1，第p个接收子块为第p个编码子块；
s26，将第p个接收子块对应的标记数据与增强后的第p-1个接收子块对应的标记数据进行F运算，得到F运算后的第p-1个接收子块对应的标记数据；
s27，对F运算后的第p-1个接收子块对应的标记数据进行Polar码译码，得到第p-1个接收子块对应的译码数据；
s28，根据增强后的第p-1个接收子块对应的标记数据和第p-1个接收子块对应的译码数据对第p个接收子块对应的标记数据进行增强。
例如，获取第2个接收子块对应的标记数据，并将第2个接收子块对应的标记数据与增强后的第1个接收子块对应的标记数据进行F运算，得到F运算后的第1个接收子块对应的标记数据；对F运算后的第1个接收子块对应的标记数据进行Polar码译码，得到第1个接收子块对应的译码数据，根据第1个接收子块对应的标记数据和第1个接收子块对应的译码数据对第2个接收子块对应的标记数据进行增强，得到增强后的第2个接收子块对应的标记数据。上述步骤的具体实施方式，可以参考s21～s24对应的具体实施方式，此处不再赘述。
可见，本申请提供的数据处理方法在接收该编码数据后，可以支持在译码过程中接收一部分信息后就能对该部分信息进行译码，也即是实现了流译码，可以降低译码器的大小，从而降低译码侧的开销。
四、对本申请提供的数据处理方法应用于译码场景中的性能分析
图8为本申请提供的数据处理方法的性能分析图。该性能分析图是采用码长为N′＝{128,256,512}，码率R＝1/8的仿真译码器得到的译码性能示意图，其中，该性能分析图的横坐标为EsN0，表示每个符号能量与噪声功率谱密度的比值；纵坐标为误块率(block error rate，BLER)，用来衡量系统性能测试。例如，当N′＝128，R＝1/8时，假设分配序列为A＝{1,4,5,6,6,8,9,9,10,10,10}；当N′＝256，R＝1/8时，假设分配序列为A＝{3,6,10,13,16,17,18,19,20,21,21}。并且，假设Δ 0＝1，Δ 1＝1。
其中，带有圆形符号的实线、带有星号的虚线和带有正方形符号的虚线三种线型为一组，可以用于对比不同的信息比特数量下，采用不同大小的译码器和不同的译码方式时，译码性能的区别。
1、分别带有圆形符号的实线、带有星号的虚线和带有正方形符号的虚线为一组译码性能对比，如图8中的(一)所示。其中，假设信息比特个数K＝48，则发送长度E＝K/R＝48/(1/8)＝384；假设译码器大小为128、256或512，译码方式为采用现有的Polar码译码或者采用本申请提供的流译码。例如，带有圆形符号的实线表示译码器大小为128，信息比特个数为K＝48，此时编码子块的数量为3，且采用本申请提供的流译码时的译码性能；带有星号的虚线表示译码器大小为512，信息比特个数为K＝48，且采用普通的Polar码译码的译码性能；带有正方形符号的虚线表示译码器大小为256，信息比特个数为K＝48，且采用普通的Polar码译码时的译码性能。对上述性能进行比较可见，带有星号的虚线表示译码器大小为512的译码结果，因为最大译码长度可以支持512(512大于发送长度384)，因此不分段，所以性能略好于带有圆形符号的实线表示的本申请的译码性能，但是其译码器的大小比本申请大一倍，本申请显著降低了译码侧的开销。带有正方形符号的虚线表示译码器大小为256的译码结果，因为最大译码长度可以支持256(256小于发送长度384)，因此分 两段，所以性能差于带有圆形符号的实线表示的本申请的译码性能。
2、分别带有圆形符号的实线、带有星号的虚线和带有正方形符号的虚线为一组译码性能对比，如图8中的(六)所示。其中，假设信息比特序列中信息比特个数为K＝88，则发送长度E＝K/R＝88/(1/8)＝704；假设译码器大小为128、256或512，译码方式为采用现有的Polar码译码或者采用本申请提供的流译码。例如，带有圆形符号的实线表示译码器大小为128，信息比特个数为K＝88，且采用本申请的流译码时的译码性能；此时码长不为译码器大小的整数倍，则可以将第一个编码子块进行速率匹配(例如进行打孔处理，打孔64个比特位置)。带有星号的虚线表示译码器大小为512，信息比特个数为K＝88，且采用普通的Polar码译码的译码性能；带有正方形符号的虚线表示译码器大小为256，信息比特个数为K＝88，且采用普通的Polar码译码时的译码性能。对上述性能进行比较可见，带有星号的虚线表示译码器大小为512的译码结果，因为最大译码长度可以支持512(512小于发送长度704)，因此分两段，所以性能差于带有圆形符号的实线表示的本申请的译码性能；并且其译码器的大小比本申请大一倍，本申请显著降低了译码侧的开销。带有正方形符号的虚线表示译码器大小为256的译码结果，因为最大译码长度可以支持256(256小于发送长度704)，因此分三段，所以性能差于带有圆形符号的实线表示的本申请的译码性能。
可以理解的是，图8中的其他子图(二)至(五)中的性能分析可以参考上述两个小节中的性能分析，此处不再赘述。
为了实现本申请提供的方法中的各功能，本申请提供的装置或设备可以包括硬件结构和/或软件模块，以硬件结构、软件模块、或硬件结构加软件模块的形式来实现上述各功能。上述各功能中的某个功能以硬件结构、软件模块、还是硬件结构加软件模块的方式来执行，取决于技术方案的特定应用和设计约束条件。本申请中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。另外，在本申请各个实施例中的各功能模块可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
图9为本申请提供的一种装置的示意图。该装置可以包括执行如图3至图7对应的方法实施例中所描述的方法/操作/步骤/动作所一一对应的模块，该模块可以是硬件电路，也可以是软件，也可以是硬件电路结合软件实现。例如，该装置可以称为数据处理装置，也可以称为通信装置。
该装置包括通信单元901和处理单元902，用于实现前述实施例中终端设备或者网络设备所执行的方法。
一种可能的实施方式中，通信单元901用于获取K个信息比特，处理单元902用于根据所述K，确定待编码块的长度，根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量。其中，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。处理单元902用于对待编码块进行编码，得到编码数据，通信单元901用于发送编码数据。
可选的，待编码块的长度为E＝K/R，R为码率；
待编码块包括m个待编码子块，
Figure PCTCN2022110969-appb-000047
编码数据包括编码块，编码块包括m个编码子块，编码子块大小为N′，N′＝2 n；
分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
可选的，每个待编码子块的长度为：
E 0＝E-(m-1)×N′，或者，E i＝N′，i∈{1,2,...,m-2,m-1}。
可选的，处理单元902用于根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量，具体可以包括：
当i＝0时，确定第0个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000048
所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i＝1时，确定第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i∈{2,3,...,m-2}时，确定第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-1时，确定第m-1个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000049
可选的，每个待编码子块的长度为：
E m-2＝E-(m-1)×N′，或者，E i＝N′，i∈{0,1,2,...,m-3,m-1}。
可选的，处理单元902用于根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量，具体可以包括：
当i∈{2,3,...,m-3}时，确定第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-2时，确定第m-2个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000050
所述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
当i＝m-1时，确定第m-1个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000051
可选的，处理单元902用于对待编码块进行编码，得到编码数据，具体可以包括：
根据每个待编码子块的信息比特数据，将所述K个信息比特分成m个子段；
确定每个编码子块的信息位和冻结位，并根据编码子块的数量m构造大小为m×2 n的信息序列；
根据所述信息序列中信息比特的位置，将所述K个信息比特插入到待编码序列中，并将待编码序列与编码矩阵进行模二乘处理，得到编码数据。
可选的，所述编码矩阵为
Figure PCTCN2022110969-appb-000052
所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
所述矩阵O为大小为2 n×2 n的全零矩阵。
可选的，通信单元901用于发送编码数据(编码数据为根据编码矩阵G得到的)时，首先发送第m-1个待编码子块，再依次发送第i个编码子块，所述i满足0≤i≤m-2。
可选的，编码矩阵为
Figure PCTCN2022110969-appb-000053
所述G′为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
所述矩阵O为大小为2 n×2 n的全零矩阵。
可选的，通信单元901用于发送编码数据(编码数据为根据编码矩阵G′得到的)时，依次发送第i个编码子块，所述i满足0≤i≤m-1。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该通信装置所实现的数据处理方法设计了一种基于分配序列的信息比特构造和编码方法，该信息比特构造方法简单有效，有利于提高系统性能，降低系统功耗。并且，该方法可以支持编码子块的长度不足2 n的整数倍时的信息比特构造和速率匹配。
另一种可能的实施方式中，通信单元901用于接收编码数据，处理单元902用于对编码数据进行译码，得到译码数据。其中，编码数据是由待编码块进行编码得到的，待编码块包括多个待编码子块，待编码块中每个待编码子块的信息比特数量是根据待编码块的长度和分配序列确定的，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。
可选的，待编码块的长度为E＝K/R，R为码率；
待编码块包括m个待编码子块，
Figure PCTCN2022110969-appb-000054
编码数据包括编码块，编码块包括m个编码子块，编码子块大小为N′，N′＝2 n；
分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
可选的，每个待编码子块的长度为：
E 0＝E-(m-1)×N′，或者，E i＝N′，i∈{1,2,...,m-2,m-1}。
可选的，当i＝0时，第0个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000055
所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i＝1时，第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
当i∈{2,3,...,m-2}时，第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-1时，第m-1个待编码子块的信息比特数量为
Figure PCTCN2022110969-appb-000056
可选的，每个待编码子块的长度为：
E m-2＝E-(m-1)×N′，或者，E i＝N′，i∈{0,1,2,...,m-3,m-1}。
可选的，当i∈{2,3,...,m-3}时，第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
当i＝m-2时，第m-2个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000057
所述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
当i＝m-1时，第m-1个待编码子块中的信息比特数量为
Figure PCTCN2022110969-appb-000058
可选的，编码数据是采用编码矩阵G进行编码得到的，编码矩阵
Figure PCTCN2022110969-appb-000059
G为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
可选的，处理单元902用于对编码数据进行译码，得到译码数据，具体可以包括：
获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子块为第m-1个编码子块，第1个接收子块为第0个编码子块；
将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第1个接收子块对应的标记数据，
对F运算后的第1个接收子块对应的标记数据进行Polar码译码，得到第1个接收子块对应的译码数据；
根据所述第1个接收子块对应的标记数据和所述第1个接收子块对应的译码数据对所述第0个接收子块对应的标记数据进行增强。
可选的，处理单元902还用于：
获取第q个接收子块对应的标记数据，所述q为2≤q≤m-1，第q个接收子块为第q-1个编码子块；
将所述第q个接收子块对应的标记数据与增强后的第0个接收子块对应的标记数据进行F运算，得到F运算后的第q个接收子块对应的标记数据；
对F运算后的第q个接收子块对应的标记数据进行Polar码译码，得到第q个接收子块对应的译码数据；
根据所述第q个接收子块对应的标记数据和所述第q个接收子块对应的译码数据对所述增强后的第0个接收子块对应的标记数据进行增强。
可选的，编码数据是采用编码矩阵G′进行编码得到的，编码矩阵
Figure PCTCN2022110969-appb-000060
G′为大小为(m×2 n)×(m×2 n)的矩阵，m和n为正整数，矩阵G N′为大小为2 n×2 n的Polar生成矩阵，矩阵O为大小为2 n×2 n的全零矩阵。
可选的，处理单元902用于对编码数据进行译码，得到译码数据，具体可以包括：
获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，第0个接收子块为第0个编码子块，第1个接收子块为第1个编码子块；
将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第0个接收子块对应的标记数据，
对F运算后的第0个接收子块对应的标记数据进行Polar码译码，得到第0个接收子块 对应的译码数据；
根据所述第0个接收子块对应的标记数据和所述第0个接收子块对应的译码数据对所述第1个接收子块对应的标记数据进行增强。
可选的，处理单元902还用于：
获取第p个接收子块对应的标记数据，p为2≤p≤m-1，第p个接收子块为第p个编码子块；
将第p个接收子块对应的标记数据与增强后的第p-1个接收子块对应的标记数据进行F运算，得到F运算后的第p-1个接收子块对应的标记数据；
对F运算后的第p-1个接收子块对应的标记数据进行Polar码译码，得到第p-1个接收子块对应的译码数据；
根据增强后的第p-1个接收子块对应的标记数据和所述第p-1个接收子块对应的译码数据对第p个接收子块对应的标记数据进行增强。
该实施方式中通信单元901和处理单元902的具体执行流程还可以参考图3至图7对应的方法实施例中的描述，此处不再赘述。该通信装置所实现的数据处理方法中设计的编码数据包括多个编码块，并且多个编码块中的信息比特数量的按照一定的规律设计的，则可以针对该编码数据实现流译码。
下面对包括图9所示的多个功能单元的设备进行描述。本申请所述的设备包括图9所示的多个功能单元。图10为本申请提供的一种通信设备的示意图，用于实现上述方法实施例中的数据处理方法。该通信设备1000也可以是芯片系统。可以理解的是，该通信设备1000例如可以是终端设备，也可以是网络设备。
其中，通信设备1000包括通信接口1001和处理器1002。通信接口1001例如可以是收发器、接口、总线、电路或者能够实现收发功能的装置。其中，通信接口1001用于通过传输介质和其它设备进行通信，从而用于设备1000可以和其它设备进行通信。处理器1002用于执行处理相关的操作。
一种可能的实施方式中，通信接口1001用于获取K个信息比特，处理器1002用于根据所述K，确定待编码块的长度，根据待编码块的长度和分配序列，确定待编码块中每个待编码子块的信息比特数量。其中，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。处理器1002用于对待编码块进行编码，得到编码数据，通信接口1001用于发送编码数据。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第一方面以及图3至图7对应的方法实施例中的描述，或者参考图9中的通信单元901和处理单元902中的描述，此处不再赘述。该通信设备所实现的数据处理方法设计了一种基于分配序列的信息比特构造和编码方法，该信息比特构造方法简单有效，有利于提高系统性能，降低系统功耗。并且，该方法可以支持编码子块的长度不足2 n的整数倍时的信息比特构造和速率匹配。
另一种可能的实施方式中，通信接口1001用于接收编码数据，处理器1002用于对编码数据进行译码，得到译码数据。其中，编码数据是由待编码块进行编码得到的，待编码块包括多个待编码子块，待编码块中每个待编码子块的信息比特数量是根据待编码块的长度和分配序列确定的，分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量。
该实施方式中通信接口1001和处理器1002的具体执行流程还可以参考第二方面以及图3至图7对应的方法实施例中的描述，或者参考图9中的通信单元901和处理单元902中的 描述，此处不再赘述。该通信设备所实现的数据处理方法中的编码数据包括多个编码块，并且多个编码块中的信息比特数量的按照一定的规律设计的，则可以针对该编码数据实现流译码。
可选的，该通信设备1000还可以包括至少一个存储器1003，用于存储程序指令和/或数据。一种实施方式中，存储器和处理器耦合。本申请中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器可能和存储器协同操作。处理器可能执行存储器中存储的程序指令。所述至少一个存储器和处理器集成在一起。
本申请中不限定上述通信接口、处理器以及存储器之间的具体连接介质。例如，存储器、处理器以及通信接口之间通过总线连接，总线1004在图10中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
在本申请中，存储器可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。本申请中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
本申请提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如图3至图7对应的实施例中的方法对数据进行处理，获取处理后的数据。
本申请提供一种通信装置，该通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如图3至图7对应的实施例中的方法对数据进行处理，获取处理后的数据。
本申请提供一种通信系统，该通信系统包括如图3至图7对应的实施例中的终端设备和网络设备。
本申请提供一种计算机可读存储介质。该计算机可读存储介质存储有程序或指令。当所述程序或指令在计算机上运行时，使得计算机执行如图3至图7对应的实施例中的数据处理方法。
本申请中提供一种计算机程序产品。该计算机程序产品包括指令。当所述指令在计算机上运行时，使得计算机执行如图3至图7对应的实施例中的数据处理方法。
本申请提供一种芯片或者芯片系统，该芯片或者芯片系统包括至少一个处理器和接口，接口和至少一个处理器通过线路互联，至少一个处理器用于运行计算机程序或指令，以执行如图3至图7对应的实施例中的数据处理方法。
其中，芯片中的接口可以为输入/输出接口、管脚或电路等。
上述芯片系统可以是片上系统(system on chip，SOC)，也可以是基带芯片等，其中基带 芯片可以包括处理器、信道编码器、数字信号处理器、调制解调器和接口模块等。
在一种实现方式中，本申请中上述描述的芯片或者芯片系统还包括至少一个存储器，该至少一个存储器中存储有指令。该存储器可以为芯片内部的存储单元，例如，寄存器、缓存等，也可以是该芯片的存储单元(例如，只读存储器、随机存取存储器等)。
本申请提供的技术方案可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、终端设备或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机可以存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，数字视频光盘(digital video disc，DVD))、或者半导体介质等。
在本申请中，在无逻辑矛盾的前提下，各实施例之间可以相互引用，例如方法实施例之间的方法和/或术语可以相互引用，例如装置实施例之间的功能和/或术语可以相互引用，例如装置实施例和方法实施例之间的功能和/或术语可以相互引用。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (30)

  1. 一种数据处理方法，其特征在于，包括：
    获取K个信息比特；
    根据所述K，确定待编码块的长度；
    根据所述待编码块的长度和分配序列，确定所述待编码块中每个待编码子块的信息比特数量，
    所述分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量；
    对所述待编码块进行编码，得到编码数据；
    发送所述编码数据。
  2. 根据权利要求1所述的方法，其特征在于，
    所述待编码块的长度为E＝K/R，所述R为码率；
    所述待编码块包括m个待编码子块，所述
    Figure PCTCN2022110969-appb-100001
    所述编码数据包括编码块，所述编码块包括m个编码子块，所述编码子块大小为N′，所述N′＝2 n；
    所述分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；
    所述分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
  3. 根据权利要求1或2所述的方法，其特征在于，每个待编码子块的长度为：
    E 0＝E-(m-1)×N′，或者，
    E i＝N′，所述i∈{1,2,...,m-2,m-1}。
  4. 根据权利要求3所述的方法，其特征在于，根据所述待编码块的长度和分配序列，确定所述待编码块中每个待编码子块的信息比特数量，包括：
    当i＝0时，确定第0个待编码子块的信息比特数量为
    Figure PCTCN2022110969-appb-100002
    所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
    当i＝1时，确定第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
    当i∈{2,3,...,m-2}时，确定第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
    当i＝m-1时，确定第m-1个待编码子块的信息比特数量为
    Figure PCTCN2022110969-appb-100003
  5. 根据权利要求1或2所述的方法，其特征在于，每个待编码子块的长度为：
    E m-2＝E-(m-1)×N′，或者，
    E i＝N′，所述i∈{0,1,2,...,m-3,m-1}。
  6. 根据权利要求5所述的方法，其特征在于，根据所述待编码块的长度和分配序列，确定所述待编码块中每个待编码子块的信息比特数量，包括：
    当i∈{2,3,...,m-3}时，确定第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
    当i＝m-2时，确定第m-2个待编码子块中的信息比特数量为
    Figure PCTCN2022110969-appb-100004
    所 述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
    当i＝m-1时，确定第m-1个待编码子块中的信息比特数量为
    Figure PCTCN2022110969-appb-100005
  7. 根据权利要求1至6任意一项所述的方法，其特征在于，所述对所述待编码块进行编码，得到编码数据，包括：
    根据每个待编码子块的信息比特数据，将所述K个信息比特分成m个子段；
    确定每个编码子块的信息位和冻结位，并根据编码子块的数量m构造大小为m×2 n的信息序列；
    根据所述信息序列中信息比特的位置，将所述K个信息比特插入到待编码序列中，并将待编码序列与编码矩阵进行模二乘处理，得到编码数据。
  8. 根据权利要求7所述的方法，其特征在于，所述编码矩阵为
    Figure PCTCN2022110969-appb-100006
    所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  9. 根据权利要求8所述的方法，其特征在于，所述发送所述编码数据，包括：
    发送第m-1个待编码子块，
    再依次发送第i个编码子块，所述i满足0≤i≤m-2。
  10. 根据权利要求7所述的方法，其特征在于，所述编码矩阵为
    Figure PCTCN2022110969-appb-100007
    所述G′为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  11. 根据权利要求10所述的方法，其特征在于，所述发送所述编码数据，包括：
    依次发送第i个编码子块，所述i满足0≤i≤m-1。
  12. 一种数据处理方法，其特征在于，包括：
    接收编码数据，所述编码数据是由待编码块进行编码得到的，
    所述待编码块包括多个待编码子块，所述待编码块中每个待编码子块的信息比特数量是根据所述待编码块的长度和分配序列确定的，
    所述分配序列用于描述在相同的码率和待编码子块大小的情况下，待编码块中除最后一个待编码子块之外的所有待编码子块中的信息比特数量；
    对所述编码数据进行译码，得到译码数据。
  13. 根据权利要求12所述的方法，其特征在于，
    所述待编码块的长度为E＝K/R，所述R为码率；
    所述待编码块包括m个待编码子块，所述
    Figure PCTCN2022110969-appb-100008
    所述编码数据包括编码块，所述编码块包括m个编码子块，所述编码子块大小为N′，所述N′＝2 n；
    所述分配序列包括S-1个变量{A 0,A 1,A 2,...,A S-2}；
    所述分配序列中的元素之间的关系为A 0≤A 1≤...≤A S-2。
  14. 根据权利要求12或13所述的方法，其特征在于，每个待编码子块的长度为：
    E 0＝E-(m-1)×N′，或者，
    E i＝N′，所述i∈{1,2,...,m-2,m-1}。
  15. 根据权利要求14所述的方法，其特征在于，
    当i＝0时，第0个待编码子块的信息比特数量为
    Figure PCTCN2022110969-appb-100009
    所述A 0为所述分配序列中的第0个元素，所述Δ 0是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
    当i＝1时，第1个待编码子块的信息比特数量为J 1＝A 1-Δ 1，所述A 1为所述分配序列中的第1个元素，所述Δ 1是根据所述E 0和所述N′的差值确定的，取值为0或1；或者，
    当i∈{2,3,...,m-2}时，第i个待编码子块的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
    当i＝m-1时，第m-1个待编码子块的信息比特数量为
    Figure PCTCN2022110969-appb-100010
  16. 根据权利要求12或13所述的方法，其特征在于，每个待编码子块的长度为：
    E m-2＝E-(m-1)×N′，或者，
    E i＝N′，所述i∈{0,1,2,...,m-3,m-1}。
  17. 根据权利要求16所述的方法，其特征在于，
    当i∈{2,3,...,m-3}时，第i个待编码子块中的信息比特数量为J i＝A i，所述A i为所述分配序列中的第i个元素；或者，
    当i＝m-2时，第m-2个待编码子块中的信息比特数量为
    Figure PCTCN2022110969-appb-100011
    所述A m-2为所述分配序列中的第m-2个元素，所述Δ 2是根据所述E m-2和所述N′的差值确定的，取值为0或1；或者，
    当i＝m-1时，第m-1个待编码子块中的信息比特数量为
    Figure PCTCN2022110969-appb-100012
  18. 根据权利要求12至17任一项所述的方法，其特征在于，所述编码数据是采用编码矩阵G进行编码得到的，所述编码矩阵
    Figure PCTCN2022110969-appb-100013
    所述G为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  19. 根据权利要求18所述的方法，其特征在于，所述对所述编码数据进行译码，得到译码数据，包括：
    获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，所述第0个接 收子块为第m-1个编码子块，所述第1个接收子块为第0个编码子块；
    将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第1个接收子块对应的标记数据，
    对F运算后的第1个接收子块对应的标记数据进行Polar码译码，得到第1个接收子块对应的译码数据；
    根据所述第1个接收子块对应的标记数据和所述第1个接收子块对应的译码数据对所述第0个接收子块对应的标记数据进行增强。
  20. 根据权利要求19所述的方法，其特征在于，所述方法还包括：
    获取第q个接收子块对应的标记数据，所述q为2≤q≤m-1，所述第q个接收子块为第q-1个编码子块；
    将所述第q个接收子块对应的标记数据与增强后的第0个接收子块对应的标记数据进行F运算，得到F运算后的第q个接收子块对应的标记数据；
    对F运算后的第q个接收子块对应的标记数据进行Polar码译码，得到第q个接收子块对应的译码数据；
    根据所述第q个接收子块对应的标记数据和所述第q个接收子块对应的译码数据对所述增强后的第0个接收子块对应的标记数据进行增强。
  21. 根据权利要求12至15任一项所述的方法，其特征在于，所述编码数据是采用编码矩阵G′进行编码得到的，所述编码矩阵
    Figure PCTCN2022110969-appb-100014
    所述G′为大小为(m×2 n)×(m×2 n)的矩阵，所述m和所述n为正整数，
    所述矩阵G N′为大小为2 n×2 n的Polar生成矩阵，
    所述矩阵O为大小为2 n×2 n的全零矩阵。
  22. 根据权利要求21所述的方法，其特征在于，所述对所述编码数据进行译码，得到译码数据，包括：
    获取第0个接收子块对应的标记数据和第1个接收子块对应的标记数据，所述第0个接收子块为第0个编码子块，所述第1个接收子块为第1个编码子块；
    将所述第0个接收子块对应的标记数据和所述第1个接收子块对应的标记数据进行F运算，得到F运算后的第0个接收子块对应的标记数据，
    对F运算后的第0个接收子块对应的标记数据进行Polar码译码，得到第0个接收子块对应的译码数据；
    根据所述第0个接收子块对应的标记数据和所述第0个接收子块对应的译码数据对所述第1个接收子块对应的标记数据进行增强。
  23. 根据权利要求22所述的方法，其特征在于，所述方法还包括：
    获取第p个接收子块对应的标记数据，所述p为2≤p≤m-1，所述第p个接收子块为第p个编码子块；
    将所述第p个接收子块对应的标记数据与增强后的第p-1个接收子块对应的标记数据进行F运算，得到F运算后的第p-1个接收子块对应的标记数据；
    对F运算后的第p-1个接收子块对应的标记数据进行Polar码译码，得到第p-1个接收子块对应的译码数据；
    根据所述增强后的第p-1个接收子块对应的标记数据和所述第p-1个接收子块对应的译码数据对所述第p个接收子块对应的标记数据进行增强。
  24. 一种数据处理装置，其特征在于，包括用于执行如权利要求1至11或者12至23中任一项所述的方法所采用的单元或模块。
  25. 一种通信设备，其特征在于，包括：存储器和处理器；
    所述存储器，用于存储指令；
    所述处理器，用于执行所述指令，使得如权利要求1至11或者12至23中任一项所述的方法被执行。
  26. 一种通信系统，其特征在于，包括：
    发送端，用于执行如权利要求1至11中任一项所述的方法；
    接收端，用于执行如权利要求12至23中任一项所述的方法。
  27. 一种芯片，其特征在于，包括处理器和接口；
    所述处理器用于读取指令以执行权利要求1至11或者12至23中任一项所述的方法。
  28. 一种通信装置，其特征在于，所述通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如权利要求1至11中任一项所述的方法对数据进行处理，获取处理后的数据。
  29. 一种通信装置，其特征在于，所述通信装置由输入输出接口和逻辑电路组成，所述输入输出接口用于输入或输出数据；所述逻辑电路按照如权利要求12至23中任一项所述的方法对数据进行处理，获取处理后的数据。
  30. 一种计算机可读存储介质，其特征在于，包括程序或指令，当所述程序或指令在计算机上运行时，如权利要求1至11或者12至23任一项所述的方法被执行。
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