WO2024029834A1

WO2024029834A1 - Flat coil

Info

Publication number: WO2024029834A1
Application number: PCT/KR2023/010901
Authority: WO
Inventors: 최현준; 변강일; 김광록; 정시훈; 강계룡; 한진욱; 응우옌 티두옌
Original assignee: 엘지전자 주식회사; 울산과학기술원
Priority date: 2022-08-01
Filing date: 2023-07-27
Publication date: 2024-02-08
Also published as: KR20240017685A

Abstract

A flat coil, according to one embodiment, may comprise: a substrate; and a conductor layer disposed on a first surface of the substrate and a second surface of the substrate. In one embodiment, the conductor layer may include multiple conductor tracks. In one embodiment, each of the conductor tracks may include a first outermost conductor pair, a middle conductor pair, and a second outermost conductor pair. In one embodiment, the conductor tracks may include a first parallel section and a second parallel section. In one embodiment, a second outermost conductor pair of the first parallel section may be connected to a first outermost conductor pair of the second parallel section. In one embodiment, a first outermost conductor pair of the first parallel section may be connected to a middle conductor pair of the second parallel section. In one embodiment, a middle conductor pair of the first parallel section may be connected to the middle conductor pair or a second outermost conductor pair of the second parallel section.

Description

flat coil

This specification relates to a planar coil.

A coil is a passive element made by winding a conductor through which current can flow several times. For example, a core coil is a coil made by wrapping a conductor several times around a core in the shape of a bar, cylinder, or cylinder. As another example, an air core coil is a coil made by winding a conductor several times in a cylindrical or circular shape, and there is no core at the center of the air core coil.

When alternating current is supplied to the coil, a magnetic field is formed around the coil, and the magnetic field generates eddy currents in the load placed around the coil. This phenomenon is referred to as electromagnetic induction. Electromagnetic induction can be applied to inductive heating to heat a load placed around a coil or to wireless power transmission to transmit power to a load placed around a coil.

Flat coils are mainly used in induction heating devices or wireless power transmission devices. A flat coil is a type of air core coil and is made by winding a conductor several times in a spiral shape in one dimension. Therefore, a planar coil may also be referred to as a helical coil.

In a planar coil, several conductors are arranged parallel to each other. When alternating current flows through the conductors of a flat coil, skin effect and proximity effect occur. When high-frequency alternating current flows through conductors arranged in parallel, the current density on the outside of the conductors tends to increase compared to the inside. This phenomenon is called the skin effect. Additionally, when current flows through conductors arranged in parallel to each other, the density distribution of the current flowing across the cross section of each conductor changes depending on the size, direction, and frequency of the current flowing through each conductor. This phenomenon is called the proximity effect.

As the frequency of the alternating current flowing through the planar coil increases, the skin effect and proximity effect increase. As the skin effect and proximity effect increase, the resistance of the conductors forming the planar coil increases. As the resistance of the conductor increases, the strength of the magnetic field formed around the planar coil decreases when alternating current is supplied to the planar coil, and the magnetic flux density decreases. As a result, the performance of devices that utilize the electromagnetic induction phenomenon caused by a planar coil may be deteriorated.

The purpose of the present specification is to provide a flat coil that can reduce the resistance of the conductor due to the skin effect and proximity effect when a high-frequency alternating current flows through the conductor.

The purpose of the present specification is to provide a flat coil that can improve the performance of devices using electromagnetic induction phenomenon by increasing the strength of the magnetic field formed around the conductor and increasing the magnetic flux density.

The purpose of the present specification is not limited to the purposes mentioned above, and other purposes and advantages of the present specification that are not mentioned will be more clearly understood by the examples of the present specification described below. Additionally, the objects and advantages of the present specification can be realized by the components and combinations thereof described in the claims.

A planar coil according to an embodiment may include a substrate and a conductor layer disposed on a first side of the substrate and a second side of the substrate.

In one embodiment, the conductor layer may include multiple conductor tracks.

In one embodiment, each conductor track may include a first outermost conductor pair, a middle conductor pair, and a second outermost conductor pair.

In one embodiment, the conductor track may include a first parallel section and a second parallel section.

In one embodiment, the second outermost conductor pair of the first parallel section may be connected to the first outermost conductor pair of the second parallel section.

In one embodiment, the first outermost conductor pair of the first parallel section may be connected to a middle conductor pair of the second parallel section.

In one embodiment, the middle conductor pair of the first parallel section may be connected to the middle conductor pair or the second outermost conductor pair of the second parallel section.

In one embodiment, the conductor track may further include a cross section disposed between the first parallel section and the second parallel section.

In one embodiment, in the cross section, the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair of the first parallel section are each the first outermost conductor of the second parallel section. It may be connected to any one of a pair, the middle conductor pair, and the second outermost conductor pair.

In one embodiment, at least one via hole may be formed in the cross section.

In one embodiment, the first conductor lane disposed on the first side and the second conductor lane disposed on the second side may be electrically connected to each other by a connector passing through the via hole.

In one embodiment, the cross section may include a connecting lane connecting two via holes.

In one embodiment, in the cross section, a first conductor lane disposed on the first side and a second conductor lane disposed on the second side may be arranged to intersect each other.

In one embodiment, the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair are a first conductor lane disposed on the first side and a second conductor lane disposed on the second side, respectively. may include.

In one embodiment, the first parallel section or the second parallel section may include at least one cross area.

In one embodiment, the first conductor lane and the second conductor lane may be arranged to intersect each other in the cross area.

According to embodiments, when a high-frequency alternating current flows through the conductor of a planar coil, the resistance of the conductor due to the skin effect and proximity effect is lowered. As a result, the strength of the magnetic field formed around the conductor of the planar coil increases and the magnetic flux density increases. Therefore, the performance of devices that utilize the electromagnetic induction phenomenon caused by a planar coil can be improved.

1 is a perspective view of a planar coil according to one embodiment.

Figure 2 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track as viewed from the first side of the substrate.

Figure 3 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track as viewed from the second side of the substrate.

Figure 4 shows a first parallel section, a cross section and a second parallel section viewed from the first side of the substrate, assuming the substrate is transparent.

Figure 5 is a graph showing the magnitude of each resistance measured when alternating currents of different frequencies are applied to planar coils according to the prior art and a planar coil according to an embodiment of the present specification.

The above-mentioned objectives, features and advantages will be described in detail later with reference to the attached drawings, and thus, those skilled in the art will be able to easily implement the embodiments of the present specification. In describing the present specification, if it is determined that a detailed description of known technologies related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the attached drawings. In the drawings, identical reference numerals indicate identical or similar components.

1 is a perspective view of a planar coil according to one embodiment. Additionally, Figure 2 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track viewed from the first side of the substrate, and Figure 3 illustrates a first parallel section, a cross section, and a second parallel section included in an arbitrary track viewed from the second side of the substrate. It represents a first parallel section, a cross section, and a second parallel section. Figure 4 also shows a first parallel section, a cross section, and a second parallel section viewed from the first side of the substrate, assuming the substrate is transparent.

In one embodiment, the planar coil 1 includes a substrate 10 and a conductor layer 20 disposed on the first side 11 and the second side 12 of the substrate 10 . The conductor layer 20 may include a first conductor layer disposed on the first side 11 and a second conductor layer disposed on the second side 12 .

The substrate 10 may be a flat substrate having a first surface 11 and a second surface 12 . Examples of the substrate 10 include a printed circuit board made of a rigid insulating material such as epoxy resin or phenol resin, or a flexible printed circuit board made of a soft insulating material such as polyimide. However, the type of substrate 10 is not limited to this.

Electrical components may be attached, fixed, or mounted on the substrate 10. In one embodiment, a conductor layer 20 made of a conductive material (e.g., metal) is attached, fixed, or mounted on at least one surface of the first surface 11 and the second surface 12 of the substrate 10. It can be.

The conductor layer 20 is a conductor wound with a predetermined number of turns based on the center point C. Although FIG. 1 shows an embodiment in which the shape of the conductor layer 20 is circular, the conductor layer 20 may have a different shape (eg, oval or square) depending on the embodiment.

In one embodiment, conductor layer 20 may include multiple conductor tracks. For example, in FIG. 1, the conductor layer 20 includes a first conductor track (T1), a second conductor track (T2), a third conductor track (T3), a fourth conductor track (T4), and a fifth conductor track (T5). Includes. The number of conductor tracks included in the conductor layer 20 may be equal to the number of turns of the conductor layer 20. For example, in the embodiment of FIG. 1, the number of turns of the conductor layer 20 is 5, so the conductor layer 20 includes five conductor tracks T1 to T5. The number of conductor tracks included in the conductor layer 20 may vary depending on the embodiment.

In one embodiment, each conductor track T1 to T5 may include multiple conductor pairs. For example, as shown in Figure 4, any conductor track may include multiple conductor pairs (CP1-1, CP1-2. CP1-3 or CP2-1, CP2-2, CP2-3). .

Additionally, each conductor pair may include a first conductor lane disposed on the first side 11 of the substrate 10 and a second conductor lane disposed on the second side 12 of the substrate 10. For example, as shown in FIG. 4, the first conductor pair CP1-1 included in the first parallel section PS1 is a first conductor lane disposed on the first surface 11 of the substrate 10. LT1-1) and a second conductor lane LB1-1 disposed on the second surface 12 of the substrate 10. Likewise, other conductor pairs (CP1-2, CP1-3 or CP2-1, CP2-2, CP2-3) are connected to the first conductor lanes (LT1-2, LT1-3, LT1-3, LT2-1) and second conductor lanes LB1-2, LB1-3, LB2-1, and LB2-2 disposed on the second surface 12 of the substrate 10.

In one embodiment, the conductor layer 20 may include multiple parallel sections (PS) and multiple cross sections (CS). Each parallel section (PS) and each cross section (CS) may be arranged alternately. Therefore, one cross section (CS) can be placed between two parallel sections (PS).

Each conductor pair included in the parallel section PS may be arranged parallel to each other. Among each conductor pair included in the cross section CS, at least one conductor pair may be arranged to intersect with another conductor pair.

The conductor lane included in each conductor pair included in the two parallel sections (PS) is connected to the conductor lane included in each conductor pair included in the cross section (CS) disposed between the two parallel sections (PS). can be connected

A first connection terminal 21 and a second connection terminal 22 may be connected to one end of an arbitrary conductor track included in the conductor layer 20, respectively. For example, the first connection terminal 21 may be connected to one end of the first conductor track T1, and the second connection terminal 22 may be connected to one end of the fifth conductor track T5. A connection terminal (eg, a positive terminal and a negative terminal) electrically connected to the power supply device may be connected to the first connection terminal 21 and the second connection terminal 22, respectively. When the connection terminal electrically connected to the power supply device is respectively connected to the first connection terminal 21 and the second connection terminal 22, current may be supplied from the power supply device to the conductor layer 20.

Below, the structure of the conductor layer 20 according to one embodiment is described in more detail with reference to FIGS. 2 to 4.

2 to 4 show two parallel sections included in the conductor layer 20 shown in FIG. 1, that is, a first parallel section (PS1) and a second parallel section (PS2), a first parallel section (PS1), and A cross section CS disposed between the second parallel sections PS2 is shown. Although not shown, another cross section may be disposed on one side of the first parallel section PS1 or on one side of the second parallel section PS2.

Each parallel section may include multiple conductor pairs. More specifically, each parallel section may include a first outermost conductor pair, a second outermost conductor pair, and one or more intermediate conductor pairs. For example, the first parallel section (PS1) includes a first outermost conductor pair (CP1-1), a middle conductor pair (CP1-2), a second outermost conductor pair (CP1-3), and a second parallel section (CP1-1). Section PS2 includes a first outermost conductor pair (CP2-1), a middle conductor pair (CP2-2), and a second outermost conductor pair (CP2-3).

The first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair of each parallel section are the first conductor lane disposed on the first side 11 of the substrate 10 and the second outermost conductor pair of the substrate 10, respectively. It may include a second conductor lane disposed in face 12. For example, the first outermost conductor pair (CP1-1) of the first parallel section (PS1) is connected to the first conductor lane (LT1-1) disposed on the first side 11 of the substrate 10 and the substrate 10. ) includes a second conductor lane (LB1-1) disposed on the second side 12 of the plane. As another example, the second outermost conductor pair (CP2-3) of the second parallel section (PS2) is connected to the first conductor lane (LT1-2) disposed on the first surface 11 of the substrate 10 and the substrate 10. ) includes a second conductor lane (LB2-2) disposed on the second side 12 of the plane.

2 to 4, each parallel section includes one middle conductor pair (CP1-2, CP2-2). However, in other embodiments, each parallel section may include two or more intermediate conductor pairs.

In one embodiment, the second outermost conductor pair of the first parallel section may be connected to the first outermost conductor pair of the second parallel section. For example, in the embodiment of FIGS. 2 to 4, the second outermost conductor pair CP1-3 of the first parallel section PS1 is the first outermost conductor pair CP2-1 of the second parallel section PS2. is connected to

In one embodiment, the first outermost conductor pair of the first parallel section may be connected to the middle conductor pair of the second parallel section. For example, in the embodiment of FIGS. 2 to 4, the first outermost conductor pair CP1-1 of the first parallel section PS1 is connected to the middle conductor pair CP2-2 of the second parallel section PS2. .

In one embodiment, the middle conductor pair of the first parallel section may be connected to the middle conductor pair of the second parallel section or the second outermost conductor pair. For example, in the embodiment of FIGS. 2 to 4, the middle conductor pair CP1-2 of the first parallel section PS1 is connected to the second outermost conductor pair CP2-3 of the second parallel section PS2. . If an additional intermediate conductor pair is disposed between the first outermost conductor pair (CP1-1) and the intermediate conductor pair (CP1-2) of the first parallel section (PS1), the additional intermediate conductor pair of the first parallel section (PS1) The pair may be connected to an additional middle conductor pair disposed between the middle conductor pair CP2-2 and the second outermost conductor pair CP2-3 of the second parallel section PS2.

In the cross section (CS) disposed between the first parallel section (PS1) and the second parallel section (PS2), the first outermost conductor pair (CP1-1) and the middle conductor pair of the first parallel section (PS1) (CP1-2) and the second outermost conductor pair (CP1-3) are the first outermost conductor pair (CP2-1), the middle conductor pair (CP2-2) and the second outermost conductor pair (CP2-1) of the second parallel section (PS2), respectively. It can be connected to any one of the outermost conductor pairs (CP2-3). For example, in the cross section (CS), the second outermost conductor pair (CP1-3) of the first parallel section (PS1) is connected to the first outermost conductor pair (CP2-1) of the second parallel section (PS2), The first outermost conductor pair (CP1-1) of the first parallel section (PS1) is connected to the middle conductor pair (CP2-2) of the second parallel section (PS2), and the middle conductor of the first parallel section (PS1) The pair (CP1-2) is connected to the second outermost conductor pair (CP2-3) of the second parallel section (PS2).

In one embodiment, at least one via hole may be formed in each cross section. For example, in the embodiments of FIGS. 2 to 4 , six via holes V1 to V6 are formed in the cross section CS.

Additionally, each cross section may include a connecting lane connecting two via holes. For example, in the embodiment of FIGS. 2 to 4, the cross section CS connects the first via hole V1 and the fourth via hole V4 and is disposed on the first surface 11 of the substrate 10. A first connecting lane (LTC1) connected to the second via hole (V2) and the sixth via hole (V6) and a second connecting lane (LTC2) disposed on the first surface 11 of the substrate 10. Includes. Additionally, the cross section CS connects the third via hole V3 and the fourth via hole V4 and includes a connecting lane (LBC) disposed on the second surface 12 of the substrate 10.

The number of via holes formed in the cross section CS or the number of connecting lanes included in the cross section CS may vary depending on the embodiment.

In the cross section CS, the first conductor lanes disposed on the first side 11 of the substrate 10 are connected to the second side 12 of the substrate 10 by connectors passing through via holes V1 to V6. It may be electrically connected to the conductor lanes arranged in . For example, in the embodiment of FIGS. 2 to 4, the second conductor lane LB1-1 disposed on the first parallel section PS1 and the second surface 12 of the substrate 10 has a first via hole ( It may be electrically connected to the first connecting lane (LTC1) disposed on the first surface 11 of the substrate 10 through a connector passing through the interior of V1). In addition, the first connecting lane (LTC1) disposed on the first side 11 of the substrate 10 is connected to the second side 12 of the substrate 10 through a connector passing through the inside of the fourth via hole V4. It may be electrically connected to the disposed second conductor lane LB2-1. The connector may be made from a conductive material (eg, metal).

In the cross section CS, the first conductor lane disposed on the first side 11 of the substrate 10 and the second conductor lane disposed on the second side 12 of the substrate 10 are arranged to intersect each other. You can. For example, in the cross section CS shown in FIG. 4, first conductor lanes LT1-1, LT1-2 and connecting lanes LTC1, LTC2 are disposed on the first side 11 of the substrate 10. is arranged to intersect with the third conductor lanes LB1-3 and the connecting lanes LBC disposed on the second surface 12 of the substrate 10.

In one embodiment, each parallel section may include at least one cross region. For example, in the embodiment of FIGS. 2 to 4, the first parallel section PS1 includes a first cross area CA1-1 and a second cross area CA1-2, and the second parallel section PS2 ) includes a first cross area (CA2-1) and a second cross area (CA2-2). Depending on the embodiment, the number of cross areas included in each parallel section may vary.

In each cross region, the first conductor lane disposed on the first side 11 of the substrate 10 and the second conductor lane disposed on the second side 12 of the substrate 10 may be arranged to cross each other. there is.

For example, in the embodiment of FIGS. 2 to 4, the first surface of the substrate 10 in the first cross area CA1-1 and the second cross area CA1-2 of the first parallel section PS1 ( The first conductor lanes (LT1-1, LT1-2, LT1-3) disposed on 11) and the second conductor lanes (LB1-1, LB1-2, LB1-3) are arranged to intersect each other. In addition, the first conductor lane (LT2-) disposed on the first surface 11 of the substrate 10 in the first cross area (CA2-1) and the second cross area (CA2-2) of the second parallel section (PS2) 1, LT1-1, and LT1-2 and the second conductor lanes LB1-3, LB2-1, and LB2-2 disposed on the second surface 12 of the substrate 10 are arranged to intersect each other.

According to the above-described embodiment, the first conductor lanes disposed on the first side 11 of the substrate 10 and the second conductor lanes disposed on the second side 12 of the substrate 10 are arranged to intersect each other. . For example, the first conductor lanes disposed on the first surface 11 and the substrate 10 in the cross area (e.g., CA1-1, CA1-2, CA2-1, CA2-2) included in each parallel section. The second conductor lanes arranged on the second side 12 are arranged to cross each other. In addition, in the cross section CS disposed between each parallel section, the first conductor lanes disposed on the first side 11 and the second conductor lanes disposed on the second side 12 of the substrate 10 are connected to each other. arranged to intersect.

In addition, according to the above-described embodiment, the first conductor lanes disposed on the first surface 11 of the substrate 10 in the cross section CS disposed between each parallel section pass through the via holes V1 to V6. The conductor lanes disposed on the second surface 12 of the substrate 10 may be electrically connected to each other by a connector.

According to the above-described embodiment, each conductor lane included in the conductor layer 20 is arranged to cross each other in a direction parallel to the substrate 10 or in a direction penetrating the substrate 10. Therefore, the conductor layer 20 of the planar coil 1 according to one embodiment has a structure similar to a Litz wire. As a result, the phenomenon of lowering the resistance of the conductor due to the skin effect and proximity effect of the planar coil 1 can be improved.

In FIG. 5, SS refers to a planar coil having a structure in which each conductor track included in the conductor layer disposed on the substrate includes only one conductor lane and is disposed on only one side of the substrate. In addition, in FIG. 5, MS refers to a planar coil having a structure in which each conductor track included in a conductor layer disposed on a substrate is arranged in parallel with each other and includes a plurality of conductor lanes disposed on only one side of the substrate. Additionally, in FIG. 5, LZ refers to a planar coil according to the embodiment described with reference to FIGS. 1 to 4.

In Figure 5, Rskin represents the size of the resistance of the conductor layer due to the skin effect that occurs when an alternating current is applied to the conductor layer of each planar coil. Also, in FIG. 5, Rproximity represents the size of the resistance of the conductor layer due to the proximity effect that occurs when an alternating current is applied to the conductor layer of each planar coil.

As shown in Figure 5, the size of resistance due to the skin effect of the planar coil (LZ) according to the embodiment described with reference to Figures 1 to 4 is the skin of the planar coil (SS) according to the prior art. It is close to the size of the resistance due to the effect or is smaller than the size of the resistance due to the skin effect of planar coils (MS) according to the prior art.

In addition, as shown in FIG. 5, the size of resistance due to the proximity effect of the planar coil (LZ) according to the embodiment described with reference to FIGS. 1 to 4 is similar to that of the planar coils (SS, MS) according to the prior art. ) is smaller than the size of the resistance due to the proximity effect. In particular, as the frequency of the alternating current applied to the conductor layer increases, the size of resistance due to the proximity effect of the planar coils (SS, MS) according to the prior art tends to increase.

In summary, as the frequency of the alternating current applied to the conductor layer increases, the size of resistance due to the skin effect and proximity effect of the planar coils (SS, MS) according to the prior art gradually increases, so the strength of the magnetic field decreases and the magnetic flux decreases. Density decreases. However, even if the frequency of the alternating current applied to the conductor layer increases, the amount of resistance due to the skin effect and proximity effect of the planar coil LZ according to the embodiment described with reference to FIGS. 1 to 4 hardly increases. Therefore, even if the frequency of the alternating current applied to the conductor layer increases, the planar coil (LZ) according to the embodiment described with reference to FIGS. 1 to 4 can guarantee higher performance compared to conventional planar coils. there is.

As described above, the present specification has been described with reference to the illustrative drawings, but the present specification is not limited to the embodiments and drawings disclosed herein, and various modifications may be made by those skilled in the art. In addition, even if the effects of the configuration of the present specification were not explicitly described and explained in the above description of the embodiments of the present specification, the predictable effects of the configuration should also be recognized.

Claims

Board; and

A conductor layer disposed on a first side of the substrate and a second side of the substrate,

The conductor layer includes a plurality of conductor tracks,

Each conductor track includes a first outermost conductor pair, a middle conductor pair, and a second outermost conductor pair,

The conductor track includes a first parallel section and a second parallel section,

The second outermost conductor pair of the first parallel section is connected to the first outermost conductor pair of the second parallel section,

The first outermost conductor pair of the first parallel section is connected to the middle conductor pair of the second parallel section,

The middle conductor pair of the first parallel section is connected to the middle conductor pair or the second outermost conductor pair of the second parallel section.

Flat coil.
According to paragraph 1,

The conductor track is

Further comprising a cross section disposed between the first parallel section and the second parallel section,

In the cross section, the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair of the first parallel section are the first outermost conductor pair and the middle conductor of the second parallel section, respectively. pair, connected to any one of the second outermost conductor pairs

Flat coil.
According to paragraph 2,

At least one via hole is formed in the cross section,

The first conductor lane disposed on the first side and the second conductor lane disposed on the second side are electrically connected to each other by a connector passing through the via hole.

Flat coil.
According to paragraph 3,

The cross section includes a connecting lane connecting two via holes.

Flat coil.
According to paragraph 2,

In the cross section, the first conductor lane disposed on the first side and the second conductor lane disposed on the second side are arranged to intersect each other.

Flat coil.
According to paragraph 1,

The first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair each include a first conductor lane disposed on the first side and a second conductor lane disposed on the second side.

Flat coil.
According to clause 6,

The first parallel section or the second parallel section includes at least one cross area,

The first conductor lane and the second conductor lane are arranged to intersect each other in the cross area.

Flat coil.