WO2024029834A1 - Bobine plate - Google Patents

Bobine plate Download PDF

Info

Publication number
WO2024029834A1
WO2024029834A1 PCT/KR2023/010901 KR2023010901W WO2024029834A1 WO 2024029834 A1 WO2024029834 A1 WO 2024029834A1 KR 2023010901 W KR2023010901 W KR 2023010901W WO 2024029834 A1 WO2024029834 A1 WO 2024029834A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
parallel section
section
pair
outermost
Prior art date
Application number
PCT/KR2023/010901
Other languages
English (en)
Korean (ko)
Inventor
최현준
변강일
김광록
정시훈
강계룡
한진욱
응우옌 티두옌
Original Assignee
엘지전자 주식회사
울산과학기술원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자 주식회사, 울산과학기술원 filed Critical 엘지전자 주식회사
Publication of WO2024029834A1 publication Critical patent/WO2024029834A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2804—Printed windings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/004—Printed inductances with the coil helically wound around an axis without a core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2804—Printed windings
    • H01F2027/2809—Printed windings on stacked layers

Definitions

  • This specification relates to a planar coil.
  • a coil is a passive element made by winding a conductor through which current can flow several times.
  • a core coil is a coil made by wrapping a conductor several times around a core in the shape of a bar, cylinder, or cylinder.
  • an air core coil is a coil made by winding a conductor several times in a cylindrical or circular shape, and there is no core at the center of the air core coil.
  • Electromagnetic induction can be applied to inductive heating to heat a load placed around a coil or to wireless power transmission to transmit power to a load placed around a coil.
  • Flat coils are mainly used in induction heating devices or wireless power transmission devices.
  • a flat coil is a type of air core coil and is made by winding a conductor several times in a spiral shape in one dimension. Therefore, a planar coil may also be referred to as a helical coil.
  • a planar coil In a planar coil, several conductors are arranged parallel to each other.
  • skin effect and proximity effect occur.
  • high-frequency alternating current flows through conductors arranged in parallel
  • the current density on the outside of the conductors tends to increase compared to the inside. This phenomenon is called the skin effect.
  • the proximity effect when current flows through conductors arranged in parallel to each other, the density distribution of the current flowing across the cross section of each conductor changes depending on the size, direction, and frequency of the current flowing through each conductor. This phenomenon is called the proximity effect.
  • the skin effect and proximity effect increase.
  • the resistance of the conductors forming the planar coil increases.
  • the strength of the magnetic field formed around the planar coil decreases when alternating current is supplied to the planar coil, and the magnetic flux density decreases. As a result, the performance of devices that utilize the electromagnetic induction phenomenon caused by a planar coil may be deteriorated.
  • the purpose of the present specification is to provide a flat coil that can reduce the resistance of the conductor due to the skin effect and proximity effect when a high-frequency alternating current flows through the conductor.
  • the purpose of the present specification is to provide a flat coil that can improve the performance of devices using electromagnetic induction phenomenon by increasing the strength of the magnetic field formed around the conductor and increasing the magnetic flux density.
  • a planar coil according to an embodiment may include a substrate and a conductor layer disposed on a first side of the substrate and a second side of the substrate.
  • the conductor layer may include multiple conductor tracks.
  • each conductor track may include a first outermost conductor pair, a middle conductor pair, and a second outermost conductor pair.
  • the conductor track may include a first parallel section and a second parallel section.
  • the second outermost conductor pair of the first parallel section may be connected to the first outermost conductor pair of the second parallel section.
  • the first outermost conductor pair of the first parallel section may be connected to a middle conductor pair of the second parallel section.
  • the middle conductor pair of the first parallel section may be connected to the middle conductor pair or the second outermost conductor pair of the second parallel section.
  • the conductor track may further include a cross section disposed between the first parallel section and the second parallel section.
  • the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair of the first parallel section are each the first outermost conductor of the second parallel section. It may be connected to any one of a pair, the middle conductor pair, and the second outermost conductor pair.
  • At least one via hole may be formed in the cross section.
  • the first conductor lane disposed on the first side and the second conductor lane disposed on the second side may be electrically connected to each other by a connector passing through the via hole.
  • the cross section may include a connecting lane connecting two via holes.
  • a first conductor lane disposed on the first side and a second conductor lane disposed on the second side may be arranged to intersect each other.
  • the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair are a first conductor lane disposed on the first side and a second conductor lane disposed on the second side, respectively. may include.
  • the first parallel section or the second parallel section may include at least one cross area.
  • first conductor lane and the second conductor lane may be arranged to intersect each other in the cross area.
  • the resistance of the conductor due to the skin effect and proximity effect is lowered.
  • the strength of the magnetic field formed around the conductor of the planar coil increases and the magnetic flux density increases. Therefore, the performance of devices that utilize the electromagnetic induction phenomenon caused by a planar coil can be improved.
  • FIG. 1 is a perspective view of a planar coil according to one embodiment.
  • Figure 2 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track as viewed from the first side of the substrate.
  • Figure 3 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track as viewed from the second side of the substrate.
  • Figure 4 shows a first parallel section, a cross section and a second parallel section viewed from the first side of the substrate, assuming the substrate is transparent.
  • Figure 5 is a graph showing the magnitude of each resistance measured when alternating currents of different frequencies are applied to planar coils according to the prior art and a planar coil according to an embodiment of the present specification.
  • Figure 1 is a perspective view of a planar coil according to one embodiment.
  • Figure 2 shows a first parallel section, a cross section, and a second parallel section included in an arbitrary track viewed from the first side of the substrate
  • Figure 3 illustrates a first parallel section, a cross section, and a second parallel section included in an arbitrary track viewed from the second side of the substrate. It represents a first parallel section, a cross section, and a second parallel section.
  • Figure 4 also shows a first parallel section, a cross section, and a second parallel section viewed from the first side of the substrate, assuming the substrate is transparent.
  • the planar coil 1 includes a substrate 10 and a conductor layer 20 disposed on the first side 11 and the second side 12 of the substrate 10 .
  • the conductor layer 20 may include a first conductor layer disposed on the first side 11 and a second conductor layer disposed on the second side 12 .
  • the substrate 10 may be a flat substrate having a first surface 11 and a second surface 12 .
  • Examples of the substrate 10 include a printed circuit board made of a rigid insulating material such as epoxy resin or phenol resin, or a flexible printed circuit board made of a soft insulating material such as polyimide.
  • the type of substrate 10 is not limited to this.
  • a conductor layer 20 made of a conductive material is attached, fixed, or mounted on at least one surface of the first surface 11 and the second surface 12 of the substrate 10. It can be.
  • the conductor layer 20 is a conductor wound with a predetermined number of turns based on the center point C.
  • FIG. 1 shows an embodiment in which the shape of the conductor layer 20 is circular, the conductor layer 20 may have a different shape (eg, oval or square) depending on the embodiment.
  • conductor layer 20 may include multiple conductor tracks.
  • the conductor layer 20 includes a first conductor track (T1), a second conductor track (T2), a third conductor track (T3), a fourth conductor track (T4), and a fifth conductor track (T5).
  • the number of conductor tracks included in the conductor layer 20 may be equal to the number of turns of the conductor layer 20.
  • the number of turns of the conductor layer 20 is 5, so the conductor layer 20 includes five conductor tracks T1 to T5.
  • the number of conductor tracks included in the conductor layer 20 may vary depending on the embodiment.
  • each conductor track T1 to T5 may include multiple conductor pairs.
  • any conductor track may include multiple conductor pairs (CP1-1, CP1-2. CP1-3 or CP2-1, CP2-2, CP2-3). .
  • each conductor pair may include a first conductor lane disposed on the first side 11 of the substrate 10 and a second conductor lane disposed on the second side 12 of the substrate 10.
  • the first conductor pair CP1-1 included in the first parallel section PS1 is a first conductor lane disposed on the first surface 11 of the substrate 10.
  • first conductor lanes LT1-2, LT1-3, LT1-3, LT2-1
  • second conductor lanes LB1-2, LB1-3, LB2-1, and LB2-2 disposed on the second surface 12 of the substrate 10.
  • the conductor layer 20 may include multiple parallel sections (PS) and multiple cross sections (CS). Each parallel section (PS) and each cross section (CS) may be arranged alternately. Therefore, one cross section (CS) can be placed between two parallel sections (PS).
  • Each conductor pair included in the parallel section PS may be arranged parallel to each other.
  • at least one conductor pair may be arranged to intersect with another conductor pair.
  • the conductor lane included in each conductor pair included in the two parallel sections (PS) is connected to the conductor lane included in each conductor pair included in the cross section (CS) disposed between the two parallel sections (PS). can be connected
  • a first connection terminal 21 and a second connection terminal 22 may be connected to one end of an arbitrary conductor track included in the conductor layer 20, respectively.
  • the first connection terminal 21 may be connected to one end of the first conductor track T1
  • the second connection terminal 22 may be connected to one end of the fifth conductor track T5.
  • a connection terminal (eg, a positive terminal and a negative terminal) electrically connected to the power supply device may be connected to the first connection terminal 21 and the second connection terminal 22, respectively.
  • FIG. 2 to 4 show two parallel sections included in the conductor layer 20 shown in FIG. 1, that is, a first parallel section (PS1) and a second parallel section (PS2), a first parallel section (PS1), and A cross section CS disposed between the second parallel sections PS2 is shown.
  • PS1 first parallel section
  • PS2 second parallel section
  • PS1 first parallel section
  • PS2 second parallel section
  • PS1 first parallel section
  • PS2 first parallel section
  • a cross section CS disposed between the second parallel sections PS2 is shown.
  • another cross section may be disposed on one side of the first parallel section PS1 or on one side of the second parallel section PS2.
  • Each parallel section may include multiple conductor pairs. More specifically, each parallel section may include a first outermost conductor pair, a second outermost conductor pair, and one or more intermediate conductor pairs.
  • the first parallel section (PS1) includes a first outermost conductor pair (CP1-1), a middle conductor pair (CP1-2), a second outermost conductor pair (CP1-3), and a second parallel section (CP1-1).
  • Section PS2 includes a first outermost conductor pair (CP2-1), a middle conductor pair (CP2-2), and a second outermost conductor pair (CP2-3).
  • the first outermost conductor pair, the middle conductor pair, and the second outermost conductor pair of each parallel section are the first conductor lane disposed on the first side 11 of the substrate 10 and the second outermost conductor pair of the substrate 10, respectively. It may include a second conductor lane disposed in face 12.
  • the first outermost conductor pair (CP1-1) of the first parallel section (PS1) is connected to the first conductor lane (LT1-1) disposed on the first side 11 of the substrate 10 and the substrate 10.
  • the second outermost conductor pair (CP2-3) of the second parallel section (PS2) is connected to the first conductor lane (LT1-2) disposed on the first surface 11 of the substrate 10 and the substrate 10.
  • the substrate 10 includes a second conductor lane (LB2-2) disposed on the second side 12 of the plane.
  • each parallel section includes one middle conductor pair (CP1-2, CP2-2).
  • each parallel section may include two or more intermediate conductor pairs.
  • the second outermost conductor pair of the first parallel section may be connected to the first outermost conductor pair of the second parallel section.
  • the second outermost conductor pair CP1-3 of the first parallel section PS1 is the first outermost conductor pair CP2-1 of the second parallel section PS2. is connected to
  • the first outermost conductor pair of the first parallel section may be connected to the middle conductor pair of the second parallel section.
  • the first outermost conductor pair CP1-1 of the first parallel section PS1 is connected to the middle conductor pair CP2-2 of the second parallel section PS2. .
  • the middle conductor pair of the first parallel section may be connected to the middle conductor pair of the second parallel section or the second outermost conductor pair.
  • the middle conductor pair CP1-2 of the first parallel section PS1 is connected to the second outermost conductor pair CP2-3 of the second parallel section PS2.
  • the additional intermediate conductor pair of the first parallel section (PS1) The pair may be connected to an additional middle conductor pair disposed between the middle conductor pair CP2-2 and the second outermost conductor pair CP2-3 of the second parallel section PS2.
  • the first outermost conductor pair (CP1-1) and the middle conductor pair of the first parallel section (PS1) (CP1-2) and the second outermost conductor pair (CP1-3) are the first outermost conductor pair (CP2-1), the middle conductor pair (CP2-2) and the second outermost conductor pair (CP2-1) of the second parallel section (PS2), respectively. It can be connected to any one of the outermost conductor pairs (CP2-3).
  • the second outermost conductor pair (CP1-3) of the first parallel section (PS1) is connected to the first outermost conductor pair (CP2-1) of the second parallel section (PS2)
  • the first outermost conductor pair (CP1-1) of the first parallel section (PS1) is connected to the middle conductor pair (CP2-2) of the second parallel section (PS2)
  • the middle conductor of the first parallel section (PS1) is connected to the second outermost conductor pair (CP2-3) of the second parallel section (PS2).
  • At least one via hole may be formed in each cross section.
  • at least one via hole may be formed in each cross section.
  • six via holes V1 to V6 are formed in the cross section CS.
  • each cross section may include a connecting lane connecting two via holes.
  • the cross section CS connects the first via hole V1 and the fourth via hole V4 and is disposed on the first surface 11 of the substrate 10.
  • the cross section CS connects the third via hole V3 and the fourth via hole V4 and includes a connecting lane (LBC) disposed on the second surface 12 of the substrate 10.
  • the number of via holes formed in the cross section CS or the number of connecting lanes included in the cross section CS may vary depending on the embodiment.
  • the first conductor lanes disposed on the first side 11 of the substrate 10 are connected to the second side 12 of the substrate 10 by connectors passing through via holes V1 to V6. It may be electrically connected to the conductor lanes arranged in .
  • the second conductor lane LB1-1 disposed on the first parallel section PS1 and the second surface 12 of the substrate 10 has a first via hole ( It may be electrically connected to the first connecting lane (LTC1) disposed on the first surface 11 of the substrate 10 through a connector passing through the interior of V1).
  • first connecting lane (LTC1) disposed on the first side 11 of the substrate 10 is connected to the second side 12 of the substrate 10 through a connector passing through the inside of the fourth via hole V4. It may be electrically connected to the disposed second conductor lane LB2-1.
  • the connector may be made from a conductive material (eg, metal).
  • first conductor lane disposed on the first side 11 of the substrate 10 and the second conductor lane disposed on the second side 12 of the substrate 10 are arranged to intersect each other. You can.
  • first conductor lanes LT1-1, LT1-2 and connecting lanes LTC1, LTC2 are disposed on the first side 11 of the substrate 10. is arranged to intersect with the third conductor lanes LB1-3 and the connecting lanes LBC disposed on the second surface 12 of the substrate 10.
  • each parallel section may include at least one cross region.
  • the first parallel section PS1 includes a first cross area CA1-1 and a second cross area CA1-2
  • the second parallel section PS2 includes a first cross area (CA2-1) and a second cross area (CA2-2).
  • the number of cross areas included in each parallel section may vary.
  • first conductor lane disposed on the first side 11 of the substrate 10 and the second conductor lane disposed on the second side 12 of the substrate 10 may be arranged to cross each other. there is.
  • the first surface of the substrate 10 in the first cross area CA1-1 and the second cross area CA1-2 of the first parallel section PS1 ( The first conductor lanes (LT1-1, LT1-2, LT1-3) disposed on 11) and the second conductor lanes (LB1-1, LB1-2, LB1-3) are arranged to intersect each other.
  • first conductor lane (LT2-) disposed on the first surface 11 of the substrate 10 in the first cross area (CA2-1) and the second cross area (CA2-2) of the second parallel section (PS2) 1, LT1-1, and LT1-2 and the second conductor lanes LB1-3, LB2-1, and LB2-2 disposed on the second surface 12 of the substrate 10 are arranged to intersect each other.
  • the first conductor lanes disposed on the first side 11 of the substrate 10 and the second conductor lanes disposed on the second side 12 of the substrate 10 are arranged to intersect each other.
  • the first conductor lanes disposed on the first surface 11 and the substrate 10 in the cross area e.g., CA1-1, CA1-2, CA2-1, CA2-2
  • the second conductor lanes arranged on the second side 12 are arranged to cross each other.
  • the cross section CS disposed between each parallel section the first conductor lanes disposed on the first side 11 and the second conductor lanes disposed on the second side 12 of the substrate 10 are connected to each other. arranged to intersect.
  • the first conductor lanes disposed on the first surface 11 of the substrate 10 in the cross section CS disposed between each parallel section pass through the via holes V1 to V6.
  • the conductor lanes disposed on the second surface 12 of the substrate 10 may be electrically connected to each other by a connector.
  • each conductor lane included in the conductor layer 20 is arranged to cross each other in a direction parallel to the substrate 10 or in a direction penetrating the substrate 10. Therefore, the conductor layer 20 of the planar coil 1 according to one embodiment has a structure similar to a Litz wire. As a result, the phenomenon of lowering the resistance of the conductor due to the skin effect and proximity effect of the planar coil 1 can be improved.
  • Figure 5 is a graph showing the magnitude of each resistance measured when alternating currents of different frequencies are applied to planar coils according to the prior art and a planar coil according to an embodiment of the present specification.
  • SS refers to a planar coil having a structure in which each conductor track included in the conductor layer disposed on the substrate includes only one conductor lane and is disposed on only one side of the substrate.
  • MS refers to a planar coil having a structure in which each conductor track included in a conductor layer disposed on a substrate is arranged in parallel with each other and includes a plurality of conductor lanes disposed on only one side of the substrate.
  • LZ refers to a planar coil according to the embodiment described with reference to FIGS. 1 to 4.
  • Rskin represents the size of the resistance of the conductor layer due to the skin effect that occurs when an alternating current is applied to the conductor layer of each planar coil.
  • Rproximity represents the size of the resistance of the conductor layer due to the proximity effect that occurs when an alternating current is applied to the conductor layer of each planar coil.
  • the size of resistance due to the skin effect of the planar coil (LZ) according to the embodiment described with reference to Figures 1 to 4 is the skin of the planar coil (SS) according to the prior art. It is close to the size of the resistance due to the effect or is smaller than the size of the resistance due to the skin effect of planar coils (MS) according to the prior art.
  • the size of resistance due to the proximity effect of the planar coil (LZ) according to the embodiment described with reference to FIGS. 1 to 4 is similar to that of the planar coils (SS, MS) according to the prior art. ) is smaller than the size of the resistance due to the proximity effect.
  • the size of resistance due to the proximity effect of the planar coils (SS, MS) according to the prior art tends to increase.
  • the planar coil (LZ) according to the embodiment described with reference to FIGS. 1 to 4 can guarantee higher performance compared to conventional planar coils. there is.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

Une bobine plate, selon un mode de réalisation de la présente invention, peut comprendre : un substrat ; et une couche conductrice disposée sur une première surface du substrat et une seconde surface du substrat. Dans un mode de réalisation, la couche conductrice peut comprendre de multiples pistes conductrices. Dans un mode de réalisation, chacune des pistes conductrices peut comprendre une première paire de conducteurs les plus à l'extérieur, une paire de conducteurs intermédiaires et une seconde paire de conducteurs les plus à l'extérieur. Dans un mode de réalisation, les pistes conductrices peuvent comprendre une première section parallèle et une seconde section parallèle. Dans un mode de réalisation, une seconde paire de conducteurs les plus à l'extérieur de la première section parallèle peut être connectée à une première paire de conducteurs les plus à l'extérieur de la seconde section parallèle. Dans un mode de réalisation, une première paire de conducteurs les plus à l'extérieur de la première section parallèle peut être connectée à une paire de conducteurs intermédiaires de la seconde section parallèle. Dans un mode de réalisation, une paire de conducteurs intermédiaires de la première section parallèle peut être connectée à la paire de conducteurs intermédiaires ou à une seconde paire de conducteurs les plus à l'extérieur de la seconde section parallèle.
PCT/KR2023/010901 2022-08-01 2023-07-27 Bobine plate WO2024029834A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2022-0095682 2022-08-01
KR1020220095682A KR20240017685A (ko) 2022-08-01 2022-08-01 평판형 코일

Publications (1)

Publication Number Publication Date
WO2024029834A1 true WO2024029834A1 (fr) 2024-02-08

Family

ID=89849238

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2023/010901 WO2024029834A1 (fr) 2022-08-01 2023-07-27 Bobine plate

Country Status (2)

Country Link
KR (1) KR20240017685A (fr)
WO (1) WO2024029834A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100057877A (ko) * 2007-09-28 2010-06-01 액세스 비지니스 그룹 인터내셔날 엘엘씨 인쇄 회로 기판 코일
KR20180084307A (ko) * 2017-01-16 2018-07-25 엘지이노텍 주식회사 코일 장치 및 코일 장치를 포함하는 무선 전력 송수신 장치
KR20190038972A (ko) * 2017-10-02 2019-04-10 엘지이노텍 주식회사 무선충전코일, 그 제조방법 및 이를 구비한 무선충전장치
CN110635574A (zh) * 2018-06-05 2019-12-31 日立-Lg数据存储韩国公司 用于无线地发送电力的多线圈
KR20210029563A (ko) * 2019-09-06 2021-03-16 엘지전자 주식회사 코일 장치 및 이를 구비하는 기기

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100057877A (ko) * 2007-09-28 2010-06-01 액세스 비지니스 그룹 인터내셔날 엘엘씨 인쇄 회로 기판 코일
KR20180084307A (ko) * 2017-01-16 2018-07-25 엘지이노텍 주식회사 코일 장치 및 코일 장치를 포함하는 무선 전력 송수신 장치
KR20190038972A (ko) * 2017-10-02 2019-04-10 엘지이노텍 주식회사 무선충전코일, 그 제조방법 및 이를 구비한 무선충전장치
CN110635574A (zh) * 2018-06-05 2019-12-31 日立-Lg数据存储韩国公司 用于无线地发送电力的多线圈
KR20210029563A (ko) * 2019-09-06 2021-03-16 엘지전자 주식회사 코일 장치 및 이를 구비하는 기기

Also Published As

Publication number Publication date
KR20240017685A (ko) 2024-02-08

Similar Documents

Publication Publication Date Title
WO2017030289A1 (fr) Unité d'antenne et module de transmission d'énergie sans fil la comprenant
CN1748267B (zh) 电力变压器
WO2016072779A1 (fr) Émetteur pour chargeur sans fil
WO2018106053A2 (fr) Module de chauffage pour cuisinière à induction et cuisinière à induction comportant un tel module
WO2011027984A2 (fr) Capteur pour mesurer des caractéristiques électriques
WO2011155750A2 (fr) Film vocal ayant une structure multicouche pour haut-parleur à plaque
WO2017209481A1 (fr) Feuille métallique hybride pour blindage magnétique et module d'émission d'énergie sans fil la comprenant
WO2016190708A1 (fr) Unité d'antenne d'envoi d'énergie sans fil et module d'envoi d'énergie sans fil la comprenant
WO2019156398A1 (fr) Haut-parleur plat à bobine mobile multicouche et à double piste
WO2019172595A1 (fr) Appareil de transmission d'énergie dans fil
WO2011037303A1 (fr) Structure topologique de carte de circuits imprimés pour antenne sur puce et dispositif d'antenne sur puce faisant appel à ladite structure
CN1175617C (zh) 网络耦连器
WO2024029834A1 (fr) Bobine plate
WO2021154048A1 (fr) Transformeur et dispositif d'affichage à panneau plat le comprenant
WO2014208913A1 (fr) Antenne réceptrice et appareil de réception de puissance sans fil la comportant
CN212113411U (zh) 一种多层板多路输出的平面变压器
WO2024029835A1 (fr) Bobine plane
CN111180176A (zh) 印刷电路板线圈
WO2021177801A1 (fr) Pièce magnétique utilisant une bobine d'enroulement et bobine de motif
WO2021158041A1 (fr) Module de câble et son procédé de fabrication
WO2021054707A1 (fr) Bobine mobile pour haut-parleur à panneau plat
WO2020242029A1 (fr) Dispositif de magnétisation sur lequel un fil de nanotubes de carbone sans revêtement isolant est enroulé
WO2020096344A1 (fr) Plot de charge sans fil et dispositif de charge sans fil
CN108511172A (zh) 一种消耗平板磁性装置漏感的方法及基于该方法的平板磁性装置
WO2023277555A1 (fr) Dispositif de couplage magnétique ultra-mince

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23850338

Country of ref document: EP

Kind code of ref document: A1